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drm: don't check modeset locks in panic handler
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
a4fc5ed6 112static int
ea5b213a 113intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 114{
7183dc29 115 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 116
117 switch (max_link_bw) {
118 case DP_LINK_BW_1_62:
119 case DP_LINK_BW_2_7:
120 break;
121 default:
122 max_link_bw = DP_LINK_BW_1_62;
123 break;
124 }
125 return max_link_bw;
126}
127
cd9dde44
AJ		 128/*
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
131 *
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
133 *
134 * 270000 * 1 * 8 / 10 == 216000
135 *
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
140 *
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
143 */
144
a4fc5ed6 145static int
c898261c 146intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 147{
cd9dde44 148 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 149}
150
fe27d53e
DA		 151static int
152intel_dp_max_data_rate(int max_link_clock, int max_lanes)
153{
154 return (max_link_clock * max_lanes * 8) / 10;
155}
156
a4fc5ed6
KP		 157static int
158intel_dp_mode_valid(struct drm_connector *connector,
159 struct drm_display_mode *mode)
160{
df0e9248 161 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 162 struct intel_connector *intel_connector = to_intel_connector(connector);
163 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 164 int target_clock = mode->clock;
165 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 166
dd06f90e
JN		 167 if (is_edp(intel_dp) && fixed_mode) {
168 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 169 return MODE_PANEL;
170
dd06f90e 171 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 172 return MODE_PANEL;
03afc4a2
DV		 173
174 target_clock = fixed_mode->clock;
7de56f43
ZY		 175 }
176
36008365
DV		 177 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
178 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
179
180 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
181 mode_rate = intel_dp_link_required(target_clock, 18);
182
183 if (mode_rate > max_rate)
c4867936 184 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 185
186 if (mode->clock < 10000)
187 return MODE_CLOCK_LOW;
188
0af78a2b
DV		 189 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
190 return MODE_H_ILLEGAL;
191
a4fc5ed6
KP		 192 return MODE_OK;
193}
194
195static uint32_t
196pack_aux(uint8_t *src, int src_bytes)
197{
198 int i;
199 uint32_t v = 0;
200
201 if (src_bytes > 4)
202 src_bytes = 4;
203 for (i = 0; i < src_bytes; i++)
204 v |= ((uint32_t) src[i]) << ((3-i) * 8);
205 return v;
206}
207
208static void
209unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
210{
211 int i;
212 if (dst_bytes > 4)
213 dst_bytes = 4;
214 for (i = 0; i < dst_bytes; i++)
215 dst[i] = src >> ((3-i) * 8);
216}
217
fb0f8fbf
KP		 218/* hrawclock is 1/4 the FSB frequency */
219static int
220intel_hrawclk(struct drm_device *dev)
221{
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 uint32_t clkcfg;
224
9473c8f4
VP		 225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev))
227 return 200;
228
fb0f8fbf
KP		 229 clkcfg = I915_READ(CLKCFG);
230 switch (clkcfg & CLKCFG_FSB_MASK) {
231 case CLKCFG_FSB_400:
232 return 100;
233 case CLKCFG_FSB_533:
234 return 133;
235 case CLKCFG_FSB_667:
236 return 166;
237 case CLKCFG_FSB_800:
238 return 200;
239 case CLKCFG_FSB_1067:
240 return 266;
241 case CLKCFG_FSB_1333:
242 return 333;
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600:
245 case CLKCFG_FSB_1600_ALT:
246 return 400;
247 default:
248 return 133;
249 }
250}
251
ebf33b18
KP		 252static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
253{
30add22d 254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 255 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 256 u32 pp_stat_reg;
ebf33b18 257
453c5420
JB		 258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 260}
261
262static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
263{
30add22d 264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 265 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 266 u32 pp_ctrl_reg;
ebf33b18 267
453c5420
JB		 268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 270}
271
9b984dae
KP		 272static void
273intel_dp_check_edp(struct intel_dp *intel_dp)
274{
30add22d 275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 276 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 277 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 278
9b984dae
KP		 279 if (!is_edp(intel_dp))
280 return;
453c5420
JB		 281
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
284
ebf33b18 285 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 288 I915_READ(pp_stat_reg),
289 I915_READ(pp_ctrl_reg));
9b984dae
KP		 290 }
291}
292
9ee32fea
DV		 293static uint32_t
294intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_device *dev = intel_dig_port->base.base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 299 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 300 uint32_t status;
301 bool done;
302
ef04f00d 303#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 304 if (has_aux_irq)
b90f5176
PZ		 305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
306 msecs_to_jiffies(10));
9ee32fea
DV		 307 else
308 done = wait_for_atomic(C, 10) == 0;
309 if (!done)
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
311 has_aux_irq);
312#undef C
313
314 return status;
315}
316
a4fc5ed6 317static int
ea5b213a 318intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 319 uint8_t *send, int send_bytes,
320 uint8_t *recv, int recv_size)
321{
174edf1f
PZ		 322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 324 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 325 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 326 uint32_t ch_data = ch_ctl + 4;
9ee32fea 327 int i, ret, recv_bytes;
a4fc5ed6 328 uint32_t status;
fb0f8fbf 329 uint32_t aux_clock_divider;
6b4e0a93 330 int try, precharge;
9ee32fea
DV		 331 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
332
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
335 * deep sleep states.
336 */
337 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 338
9b984dae 339 intel_dp_check_edp(intel_dp);
a4fc5ed6 340 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 343 *
344 * Note that PCH attached eDP panels should use a 125MHz input
345 * clock divider.
a4fc5ed6 346 */
1c95822a 347 if (is_cpu_edp(intel_dp)) {
affa9354 348 if (HAS_DDI(dev))
b8fc2f6a
PZ		 349 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
350 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 351 aux_clock_divider = 100;
352 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 353 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 354 else
355 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 356 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
357 /* Workaround for non-ULT HSW */
358 aux_clock_divider = 74;
359 } else if (HAS_PCH_SPLIT(dev)) {
6b3ec1c9 360 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 361 } else {
5eb08b69 362 aux_clock_divider = intel_hrawclk(dev) / 2;
2c55c336 363 }
5eb08b69 364
6b4e0a93
DV		 365 if (IS_GEN6(dev))
366 precharge = 3;
367 else
368 precharge = 5;
369
11bee43e
JB		 370 /* Try to wait for any previous AUX channel activity */
371 for (try = 0; try < 3; try++) {
ef04f00d 372 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 373 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
374 break;
375 msleep(1);
376 }
377
378 if (try == 3) {
379 WARN(1, "dp_aux_ch not started status 0x%08x\n",
380 I915_READ(ch_ctl));
9ee32fea
DV		 381 ret = -EBUSY;
382 goto out;
4f7f7b7e
CW		 383 }
384
fb0f8fbf
KP		 385 /* Must try at least 3 times according to DP spec */
386 for (try = 0; try < 5; try++) {
387 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 388 for (i = 0; i < send_bytes; i += 4)
389 I915_WRITE(ch_data + i,
390 pack_aux(send + i, send_bytes - i));
0206e353 391
fb0f8fbf 392 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 393 I915_WRITE(ch_ctl,
394 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 395 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 396 DP_AUX_CH_CTL_TIME_OUT_400us |
397 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
398 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
399 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
400 DP_AUX_CH_CTL_DONE |
401 DP_AUX_CH_CTL_TIME_OUT_ERROR |
402 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 403
404 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 405
fb0f8fbf 406 /* Clear done status and any errors */
4f7f7b7e
CW		 407 I915_WRITE(ch_ctl,
408 status |
409 DP_AUX_CH_CTL_DONE |
410 DP_AUX_CH_CTL_TIME_OUT_ERROR |
411 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 412
413 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
414 DP_AUX_CH_CTL_RECEIVE_ERROR))
415 continue;
4f7f7b7e 416 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 417 break;
418 }
419
a4fc5ed6 420 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 421 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 422 ret = -EBUSY;
423 goto out;
a4fc5ed6
KP		 424 }
425
426 /* Check for timeout or receive error.
427 * Timeouts occur when the sink is not connected
428 */
a5b3da54 429 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 430 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 431 ret = -EIO;
432 goto out;
a5b3da54 433 }
1ae8c0a5
KP		 434
435 /* Timeouts occur when the device isn't connected, so they're
436 * "normal" -- don't fill the kernel log with these */
a5b3da54 437 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 438 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 439 ret = -ETIMEDOUT;
440 goto out;
a4fc5ed6
KP		 441 }
442
443 /* Unload any bytes sent back from the other side */
444 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
445 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 446 if (recv_bytes > recv_size)
447 recv_bytes = recv_size;
0206e353 448
4f7f7b7e
CW		 449 for (i = 0; i < recv_bytes; i += 4)
450 unpack_aux(I915_READ(ch_data + i),
451 recv + i, recv_bytes - i);
a4fc5ed6 452
9ee32fea
DV		 453 ret = recv_bytes;
454out:
455 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
456
457 return ret;
a4fc5ed6
KP		 458}
459
460/* Write data to the aux channel in native mode */
461static int
ea5b213a 462intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 463 uint16_t address, uint8_t *send, int send_bytes)
464{
465 int ret;
466 uint8_t msg[20];
467 int msg_bytes;
468 uint8_t ack;
469
9b984dae 470 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 471 if (send_bytes > 16)
472 return -1;
473 msg[0] = AUX_NATIVE_WRITE << 4;
474 msg[1] = address >> 8;
eebc863e 475 msg[2] = address & 0xff;
a4fc5ed6
KP		 476 msg[3] = send_bytes - 1;
477 memcpy(&msg[4], send, send_bytes);
478 msg_bytes = send_bytes + 4;
479 for (;;) {
ea5b213a 480 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 481 if (ret < 0)
482 return ret;
483 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
484 break;
485 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
486 udelay(100);
487 else
a5b3da54 488 return -EIO;
a4fc5ed6
KP		 489 }
490 return send_bytes;
491}
492
493/* Write a single byte to the aux channel in native mode */
494static int
ea5b213a 495intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 496 uint16_t address, uint8_t byte)
497{
ea5b213a 498 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 499}
500
501/* read bytes from a native aux channel */
502static int
ea5b213a 503intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 504 uint16_t address, uint8_t *recv, int recv_bytes)
505{
506 uint8_t msg[4];
507 int msg_bytes;
508 uint8_t reply[20];
509 int reply_bytes;
510 uint8_t ack;
511 int ret;
512
9b984dae 513 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 514 msg[0] = AUX_NATIVE_READ << 4;
515 msg[1] = address >> 8;
516 msg[2] = address & 0xff;
517 msg[3] = recv_bytes - 1;
518
519 msg_bytes = 4;
520 reply_bytes = recv_bytes + 1;
521
522 for (;;) {
ea5b213a 523 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 524 reply, reply_bytes);
a5b3da54
KP		 525 if (ret == 0)
526 return -EPROTO;
527 if (ret < 0)
a4fc5ed6
KP		 528 return ret;
529 ack = reply[0];
530 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
531 memcpy(recv, reply + 1, ret - 1);
532 return ret - 1;
533 }
534 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
535 udelay(100);
536 else
a5b3da54 537 return -EIO;
a4fc5ed6
KP		 538 }
539}
540
541static int
ab2c0672
DA		 542intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
543 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 544{
ab2c0672 545 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 546 struct intel_dp *intel_dp = container_of(adapter,
547 struct intel_dp,
548 adapter);
ab2c0672
DA		 549 uint16_t address = algo_data->address;
550 uint8_t msg[5];
551 uint8_t reply[2];
8316f337 552 unsigned retry;
ab2c0672
DA		 553 int msg_bytes;
554 int reply_bytes;
555 int ret;
556
9b984dae 557 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 558 /* Set up the command byte */
559 if (mode & MODE_I2C_READ)
560 msg[0] = AUX_I2C_READ << 4;
561 else
562 msg[0] = AUX_I2C_WRITE << 4;
563
564 if (!(mode & MODE_I2C_STOP))
565 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 566
ab2c0672
DA		 567 msg[1] = address >> 8;
568 msg[2] = address;
569
570 switch (mode) {
571 case MODE_I2C_WRITE:
572 msg[3] = 0;
573 msg[4] = write_byte;
574 msg_bytes = 5;
575 reply_bytes = 1;
576 break;
577 case MODE_I2C_READ:
578 msg[3] = 0;
579 msg_bytes = 4;
580 reply_bytes = 2;
581 break;
582 default:
583 msg_bytes = 3;
584 reply_bytes = 1;
585 break;
586 }
587
8316f337
DF		 588 for (retry = 0; retry < 5; retry++) {
589 ret = intel_dp_aux_ch(intel_dp,
590 msg, msg_bytes,
591 reply, reply_bytes);
ab2c0672 592 if (ret < 0) {
3ff99164 593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 594 return ret;
595 }
8316f337
DF		 596
597 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
598 case AUX_NATIVE_REPLY_ACK:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
601 */
602 break;
603 case AUX_NATIVE_REPLY_NACK:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
605 return -EREMOTEIO;
606 case AUX_NATIVE_REPLY_DEFER:
607 udelay(100);
608 continue;
609 default:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
611 reply[0]);
612 return -EREMOTEIO;
613 }
614
ab2c0672
DA		 615 switch (reply[0] & AUX_I2C_REPLY_MASK) {
616 case AUX_I2C_REPLY_ACK:
617 if (mode == MODE_I2C_READ) {
618 *read_byte = reply[1];
619 }
620 return reply_bytes - 1;
621 case AUX_I2C_REPLY_NACK:
8316f337 622 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 623 return -EREMOTEIO;
624 case AUX_I2C_REPLY_DEFER:
8316f337 625 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 626 udelay(100);
627 break;
628 default:
8316f337 629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 630 return -EREMOTEIO;
631 }
632 }
8316f337
DF		 633
634 DRM_ERROR("too many retries, giving up\n");
635 return -EREMOTEIO;
a4fc5ed6
KP		 636}
637
638static int
ea5b213a 639intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 640 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 641{
0b5c541b
KP		 642 int ret;
643
d54e9d28 644 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 645 intel_dp->algo.running = false;
646 intel_dp->algo.address = 0;
647 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
648
0206e353 649 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 650 intel_dp->adapter.owner = THIS_MODULE;
651 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 652 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 653 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
654 intel_dp->adapter.algo_data = &intel_dp->algo;
655 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
656
0b5c541b
KP		 657 ironlake_edp_panel_vdd_on(intel_dp);
658 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 659 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 660 return ret;
a4fc5ed6
KP		 661}
662
00c09d70 663bool
5bfe2ac0
DV		 664intel_dp_compute_config(struct intel_encoder *encoder,
665 struct intel_crtc_config *pipe_config)
a4fc5ed6 666{
5bfe2ac0 667 struct drm_device *dev = encoder->base.dev;
36008365 668 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0
DV		 669 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
670 struct drm_display_mode *mode = &pipe_config->requested_mode;
671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
dd06f90e 672 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 673 int lane_count, clock;
397fe157 674 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 675 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 676 int bpp, mode_rate;
a4fc5ed6 677 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 678 int target_clock, link_avail, link_clock;
a4fc5ed6 679
5bfe2ac0
DV		 680 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
681 pipe_config->has_pch_encoder = true;
682
03afc4a2
DV		 683 pipe_config->has_dp_encoder = true;
684
dd06f90e
JN		 685 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
686 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
687 adjusted_mode);
53b41837
YN		 688 intel_pch_panel_fitting(dev,
689 intel_connector->panel.fitting_mode,
1d8e1c75 690 mode, adjusted_mode);
0d3a1bee 691 }
36008365
DV		 692 /* We need to take the panel's fixed mode into account. */
693 target_clock = adjusted_mode->clock;
0d3a1bee 694
cb1793ce 695 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 696 return false;
697
083f9560
DV		 698 DRM_DEBUG_KMS("DP link computation with max lane count %i "
699 "max bw %02x pixel clock %iKHz\n",
71244653 700 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 701
36008365
DV		 702 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
703 * bpc in between. */
03afc4a2 704 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
36008365
DV		 705 for (; bpp >= 6*3; bpp -= 2*3) {
706 mode_rate = intel_dp_link_required(target_clock, bpp);
707
708 for (clock = 0; clock <= max_clock; clock++) {
709 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
710 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
711 link_avail = intel_dp_max_data_rate(link_clock,
712 lane_count);
713
714 if (mode_rate <= link_avail) {
715 goto found;
716 }
717 }
718 }
719 }
c4867936 720
36008365 721 return false;
3685a8f3 722
36008365 723found:
55bc60db
VS		 724 if (intel_dp->color_range_auto) {
725 /*
726 * See:
727 * CEA-861-E - 5.1 Default Encoding Parameters
728 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
729 */
18316c8c 730 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 731 intel_dp->color_range = DP_COLOR_RANGE_16_235;
732 else
733 intel_dp->color_range = 0;
734 }
735
3685a8f3 736 if (intel_dp->color_range)
50f3b016 737 pipe_config->limited_color_range = true;
3685a8f3 738
36008365
DV		 739 intel_dp->link_bw = bws[clock];
740 intel_dp->lane_count = lane_count;
741 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
df92b1e6 742 pipe_config->pixel_target_clock = target_clock;
fe27d53e 743
36008365
DV		 744 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
745 intel_dp->link_bw, intel_dp->lane_count,
746 adjusted_mode->clock, bpp);
747 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
748 mode_rate, link_avail);
749
03afc4a2
DV		 750 intel_link_compute_m_n(bpp, lane_count,
751 target_clock, adjusted_mode->clock,
752 &pipe_config->dp_m_n);
a4fc5ed6 753
57c21963
DV		 754 /*
755 * XXX: We have a strange regression where using the vbt edp bpp value
756 * for the link bw computation results in black screens, the panel only
757 * works when we do the computation at the usual 24bpp (but still
758 * requires us to use 18bpp). Until that's fully debugged, stay
759 * bug-for-bug compatible with the old code.
760 */
761 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
762 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
763 bpp, dev_priv->edp.bpp);
764 bpp = min_t(int, bpp, dev_priv->edp.bpp);
765 }
766 pipe_config->pipe_bpp = bpp;
767
03afc4a2 768 return true;
a4fc5ed6
KP		 769}
770
247d89f6
PZ		 771void intel_dp_init_link_config(struct intel_dp *intel_dp)
772{
773 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
774 intel_dp->link_configuration[0] = intel_dp->link_bw;
775 intel_dp->link_configuration[1] = intel_dp->lane_count;
776 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
777 /*
778 * Check for DPCD version > 1.1 and enhanced framing support
779 */
780 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
781 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
782 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
783 }
784}
785
ea9b6006
DV		 786static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
787{
788 struct drm_device *dev = crtc->dev;
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 dpa_ctl;
791
792 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
793 dpa_ctl = I915_READ(DP_A);
794 dpa_ctl &= ~DP_PLL_FREQ_MASK;
795
796 if (clock < 200000) {
1ce17038
DV		 797 /* For a long time we've carried around a ILK-DevA w/a for the
798 * 160MHz clock. If we're really unlucky, it's still required.
799 */
800 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 801 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 802 } else {
803 dpa_ctl |= DP_PLL_FREQ_270MHZ;
804 }
1ce17038 805
ea9b6006
DV		 806 I915_WRITE(DP_A, dpa_ctl);
807
808 POSTING_READ(DP_A);
809 udelay(500);
810}
811
a4fc5ed6
KP		 812static void
813intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
814 struct drm_display_mode *adjusted_mode)
815{
e3421a18 816 struct drm_device *dev = encoder->dev;
417e822d 817 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 818 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 819 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
821
417e822d 822 /*
1a2eb460 823 * There are four kinds of DP registers:
417e822d
KP		 824 *
825 * IBX PCH
1a2eb460
KP		 826 * SNB CPU
827 * IVB CPU
417e822d
KP		 828 * CPT PCH
829 *
830 * IBX PCH and CPU are the same for almost everything,
831 * except that the CPU DP PLL is configured in this
832 * register
833 *
834 * CPT PCH is quite different, having many bits moved
835 * to the TRANS_DP_CTL register instead. That
836 * configuration happens (oddly) in ironlake_pch_enable
837 */
9c9e7927 838
417e822d
KP		 839 /* Preserve the BIOS-computed detected bit. This is
840 * supposed to be read-only.
841 */
842 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 843
417e822d 844 /* Handle DP bits in common between all three register formats */
417e822d 845 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 846
ea5b213a 847 switch (intel_dp->lane_count) {
a4fc5ed6 848 case 1:
ea5b213a 849 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 850 break;
851 case 2:
ea5b213a 852 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 853 break;
854 case 4:
ea5b213a 855 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 856 break;
857 }
e0dac65e
WF		 858 if (intel_dp->has_audio) {
859 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
860 pipe_name(intel_crtc->pipe));
ea5b213a 861 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 862 intel_write_eld(encoder, adjusted_mode);
863 }
247d89f6
PZ		 864
865 intel_dp_init_link_config(intel_dp);
a4fc5ed6 866
417e822d 867 /* Split out the IBX/CPU vs CPT settings */
32f9d658 868
19c03924 869 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 870 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
871 intel_dp->DP |= DP_SYNC_HS_HIGH;
872 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
873 intel_dp->DP |= DP_SYNC_VS_HIGH;
874 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
875
876 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
877 intel_dp->DP |= DP_ENHANCED_FRAMING;
878
879 intel_dp->DP |= intel_crtc->pipe << 29;
880
881 /* don't miss out required setting for eDP */
1a2eb460
KP		 882 if (adjusted_mode->clock < 200000)
883 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
884 else
885 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
886 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
b2634017 887 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 888 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 889
890 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
891 intel_dp->DP |= DP_SYNC_HS_HIGH;
892 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
893 intel_dp->DP |= DP_SYNC_VS_HIGH;
894 intel_dp->DP |= DP_LINK_TRAIN_OFF;
895
896 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
897 intel_dp->DP |= DP_ENHANCED_FRAMING;
898
899 if (intel_crtc->pipe == 1)
900 intel_dp->DP |= DP_PIPEB_SELECT;
901
b2634017 902 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
417e822d 903 /* don't miss out required setting for eDP */
417e822d
KP		 904 if (adjusted_mode->clock < 200000)
905 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
906 else
907 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
908 }
909 } else {
910 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 911 }
ea9b6006 912
5d66d5b6 913 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ea9b6006 914 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 915}
916
99ea7127
KP		 917#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
918#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
919
920#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
921#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
922
923#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
924#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
925
926static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
927 u32 mask,
928 u32 value)
bd943159 929{
30add22d 930 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 931 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 932 u32 pp_stat_reg, pp_ctrl_reg;
933
934 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
935 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 936
99ea7127 937 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 938 mask, value,
939 I915_READ(pp_stat_reg),
940 I915_READ(pp_ctrl_reg));
32ce697c 941
453c5420 942 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 943 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 944 I915_READ(pp_stat_reg),
945 I915_READ(pp_ctrl_reg));
32ce697c 946 }
99ea7127 947}
32ce697c 948
99ea7127
KP		 949static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
950{
951 DRM_DEBUG_KMS("Wait for panel power on\n");
952 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 953}
954
99ea7127
KP		 955static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
956{
957 DRM_DEBUG_KMS("Wait for panel power off time\n");
958 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
959}
960
961static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
962{
963 DRM_DEBUG_KMS("Wait for panel power cycle\n");
964 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
965}
966
967
832dd3c1
KP		 968/* Read the current pp_control value, unlocking the register if it
969 * is locked
970 */
971
453c5420 972static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 973{
453c5420
JB		 974 struct drm_device *dev = intel_dp_to_dev(intel_dp);
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 u32 control;
977 u32 pp_ctrl_reg;
978
979 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
980 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 981
982 control &= ~PANEL_UNLOCK_MASK;
983 control |= PANEL_UNLOCK_REGS;
984 return control;
bd943159
KP		 985}
986
82a4d9c0 987void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 988{
30add22d 989 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 990 struct drm_i915_private *dev_priv = dev->dev_private;
991 u32 pp;
453c5420 992 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 993
97af61f5
KP		 994 if (!is_edp(intel_dp))
995 return;
f01eca2e 996 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 997
bd943159
KP		 998 WARN(intel_dp->want_panel_vdd,
999 "eDP VDD already requested on\n");
1000
1001 intel_dp->want_panel_vdd = true;
99ea7127 1002
bd943159
KP		 1003 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1004 DRM_DEBUG_KMS("eDP VDD already on\n");
1005 return;
1006 }
1007
99ea7127
KP		 1008 if (!ironlake_edp_have_panel_power(intel_dp))
1009 ironlake_wait_panel_power_cycle(intel_dp);
1010
453c5420 1011 pp = ironlake_get_pp_control(intel_dp);
5d613501 1012 pp |= EDP_FORCE_VDD;
ebf33b18 1013
453c5420
JB		 1014 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1015 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1016
1017 I915_WRITE(pp_ctrl_reg, pp);
1018 POSTING_READ(pp_ctrl_reg);
1019 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1020 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1021 /*
1022 * If the panel wasn't on, delay before accessing aux channel
1023 */
1024 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1025 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1026 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1027 }
5d613501
JB		 1028}
1029
bd943159 1030static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1031{
30add22d 1032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1033 struct drm_i915_private *dev_priv = dev->dev_private;
1034 u32 pp;
453c5420 1035 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1036
a0e99e68
DV		 1037 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1038
bd943159 1039 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1040 pp = ironlake_get_pp_control(intel_dp);
bd943159 1041 pp &= ~EDP_FORCE_VDD;
bd943159 1042
453c5420
JB		 1043 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1044 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1045
1046 I915_WRITE(pp_ctrl_reg, pp);
1047 POSTING_READ(pp_ctrl_reg);
99ea7127 1048
453c5420
JB		 1049 /* Make sure sequencer is idle before allowing subsequent activity */
1050 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1051 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1052 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1053 }
1054}
5d613501 1055
bd943159
KP		 1056static void ironlake_panel_vdd_work(struct work_struct *__work)
1057{
1058 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1059 struct intel_dp, panel_vdd_work);
30add22d 1060 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1061
627f7675 1062 mutex_lock(&dev->mode_config.mutex);
bd943159 1063 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1064 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1065}
1066
82a4d9c0 1067void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1068{
97af61f5
KP		 1069 if (!is_edp(intel_dp))
1070 return;
5d613501 1071
bd943159
KP		 1072 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1073 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1074
bd943159
KP		 1075 intel_dp->want_panel_vdd = false;
1076
1077 if (sync) {
1078 ironlake_panel_vdd_off_sync(intel_dp);
1079 } else {
1080 /*
1081 * Queue the timer to fire a long
1082 * time from now (relative to the power down delay)
1083 * to keep the panel power up across a sequence of operations
1084 */
1085 schedule_delayed_work(&intel_dp->panel_vdd_work,
1086 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1087 }
5d613501
JB		 1088}
1089
82a4d9c0 1090void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1091{
30add22d 1092 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1093 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1094 u32 pp;
453c5420 1095 u32 pp_ctrl_reg;
9934c132 1096
97af61f5 1097 if (!is_edp(intel_dp))
bd943159 1098 return;
99ea7127
KP		 1099
1100 DRM_DEBUG_KMS("Turn eDP power on\n");
1101
1102 if (ironlake_edp_have_panel_power(intel_dp)) {
1103 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1104 return;
99ea7127 1105 }
9934c132 1106
99ea7127 1107 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1108
453c5420 1109 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1110 if (IS_GEN5(dev)) {
1111 /* ILK workaround: disable reset around power sequence */
1112 pp &= ~PANEL_POWER_RESET;
1113 I915_WRITE(PCH_PP_CONTROL, pp);
1114 POSTING_READ(PCH_PP_CONTROL);
1115 }
37c6c9b0 1116
1c0ae80a 1117 pp |= POWER_TARGET_ON;
99ea7127
KP		 1118 if (!IS_GEN5(dev))
1119 pp |= PANEL_POWER_RESET;
1120
453c5420
JB		 1121 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1122
1123 I915_WRITE(pp_ctrl_reg, pp);
1124 POSTING_READ(pp_ctrl_reg);
9934c132 1125
99ea7127 1126 ironlake_wait_panel_on(intel_dp);
9934c132 1127
05ce1a49
KP		 1128 if (IS_GEN5(dev)) {
1129 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1130 I915_WRITE(PCH_PP_CONTROL, pp);
1131 POSTING_READ(PCH_PP_CONTROL);
1132 }
9934c132
JB		 1133}
1134
82a4d9c0 1135void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1136{
30add22d 1137 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1138 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1139 u32 pp;
453c5420 1140 u32 pp_ctrl_reg;
9934c132 1141
97af61f5
KP		 1142 if (!is_edp(intel_dp))
1143 return;
37c6c9b0 1144
99ea7127 1145 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1146
6cb49835 1147 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1148
453c5420 1149 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1150 /* We need to switch off panel power _and_ force vdd, for otherwise some
1151 * panels get very unhappy and cease to work. */
1152 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1153
1154 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1155
1156 I915_WRITE(pp_ctrl_reg, pp);
1157 POSTING_READ(pp_ctrl_reg);
9934c132 1158
35a38556
DV		 1159 intel_dp->want_panel_vdd = false;
1160
99ea7127 1161 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1162}
1163
d6c50ff8 1164void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1165{
da63a9f2
PZ		 1166 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1167 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1168 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1169 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1170 u32 pp;
453c5420 1171 u32 pp_ctrl_reg;
32f9d658 1172
f01eca2e
KP		 1173 if (!is_edp(intel_dp))
1174 return;
1175
28c97730 1176 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1177 /*
1178 * If we enable the backlight right away following a panel power
1179 * on, we may see slight flicker as the panel syncs with the eDP
1180 * link. So delay a bit to make sure the image is solid before
1181 * allowing it to appear.
1182 */
f01eca2e 1183 msleep(intel_dp->backlight_on_delay);
453c5420 1184 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1185 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1186
1187 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1188
1189 I915_WRITE(pp_ctrl_reg, pp);
1190 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1191
1192 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1193}
1194
d6c50ff8 1195void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1196{
30add22d 1197 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 u32 pp;
453c5420 1200 u32 pp_ctrl_reg;
32f9d658 1201
f01eca2e
KP		 1202 if (!is_edp(intel_dp))
1203 return;
1204
035aa3de
DV		 1205 intel_panel_disable_backlight(dev);
1206
28c97730 1207 DRM_DEBUG_KMS("\n");
453c5420 1208 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1209 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1210
1211 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1212
1213 I915_WRITE(pp_ctrl_reg, pp);
1214 POSTING_READ(pp_ctrl_reg);
f01eca2e 1215 msleep(intel_dp->backlight_off_delay);
32f9d658 1216}
a4fc5ed6 1217
2bd2ad64 1218static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1219{
da63a9f2
PZ		 1220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1221 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1222 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 u32 dpa_ctl;
1225
2bd2ad64
DV		 1226 assert_pipe_disabled(dev_priv,
1227 to_intel_crtc(crtc)->pipe);
1228
d240f20f
JB		 1229 DRM_DEBUG_KMS("\n");
1230 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1231 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1232 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233
1234 /* We don't adjust intel_dp->DP while tearing down the link, to
1235 * facilitate link retraining (e.g. after hotplug). Hence clear all
1236 * enable bits here to ensure that we don't enable too much. */
1237 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1238 intel_dp->DP |= DP_PLL_ENABLE;
1239 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1240 POSTING_READ(DP_A);
1241 udelay(200);
d240f20f
JB		 1242}
1243
2bd2ad64 1244static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1245{
da63a9f2
PZ		 1246 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1247 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1248 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 u32 dpa_ctl;
1251
2bd2ad64
DV		 1252 assert_pipe_disabled(dev_priv,
1253 to_intel_crtc(crtc)->pipe);
1254
d240f20f 1255 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1256 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1257 "dp pll off, should be on\n");
1258 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1259
1260 /* We can't rely on the value tracked for the DP register in
1261 * intel_dp->DP because link_down must not change that (otherwise link
1262 * re-training will fail. */
298b0b39 1263 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1264 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1265 POSTING_READ(DP_A);
d240f20f
JB		 1266 udelay(200);
1267}
1268
c7ad3810 1269/* If the sink supports it, try to set the power state appropriately */
c19b0669 1270void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1271{
1272 int ret, i;
1273
1274 /* Should have a valid DPCD by this point */
1275 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1276 return;
1277
1278 if (mode != DRM_MODE_DPMS_ON) {
1279 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1280 DP_SET_POWER_D3);
1281 if (ret != 1)
1282 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1283 } else {
1284 /*
1285 * When turning on, we need to retry for 1ms to give the sink
1286 * time to wake up.
1287 */
1288 for (i = 0; i < 3; i++) {
1289 ret = intel_dp_aux_native_write_1(intel_dp,
1290 DP_SET_POWER,
1291 DP_SET_POWER_D0);
1292 if (ret == 1)
1293 break;
1294 msleep(1);
1295 }
1296 }
1297}
1298
19d8fe15
DV		 1299static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1300 enum pipe *pipe)
d240f20f 1301{
19d8fe15
DV		 1302 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1303 struct drm_device *dev = encoder->base.dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 u32 tmp = I915_READ(intel_dp->output_reg);
1306
1307 if (!(tmp & DP_PORT_EN))
1308 return false;
1309
5d66d5b6 1310 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15
DV		 1311 *pipe = PORT_TO_PIPE_CPT(tmp);
1312 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1313 *pipe = PORT_TO_PIPE(tmp);
1314 } else {
1315 u32 trans_sel;
1316 u32 trans_dp;
1317 int i;
1318
1319 switch (intel_dp->output_reg) {
1320 case PCH_DP_B:
1321 trans_sel = TRANS_DP_PORT_SEL_B;
1322 break;
1323 case PCH_DP_C:
1324 trans_sel = TRANS_DP_PORT_SEL_C;
1325 break;
1326 case PCH_DP_D:
1327 trans_sel = TRANS_DP_PORT_SEL_D;
1328 break;
1329 default:
1330 return true;
1331 }
1332
1333 for_each_pipe(i) {
1334 trans_dp = I915_READ(TRANS_DP_CTL(i));
1335 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1336 *pipe = i;
1337 return true;
1338 }
1339 }
19d8fe15 1340
4a0833ec
DV		 1341 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1342 intel_dp->output_reg);
1343 }
d240f20f 1344
2af8898b 1345 return true;
19d8fe15 1346}
d240f20f 1347
e8cb4558 1348static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1349{
e8cb4558 1350 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1351
1352 /* Make sure the panel is off before trying to change the mode. But also
1353 * ensure that we have vdd while we switch off the panel. */
1354 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1355 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1356 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1357 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1358
1359 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1360 if (!is_cpu_edp(intel_dp))
1361 intel_dp_link_down(intel_dp);
d240f20f
JB		 1362}
1363
2bd2ad64 1364static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1365{
2bd2ad64 1366 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1367 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1368
3739850b
DV		 1369 if (is_cpu_edp(intel_dp)) {
1370 intel_dp_link_down(intel_dp);
b2634017
JB		 1371 if (!IS_VALLEYVIEW(dev))
1372 ironlake_edp_pll_off(intel_dp);
3739850b 1373 }
2bd2ad64
DV		 1374}
1375
e8cb4558 1376static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1377{
e8cb4558
DV		 1378 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1379 struct drm_device *dev = encoder->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1382
0c33d8d7
DV		 1383 if (WARN_ON(dp_reg & DP_PORT_EN))
1384 return;
5d613501 1385
97af61f5 1386 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1387 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1388 intel_dp_start_link_train(intel_dp);
97af61f5 1389 ironlake_edp_panel_on(intel_dp);
bd943159 1390 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1391 intel_dp_complete_link_train(intel_dp);
f01eca2e 1392 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1393}
1394
2bd2ad64 1395static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1396{
2bd2ad64 1397 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1398 struct drm_device *dev = encoder->base.dev;
a4fc5ed6 1399
b2634017 1400 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
2bd2ad64 1401 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1402}
1403
1404/*
df0c237d
JB		 1405 * Native read with retry for link status and receiver capability reads for
1406 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1407 */
1408static bool
df0c237d
JB		 1409intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1410 uint8_t *recv, int recv_bytes)
a4fc5ed6 1411{
61da5fab
JB		 1412 int ret, i;
1413
df0c237d
JB		 1414 /*
1415 * Sinks are *supposed* to come up within 1ms from an off state,
1416 * but we're also supposed to retry 3 times per the spec.
1417 */
61da5fab 1418 for (i = 0; i < 3; i++) {
df0c237d
JB		 1419 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1420 recv_bytes);
1421 if (ret == recv_bytes)
61da5fab
JB		 1422 return true;
1423 msleep(1);
1424 }
a4fc5ed6 1425
61da5fab 1426 return false;
a4fc5ed6
KP		 1427}
1428
1429/*
1430 * Fetch AUX CH registers 0x202 - 0x207 which contain
1431 * link status information
1432 */
1433static bool
93f62dad 1434intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1435{
df0c237d
JB		 1436 return intel_dp_aux_native_read_retry(intel_dp,
1437 DP_LANE0_1_STATUS,
93f62dad 1438 link_status,
df0c237d 1439 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1440}
1441
a4fc5ed6
KP		 1442#if 0
1443static char *voltage_names[] = {
1444 "0.4V", "0.6V", "0.8V", "1.2V"
1445};
1446static char *pre_emph_names[] = {
1447 "0dB", "3.5dB", "6dB", "9.5dB"
1448};
1449static char *link_train_names[] = {
1450 "pattern 1", "pattern 2", "idle", "off"
1451};
1452#endif
1453
1454/*
1455 * These are source-specific values; current Intel hardware supports
1456 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1457 */
a4fc5ed6
KP		 1458
1459static uint8_t
1a2eb460 1460intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1461{
30add22d 1462 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1463
1464 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1465 return DP_TRAIN_VOLTAGE_SWING_800;
1466 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1467 return DP_TRAIN_VOLTAGE_SWING_1200;
1468 else
1469 return DP_TRAIN_VOLTAGE_SWING_800;
1470}
1471
1472static uint8_t
1473intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1474{
30add22d 1475 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1476
22b8bf17 1477 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1478 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1479 case DP_TRAIN_VOLTAGE_SWING_400:
1480 return DP_TRAIN_PRE_EMPHASIS_9_5;
1481 case DP_TRAIN_VOLTAGE_SWING_600:
1482 return DP_TRAIN_PRE_EMPHASIS_6;
1483 case DP_TRAIN_VOLTAGE_SWING_800:
1484 return DP_TRAIN_PRE_EMPHASIS_3_5;
1485 case DP_TRAIN_VOLTAGE_SWING_1200:
1486 default:
1487 return DP_TRAIN_PRE_EMPHASIS_0;
1488 }
1489 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1490 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1491 case DP_TRAIN_VOLTAGE_SWING_400:
1492 return DP_TRAIN_PRE_EMPHASIS_6;
1493 case DP_TRAIN_VOLTAGE_SWING_600:
1494 case DP_TRAIN_VOLTAGE_SWING_800:
1495 return DP_TRAIN_PRE_EMPHASIS_3_5;
1496 default:
1497 return DP_TRAIN_PRE_EMPHASIS_0;
1498 }
1499 } else {
1500 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1501 case DP_TRAIN_VOLTAGE_SWING_400:
1502 return DP_TRAIN_PRE_EMPHASIS_6;
1503 case DP_TRAIN_VOLTAGE_SWING_600:
1504 return DP_TRAIN_PRE_EMPHASIS_6;
1505 case DP_TRAIN_VOLTAGE_SWING_800:
1506 return DP_TRAIN_PRE_EMPHASIS_3_5;
1507 case DP_TRAIN_VOLTAGE_SWING_1200:
1508 default:
1509 return DP_TRAIN_PRE_EMPHASIS_0;
1510 }
a4fc5ed6
KP		 1511 }
1512}
1513
1514static void
93f62dad 1515intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1516{
1517 uint8_t v = 0;
1518 uint8_t p = 0;
1519 int lane;
1a2eb460
KP		 1520 uint8_t voltage_max;
1521 uint8_t preemph_max;
a4fc5ed6 1522
33a34e4e 1523 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1524 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1525 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1526
1527 if (this_v > v)
1528 v = this_v;
1529 if (this_p > p)
1530 p = this_p;
1531 }
1532
1a2eb460 1533 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1534 if (v >= voltage_max)
1535 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1536
1a2eb460
KP		 1537 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1538 if (p >= preemph_max)
1539 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1540
1541 for (lane = 0; lane < 4; lane++)
33a34e4e 1542 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1543}
1544
1545static uint32_t
f0a3424e 1546intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1547{
3cf2efb1 1548 uint32_t signal_levels = 0;
a4fc5ed6 1549
3cf2efb1 1550 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1551 case DP_TRAIN_VOLTAGE_SWING_400:
1552 default:
1553 signal_levels |= DP_VOLTAGE_0_4;
1554 break;
1555 case DP_TRAIN_VOLTAGE_SWING_600:
1556 signal_levels |= DP_VOLTAGE_0_6;
1557 break;
1558 case DP_TRAIN_VOLTAGE_SWING_800:
1559 signal_levels |= DP_VOLTAGE_0_8;
1560 break;
1561 case DP_TRAIN_VOLTAGE_SWING_1200:
1562 signal_levels |= DP_VOLTAGE_1_2;
1563 break;
1564 }
3cf2efb1 1565 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1566 case DP_TRAIN_PRE_EMPHASIS_0:
1567 default:
1568 signal_levels |= DP_PRE_EMPHASIS_0;
1569 break;
1570 case DP_TRAIN_PRE_EMPHASIS_3_5:
1571 signal_levels |= DP_PRE_EMPHASIS_3_5;
1572 break;
1573 case DP_TRAIN_PRE_EMPHASIS_6:
1574 signal_levels |= DP_PRE_EMPHASIS_6;
1575 break;
1576 case DP_TRAIN_PRE_EMPHASIS_9_5:
1577 signal_levels |= DP_PRE_EMPHASIS_9_5;
1578 break;
1579 }
1580 return signal_levels;
1581}
1582
e3421a18
ZW		 1583/* Gen6's DP voltage swing and pre-emphasis control */
1584static uint32_t
1585intel_gen6_edp_signal_levels(uint8_t train_set)
1586{
3c5a62b5
YL		 1587 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1588 DP_TRAIN_PRE_EMPHASIS_MASK);
1589 switch (signal_levels) {
e3421a18 1590 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1591 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1592 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1593 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1594 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1595 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1596 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1597 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1598 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1599 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1600 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1601 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1602 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1603 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1604 default:
3c5a62b5
YL		 1605 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1606 "0x%x\n", signal_levels);
1607 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1608 }
1609}
1610
1a2eb460
KP		 1611/* Gen7's DP voltage swing and pre-emphasis control */
1612static uint32_t
1613intel_gen7_edp_signal_levels(uint8_t train_set)
1614{
1615 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1616 DP_TRAIN_PRE_EMPHASIS_MASK);
1617 switch (signal_levels) {
1618 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1619 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1620 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1621 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1622 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1623 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1624
1625 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1626 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1627 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1628 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1629
1630 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1631 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1632 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1633 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1634
1635 default:
1636 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1637 "0x%x\n", signal_levels);
1638 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1639 }
1640}
1641
d6c0d722
PZ		 1642/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1643static uint32_t
f0a3424e 1644intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1645{
d6c0d722
PZ		 1646 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1647 DP_TRAIN_PRE_EMPHASIS_MASK);
1648 switch (signal_levels) {
1649 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1650 return DDI_BUF_EMP_400MV_0DB_HSW;
1651 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1652 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1653 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1654 return DDI_BUF_EMP_400MV_6DB_HSW;
1655 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1656 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1657
d6c0d722
PZ		 1658 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1659 return DDI_BUF_EMP_600MV_0DB_HSW;
1660 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1661 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1662 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1663 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1664
d6c0d722
PZ		 1665 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1666 return DDI_BUF_EMP_800MV_0DB_HSW;
1667 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1668 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1669 default:
1670 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1671 "0x%x\n", signal_levels);
1672 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1673 }
a4fc5ed6
KP		 1674}
1675
f0a3424e
PZ		 1676/* Properly updates "DP" with the correct signal levels. */
1677static void
1678intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1679{
1680 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1681 struct drm_device *dev = intel_dig_port->base.base.dev;
1682 uint32_t signal_levels, mask;
1683 uint8_t train_set = intel_dp->train_set[0];
1684
22b8bf17 1685 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1686 signal_levels = intel_hsw_signal_levels(train_set);
1687 mask = DDI_BUF_EMP_MASK;
1688 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1689 signal_levels = intel_gen7_edp_signal_levels(train_set);
1690 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1691 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1692 signal_levels = intel_gen6_edp_signal_levels(train_set);
1693 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1694 } else {
1695 signal_levels = intel_gen4_signal_levels(train_set);
1696 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1697 }
1698
1699 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1700
1701 *DP = (*DP & ~mask) | signal_levels;
1702}
1703
a4fc5ed6 1704static bool
ea5b213a 1705intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1706 uint32_t dp_reg_value,
58e10eb9 1707 uint8_t dp_train_pat)
a4fc5ed6 1708{
174edf1f
PZ		 1709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1710 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1711 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1712 enum port port = intel_dig_port->port;
a4fc5ed6 1713 int ret;
d6c0d722 1714 uint32_t temp;
a4fc5ed6 1715
22b8bf17 1716 if (HAS_DDI(dev)) {
174edf1f 1717 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1718
1719 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1720 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1721 else
1722 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1723
1724 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1725 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1726 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1727
10aa17c8
PZ		 1728 if (port != PORT_A) {
1729 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1730 I915_WRITE(DP_TP_CTL(port), temp);
1731
1732 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1733 DP_TP_STATUS_IDLE_DONE), 1))
1734 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1735
1736 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1737 }
d6c0d722 1738
d6c0d722
PZ		 1739 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1740
1741 break;
1742 case DP_TRAINING_PATTERN_1:
1743 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1744 break;
1745 case DP_TRAINING_PATTERN_2:
1746 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1747 break;
1748 case DP_TRAINING_PATTERN_3:
1749 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1750 break;
1751 }
174edf1f 1752 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1753
1754 } else if (HAS_PCH_CPT(dev) &&
1755 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1756 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1757
1758 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1759 case DP_TRAINING_PATTERN_DISABLE:
1760 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1761 break;
1762 case DP_TRAINING_PATTERN_1:
1763 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1764 break;
1765 case DP_TRAINING_PATTERN_2:
1766 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1767 break;
1768 case DP_TRAINING_PATTERN_3:
1769 DRM_ERROR("DP training pattern 3 not supported\n");
1770 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1771 break;
1772 }
1773
1774 } else {
1775 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1776
1777 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1778 case DP_TRAINING_PATTERN_DISABLE:
1779 dp_reg_value |= DP_LINK_TRAIN_OFF;
1780 break;
1781 case DP_TRAINING_PATTERN_1:
1782 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1783 break;
1784 case DP_TRAINING_PATTERN_2:
1785 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1786 break;
1787 case DP_TRAINING_PATTERN_3:
1788 DRM_ERROR("DP training pattern 3 not supported\n");
1789 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1790 break;
1791 }
1792 }
1793
ea5b213a
CW		 1794 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1795 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1796
ea5b213a 1797 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1798 DP_TRAINING_PATTERN_SET,
1799 dp_train_pat);
1800
47ea7542
PZ		 1801 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1802 DP_TRAINING_PATTERN_DISABLE) {
1803 ret = intel_dp_aux_native_write(intel_dp,
1804 DP_TRAINING_LANE0_SET,
1805 intel_dp->train_set,
1806 intel_dp->lane_count);
1807 if (ret != intel_dp->lane_count)
1808 return false;
1809 }
a4fc5ed6
KP		 1810
1811 return true;
1812}
1813
33a34e4e 1814/* Enable corresponding port and start training pattern 1 */
c19b0669 1815void
33a34e4e 1816intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1817{
da63a9f2 1818 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1819 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1820 int i;
1821 uint8_t voltage;
1822 bool clock_recovery = false;
cdb0e95b 1823 int voltage_tries, loop_tries;
ea5b213a 1824 uint32_t DP = intel_dp->DP;
a4fc5ed6 1825
affa9354 1826 if (HAS_DDI(dev))
c19b0669
PZ		 1827 intel_ddi_prepare_link_retrain(encoder);
1828
3cf2efb1
CW		 1829 /* Write the link configuration data */
1830 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1831 intel_dp->link_configuration,
1832 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1833
1834 DP |= DP_PORT_EN;
1a2eb460 1835
33a34e4e 1836 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1837 voltage = 0xff;
cdb0e95b
KP		 1838 voltage_tries = 0;
1839 loop_tries = 0;
a4fc5ed6
KP		 1840 clock_recovery = false;
1841 for (;;) {
33a34e4e 1842 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1843 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 1844
1845 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 1846
a7c9655f 1847 /* Set training pattern 1 */
47ea7542 1848 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1849 DP_TRAINING_PATTERN_1 |
1850 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1851 break;
a4fc5ed6 1852
a7c9655f 1853 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1854 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1855 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1856 break;
93f62dad 1857 }
a4fc5ed6 1858
01916270 1859 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1860 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1861 clock_recovery = true;
1862 break;
1863 }
1864
1865 /* Check to see if we've tried the max voltage */
1866 for (i = 0; i < intel_dp->lane_count; i++)
1867 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1868 break;
3b4f819d 1869 if (i == intel_dp->lane_count) {
b06fbda3
DV		 1870 ++loop_tries;
1871 if (loop_tries == 5) {
cdb0e95b
KP		 1872 DRM_DEBUG_KMS("too many full retries, give up\n");
1873 break;
1874 }
1875 memset(intel_dp->train_set, 0, 4);
1876 voltage_tries = 0;
1877 continue;
1878 }
a4fc5ed6 1879
3cf2efb1 1880 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1881 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1882 ++voltage_tries;
b06fbda3
DV		 1883 if (voltage_tries == 5) {
1884 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1885 break;
1886 }
1887 } else
1888 voltage_tries = 0;
1889 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1890
3cf2efb1 1891 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1892 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1893 }
1894
33a34e4e
JB		 1895 intel_dp->DP = DP;
1896}
1897
c19b0669 1898void
33a34e4e
JB		 1899intel_dp_complete_link_train(struct intel_dp *intel_dp)
1900{
33a34e4e 1901 bool channel_eq = false;
37f80975 1902 int tries, cr_tries;
33a34e4e
JB		 1903 uint32_t DP = intel_dp->DP;
1904
a4fc5ed6
KP		 1905 /* channel equalization */
1906 tries = 0;
37f80975 1907 cr_tries = 0;
a4fc5ed6
KP		 1908 channel_eq = false;
1909 for (;;) {
93f62dad 1910 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1911
37f80975
JB		 1912 if (cr_tries > 5) {
1913 DRM_ERROR("failed to train DP, aborting\n");
1914 intel_dp_link_down(intel_dp);
1915 break;
1916 }
1917
f0a3424e 1918 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 1919
a4fc5ed6 1920 /* channel eq pattern */
47ea7542 1921 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1922 DP_TRAINING_PATTERN_2 |
1923 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1924 break;
1925
a7c9655f 1926 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1927 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1928 break;
a4fc5ed6 1929
37f80975 1930 /* Make sure clock is still ok */
01916270 1931 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1932 intel_dp_start_link_train(intel_dp);
1933 cr_tries++;
1934 continue;
1935 }
1936
1ffdff13 1937 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1938 channel_eq = true;
1939 break;
1940 }
a4fc5ed6 1941
37f80975
JB		 1942 /* Try 5 times, then try clock recovery if that fails */
1943 if (tries > 5) {
1944 intel_dp_link_down(intel_dp);
1945 intel_dp_start_link_train(intel_dp);
1946 tries = 0;
1947 cr_tries++;
1948 continue;
1949 }
a4fc5ed6 1950
3cf2efb1 1951 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1952 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1953 ++tries;
869184a6 1954 }
3cf2efb1 1955
d6c0d722
PZ		 1956 if (channel_eq)
1957 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1958
47ea7542 1959 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1960}
1961
1962static void
ea5b213a 1963intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1964{
da63a9f2
PZ		 1965 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1966 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1967 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 1968 struct intel_crtc *intel_crtc =
1969 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 1970 uint32_t DP = intel_dp->DP;
a4fc5ed6 1971
c19b0669
PZ		 1972 /*
1973 * DDI code has a strict mode set sequence and we should try to respect
1974 * it, otherwise we might hang the machine in many different ways. So we
1975 * really should be disabling the port only on a complete crtc_disable
1976 * sequence. This function is just called under two conditions on DDI
1977 * code:
1978 * - Link train failed while doing crtc_enable, and on this case we
1979 * really should respect the mode set sequence and wait for a
1980 * crtc_disable.
1981 * - Someone turned the monitor off and intel_dp_check_link_status
1982 * called us. We don't need to disable the whole port on this case, so
1983 * when someone turns the monitor on again,
1984 * intel_ddi_prepare_link_retrain will take care of redoing the link
1985 * train.
1986 */
affa9354 1987 if (HAS_DDI(dev))
c19b0669
PZ		 1988 return;
1989
0c33d8d7 1990 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 1991 return;
1992
28c97730 1993 DRM_DEBUG_KMS("\n");
32f9d658 1994
1a2eb460 1995 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1996 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1997 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1998 } else {
1999 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2000 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2001 }
fe255d00 2002 POSTING_READ(intel_dp->output_reg);
5eb08b69 2003
ab527efc
DV		 2004 /* We don't really know why we're doing this */
2005 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2006
493a7081 2007 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2008 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2009 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2010
5bddd17f
EA		 2011 /* Hardware workaround: leaving our transcoder select
2012 * set to transcoder B while it's off will prevent the
2013 * corresponding HDMI output on transcoder A.
2014 *
2015 * Combine this with another hardware workaround:
2016 * transcoder select bit can only be cleared while the
2017 * port is enabled.
2018 */
2019 DP &= ~DP_PIPEB_SELECT;
2020 I915_WRITE(intel_dp->output_reg, DP);
2021
2022 /* Changes to enable or select take place the vblank
2023 * after being written.
2024 */
ff50afe9
DV		 2025 if (WARN_ON(crtc == NULL)) {
2026 /* We should never try to disable a port without a crtc
2027 * attached. For paranoia keep the code around for a
2028 * bit. */
31acbcc4
CW		 2029 POSTING_READ(intel_dp->output_reg);
2030 msleep(50);
2031 } else
ab527efc 2032 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2033 }
2034
832afda6 2035 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2036 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2037 POSTING_READ(intel_dp->output_reg);
f01eca2e 2038 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2039}
2040
26d61aad
KP		 2041static bool
2042intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2043{
577c7a50
DL		 2044 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2045
92fd8fd1 2046 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2047 sizeof(intel_dp->dpcd)) == 0)
2048 return false; /* aux transfer failed */
92fd8fd1 2049
577c7a50
DL		 2050 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2051 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2052 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2053
edb39244
AJ		 2054 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2055 return false; /* DPCD not present */
2056
2057 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2058 DP_DWN_STRM_PORT_PRESENT))
2059 return true; /* native DP sink */
2060
2061 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2062 return true; /* no per-port downstream info */
2063
2064 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2065 intel_dp->downstream_ports,
2066 DP_MAX_DOWNSTREAM_PORTS) == 0)
2067 return false; /* downstream port status fetch failed */
2068
2069 return true;
92fd8fd1
KP		 2070}
2071
0d198328
AJ		 2072static void
2073intel_dp_probe_oui(struct intel_dp *intel_dp)
2074{
2075 u8 buf[3];
2076
2077 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2078 return;
2079
351cfc34
DV		 2080 ironlake_edp_panel_vdd_on(intel_dp);
2081
0d198328
AJ		 2082 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2083 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2084 buf[0], buf[1], buf[2]);
2085
2086 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2087 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2088 buf[0], buf[1], buf[2]);
351cfc34
DV		 2089
2090 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2091}
2092
a60f0e38
JB		 2093static bool
2094intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2095{
2096 int ret;
2097
2098 ret = intel_dp_aux_native_read_retry(intel_dp,
2099 DP_DEVICE_SERVICE_IRQ_VECTOR,
2100 sink_irq_vector, 1);
2101 if (!ret)
2102 return false;
2103
2104 return true;
2105}
2106
2107static void
2108intel_dp_handle_test_request(struct intel_dp *intel_dp)
2109{
2110 /* NAK by default */
9324cf7f 2111 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2112}
2113
a4fc5ed6
KP		 2114/*
2115 * According to DP spec
2116 * 5.1.2:
2117 * 1. Read DPCD
2118 * 2. Configure link according to Receiver Capabilities
2119 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2120 * 4. Check link status on receipt of hot-plug interrupt
2121 */
2122
00c09d70 2123void
ea5b213a 2124intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2125{
da63a9f2 2126 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2127 u8 sink_irq_vector;
93f62dad 2128 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2129
da63a9f2 2130 if (!intel_encoder->connectors_active)
d2b996ac 2131 return;
59cd09e1 2132
da63a9f2 2133 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2134 return;
2135
92fd8fd1 2136 /* Try to read receiver status if the link appears to be up */
93f62dad 2137 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2138 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2139 return;
2140 }
2141
92fd8fd1 2142 /* Now read the DPCD to see if it's actually running */
26d61aad 2143 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2144 intel_dp_link_down(intel_dp);
2145 return;
2146 }
2147
a60f0e38
JB		 2148 /* Try to read the source of the interrupt */
2149 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2150 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2151 /* Clear interrupt source */
2152 intel_dp_aux_native_write_1(intel_dp,
2153 DP_DEVICE_SERVICE_IRQ_VECTOR,
2154 sink_irq_vector);
2155
2156 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2157 intel_dp_handle_test_request(intel_dp);
2158 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2159 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2160 }
2161
1ffdff13 2162 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2163 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2164 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2165 intel_dp_start_link_train(intel_dp);
2166 intel_dp_complete_link_train(intel_dp);
2167 }
a4fc5ed6 2168}
a4fc5ed6 2169
caf9ab24 2170/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2171static enum drm_connector_status
26d61aad 2172intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2173{
caf9ab24
AJ		 2174 uint8_t *dpcd = intel_dp->dpcd;
2175 bool hpd;
2176 uint8_t type;
2177
2178 if (!intel_dp_get_dpcd(intel_dp))
2179 return connector_status_disconnected;
2180
2181 /* if there's no downstream port, we're done */
2182 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2183 return connector_status_connected;
caf9ab24
AJ		 2184
2185 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2186 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2187 if (hpd) {
23235177 2188 uint8_t reg;
caf9ab24 2189 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2190 &reg, 1))
caf9ab24 2191 return connector_status_unknown;
23235177
AJ		 2192 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2193 : connector_status_disconnected;
caf9ab24
AJ		 2194 }
2195
2196 /* If no HPD, poke DDC gently */
2197 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2198 return connector_status_connected;
caf9ab24
AJ		 2199
2200 /* Well we tried, say unknown for unreliable port types */
2201 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2202 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2203 return connector_status_unknown;
2204
2205 /* Anything else is out of spec, warn and ignore */
2206 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2207 return connector_status_disconnected;
71ba9000
AJ		 2208}
2209
5eb08b69 2210static enum drm_connector_status
a9756bb5 2211ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2212{
30add22d 2213 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2216 enum drm_connector_status status;
2217
fe16d949
CW		 2218 /* Can't disconnect eDP, but you can close the lid... */
2219 if (is_edp(intel_dp)) {
30add22d 2220 status = intel_panel_detect(dev);
fe16d949
CW		 2221 if (status == connector_status_unknown)
2222 status = connector_status_connected;
2223 return status;
2224 }
01cb9ea6 2225
1b469639
DL		 2226 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2227 return connector_status_disconnected;
2228
26d61aad 2229 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2230}
2231
a4fc5ed6 2232static enum drm_connector_status
a9756bb5 2233g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2234{
30add22d 2235 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2236 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2237 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2238 uint32_t bit;
5eb08b69 2239
35aad75f
JB		 2240 /* Can't disconnect eDP, but you can close the lid... */
2241 if (is_edp(intel_dp)) {
2242 enum drm_connector_status status;
2243
2244 status = intel_panel_detect(dev);
2245 if (status == connector_status_unknown)
2246 status = connector_status_connected;
2247 return status;
2248 }
2249
34f2be46
VS		 2250 switch (intel_dig_port->port) {
2251 case PORT_B:
26739f12 2252 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2253 break;
34f2be46 2254 case PORT_C:
26739f12 2255 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2256 break;
34f2be46 2257 case PORT_D:
26739f12 2258 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2259 break;
2260 default:
2261 return connector_status_unknown;
2262 }
2263
10f76a38 2264 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2265 return connector_status_disconnected;
2266
26d61aad 2267 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2268}
2269
8c241fef
KP		 2270static struct edid *
2271intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2272{
9cd300e0 2273 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2274
9cd300e0
JN		 2275 /* use cached edid if we have one */
2276 if (intel_connector->edid) {
2277 struct edid *edid;
2278 int size;
2279
2280 /* invalid edid */
2281 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2282 return NULL;
2283
9cd300e0 2284 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2285 edid = kmalloc(size, GFP_KERNEL);
2286 if (!edid)
2287 return NULL;
2288
9cd300e0 2289 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2290 return edid;
2291 }
8c241fef 2292
9cd300e0 2293 return drm_get_edid(connector, adapter);
8c241fef
KP		 2294}
2295
2296static int
2297intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2298{
9cd300e0 2299 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2300
9cd300e0
JN		 2301 /* use cached edid if we have one */
2302 if (intel_connector->edid) {
2303 /* invalid edid */
2304 if (IS_ERR(intel_connector->edid))
2305 return 0;
2306
2307 return intel_connector_update_modes(connector,
2308 intel_connector->edid);
d6f24d0f
JB		 2309 }
2310
9cd300e0 2311 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2312}
2313
a9756bb5
ZW		 2314static enum drm_connector_status
2315intel_dp_detect(struct drm_connector *connector, bool force)
2316{
2317 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2318 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2319 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2320 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2321 enum drm_connector_status status;
2322 struct edid *edid = NULL;
2323
2324 intel_dp->has_audio = false;
2325
2326 if (HAS_PCH_SPLIT(dev))
2327 status = ironlake_dp_detect(intel_dp);
2328 else
2329 status = g4x_dp_detect(intel_dp);
1b9be9d0 2330
a9756bb5
ZW		 2331 if (status != connector_status_connected)
2332 return status;
2333
0d198328
AJ		 2334 intel_dp_probe_oui(intel_dp);
2335
c3e5f67b
DV		 2336 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2337 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2338 } else {
8c241fef 2339 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2340 if (edid) {
2341 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2342 kfree(edid);
2343 }
a9756bb5
ZW		 2344 }
2345
d63885da
PZ		 2346 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2347 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2348 return connector_status_connected;
a4fc5ed6
KP		 2349}
2350
2351static int intel_dp_get_modes(struct drm_connector *connector)
2352{
df0e9248 2353 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2354 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2355 struct drm_device *dev = connector->dev;
32f9d658 2356 int ret;
a4fc5ed6
KP		 2357
2358 /* We should parse the EDID data and find out if it has an audio sink
2359 */
2360
8c241fef 2361 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2362 if (ret)
32f9d658
ZW		 2363 return ret;
2364
f8779fda 2365 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2366 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2367 struct drm_display_mode *mode;
dd06f90e
JN		 2368 mode = drm_mode_duplicate(dev,
2369 intel_connector->panel.fixed_mode);
f8779fda 2370 if (mode) {
32f9d658
ZW		 2371 drm_mode_probed_add(connector, mode);
2372 return 1;
2373 }
2374 }
2375 return 0;
a4fc5ed6
KP		 2376}
2377
1aad7ac0
CW		 2378static bool
2379intel_dp_detect_audio(struct drm_connector *connector)
2380{
2381 struct intel_dp *intel_dp = intel_attached_dp(connector);
2382 struct edid *edid;
2383 bool has_audio = false;
2384
8c241fef 2385 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2386 if (edid) {
2387 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2388 kfree(edid);
2389 }
2390
2391 return has_audio;
2392}
2393
f684960e
CW		 2394static int
2395intel_dp_set_property(struct drm_connector *connector,
2396 struct drm_property *property,
2397 uint64_t val)
2398{
e953fd7b 2399 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2400 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2401 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2402 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2403 int ret;
2404
662595df 2405 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2406 if (ret)
2407 return ret;
2408
3f43c48d 2409 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2410 int i = val;
2411 bool has_audio;
2412
2413 if (i == intel_dp->force_audio)
f684960e
CW		 2414 return 0;
2415
1aad7ac0 2416 intel_dp->force_audio = i;
f684960e 2417
c3e5f67b 2418 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2419 has_audio = intel_dp_detect_audio(connector);
2420 else
c3e5f67b 2421 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2422
2423 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2424 return 0;
2425
1aad7ac0 2426 intel_dp->has_audio = has_audio;
f684960e
CW		 2427 goto done;
2428 }
2429
e953fd7b 2430 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2431 bool old_auto = intel_dp->color_range_auto;
2432 uint32_t old_range = intel_dp->color_range;
2433
55bc60db
VS		 2434 switch (val) {
2435 case INTEL_BROADCAST_RGB_AUTO:
2436 intel_dp->color_range_auto = true;
2437 break;
2438 case INTEL_BROADCAST_RGB_FULL:
2439 intel_dp->color_range_auto = false;
2440 intel_dp->color_range = 0;
2441 break;
2442 case INTEL_BROADCAST_RGB_LIMITED:
2443 intel_dp->color_range_auto = false;
2444 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2445 break;
2446 default:
2447 return -EINVAL;
2448 }
ae4edb80
DV		 2449
2450 if (old_auto == intel_dp->color_range_auto &&
2451 old_range == intel_dp->color_range)
2452 return 0;
2453
e953fd7b
CW		 2454 goto done;
2455 }
2456
53b41837
YN		 2457 if (is_edp(intel_dp) &&
2458 property == connector->dev->mode_config.scaling_mode_property) {
2459 if (val == DRM_MODE_SCALE_NONE) {
2460 DRM_DEBUG_KMS("no scaling not supported\n");
2461 return -EINVAL;
2462 }
2463
2464 if (intel_connector->panel.fitting_mode == val) {
2465 /* the eDP scaling property is not changed */
2466 return 0;
2467 }
2468 intel_connector->panel.fitting_mode = val;
2469
2470 goto done;
2471 }
2472
f684960e
CW		 2473 return -EINVAL;
2474
2475done:
c0c36b94
CW		 2476 if (intel_encoder->base.crtc)
2477 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2478
2479 return 0;
2480}
2481
a4fc5ed6 2482static void
0206e353 2483intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2484{
be3cd5e3 2485 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2486 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2487
9cd300e0
JN		 2488 if (!IS_ERR_OR_NULL(intel_connector->edid))
2489 kfree(intel_connector->edid);
2490
dc652f90 2491 if (is_edp(intel_dp))
1d508706 2492 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2493
a4fc5ed6
KP		 2494 drm_sysfs_connector_remove(connector);
2495 drm_connector_cleanup(connector);
55f78c43 2496 kfree(connector);
a4fc5ed6
KP		 2497}
2498
00c09d70 2499void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2500{
da63a9f2
PZ		 2501 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2502 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2503
2504 i2c_del_adapter(&intel_dp->adapter);
2505 drm_encoder_cleanup(encoder);
bd943159
KP		 2506 if (is_edp(intel_dp)) {
2507 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2508 ironlake_panel_vdd_off_sync(intel_dp);
2509 }
da63a9f2 2510 kfree(intel_dig_port);
24d05927
DV		 2511}
2512
a4fc5ed6 2513static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2514 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2515};
2516
2517static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2518 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2519 .detect = intel_dp_detect,
2520 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2521 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2522 .destroy = intel_dp_destroy,
2523};
2524
2525static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2526 .get_modes = intel_dp_get_modes,
2527 .mode_valid = intel_dp_mode_valid,
df0e9248 2528 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2529};
2530
a4fc5ed6 2531static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2532 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2533};
2534
995b6762 2535static void
21d40d37 2536intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2537{
fa90ecef 2538 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2539
885a5014 2540 intel_dp_check_link_status(intel_dp);
c8110e52 2541}
6207937d 2542
e3421a18
ZW		 2543/* Return which DP Port should be selected for Transcoder DP control */
2544int
0206e353 2545intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2546{
2547 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2548 struct intel_encoder *intel_encoder;
2549 struct intel_dp *intel_dp;
e3421a18 2550
fa90ecef
PZ		 2551 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2552 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2553
fa90ecef
PZ		 2554 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2555 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2556 return intel_dp->output_reg;
e3421a18 2557 }
ea5b213a 2558
e3421a18
ZW		 2559 return -1;
2560}
2561
36e83a18 2562/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2563bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2564{
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2566 struct child_device_config *p_child;
2567 int i;
2568
2569 if (!dev_priv->child_dev_num)
2570 return false;
2571
2572 for (i = 0; i < dev_priv->child_dev_num; i++) {
2573 p_child = dev_priv->child_dev + i;
2574
2575 if (p_child->dvo_port == PORT_IDPD &&
2576 p_child->device_type == DEVICE_TYPE_eDP)
2577 return true;
2578 }
2579 return false;
2580}
2581
f684960e
CW		 2582static void
2583intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2584{
53b41837
YN		 2585 struct intel_connector *intel_connector = to_intel_connector(connector);
2586
3f43c48d 2587 intel_attach_force_audio_property(connector);
e953fd7b 2588 intel_attach_broadcast_rgb_property(connector);
55bc60db 2589 intel_dp->color_range_auto = true;
53b41837
YN		 2590
2591 if (is_edp(intel_dp)) {
2592 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2593 drm_object_attach_property(
2594 &connector->base,
53b41837 2595 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2596 DRM_MODE_SCALE_ASPECT);
2597 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2598 }
f684960e
CW		 2599}
2600
67a54566
DV		 2601static void
2602intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2603 struct intel_dp *intel_dp,
2604 struct edp_power_seq *out)
67a54566
DV		 2605{
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 struct edp_power_seq cur, vbt, spec, final;
2608 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 2609 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2610
2611 if (HAS_PCH_SPLIT(dev)) {
2612 pp_control_reg = PCH_PP_CONTROL;
2613 pp_on_reg = PCH_PP_ON_DELAYS;
2614 pp_off_reg = PCH_PP_OFF_DELAYS;
2615 pp_div_reg = PCH_PP_DIVISOR;
2616 } else {
2617 pp_control_reg = PIPEA_PP_CONTROL;
2618 pp_on_reg = PIPEA_PP_ON_DELAYS;
2619 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2620 pp_div_reg = PIPEA_PP_DIVISOR;
2621 }
67a54566
DV		 2622
2623 /* Workaround: Need to write PP_CONTROL with the unlock key as
2624 * the very first thing. */
453c5420
JB		 2625 pp = ironlake_get_pp_control(intel_dp);
2626 I915_WRITE(pp_control_reg, pp);
67a54566 2627
453c5420
JB		 2628 pp_on = I915_READ(pp_on_reg);
2629 pp_off = I915_READ(pp_off_reg);
2630 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 2631
2632 /* Pull timing values out of registers */
2633 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2634 PANEL_POWER_UP_DELAY_SHIFT;
2635
2636 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2637 PANEL_LIGHT_ON_DELAY_SHIFT;
2638
2639 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2640 PANEL_LIGHT_OFF_DELAY_SHIFT;
2641
2642 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2643 PANEL_POWER_DOWN_DELAY_SHIFT;
2644
2645 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2646 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2647
2648 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2649 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2650
2651 vbt = dev_priv->edp.pps;
2652
2653 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2654 * our hw here, which are all in 100usec. */
2655 spec.t1_t3 = 210 * 10;
2656 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2657 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2658 spec.t10 = 500 * 10;
2659 /* This one is special and actually in units of 100ms, but zero
2660 * based in the hw (so we need to add 100 ms). But the sw vbt
2661 * table multiplies it with 1000 to make it in units of 100usec,
2662 * too. */
2663 spec.t11_t12 = (510 + 100) * 10;
2664
2665 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2666 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2667
2668 /* Use the max of the register settings and vbt. If both are
2669 * unset, fall back to the spec limits. */
2670#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2671 spec.field : \
2672 max(cur.field, vbt.field))
2673 assign_final(t1_t3);
2674 assign_final(t8);
2675 assign_final(t9);
2676 assign_final(t10);
2677 assign_final(t11_t12);
2678#undef assign_final
2679
2680#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2681 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2682 intel_dp->backlight_on_delay = get_delay(t8);
2683 intel_dp->backlight_off_delay = get_delay(t9);
2684 intel_dp->panel_power_down_delay = get_delay(t10);
2685 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2686#undef get_delay
2687
f30d26e4
JN		 2688 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2689 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2690 intel_dp->panel_power_cycle_delay);
2691
2692 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2693 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2694
2695 if (out)
2696 *out = final;
2697}
2698
2699static void
2700intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2701 struct intel_dp *intel_dp,
2702 struct edp_power_seq *seq)
2703{
2704 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 2705 u32 pp_on, pp_off, pp_div, port_sel = 0;
2706 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2707 int pp_on_reg, pp_off_reg, pp_div_reg;
2708
2709 if (HAS_PCH_SPLIT(dev)) {
2710 pp_on_reg = PCH_PP_ON_DELAYS;
2711 pp_off_reg = PCH_PP_OFF_DELAYS;
2712 pp_div_reg = PCH_PP_DIVISOR;
2713 } else {
2714 pp_on_reg = PIPEA_PP_ON_DELAYS;
2715 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2716 pp_div_reg = PIPEA_PP_DIVISOR;
2717 }
2718
2719 if (IS_VALLEYVIEW(dev))
2720 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
f30d26e4 2721
67a54566 2722 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2723 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2724 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2725 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2726 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2727 /* Compute the divisor for the pp clock, simply match the Bspec
2728 * formula. */
453c5420 2729 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2730 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2731 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2732
2733 /* Haswell doesn't have any port selection bits for the panel
2734 * power sequencer any more. */
2735 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2736 if (is_cpu_edp(intel_dp))
453c5420 2737 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2738 else
453c5420 2739 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 2740 }
2741
453c5420
JB		 2742 pp_on |= port_sel;
2743
2744 I915_WRITE(pp_on_reg, pp_on);
2745 I915_WRITE(pp_off_reg, pp_off);
2746 I915_WRITE(pp_div_reg, pp_div);
67a54566 2747
67a54566 2748 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 2749 I915_READ(pp_on_reg),
2750 I915_READ(pp_off_reg),
2751 I915_READ(pp_div_reg));
f684960e
CW		 2752}
2753
a4fc5ed6 2754void
f0fec3f2
PZ		 2755intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2756 struct intel_connector *intel_connector)
a4fc5ed6 2757{
f0fec3f2
PZ		 2758 struct drm_connector *connector = &intel_connector->base;
2759 struct intel_dp *intel_dp = &intel_dig_port->dp;
2760 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2761 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2762 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2763 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2764 struct edp_power_seq power_seq = { 0 };
174edf1f 2765 enum port port = intel_dig_port->port;
5eb08b69 2766 const char *name = NULL;
b329530c 2767 int type;
a4fc5ed6 2768
0767935e
DV		 2769 /* Preserve the current hw state. */
2770 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2771 intel_dp->attached_connector = intel_connector;
3d3dc149 2772
f0fec3f2 2773 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2774 if (intel_dpd_is_edp(dev))
ea5b213a 2775 intel_dp->is_pch_edp = true;
b329530c 2776
19c03924
GB		 2777 /*
2778 * FIXME : We need to initialize built-in panels before external panels.
2779 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2780 */
f0fec3f2 2781 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2782 type = DRM_MODE_CONNECTOR_eDP;
2783 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2784 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2785 type = DRM_MODE_CONNECTOR_eDP;
2786 intel_encoder->type = INTEL_OUTPUT_EDP;
2787 } else {
00c09d70
PZ		 2788 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2789 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2790 * rewrite it.
2791 */
b329530c 2792 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2793 }
2794
b329530c 2795 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2796 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2797
a4fc5ed6
KP		 2798 connector->interlace_allowed = true;
2799 connector->doublescan_allowed = 0;
2800
f0fec3f2
PZ		 2801 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2802 ironlake_panel_vdd_work);
a4fc5ed6 2803
df0e9248 2804 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2805 drm_sysfs_connector_add(connector);
2806
affa9354 2807 if (HAS_DDI(dev))
bcbc889b
PZ		 2808 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2809 else
2810 intel_connector->get_hw_state = intel_connector_get_hw_state;
2811
9ed35ab1
PZ		 2812 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2813 if (HAS_DDI(dev)) {
2814 switch (intel_dig_port->port) {
2815 case PORT_A:
2816 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2817 break;
2818 case PORT_B:
2819 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2820 break;
2821 case PORT_C:
2822 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2823 break;
2824 case PORT_D:
2825 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2826 break;
2827 default:
2828 BUG();
2829 }
2830 }
e8cb4558 2831
a4fc5ed6 2832 /* Set up the DDC bus. */
ab9d7c30
PZ		 2833 switch (port) {
2834 case PORT_A:
1d843f9d 2835 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 2836 name = "DPDDC-A";
2837 break;
2838 case PORT_B:
1d843f9d 2839 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 2840 name = "DPDDC-B";
2841 break;
2842 case PORT_C:
1d843f9d 2843 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 2844 name = "DPDDC-C";
2845 break;
2846 case PORT_D:
1d843f9d 2847 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 2848 name = "DPDDC-D";
2849 break;
2850 default:
ad1c0b19 2851 BUG();
5eb08b69
ZW		 2852 }
2853
67a54566 2854 if (is_edp(intel_dp))
f30d26e4 2855 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 2856
2857 intel_dp_i2c_init(intel_dp, intel_connector, name);
2858
67a54566 2859 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2860 if (is_edp(intel_dp)) {
2861 bool ret;
f8779fda 2862 struct drm_display_mode *scan;
c1f05264 2863 struct edid *edid;
5d613501
JB		 2864
2865 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2866 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2867 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2868
59f3e272 2869 if (ret) {
7183dc29
JB		 2870 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2871 dev_priv->no_aux_handshake =
2872 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2873 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2874 } else {
3d3dc149 2875 /* if this fails, presume the device is a ghost */
48898b03 2876 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2877 intel_dp_encoder_destroy(&intel_encoder->base);
2878 intel_dp_destroy(connector);
3d3dc149 2879 return;
89667383 2880 }
89667383 2881
f30d26e4
JN		 2882 /* We now know it's not a ghost, init power sequence regs. */
2883 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2884 &power_seq);
2885
d6f24d0f
JB		 2886 ironlake_edp_panel_vdd_on(intel_dp);
2887 edid = drm_get_edid(connector, &intel_dp->adapter);
2888 if (edid) {
9cd300e0
JN		 2889 if (drm_add_edid_modes(connector, edid)) {
2890 drm_mode_connector_update_edid_property(connector, edid);
2891 drm_edid_to_eld(connector, edid);
2892 } else {
2893 kfree(edid);
2894 edid = ERR_PTR(-EINVAL);
2895 }
2896 } else {
2897 edid = ERR_PTR(-ENOENT);
d6f24d0f 2898 }
9cd300e0 2899 intel_connector->edid = edid;
f8779fda
JN		 2900
2901 /* prefer fixed mode from EDID if available */
2902 list_for_each_entry(scan, &connector->probed_modes, head) {
2903 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2904 fixed_mode = drm_mode_duplicate(dev, scan);
2905 break;
2906 }
d6f24d0f 2907 }
f8779fda
JN		 2908
2909 /* fallback to VBT if available for eDP */
2910 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2911 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2912 if (fixed_mode)
2913 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2914 }
f8779fda 2915
d6f24d0f
JB		 2916 ironlake_edp_panel_vdd_off(intel_dp, false);
2917 }
552fb0b7 2918
4d926461 2919 if (is_edp(intel_dp)) {
dd06f90e 2920 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2921 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2922 }
2923
f684960e
CW		 2924 intel_dp_add_properties(intel_dp, connector);
2925
a4fc5ed6
KP		 2926 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2927 * 0xd. Failure to do so will result in spurious interrupts being
2928 * generated on the port when a cable is not attached.
2929 */
2930 if (IS_G4X(dev) && !IS_GM45(dev)) {
2931 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2932 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2933 }
2934}
f0fec3f2
PZ		 2935
2936void
2937intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2938{
2939 struct intel_digital_port *intel_dig_port;
2940 struct intel_encoder *intel_encoder;
2941 struct drm_encoder *encoder;
2942 struct intel_connector *intel_connector;
2943
2944 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2945 if (!intel_dig_port)
2946 return;
2947
2948 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2949 if (!intel_connector) {
2950 kfree(intel_dig_port);
2951 return;
2952 }
2953
2954 intel_encoder = &intel_dig_port->base;
2955 encoder = &intel_encoder->base;
2956
2957 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2958 DRM_MODE_ENCODER_TMDS);
00c09d70 2959 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2960
5bfe2ac0 2961 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 2962 intel_encoder->enable = intel_enable_dp;
2963 intel_encoder->pre_enable = intel_pre_enable_dp;
2964 intel_encoder->disable = intel_disable_dp;
2965 intel_encoder->post_disable = intel_post_disable_dp;
2966 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2967
174edf1f 2968 intel_dig_port->port = port;
f0fec3f2
PZ		 2969 intel_dig_port->dp.output_reg = output_reg;
2970
00c09d70 2971 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2972 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2973 intel_encoder->cloneable = false;
2974 intel_encoder->hot_plug = intel_dp_hot_plug;
2975
2976 intel_dp_init_connector(intel_dig_port, intel_connector);
2977}
Linux 6.x block layer and io_uring tree(s)