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drm/i915: remove leftover display.update_wm assignment
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
32f9d658 112void
0206e353 113intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 114 int *lane_num, int *link_bw)
32f9d658 115{
fa90ecef 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
32f9d658 117
ea5b213a 118 *lane_num = intel_dp->lane_count;
3b5c662e 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
fa90ecef 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
dd06f90e 127 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 128
dd06f90e
JN		 129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 131 else
132 return mode->clock;
133}
134
a4fc5ed6 135static int
ea5b213a 136intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 137{
7183dc29 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
cd9dde44
AJ		 151/*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
a4fc5ed6 168static int
c898261c 169intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 170{
cd9dde44 171 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 172}
173
fe27d53e
DA		 174static int
175intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176{
177 return (max_link_clock * max_lanes * 8) / 10;
178}
179
c4867936
DV		 180static bool
181intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
cb1793ce 183 bool adjust_mode)
c4867936 184{
9fa5f652
PZ		 185 int max_link_clock =
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
30add22d 295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
30add22d 303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
30add22d 312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
9ee32fea
DV		 325static uint32_t
326intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
332 uint32_t status;
333 bool done;
334
335 if (IS_HASWELL(dev)) {
336 switch (intel_dig_port->port) {
337 case PORT_A:
338 ch_ctl = DPA_AUX_CH_CTL;
339 break;
340 case PORT_B:
341 ch_ctl = PCH_DPB_AUX_CH_CTL;
342 break;
343 case PORT_C:
344 ch_ctl = PCH_DPC_AUX_CH_CTL;
345 break;
346 case PORT_D:
347 ch_ctl = PCH_DPD_AUX_CH_CTL;
348 break;
349 default:
350 BUG();
351 }
352 }
353
ef04f00d 354#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea
DV		 355 if (has_aux_irq)
356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
357 else
358 done = wait_for_atomic(C, 10) == 0;
359 if (!done)
360 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
361 has_aux_irq);
362#undef C
363
364 return status;
365}
366
a4fc5ed6 367static int
ea5b213a 368intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 369 uint8_t *send, int send_bytes,
370 uint8_t *recv, int recv_size)
371{
ea5b213a 372 uint32_t output_reg = intel_dp->output_reg;
174edf1f
PZ		 373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6
KP		 375 struct drm_i915_private *dev_priv = dev->dev_private;
376 uint32_t ch_ctl = output_reg + 0x10;
377 uint32_t ch_data = ch_ctl + 4;
9ee32fea 378 int i, ret, recv_bytes;
a4fc5ed6 379 uint32_t status;
fb0f8fbf 380 uint32_t aux_clock_divider;
6b4e0a93 381 int try, precharge;
9ee32fea
DV		 382 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
383
384 /* dp aux is extremely sensitive to irq latency, hence request the
385 * lowest possible wakeup latency and so prevent the cpu from going into
386 * deep sleep states.
387 */
388 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 389
750eb99e 390 if (IS_HASWELL(dev)) {
174edf1f 391 switch (intel_dig_port->port) {
750eb99e
PZ		 392 case PORT_A:
393 ch_ctl = DPA_AUX_CH_CTL;
394 ch_data = DPA_AUX_CH_DATA1;
395 break;
396 case PORT_B:
397 ch_ctl = PCH_DPB_AUX_CH_CTL;
398 ch_data = PCH_DPB_AUX_CH_DATA1;
399 break;
400 case PORT_C:
401 ch_ctl = PCH_DPC_AUX_CH_CTL;
402 ch_data = PCH_DPC_AUX_CH_DATA1;
403 break;
404 case PORT_D:
405 ch_ctl = PCH_DPD_AUX_CH_CTL;
406 ch_data = PCH_DPD_AUX_CH_DATA1;
407 break;
408 default:
409 BUG();
410 }
411 }
412
9b984dae 413 intel_dp_check_edp(intel_dp);
a4fc5ed6 414 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 415 * and would like to run at 2MHz. So, take the
416 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 417 *
418 * Note that PCH attached eDP panels should use a 125MHz input
419 * clock divider.
a4fc5ed6 420 */
1c95822a 421 if (is_cpu_edp(intel_dp)) {
affa9354 422 if (HAS_DDI(dev))
b8fc2f6a
PZ		 423 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
424 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 425 aux_clock_divider = 100;
426 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 427 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 428 else
429 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
430 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 431 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 432 else
433 aux_clock_divider = intel_hrawclk(dev) / 2;
434
6b4e0a93
DV		 435 if (IS_GEN6(dev))
436 precharge = 3;
437 else
438 precharge = 5;
439
11bee43e
JB		 440 /* Try to wait for any previous AUX channel activity */
441 for (try = 0; try < 3; try++) {
ef04f00d 442 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 443 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
444 break;
445 msleep(1);
446 }
447
448 if (try == 3) {
449 WARN(1, "dp_aux_ch not started status 0x%08x\n",
450 I915_READ(ch_ctl));
9ee32fea
DV		 451 ret = -EBUSY;
452 goto out;
4f7f7b7e
CW		 453 }
454
fb0f8fbf
KP		 455 /* Must try at least 3 times according to DP spec */
456 for (try = 0; try < 5; try++) {
457 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 458 for (i = 0; i < send_bytes; i += 4)
459 I915_WRITE(ch_data + i,
460 pack_aux(send + i, send_bytes - i));
0206e353 461
fb0f8fbf 462 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 463 I915_WRITE(ch_ctl,
464 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 465 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 466 DP_AUX_CH_CTL_TIME_OUT_400us |
467 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
468 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
469 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
470 DP_AUX_CH_CTL_DONE |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 473
474 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 475
fb0f8fbf 476 /* Clear done status and any errors */
4f7f7b7e
CW		 477 I915_WRITE(ch_ctl,
478 status |
479 DP_AUX_CH_CTL_DONE |
480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 482
483 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
484 DP_AUX_CH_CTL_RECEIVE_ERROR))
485 continue;
4f7f7b7e 486 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 487 break;
488 }
489
a4fc5ed6 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 492 ret = -EBUSY;
493 goto out;
a4fc5ed6
KP		 494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
a5b3da54 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 501 ret = -EIO;
502 goto out;
a5b3da54 503 }
1ae8c0a5
KP		 504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
a5b3da54 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 509 ret = -ETIMEDOUT;
510 goto out;
a4fc5ed6
KP		 511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
0206e353 518
4f7f7b7e
CW		 519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
a4fc5ed6 522
9ee32fea
DV		 523 ret = recv_bytes;
524out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
526
527 return ret;
a4fc5ed6
KP		 528}
529
530/* Write data to the aux channel in native mode */
531static int
ea5b213a 532intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 533 uint16_t address, uint8_t *send, int send_bytes)
534{
535 int ret;
536 uint8_t msg[20];
537 int msg_bytes;
538 uint8_t ack;
539
9b984dae 540 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 541 if (send_bytes > 16)
542 return -1;
543 msg[0] = AUX_NATIVE_WRITE << 4;
544 msg[1] = address >> 8;
eebc863e 545 msg[2] = address & 0xff;
a4fc5ed6
KP		 546 msg[3] = send_bytes - 1;
547 memcpy(&msg[4], send, send_bytes);
548 msg_bytes = send_bytes + 4;
549 for (;;) {
ea5b213a 550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 551 if (ret < 0)
552 return ret;
553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
554 break;
555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
556 udelay(100);
557 else
a5b3da54 558 return -EIO;
a4fc5ed6
KP		 559 }
560 return send_bytes;
561}
562
563/* Write a single byte to the aux channel in native mode */
564static int
ea5b213a 565intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 566 uint16_t address, uint8_t byte)
567{
ea5b213a 568 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 569}
570
571/* read bytes from a native aux channel */
572static int
ea5b213a 573intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 574 uint16_t address, uint8_t *recv, int recv_bytes)
575{
576 uint8_t msg[4];
577 int msg_bytes;
578 uint8_t reply[20];
579 int reply_bytes;
580 uint8_t ack;
581 int ret;
582
9b984dae 583 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 584 msg[0] = AUX_NATIVE_READ << 4;
585 msg[1] = address >> 8;
586 msg[2] = address & 0xff;
587 msg[3] = recv_bytes - 1;
588
589 msg_bytes = 4;
590 reply_bytes = recv_bytes + 1;
591
592 for (;;) {
ea5b213a 593 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 594 reply, reply_bytes);
a5b3da54
KP		 595 if (ret == 0)
596 return -EPROTO;
597 if (ret < 0)
a4fc5ed6
KP		 598 return ret;
599 ack = reply[0];
600 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
601 memcpy(recv, reply + 1, ret - 1);
602 return ret - 1;
603 }
604 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
605 udelay(100);
606 else
a5b3da54 607 return -EIO;
a4fc5ed6
KP		 608 }
609}
610
611static int
ab2c0672
DA		 612intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
613 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 614{
ab2c0672 615 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 616 struct intel_dp *intel_dp = container_of(adapter,
617 struct intel_dp,
618 adapter);
ab2c0672
DA		 619 uint16_t address = algo_data->address;
620 uint8_t msg[5];
621 uint8_t reply[2];
8316f337 622 unsigned retry;
ab2c0672
DA		 623 int msg_bytes;
624 int reply_bytes;
625 int ret;
626
9b984dae 627 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 628 /* Set up the command byte */
629 if (mode & MODE_I2C_READ)
630 msg[0] = AUX_I2C_READ << 4;
631 else
632 msg[0] = AUX_I2C_WRITE << 4;
633
634 if (!(mode & MODE_I2C_STOP))
635 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 636
ab2c0672
DA		 637 msg[1] = address >> 8;
638 msg[2] = address;
639
640 switch (mode) {
641 case MODE_I2C_WRITE:
642 msg[3] = 0;
643 msg[4] = write_byte;
644 msg_bytes = 5;
645 reply_bytes = 1;
646 break;
647 case MODE_I2C_READ:
648 msg[3] = 0;
649 msg_bytes = 4;
650 reply_bytes = 2;
651 break;
652 default:
653 msg_bytes = 3;
654 reply_bytes = 1;
655 break;
656 }
657
8316f337
DF		 658 for (retry = 0; retry < 5; retry++) {
659 ret = intel_dp_aux_ch(intel_dp,
660 msg, msg_bytes,
661 reply, reply_bytes);
ab2c0672 662 if (ret < 0) {
3ff99164 663 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 664 return ret;
665 }
8316f337
DF		 666
667 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
668 case AUX_NATIVE_REPLY_ACK:
669 /* I2C-over-AUX Reply field is only valid
670 * when paired with AUX ACK.
671 */
672 break;
673 case AUX_NATIVE_REPLY_NACK:
674 DRM_DEBUG_KMS("aux_ch native nack\n");
675 return -EREMOTEIO;
676 case AUX_NATIVE_REPLY_DEFER:
677 udelay(100);
678 continue;
679 default:
680 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
681 reply[0]);
682 return -EREMOTEIO;
683 }
684
ab2c0672
DA		 685 switch (reply[0] & AUX_I2C_REPLY_MASK) {
686 case AUX_I2C_REPLY_ACK:
687 if (mode == MODE_I2C_READ) {
688 *read_byte = reply[1];
689 }
690 return reply_bytes - 1;
691 case AUX_I2C_REPLY_NACK:
8316f337 692 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 693 return -EREMOTEIO;
694 case AUX_I2C_REPLY_DEFER:
8316f337 695 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 696 udelay(100);
697 break;
698 default:
8316f337 699 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 700 return -EREMOTEIO;
701 }
702 }
8316f337
DF		 703
704 DRM_ERROR("too many retries, giving up\n");
705 return -EREMOTEIO;
a4fc5ed6
KP		 706}
707
708static int
ea5b213a 709intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 710 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 711{
0b5c541b
KP		 712 int ret;
713
d54e9d28 714 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 715 intel_dp->algo.running = false;
716 intel_dp->algo.address = 0;
717 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
718
0206e353 719 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 720 intel_dp->adapter.owner = THIS_MODULE;
721 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 722 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 723 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
724 intel_dp->adapter.algo_data = &intel_dp->algo;
725 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
726
0b5c541b
KP		 727 ironlake_edp_panel_vdd_on(intel_dp);
728 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 729 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 730 return ret;
a4fc5ed6
KP		 731}
732
00c09d70 733bool
e811f5ae
LP		 734intel_dp_mode_fixup(struct drm_encoder *encoder,
735 const struct drm_display_mode *mode,
a4fc5ed6
KP		 736 struct drm_display_mode *adjusted_mode)
737{
0d3a1bee 738 struct drm_device *dev = encoder->dev;
ea5b213a 739 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 740 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 741 int lane_count, clock;
397fe157 742 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 743 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 744 int bpp, mode_rate;
a4fc5ed6
KP		 745 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
746
dd06f90e
JN		 747 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
748 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
749 adjusted_mode);
53b41837
YN		 750 intel_pch_panel_fitting(dev,
751 intel_connector->panel.fitting_mode,
1d8e1c75 752 mode, adjusted_mode);
0d3a1bee
ZY		 753 }
754
cb1793ce 755 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 756 return false;
757
083f9560
DV		 758 DRM_DEBUG_KMS("DP link computation with max lane count %i "
759 "max bw %02x pixel clock %iKHz\n",
71244653 760 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 761
cb1793ce 762 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 763 return false;
764
765 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 766 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 767
2514bc51
JB		 768 for (clock = 0; clock <= max_clock; clock++) {
769 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
9fa5f652
PZ		 770 int link_bw_clock =
771 drm_dp_bw_code_to_link_rate(bws[clock]);
772 int link_avail = intel_dp_max_data_rate(link_bw_clock,
773 lane_count);
a4fc5ed6 774
083f9560 775 if (mode_rate <= link_avail) {
ea5b213a
CW		 776 intel_dp->link_bw = bws[clock];
777 intel_dp->lane_count = lane_count;
9fa5f652 778 adjusted_mode->clock = link_bw_clock;
083f9560
DV		 779 DRM_DEBUG_KMS("DP link bw %02x lane "
780 "count %d clock %d bpp %d\n",
ea5b213a 781 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 782 adjusted_mode->clock, bpp);
783 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
784 mode_rate, link_avail);
a4fc5ed6
KP		 785 return true;
786 }
787 }
788 }
fe27d53e 789
a4fc5ed6
KP		 790 return false;
791}
792
a4fc5ed6
KP		 793void
794intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
795 struct drm_display_mode *adjusted_mode)
796{
797 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 798 struct intel_encoder *intel_encoder;
799 struct intel_dp *intel_dp;
a4fc5ed6
KP		 800 struct drm_i915_private *dev_priv = dev->dev_private;
801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 802 int lane_count = 4;
e69d0bc1 803 struct intel_link_m_n m_n;
9db4a9c7 804 int pipe = intel_crtc->pipe;
afe2fcf5 805 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 806
807 /*
21d40d37 808 * Find the lane count in the intel_encoder private
a4fc5ed6 809 */
fa90ecef
PZ		 810 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
811 intel_dp = enc_to_intel_dp(&intel_encoder->base);
a4fc5ed6 812
fa90ecef
PZ		 813 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
814 intel_encoder->type == INTEL_OUTPUT_EDP)
9a10f401 815 {
ea5b213a 816 lane_count = intel_dp->lane_count;
51190667 817 break;
a4fc5ed6
KP		 818 }
819 }
820
821 /*
822 * Compute the GMCH and Link ratios. The '3' here is
823 * the number of bytes_per_pixel post-LUT, which we always
824 * set up for 8-bits of R/G/B, or 3 bytes total.
825 */
e69d0bc1
DV		 826 intel_link_compute_m_n(intel_crtc->bpp, lane_count,
827 mode->clock, adjusted_mode->clock, &m_n);
a4fc5ed6 828
1eb8dfec 829 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 830 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
831 TU_SIZE(m_n.tu) | m_n.gmch_m);
832 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
833 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
834 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 835 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 836 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 837 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
838 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
839 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 840 } else if (IS_VALLEYVIEW(dev)) {
841 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
842 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
843 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
844 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 845 } else {
9db4a9c7 846 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 847 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 848 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
849 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
850 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 851 }
852}
853
247d89f6
PZ		 854void intel_dp_init_link_config(struct intel_dp *intel_dp)
855{
856 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
857 intel_dp->link_configuration[0] = intel_dp->link_bw;
858 intel_dp->link_configuration[1] = intel_dp->lane_count;
859 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
860 /*
861 * Check for DPCD version > 1.1 and enhanced framing support
862 */
863 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
864 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
865 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
866 }
867}
868
ea9b6006
DV		 869static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
870{
871 struct drm_device *dev = crtc->dev;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873 u32 dpa_ctl;
874
875 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
876 dpa_ctl = I915_READ(DP_A);
877 dpa_ctl &= ~DP_PLL_FREQ_MASK;
878
879 if (clock < 200000) {
1ce17038
DV		 880 /* For a long time we've carried around a ILK-DevA w/a for the
881 * 160MHz clock. If we're really unlucky, it's still required.
882 */
883 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 884 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 885 } else {
886 dpa_ctl |= DP_PLL_FREQ_270MHZ;
887 }
1ce17038 888
ea9b6006
DV		 889 I915_WRITE(DP_A, dpa_ctl);
890
891 POSTING_READ(DP_A);
892 udelay(500);
893}
894
a4fc5ed6
KP		 895static void
896intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
897 struct drm_display_mode *adjusted_mode)
898{
e3421a18 899 struct drm_device *dev = encoder->dev;
417e822d 900 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 901 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 902 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
904
417e822d 905 /*
1a2eb460 906 * There are four kinds of DP registers:
417e822d
KP		 907 *
908 * IBX PCH
1a2eb460
KP		 909 * SNB CPU
910 * IVB CPU
417e822d
KP		 911 * CPT PCH
912 *
913 * IBX PCH and CPU are the same for almost everything,
914 * except that the CPU DP PLL is configured in this
915 * register
916 *
917 * CPT PCH is quite different, having many bits moved
918 * to the TRANS_DP_CTL register instead. That
919 * configuration happens (oddly) in ironlake_pch_enable
920 */
9c9e7927 921
417e822d
KP		 922 /* Preserve the BIOS-computed detected bit. This is
923 * supposed to be read-only.
924 */
925 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 926
417e822d 927 /* Handle DP bits in common between all three register formats */
417e822d 928 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 929
ea5b213a 930 switch (intel_dp->lane_count) {
a4fc5ed6 931 case 1:
ea5b213a 932 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 933 break;
934 case 2:
ea5b213a 935 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 936 break;
937 case 4:
ea5b213a 938 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 939 break;
940 }
e0dac65e
WF		 941 if (intel_dp->has_audio) {
942 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
943 pipe_name(intel_crtc->pipe));
ea5b213a 944 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 945 intel_write_eld(encoder, adjusted_mode);
946 }
247d89f6
PZ		 947
948 intel_dp_init_link_config(intel_dp);
a4fc5ed6 949
417e822d 950 /* Split out the IBX/CPU vs CPT settings */
32f9d658 951
19c03924 952 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 953 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
954 intel_dp->DP |= DP_SYNC_HS_HIGH;
955 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
956 intel_dp->DP |= DP_SYNC_VS_HIGH;
957 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
958
959 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
960 intel_dp->DP |= DP_ENHANCED_FRAMING;
961
962 intel_dp->DP |= intel_crtc->pipe << 29;
963
964 /* don't miss out required setting for eDP */
1a2eb460
KP		 965 if (adjusted_mode->clock < 200000)
966 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
967 else
968 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
969 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 970 intel_dp->DP |= intel_dp->color_range;
971
972 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
973 intel_dp->DP |= DP_SYNC_HS_HIGH;
974 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
975 intel_dp->DP |= DP_SYNC_VS_HIGH;
976 intel_dp->DP |= DP_LINK_TRAIN_OFF;
977
978 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
979 intel_dp->DP |= DP_ENHANCED_FRAMING;
980
981 if (intel_crtc->pipe == 1)
982 intel_dp->DP |= DP_PIPEB_SELECT;
983
984 if (is_cpu_edp(intel_dp)) {
985 /* don't miss out required setting for eDP */
417e822d
KP		 986 if (adjusted_mode->clock < 200000)
987 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
988 else
989 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
990 }
991 } else {
992 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 993 }
ea9b6006
DV		 994
995 if (is_cpu_edp(intel_dp))
996 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 997}
998
99ea7127
KP		 999#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1000#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1001
1002#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1003#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1004
1005#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1006#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1007
1008static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1009 u32 mask,
1010 u32 value)
bd943159 1011{
30add22d 1012 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1013 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 1014
99ea7127
KP		 1015 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1016 mask, value,
1017 I915_READ(PCH_PP_STATUS),
1018 I915_READ(PCH_PP_CONTROL));
32ce697c 1019
99ea7127
KP		 1020 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1021 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1022 I915_READ(PCH_PP_STATUS),
1023 I915_READ(PCH_PP_CONTROL));
32ce697c 1024 }
99ea7127 1025}
32ce697c 1026
99ea7127
KP		 1027static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1028{
1029 DRM_DEBUG_KMS("Wait for panel power on\n");
1030 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1031}
1032
99ea7127
KP		 1033static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1034{
1035 DRM_DEBUG_KMS("Wait for panel power off time\n");
1036 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1037}
1038
1039static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1040{
1041 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1042 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1043}
1044
1045
832dd3c1
KP		 1046/* Read the current pp_control value, unlocking the register if it
1047 * is locked
1048 */
1049
1050static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1051{
1052 u32 control = I915_READ(PCH_PP_CONTROL);
1053
1054 control &= ~PANEL_UNLOCK_MASK;
1055 control |= PANEL_UNLOCK_REGS;
1056 return control;
bd943159
KP		 1057}
1058
82a4d9c0 1059void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1060{
30add22d 1061 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1062 struct drm_i915_private *dev_priv = dev->dev_private;
1063 u32 pp;
1064
97af61f5
KP		 1065 if (!is_edp(intel_dp))
1066 return;
f01eca2e 1067 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1068
bd943159
KP		 1069 WARN(intel_dp->want_panel_vdd,
1070 "eDP VDD already requested on\n");
1071
1072 intel_dp->want_panel_vdd = true;
99ea7127 1073
bd943159
KP		 1074 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1075 DRM_DEBUG_KMS("eDP VDD already on\n");
1076 return;
1077 }
1078
99ea7127
KP		 1079 if (!ironlake_edp_have_panel_power(intel_dp))
1080 ironlake_wait_panel_power_cycle(intel_dp);
1081
832dd3c1 1082 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1083 pp |= EDP_FORCE_VDD;
1084 I915_WRITE(PCH_PP_CONTROL, pp);
1085 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1086 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1087 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1088
1089 /*
1090 * If the panel wasn't on, delay before accessing aux channel
1091 */
1092 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1093 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1094 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1095 }
5d613501
JB		 1096}
1097
bd943159 1098static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1099{
30add22d 1100 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1101 struct drm_i915_private *dev_priv = dev->dev_private;
1102 u32 pp;
1103
bd943159 1104 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1105 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1106 pp &= ~EDP_FORCE_VDD;
1107 I915_WRITE(PCH_PP_CONTROL, pp);
1108 POSTING_READ(PCH_PP_CONTROL);
1109
1110 /* Make sure sequencer is idle before allowing subsequent activity */
1111 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1112 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1113
1114 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1115 }
1116}
5d613501 1117
bd943159
KP		 1118static void ironlake_panel_vdd_work(struct work_struct *__work)
1119{
1120 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1121 struct intel_dp, panel_vdd_work);
30add22d 1122 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1123
627f7675 1124 mutex_lock(&dev->mode_config.mutex);
bd943159 1125 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1126 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1127}
1128
82a4d9c0 1129void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1130{
97af61f5
KP		 1131 if (!is_edp(intel_dp))
1132 return;
5d613501 1133
bd943159
KP		 1134 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1135 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1136
bd943159
KP		 1137 intel_dp->want_panel_vdd = false;
1138
1139 if (sync) {
1140 ironlake_panel_vdd_off_sync(intel_dp);
1141 } else {
1142 /*
1143 * Queue the timer to fire a long
1144 * time from now (relative to the power down delay)
1145 * to keep the panel power up across a sequence of operations
1146 */
1147 schedule_delayed_work(&intel_dp->panel_vdd_work,
1148 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1149 }
5d613501
JB		 1150}
1151
82a4d9c0 1152void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1153{
30add22d 1154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1155 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1156 u32 pp;
9934c132 1157
97af61f5 1158 if (!is_edp(intel_dp))
bd943159 1159 return;
99ea7127
KP		 1160
1161 DRM_DEBUG_KMS("Turn eDP power on\n");
1162
1163 if (ironlake_edp_have_panel_power(intel_dp)) {
1164 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1165 return;
99ea7127 1166 }
9934c132 1167
99ea7127 1168 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1169
99ea7127 1170 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1171 if (IS_GEN5(dev)) {
1172 /* ILK workaround: disable reset around power sequence */
1173 pp &= ~PANEL_POWER_RESET;
1174 I915_WRITE(PCH_PP_CONTROL, pp);
1175 POSTING_READ(PCH_PP_CONTROL);
1176 }
37c6c9b0 1177
1c0ae80a 1178 pp |= POWER_TARGET_ON;
99ea7127
KP		 1179 if (!IS_GEN5(dev))
1180 pp |= PANEL_POWER_RESET;
1181
9934c132 1182 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1183 POSTING_READ(PCH_PP_CONTROL);
9934c132 1184
99ea7127 1185 ironlake_wait_panel_on(intel_dp);
9934c132 1186
05ce1a49
KP		 1187 if (IS_GEN5(dev)) {
1188 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1189 I915_WRITE(PCH_PP_CONTROL, pp);
1190 POSTING_READ(PCH_PP_CONTROL);
1191 }
9934c132
JB		 1192}
1193
82a4d9c0 1194void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1195{
30add22d 1196 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1197 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1198 u32 pp;
9934c132 1199
97af61f5
KP		 1200 if (!is_edp(intel_dp))
1201 return;
37c6c9b0 1202
99ea7127 1203 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1204
6cb49835 1205 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1206
99ea7127 1207 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1208 /* We need to switch off panel power _and_ force vdd, for otherwise some
1209 * panels get very unhappy and cease to work. */
1210 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1211 I915_WRITE(PCH_PP_CONTROL, pp);
1212 POSTING_READ(PCH_PP_CONTROL);
9934c132 1213
35a38556
DV		 1214 intel_dp->want_panel_vdd = false;
1215
99ea7127 1216 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1217}
1218
d6c50ff8 1219void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1220{
da63a9f2
PZ		 1221 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1222 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1223 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1224 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658
ZW		 1225 u32 pp;
1226
f01eca2e
KP		 1227 if (!is_edp(intel_dp))
1228 return;
1229
28c97730 1230 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1231 /*
1232 * If we enable the backlight right away following a panel power
1233 * on, we may see slight flicker as the panel syncs with the eDP
1234 * link. So delay a bit to make sure the image is solid before
1235 * allowing it to appear.
1236 */
f01eca2e 1237 msleep(intel_dp->backlight_on_delay);
832dd3c1 1238 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1239 pp |= EDP_BLC_ENABLE;
1240 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1241 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1242
1243 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1244}
1245
d6c50ff8 1246void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1247{
30add22d 1248 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250 u32 pp;
1251
f01eca2e
KP		 1252 if (!is_edp(intel_dp))
1253 return;
1254
035aa3de
DV		 1255 intel_panel_disable_backlight(dev);
1256
28c97730 1257 DRM_DEBUG_KMS("\n");
832dd3c1 1258 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1259 pp &= ~EDP_BLC_ENABLE;
1260 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1261 POSTING_READ(PCH_PP_CONTROL);
1262 msleep(intel_dp->backlight_off_delay);
32f9d658 1263}
a4fc5ed6 1264
2bd2ad64 1265static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1266{
da63a9f2
PZ		 1267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1268 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1269 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1270 struct drm_i915_private *dev_priv = dev->dev_private;
1271 u32 dpa_ctl;
1272
2bd2ad64
DV		 1273 assert_pipe_disabled(dev_priv,
1274 to_intel_crtc(crtc)->pipe);
1275
d240f20f
JB		 1276 DRM_DEBUG_KMS("\n");
1277 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1278 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1279 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1280
1281 /* We don't adjust intel_dp->DP while tearing down the link, to
1282 * facilitate link retraining (e.g. after hotplug). Hence clear all
1283 * enable bits here to ensure that we don't enable too much. */
1284 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1285 intel_dp->DP |= DP_PLL_ENABLE;
1286 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1287 POSTING_READ(DP_A);
1288 udelay(200);
d240f20f
JB		 1289}
1290
2bd2ad64 1291static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1292{
da63a9f2
PZ		 1293 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1294 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1295 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 u32 dpa_ctl;
1298
2bd2ad64
DV		 1299 assert_pipe_disabled(dev_priv,
1300 to_intel_crtc(crtc)->pipe);
1301
d240f20f 1302 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1303 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1304 "dp pll off, should be on\n");
1305 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1306
1307 /* We can't rely on the value tracked for the DP register in
1308 * intel_dp->DP because link_down must not change that (otherwise link
1309 * re-training will fail. */
298b0b39 1310 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1311 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1312 POSTING_READ(DP_A);
d240f20f
JB		 1313 udelay(200);
1314}
1315
c7ad3810 1316/* If the sink supports it, try to set the power state appropriately */
c19b0669 1317void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1318{
1319 int ret, i;
1320
1321 /* Should have a valid DPCD by this point */
1322 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1323 return;
1324
1325 if (mode != DRM_MODE_DPMS_ON) {
1326 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1327 DP_SET_POWER_D3);
1328 if (ret != 1)
1329 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1330 } else {
1331 /*
1332 * When turning on, we need to retry for 1ms to give the sink
1333 * time to wake up.
1334 */
1335 for (i = 0; i < 3; i++) {
1336 ret = intel_dp_aux_native_write_1(intel_dp,
1337 DP_SET_POWER,
1338 DP_SET_POWER_D0);
1339 if (ret == 1)
1340 break;
1341 msleep(1);
1342 }
1343 }
1344}
1345
19d8fe15
DV		 1346static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1347 enum pipe *pipe)
d240f20f 1348{
19d8fe15
DV		 1349 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1350 struct drm_device *dev = encoder->base.dev;
1351 struct drm_i915_private *dev_priv = dev->dev_private;
1352 u32 tmp = I915_READ(intel_dp->output_reg);
1353
1354 if (!(tmp & DP_PORT_EN))
1355 return false;
1356
1357 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1358 *pipe = PORT_TO_PIPE_CPT(tmp);
1359 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1360 *pipe = PORT_TO_PIPE(tmp);
1361 } else {
1362 u32 trans_sel;
1363 u32 trans_dp;
1364 int i;
1365
1366 switch (intel_dp->output_reg) {
1367 case PCH_DP_B:
1368 trans_sel = TRANS_DP_PORT_SEL_B;
1369 break;
1370 case PCH_DP_C:
1371 trans_sel = TRANS_DP_PORT_SEL_C;
1372 break;
1373 case PCH_DP_D:
1374 trans_sel = TRANS_DP_PORT_SEL_D;
1375 break;
1376 default:
1377 return true;
1378 }
1379
1380 for_each_pipe(i) {
1381 trans_dp = I915_READ(TRANS_DP_CTL(i));
1382 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1383 *pipe = i;
1384 return true;
1385 }
1386 }
19d8fe15 1387
4a0833ec
DV		 1388 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1389 intel_dp->output_reg);
1390 }
d240f20f 1391
19d8fe15
DV		 1392 return true;
1393}
d240f20f 1394
e8cb4558 1395static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1396{
e8cb4558 1397 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1398
1399 /* Make sure the panel is off before trying to change the mode. But also
1400 * ensure that we have vdd while we switch off the panel. */
1401 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1402 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1403 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1404 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1405
1406 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1407 if (!is_cpu_edp(intel_dp))
1408 intel_dp_link_down(intel_dp);
d240f20f
JB		 1409}
1410
2bd2ad64 1411static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1412{
2bd2ad64
DV		 1413 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1414
3739850b
DV		 1415 if (is_cpu_edp(intel_dp)) {
1416 intel_dp_link_down(intel_dp);
2bd2ad64 1417 ironlake_edp_pll_off(intel_dp);
3739850b 1418 }
2bd2ad64
DV		 1419}
1420
e8cb4558 1421static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1422{
e8cb4558
DV		 1423 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1424 struct drm_device *dev = encoder->base.dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1427
0c33d8d7
DV		 1428 if (WARN_ON(dp_reg & DP_PORT_EN))
1429 return;
5d613501 1430
97af61f5 1431 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1432 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1433 intel_dp_start_link_train(intel_dp);
97af61f5 1434 ironlake_edp_panel_on(intel_dp);
bd943159 1435 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1436 intel_dp_complete_link_train(intel_dp);
f01eca2e 1437 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1438}
1439
2bd2ad64 1440static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1441{
2bd2ad64 1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 1443
2bd2ad64
DV		 1444 if (is_cpu_edp(intel_dp))
1445 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1446}
1447
1448/*
df0c237d
JB		 1449 * Native read with retry for link status and receiver capability reads for
1450 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1451 */
1452static bool
df0c237d
JB		 1453intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1454 uint8_t *recv, int recv_bytes)
a4fc5ed6 1455{
61da5fab
JB		 1456 int ret, i;
1457
df0c237d
JB		 1458 /*
1459 * Sinks are *supposed* to come up within 1ms from an off state,
1460 * but we're also supposed to retry 3 times per the spec.
1461 */
61da5fab 1462 for (i = 0; i < 3; i++) {
df0c237d
JB		 1463 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1464 recv_bytes);
1465 if (ret == recv_bytes)
61da5fab
JB		 1466 return true;
1467 msleep(1);
1468 }
a4fc5ed6 1469
61da5fab 1470 return false;
a4fc5ed6
KP		 1471}
1472
1473/*
1474 * Fetch AUX CH registers 0x202 - 0x207 which contain
1475 * link status information
1476 */
1477static bool
93f62dad 1478intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1479{
df0c237d
JB		 1480 return intel_dp_aux_native_read_retry(intel_dp,
1481 DP_LANE0_1_STATUS,
93f62dad 1482 link_status,
df0c237d 1483 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1484}
1485
a4fc5ed6
KP		 1486#if 0
1487static char *voltage_names[] = {
1488 "0.4V", "0.6V", "0.8V", "1.2V"
1489};
1490static char *pre_emph_names[] = {
1491 "0dB", "3.5dB", "6dB", "9.5dB"
1492};
1493static char *link_train_names[] = {
1494 "pattern 1", "pattern 2", "idle", "off"
1495};
1496#endif
1497
1498/*
1499 * These are source-specific values; current Intel hardware supports
1500 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1501 */
a4fc5ed6
KP		 1502
1503static uint8_t
1a2eb460 1504intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1505{
30add22d 1506 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1507
1508 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1509 return DP_TRAIN_VOLTAGE_SWING_800;
1510 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1511 return DP_TRAIN_VOLTAGE_SWING_1200;
1512 else
1513 return DP_TRAIN_VOLTAGE_SWING_800;
1514}
1515
1516static uint8_t
1517intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1518{
30add22d 1519 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1520
d6c0d722
PZ		 1521 if (IS_HASWELL(dev)) {
1522 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1523 case DP_TRAIN_VOLTAGE_SWING_400:
1524 return DP_TRAIN_PRE_EMPHASIS_9_5;
1525 case DP_TRAIN_VOLTAGE_SWING_600:
1526 return DP_TRAIN_PRE_EMPHASIS_6;
1527 case DP_TRAIN_VOLTAGE_SWING_800:
1528 return DP_TRAIN_PRE_EMPHASIS_3_5;
1529 case DP_TRAIN_VOLTAGE_SWING_1200:
1530 default:
1531 return DP_TRAIN_PRE_EMPHASIS_0;
1532 }
1533 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1534 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1535 case DP_TRAIN_VOLTAGE_SWING_400:
1536 return DP_TRAIN_PRE_EMPHASIS_6;
1537 case DP_TRAIN_VOLTAGE_SWING_600:
1538 case DP_TRAIN_VOLTAGE_SWING_800:
1539 return DP_TRAIN_PRE_EMPHASIS_3_5;
1540 default:
1541 return DP_TRAIN_PRE_EMPHASIS_0;
1542 }
1543 } else {
1544 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1545 case DP_TRAIN_VOLTAGE_SWING_400:
1546 return DP_TRAIN_PRE_EMPHASIS_6;
1547 case DP_TRAIN_VOLTAGE_SWING_600:
1548 return DP_TRAIN_PRE_EMPHASIS_6;
1549 case DP_TRAIN_VOLTAGE_SWING_800:
1550 return DP_TRAIN_PRE_EMPHASIS_3_5;
1551 case DP_TRAIN_VOLTAGE_SWING_1200:
1552 default:
1553 return DP_TRAIN_PRE_EMPHASIS_0;
1554 }
a4fc5ed6
KP		 1555 }
1556}
1557
1558static void
93f62dad 1559intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1560{
1561 uint8_t v = 0;
1562 uint8_t p = 0;
1563 int lane;
1a2eb460
KP		 1564 uint8_t voltage_max;
1565 uint8_t preemph_max;
a4fc5ed6 1566
33a34e4e 1567 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1568 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1569 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1570
1571 if (this_v > v)
1572 v = this_v;
1573 if (this_p > p)
1574 p = this_p;
1575 }
1576
1a2eb460 1577 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1578 if (v >= voltage_max)
1579 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1580
1a2eb460
KP		 1581 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1582 if (p >= preemph_max)
1583 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1584
1585 for (lane = 0; lane < 4; lane++)
33a34e4e 1586 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1587}
1588
1589static uint32_t
93f62dad 1590intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1591{
3cf2efb1 1592 uint32_t signal_levels = 0;
a4fc5ed6 1593
3cf2efb1 1594 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1595 case DP_TRAIN_VOLTAGE_SWING_400:
1596 default:
1597 signal_levels |= DP_VOLTAGE_0_4;
1598 break;
1599 case DP_TRAIN_VOLTAGE_SWING_600:
1600 signal_levels |= DP_VOLTAGE_0_6;
1601 break;
1602 case DP_TRAIN_VOLTAGE_SWING_800:
1603 signal_levels |= DP_VOLTAGE_0_8;
1604 break;
1605 case DP_TRAIN_VOLTAGE_SWING_1200:
1606 signal_levels |= DP_VOLTAGE_1_2;
1607 break;
1608 }
3cf2efb1 1609 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1610 case DP_TRAIN_PRE_EMPHASIS_0:
1611 default:
1612 signal_levels |= DP_PRE_EMPHASIS_0;
1613 break;
1614 case DP_TRAIN_PRE_EMPHASIS_3_5:
1615 signal_levels |= DP_PRE_EMPHASIS_3_5;
1616 break;
1617 case DP_TRAIN_PRE_EMPHASIS_6:
1618 signal_levels |= DP_PRE_EMPHASIS_6;
1619 break;
1620 case DP_TRAIN_PRE_EMPHASIS_9_5:
1621 signal_levels |= DP_PRE_EMPHASIS_9_5;
1622 break;
1623 }
1624 return signal_levels;
1625}
1626
e3421a18
ZW		 1627/* Gen6's DP voltage swing and pre-emphasis control */
1628static uint32_t
1629intel_gen6_edp_signal_levels(uint8_t train_set)
1630{
3c5a62b5
YL		 1631 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1632 DP_TRAIN_PRE_EMPHASIS_MASK);
1633 switch (signal_levels) {
e3421a18 1634 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1635 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1636 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1637 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1638 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1640 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1641 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1642 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1643 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1644 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1645 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1646 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1647 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1648 default:
3c5a62b5
YL		 1649 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1650 "0x%x\n", signal_levels);
1651 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1652 }
1653}
1654
1a2eb460
KP		 1655/* Gen7's DP voltage swing and pre-emphasis control */
1656static uint32_t
1657intel_gen7_edp_signal_levels(uint8_t train_set)
1658{
1659 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1660 DP_TRAIN_PRE_EMPHASIS_MASK);
1661 switch (signal_levels) {
1662 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1663 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1664 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1665 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1666 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1667 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1668
1669 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1670 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1671 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1672 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1673
1674 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1675 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1676 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1678
1679 default:
1680 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1681 "0x%x\n", signal_levels);
1682 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1683 }
1684}
1685
d6c0d722
PZ		 1686/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1687static uint32_t
1688intel_dp_signal_levels_hsw(uint8_t train_set)
a4fc5ed6 1689{
d6c0d722
PZ		 1690 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1691 DP_TRAIN_PRE_EMPHASIS_MASK);
1692 switch (signal_levels) {
1693 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1694 return DDI_BUF_EMP_400MV_0DB_HSW;
1695 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1696 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1697 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1698 return DDI_BUF_EMP_400MV_6DB_HSW;
1699 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1700 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1701
d6c0d722
PZ		 1702 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1703 return DDI_BUF_EMP_600MV_0DB_HSW;
1704 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1705 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1706 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1707 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1708
d6c0d722
PZ		 1709 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1710 return DDI_BUF_EMP_800MV_0DB_HSW;
1711 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1712 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1713 default:
1714 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1715 "0x%x\n", signal_levels);
1716 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1717 }
a4fc5ed6
KP		 1718}
1719
1720static bool
ea5b213a 1721intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1722 uint32_t dp_reg_value,
58e10eb9 1723 uint8_t dp_train_pat)
a4fc5ed6 1724{
174edf1f
PZ		 1725 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1726 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1727 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1728 enum port port = intel_dig_port->port;
a4fc5ed6 1729 int ret;
d6c0d722 1730 uint32_t temp;
a4fc5ed6 1731
d6c0d722 1732 if (IS_HASWELL(dev)) {
174edf1f 1733 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1734
1735 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1736 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1737 else
1738 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1739
1740 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1741 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1742 case DP_TRAINING_PATTERN_DISABLE:
1743 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
174edf1f 1744 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 1745
174edf1f 1746 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
d6c0d722
PZ		 1747 DP_TP_STATUS_IDLE_DONE), 1))
1748 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1749
1750 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1751 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1752
1753 break;
1754 case DP_TRAINING_PATTERN_1:
1755 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1756 break;
1757 case DP_TRAINING_PATTERN_2:
1758 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1759 break;
1760 case DP_TRAINING_PATTERN_3:
1761 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1762 break;
1763 }
174edf1f 1764 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1765
1766 } else if (HAS_PCH_CPT(dev) &&
1767 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1768 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1769
1770 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1771 case DP_TRAINING_PATTERN_DISABLE:
1772 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1773 break;
1774 case DP_TRAINING_PATTERN_1:
1775 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1776 break;
1777 case DP_TRAINING_PATTERN_2:
1778 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1779 break;
1780 case DP_TRAINING_PATTERN_3:
1781 DRM_ERROR("DP training pattern 3 not supported\n");
1782 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1783 break;
1784 }
1785
1786 } else {
1787 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1788
1789 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1790 case DP_TRAINING_PATTERN_DISABLE:
1791 dp_reg_value |= DP_LINK_TRAIN_OFF;
1792 break;
1793 case DP_TRAINING_PATTERN_1:
1794 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1795 break;
1796 case DP_TRAINING_PATTERN_2:
1797 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1798 break;
1799 case DP_TRAINING_PATTERN_3:
1800 DRM_ERROR("DP training pattern 3 not supported\n");
1801 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1802 break;
1803 }
1804 }
1805
ea5b213a
CW		 1806 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1807 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1808
ea5b213a 1809 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1810 DP_TRAINING_PATTERN_SET,
1811 dp_train_pat);
1812
47ea7542
PZ		 1813 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1814 DP_TRAINING_PATTERN_DISABLE) {
1815 ret = intel_dp_aux_native_write(intel_dp,
1816 DP_TRAINING_LANE0_SET,
1817 intel_dp->train_set,
1818 intel_dp->lane_count);
1819 if (ret != intel_dp->lane_count)
1820 return false;
1821 }
a4fc5ed6
KP		 1822
1823 return true;
1824}
1825
33a34e4e 1826/* Enable corresponding port and start training pattern 1 */
c19b0669 1827void
33a34e4e 1828intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1829{
da63a9f2 1830 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1831 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1832 int i;
1833 uint8_t voltage;
1834 bool clock_recovery = false;
cdb0e95b 1835 int voltage_tries, loop_tries;
ea5b213a 1836 uint32_t DP = intel_dp->DP;
a4fc5ed6 1837
affa9354 1838 if (HAS_DDI(dev))
c19b0669
PZ		 1839 intel_ddi_prepare_link_retrain(encoder);
1840
3cf2efb1
CW		 1841 /* Write the link configuration data */
1842 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1843 intel_dp->link_configuration,
1844 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1845
1846 DP |= DP_PORT_EN;
1a2eb460 1847
33a34e4e 1848 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1849 voltage = 0xff;
cdb0e95b
KP		 1850 voltage_tries = 0;
1851 loop_tries = 0;
a4fc5ed6
KP		 1852 clock_recovery = false;
1853 for (;;) {
33a34e4e 1854 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1855 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1856 uint32_t signal_levels;
417e822d 1857
d6c0d722
PZ		 1858 if (IS_HASWELL(dev)) {
1859 signal_levels = intel_dp_signal_levels_hsw(
1860 intel_dp->train_set[0]);
1861 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1862 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1863 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1864 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1865 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1866 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1867 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1868 } else {
93f62dad 1869 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1870 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1871 }
d6c0d722
PZ		 1872 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1873 signal_levels);
a4fc5ed6 1874
a7c9655f 1875 /* Set training pattern 1 */
47ea7542 1876 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1877 DP_TRAINING_PATTERN_1 |
1878 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1879 break;
a4fc5ed6 1880
a7c9655f 1881 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1882 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1883 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1884 break;
93f62dad 1885 }
a4fc5ed6 1886
01916270 1887 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1888 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1889 clock_recovery = true;
1890 break;
1891 }
1892
1893 /* Check to see if we've tried the max voltage */
1894 for (i = 0; i < intel_dp->lane_count; i++)
1895 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1896 break;
0d710688 1897 if (i == intel_dp->lane_count && voltage_tries == 5) {
b06fbda3
DV		 1898 ++loop_tries;
1899 if (loop_tries == 5) {
cdb0e95b
KP		 1900 DRM_DEBUG_KMS("too many full retries, give up\n");
1901 break;
1902 }
1903 memset(intel_dp->train_set, 0, 4);
1904 voltage_tries = 0;
1905 continue;
1906 }
a4fc5ed6 1907
3cf2efb1 1908 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1909 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1910 ++voltage_tries;
b06fbda3
DV		 1911 if (voltage_tries == 5) {
1912 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1913 break;
1914 }
1915 } else
1916 voltage_tries = 0;
1917 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1918
3cf2efb1 1919 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1920 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1921 }
1922
33a34e4e
JB		 1923 intel_dp->DP = DP;
1924}
1925
c19b0669 1926void
33a34e4e
JB		 1927intel_dp_complete_link_train(struct intel_dp *intel_dp)
1928{
30add22d 1929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33a34e4e 1930 bool channel_eq = false;
37f80975 1931 int tries, cr_tries;
33a34e4e
JB		 1932 uint32_t DP = intel_dp->DP;
1933
a4fc5ed6
KP		 1934 /* channel equalization */
1935 tries = 0;
37f80975 1936 cr_tries = 0;
a4fc5ed6
KP		 1937 channel_eq = false;
1938 for (;;) {
33a34e4e 1939 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1940 uint32_t signal_levels;
93f62dad 1941 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1942
37f80975
JB		 1943 if (cr_tries > 5) {
1944 DRM_ERROR("failed to train DP, aborting\n");
1945 intel_dp_link_down(intel_dp);
1946 break;
1947 }
1948
d6c0d722
PZ		 1949 if (IS_HASWELL(dev)) {
1950 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1951 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1952 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1953 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1954 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1955 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1956 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1957 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1958 } else {
93f62dad 1959 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1960 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1961 }
1962
a4fc5ed6 1963 /* channel eq pattern */
47ea7542 1964 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1965 DP_TRAINING_PATTERN_2 |
1966 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1967 break;
1968
a7c9655f 1969 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1970 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1971 break;
a4fc5ed6 1972
37f80975 1973 /* Make sure clock is still ok */
01916270 1974 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1975 intel_dp_start_link_train(intel_dp);
1976 cr_tries++;
1977 continue;
1978 }
1979
1ffdff13 1980 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1981 channel_eq = true;
1982 break;
1983 }
a4fc5ed6 1984
37f80975
JB		 1985 /* Try 5 times, then try clock recovery if that fails */
1986 if (tries > 5) {
1987 intel_dp_link_down(intel_dp);
1988 intel_dp_start_link_train(intel_dp);
1989 tries = 0;
1990 cr_tries++;
1991 continue;
1992 }
a4fc5ed6 1993
3cf2efb1 1994 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1995 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1996 ++tries;
869184a6 1997 }
3cf2efb1 1998
d6c0d722
PZ		 1999 if (channel_eq)
2000 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2001
47ea7542 2002 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2003}
2004
2005static void
ea5b213a 2006intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2007{
da63a9f2
PZ		 2008 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2009 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2010 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2011 struct intel_crtc *intel_crtc =
2012 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2013 uint32_t DP = intel_dp->DP;
a4fc5ed6 2014
c19b0669
PZ		 2015 /*
2016 * DDI code has a strict mode set sequence and we should try to respect
2017 * it, otherwise we might hang the machine in many different ways. So we
2018 * really should be disabling the port only on a complete crtc_disable
2019 * sequence. This function is just called under two conditions on DDI
2020 * code:
2021 * - Link train failed while doing crtc_enable, and on this case we
2022 * really should respect the mode set sequence and wait for a
2023 * crtc_disable.
2024 * - Someone turned the monitor off and intel_dp_check_link_status
2025 * called us. We don't need to disable the whole port on this case, so
2026 * when someone turns the monitor on again,
2027 * intel_ddi_prepare_link_retrain will take care of redoing the link
2028 * train.
2029 */
affa9354 2030 if (HAS_DDI(dev))
c19b0669
PZ		 2031 return;
2032
0c33d8d7 2033 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2034 return;
2035
28c97730 2036 DRM_DEBUG_KMS("\n");
32f9d658 2037
1a2eb460 2038 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2039 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2040 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2041 } else {
2042 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2043 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2044 }
fe255d00 2045 POSTING_READ(intel_dp->output_reg);
5eb08b69 2046
ab527efc
DV		 2047 /* We don't really know why we're doing this */
2048 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2049
493a7081 2050 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2051 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2052 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2053
5bddd17f
EA		 2054 /* Hardware workaround: leaving our transcoder select
2055 * set to transcoder B while it's off will prevent the
2056 * corresponding HDMI output on transcoder A.
2057 *
2058 * Combine this with another hardware workaround:
2059 * transcoder select bit can only be cleared while the
2060 * port is enabled.
2061 */
2062 DP &= ~DP_PIPEB_SELECT;
2063 I915_WRITE(intel_dp->output_reg, DP);
2064
2065 /* Changes to enable or select take place the vblank
2066 * after being written.
2067 */
ff50afe9
DV		 2068 if (WARN_ON(crtc == NULL)) {
2069 /* We should never try to disable a port without a crtc
2070 * attached. For paranoia keep the code around for a
2071 * bit. */
31acbcc4
CW		 2072 POSTING_READ(intel_dp->output_reg);
2073 msleep(50);
2074 } else
ab527efc 2075 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2076 }
2077
832afda6 2078 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2079 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2080 POSTING_READ(intel_dp->output_reg);
f01eca2e 2081 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2082}
2083
26d61aad
KP		 2084static bool
2085intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2086{
577c7a50
DL		 2087 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2088
92fd8fd1 2089 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2090 sizeof(intel_dp->dpcd)) == 0)
2091 return false; /* aux transfer failed */
92fd8fd1 2092
577c7a50
DL		 2093 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2094 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2095 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2096
edb39244
AJ		 2097 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2098 return false; /* DPCD not present */
2099
2100 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2101 DP_DWN_STRM_PORT_PRESENT))
2102 return true; /* native DP sink */
2103
2104 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2105 return true; /* no per-port downstream info */
2106
2107 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2108 intel_dp->downstream_ports,
2109 DP_MAX_DOWNSTREAM_PORTS) == 0)
2110 return false; /* downstream port status fetch failed */
2111
2112 return true;
92fd8fd1
KP		 2113}
2114
0d198328
AJ		 2115static void
2116intel_dp_probe_oui(struct intel_dp *intel_dp)
2117{
2118 u8 buf[3];
2119
2120 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2121 return;
2122
351cfc34
DV		 2123 ironlake_edp_panel_vdd_on(intel_dp);
2124
0d198328
AJ		 2125 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2126 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2127 buf[0], buf[1], buf[2]);
2128
2129 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2130 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2131 buf[0], buf[1], buf[2]);
351cfc34
DV		 2132
2133 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2134}
2135
a60f0e38
JB		 2136static bool
2137intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2138{
2139 int ret;
2140
2141 ret = intel_dp_aux_native_read_retry(intel_dp,
2142 DP_DEVICE_SERVICE_IRQ_VECTOR,
2143 sink_irq_vector, 1);
2144 if (!ret)
2145 return false;
2146
2147 return true;
2148}
2149
2150static void
2151intel_dp_handle_test_request(struct intel_dp *intel_dp)
2152{
2153 /* NAK by default */
9324cf7f 2154 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2155}
2156
a4fc5ed6
KP		 2157/*
2158 * According to DP spec
2159 * 5.1.2:
2160 * 1. Read DPCD
2161 * 2. Configure link according to Receiver Capabilities
2162 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2163 * 4. Check link status on receipt of hot-plug interrupt
2164 */
2165
00c09d70 2166void
ea5b213a 2167intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2168{
da63a9f2 2169 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2170 u8 sink_irq_vector;
93f62dad 2171 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2172
da63a9f2 2173 if (!intel_encoder->connectors_active)
d2b996ac 2174 return;
59cd09e1 2175
da63a9f2 2176 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2177 return;
2178
92fd8fd1 2179 /* Try to read receiver status if the link appears to be up */
93f62dad 2180 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2181 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2182 return;
2183 }
2184
92fd8fd1 2185 /* Now read the DPCD to see if it's actually running */
26d61aad 2186 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2187 intel_dp_link_down(intel_dp);
2188 return;
2189 }
2190
a60f0e38
JB		 2191 /* Try to read the source of the interrupt */
2192 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2193 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2194 /* Clear interrupt source */
2195 intel_dp_aux_native_write_1(intel_dp,
2196 DP_DEVICE_SERVICE_IRQ_VECTOR,
2197 sink_irq_vector);
2198
2199 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2200 intel_dp_handle_test_request(intel_dp);
2201 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2202 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2203 }
2204
1ffdff13 2205 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2206 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2207 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2208 intel_dp_start_link_train(intel_dp);
2209 intel_dp_complete_link_train(intel_dp);
2210 }
a4fc5ed6 2211}
a4fc5ed6 2212
caf9ab24 2213/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2214static enum drm_connector_status
26d61aad 2215intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2216{
caf9ab24
AJ		 2217 uint8_t *dpcd = intel_dp->dpcd;
2218 bool hpd;
2219 uint8_t type;
2220
2221 if (!intel_dp_get_dpcd(intel_dp))
2222 return connector_status_disconnected;
2223
2224 /* if there's no downstream port, we're done */
2225 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2226 return connector_status_connected;
caf9ab24
AJ		 2227
2228 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2229 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2230 if (hpd) {
23235177 2231 uint8_t reg;
caf9ab24 2232 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2233 &reg, 1))
caf9ab24 2234 return connector_status_unknown;
23235177
AJ		 2235 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2236 : connector_status_disconnected;
caf9ab24
AJ		 2237 }
2238
2239 /* If no HPD, poke DDC gently */
2240 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2241 return connector_status_connected;
caf9ab24
AJ		 2242
2243 /* Well we tried, say unknown for unreliable port types */
2244 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2245 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2246 return connector_status_unknown;
2247
2248 /* Anything else is out of spec, warn and ignore */
2249 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2250 return connector_status_disconnected;
71ba9000
AJ		 2251}
2252
5eb08b69 2253static enum drm_connector_status
a9756bb5 2254ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2255{
30add22d 2256 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2257 struct drm_i915_private *dev_priv = dev->dev_private;
2258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2259 enum drm_connector_status status;
2260
fe16d949
CW		 2261 /* Can't disconnect eDP, but you can close the lid... */
2262 if (is_edp(intel_dp)) {
30add22d 2263 status = intel_panel_detect(dev);
fe16d949
CW		 2264 if (status == connector_status_unknown)
2265 status = connector_status_connected;
2266 return status;
2267 }
01cb9ea6 2268
1b469639
DL		 2269 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2270 return connector_status_disconnected;
2271
26d61aad 2272 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2273}
2274
a4fc5ed6 2275static enum drm_connector_status
a9756bb5 2276g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2277{
30add22d 2278 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2279 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2280 uint32_t bit;
5eb08b69 2281
ea5b213a 2282 switch (intel_dp->output_reg) {
a4fc5ed6 2283 case DP_B:
10f76a38 2284 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2285 break;
2286 case DP_C:
10f76a38 2287 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2288 break;
2289 case DP_D:
10f76a38 2290 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2291 break;
2292 default:
2293 return connector_status_unknown;
2294 }
2295
10f76a38 2296 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2297 return connector_status_disconnected;
2298
26d61aad 2299 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2300}
2301
8c241fef
KP		 2302static struct edid *
2303intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2304{
9cd300e0 2305 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2306
9cd300e0
JN		 2307 /* use cached edid if we have one */
2308 if (intel_connector->edid) {
2309 struct edid *edid;
2310 int size;
2311
2312 /* invalid edid */
2313 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2314 return NULL;
2315
9cd300e0 2316 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2317 edid = kmalloc(size, GFP_KERNEL);
2318 if (!edid)
2319 return NULL;
2320
9cd300e0 2321 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2322 return edid;
2323 }
8c241fef 2324
9cd300e0 2325 return drm_get_edid(connector, adapter);
8c241fef
KP		 2326}
2327
2328static int
2329intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2330{
9cd300e0 2331 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2332
9cd300e0
JN		 2333 /* use cached edid if we have one */
2334 if (intel_connector->edid) {
2335 /* invalid edid */
2336 if (IS_ERR(intel_connector->edid))
2337 return 0;
2338
2339 return intel_connector_update_modes(connector,
2340 intel_connector->edid);
d6f24d0f
JB		 2341 }
2342
9cd300e0 2343 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2344}
2345
a9756bb5
ZW		 2346static enum drm_connector_status
2347intel_dp_detect(struct drm_connector *connector, bool force)
2348{
2349 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2350 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2351 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2352 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2353 enum drm_connector_status status;
2354 struct edid *edid = NULL;
2355
2356 intel_dp->has_audio = false;
2357
2358 if (HAS_PCH_SPLIT(dev))
2359 status = ironlake_dp_detect(intel_dp);
2360 else
2361 status = g4x_dp_detect(intel_dp);
1b9be9d0 2362
a9756bb5
ZW		 2363 if (status != connector_status_connected)
2364 return status;
2365
0d198328
AJ		 2366 intel_dp_probe_oui(intel_dp);
2367
c3e5f67b
DV		 2368 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2369 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2370 } else {
8c241fef 2371 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2372 if (edid) {
2373 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2374 kfree(edid);
2375 }
a9756bb5
ZW		 2376 }
2377
d63885da
PZ		 2378 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2379 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2380 return connector_status_connected;
a4fc5ed6
KP		 2381}
2382
2383static int intel_dp_get_modes(struct drm_connector *connector)
2384{
df0e9248 2385 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2386 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2387 struct drm_device *dev = connector->dev;
32f9d658 2388 int ret;
a4fc5ed6
KP		 2389
2390 /* We should parse the EDID data and find out if it has an audio sink
2391 */
2392
8c241fef 2393 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2394 if (ret)
32f9d658
ZW		 2395 return ret;
2396
f8779fda 2397 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2398 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2399 struct drm_display_mode *mode;
dd06f90e
JN		 2400 mode = drm_mode_duplicate(dev,
2401 intel_connector->panel.fixed_mode);
f8779fda 2402 if (mode) {
32f9d658
ZW		 2403 drm_mode_probed_add(connector, mode);
2404 return 1;
2405 }
2406 }
2407 return 0;
a4fc5ed6
KP		 2408}
2409
1aad7ac0
CW		 2410static bool
2411intel_dp_detect_audio(struct drm_connector *connector)
2412{
2413 struct intel_dp *intel_dp = intel_attached_dp(connector);
2414 struct edid *edid;
2415 bool has_audio = false;
2416
8c241fef 2417 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2418 if (edid) {
2419 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2420 kfree(edid);
2421 }
2422
2423 return has_audio;
2424}
2425
f684960e
CW		 2426static int
2427intel_dp_set_property(struct drm_connector *connector,
2428 struct drm_property *property,
2429 uint64_t val)
2430{
e953fd7b 2431 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2432 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2433 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2434 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2435 int ret;
2436
662595df 2437 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2438 if (ret)
2439 return ret;
2440
3f43c48d 2441 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2442 int i = val;
2443 bool has_audio;
2444
2445 if (i == intel_dp->force_audio)
f684960e
CW		 2446 return 0;
2447
1aad7ac0 2448 intel_dp->force_audio = i;
f684960e 2449
c3e5f67b 2450 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2451 has_audio = intel_dp_detect_audio(connector);
2452 else
c3e5f67b 2453 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2454
2455 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2456 return 0;
2457
1aad7ac0 2458 intel_dp->has_audio = has_audio;
f684960e
CW		 2459 goto done;
2460 }
2461
e953fd7b
CW		 2462 if (property == dev_priv->broadcast_rgb_property) {
2463 if (val == !!intel_dp->color_range)
2464 return 0;
2465
2466 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2467 goto done;
2468 }
2469
53b41837
YN		 2470 if (is_edp(intel_dp) &&
2471 property == connector->dev->mode_config.scaling_mode_property) {
2472 if (val == DRM_MODE_SCALE_NONE) {
2473 DRM_DEBUG_KMS("no scaling not supported\n");
2474 return -EINVAL;
2475 }
2476
2477 if (intel_connector->panel.fitting_mode == val) {
2478 /* the eDP scaling property is not changed */
2479 return 0;
2480 }
2481 intel_connector->panel.fitting_mode = val;
2482
2483 goto done;
2484 }
2485
f684960e
CW		 2486 return -EINVAL;
2487
2488done:
da63a9f2
PZ		 2489 if (intel_encoder->base.crtc) {
2490 struct drm_crtc *crtc = intel_encoder->base.crtc;
a6778b3c
DV		 2491 intel_set_mode(crtc, &crtc->mode,
2492 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2493 }
2494
2495 return 0;
2496}
2497
a4fc5ed6 2498static void
0206e353 2499intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2500{
aaa6fd2a 2501 struct drm_device *dev = connector->dev;
be3cd5e3 2502 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2503 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2504
9cd300e0
JN		 2505 if (!IS_ERR_OR_NULL(intel_connector->edid))
2506 kfree(intel_connector->edid);
2507
1d508706 2508 if (is_edp(intel_dp)) {
aaa6fd2a 2509 intel_panel_destroy_backlight(dev);
1d508706
JN		 2510 intel_panel_fini(&intel_connector->panel);
2511 }
aaa6fd2a 2512
a4fc5ed6
KP		 2513 drm_sysfs_connector_remove(connector);
2514 drm_connector_cleanup(connector);
55f78c43 2515 kfree(connector);
a4fc5ed6
KP		 2516}
2517
00c09d70 2518void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2519{
da63a9f2
PZ		 2520 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2521 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2522
2523 i2c_del_adapter(&intel_dp->adapter);
2524 drm_encoder_cleanup(encoder);
bd943159
KP		 2525 if (is_edp(intel_dp)) {
2526 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2527 ironlake_panel_vdd_off_sync(intel_dp);
2528 }
da63a9f2 2529 kfree(intel_dig_port);
24d05927
DV		 2530}
2531
a4fc5ed6 2532static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2533 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2534 .mode_set = intel_dp_mode_set,
1f703855 2535 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2536};
2537
2538static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2539 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2540 .detect = intel_dp_detect,
2541 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2542 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2543 .destroy = intel_dp_destroy,
2544};
2545
2546static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2547 .get_modes = intel_dp_get_modes,
2548 .mode_valid = intel_dp_mode_valid,
df0e9248 2549 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2550};
2551
a4fc5ed6 2552static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2553 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2554};
2555
995b6762 2556static void
21d40d37 2557intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2558{
fa90ecef 2559 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2560
885a5014 2561 intel_dp_check_link_status(intel_dp);
c8110e52 2562}
6207937d 2563
e3421a18
ZW		 2564/* Return which DP Port should be selected for Transcoder DP control */
2565int
0206e353 2566intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2567{
2568 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2569 struct intel_encoder *intel_encoder;
2570 struct intel_dp *intel_dp;
e3421a18 2571
fa90ecef
PZ		 2572 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2573 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2574
fa90ecef
PZ		 2575 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2576 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2577 return intel_dp->output_reg;
e3421a18 2578 }
ea5b213a 2579
e3421a18
ZW		 2580 return -1;
2581}
2582
36e83a18 2583/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2584bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2585{
2586 struct drm_i915_private *dev_priv = dev->dev_private;
2587 struct child_device_config *p_child;
2588 int i;
2589
2590 if (!dev_priv->child_dev_num)
2591 return false;
2592
2593 for (i = 0; i < dev_priv->child_dev_num; i++) {
2594 p_child = dev_priv->child_dev + i;
2595
2596 if (p_child->dvo_port == PORT_IDPD &&
2597 p_child->device_type == DEVICE_TYPE_eDP)
2598 return true;
2599 }
2600 return false;
2601}
2602
f684960e
CW		 2603static void
2604intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2605{
53b41837
YN		 2606 struct intel_connector *intel_connector = to_intel_connector(connector);
2607
3f43c48d 2608 intel_attach_force_audio_property(connector);
e953fd7b 2609 intel_attach_broadcast_rgb_property(connector);
53b41837
YN		 2610
2611 if (is_edp(intel_dp)) {
2612 drm_mode_create_scaling_mode_property(connector->dev);
2613 drm_connector_attach_property(
2614 connector,
2615 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2616 DRM_MODE_SCALE_ASPECT);
2617 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2618 }
f684960e
CW		 2619}
2620
67a54566
DV		 2621static void
2622intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2623 struct intel_dp *intel_dp)
2624{
2625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 struct edp_power_seq cur, vbt, spec, final;
2627 u32 pp_on, pp_off, pp_div, pp;
2628
2629 /* Workaround: Need to write PP_CONTROL with the unlock key as
2630 * the very first thing. */
2631 pp = ironlake_get_pp_control(dev_priv);
2632 I915_WRITE(PCH_PP_CONTROL, pp);
2633
2634 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2635 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2636 pp_div = I915_READ(PCH_PP_DIVISOR);
2637
2638 /* Pull timing values out of registers */
2639 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2640 PANEL_POWER_UP_DELAY_SHIFT;
2641
2642 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2643 PANEL_LIGHT_ON_DELAY_SHIFT;
2644
2645 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2646 PANEL_LIGHT_OFF_DELAY_SHIFT;
2647
2648 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2649 PANEL_POWER_DOWN_DELAY_SHIFT;
2650
2651 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2652 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2653
2654 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2655 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2656
2657 vbt = dev_priv->edp.pps;
2658
2659 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2660 * our hw here, which are all in 100usec. */
2661 spec.t1_t3 = 210 * 10;
2662 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2663 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2664 spec.t10 = 500 * 10;
2665 /* This one is special and actually in units of 100ms, but zero
2666 * based in the hw (so we need to add 100 ms). But the sw vbt
2667 * table multiplies it with 1000 to make it in units of 100usec,
2668 * too. */
2669 spec.t11_t12 = (510 + 100) * 10;
2670
2671 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2672 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2673
2674 /* Use the max of the register settings and vbt. If both are
2675 * unset, fall back to the spec limits. */
2676#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2677 spec.field : \
2678 max(cur.field, vbt.field))
2679 assign_final(t1_t3);
2680 assign_final(t8);
2681 assign_final(t9);
2682 assign_final(t10);
2683 assign_final(t11_t12);
2684#undef assign_final
2685
2686#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2687 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2688 intel_dp->backlight_on_delay = get_delay(t8);
2689 intel_dp->backlight_off_delay = get_delay(t9);
2690 intel_dp->panel_power_down_delay = get_delay(t10);
2691 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2692#undef get_delay
2693
2694 /* And finally store the new values in the power sequencer. */
2695 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2696 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2697 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2698 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2699 /* Compute the divisor for the pp clock, simply match the Bspec
2700 * formula. */
2701 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2702 << PP_REFERENCE_DIVIDER_SHIFT;
2703 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2704 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2705
2706 /* Haswell doesn't have any port selection bits for the panel
2707 * power sequencer any more. */
2708 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2709 if (is_cpu_edp(intel_dp))
2710 pp_on |= PANEL_POWER_PORT_DP_A;
2711 else
2712 pp_on |= PANEL_POWER_PORT_DP_D;
2713 }
2714
2715 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2716 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2717 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2718
2719
2720 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2721 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2722 intel_dp->panel_power_cycle_delay);
2723
2724 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2725 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2726
2727 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2728 I915_READ(PCH_PP_ON_DELAYS),
2729 I915_READ(PCH_PP_OFF_DELAYS),
2730 I915_READ(PCH_PP_DIVISOR));
f684960e
CW		 2731}
2732
a4fc5ed6 2733void
f0fec3f2
PZ		 2734intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2735 struct intel_connector *intel_connector)
a4fc5ed6 2736{
f0fec3f2
PZ		 2737 struct drm_connector *connector = &intel_connector->base;
2738 struct intel_dp *intel_dp = &intel_dig_port->dp;
2739 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2740 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2741 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2742 struct drm_display_mode *fixed_mode = NULL;
174edf1f 2743 enum port port = intel_dig_port->port;
5eb08b69 2744 const char *name = NULL;
b329530c 2745 int type;
a4fc5ed6 2746
0767935e
DV		 2747 /* Preserve the current hw state. */
2748 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2749 intel_dp->attached_connector = intel_connector;
3d3dc149 2750
f0fec3f2 2751 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2752 if (intel_dpd_is_edp(dev))
ea5b213a 2753 intel_dp->is_pch_edp = true;
b329530c 2754
19c03924
GB		 2755 /*
2756 * FIXME : We need to initialize built-in panels before external panels.
2757 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2758 */
f0fec3f2 2759 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2760 type = DRM_MODE_CONNECTOR_eDP;
2761 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2762 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2763 type = DRM_MODE_CONNECTOR_eDP;
2764 intel_encoder->type = INTEL_OUTPUT_EDP;
2765 } else {
00c09d70
PZ		 2766 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2767 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2768 * rewrite it.
2769 */
b329530c 2770 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2771 }
2772
b329530c 2773 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2774 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2775
eb1f8e4f 2776 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2777 connector->interlace_allowed = true;
2778 connector->doublescan_allowed = 0;
2779
f0fec3f2
PZ		 2780 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2781 ironlake_panel_vdd_work);
a4fc5ed6 2782
df0e9248 2783 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2784 drm_sysfs_connector_add(connector);
2785
affa9354 2786 if (HAS_DDI(dev))
bcbc889b
PZ		 2787 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2788 else
2789 intel_connector->get_hw_state = intel_connector_get_hw_state;
2790
e8cb4558 2791
a4fc5ed6 2792 /* Set up the DDC bus. */
ab9d7c30
PZ		 2793 switch (port) {
2794 case PORT_A:
2795 name = "DPDDC-A";
2796 break;
2797 case PORT_B:
2798 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2799 name = "DPDDC-B";
2800 break;
2801 case PORT_C:
2802 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2803 name = "DPDDC-C";
2804 break;
2805 case PORT_D:
2806 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2807 name = "DPDDC-D";
2808 break;
2809 default:
2810 WARN(1, "Invalid port %c\n", port_name(port));
2811 break;
5eb08b69
ZW		 2812 }
2813
67a54566
DV		 2814 if (is_edp(intel_dp))
2815 intel_dp_init_panel_power_sequencer(dev, intel_dp);
c1f05264
DA		 2816
2817 intel_dp_i2c_init(intel_dp, intel_connector, name);
2818
67a54566 2819 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2820 if (is_edp(intel_dp)) {
2821 bool ret;
f8779fda 2822 struct drm_display_mode *scan;
c1f05264 2823 struct edid *edid;
5d613501
JB		 2824
2825 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2826 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2827 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2828
59f3e272 2829 if (ret) {
7183dc29
JB		 2830 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2831 dev_priv->no_aux_handshake =
2832 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2833 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2834 } else {
3d3dc149 2835 /* if this fails, presume the device is a ghost */
48898b03 2836 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2837 intel_dp_encoder_destroy(&intel_encoder->base);
2838 intel_dp_destroy(connector);
3d3dc149 2839 return;
89667383 2840 }
89667383 2841
d6f24d0f
JB		 2842 ironlake_edp_panel_vdd_on(intel_dp);
2843 edid = drm_get_edid(connector, &intel_dp->adapter);
2844 if (edid) {
9cd300e0
JN		 2845 if (drm_add_edid_modes(connector, edid)) {
2846 drm_mode_connector_update_edid_property(connector, edid);
2847 drm_edid_to_eld(connector, edid);
2848 } else {
2849 kfree(edid);
2850 edid = ERR_PTR(-EINVAL);
2851 }
2852 } else {
2853 edid = ERR_PTR(-ENOENT);
d6f24d0f 2854 }
9cd300e0 2855 intel_connector->edid = edid;
f8779fda
JN		 2856
2857 /* prefer fixed mode from EDID if available */
2858 list_for_each_entry(scan, &connector->probed_modes, head) {
2859 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2860 fixed_mode = drm_mode_duplicate(dev, scan);
2861 break;
2862 }
d6f24d0f 2863 }
f8779fda
JN		 2864
2865 /* fallback to VBT if available for eDP */
2866 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2867 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2868 if (fixed_mode)
2869 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2870 }
f8779fda 2871
d6f24d0f
JB		 2872 ironlake_edp_panel_vdd_off(intel_dp, false);
2873 }
552fb0b7 2874
4d926461 2875 if (is_edp(intel_dp)) {
dd06f90e 2876 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2877 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2878 }
2879
f684960e
CW		 2880 intel_dp_add_properties(intel_dp, connector);
2881
a4fc5ed6
KP		 2882 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2883 * 0xd. Failure to do so will result in spurious interrupts being
2884 * generated on the port when a cable is not attached.
2885 */
2886 if (IS_G4X(dev) && !IS_GM45(dev)) {
2887 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2888 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2889 }
2890}
f0fec3f2
PZ		 2891
2892void
2893intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2894{
2895 struct intel_digital_port *intel_dig_port;
2896 struct intel_encoder *intel_encoder;
2897 struct drm_encoder *encoder;
2898 struct intel_connector *intel_connector;
2899
2900 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2901 if (!intel_dig_port)
2902 return;
2903
2904 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2905 if (!intel_connector) {
2906 kfree(intel_dig_port);
2907 return;
2908 }
2909
2910 intel_encoder = &intel_dig_port->base;
2911 encoder = &intel_encoder->base;
2912
2913 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2914 DRM_MODE_ENCODER_TMDS);
00c09d70 2915 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2916
00c09d70
PZ		 2917 intel_encoder->enable = intel_enable_dp;
2918 intel_encoder->pre_enable = intel_pre_enable_dp;
2919 intel_encoder->disable = intel_disable_dp;
2920 intel_encoder->post_disable = intel_post_disable_dp;
2921 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2922
174edf1f 2923 intel_dig_port->port = port;
f0fec3f2
PZ		 2924 intel_dig_port->dp.output_reg = output_reg;
2925
00c09d70 2926 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2927 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2928 intel_encoder->cloneable = false;
2929 intel_encoder->hot_plug = intel_dp_hot_plug;
2930
2931 intel_dp_init_connector(intel_dig_port, intel_connector);
2932}
Linux 6.x block layer and io_uring tree(s)