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drm/i915: Don't kick the power seqeuncer just to check if we have vdd/panel power
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a4fc5ed6 117
0e32b39c 118int
ea5b213a 119intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 120{
7183dc29 121 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 122 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 123
124 switch (max_link_bw) {
125 case DP_LINK_BW_1_62:
126 case DP_LINK_BW_2_7:
127 break;
d4eead50 128 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 129 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
130 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 131 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
132 max_link_bw = DP_LINK_BW_5_4;
133 else
134 max_link_bw = DP_LINK_BW_2_7;
d4eead50 135 break;
a4fc5ed6 136 default:
d4eead50
ID		 137 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw);
a4fc5ed6
KP		 139 max_link_bw = DP_LINK_BW_1_62;
140 break;
141 }
142 return max_link_bw;
143}
144
eeb6324d
PZ		 145static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
146{
147 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
148 struct drm_device *dev = intel_dig_port->base.base.dev;
149 u8 source_max, sink_max;
150
151 source_max = 4;
152 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
153 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
154 source_max = 2;
155
156 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
157
158 return min(source_max, sink_max);
159}
160
cd9dde44
AJ		 161/*
162 * The units on the numbers in the next two are... bizarre. Examples will
163 * make it clearer; this one parallels an example in the eDP spec.
164 *
165 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 *
167 * 270000 * 1 * 8 / 10 == 216000
168 *
169 * The actual data capacity of that configuration is 2.16Gbit/s, so the
170 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
171 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
172 * 119000. At 18bpp that's 2142000 kilobits per second.
173 *
174 * Thus the strange-looking division by 10 in intel_dp_link_required, to
175 * get the result in decakilobits instead of kilobits.
176 */
177
a4fc5ed6 178static int
c898261c 179intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 180{
cd9dde44 181 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 182}
183
fe27d53e
DA		 184static int
185intel_dp_max_data_rate(int max_link_clock, int max_lanes)
186{
187 return (max_link_clock * max_lanes * 8) / 10;
188}
189
c19de8eb 190static enum drm_mode_status
a4fc5ed6
KP		 191intel_dp_mode_valid(struct drm_connector *connector,
192 struct drm_display_mode *mode)
193{
df0e9248 194 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 195 struct intel_connector *intel_connector = to_intel_connector(connector);
196 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 197 int target_clock = mode->clock;
198 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 199
dd06f90e
JN		 200 if (is_edp(intel_dp) && fixed_mode) {
201 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 202 return MODE_PANEL;
203
dd06f90e 204 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 205 return MODE_PANEL;
03afc4a2
DV		 206
207 target_clock = fixed_mode->clock;
7de56f43
ZY		 208 }
209
36008365 210 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 211 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 212
213 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
214 mode_rate = intel_dp_link_required(target_clock, 18);
215
216 if (mode_rate > max_rate)
c4867936 217 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 218
219 if (mode->clock < 10000)
220 return MODE_CLOCK_LOW;
221
0af78a2b
DV		 222 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
223 return MODE_H_ILLEGAL;
224
a4fc5ed6
KP		 225 return MODE_OK;
226}
227
228static uint32_t
5ca476f8 229pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 230{
231 int i;
232 uint32_t v = 0;
233
234 if (src_bytes > 4)
235 src_bytes = 4;
236 for (i = 0; i < src_bytes; i++)
237 v |= ((uint32_t) src[i]) << ((3-i) * 8);
238 return v;
239}
240
241static void
242unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
331 uint32_t DP;
332
333 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
334 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
335 pipe_name(pipe), port_name(intel_dig_port->port)))
336 return;
337
338 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
339 pipe_name(pipe), port_name(intel_dig_port->port));
340
341 /* Preserve the BIOS-computed detected bit. This is
342 * supposed to be read-only.
343 */
344 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
345 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
346 DP |= DP_PORT_WIDTH(1);
347 DP |= DP_LINK_TRAIN_PAT_1;
348
349 if (IS_CHERRYVIEW(dev))
350 DP |= DP_PIPE_SELECT_CHV(pipe);
351 else if (pipe == PIPE_B)
352 DP |= DP_PIPEB_SELECT;
353
354 /*
355 * Similar magic as in intel_dp_enable_port().
356 * We _must_ do this port enable + disable trick
357 * to make this power seqeuencer lock onto the port.
358 * Otherwise even VDD force bit won't work.
359 */
360 I915_WRITE(intel_dp->output_reg, DP);
361 POSTING_READ(intel_dp->output_reg);
362
363 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
364 POSTING_READ(intel_dp->output_reg);
365
366 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
367 POSTING_READ(intel_dp->output_reg);
368}
369
bf13e81b
JN		 370static enum pipe
371vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
372{
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 376 struct intel_encoder *encoder;
377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
bf13e81b 378
e39b999a 379 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 380
a4a5d2f8
VS		 381 if (intel_dp->pps_pipe != INVALID_PIPE)
382 return intel_dp->pps_pipe;
383
384 /*
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
387 */
388 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
389 base.head) {
390 struct intel_dp *tmp;
391
392 if (encoder->type != INTEL_OUTPUT_EDP)
393 continue;
394
395 tmp = enc_to_intel_dp(&encoder->base);
396
397 if (tmp->pps_pipe != INVALID_PIPE)
398 pipes &= ~(1 << tmp->pps_pipe);
399 }
400
401 /*
402 * Didn't find one. This should not happen since there
403 * are two power sequencers and up to two eDP ports.
404 */
405 if (WARN_ON(pipes == 0))
406 return PIPE_A;
407
408 intel_dp->pps_pipe = ffs(pipes) - 1;
409
410 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
411 pipe_name(intel_dp->pps_pipe),
412 port_name(intel_dig_port->port));
413
414 /* init power sequencer on this pipe and port */
36b5f425
VS		 415 intel_dp_init_panel_power_sequencer(dev, intel_dp);
416 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 417
961a0db0
VS		 418 /*
419 * Even vdd force doesn't work until we've made
420 * the power sequencer lock in on the port.
421 */
422 vlv_power_sequencer_kick(intel_dp);
423
a4a5d2f8
VS		 424 return intel_dp->pps_pipe;
425}
426
6491ab27
VS		 427typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
428 enum pipe pipe);
429
430static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
431 enum pipe pipe)
432{
433 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
434}
435
436static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
437 enum pipe pipe)
438{
439 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
440}
441
442static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
443 enum pipe pipe)
444{
445 return true;
446}
bf13e81b 447
a4a5d2f8 448static enum pipe
6491ab27
VS		 449vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
450 enum port port,
451 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 452{
453 enum pipe pipe;
bf13e81b 454
bf13e81b
JN		 455 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
456 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
457 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 458
459 if (port_sel != PANEL_PORT_SELECT_VLV(port))
460 continue;
461
6491ab27
VS		 462 if (!pipe_check(dev_priv, pipe))
463 continue;
464
a4a5d2f8 465 return pipe;
bf13e81b
JN		 466 }
467
a4a5d2f8
VS		 468 return INVALID_PIPE;
469}
470
471static void
472vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
473{
474 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
475 struct drm_device *dev = intel_dig_port->base.base.dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 477 enum port port = intel_dig_port->port;
478
479 lockdep_assert_held(&dev_priv->pps_mutex);
480
481 /* try to find a pipe with this port selected */
6491ab27
VS		 482 /* first pick one where the panel is on */
483 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
484 vlv_pipe_has_pp_on);
485 /* didn't find one? pick one where vdd is on */
486 if (intel_dp->pps_pipe == INVALID_PIPE)
487 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
488 vlv_pipe_has_vdd_on);
489 /* didn't find one? pick one with just the correct port */
490 if (intel_dp->pps_pipe == INVALID_PIPE)
491 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
492 vlv_pipe_any);
a4a5d2f8
VS		 493
494 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
495 if (intel_dp->pps_pipe == INVALID_PIPE) {
496 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
497 port_name(port));
498 return;
bf13e81b
JN		 499 }
500
a4a5d2f8
VS		 501 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
502 port_name(port), pipe_name(intel_dp->pps_pipe));
503
36b5f425
VS		 504 intel_dp_init_panel_power_sequencer(dev, intel_dp);
505 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 506}
507
773538e8
VS		 508void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
509{
510 struct drm_device *dev = dev_priv->dev;
511 struct intel_encoder *encoder;
512
513 if (WARN_ON(!IS_VALLEYVIEW(dev)))
514 return;
515
516 /*
517 * We can't grab pps_mutex here due to deadlock with power_domain
518 * mutex when power_domain functions are called while holding pps_mutex.
519 * That also means that in order to use pps_pipe the code needs to
520 * hold both a power domain reference and pps_mutex, and the power domain
521 * reference get/put must be done while _not_ holding pps_mutex.
522 * pps_{lock,unlock}() do these steps in the correct order, so one
523 * should use them always.
524 */
525
526 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
527 struct intel_dp *intel_dp;
528
529 if (encoder->type != INTEL_OUTPUT_EDP)
530 continue;
531
532 intel_dp = enc_to_intel_dp(&encoder->base);
533 intel_dp->pps_pipe = INVALID_PIPE;
534 }
bf13e81b
JN		 535}
536
537static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
538{
539 struct drm_device *dev = intel_dp_to_dev(intel_dp);
540
541 if (HAS_PCH_SPLIT(dev))
542 return PCH_PP_CONTROL;
543 else
544 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
545}
546
547static u32 _pp_stat_reg(struct intel_dp *intel_dp)
548{
549 struct drm_device *dev = intel_dp_to_dev(intel_dp);
550
551 if (HAS_PCH_SPLIT(dev))
552 return PCH_PP_STATUS;
553 else
554 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
555}
556
01527b31
CT		 557/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
558 This function only applicable when panel PM state is not to be tracked */
559static int edp_notify_handler(struct notifier_block *this, unsigned long code,
560 void *unused)
561{
562 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
563 edp_notifier);
564 struct drm_device *dev = intel_dp_to_dev(intel_dp);
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 u32 pp_div;
567 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 568
569 if (!is_edp(intel_dp) || code != SYS_RESTART)
570 return 0;
571
773538e8 572 pps_lock(intel_dp);
e39b999a 573
01527b31 574 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 575 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
576
01527b31
CT		 577 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
578 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
579 pp_div = I915_READ(pp_div_reg);
580 pp_div &= PP_REFERENCE_DIVIDER_MASK;
581
582 /* 0x1F write to PP_DIV_REG sets max cycle delay */
583 I915_WRITE(pp_div_reg, pp_div | 0x1F);
584 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
585 msleep(intel_dp->panel_power_cycle_delay);
586 }
587
773538e8 588 pps_unlock(intel_dp);
e39b999a 589
01527b31
CT		 590 return 0;
591}
592
4be73780 593static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 594{
30add22d 595 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 596 struct drm_i915_private *dev_priv = dev->dev_private;
597
e39b999a
VS		 598 lockdep_assert_held(&dev_priv->pps_mutex);
599
9a42356b
VS		 600 if (IS_VALLEYVIEW(dev) &&
601 intel_dp->pps_pipe == INVALID_PIPE)
602 return false;
603
bf13e81b 604 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 605}
606
4be73780 607static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 608{
30add22d 609 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 610 struct drm_i915_private *dev_priv = dev->dev_private;
611
e39b999a
VS		 612 lockdep_assert_held(&dev_priv->pps_mutex);
613
9a42356b
VS		 614 if (IS_VALLEYVIEW(dev) &&
615 intel_dp->pps_pipe == INVALID_PIPE)
616 return false;
617
773538e8 618 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 619}
620
9b984dae
KP		 621static void
622intel_dp_check_edp(struct intel_dp *intel_dp)
623{
30add22d 624 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 625 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 626
9b984dae
KP		 627 if (!is_edp(intel_dp))
628 return;
453c5420 629
4be73780 630 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 631 WARN(1, "eDP powered off while attempting aux channel communication.\n");
632 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 633 I915_READ(_pp_stat_reg(intel_dp)),
634 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 635 }
636}
637
9ee32fea
DV		 638static uint32_t
639intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
640{
641 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
642 struct drm_device *dev = intel_dig_port->base.base.dev;
643 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 644 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 645 uint32_t status;
646 bool done;
647
ef04f00d 648#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 649 if (has_aux_irq)
b18ac466 650 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 651 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 652 else
653 done = wait_for_atomic(C, 10) == 0;
654 if (!done)
655 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
656 has_aux_irq);
657#undef C
658
659 return status;
660}
661
ec5b01dd 662static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 663{
174edf1f
PZ		 664 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
665 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 666
ec5b01dd
DL		 667 /*
668 * The clock divider is based off the hrawclk, and would like to run at
669 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 670 */
ec5b01dd
DL		 671 return index ? 0 : intel_hrawclk(dev) / 2;
672}
673
674static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
675{
676 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
677 struct drm_device *dev = intel_dig_port->base.base.dev;
678
679 if (index)
680 return 0;
681
682 if (intel_dig_port->port == PORT_A) {
683 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 684 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 685 else
b84a1cf8 686 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 687 } else {
688 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
689 }
690}
691
692static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
693{
694 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
695 struct drm_device *dev = intel_dig_port->base.base.dev;
696 struct drm_i915_private *dev_priv = dev->dev_private;
697
698 if (intel_dig_port->port == PORT_A) {
699 if (index)
700 return 0;
701 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 702 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
703 /* Workaround for non-ULT HSW */
bc86625a
CW		 704 switch (index) {
705 case 0: return 63;
706 case 1: return 72;
707 default: return 0;
708 }
ec5b01dd 709 } else {
bc86625a 710 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 711 }
b84a1cf8
RV		 712}
713
ec5b01dd
DL		 714static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
715{
716 return index ? 0 : 100;
717}
718
b6b5e383
DL		 719static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
720{
721 /*
722 * SKL doesn't need us to program the AUX clock divider (Hardware will
723 * derive the clock from CDCLK automatically). We still implement the
724 * get_aux_clock_divider vfunc to plug-in into the existing code.
725 */
726 return index ? 0 : 1;
727}
728
5ed12a19
DL		 729static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
730 bool has_aux_irq,
731 int send_bytes,
732 uint32_t aux_clock_divider)
733{
734 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
735 struct drm_device *dev = intel_dig_port->base.base.dev;
736 uint32_t precharge, timeout;
737
738 if (IS_GEN6(dev))
739 precharge = 3;
740 else
741 precharge = 5;
742
743 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
744 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
745 else
746 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
747
748 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 749 DP_AUX_CH_CTL_DONE |
5ed12a19 750 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 751 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 752 timeout |
788d4433 753 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 754 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
755 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 756 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 757}
758
b9ca5fad
DL		 759static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
760 bool has_aux_irq,
761 int send_bytes,
762 uint32_t unused)
763{
764 return DP_AUX_CH_CTL_SEND_BUSY |
765 DP_AUX_CH_CTL_DONE |
766 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
767 DP_AUX_CH_CTL_TIME_OUT_ERROR |
768 DP_AUX_CH_CTL_TIME_OUT_1600us |
769 DP_AUX_CH_CTL_RECEIVE_ERROR |
770 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
771 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
772}
773
b84a1cf8
RV		 774static int
775intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 776 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 777 uint8_t *recv, int recv_size)
778{
779 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
780 struct drm_device *dev = intel_dig_port->base.base.dev;
781 struct drm_i915_private *dev_priv = dev->dev_private;
782 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
783 uint32_t ch_data = ch_ctl + 4;
bc86625a 784 uint32_t aux_clock_divider;
b84a1cf8
RV		 785 int i, ret, recv_bytes;
786 uint32_t status;
5ed12a19 787 int try, clock = 0;
4e6b788c 788 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 789 bool vdd;
790
773538e8 791 pps_lock(intel_dp);
e39b999a 792
72c3500a
VS		 793 /*
794 * We will be called with VDD already enabled for dpcd/edid/oui reads.
795 * In such cases we want to leave VDD enabled and it's up to upper layers
796 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
797 * ourselves.
798 */
1e0560e0 799 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 800
801 /* dp aux is extremely sensitive to irq latency, hence request the
802 * lowest possible wakeup latency and so prevent the cpu from going into
803 * deep sleep states.
804 */
805 pm_qos_update_request(&dev_priv->pm_qos, 0);
806
807 intel_dp_check_edp(intel_dp);
5eb08b69 808
c67a470b
PZ		 809 intel_aux_display_runtime_get(dev_priv);
810
11bee43e
JB		 811 /* Try to wait for any previous AUX channel activity */
812 for (try = 0; try < 3; try++) {
ef04f00d 813 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 814 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
815 break;
816 msleep(1);
817 }
818
819 if (try == 3) {
820 WARN(1, "dp_aux_ch not started status 0x%08x\n",
821 I915_READ(ch_ctl));
9ee32fea
DV		 822 ret = -EBUSY;
823 goto out;
4f7f7b7e
CW		 824 }
825
46a5ae9f
PZ		 826 /* Only 5 data registers! */
827 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
828 ret = -E2BIG;
829 goto out;
830 }
831
ec5b01dd 832 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 833 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
834 has_aux_irq,
835 send_bytes,
836 aux_clock_divider);
5ed12a19 837
bc86625a
CW		 838 /* Must try at least 3 times according to DP spec */
839 for (try = 0; try < 5; try++) {
840 /* Load the send data into the aux channel data registers */
841 for (i = 0; i < send_bytes; i += 4)
842 I915_WRITE(ch_data + i,
843 pack_aux(send + i, send_bytes - i));
844
845 /* Send the command and wait for it to complete */
5ed12a19 846 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 847
848 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
849
850 /* Clear done status and any errors */
851 I915_WRITE(ch_ctl,
852 status |
853 DP_AUX_CH_CTL_DONE |
854 DP_AUX_CH_CTL_TIME_OUT_ERROR |
855 DP_AUX_CH_CTL_RECEIVE_ERROR);
856
857 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
858 DP_AUX_CH_CTL_RECEIVE_ERROR))
859 continue;
860 if (status & DP_AUX_CH_CTL_DONE)
861 break;
862 }
4f7f7b7e 863 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 864 break;
865 }
866
a4fc5ed6 867 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 868 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 869 ret = -EBUSY;
870 goto out;
a4fc5ed6
KP		 871 }
872
873 /* Check for timeout or receive error.
874 * Timeouts occur when the sink is not connected
875 */
a5b3da54 876 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 877 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 878 ret = -EIO;
879 goto out;
a5b3da54 880 }
1ae8c0a5
KP		 881
882 /* Timeouts occur when the device isn't connected, so they're
883 * "normal" -- don't fill the kernel log with these */
a5b3da54 884 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 885 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 886 ret = -ETIMEDOUT;
887 goto out;
a4fc5ed6
KP		 888 }
889
890 /* Unload any bytes sent back from the other side */
891 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
892 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 893 if (recv_bytes > recv_size)
894 recv_bytes = recv_size;
0206e353 895
4f7f7b7e
CW		 896 for (i = 0; i < recv_bytes; i += 4)
897 unpack_aux(I915_READ(ch_data + i),
898 recv + i, recv_bytes - i);
a4fc5ed6 899
9ee32fea
DV		 900 ret = recv_bytes;
901out:
902 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 903 intel_aux_display_runtime_put(dev_priv);
9ee32fea 904
884f19e9
JN		 905 if (vdd)
906 edp_panel_vdd_off(intel_dp, false);
907
773538e8 908 pps_unlock(intel_dp);
e39b999a 909
9ee32fea 910 return ret;
a4fc5ed6
KP		 911}
912
a6c8aff0
JN		 913#define BARE_ADDRESS_SIZE 3
914#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 915static ssize_t
916intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 917{
9d1a1031
JN		 918 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
919 uint8_t txbuf[20], rxbuf[20];
920 size_t txsize, rxsize;
a4fc5ed6 921 int ret;
a4fc5ed6 922
9d1a1031
JN		 923 txbuf[0] = msg->request << 4;
924 txbuf[1] = msg->address >> 8;
925 txbuf[2] = msg->address & 0xff;
926 txbuf[3] = msg->size - 1;
46a5ae9f 927
9d1a1031
JN		 928 switch (msg->request & ~DP_AUX_I2C_MOT) {
929 case DP_AUX_NATIVE_WRITE:
930 case DP_AUX_I2C_WRITE:
a6c8aff0 931 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 932 rxsize = 1;
f51a44b9 933
9d1a1031
JN		 934 if (WARN_ON(txsize > 20))
935 return -E2BIG;
a4fc5ed6 936
9d1a1031 937 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 938
9d1a1031
JN		 939 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
940 if (ret > 0) {
941 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 942
9d1a1031
JN		 943 /* Return payload size. */
944 ret = msg->size;
945 }
946 break;
46a5ae9f 947
9d1a1031
JN		 948 case DP_AUX_NATIVE_READ:
949 case DP_AUX_I2C_READ:
a6c8aff0 950 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 951 rxsize = msg->size + 1;
a4fc5ed6 952
9d1a1031
JN		 953 if (WARN_ON(rxsize > 20))
954 return -E2BIG;
a4fc5ed6 955
9d1a1031
JN		 956 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
957 if (ret > 0) {
958 msg->reply = rxbuf[0] >> 4;
959 /*
960 * Assume happy day, and copy the data. The caller is
961 * expected to check msg->reply before touching it.
962 *
963 * Return payload size.
964 */
965 ret--;
966 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 967 }
9d1a1031
JN		 968 break;
969
970 default:
971 ret = -EINVAL;
972 break;
a4fc5ed6 973 }
f51a44b9 974
9d1a1031 975 return ret;
a4fc5ed6
KP		 976}
977
9d1a1031
JN		 978static void
979intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
980{
981 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 982 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
983 enum port port = intel_dig_port->port;
0b99836f 984 const char *name = NULL;
ab2c0672
DA		 985 int ret;
986
33ad6626
JN		 987 switch (port) {
988 case PORT_A:
989 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 990 name = "DPDDC-A";
ab2c0672 991 break;
33ad6626
JN		 992 case PORT_B:
993 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 994 name = "DPDDC-B";
ab2c0672 995 break;
33ad6626
JN		 996 case PORT_C:
997 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 998 name = "DPDDC-C";
ab2c0672 999 break;
33ad6626
JN		 1000 case PORT_D:
1001 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1002 name = "DPDDC-D";
33ad6626
JN		 1003 break;
1004 default:
1005 BUG();
ab2c0672
DA		 1006 }
1007
1b1aad75
DL		 1008 /*
1009 * The AUX_CTL register is usually DP_CTL + 0x10.
1010 *
1011 * On Haswell and Broadwell though:
1012 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1013 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1014 *
1015 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1016 */
1017 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1018 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1019
0b99836f 1020 intel_dp->aux.name = name;
9d1a1031
JN		 1021 intel_dp->aux.dev = dev->dev;
1022 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1023
0b99836f
JN		 1024 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1025 connector->base.kdev->kobj.name);
8316f337 1026
4f71d0cb 1027 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1028 if (ret < 0) {
4f71d0cb 1029 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1030 name, ret);
1031 return;
ab2c0672 1032 }
8a5e6aeb 1033
0b99836f
JN		 1034 ret = sysfs_create_link(&connector->base.kdev->kobj,
1035 &intel_dp->aux.ddc.dev.kobj,
1036 intel_dp->aux.ddc.dev.kobj.name);
1037 if (ret < 0) {
1038 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1039 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1040 }
a4fc5ed6
KP		 1041}
1042
80f65de3
ID		 1043static void
1044intel_dp_connector_unregister(struct intel_connector *intel_connector)
1045{
1046 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1047
0e32b39c
DA		 1048 if (!intel_connector->mst_port)
1049 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1050 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1051 intel_connector_unregister(intel_connector);
1052}
1053
0e50338c
DV		 1054static void
1055hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1056{
1057 switch (link_bw) {
1058 case DP_LINK_BW_1_62:
1059 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1060 break;
1061 case DP_LINK_BW_2_7:
1062 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1063 break;
1064 case DP_LINK_BW_5_4:
1065 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1066 break;
1067 }
1068}
1069
c6bb3538
DV		 1070static void
1071intel_dp_set_clock(struct intel_encoder *encoder,
1072 struct intel_crtc_config *pipe_config, int link_bw)
1073{
1074 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1075 const struct dp_link_dpll *divisor = NULL;
1076 int i, count = 0;
c6bb3538
DV		 1077
1078 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1079 divisor = gen4_dpll;
1080 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1081 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1082 divisor = pch_dpll;
1083 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1084 } else if (IS_CHERRYVIEW(dev)) {
1085 divisor = chv_dpll;
1086 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1087 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1088 divisor = vlv_dpll;
1089 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1090 }
9dd4ffdf
CML		 1091
1092 if (divisor && count) {
1093 for (i = 0; i < count; i++) {
1094 if (link_bw == divisor[i].link_bw) {
1095 pipe_config->dpll = divisor[i].dpll;
1096 pipe_config->clock_set = true;
1097 break;
1098 }
1099 }
c6bb3538
DV		 1100 }
1101}
1102
00c09d70 1103bool
5bfe2ac0
DV		 1104intel_dp_compute_config(struct intel_encoder *encoder,
1105 struct intel_crtc_config *pipe_config)
a4fc5ed6 1106{
5bfe2ac0 1107 struct drm_device *dev = encoder->base.dev;
36008365 1108 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1109 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1110 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1111 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1112 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1113 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1114 int lane_count, clock;
56071a20 1115 int min_lane_count = 1;
eeb6324d 1116 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1117 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1118 int min_clock = 0;
06ea66b6 1119 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1120 int bpp, mode_rate;
06ea66b6 1121 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1122 int link_avail, link_clock;
a4fc5ed6 1123
bc7d38a4 1124 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1125 pipe_config->has_pch_encoder = true;
1126
03afc4a2 1127 pipe_config->has_dp_encoder = true;
f769cd24 1128 pipe_config->has_drrs = false;
9ed109a7 1129 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1130
dd06f90e
JN		 1131 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1132 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1133 adjusted_mode);
2dd24552
JB		 1134 if (!HAS_PCH_SPLIT(dev))
1135 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1136 intel_connector->panel.fitting_mode);
1137 else
b074cec8
JB		 1138 intel_pch_panel_fitting(intel_crtc, pipe_config,
1139 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1140 }
1141
cb1793ce 1142 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1143 return false;
1144
083f9560
DV		 1145 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1146 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1147 max_lane_count, bws[max_clock],
1148 adjusted_mode->crtc_clock);
083f9560 1149
36008365
DV		 1150 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1151 * bpc in between. */
3e7ca985 1152 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1153 if (is_edp(intel_dp)) {
1154 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1155 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1156 dev_priv->vbt.edp_bpp);
1157 bpp = dev_priv->vbt.edp_bpp;
1158 }
1159
344c5bbc
JN		 1160 /*
1161 * Use the maximum clock and number of lanes the eDP panel
1162 * advertizes being capable of. The panels are generally
1163 * designed to support only a single clock and lane
1164 * configuration, and typically these values correspond to the
1165 * native resolution of the panel.
1166 */
1167 min_lane_count = max_lane_count;
1168 min_clock = max_clock;
7984211e 1169 }
657445fe 1170
36008365 1171 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1172 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1173 bpp);
36008365 1174
c6930992
DA		 1175 for (clock = min_clock; clock <= max_clock; clock++) {
1176 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1177 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1178 link_avail = intel_dp_max_data_rate(link_clock,
1179 lane_count);
1180
1181 if (mode_rate <= link_avail) {
1182 goto found;
1183 }
1184 }
1185 }
1186 }
c4867936 1187
36008365 1188 return false;
3685a8f3 1189
36008365 1190found:
55bc60db
VS		 1191 if (intel_dp->color_range_auto) {
1192 /*
1193 * See:
1194 * CEA-861-E - 5.1 Default Encoding Parameters
1195 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1196 */
18316c8c 1197 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1198 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1199 else
1200 intel_dp->color_range = 0;
1201 }
1202
3685a8f3 1203 if (intel_dp->color_range)
50f3b016 1204 pipe_config->limited_color_range = true;
a4fc5ed6 1205
36008365
DV		 1206 intel_dp->link_bw = bws[clock];
1207 intel_dp->lane_count = lane_count;
657445fe 1208 pipe_config->pipe_bpp = bpp;
ff9a6750 1209 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1210
36008365
DV		 1211 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1212 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1213 pipe_config->port_clock, bpp);
36008365
DV		 1214 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1215 mode_rate, link_avail);
a4fc5ed6 1216
03afc4a2 1217 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1218 adjusted_mode->crtc_clock,
1219 pipe_config->port_clock,
03afc4a2 1220 &pipe_config->dp_m_n);
9d1a455b 1221
439d7ac0
PB		 1222 if (intel_connector->panel.downclock_mode != NULL &&
1223 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1224 pipe_config->has_drrs = true;
439d7ac0
PB		 1225 intel_link_compute_m_n(bpp, lane_count,
1226 intel_connector->panel.downclock_mode->clock,
1227 pipe_config->port_clock,
1228 &pipe_config->dp_m2_n2);
1229 }
1230
ea155f32 1231 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1232 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1233 else
1234 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1235
03afc4a2 1236 return true;
a4fc5ed6
KP		 1237}
1238
7c62a164 1239static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1240{
7c62a164
DV		 1241 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1242 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1243 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1244 struct drm_i915_private *dev_priv = dev->dev_private;
1245 u32 dpa_ctl;
1246
ff9a6750 1247 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1248 dpa_ctl = I915_READ(DP_A);
1249 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1250
ff9a6750 1251 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1252 /* For a long time we've carried around a ILK-DevA w/a for the
1253 * 160MHz clock. If we're really unlucky, it's still required.
1254 */
1255 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1256 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1257 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1258 } else {
1259 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1260 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1261 }
1ce17038 1262
ea9b6006
DV		 1263 I915_WRITE(DP_A, dpa_ctl);
1264
1265 POSTING_READ(DP_A);
1266 udelay(500);
1267}
1268
8ac33ed3 1269static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1270{
b934223d 1271 struct drm_device *dev = encoder->base.dev;
417e822d 1272 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1273 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1274 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1275 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1276 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1277
417e822d 1278 /*
1a2eb460 1279 * There are four kinds of DP registers:
417e822d
KP		 1280 *
1281 * IBX PCH
1a2eb460
KP		 1282 * SNB CPU
1283 * IVB CPU
417e822d
KP		 1284 * CPT PCH
1285 *
1286 * IBX PCH and CPU are the same for almost everything,
1287 * except that the CPU DP PLL is configured in this
1288 * register
1289 *
1290 * CPT PCH is quite different, having many bits moved
1291 * to the TRANS_DP_CTL register instead. That
1292 * configuration happens (oddly) in ironlake_pch_enable
1293 */
9c9e7927 1294
417e822d
KP		 1295 /* Preserve the BIOS-computed detected bit. This is
1296 * supposed to be read-only.
1297 */
1298 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1299
417e822d 1300 /* Handle DP bits in common between all three register formats */
417e822d 1301 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1302 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1303
9ed109a7 1304 if (crtc->config.has_audio) {
e0dac65e 1305 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1306 pipe_name(crtc->pipe));
ea5b213a 1307 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
33d1e7c6 1308 intel_write_eld(encoder);
e0dac65e 1309 }
247d89f6 1310
417e822d 1311 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1312
bc7d38a4 1313 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1314 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1315 intel_dp->DP |= DP_SYNC_HS_HIGH;
1316 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1317 intel_dp->DP |= DP_SYNC_VS_HIGH;
1318 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1319
6aba5b6c 1320 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1321 intel_dp->DP |= DP_ENHANCED_FRAMING;
1322
7c62a164 1323 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1324 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1325 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1326 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1327
1328 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1329 intel_dp->DP |= DP_SYNC_HS_HIGH;
1330 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1331 intel_dp->DP |= DP_SYNC_VS_HIGH;
1332 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1333
6aba5b6c 1334 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1335 intel_dp->DP |= DP_ENHANCED_FRAMING;
1336
44f37d1f
CML		 1337 if (!IS_CHERRYVIEW(dev)) {
1338 if (crtc->pipe == 1)
1339 intel_dp->DP |= DP_PIPEB_SELECT;
1340 } else {
1341 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1342 }
417e822d
KP		 1343 } else {
1344 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1345 }
a4fc5ed6
KP		 1346}
1347
ffd6749d
PZ		 1348#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1349#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1350
1a5ef5b7
PZ		 1351#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1352#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1353
ffd6749d
PZ		 1354#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1355#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1356
4be73780 1357static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1358 u32 mask,
1359 u32 value)
bd943159 1360{
30add22d 1361 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1362 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1363 u32 pp_stat_reg, pp_ctrl_reg;
1364
e39b999a
VS		 1365 lockdep_assert_held(&dev_priv->pps_mutex);
1366
bf13e81b
JN		 1367 pp_stat_reg = _pp_stat_reg(intel_dp);
1368 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1369
99ea7127 1370 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1371 mask, value,
1372 I915_READ(pp_stat_reg),
1373 I915_READ(pp_ctrl_reg));
32ce697c 1374
453c5420 1375 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1376 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1377 I915_READ(pp_stat_reg),
1378 I915_READ(pp_ctrl_reg));
32ce697c 1379 }
54c136d4
CW		 1380
1381 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1382}
32ce697c 1383
4be73780 1384static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1385{
1386 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1387 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1388}
1389
4be73780 1390static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1391{
1392 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1393 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1394}
1395
4be73780 1396static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1397{
1398 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1399
1400 /* When we disable the VDD override bit last we have to do the manual
1401 * wait. */
1402 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1403 intel_dp->panel_power_cycle_delay);
1404
4be73780 1405 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1406}
1407
4be73780 1408static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1409{
1410 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1411 intel_dp->backlight_on_delay);
1412}
1413
4be73780 1414static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1415{
1416 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1417 intel_dp->backlight_off_delay);
1418}
99ea7127 1419
832dd3c1
KP		 1420/* Read the current pp_control value, unlocking the register if it
1421 * is locked
1422 */
1423
453c5420 1424static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1425{
453c5420
JB		 1426 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 u32 control;
832dd3c1 1429
e39b999a
VS		 1430 lockdep_assert_held(&dev_priv->pps_mutex);
1431
bf13e81b 1432 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1433 control &= ~PANEL_UNLOCK_MASK;
1434 control |= PANEL_UNLOCK_REGS;
1435 return control;
bd943159
KP		 1436}
1437
951468f3
VS		 1438/*
1439 * Must be paired with edp_panel_vdd_off().
1440 * Must hold pps_mutex around the whole on/off sequence.
1441 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1442 */
1e0560e0 1443static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1444{
30add22d 1445 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1447 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1448 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1449 enum intel_display_power_domain power_domain;
5d613501 1450 u32 pp;
453c5420 1451 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1452 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1453
e39b999a
VS		 1454 lockdep_assert_held(&dev_priv->pps_mutex);
1455
97af61f5 1456 if (!is_edp(intel_dp))
adddaaf4 1457 return false;
bd943159
KP		 1458
1459 intel_dp->want_panel_vdd = true;
99ea7127 1460
4be73780 1461 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1462 return need_to_disable;
b0665d57 1463
4e6e1a54
ID		 1464 power_domain = intel_display_port_power_domain(intel_encoder);
1465 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1466
b0665d57 1467 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1468
4be73780
DV		 1469 if (!edp_have_panel_power(intel_dp))
1470 wait_panel_power_cycle(intel_dp);
99ea7127 1471
453c5420 1472 pp = ironlake_get_pp_control(intel_dp);
5d613501 1473 pp |= EDP_FORCE_VDD;
ebf33b18 1474
bf13e81b
JN		 1475 pp_stat_reg = _pp_stat_reg(intel_dp);
1476 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1477
1478 I915_WRITE(pp_ctrl_reg, pp);
1479 POSTING_READ(pp_ctrl_reg);
1480 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1481 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1482 /*
1483 * If the panel wasn't on, delay before accessing aux channel
1484 */
4be73780 1485 if (!edp_have_panel_power(intel_dp)) {
bd943159 1486 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1487 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1488 }
adddaaf4
JN		 1489
1490 return need_to_disable;
1491}
1492
951468f3
VS		 1493/*
1494 * Must be paired with intel_edp_panel_vdd_off() or
1495 * intel_edp_panel_off().
1496 * Nested calls to these functions are not allowed since
1497 * we drop the lock. Caller must use some higher level
1498 * locking to prevent nested calls from other threads.
1499 */
b80d6c78 1500void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1501{
c695b6b6 1502 bool vdd;
adddaaf4 1503
c695b6b6
VS		 1504 if (!is_edp(intel_dp))
1505 return;
1506
773538e8 1507 pps_lock(intel_dp);
c695b6b6 1508 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1509 pps_unlock(intel_dp);
c695b6b6
VS		 1510
1511 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1512}
1513
4be73780 1514static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1515{
30add22d 1516 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1517 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1518 struct intel_digital_port *intel_dig_port =
1519 dp_to_dig_port(intel_dp);
1520 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1521 enum intel_display_power_domain power_domain;
5d613501 1522 u32 pp;
453c5420 1523 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1524
e39b999a 1525 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1526
15e899a0 1527 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1528
15e899a0 1529 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1530 return;
b0665d57 1531
be2c9196 1532 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1533
be2c9196
VS		 1534 pp = ironlake_get_pp_control(intel_dp);
1535 pp &= ~EDP_FORCE_VDD;
453c5420 1536
be2c9196
VS		 1537 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1538 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1539
be2c9196
VS		 1540 I915_WRITE(pp_ctrl_reg, pp);
1541 POSTING_READ(pp_ctrl_reg);
90791a5c 1542
be2c9196
VS		 1543 /* Make sure sequencer is idle before allowing subsequent activity */
1544 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1545 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1546
be2c9196
VS		 1547 if ((pp & POWER_TARGET_ON) == 0)
1548 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1549
be2c9196
VS		 1550 power_domain = intel_display_port_power_domain(intel_encoder);
1551 intel_display_power_put(dev_priv, power_domain);
bd943159 1552}
5d613501 1553
4be73780 1554static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1555{
1556 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1557 struct intel_dp, panel_vdd_work);
bd943159 1558
773538e8 1559 pps_lock(intel_dp);
15e899a0
VS		 1560 if (!intel_dp->want_panel_vdd)
1561 edp_panel_vdd_off_sync(intel_dp);
773538e8 1562 pps_unlock(intel_dp);
bd943159
KP		 1563}
1564
aba86890
ID		 1565static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1566{
1567 unsigned long delay;
1568
1569 /*
1570 * Queue the timer to fire a long time from now (relative to the power
1571 * down delay) to keep the panel power up across a sequence of
1572 * operations.
1573 */
1574 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1575 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1576}
1577
951468f3
VS		 1578/*
1579 * Must be paired with edp_panel_vdd_on().
1580 * Must hold pps_mutex around the whole on/off sequence.
1581 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1582 */
4be73780 1583static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1584{
e39b999a
VS		 1585 struct drm_i915_private *dev_priv =
1586 intel_dp_to_dev(intel_dp)->dev_private;
1587
1588 lockdep_assert_held(&dev_priv->pps_mutex);
1589
97af61f5
KP		 1590 if (!is_edp(intel_dp))
1591 return;
5d613501 1592
bd943159 1593 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1594
bd943159
KP		 1595 intel_dp->want_panel_vdd = false;
1596
aba86890 1597 if (sync)
4be73780 1598 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1599 else
1600 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1601}
1602
9f0fb5be 1603static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1604{
30add22d 1605 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1606 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1607 u32 pp;
453c5420 1608 u32 pp_ctrl_reg;
9934c132 1609
9f0fb5be
VS		 1610 lockdep_assert_held(&dev_priv->pps_mutex);
1611
97af61f5 1612 if (!is_edp(intel_dp))
bd943159 1613 return;
99ea7127
KP		 1614
1615 DRM_DEBUG_KMS("Turn eDP power on\n");
1616
4be73780 1617 if (edp_have_panel_power(intel_dp)) {
99ea7127 1618 DRM_DEBUG_KMS("eDP power already on\n");
9f0fb5be 1619 return;
99ea7127 1620 }
9934c132 1621
4be73780 1622 wait_panel_power_cycle(intel_dp);
37c6c9b0 1623
bf13e81b 1624 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1625 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1626 if (IS_GEN5(dev)) {
1627 /* ILK workaround: disable reset around power sequence */
1628 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1629 I915_WRITE(pp_ctrl_reg, pp);
1630 POSTING_READ(pp_ctrl_reg);
05ce1a49 1631 }
37c6c9b0 1632
1c0ae80a 1633 pp |= POWER_TARGET_ON;
99ea7127
KP		 1634 if (!IS_GEN5(dev))
1635 pp |= PANEL_POWER_RESET;
1636
453c5420
JB		 1637 I915_WRITE(pp_ctrl_reg, pp);
1638 POSTING_READ(pp_ctrl_reg);
9934c132 1639
4be73780 1640 wait_panel_on(intel_dp);
dce56b3c 1641 intel_dp->last_power_on = jiffies;
9934c132 1642
05ce1a49
KP		 1643 if (IS_GEN5(dev)) {
1644 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1645 I915_WRITE(pp_ctrl_reg, pp);
1646 POSTING_READ(pp_ctrl_reg);
05ce1a49 1647 }
9f0fb5be 1648}
e39b999a 1649
9f0fb5be
VS		 1650void intel_edp_panel_on(struct intel_dp *intel_dp)
1651{
1652 if (!is_edp(intel_dp))
1653 return;
1654
1655 pps_lock(intel_dp);
1656 edp_panel_on(intel_dp);
773538e8 1657 pps_unlock(intel_dp);
9934c132
JB		 1658}
1659
9f0fb5be
VS		 1660
1661static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1662{
4e6e1a54
ID		 1663 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1664 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1665 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1666 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1667 enum intel_display_power_domain power_domain;
99ea7127 1668 u32 pp;
453c5420 1669 u32 pp_ctrl_reg;
9934c132 1670
9f0fb5be
VS		 1671 lockdep_assert_held(&dev_priv->pps_mutex);
1672
97af61f5
KP		 1673 if (!is_edp(intel_dp))
1674 return;
37c6c9b0 1675
99ea7127 1676 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1677
24f3e092
JN		 1678 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1679
453c5420 1680 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1681 /* We need to switch off panel power _and_ force vdd, for otherwise some
1682 * panels get very unhappy and cease to work. */
b3064154
PJ		 1683 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1684 EDP_BLC_ENABLE);
453c5420 1685
bf13e81b 1686 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1687
849e39f5
PZ		 1688 intel_dp->want_panel_vdd = false;
1689
453c5420
JB		 1690 I915_WRITE(pp_ctrl_reg, pp);
1691 POSTING_READ(pp_ctrl_reg);
9934c132 1692
dce56b3c 1693 intel_dp->last_power_cycle = jiffies;
4be73780 1694 wait_panel_off(intel_dp);
849e39f5
PZ		 1695
1696 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1697 power_domain = intel_display_port_power_domain(intel_encoder);
1698 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1699}
e39b999a 1700
9f0fb5be
VS		 1701void intel_edp_panel_off(struct intel_dp *intel_dp)
1702{
1703 if (!is_edp(intel_dp))
1704 return;
1705
1706 pps_lock(intel_dp);
1707 edp_panel_off(intel_dp);
773538e8 1708 pps_unlock(intel_dp);
9934c132
JB		 1709}
1710
1250d107
JN		 1711/* Enable backlight in the panel power control. */
1712static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1713{
da63a9f2
PZ		 1714 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1715 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 u32 pp;
453c5420 1718 u32 pp_ctrl_reg;
32f9d658 1719
01cb9ea6
JB		 1720 /*
1721 * If we enable the backlight right away following a panel power
1722 * on, we may see slight flicker as the panel syncs with the eDP
1723 * link. So delay a bit to make sure the image is solid before
1724 * allowing it to appear.
1725 */
4be73780 1726 wait_backlight_on(intel_dp);
e39b999a 1727
773538e8 1728 pps_lock(intel_dp);
e39b999a 1729
453c5420 1730 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1731 pp |= EDP_BLC_ENABLE;
453c5420 1732
bf13e81b 1733 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1734
1735 I915_WRITE(pp_ctrl_reg, pp);
1736 POSTING_READ(pp_ctrl_reg);
e39b999a 1737
773538e8 1738 pps_unlock(intel_dp);
32f9d658
ZW		 1739}
1740
1250d107
JN		 1741/* Enable backlight PWM and backlight PP control. */
1742void intel_edp_backlight_on(struct intel_dp *intel_dp)
1743{
1744 if (!is_edp(intel_dp))
1745 return;
1746
1747 DRM_DEBUG_KMS("\n");
1748
1749 intel_panel_enable_backlight(intel_dp->attached_connector);
1750 _intel_edp_backlight_on(intel_dp);
1751}
1752
1753/* Disable backlight in the panel power control. */
1754static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1755{
30add22d 1756 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1757 struct drm_i915_private *dev_priv = dev->dev_private;
1758 u32 pp;
453c5420 1759 u32 pp_ctrl_reg;
32f9d658 1760
f01eca2e
KP		 1761 if (!is_edp(intel_dp))
1762 return;
1763
773538e8 1764 pps_lock(intel_dp);
e39b999a 1765
453c5420 1766 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1767 pp &= ~EDP_BLC_ENABLE;
453c5420 1768
bf13e81b 1769 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1770
1771 I915_WRITE(pp_ctrl_reg, pp);
1772 POSTING_READ(pp_ctrl_reg);
f7d2323c 1773
773538e8 1774 pps_unlock(intel_dp);
e39b999a
VS		 1775
1776 intel_dp->last_backlight_off = jiffies;
f7d2323c 1777 edp_wait_backlight_off(intel_dp);
1250d107 1778}
f7d2323c 1779
1250d107
JN		 1780/* Disable backlight PP control and backlight PWM. */
1781void intel_edp_backlight_off(struct intel_dp *intel_dp)
1782{
1783 if (!is_edp(intel_dp))
1784 return;
1785
1786 DRM_DEBUG_KMS("\n");
f7d2323c 1787
1250d107 1788 _intel_edp_backlight_off(intel_dp);
f7d2323c 1789 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1790}
a4fc5ed6 1791
73580fb7
JN		 1792/*
1793 * Hook for controlling the panel power control backlight through the bl_power
1794 * sysfs attribute. Take care to handle multiple calls.
1795 */
1796static void intel_edp_backlight_power(struct intel_connector *connector,
1797 bool enable)
1798{
1799 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1800 bool is_enabled;
1801
773538e8 1802 pps_lock(intel_dp);
e39b999a 1803 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1804 pps_unlock(intel_dp);
73580fb7
JN		 1805
1806 if (is_enabled == enable)
1807 return;
1808
23ba9373
JN		 1809 DRM_DEBUG_KMS("panel power control backlight %s\n",
1810 enable ? "enable" : "disable");
73580fb7
JN		 1811
1812 if (enable)
1813 _intel_edp_backlight_on(intel_dp);
1814 else
1815 _intel_edp_backlight_off(intel_dp);
1816}
1817
2bd2ad64 1818static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1819{
da63a9f2
PZ		 1820 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1821 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1822 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 u32 dpa_ctl;
1825
2bd2ad64
DV		 1826 assert_pipe_disabled(dev_priv,
1827 to_intel_crtc(crtc)->pipe);
1828
d240f20f
JB		 1829 DRM_DEBUG_KMS("\n");
1830 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1831 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1832 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1833
1834 /* We don't adjust intel_dp->DP while tearing down the link, to
1835 * facilitate link retraining (e.g. after hotplug). Hence clear all
1836 * enable bits here to ensure that we don't enable too much. */
1837 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1838 intel_dp->DP |= DP_PLL_ENABLE;
1839 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1840 POSTING_READ(DP_A);
1841 udelay(200);
d240f20f
JB		 1842}
1843
2bd2ad64 1844static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1845{
da63a9f2
PZ		 1846 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1847 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1848 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1849 struct drm_i915_private *dev_priv = dev->dev_private;
1850 u32 dpa_ctl;
1851
2bd2ad64
DV		 1852 assert_pipe_disabled(dev_priv,
1853 to_intel_crtc(crtc)->pipe);
1854
d240f20f 1855 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1856 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1857 "dp pll off, should be on\n");
1858 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1859
1860 /* We can't rely on the value tracked for the DP register in
1861 * intel_dp->DP because link_down must not change that (otherwise link
1862 * re-training will fail. */
298b0b39 1863 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1864 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1865 POSTING_READ(DP_A);
d240f20f
JB		 1866 udelay(200);
1867}
1868
c7ad3810 1869/* If the sink supports it, try to set the power state appropriately */
c19b0669 1870void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1871{
1872 int ret, i;
1873
1874 /* Should have a valid DPCD by this point */
1875 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1876 return;
1877
1878 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1879 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1880 DP_SET_POWER_D3);
c7ad3810
JB		 1881 } else {
1882 /*
1883 * When turning on, we need to retry for 1ms to give the sink
1884 * time to wake up.
1885 */
1886 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1887 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1888 DP_SET_POWER_D0);
c7ad3810
JB		 1889 if (ret == 1)
1890 break;
1891 msleep(1);
1892 }
1893 }
f9cac721
JN		 1894
1895 if (ret != 1)
1896 DRM_DEBUG_KMS("failed to %s sink power state\n",
1897 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1898}
1899
19d8fe15
DV		 1900static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1901 enum pipe *pipe)
d240f20f 1902{
19d8fe15 1903 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1904 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1905 struct drm_device *dev = encoder->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1907 enum intel_display_power_domain power_domain;
1908 u32 tmp;
1909
1910 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1911 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1912 return false;
1913
1914 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1915
1916 if (!(tmp & DP_PORT_EN))
1917 return false;
1918
bc7d38a4 1919 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1920 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1921 } else if (IS_CHERRYVIEW(dev)) {
1922 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1923 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1924 *pipe = PORT_TO_PIPE(tmp);
1925 } else {
1926 u32 trans_sel;
1927 u32 trans_dp;
1928 int i;
1929
1930 switch (intel_dp->output_reg) {
1931 case PCH_DP_B:
1932 trans_sel = TRANS_DP_PORT_SEL_B;
1933 break;
1934 case PCH_DP_C:
1935 trans_sel = TRANS_DP_PORT_SEL_C;
1936 break;
1937 case PCH_DP_D:
1938 trans_sel = TRANS_DP_PORT_SEL_D;
1939 break;
1940 default:
1941 return true;
1942 }
1943
055e393f 1944 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1945 trans_dp = I915_READ(TRANS_DP_CTL(i));
1946 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1947 *pipe = i;
1948 return true;
1949 }
1950 }
19d8fe15 1951
4a0833ec
DV		 1952 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1953 intel_dp->output_reg);
1954 }
d240f20f 1955
19d8fe15
DV		 1956 return true;
1957}
d240f20f 1958
045ac3b5
JB		 1959static void intel_dp_get_config(struct intel_encoder *encoder,
1960 struct intel_crtc_config *pipe_config)
1961{
1962 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1963 u32 tmp, flags = 0;
63000ef6
XZ		 1964 struct drm_device *dev = encoder->base.dev;
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966 enum port port = dp_to_dig_port(intel_dp)->port;
1967 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1968 int dotclock;
045ac3b5 1969
9ed109a7
DV		 1970 tmp = I915_READ(intel_dp->output_reg);
1971 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1972 pipe_config->has_audio = true;
1973
63000ef6 1974 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1975 if (tmp & DP_SYNC_HS_HIGH)
1976 flags |= DRM_MODE_FLAG_PHSYNC;
1977 else
1978 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1979
63000ef6
XZ		 1980 if (tmp & DP_SYNC_VS_HIGH)
1981 flags |= DRM_MODE_FLAG_PVSYNC;
1982 else
1983 flags |= DRM_MODE_FLAG_NVSYNC;
1984 } else {
1985 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1986 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1987 flags |= DRM_MODE_FLAG_PHSYNC;
1988 else
1989 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1990
63000ef6
XZ		 1991 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1992 flags |= DRM_MODE_FLAG_PVSYNC;
1993 else
1994 flags |= DRM_MODE_FLAG_NVSYNC;
1995 }
045ac3b5
JB		 1996
1997 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1998
8c875fca
VS		 1999 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2000 tmp & DP_COLOR_RANGE_16_235)
2001 pipe_config->limited_color_range = true;
2002
eb14cb74
VS		 2003 pipe_config->has_dp_encoder = true;
2004
2005 intel_dp_get_m_n(crtc, pipe_config);
2006
18442d08 2007 if (port == PORT_A) {
f1f644dc
JB		 2008 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2009 pipe_config->port_clock = 162000;
2010 else
2011 pipe_config->port_clock = 270000;
2012 }
18442d08
VS		 2013
2014 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2015 &pipe_config->dp_m_n);
2016
2017 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2018 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2019
241bfc38 2020 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2021
c6cd2ee2
JN		 2022 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2023 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2024 /*
2025 * This is a big fat ugly hack.
2026 *
2027 * Some machines in UEFI boot mode provide us a VBT that has 18
2028 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2029 * unknown we fail to light up. Yet the same BIOS boots up with
2030 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2031 * max, not what it tells us to use.
2032 *
2033 * Note: This will still be broken if the eDP panel is not lit
2034 * up by the BIOS, and thus we can't get the mode at module
2035 * load.
2036 */
2037 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2038 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2039 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2040 }
045ac3b5
JB		 2041}
2042
34eb7579 2043static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 2044{
34eb7579 2045 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 2046}
2047
2b28bb1b
RV		 2048static bool intel_edp_is_psr_enabled(struct drm_device *dev)
2049{
2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051
18b5992c 2052 if (!HAS_PSR(dev))
2b28bb1b
RV		 2053 return false;
2054
18b5992c 2055 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 2056}
2057
2058static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2059 struct edp_vsc_psr *vsc_psr)
2060{
2061 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2062 struct drm_device *dev = dig_port->base.base.dev;
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2065 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2066 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2067 uint32_t *data = (uint32_t *) vsc_psr;
2068 unsigned int i;
2069
2070 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2071 the video DIP being updated before program video DIP data buffer
2072 registers for DIP being updated. */
2073 I915_WRITE(ctl_reg, 0);
2074 POSTING_READ(ctl_reg);
2075
2076 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2077 if (i < sizeof(struct edp_vsc_psr))
2078 I915_WRITE(data_reg + i, *data++);
2079 else
2080 I915_WRITE(data_reg + i, 0);
2081 }
2082
2083 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2084 POSTING_READ(ctl_reg);
2085}
2086
ba80f4d4 2087static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2088{
2b28bb1b
RV		 2089 struct edp_vsc_psr psr_vsc;
2090
2b28bb1b
RV		 2091 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2092 memset(&psr_vsc, 0, sizeof(psr_vsc));
2093 psr_vsc.sdp_header.HB0 = 0;
2094 psr_vsc.sdp_header.HB1 = 0x7;
2095 psr_vsc.sdp_header.HB2 = 0x2;
2096 psr_vsc.sdp_header.HB3 = 0x8;
2097 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2098}
2099
2100static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2101{
0e0ae652
RV		 2102 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2103 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2104 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2105 uint32_t aux_clock_divider;
2b28bb1b 2106 int precharge = 0x3;
0e0ae652 2107 bool only_standby = false;
5ca476f8
VS		 2108 static const uint8_t aux_msg[] = {
2109 [0] = DP_AUX_NATIVE_WRITE << 4,
2110 [1] = DP_SET_POWER >> 8,
2111 [2] = DP_SET_POWER & 0xff,
2112 [3] = 1 - 1,
2113 [4] = DP_SET_POWER_D0,
2114 };
2115 int i;
2116
2117 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2118
ec5b01dd
DL		 2119 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2120
0e0ae652
RV		 2121 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2122 only_standby = true;
2123
2b28bb1b 2124 /* Enable PSR in sink */
0e0ae652 2125 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2126 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2127 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2128 else
9d1a1031
JN		 2129 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2130 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2131
2132 /* Setup AUX registers */
5ca476f8
VS		 2133 for (i = 0; i < sizeof(aux_msg); i += 4)
2134 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2135 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2136
18b5992c 2137 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2138 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2139 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2140 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2141 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2142}
2143
2144static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2145{
0e0ae652
RV		 2146 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2147 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2148 struct drm_i915_private *dev_priv = dev->dev_private;
2149 uint32_t max_sleep_time = 0x1f;
2150 uint32_t idle_frames = 1;
2151 uint32_t val = 0x0;
ed8546ac 2152 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2153 bool only_standby = false;
2154
2155 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2156 only_standby = true;
2b28bb1b 2157
0e0ae652 2158 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2159 val |= EDP_PSR_LINK_STANDBY;
2160 val |= EDP_PSR_TP2_TP3_TIME_0us;
2161 val |= EDP_PSR_TP1_TIME_0us;
2162 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2163 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2164 } else
2165 val |= EDP_PSR_LINK_DISABLE;
2166
18b5992c 2167 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2168 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2169 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2170 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2171 EDP_PSR_ENABLE);
2172}
2173
3f51e471
RV		 2174static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2175{
2176 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2177 struct drm_device *dev = dig_port->base.base.dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct drm_crtc *crtc = dig_port->base.base.crtc;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2181
f0355c4a 2182 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2183 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2184 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2185
a031d709
RV		 2186 dev_priv->psr.source_ok = false;
2187
9ca15301 2188 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2189 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2190 return false;
2191 }
2192
d330a953 2193 if (!i915.enable_psr) {
105b7c11 2194 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2195 return false;
2196 }
2197
4c8c7000
RV		 2198 /* Below limitations aren't valid for Broadwell */
2199 if (IS_BROADWELL(dev))
2200 goto out;
2201
3f51e471
RV		 2202 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2203 S3D_ENABLE) {
2204 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2205 return false;
2206 }
2207
ca73b4f0 2208 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2209 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2210 return false;
2211 }
2212
4c8c7000 2213 out:
a031d709 2214 dev_priv->psr.source_ok = true;
3f51e471
RV		 2215 return true;
2216}
2217
3d739d92 2218static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2219{
7c8f8a70
RV		 2220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2221 struct drm_device *dev = intel_dig_port->base.base.dev;
2222 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2223
3638379c
DV		 2224 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2225 WARN_ON(dev_priv->psr.active);
f0355c4a 2226 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2227
7ca5a41f 2228 /* Enable/Re-enable PSR on the host */
2b28bb1b 2229 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2230
7c8f8a70 2231 dev_priv->psr.active = true;
2b28bb1b
RV		 2232}
2233
3d739d92
RV		 2234void intel_edp_psr_enable(struct intel_dp *intel_dp)
2235{
2236 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2237 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2238
4704c573
RV		 2239 if (!HAS_PSR(dev)) {
2240 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2241 return;
2242 }
2243
34eb7579
RV		 2244 if (!is_edp_psr(intel_dp)) {
2245 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2246 return;
2247 }
2248
f0355c4a 2249 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2250 if (dev_priv->psr.enabled) {
2251 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2252 goto unlock;
109fc2ad
DV		 2253 }
2254
0aa48783
RV		 2255 if (!intel_edp_psr_match_conditions(intel_dp))
2256 goto unlock;
2257
9ca15301
DV		 2258 dev_priv->psr.busy_frontbuffer_bits = 0;
2259
ba80f4d4 2260 intel_edp_psr_setup_vsc(intel_dp);
16487254 2261
ba80f4d4
RV		 2262 /* Avoid continuous PSR exit by masking memup and hpd */
2263 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2264 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2265
7ca5a41f
RV		 2266 /* Enable PSR on the panel */
2267 intel_edp_psr_enable_sink(intel_dp);
2268
0aa48783
RV		 2269 dev_priv->psr.enabled = intel_dp;
2270unlock:
f0355c4a 2271 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2272}
2273
2b28bb1b
RV		 2274void intel_edp_psr_disable(struct intel_dp *intel_dp)
2275{
2276 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278
f0355c4a
DV		 2279 mutex_lock(&dev_priv->psr.lock);
2280 if (!dev_priv->psr.enabled) {
2281 mutex_unlock(&dev_priv->psr.lock);
2282 return;
2283 }
2284
3638379c
DV		 2285 if (dev_priv->psr.active) {
2286 I915_WRITE(EDP_PSR_CTL(dev),
2287 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2288
2289 /* Wait till PSR is idle */
2290 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2291 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2292 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2293
3638379c
DV		 2294 dev_priv->psr.active = false;
2295 } else {
2296 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2297 }
7c8f8a70 2298
2807cf69 2299 dev_priv->psr.enabled = NULL;
f0355c4a 2300 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2301
2302 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2303}
2304
f02a326e 2305static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2306{
2307 struct drm_i915_private *dev_priv =
2308 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2309 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2310
8d7f4fe9
RV		 2311 /* We have to make sure PSR is ready for re-enable
2312 * otherwise it keeps disabled until next full enable/disable cycle.
2313 * PSR might take some time to get fully disabled
2314 * and be ready for re-enable.
2315 */
2316 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2317 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2318 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2319 return;
2320 }
2321
f0355c4a
DV		 2322 mutex_lock(&dev_priv->psr.lock);
2323 intel_dp = dev_priv->psr.enabled;
2324
2807cf69 2325 if (!intel_dp)
f0355c4a 2326 goto unlock;
2807cf69 2327
9ca15301
DV		 2328 /*
2329 * The delayed work can race with an invalidate hence we need to
2330 * recheck. Since psr_flush first clears this and then reschedules we
2331 * won't ever miss a flush when bailing out here.
2332 */
2333 if (dev_priv->psr.busy_frontbuffer_bits)
2334 goto unlock;
2335
2336 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2337unlock:
2338 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2339}
2340
9ca15301 2341static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2342{
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344
3638379c
DV		 2345 if (dev_priv->psr.active) {
2346 u32 val = I915_READ(EDP_PSR_CTL(dev));
2347
2348 WARN_ON(!(val & EDP_PSR_ENABLE));
2349
2350 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2351
2352 dev_priv->psr.active = false;
2353 }
7c8f8a70 2354
9ca15301
DV		 2355}
2356
2357void intel_edp_psr_invalidate(struct drm_device *dev,
2358 unsigned frontbuffer_bits)
2359{
2360 struct drm_i915_private *dev_priv = dev->dev_private;
2361 struct drm_crtc *crtc;
2362 enum pipe pipe;
2363
9ca15301
DV		 2364 mutex_lock(&dev_priv->psr.lock);
2365 if (!dev_priv->psr.enabled) {
2366 mutex_unlock(&dev_priv->psr.lock);
2367 return;
2368 }
2369
2370 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2371 pipe = to_intel_crtc(crtc)->pipe;
2372
2373 intel_edp_psr_do_exit(dev);
2374
2375 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2376
2377 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2378 mutex_unlock(&dev_priv->psr.lock);
2379}
2380
2381void intel_edp_psr_flush(struct drm_device *dev,
2382 unsigned frontbuffer_bits)
2383{
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2385 struct drm_crtc *crtc;
2386 enum pipe pipe;
2387
9ca15301
DV		 2388 mutex_lock(&dev_priv->psr.lock);
2389 if (!dev_priv->psr.enabled) {
2390 mutex_unlock(&dev_priv->psr.lock);
2391 return;
2392 }
2393
2394 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2395 pipe = to_intel_crtc(crtc)->pipe;
2396 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2397
2398 /*
2399 * On Haswell sprite plane updates don't result in a psr invalidating
2400 * signal in the hardware. Which means we need to manually fake this in
2401 * software for all flushes, not just when we've seen a preceding
2402 * invalidation through frontbuffer rendering.
2403 */
2404 if (IS_HASWELL(dev) &&
2405 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2406 intel_edp_psr_do_exit(dev);
2407
2408 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2409 schedule_delayed_work(&dev_priv->psr.work,
2410 msecs_to_jiffies(100));
f0355c4a 2411 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2412}
2413
2414void intel_edp_psr_init(struct drm_device *dev)
2415{
2416 struct drm_i915_private *dev_priv = dev->dev_private;
2417
7c8f8a70 2418 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2419 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2420}
2421
e8cb4558 2422static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2423{
e8cb4558 2424 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2425 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2426
2427 /* Make sure the panel is off before trying to change the mode. But also
2428 * ensure that we have vdd while we switch off the panel. */
24f3e092 2429 intel_edp_panel_vdd_on(intel_dp);
4be73780 2430 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2431 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2432 intel_edp_panel_off(intel_dp);
3739850b 2433
08aff3fe
VS		 2434 /* disable the port before the pipe on g4x */
2435 if (INTEL_INFO(dev)->gen < 5)
3739850b 2436 intel_dp_link_down(intel_dp);
d240f20f
JB		 2437}
2438
08aff3fe 2439static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2440{
2bd2ad64 2441 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2442 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2443
49277c31 2444 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2445 if (port == PORT_A)
2446 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2447}
2448
2449static void vlv_post_disable_dp(struct intel_encoder *encoder)
2450{
2451 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2452
2453 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2454}
2455
580d3811
VS		 2456static void chv_post_disable_dp(struct intel_encoder *encoder)
2457{
2458 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2459 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2460 struct drm_device *dev = encoder->base.dev;
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462 struct intel_crtc *intel_crtc =
2463 to_intel_crtc(encoder->base.crtc);
2464 enum dpio_channel ch = vlv_dport_to_channel(dport);
2465 enum pipe pipe = intel_crtc->pipe;
2466 u32 val;
2467
2468 intel_dp_link_down(intel_dp);
2469
2470 mutex_lock(&dev_priv->dpio_lock);
2471
2472 /* Propagate soft reset to data lane reset */
97fd4d5c 2473 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2474 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2475 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2476
97fd4d5c
VS		 2477 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2478 val |= CHV_PCS_REQ_SOFTRESET_EN;
2479 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2480
2481 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2482 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2483 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2484
2485 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2486 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2487 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2488
2489 mutex_unlock(&dev_priv->dpio_lock);
2490}
2491
7b13b58a
VS		 2492static void
2493_intel_dp_set_link_train(struct intel_dp *intel_dp,
2494 uint32_t *DP,
2495 uint8_t dp_train_pat)
2496{
2497 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2498 struct drm_device *dev = intel_dig_port->base.base.dev;
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 enum port port = intel_dig_port->port;
2501
2502 if (HAS_DDI(dev)) {
2503 uint32_t temp = I915_READ(DP_TP_CTL(port));
2504
2505 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2506 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2507 else
2508 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2509
2510 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2511 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2512 case DP_TRAINING_PATTERN_DISABLE:
2513 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2514
2515 break;
2516 case DP_TRAINING_PATTERN_1:
2517 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2518 break;
2519 case DP_TRAINING_PATTERN_2:
2520 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2521 break;
2522 case DP_TRAINING_PATTERN_3:
2523 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2524 break;
2525 }
2526 I915_WRITE(DP_TP_CTL(port), temp);
2527
2528 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2529 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2530
2531 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2532 case DP_TRAINING_PATTERN_DISABLE:
2533 *DP |= DP_LINK_TRAIN_OFF_CPT;
2534 break;
2535 case DP_TRAINING_PATTERN_1:
2536 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2537 break;
2538 case DP_TRAINING_PATTERN_2:
2539 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2540 break;
2541 case DP_TRAINING_PATTERN_3:
2542 DRM_ERROR("DP training pattern 3 not supported\n");
2543 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2544 break;
2545 }
2546
2547 } else {
2548 if (IS_CHERRYVIEW(dev))
2549 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2550 else
2551 *DP &= ~DP_LINK_TRAIN_MASK;
2552
2553 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2554 case DP_TRAINING_PATTERN_DISABLE:
2555 *DP |= DP_LINK_TRAIN_OFF;
2556 break;
2557 case DP_TRAINING_PATTERN_1:
2558 *DP |= DP_LINK_TRAIN_PAT_1;
2559 break;
2560 case DP_TRAINING_PATTERN_2:
2561 *DP |= DP_LINK_TRAIN_PAT_2;
2562 break;
2563 case DP_TRAINING_PATTERN_3:
2564 if (IS_CHERRYVIEW(dev)) {
2565 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2566 } else {
2567 DRM_ERROR("DP training pattern 3 not supported\n");
2568 *DP |= DP_LINK_TRAIN_PAT_2;
2569 }
2570 break;
2571 }
2572 }
2573}
2574
2575static void intel_dp_enable_port(struct intel_dp *intel_dp)
2576{
2577 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579
7b13b58a
VS		 2580 /* enable with pattern 1 (as per spec) */
2581 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2582 DP_TRAINING_PATTERN_1);
2583
2584 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2585 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2586
2587 /*
2588 * Magic for VLV/CHV. We _must_ first set up the register
2589 * without actually enabling the port, and then do another
2590 * write to enable the port. Otherwise link training will
2591 * fail when the power sequencer is freshly used for this port.
2592 */
2593 intel_dp->DP |= DP_PORT_EN;
2594
2595 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2596 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2597}
2598
e8cb4558 2599static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2600{
e8cb4558
DV		 2601 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2602 struct drm_device *dev = encoder->base.dev;
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2605
0c33d8d7
DV		 2606 if (WARN_ON(dp_reg & DP_PORT_EN))
2607 return;
5d613501 2608
093e3f13
VS		 2609 pps_lock(intel_dp);
2610
2611 if (IS_VALLEYVIEW(dev))
2612 vlv_init_panel_power_sequencer(intel_dp);
2613
7b13b58a 2614 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2615
2616 edp_panel_vdd_on(intel_dp);
2617 edp_panel_on(intel_dp);
2618 edp_panel_vdd_off(intel_dp, true);
2619
2620 pps_unlock(intel_dp);
2621
61234fa5
VS		 2622 if (IS_VALLEYVIEW(dev))
2623 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2624
f01eca2e 2625 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2626 intel_dp_start_link_train(intel_dp);
33a34e4e 2627 intel_dp_complete_link_train(intel_dp);
3ab9c637 2628 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2629}
89b667f8 2630
ecff4f3b
JN		 2631static void g4x_enable_dp(struct intel_encoder *encoder)
2632{
828f5c6e
JN		 2633 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2634
ecff4f3b 2635 intel_enable_dp(encoder);
4be73780 2636 intel_edp_backlight_on(intel_dp);
ab1f90f9 2637}
89b667f8 2638
ab1f90f9
JN		 2639static void vlv_enable_dp(struct intel_encoder *encoder)
2640{
828f5c6e
JN		 2641 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2642
4be73780 2643 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2644}
2645
ecff4f3b 2646static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2647{
2648 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2649 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2650
8ac33ed3
DV		 2651 intel_dp_prepare(encoder);
2652
d41f1efb
DV		 2653 /* Only ilk+ has port A */
2654 if (dport->port == PORT_A) {
2655 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2656 ironlake_edp_pll_on(intel_dp);
d41f1efb 2657 }
ab1f90f9
JN		 2658}
2659
a4a5d2f8
VS		 2660static void vlv_steal_power_sequencer(struct drm_device *dev,
2661 enum pipe pipe)
2662{
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 struct intel_encoder *encoder;
2665
2666 lockdep_assert_held(&dev_priv->pps_mutex);
2667
2668 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2669 base.head) {
2670 struct intel_dp *intel_dp;
773538e8 2671 enum port port;
a4a5d2f8
VS		 2672
2673 if (encoder->type != INTEL_OUTPUT_EDP)
2674 continue;
2675
2676 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2677 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2678
2679 if (intel_dp->pps_pipe != pipe)
2680 continue;
2681
2682 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2683 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2684
2685 /* make sure vdd is off before we steal it */
2686 edp_panel_vdd_off_sync(intel_dp);
2687
2688 intel_dp->pps_pipe = INVALID_PIPE;
2689 }
2690}
2691
2692static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2693{
2694 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2695 struct intel_encoder *encoder = &intel_dig_port->base;
2696 struct drm_device *dev = encoder->base.dev;
2697 struct drm_i915_private *dev_priv = dev->dev_private;
2698 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2699
2700 lockdep_assert_held(&dev_priv->pps_mutex);
2701
093e3f13
VS		 2702 if (!is_edp(intel_dp))
2703 return;
2704
a4a5d2f8
VS		 2705 if (intel_dp->pps_pipe == crtc->pipe)
2706 return;
2707
2708 /*
2709 * If another power sequencer was being used on this
2710 * port previously make sure to turn off vdd there while
2711 * we still have control of it.
2712 */
2713 if (intel_dp->pps_pipe != INVALID_PIPE)
2714 edp_panel_vdd_off_sync(intel_dp);
2715
2716 /*
2717 * We may be stealing the power
2718 * sequencer from another port.
2719 */
2720 vlv_steal_power_sequencer(dev, crtc->pipe);
2721
2722 /* now it's all ours */
2723 intel_dp->pps_pipe = crtc->pipe;
2724
2725 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2726 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2727
2728 /* init power sequencer on this pipe and port */
36b5f425
VS		 2729 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2730 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2731}
2732
ab1f90f9 2733static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2734{
2bd2ad64 2735 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2736 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2737 struct drm_device *dev = encoder->base.dev;
89b667f8 2738 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2739 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2740 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2741 int pipe = intel_crtc->pipe;
2742 u32 val;
a4fc5ed6 2743
ab1f90f9 2744 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2745
ab3c759a 2746 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2747 val = 0;
2748 if (pipe)
2749 val |= (1<<21);
2750 else
2751 val &= ~(1<<21);
2752 val |= 0x001000c4;
ab3c759a
CML		 2753 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2754 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2755 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2756
ab1f90f9
JN		 2757 mutex_unlock(&dev_priv->dpio_lock);
2758
2759 intel_enable_dp(encoder);
89b667f8
JB		 2760}
2761
ecff4f3b 2762static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2763{
2764 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2765 struct drm_device *dev = encoder->base.dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2767 struct intel_crtc *intel_crtc =
2768 to_intel_crtc(encoder->base.crtc);
e4607fcf 2769 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2770 int pipe = intel_crtc->pipe;
89b667f8 2771
8ac33ed3
DV		 2772 intel_dp_prepare(encoder);
2773
89b667f8 2774 /* Program Tx lane resets to default */
0980a60f 2775 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2776 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2777 DPIO_PCS_TX_LANE2_RESET |
2778 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2779 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2780 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2781 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2782 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2783 DPIO_PCS_CLK_SOFT_RESET);
2784
2785 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2786 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2787 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2788 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2789 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2790}
2791
e4a1d846
CML		 2792static void chv_pre_enable_dp(struct intel_encoder *encoder)
2793{
2794 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2795 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2796 struct drm_device *dev = encoder->base.dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2798 struct intel_crtc *intel_crtc =
2799 to_intel_crtc(encoder->base.crtc);
2800 enum dpio_channel ch = vlv_dport_to_channel(dport);
2801 int pipe = intel_crtc->pipe;
2802 int data, i;
949c1d43 2803 u32 val;
e4a1d846 2804
e4a1d846 2805 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2806
570e2a74
VS		 2807 /* allow hardware to manage TX FIFO reset source */
2808 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2809 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2810 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2811
2812 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2813 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2814 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2815
949c1d43 2816 /* Deassert soft data lane reset*/
97fd4d5c 2817 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2818 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2819 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2820
2821 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2822 val |= CHV_PCS_REQ_SOFTRESET_EN;
2823 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2824
2825 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2826 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2827 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2828
97fd4d5c 2829 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2830 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2831 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2832
2833 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2834 for (i = 0; i < 4; i++) {
2835 /* Set the latency optimal bit */
2836 data = (i == 1) ? 0x0 : 0x6;
2837 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2838 data << DPIO_FRC_LATENCY_SHFIT);
2839
2840 /* Set the upar bit */
2841 data = (i == 1) ? 0x0 : 0x1;
2842 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2843 data << DPIO_UPAR_SHIFT);
2844 }
2845
2846 /* Data lane stagger programming */
2847 /* FIXME: Fix up value only after power analysis */
2848
2849 mutex_unlock(&dev_priv->dpio_lock);
2850
e4a1d846 2851 intel_enable_dp(encoder);
e4a1d846
CML		 2852}
2853
9197c88b
VS		 2854static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2855{
2856 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2857 struct drm_device *dev = encoder->base.dev;
2858 struct drm_i915_private *dev_priv = dev->dev_private;
2859 struct intel_crtc *intel_crtc =
2860 to_intel_crtc(encoder->base.crtc);
2861 enum dpio_channel ch = vlv_dport_to_channel(dport);
2862 enum pipe pipe = intel_crtc->pipe;
2863 u32 val;
2864
625695f8
VS		 2865 intel_dp_prepare(encoder);
2866
9197c88b
VS		 2867 mutex_lock(&dev_priv->dpio_lock);
2868
b9e5ac3c
VS		 2869 /* program left/right clock distribution */
2870 if (pipe != PIPE_B) {
2871 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2872 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2873 if (ch == DPIO_CH0)
2874 val |= CHV_BUFLEFTENA1_FORCE;
2875 if (ch == DPIO_CH1)
2876 val |= CHV_BUFRIGHTENA1_FORCE;
2877 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2878 } else {
2879 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2880 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2881 if (ch == DPIO_CH0)
2882 val |= CHV_BUFLEFTENA2_FORCE;
2883 if (ch == DPIO_CH1)
2884 val |= CHV_BUFRIGHTENA2_FORCE;
2885 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2886 }
2887
9197c88b
VS		 2888 /* program clock channel usage */
2889 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2890 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2891 if (pipe != PIPE_B)
2892 val &= ~CHV_PCS_USEDCLKCHANNEL;
2893 else
2894 val |= CHV_PCS_USEDCLKCHANNEL;
2895 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2896
2897 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2898 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2899 if (pipe != PIPE_B)
2900 val &= ~CHV_PCS_USEDCLKCHANNEL;
2901 else
2902 val |= CHV_PCS_USEDCLKCHANNEL;
2903 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2904
2905 /*
2906 * This a a bit weird since generally CL
2907 * matches the pipe, but here we need to
2908 * pick the CL based on the port.
2909 */
2910 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2911 if (pipe != PIPE_B)
2912 val &= ~CHV_CMN_USEDCLKCHANNEL;
2913 else
2914 val |= CHV_CMN_USEDCLKCHANNEL;
2915 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2916
2917 mutex_unlock(&dev_priv->dpio_lock);
2918}
2919
a4fc5ed6 2920/*
df0c237d
JB		 2921 * Native read with retry for link status and receiver capability reads for
2922 * cases where the sink may still be asleep.
9d1a1031
JN		 2923 *
2924 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2925 * supposed to retry 3 times per the spec.
a4fc5ed6 2926 */
9d1a1031
JN		 2927static ssize_t
2928intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2929 void *buffer, size_t size)
a4fc5ed6 2930{
9d1a1031
JN		 2931 ssize_t ret;
2932 int i;
61da5fab 2933
61da5fab 2934 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2935 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2936 if (ret == size)
2937 return ret;
61da5fab
JB		 2938 msleep(1);
2939 }
a4fc5ed6 2940
9d1a1031 2941 return ret;
a4fc5ed6
KP		 2942}
2943
2944/*
2945 * Fetch AUX CH registers 0x202 - 0x207 which contain
2946 * link status information
2947 */
2948static bool
93f62dad 2949intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2950{
9d1a1031
JN		 2951 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2952 DP_LANE0_1_STATUS,
2953 link_status,
2954 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2955}
2956
1100244e 2957/* These are source-specific values. */
a4fc5ed6 2958static uint8_t
1a2eb460 2959intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2960{
30add22d 2961 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2962 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2963
5a9d1f1a
DL		 2964 if (INTEL_INFO(dev)->gen >= 9)
2965 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2966 else if (IS_VALLEYVIEW(dev))
bd60018a 2967 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2968 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2969 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2970 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2971 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2972 else
bd60018a 2973 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2974}
2975
2976static uint8_t
2977intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2978{
30add22d 2979 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2980 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2981
5a9d1f1a
DL		 2982 if (INTEL_INFO(dev)->gen >= 9) {
2983 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2985 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2987 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2988 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2989 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2990 default:
2991 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2992 }
2993 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2994 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2996 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2998 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3000 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3001 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3002 default:
bd60018a 3003 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3004 }
e2fa6fba
P		 3005 } else if (IS_VALLEYVIEW(dev)) {
3006 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3008 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3010 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3014 default:
bd60018a 3015 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3016 }
bc7d38a4 3017 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3018 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3020 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3023 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3024 default:
bd60018a 3025 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3026 }
3027 } else {
3028 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3030 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3036 default:
bd60018a 3037 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3038 }
a4fc5ed6
KP		 3039 }
3040}
3041
e2fa6fba
P		 3042static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
3043{
3044 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3045 struct drm_i915_private *dev_priv = dev->dev_private;
3046 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3047 struct intel_crtc *intel_crtc =
3048 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3049 unsigned long demph_reg_value, preemph_reg_value,
3050 uniqtranscale_reg_value;
3051 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3052 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3053 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3054
3055 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3056 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3057 preemph_reg_value = 0x0004000;
3058 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3060 demph_reg_value = 0x2B405555;
3061 uniqtranscale_reg_value = 0x552AB83A;
3062 break;
bd60018a 3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3064 demph_reg_value = 0x2B404040;
3065 uniqtranscale_reg_value = 0x5548B83A;
3066 break;
bd60018a 3067 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3068 demph_reg_value = 0x2B245555;
3069 uniqtranscale_reg_value = 0x5560B83A;
3070 break;
bd60018a 3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3072 demph_reg_value = 0x2B405555;
3073 uniqtranscale_reg_value = 0x5598DA3A;
3074 break;
3075 default:
3076 return 0;
3077 }
3078 break;
bd60018a 3079 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3080 preemph_reg_value = 0x0002000;
3081 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3083 demph_reg_value = 0x2B404040;
3084 uniqtranscale_reg_value = 0x5552B83A;
3085 break;
bd60018a 3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3087 demph_reg_value = 0x2B404848;
3088 uniqtranscale_reg_value = 0x5580B83A;
3089 break;
bd60018a 3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3091 demph_reg_value = 0x2B404040;
3092 uniqtranscale_reg_value = 0x55ADDA3A;
3093 break;
3094 default:
3095 return 0;
3096 }
3097 break;
bd60018a 3098 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3099 preemph_reg_value = 0x0000000;
3100 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3102 demph_reg_value = 0x2B305555;
3103 uniqtranscale_reg_value = 0x5570B83A;
3104 break;
bd60018a 3105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3106 demph_reg_value = 0x2B2B4040;
3107 uniqtranscale_reg_value = 0x55ADDA3A;
3108 break;
3109 default:
3110 return 0;
3111 }
3112 break;
bd60018a 3113 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3114 preemph_reg_value = 0x0006000;
3115 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3117 demph_reg_value = 0x1B405555;
3118 uniqtranscale_reg_value = 0x55ADDA3A;
3119 break;
3120 default:
3121 return 0;
3122 }
3123 break;
3124 default:
3125 return 0;
3126 }
3127
0980a60f 3128 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3129 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3130 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3131 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3132 uniqtranscale_reg_value);
ab3c759a
CML		 3133 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3134 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3135 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3136 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3137 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3138
3139 return 0;
3140}
3141
e4a1d846
CML		 3142static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3143{
3144 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3145 struct drm_i915_private *dev_priv = dev->dev_private;
3146 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3147 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3148 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3149 uint8_t train_set = intel_dp->train_set[0];
3150 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3151 enum pipe pipe = intel_crtc->pipe;
3152 int i;
e4a1d846
CML		 3153
3154 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3155 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3156 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3157 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3158 deemph_reg_value = 128;
3159 margin_reg_value = 52;
3160 break;
bd60018a 3161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3162 deemph_reg_value = 128;
3163 margin_reg_value = 77;
3164 break;
bd60018a 3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3166 deemph_reg_value = 128;
3167 margin_reg_value = 102;
3168 break;
bd60018a 3169 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3170 deemph_reg_value = 128;
3171 margin_reg_value = 154;
3172 /* FIXME extra to set for 1200 */
3173 break;
3174 default:
3175 return 0;
3176 }
3177 break;
bd60018a 3178 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3179 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3181 deemph_reg_value = 85;
3182 margin_reg_value = 78;
3183 break;
bd60018a 3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3185 deemph_reg_value = 85;
3186 margin_reg_value = 116;
3187 break;
bd60018a 3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3189 deemph_reg_value = 85;
3190 margin_reg_value = 154;
3191 break;
3192 default:
3193 return 0;
3194 }
3195 break;
bd60018a 3196 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3197 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3199 deemph_reg_value = 64;
3200 margin_reg_value = 104;
3201 break;
bd60018a 3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3203 deemph_reg_value = 64;
3204 margin_reg_value = 154;
3205 break;
3206 default:
3207 return 0;
3208 }
3209 break;
bd60018a 3210 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3211 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3213 deemph_reg_value = 43;
3214 margin_reg_value = 154;
3215 break;
3216 default:
3217 return 0;
3218 }
3219 break;
3220 default:
3221 return 0;
3222 }
3223
3224 mutex_lock(&dev_priv->dpio_lock);
3225
3226 /* Clear calc init */
1966e59e
VS		 3227 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3228 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3229 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3230 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3231 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3232
3233 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3234 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3235 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3236 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3237 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3238
a02ef3c7
VS		 3239 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3240 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3241 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3242 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3243
3244 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3245 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3246 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3247 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3248
e4a1d846 3249 /* Program swing deemph */
f72df8db
VS		 3250 for (i = 0; i < 4; i++) {
3251 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3252 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3253 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3254 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3255 }
e4a1d846
CML		 3256
3257 /* Program swing margin */
f72df8db
VS		 3258 for (i = 0; i < 4; i++) {
3259 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3260 val &= ~DPIO_SWING_MARGIN000_MASK;
3261 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3262 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3263 }
e4a1d846
CML		 3264
3265 /* Disable unique transition scale */
f72df8db
VS		 3266 for (i = 0; i < 4; i++) {
3267 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3268 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3269 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3270 }
e4a1d846
CML		 3271
3272 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3273 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3274 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3275 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3276
3277 /*
3278 * The document said it needs to set bit 27 for ch0 and bit 26
3279 * for ch1. Might be a typo in the doc.
3280 * For now, for this unique transition scale selection, set bit
3281 * 27 for ch0 and ch1.
3282 */
f72df8db
VS		 3283 for (i = 0; i < 4; i++) {
3284 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3285 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3286 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3287 }
e4a1d846 3288
f72df8db
VS		 3289 for (i = 0; i < 4; i++) {
3290 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3291 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3292 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3293 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3294 }
e4a1d846
CML		 3295 }
3296
3297 /* Start swing calculation */
1966e59e
VS		 3298 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3299 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3300 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3301
3302 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3303 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3304 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3305
3306 /* LRC Bypass */
3307 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3308 val |= DPIO_LRC_BYPASS;
3309 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3310
3311 mutex_unlock(&dev_priv->dpio_lock);
3312
3313 return 0;
3314}
3315
a4fc5ed6 3316static void
0301b3ac
JN		 3317intel_get_adjust_train(struct intel_dp *intel_dp,
3318 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3319{
3320 uint8_t v = 0;
3321 uint8_t p = 0;
3322 int lane;
1a2eb460
KP		 3323 uint8_t voltage_max;
3324 uint8_t preemph_max;
a4fc5ed6 3325
33a34e4e 3326 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3327 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3328 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3329
3330 if (this_v > v)
3331 v = this_v;
3332 if (this_p > p)
3333 p = this_p;
3334 }
3335
1a2eb460 3336 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3337 if (v >= voltage_max)
3338 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3339
1a2eb460
KP		 3340 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3341 if (p >= preemph_max)
3342 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3343
3344 for (lane = 0; lane < 4; lane++)
33a34e4e 3345 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3346}
3347
3348static uint32_t
f0a3424e 3349intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3350{
3cf2efb1 3351 uint32_t signal_levels = 0;
a4fc5ed6 3352
3cf2efb1 3353 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3354 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3355 default:
3356 signal_levels |= DP_VOLTAGE_0_4;
3357 break;
bd60018a 3358 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3359 signal_levels |= DP_VOLTAGE_0_6;
3360 break;
bd60018a 3361 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3362 signal_levels |= DP_VOLTAGE_0_8;
3363 break;
bd60018a 3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3365 signal_levels |= DP_VOLTAGE_1_2;
3366 break;
3367 }
3cf2efb1 3368 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3369 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3370 default:
3371 signal_levels |= DP_PRE_EMPHASIS_0;
3372 break;
bd60018a 3373 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3374 signal_levels |= DP_PRE_EMPHASIS_3_5;
3375 break;
bd60018a 3376 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3377 signal_levels |= DP_PRE_EMPHASIS_6;
3378 break;
bd60018a 3379 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3380 signal_levels |= DP_PRE_EMPHASIS_9_5;
3381 break;
3382 }
3383 return signal_levels;
3384}
3385
e3421a18
ZW		 3386/* Gen6's DP voltage swing and pre-emphasis control */
3387static uint32_t
3388intel_gen6_edp_signal_levels(uint8_t train_set)
3389{
3c5a62b5
YL		 3390 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3391 DP_TRAIN_PRE_EMPHASIS_MASK);
3392 switch (signal_levels) {
bd60018a
SJ		 3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3395 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3396 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3397 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3398 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3400 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3401 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3402 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3403 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3404 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3406 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3407 default:
3c5a62b5
YL		 3408 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3409 "0x%x\n", signal_levels);
3410 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3411 }
3412}
3413
1a2eb460
KP		 3414/* Gen7's DP voltage swing and pre-emphasis control */
3415static uint32_t
3416intel_gen7_edp_signal_levels(uint8_t train_set)
3417{
3418 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3419 DP_TRAIN_PRE_EMPHASIS_MASK);
3420 switch (signal_levels) {
bd60018a 3421 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3422 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3423 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3424 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3425 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3426 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3427
bd60018a 3428 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3429 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3431 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3432
bd60018a 3433 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3434 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3435 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3436 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3437
3438 default:
3439 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3440 "0x%x\n", signal_levels);
3441 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3442 }
3443}
3444
d6c0d722
PZ		 3445/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3446static uint32_t
f0a3424e 3447intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3448{
d6c0d722
PZ		 3449 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3450 DP_TRAIN_PRE_EMPHASIS_MASK);
3451 switch (signal_levels) {
bd60018a 3452 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3453 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3454 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3455 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3457 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3458 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3459 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3460
bd60018a 3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3462 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3463 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3464 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3465 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3466 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3467
bd60018a 3468 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3469 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3470 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3471 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3472 default:
3473 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3474 "0x%x\n", signal_levels);
c5fe6a06 3475 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3476 }
a4fc5ed6
KP		 3477}
3478
f0a3424e
PZ		 3479/* Properly updates "DP" with the correct signal levels. */
3480static void
3481intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3482{
3483 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3484 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3485 struct drm_device *dev = intel_dig_port->base.base.dev;
3486 uint32_t signal_levels, mask;
3487 uint8_t train_set = intel_dp->train_set[0];
3488
5a9d1f1a 3489 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3490 signal_levels = intel_hsw_signal_levels(train_set);
3491 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3492 } else if (IS_CHERRYVIEW(dev)) {
3493 signal_levels = intel_chv_signal_levels(intel_dp);
3494 mask = 0;
e2fa6fba
P		 3495 } else if (IS_VALLEYVIEW(dev)) {
3496 signal_levels = intel_vlv_signal_levels(intel_dp);
3497 mask = 0;
bc7d38a4 3498 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3499 signal_levels = intel_gen7_edp_signal_levels(train_set);
3500 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3501 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3502 signal_levels = intel_gen6_edp_signal_levels(train_set);
3503 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3504 } else {
3505 signal_levels = intel_gen4_signal_levels(train_set);
3506 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3507 }
3508
3509 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3510
3511 *DP = (*DP & ~mask) | signal_levels;
3512}
3513
a4fc5ed6 3514static bool
ea5b213a 3515intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3516 uint32_t *DP,
58e10eb9 3517 uint8_t dp_train_pat)
a4fc5ed6 3518{
174edf1f
PZ		 3519 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3520 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3521 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3522 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3523 int ret, len;
a4fc5ed6 3524
7b13b58a 3525 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3526
70aff66c 3527 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3528 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3529
2cdfe6c8
JN		 3530 buf[0] = dp_train_pat;
3531 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3532 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3533 /* don't write DP_TRAINING_LANEx_SET on disable */
3534 len = 1;
3535 } else {
3536 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3537 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3538 len = intel_dp->lane_count + 1;
47ea7542 3539 }
a4fc5ed6 3540
9d1a1031
JN		 3541 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3542 buf, len);
2cdfe6c8
JN		 3543
3544 return ret == len;
a4fc5ed6
KP		 3545}
3546
70aff66c
JN		 3547static bool
3548intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3549 uint8_t dp_train_pat)
3550{
953d22e8 3551 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3552 intel_dp_set_signal_levels(intel_dp, DP);
3553 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3554}
3555
3556static bool
3557intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3558 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3559{
3560 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3561 struct drm_device *dev = intel_dig_port->base.base.dev;
3562 struct drm_i915_private *dev_priv = dev->dev_private;
3563 int ret;
3564
3565 intel_get_adjust_train(intel_dp, link_status);
3566 intel_dp_set_signal_levels(intel_dp, DP);
3567
3568 I915_WRITE(intel_dp->output_reg, *DP);
3569 POSTING_READ(intel_dp->output_reg);
3570
9d1a1031
JN		 3571 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3572 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3573
3574 return ret == intel_dp->lane_count;
3575}
3576
3ab9c637
ID		 3577static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3578{
3579 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3580 struct drm_device *dev = intel_dig_port->base.base.dev;
3581 struct drm_i915_private *dev_priv = dev->dev_private;
3582 enum port port = intel_dig_port->port;
3583 uint32_t val;
3584
3585 if (!HAS_DDI(dev))
3586 return;
3587
3588 val = I915_READ(DP_TP_CTL(port));
3589 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3590 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3591 I915_WRITE(DP_TP_CTL(port), val);
3592
3593 /*
3594 * On PORT_A we can have only eDP in SST mode. There the only reason
3595 * we need to set idle transmission mode is to work around a HW issue
3596 * where we enable the pipe while not in idle link-training mode.
3597 * In this case there is requirement to wait for a minimum number of
3598 * idle patterns to be sent.
3599 */
3600 if (port == PORT_A)
3601 return;
3602
3603 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3604 1))
3605 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3606}
3607
33a34e4e 3608/* Enable corresponding port and start training pattern 1 */
c19b0669 3609void
33a34e4e 3610intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3611{
da63a9f2 3612 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3613 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3614 int i;
3615 uint8_t voltage;
cdb0e95b 3616 int voltage_tries, loop_tries;
ea5b213a 3617 uint32_t DP = intel_dp->DP;
6aba5b6c 3618 uint8_t link_config[2];
a4fc5ed6 3619
affa9354 3620 if (HAS_DDI(dev))
c19b0669
PZ		 3621 intel_ddi_prepare_link_retrain(encoder);
3622
3cf2efb1 3623 /* Write the link configuration data */
6aba5b6c
JN		 3624 link_config[0] = intel_dp->link_bw;
3625 link_config[1] = intel_dp->lane_count;
3626 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3627 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3628 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3629
3630 link_config[0] = 0;
3631 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3632 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3633
3634 DP |= DP_PORT_EN;
1a2eb460 3635
70aff66c
JN		 3636 /* clock recovery */
3637 if (!intel_dp_reset_link_train(intel_dp, &DP,
3638 DP_TRAINING_PATTERN_1 |
3639 DP_LINK_SCRAMBLING_DISABLE)) {
3640 DRM_ERROR("failed to enable link training\n");
3641 return;
3642 }
3643
a4fc5ed6 3644 voltage = 0xff;
cdb0e95b
KP		 3645 voltage_tries = 0;
3646 loop_tries = 0;
a4fc5ed6 3647 for (;;) {
70aff66c 3648 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3649
a7c9655f 3650 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3651 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3652 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3653 break;
93f62dad 3654 }
a4fc5ed6 3655
01916270 3656 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3657 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3658 break;
3659 }
3660
3661 /* Check to see if we've tried the max voltage */
3662 for (i = 0; i < intel_dp->lane_count; i++)
3663 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3664 break;
3b4f819d 3665 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3666 ++loop_tries;
3667 if (loop_tries == 5) {
3def84b3 3668 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3669 break;
3670 }
70aff66c
JN		 3671 intel_dp_reset_link_train(intel_dp, &DP,
3672 DP_TRAINING_PATTERN_1 |
3673 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3674 voltage_tries = 0;
3675 continue;
3676 }
a4fc5ed6 3677
3cf2efb1 3678 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3679 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3680 ++voltage_tries;
b06fbda3 3681 if (voltage_tries == 5) {
3def84b3 3682 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3683 break;
3684 }
3685 } else
3686 voltage_tries = 0;
3687 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3688
70aff66c
JN		 3689 /* Update training set as requested by target */
3690 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3691 DRM_ERROR("failed to update link training\n");
3692 break;
3693 }
a4fc5ed6
KP		 3694 }
3695
33a34e4e
JB		 3696 intel_dp->DP = DP;
3697}
3698
c19b0669 3699void
33a34e4e
JB		 3700intel_dp_complete_link_train(struct intel_dp *intel_dp)
3701{
33a34e4e 3702 bool channel_eq = false;
37f80975 3703 int tries, cr_tries;
33a34e4e 3704 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3705 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3706
3707 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3708 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3709 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3710
a4fc5ed6 3711 /* channel equalization */
70aff66c 3712 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3713 training_pattern |
70aff66c
JN		 3714 DP_LINK_SCRAMBLING_DISABLE)) {
3715 DRM_ERROR("failed to start channel equalization\n");
3716 return;
3717 }
3718
a4fc5ed6 3719 tries = 0;
37f80975 3720 cr_tries = 0;
a4fc5ed6
KP		 3721 channel_eq = false;
3722 for (;;) {
70aff66c 3723 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3724
37f80975
JB		 3725 if (cr_tries > 5) {
3726 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3727 break;
3728 }
3729
a7c9655f 3730 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3731 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3732 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3733 break;
70aff66c 3734 }
a4fc5ed6 3735
37f80975 3736 /* Make sure clock is still ok */
01916270 3737 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3738 intel_dp_start_link_train(intel_dp);
70aff66c 3739 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3740 training_pattern |
70aff66c 3741 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3742 cr_tries++;
3743 continue;
3744 }
3745
1ffdff13 3746 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3747 channel_eq = true;
3748 break;
3749 }
a4fc5ed6 3750
37f80975
JB		 3751 /* Try 5 times, then try clock recovery if that fails */
3752 if (tries > 5) {
3753 intel_dp_link_down(intel_dp);
3754 intel_dp_start_link_train(intel_dp);
70aff66c 3755 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3756 training_pattern |
70aff66c 3757 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3758 tries = 0;
3759 cr_tries++;
3760 continue;
3761 }
a4fc5ed6 3762
70aff66c
JN		 3763 /* Update training set as requested by target */
3764 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3765 DRM_ERROR("failed to update link training\n");
3766 break;
3767 }
3cf2efb1 3768 ++tries;
869184a6 3769 }
3cf2efb1 3770
3ab9c637
ID		 3771 intel_dp_set_idle_link_train(intel_dp);
3772
3773 intel_dp->DP = DP;
3774
d6c0d722 3775 if (channel_eq)
07f42258 3776 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3777
3ab9c637
ID		 3778}
3779
3780void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3781{
70aff66c 3782 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3783 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3784}
3785
3786static void
ea5b213a 3787intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3788{
da63a9f2 3789 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3790 enum port port = intel_dig_port->port;
da63a9f2 3791 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3792 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3793 struct intel_crtc *intel_crtc =
3794 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3795 uint32_t DP = intel_dp->DP;
a4fc5ed6 3796
bc76e320 3797 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3798 return;
3799
0c33d8d7 3800 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3801 return;
3802
28c97730 3803 DRM_DEBUG_KMS("\n");
32f9d658 3804
bc7d38a4 3805 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3806 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3807 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3808 } else {
aad3d14d
VS		 3809 if (IS_CHERRYVIEW(dev))
3810 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3811 else
3812 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3813 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3814 }
fe255d00 3815 POSTING_READ(intel_dp->output_reg);
5eb08b69 3816
493a7081 3817 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3818 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3819 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3820
5bddd17f
EA		 3821 /* Hardware workaround: leaving our transcoder select
3822 * set to transcoder B while it's off will prevent the
3823 * corresponding HDMI output on transcoder A.
3824 *
3825 * Combine this with another hardware workaround:
3826 * transcoder select bit can only be cleared while the
3827 * port is enabled.
3828 */
3829 DP &= ~DP_PIPEB_SELECT;
3830 I915_WRITE(intel_dp->output_reg, DP);
3831
3832 /* Changes to enable or select take place the vblank
3833 * after being written.
3834 */
ff50afe9
DV		 3835 if (WARN_ON(crtc == NULL)) {
3836 /* We should never try to disable a port without a crtc
3837 * attached. For paranoia keep the code around for a
3838 * bit. */
31acbcc4
CW		 3839 POSTING_READ(intel_dp->output_reg);
3840 msleep(50);
3841 } else
ab527efc 3842 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3843 }
3844
832afda6 3845 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3846 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3847 POSTING_READ(intel_dp->output_reg);
f01eca2e 3848 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3849}
3850
26d61aad
KP		 3851static bool
3852intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3853{
a031d709
RV		 3854 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3855 struct drm_device *dev = dig_port->base.base.dev;
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3857
9d1a1031
JN		 3858 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3859 sizeof(intel_dp->dpcd)) < 0)
edb39244 3860 return false; /* aux transfer failed */
92fd8fd1 3861
a8e98153 3862 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3863
edb39244
AJ		 3864 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3865 return false; /* DPCD not present */
3866
2293bb5c
SK		 3867 /* Check if the panel supports PSR */
3868 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3869 if (is_edp(intel_dp)) {
9d1a1031
JN		 3870 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3871 intel_dp->psr_dpcd,
3872 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3873 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3874 dev_priv->psr.sink_support = true;
50003939 3875 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3876 }
50003939
JN		 3877 }
3878
06ea66b6
TP		 3879 /* Training Pattern 3 support */
3880 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3881 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3882 intel_dp->use_tps3 = true;
f8d8a672 3883 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3884 } else
3885 intel_dp->use_tps3 = false;
3886
edb39244
AJ		 3887 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3888 DP_DWN_STRM_PORT_PRESENT))
3889 return true; /* native DP sink */
3890
3891 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3892 return true; /* no per-port downstream info */
3893
9d1a1031
JN		 3894 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3895 intel_dp->downstream_ports,
3896 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3897 return false; /* downstream port status fetch failed */
3898
3899 return true;
92fd8fd1
KP		 3900}
3901
0d198328
AJ		 3902static void
3903intel_dp_probe_oui(struct intel_dp *intel_dp)
3904{
3905 u8 buf[3];
3906
3907 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3908 return;
3909
9d1a1031 3910 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3911 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3912 buf[0], buf[1], buf[2]);
3913
9d1a1031 3914 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3915 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3916 buf[0], buf[1], buf[2]);
3917}
3918
0e32b39c
DA		 3919static bool
3920intel_dp_probe_mst(struct intel_dp *intel_dp)
3921{
3922 u8 buf[1];
3923
3924 if (!intel_dp->can_mst)
3925 return false;
3926
3927 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3928 return false;
3929
0e32b39c
DA		 3930 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3931 if (buf[0] & DP_MST_CAP) {
3932 DRM_DEBUG_KMS("Sink is MST capable\n");
3933 intel_dp->is_mst = true;
3934 } else {
3935 DRM_DEBUG_KMS("Sink is not MST capable\n");
3936 intel_dp->is_mst = false;
3937 }
3938 }
0e32b39c
DA		 3939
3940 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3941 return intel_dp->is_mst;
3942}
3943
d2e216d0
RV		 3944int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3945{
3946 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3947 struct drm_device *dev = intel_dig_port->base.base.dev;
3948 struct intel_crtc *intel_crtc =
3949 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3950 u8 buf;
3951 int test_crc_count;
3952 int attempts = 6;
d2e216d0 3953
ad9dc91b 3954 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3955 return -EIO;
d2e216d0 3956
ad9dc91b 3957 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3958 return -ENOTTY;
3959
1dda5f93
RV		 3960 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3961 return -EIO;
3962
9d1a1031 3963 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3964 buf | DP_TEST_SINK_START) < 0)
bda0381e 3965 return -EIO;
d2e216d0 3966
1dda5f93 3967 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3968 return -EIO;
ad9dc91b 3969 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3970
ad9dc91b 3971 do {
1dda5f93
RV		 3972 if (drm_dp_dpcd_readb(&intel_dp->aux,
3973 DP_TEST_SINK_MISC, &buf) < 0)
3974 return -EIO;
ad9dc91b
RV		 3975 intel_wait_for_vblank(dev, intel_crtc->pipe);
3976 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3977
3978 if (attempts == 0) {
3979 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3980 return -EIO;
3981 }
d2e216d0 3982
9d1a1031 3983 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3984 return -EIO;
d2e216d0 3985
1dda5f93
RV		 3986 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3987 return -EIO;
3988 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3989 buf & ~DP_TEST_SINK_START) < 0)
3990 return -EIO;
ce31d9f4 3991
d2e216d0
RV		 3992 return 0;
3993}
3994
a60f0e38
JB		 3995static bool
3996intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3997{
9d1a1031
JN		 3998 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3999 DP_DEVICE_SERVICE_IRQ_VECTOR,
4000 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4001}
4002
0e32b39c
DA		 4003static bool
4004intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4005{
4006 int ret;
4007
4008 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4009 DP_SINK_COUNT_ESI,
4010 sink_irq_vector, 14);
4011 if (ret != 14)
4012 return false;
4013
4014 return true;
4015}
4016
a60f0e38
JB		 4017static void
4018intel_dp_handle_test_request(struct intel_dp *intel_dp)
4019{
4020 /* NAK by default */
9d1a1031 4021 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 4022}
4023
0e32b39c
DA		 4024static int
4025intel_dp_check_mst_status(struct intel_dp *intel_dp)
4026{
4027 bool bret;
4028
4029 if (intel_dp->is_mst) {
4030 u8 esi[16] = { 0 };
4031 int ret = 0;
4032 int retry;
4033 bool handled;
4034 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4035go_again:
4036 if (bret == true) {
4037
4038 /* check link status - esi[10] = 0x200c */
4039 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4040 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4041 intel_dp_start_link_train(intel_dp);
4042 intel_dp_complete_link_train(intel_dp);
4043 intel_dp_stop_link_train(intel_dp);
4044 }
4045
4046 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4047 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4048
4049 if (handled) {
4050 for (retry = 0; retry < 3; retry++) {
4051 int wret;
4052 wret = drm_dp_dpcd_write(&intel_dp->aux,
4053 DP_SINK_COUNT_ESI+1,
4054 &esi[1], 3);
4055 if (wret == 3) {
4056 break;
4057 }
4058 }
4059
4060 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4061 if (bret == true) {
4062 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4063 goto go_again;
4064 }
4065 } else
4066 ret = 0;
4067
4068 return ret;
4069 } else {
4070 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4071 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4072 intel_dp->is_mst = false;
4073 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4074 /* send a hotplug event */
4075 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4076 }
4077 }
4078 return -EINVAL;
4079}
4080
a4fc5ed6
KP		 4081/*
4082 * According to DP spec
4083 * 5.1.2:
4084 * 1. Read DPCD
4085 * 2. Configure link according to Receiver Capabilities
4086 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4087 * 4. Check link status on receipt of hot-plug interrupt
4088 */
00c09d70 4089void
ea5b213a 4090intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4091{
5b215bcf 4092 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4093 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4094 u8 sink_irq_vector;
93f62dad 4095 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4096
5b215bcf
DA		 4097 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4098
da63a9f2 4099 if (!intel_encoder->connectors_active)
d2b996ac 4100 return;
59cd09e1 4101
da63a9f2 4102 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4103 return;
4104
1a125d8a
ID		 4105 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4106 return;
4107
92fd8fd1 4108 /* Try to read receiver status if the link appears to be up */
93f62dad 4109 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4110 return;
4111 }
4112
92fd8fd1 4113 /* Now read the DPCD to see if it's actually running */
26d61aad 4114 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4115 return;
4116 }
4117
a60f0e38
JB		 4118 /* Try to read the source of the interrupt */
4119 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4120 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4121 /* Clear interrupt source */
9d1a1031
JN		 4122 drm_dp_dpcd_writeb(&intel_dp->aux,
4123 DP_DEVICE_SERVICE_IRQ_VECTOR,
4124 sink_irq_vector);
a60f0e38
JB		 4125
4126 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4127 intel_dp_handle_test_request(intel_dp);
4128 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4129 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4130 }
4131
1ffdff13 4132 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4133 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4134 intel_encoder->base.name);
33a34e4e
JB		 4135 intel_dp_start_link_train(intel_dp);
4136 intel_dp_complete_link_train(intel_dp);
3ab9c637 4137 intel_dp_stop_link_train(intel_dp);
33a34e4e 4138 }
a4fc5ed6 4139}
a4fc5ed6 4140
caf9ab24 4141/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4142static enum drm_connector_status
26d61aad 4143intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4144{
caf9ab24 4145 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4146 uint8_t type;
4147
4148 if (!intel_dp_get_dpcd(intel_dp))
4149 return connector_status_disconnected;
4150
4151 /* if there's no downstream port, we're done */
4152 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4153 return connector_status_connected;
caf9ab24
AJ		 4154
4155 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4156 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4157 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4158 uint8_t reg;
9d1a1031
JN		 4159
4160 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4161 &reg, 1) < 0)
caf9ab24 4162 return connector_status_unknown;
9d1a1031 4163
23235177
AJ		 4164 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4165 : connector_status_disconnected;
caf9ab24
AJ		 4166 }
4167
4168 /* If no HPD, poke DDC gently */
0b99836f 4169 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4170 return connector_status_connected;
caf9ab24
AJ		 4171
4172 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4173 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4174 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4175 if (type == DP_DS_PORT_TYPE_VGA ||
4176 type == DP_DS_PORT_TYPE_NON_EDID)
4177 return connector_status_unknown;
4178 } else {
4179 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4180 DP_DWN_STRM_PORT_TYPE_MASK;
4181 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4182 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4183 return connector_status_unknown;
4184 }
caf9ab24
AJ		 4185
4186 /* Anything else is out of spec, warn and ignore */
4187 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4188 return connector_status_disconnected;
71ba9000
AJ		 4189}
4190
d410b56d
CW		 4191static enum drm_connector_status
4192edp_detect(struct intel_dp *intel_dp)
4193{
4194 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4195 enum drm_connector_status status;
4196
4197 status = intel_panel_detect(dev);
4198 if (status == connector_status_unknown)
4199 status = connector_status_connected;
4200
4201 return status;
4202}
4203
5eb08b69 4204static enum drm_connector_status
a9756bb5 4205ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4206{
30add22d 4207 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4208 struct drm_i915_private *dev_priv = dev->dev_private;
4209 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4210
1b469639
DL		 4211 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4212 return connector_status_disconnected;
4213
26d61aad 4214 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4215}
4216
2a592bec
DA		 4217static int g4x_digital_port_connected(struct drm_device *dev,
4218 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4219{
a4fc5ed6 4220 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4221 uint32_t bit;
5eb08b69 4222
232a6ee9
TP		 4223 if (IS_VALLEYVIEW(dev)) {
4224 switch (intel_dig_port->port) {
4225 case PORT_B:
4226 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4227 break;
4228 case PORT_C:
4229 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4230 break;
4231 case PORT_D:
4232 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4233 break;
4234 default:
2a592bec 4235 return -EINVAL;
232a6ee9
TP		 4236 }
4237 } else {
4238 switch (intel_dig_port->port) {
4239 case PORT_B:
4240 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4241 break;
4242 case PORT_C:
4243 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4244 break;
4245 case PORT_D:
4246 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4247 break;
4248 default:
2a592bec 4249 return -EINVAL;
232a6ee9 4250 }
a4fc5ed6
KP		 4251 }
4252
10f76a38 4253 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4254 return 0;
4255 return 1;
4256}
4257
4258static enum drm_connector_status
4259g4x_dp_detect(struct intel_dp *intel_dp)
4260{
4261 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4263 int ret;
4264
4265 /* Can't disconnect eDP, but you can close the lid... */
4266 if (is_edp(intel_dp)) {
4267 enum drm_connector_status status;
4268
4269 status = intel_panel_detect(dev);
4270 if (status == connector_status_unknown)
4271 status = connector_status_connected;
4272 return status;
4273 }
4274
4275 ret = g4x_digital_port_connected(dev, intel_dig_port);
4276 if (ret == -EINVAL)
4277 return connector_status_unknown;
4278 else if (ret == 0)
a4fc5ed6
KP		 4279 return connector_status_disconnected;
4280
26d61aad 4281 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4282}
4283
8c241fef 4284static struct edid *
beb60608 4285intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4286{
beb60608 4287 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4288
9cd300e0
JN		 4289 /* use cached edid if we have one */
4290 if (intel_connector->edid) {
9cd300e0
JN		 4291 /* invalid edid */
4292 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4293 return NULL;
4294
55e9edeb 4295 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4296 } else
4297 return drm_get_edid(&intel_connector->base,
4298 &intel_dp->aux.ddc);
4299}
8c241fef 4300
beb60608
CW		 4301static void
4302intel_dp_set_edid(struct intel_dp *intel_dp)
4303{
4304 struct intel_connector *intel_connector = intel_dp->attached_connector;
4305 struct edid *edid;
8c241fef 4306
beb60608
CW		 4307 edid = intel_dp_get_edid(intel_dp);
4308 intel_connector->detect_edid = edid;
4309
4310 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4311 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4312 else
4313 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4314}
4315
beb60608
CW		 4316static void
4317intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4318{
beb60608 4319 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4320
beb60608
CW		 4321 kfree(intel_connector->detect_edid);
4322 intel_connector->detect_edid = NULL;
9cd300e0 4323
beb60608
CW		 4324 intel_dp->has_audio = false;
4325}
d6f24d0f 4326
beb60608
CW		 4327static enum intel_display_power_domain
4328intel_dp_power_get(struct intel_dp *dp)
4329{
4330 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4331 enum intel_display_power_domain power_domain;
4332
4333 power_domain = intel_display_port_power_domain(encoder);
4334 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4335
4336 return power_domain;
4337}
d6f24d0f 4338
beb60608
CW		 4339static void
4340intel_dp_power_put(struct intel_dp *dp,
4341 enum intel_display_power_domain power_domain)
4342{
4343 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4344 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4345}
4346
a9756bb5
ZW		 4347static enum drm_connector_status
4348intel_dp_detect(struct drm_connector *connector, bool force)
4349{
4350 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4353 struct drm_device *dev = connector->dev;
a9756bb5 4354 enum drm_connector_status status;
671dedd2 4355 enum intel_display_power_domain power_domain;
0e32b39c 4356 bool ret;
a9756bb5 4357
164c8598 4358 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4359 connector->base.id, connector->name);
beb60608 4360 intel_dp_unset_edid(intel_dp);
164c8598 4361
0e32b39c
DA		 4362 if (intel_dp->is_mst) {
4363 /* MST devices are disconnected from a monitor POV */
4364 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4365 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4366 return connector_status_disconnected;
0e32b39c
DA		 4367 }
4368
beb60608 4369 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4370
d410b56d
CW		 4371 /* Can't disconnect eDP, but you can close the lid... */
4372 if (is_edp(intel_dp))
4373 status = edp_detect(intel_dp);
4374 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4375 status = ironlake_dp_detect(intel_dp);
4376 else
4377 status = g4x_dp_detect(intel_dp);
4378 if (status != connector_status_connected)
c8c8fb33 4379 goto out;
a9756bb5 4380
0d198328
AJ		 4381 intel_dp_probe_oui(intel_dp);
4382
0e32b39c
DA		 4383 ret = intel_dp_probe_mst(intel_dp);
4384 if (ret) {
4385 /* if we are in MST mode then this connector
4386 won't appear connected or have anything with EDID on it */
4387 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4388 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4389 status = connector_status_disconnected;
4390 goto out;
4391 }
4392
beb60608 4393 intel_dp_set_edid(intel_dp);
a9756bb5 4394
d63885da
PZ		 4395 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4396 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4397 status = connector_status_connected;
4398
4399out:
beb60608 4400 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4401 return status;
a4fc5ed6
KP		 4402}
4403
beb60608
CW		 4404static void
4405intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4406{
df0e9248 4407 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4408 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4409 enum intel_display_power_domain power_domain;
a4fc5ed6 4410
beb60608
CW		 4411 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4412 connector->base.id, connector->name);
4413 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4414
beb60608
CW		 4415 if (connector->status != connector_status_connected)
4416 return;
671dedd2 4417
beb60608
CW		 4418 power_domain = intel_dp_power_get(intel_dp);
4419
4420 intel_dp_set_edid(intel_dp);
4421
4422 intel_dp_power_put(intel_dp, power_domain);
4423
4424 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4425 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4426}
4427
4428static int intel_dp_get_modes(struct drm_connector *connector)
4429{
4430 struct intel_connector *intel_connector = to_intel_connector(connector);
4431 struct edid *edid;
4432
4433 edid = intel_connector->detect_edid;
4434 if (edid) {
4435 int ret = intel_connector_update_modes(connector, edid);
4436 if (ret)
4437 return ret;
4438 }
32f9d658 4439
f8779fda 4440 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4441 if (is_edp(intel_attached_dp(connector)) &&
4442 intel_connector->panel.fixed_mode) {
f8779fda 4443 struct drm_display_mode *mode;
beb60608
CW		 4444
4445 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4446 intel_connector->panel.fixed_mode);
f8779fda 4447 if (mode) {
32f9d658
ZW		 4448 drm_mode_probed_add(connector, mode);
4449 return 1;
4450 }
4451 }
beb60608 4452
32f9d658 4453 return 0;
a4fc5ed6
KP		 4454}
4455
1aad7ac0
CW		 4456static bool
4457intel_dp_detect_audio(struct drm_connector *connector)
4458{
1aad7ac0 4459 bool has_audio = false;
beb60608 4460 struct edid *edid;
1aad7ac0 4461
beb60608
CW		 4462 edid = to_intel_connector(connector)->detect_edid;
4463 if (edid)
1aad7ac0 4464 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4465
1aad7ac0
CW		 4466 return has_audio;
4467}
4468
f684960e
CW		 4469static int
4470intel_dp_set_property(struct drm_connector *connector,
4471 struct drm_property *property,
4472 uint64_t val)
4473{
e953fd7b 4474 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4475 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4476 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4477 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4478 int ret;
4479
662595df 4480 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4481 if (ret)
4482 return ret;
4483
3f43c48d 4484 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4485 int i = val;
4486 bool has_audio;
4487
4488 if (i == intel_dp->force_audio)
f684960e
CW		 4489 return 0;
4490
1aad7ac0 4491 intel_dp->force_audio = i;
f684960e 4492
c3e5f67b 4493 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4494 has_audio = intel_dp_detect_audio(connector);
4495 else
c3e5f67b 4496 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4497
4498 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4499 return 0;
4500
1aad7ac0 4501 intel_dp->has_audio = has_audio;
f684960e
CW		 4502 goto done;
4503 }
4504
e953fd7b 4505 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4506 bool old_auto = intel_dp->color_range_auto;
4507 uint32_t old_range = intel_dp->color_range;
4508
55bc60db
VS		 4509 switch (val) {
4510 case INTEL_BROADCAST_RGB_AUTO:
4511 intel_dp->color_range_auto = true;
4512 break;
4513 case INTEL_BROADCAST_RGB_FULL:
4514 intel_dp->color_range_auto = false;
4515 intel_dp->color_range = 0;
4516 break;
4517 case INTEL_BROADCAST_RGB_LIMITED:
4518 intel_dp->color_range_auto = false;
4519 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4520 break;
4521 default:
4522 return -EINVAL;
4523 }
ae4edb80
DV		 4524
4525 if (old_auto == intel_dp->color_range_auto &&
4526 old_range == intel_dp->color_range)
4527 return 0;
4528
e953fd7b
CW		 4529 goto done;
4530 }
4531
53b41837
YN		 4532 if (is_edp(intel_dp) &&
4533 property == connector->dev->mode_config.scaling_mode_property) {
4534 if (val == DRM_MODE_SCALE_NONE) {
4535 DRM_DEBUG_KMS("no scaling not supported\n");
4536 return -EINVAL;
4537 }
4538
4539 if (intel_connector->panel.fitting_mode == val) {
4540 /* the eDP scaling property is not changed */
4541 return 0;
4542 }
4543 intel_connector->panel.fitting_mode = val;
4544
4545 goto done;
4546 }
4547
f684960e
CW		 4548 return -EINVAL;
4549
4550done:
c0c36b94
CW		 4551 if (intel_encoder->base.crtc)
4552 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4553
4554 return 0;
4555}
4556
a4fc5ed6 4557static void
73845adf 4558intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4559{
1d508706 4560 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4561
10e972d3 4562 kfree(intel_connector->detect_edid);
beb60608 4563
9cd300e0
JN		 4564 if (!IS_ERR_OR_NULL(intel_connector->edid))
4565 kfree(intel_connector->edid);
4566
acd8db10
PZ		 4567 /* Can't call is_edp() since the encoder may have been destroyed
4568 * already. */
4569 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4570 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4571
a4fc5ed6 4572 drm_connector_cleanup(connector);
55f78c43 4573 kfree(connector);
a4fc5ed6
KP		 4574}
4575
00c09d70 4576void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4577{
da63a9f2
PZ		 4578 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4579 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4580
4f71d0cb 4581 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4582 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4583 drm_encoder_cleanup(encoder);
bd943159
KP		 4584 if (is_edp(intel_dp)) {
4585 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4586 /*
4587 * vdd might still be enabled do to the delayed vdd off.
4588 * Make sure vdd is actually turned off here.
4589 */
773538e8 4590 pps_lock(intel_dp);
4be73780 4591 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4592 pps_unlock(intel_dp);
4593
01527b31
CT		 4594 if (intel_dp->edp_notifier.notifier_call) {
4595 unregister_reboot_notifier(&intel_dp->edp_notifier);
4596 intel_dp->edp_notifier.notifier_call = NULL;
4597 }
bd943159 4598 }
da63a9f2 4599 kfree(intel_dig_port);
24d05927
DV		 4600}
4601
07f9cd0b
ID		 4602static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4603{
4604 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4605
4606 if (!is_edp(intel_dp))
4607 return;
4608
951468f3
VS		 4609 /*
4610 * vdd might still be enabled do to the delayed vdd off.
4611 * Make sure vdd is actually turned off here.
4612 */
773538e8 4613 pps_lock(intel_dp);
07f9cd0b 4614 edp_panel_vdd_off_sync(intel_dp);
773538e8 4615 pps_unlock(intel_dp);
07f9cd0b
ID		 4616}
4617
6d93c0c4
ID		 4618static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4619{
4620 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4621}
4622
a4fc5ed6 4623static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4624 .dpms = intel_connector_dpms,
a4fc5ed6 4625 .detect = intel_dp_detect,
beb60608 4626 .force = intel_dp_force,
a4fc5ed6 4627 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4628 .set_property = intel_dp_set_property,
73845adf 4629 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4630};
4631
4632static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4633 .get_modes = intel_dp_get_modes,
4634 .mode_valid = intel_dp_mode_valid,
df0e9248 4635 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4636};
4637
a4fc5ed6 4638static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4639 .reset = intel_dp_encoder_reset,
24d05927 4640 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4641};
4642
0e32b39c 4643void
21d40d37 4644intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4645{
0e32b39c 4646 return;
c8110e52 4647}
6207937d 4648
13cf5504
DA		 4649bool
4650intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4651{
4652 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4653 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4654 struct drm_device *dev = intel_dig_port->base.base.dev;
4655 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4656 enum intel_display_power_domain power_domain;
4657 bool ret = true;
4658
0e32b39c
DA		 4659 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4660 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4661
26fbb774
VS		 4662 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4663 port_name(intel_dig_port->port),
0e32b39c 4664 long_hpd ? "long" : "short");
13cf5504 4665
1c767b33
ID		 4666 power_domain = intel_display_port_power_domain(intel_encoder);
4667 intel_display_power_get(dev_priv, power_domain);
4668
0e32b39c 4669 if (long_hpd) {
2a592bec
DA		 4670
4671 if (HAS_PCH_SPLIT(dev)) {
4672 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4673 goto mst_fail;
4674 } else {
4675 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4676 goto mst_fail;
4677 }
0e32b39c
DA		 4678
4679 if (!intel_dp_get_dpcd(intel_dp)) {
4680 goto mst_fail;
4681 }
4682
4683 intel_dp_probe_oui(intel_dp);
4684
4685 if (!intel_dp_probe_mst(intel_dp))
4686 goto mst_fail;
4687
4688 } else {
4689 if (intel_dp->is_mst) {
1c767b33 4690 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4691 goto mst_fail;
4692 }
4693
4694 if (!intel_dp->is_mst) {
4695 /*
4696 * we'll check the link status via the normal hot plug path later -
4697 * but for short hpds we should check it now
4698 */
5b215bcf 4699 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4700 intel_dp_check_link_status(intel_dp);
5b215bcf 4701 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4702 }
4703 }
1c767b33
ID		 4704 ret = false;
4705 goto put_power;
0e32b39c
DA		 4706mst_fail:
4707 /* if we were in MST mode, and device is not there get out of MST mode */
4708 if (intel_dp->is_mst) {
4709 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4710 intel_dp->is_mst = false;
4711 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4712 }
1c767b33
ID		 4713put_power:
4714 intel_display_power_put(dev_priv, power_domain);
4715
4716 return ret;
13cf5504
DA		 4717}
4718
e3421a18
ZW		 4719/* Return which DP Port should be selected for Transcoder DP control */
4720int
0206e353 4721intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4722{
4723 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4724 struct intel_encoder *intel_encoder;
4725 struct intel_dp *intel_dp;
e3421a18 4726
fa90ecef
PZ		 4727 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4728 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4729
fa90ecef
PZ		 4730 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4731 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4732 return intel_dp->output_reg;
e3421a18 4733 }
ea5b213a 4734
e3421a18
ZW		 4735 return -1;
4736}
4737
36e83a18 4738/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4739bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4740{
4741 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4742 union child_device_config *p_child;
36e83a18 4743 int i;
5d8a7752
VS		 4744 static const short port_mapping[] = {
4745 [PORT_B] = PORT_IDPB,
4746 [PORT_C] = PORT_IDPC,
4747 [PORT_D] = PORT_IDPD,
4748 };
36e83a18 4749
3b32a35b
VS		 4750 if (port == PORT_A)
4751 return true;
4752
41aa3448 4753 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4754 return false;
4755
41aa3448
RV		 4756 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4757 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4758
5d8a7752 4759 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4760 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4761 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4762 return true;
4763 }
4764 return false;
4765}
4766
0e32b39c 4767void
f684960e
CW		 4768intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4769{
53b41837
YN		 4770 struct intel_connector *intel_connector = to_intel_connector(connector);
4771
3f43c48d 4772 intel_attach_force_audio_property(connector);
e953fd7b 4773 intel_attach_broadcast_rgb_property(connector);
55bc60db 4774 intel_dp->color_range_auto = true;
53b41837
YN		 4775
4776 if (is_edp(intel_dp)) {
4777 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4778 drm_object_attach_property(
4779 &connector->base,
53b41837 4780 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4781 DRM_MODE_SCALE_ASPECT);
4782 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4783 }
f684960e
CW		 4784}
4785
dada1a9f
ID		 4786static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4787{
4788 intel_dp->last_power_cycle = jiffies;
4789 intel_dp->last_power_on = jiffies;
4790 intel_dp->last_backlight_off = jiffies;
4791}
4792
67a54566
DV		 4793static void
4794intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4795 struct intel_dp *intel_dp)
67a54566
DV		 4796{
4797 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4798 struct edp_power_seq cur, vbt, spec,
4799 *final = &intel_dp->pps_delays;
67a54566 4800 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4801 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4802
e39b999a
VS		 4803 lockdep_assert_held(&dev_priv->pps_mutex);
4804
81ddbc69
VS		 4805 /* already initialized? */
4806 if (final->t11_t12 != 0)
4807 return;
4808
453c5420 4809 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4810 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4811 pp_on_reg = PCH_PP_ON_DELAYS;
4812 pp_off_reg = PCH_PP_OFF_DELAYS;
4813 pp_div_reg = PCH_PP_DIVISOR;
4814 } else {
bf13e81b
JN		 4815 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4816
4817 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4818 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4819 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4820 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4821 }
67a54566
DV		 4822
4823 /* Workaround: Need to write PP_CONTROL with the unlock key as
4824 * the very first thing. */
453c5420 4825 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4826 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4827
453c5420
JB		 4828 pp_on = I915_READ(pp_on_reg);
4829 pp_off = I915_READ(pp_off_reg);
4830 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4831
4832 /* Pull timing values out of registers */
4833 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4834 PANEL_POWER_UP_DELAY_SHIFT;
4835
4836 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4837 PANEL_LIGHT_ON_DELAY_SHIFT;
4838
4839 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4840 PANEL_LIGHT_OFF_DELAY_SHIFT;
4841
4842 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4843 PANEL_POWER_DOWN_DELAY_SHIFT;
4844
4845 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4846 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4847
4848 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4849 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4850
41aa3448 4851 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4852
4853 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4854 * our hw here, which are all in 100usec. */
4855 spec.t1_t3 = 210 * 10;
4856 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4857 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4858 spec.t10 = 500 * 10;
4859 /* This one is special and actually in units of 100ms, but zero
4860 * based in the hw (so we need to add 100 ms). But the sw vbt
4861 * table multiplies it with 1000 to make it in units of 100usec,
4862 * too. */
4863 spec.t11_t12 = (510 + 100) * 10;
4864
4865 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4866 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4867
4868 /* Use the max of the register settings and vbt. If both are
4869 * unset, fall back to the spec limits. */
36b5f425 4870#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4871 spec.field : \
4872 max(cur.field, vbt.field))
4873 assign_final(t1_t3);
4874 assign_final(t8);
4875 assign_final(t9);
4876 assign_final(t10);
4877 assign_final(t11_t12);
4878#undef assign_final
4879
36b5f425 4880#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4881 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4882 intel_dp->backlight_on_delay = get_delay(t8);
4883 intel_dp->backlight_off_delay = get_delay(t9);
4884 intel_dp->panel_power_down_delay = get_delay(t10);
4885 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4886#undef get_delay
4887
f30d26e4
JN		 4888 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4889 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4890 intel_dp->panel_power_cycle_delay);
4891
4892 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4893 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4894}
4895
4896static void
4897intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4898 struct intel_dp *intel_dp)
f30d26e4
JN		 4899{
4900 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4901 u32 pp_on, pp_off, pp_div, port_sel = 0;
4902 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4903 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4904 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4905 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4906
e39b999a 4907 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4908
4909 if (HAS_PCH_SPLIT(dev)) {
4910 pp_on_reg = PCH_PP_ON_DELAYS;
4911 pp_off_reg = PCH_PP_OFF_DELAYS;
4912 pp_div_reg = PCH_PP_DIVISOR;
4913 } else {
bf13e81b
JN		 4914 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4915
4916 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4917 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4918 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4919 }
4920
b2f19d1a
PZ		 4921 /*
4922 * And finally store the new values in the power sequencer. The
4923 * backlight delays are set to 1 because we do manual waits on them. For
4924 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4925 * we'll end up waiting for the backlight off delay twice: once when we
4926 * do the manual sleep, and once when we disable the panel and wait for
4927 * the PP_STATUS bit to become zero.
4928 */
f30d26e4 4929 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4930 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4931 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4932 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4933 /* Compute the divisor for the pp clock, simply match the Bspec
4934 * formula. */
453c5420 4935 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4936 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4937 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4938
4939 /* Haswell doesn't have any port selection bits for the panel
4940 * power sequencer any more. */
bc7d38a4 4941 if (IS_VALLEYVIEW(dev)) {
ad933b56 4942 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4943 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4944 if (port == PORT_A)
a24c144c 4945 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4946 else
a24c144c 4947 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4948 }
4949
453c5420
JB		 4950 pp_on |= port_sel;
4951
4952 I915_WRITE(pp_on_reg, pp_on);
4953 I915_WRITE(pp_off_reg, pp_off);
4954 I915_WRITE(pp_div_reg, pp_div);
67a54566 4955
67a54566 4956 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4957 I915_READ(pp_on_reg),
4958 I915_READ(pp_off_reg),
4959 I915_READ(pp_div_reg));
f684960e
CW		 4960}
4961
439d7ac0
PB		 4962void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4963{
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 struct intel_encoder *encoder;
4966 struct intel_dp *intel_dp = NULL;
4967 struct intel_crtc_config *config = NULL;
4968 struct intel_crtc *intel_crtc = NULL;
4969 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4970 u32 reg, val;
4971 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4972
4973 if (refresh_rate <= 0) {
4974 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4975 return;
4976 }
4977
4978 if (intel_connector == NULL) {
4979 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4980 return;
4981 }
4982
1fcc9d1c
DV		 4983 /*
4984 * FIXME: This needs proper synchronization with psr state. But really
4985 * hard to tell without seeing the user of this function of this code.
4986 * Check locking and ordering once that lands.
4987 */
439d7ac0
PB		 4988 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4989 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4990 return;
4991 }
4992
4993 encoder = intel_attached_encoder(&intel_connector->base);
4994 intel_dp = enc_to_intel_dp(&encoder->base);
4995 intel_crtc = encoder->new_crtc;
4996
4997 if (!intel_crtc) {
4998 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4999 return;
5000 }
5001
5002 config = &intel_crtc->config;
5003
5004 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
5005 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5006 return;
5007 }
5008
5009 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
5010 index = DRRS_LOW_RR;
5011
5012 if (index == intel_dp->drrs_state.refresh_rate_type) {
5013 DRM_DEBUG_KMS(
5014 "DRRS requested for previously set RR...ignoring\n");
5015 return;
5016 }
5017
5018 if (!intel_crtc->active) {
5019 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5020 return;
5021 }
5022
5023 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
5024 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
5025 val = I915_READ(reg);
5026 if (index > DRRS_HIGH_RR) {
5027 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 5028 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 5029 } else {
5030 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5031 }
5032 I915_WRITE(reg, val);
5033 }
5034
5035 /*
5036 * mutex taken to ensure that there is no race between differnt
5037 * drrs calls trying to update refresh rate. This scenario may occur
5038 * in future when idleness detection based DRRS in kernel and
5039 * possible calls from user space to set differnt RR are made.
5040 */
5041
5042 mutex_lock(&intel_dp->drrs_state.mutex);
5043
5044 intel_dp->drrs_state.refresh_rate_type = index;
5045
5046 mutex_unlock(&intel_dp->drrs_state.mutex);
5047
5048 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5049}
5050
4f9db5b5
PB		 5051static struct drm_display_mode *
5052intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
5053 struct intel_connector *intel_connector,
5054 struct drm_display_mode *fixed_mode)
5055{
5056 struct drm_connector *connector = &intel_connector->base;
5057 struct intel_dp *intel_dp = &intel_dig_port->dp;
5058 struct drm_device *dev = intel_dig_port->base.base.dev;
5059 struct drm_i915_private *dev_priv = dev->dev_private;
5060 struct drm_display_mode *downclock_mode = NULL;
5061
5062 if (INTEL_INFO(dev)->gen <= 6) {
5063 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5064 return NULL;
5065 }
5066
5067 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5068 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5069 return NULL;
5070 }
5071
5072 downclock_mode = intel_find_panel_downclock
5073 (dev, fixed_mode, connector);
5074
5075 if (!downclock_mode) {
4079b8d1 5076 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 5077 return NULL;
5078 }
5079
439d7ac0
PB		 5080 dev_priv->drrs.connector = intel_connector;
5081
5082 mutex_init(&intel_dp->drrs_state.mutex);
5083
4f9db5b5
PB		 5084 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5085
5086 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5087 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5088 return downclock_mode;
5089}
5090
aba86890
ID		 5091void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5092{
5093 struct drm_device *dev = intel_encoder->base.dev;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 struct intel_dp *intel_dp;
5096 enum intel_display_power_domain power_domain;
5097
5098 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5099 return;
5100
5101 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5102
5103 pps_lock(intel_dp);
5104
aba86890 5105 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5106 goto out;
aba86890
ID		 5107 /*
5108 * The VDD bit needs a power domain reference, so if the bit is
5109 * already enabled when we boot or resume, grab this reference and
5110 * schedule a vdd off, so we don't hold on to the reference
5111 * indefinitely.
5112 */
5113 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5114 power_domain = intel_display_port_power_domain(intel_encoder);
5115 intel_display_power_get(dev_priv, power_domain);
5116
5117 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5118 out:
773538e8 5119 pps_unlock(intel_dp);
aba86890
ID		 5120}
5121
ed92f0b2 5122static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5123 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5124{
5125 struct drm_connector *connector = &intel_connector->base;
5126 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5127 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5128 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5131 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5132 bool has_dpcd;
5133 struct drm_display_mode *scan;
5134 struct edid *edid;
5135
4f9db5b5
PB		 5136 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5137
ed92f0b2
PZ		 5138 if (!is_edp(intel_dp))
5139 return true;
5140
aba86890 5141 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5142
ed92f0b2 5143 /* Cache DPCD and EDID for edp. */
ed92f0b2 5144 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5145
5146 if (has_dpcd) {
5147 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5148 dev_priv->no_aux_handshake =
5149 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5150 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5151 } else {
5152 /* if this fails, presume the device is a ghost */
5153 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5154 return false;
5155 }
5156
5157 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5158 pps_lock(intel_dp);
36b5f425 5159 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5160 pps_unlock(intel_dp);
ed92f0b2 5161
060c8778 5162 mutex_lock(&dev->mode_config.mutex);
0b99836f 5163 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5164 if (edid) {
5165 if (drm_add_edid_modes(connector, edid)) {
5166 drm_mode_connector_update_edid_property(connector,
5167 edid);
5168 drm_edid_to_eld(connector, edid);
5169 } else {
5170 kfree(edid);
5171 edid = ERR_PTR(-EINVAL);
5172 }
5173 } else {
5174 edid = ERR_PTR(-ENOENT);
5175 }
5176 intel_connector->edid = edid;
5177
5178 /* prefer fixed mode from EDID if available */
5179 list_for_each_entry(scan, &connector->probed_modes, head) {
5180 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5181 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5182 downclock_mode = intel_dp_drrs_init(
5183 intel_dig_port,
5184 intel_connector, fixed_mode);
ed92f0b2
PZ		 5185 break;
5186 }
5187 }
5188
5189 /* fallback to VBT if available for eDP */
5190 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5191 fixed_mode = drm_mode_duplicate(dev,
5192 dev_priv->vbt.lfp_lvds_vbt_mode);
5193 if (fixed_mode)
5194 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5195 }
060c8778 5196 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5197
01527b31
CT		 5198 if (IS_VALLEYVIEW(dev)) {
5199 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5200 register_reboot_notifier(&intel_dp->edp_notifier);
5201 }
5202
4f9db5b5 5203 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5204 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5205 intel_panel_setup_backlight(connector);
5206
5207 return true;
5208}
5209
16c25533 5210bool
f0fec3f2
PZ		 5211intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5212 struct intel_connector *intel_connector)
a4fc5ed6 5213{
f0fec3f2
PZ		 5214 struct drm_connector *connector = &intel_connector->base;
5215 struct intel_dp *intel_dp = &intel_dig_port->dp;
5216 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5217 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5218 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5219 enum port port = intel_dig_port->port;
0b99836f 5220 int type;
a4fc5ed6 5221
a4a5d2f8
VS		 5222 intel_dp->pps_pipe = INVALID_PIPE;
5223
ec5b01dd 5224 /* intel_dp vfuncs */
b6b5e383
DL		 5225 if (INTEL_INFO(dev)->gen >= 9)
5226 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5227 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5228 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5229 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5230 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5231 else if (HAS_PCH_SPLIT(dev))
5232 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5233 else
5234 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5235
b9ca5fad
DL		 5236 if (INTEL_INFO(dev)->gen >= 9)
5237 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5238 else
5239 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5240
0767935e
DV		 5241 /* Preserve the current hw state. */
5242 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5243 intel_dp->attached_connector = intel_connector;
3d3dc149 5244
3b32a35b 5245 if (intel_dp_is_edp(dev, port))
b329530c 5246 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5247 else
5248 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5249
f7d24902
ID		 5250 /*
5251 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5252 * for DP the encoder type can be set by the caller to
5253 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5254 */
5255 if (type == DRM_MODE_CONNECTOR_eDP)
5256 intel_encoder->type = INTEL_OUTPUT_EDP;
5257
c17ed5b5
VS		 5258 /* eDP only on port B and/or C on vlv/chv */
5259 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5260 port != PORT_B && port != PORT_C))
5261 return false;
5262
e7281eab
ID		 5263 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5264 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5265 port_name(port));
5266
b329530c 5267 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5268 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5269
a4fc5ed6
KP		 5270 connector->interlace_allowed = true;
5271 connector->doublescan_allowed = 0;
5272
f0fec3f2 5273 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5274 edp_panel_vdd_work);
a4fc5ed6 5275
df0e9248 5276 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5277 drm_connector_register(connector);
a4fc5ed6 5278
affa9354 5279 if (HAS_DDI(dev))
bcbc889b
PZ		 5280 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5281 else
5282 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5283 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5284
0b99836f 5285 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5286 switch (port) {
5287 case PORT_A:
1d843f9d 5288 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5289 break;
5290 case PORT_B:
1d843f9d 5291 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5292 break;
5293 case PORT_C:
1d843f9d 5294 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5295 break;
5296 case PORT_D:
1d843f9d 5297 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5298 break;
5299 default:
ad1c0b19 5300 BUG();
5eb08b69
ZW		 5301 }
5302
dada1a9f 5303 if (is_edp(intel_dp)) {
773538e8 5304 pps_lock(intel_dp);
a4a5d2f8
VS		 5305 if (IS_VALLEYVIEW(dev)) {
5306 vlv_initial_power_sequencer_setup(intel_dp);
5307 } else {
5308 intel_dp_init_panel_power_timestamps(intel_dp);
36b5f425 5309 intel_dp_init_panel_power_sequencer(dev, intel_dp);
a4a5d2f8 5310 }
773538e8 5311 pps_unlock(intel_dp);
dada1a9f 5312 }
0095e6dc 5313
9d1a1031 5314 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5315
0e32b39c
DA		 5316 /* init MST on ports that can support it */
5317 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5318 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5319 intel_dp_mst_encoder_init(intel_dig_port,
5320 intel_connector->base.base.id);
0e32b39c
DA		 5321 }
5322 }
5323
36b5f425 5324 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5325 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5326 if (is_edp(intel_dp)) {
5327 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5328 /*
5329 * vdd might still be enabled do to the delayed vdd off.
5330 * Make sure vdd is actually turned off here.
5331 */
773538e8 5332 pps_lock(intel_dp);
4be73780 5333 edp_panel_vdd_off_sync(intel_dp);
773538e8 5334 pps_unlock(intel_dp);
15b1d171 5335 }
34ea3d38 5336 drm_connector_unregister(connector);
b2f246a8 5337 drm_connector_cleanup(connector);
16c25533 5338 return false;
b2f246a8 5339 }
32f9d658 5340
f684960e
CW		 5341 intel_dp_add_properties(intel_dp, connector);
5342
a4fc5ed6
KP		 5343 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5344 * 0xd. Failure to do so will result in spurious interrupts being
5345 * generated on the port when a cable is not attached.
5346 */
5347 if (IS_G4X(dev) && !IS_GM45(dev)) {
5348 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5349 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5350 }
16c25533
PZ		 5351
5352 return true;
a4fc5ed6 5353}
f0fec3f2
PZ		 5354
5355void
5356intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5357{
13cf5504 5358 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5359 struct intel_digital_port *intel_dig_port;
5360 struct intel_encoder *intel_encoder;
5361 struct drm_encoder *encoder;
5362 struct intel_connector *intel_connector;
5363
b14c5679 5364 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5365 if (!intel_dig_port)
5366 return;
5367
b14c5679 5368 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5369 if (!intel_connector) {
5370 kfree(intel_dig_port);
5371 return;
5372 }
5373
5374 intel_encoder = &intel_dig_port->base;
5375 encoder = &intel_encoder->base;
5376
5377 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5378 DRM_MODE_ENCODER_TMDS);
5379
5bfe2ac0 5380 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5381 intel_encoder->disable = intel_disable_dp;
00c09d70 5382 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5383 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5384 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5385 if (IS_CHERRYVIEW(dev)) {
9197c88b 5386 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5387 intel_encoder->pre_enable = chv_pre_enable_dp;
5388 intel_encoder->enable = vlv_enable_dp;
580d3811 5389 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5390 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5391 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5392 intel_encoder->pre_enable = vlv_pre_enable_dp;
5393 intel_encoder->enable = vlv_enable_dp;
49277c31 5394 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5395 } else {
ecff4f3b
JN		 5396 intel_encoder->pre_enable = g4x_pre_enable_dp;
5397 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5398 if (INTEL_INFO(dev)->gen >= 5)
5399 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5400 }
f0fec3f2 5401
174edf1f 5402 intel_dig_port->port = port;
f0fec3f2
PZ		 5403 intel_dig_port->dp.output_reg = output_reg;
5404
00c09d70 5405 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5406 if (IS_CHERRYVIEW(dev)) {
5407 if (port == PORT_D)
5408 intel_encoder->crtc_mask = 1 << 2;
5409 else
5410 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5411 } else {
5412 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5413 }
bc079e8b 5414 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5415 intel_encoder->hot_plug = intel_dp_hot_plug;
5416
13cf5504
DA		 5417 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5418 dev_priv->hpd_irq_port[port] = intel_dig_port;
5419
15b1d171
PZ		 5420 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5421 drm_encoder_cleanup(encoder);
5422 kfree(intel_dig_port);
b2f246a8 5423 kfree(intel_connector);
15b1d171 5424 }
f0fec3f2 5425}
0e32b39c
DA		 5426
5427void intel_dp_mst_suspend(struct drm_device *dev)
5428{
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5430 int i;
5431
5432 /* disable MST */
5433 for (i = 0; i < I915_MAX_PORTS; i++) {
5434 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5435 if (!intel_dig_port)
5436 continue;
5437
5438 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5439 if (!intel_dig_port->dp.can_mst)
5440 continue;
5441 if (intel_dig_port->dp.is_mst)
5442 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5443 }
5444 }
5445}
5446
5447void intel_dp_mst_resume(struct drm_device *dev)
5448{
5449 struct drm_i915_private *dev_priv = dev->dev_private;
5450 int i;
5451
5452 for (i = 0; i < I915_MAX_PORTS; i++) {
5453 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5454 if (!intel_dig_port)
5455 continue;
5456 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5457 int ret;
5458
5459 if (!intel_dig_port->dp.can_mst)
5460 continue;
5461
5462 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5463 if (ret != 0) {
5464 intel_dp_check_mst_status(&intel_dig_port->dp);
5465 }
5466 }
5467 }
5468}
Linux 6.x block layer and io_uring tree(s)