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drm/i915: Reset the HEAD pointer for the ring after writing START
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
ad933b56 311 if (port_sel == PANEL_PORT_SELECT_VLV(port))
bf13e81b
JN		 312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
01527b31
CT		 339/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340 This function only applicable when panel PM state is not to be tracked */
341static int edp_notify_handler(struct notifier_block *this, unsigned long code,
342 void *unused)
343{
344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
345 edp_notifier);
346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 u32 pp_div;
349 u32 pp_ctrl_reg, pp_div_reg;
350 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
351
352 if (!is_edp(intel_dp) || code != SYS_RESTART)
353 return 0;
354
355 if (IS_VALLEYVIEW(dev)) {
356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
358 pp_div = I915_READ(pp_div_reg);
359 pp_div &= PP_REFERENCE_DIVIDER_MASK;
360
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg, pp_div | 0x1F);
363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
364 msleep(intel_dp->panel_power_cycle_delay);
365 }
366
367 return 0;
368}
369
4be73780 370static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 371{
30add22d 372 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 373 struct drm_i915_private *dev_priv = dev->dev_private;
374
bf13e81b 375 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 376}
377
4be73780 378static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 379{
30add22d 380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 381 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
383 struct intel_encoder *intel_encoder = &intel_dig_port->base;
384 enum intel_display_power_domain power_domain;
ebf33b18 385
bb4932c4
ID		 386 power_domain = intel_display_port_power_domain(intel_encoder);
387 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 388 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 389}
390
9b984dae
KP		 391static void
392intel_dp_check_edp(struct intel_dp *intel_dp)
393{
30add22d 394 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 395 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 396
9b984dae
KP		 397 if (!is_edp(intel_dp))
398 return;
453c5420 399
4be73780 400 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 401 WARN(1, "eDP powered off while attempting aux channel communication.\n");
402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 403 I915_READ(_pp_stat_reg(intel_dp)),
404 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 405 }
406}
407
9ee32fea
DV		 408static uint32_t
409intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
410{
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct drm_device *dev = intel_dig_port->base.base.dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 414 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 415 uint32_t status;
416 bool done;
417
ef04f00d 418#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 419 if (has_aux_irq)
b18ac466 420 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 421 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 422 else
423 done = wait_for_atomic(C, 10) == 0;
424 if (!done)
425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
426 has_aux_irq);
427#undef C
428
429 return status;
430}
431
ec5b01dd 432static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 433{
174edf1f
PZ		 434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 436
ec5b01dd
DL		 437 /*
438 * The clock divider is based off the hrawclk, and would like to run at
439 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 440 */
ec5b01dd
DL		 441 return index ? 0 : intel_hrawclk(dev) / 2;
442}
443
444static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448
449 if (index)
450 return 0;
451
452 if (intel_dig_port->port == PORT_A) {
453 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 454 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 455 else
b84a1cf8 456 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 457 } else {
458 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
459 }
460}
461
462static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
463{
464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
465 struct drm_device *dev = intel_dig_port->base.base.dev;
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 if (intel_dig_port->port == PORT_A) {
469 if (index)
470 return 0;
471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 472 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
473 /* Workaround for non-ULT HSW */
bc86625a
CW		 474 switch (index) {
475 case 0: return 63;
476 case 1: return 72;
477 default: return 0;
478 }
ec5b01dd 479 } else {
bc86625a 480 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 481 }
b84a1cf8
RV		 482}
483
ec5b01dd
DL		 484static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
485{
486 return index ? 0 : 100;
487}
488
5ed12a19
DL		 489static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
490 bool has_aux_irq,
491 int send_bytes,
492 uint32_t aux_clock_divider)
493{
494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
495 struct drm_device *dev = intel_dig_port->base.base.dev;
496 uint32_t precharge, timeout;
497
498 if (IS_GEN6(dev))
499 precharge = 3;
500 else
501 precharge = 5;
502
503 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
504 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
505 else
506 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
507
508 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 509 DP_AUX_CH_CTL_DONE |
5ed12a19 510 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 511 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 512 timeout |
788d4433 513 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 514 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
515 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 516 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 517}
518
b84a1cf8
RV		 519static int
520intel_dp_aux_ch(struct intel_dp *intel_dp,
521 uint8_t *send, int send_bytes,
522 uint8_t *recv, int recv_size)
523{
524 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
525 struct drm_device *dev = intel_dig_port->base.base.dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
528 uint32_t ch_data = ch_ctl + 4;
bc86625a 529 uint32_t aux_clock_divider;
b84a1cf8
RV		 530 int i, ret, recv_bytes;
531 uint32_t status;
5ed12a19 532 int try, clock = 0;
4e6b788c 533 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 534 bool vdd;
535
72c3500a
VS		 536 /*
537 * We will be called with VDD already enabled for dpcd/edid/oui reads.
538 * In such cases we want to leave VDD enabled and it's up to upper layers
539 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
540 * ourselves.
541 */
1e0560e0 542 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 543
544 /* dp aux is extremely sensitive to irq latency, hence request the
545 * lowest possible wakeup latency and so prevent the cpu from going into
546 * deep sleep states.
547 */
548 pm_qos_update_request(&dev_priv->pm_qos, 0);
549
550 intel_dp_check_edp(intel_dp);
5eb08b69 551
c67a470b
PZ		 552 intel_aux_display_runtime_get(dev_priv);
553
11bee43e
JB		 554 /* Try to wait for any previous AUX channel activity */
555 for (try = 0; try < 3; try++) {
ef04f00d 556 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 557 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
558 break;
559 msleep(1);
560 }
561
562 if (try == 3) {
563 WARN(1, "dp_aux_ch not started status 0x%08x\n",
564 I915_READ(ch_ctl));
9ee32fea
DV		 565 ret = -EBUSY;
566 goto out;
4f7f7b7e
CW		 567 }
568
46a5ae9f
PZ		 569 /* Only 5 data registers! */
570 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
571 ret = -E2BIG;
572 goto out;
573 }
574
ec5b01dd 575 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 576 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
577 has_aux_irq,
578 send_bytes,
579 aux_clock_divider);
5ed12a19 580
bc86625a
CW		 581 /* Must try at least 3 times according to DP spec */
582 for (try = 0; try < 5; try++) {
583 /* Load the send data into the aux channel data registers */
584 for (i = 0; i < send_bytes; i += 4)
585 I915_WRITE(ch_data + i,
586 pack_aux(send + i, send_bytes - i));
587
588 /* Send the command and wait for it to complete */
5ed12a19 589 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 590
591 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
592
593 /* Clear done status and any errors */
594 I915_WRITE(ch_ctl,
595 status |
596 DP_AUX_CH_CTL_DONE |
597 DP_AUX_CH_CTL_TIME_OUT_ERROR |
598 DP_AUX_CH_CTL_RECEIVE_ERROR);
599
600 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
601 DP_AUX_CH_CTL_RECEIVE_ERROR))
602 continue;
603 if (status & DP_AUX_CH_CTL_DONE)
604 break;
605 }
4f7f7b7e 606 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 607 break;
608 }
609
a4fc5ed6 610 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 611 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 612 ret = -EBUSY;
613 goto out;
a4fc5ed6
KP		 614 }
615
616 /* Check for timeout or receive error.
617 * Timeouts occur when the sink is not connected
618 */
a5b3da54 619 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 620 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 621 ret = -EIO;
622 goto out;
a5b3da54 623 }
1ae8c0a5
KP		 624
625 /* Timeouts occur when the device isn't connected, so they're
626 * "normal" -- don't fill the kernel log with these */
a5b3da54 627 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 628 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 629 ret = -ETIMEDOUT;
630 goto out;
a4fc5ed6
KP		 631 }
632
633 /* Unload any bytes sent back from the other side */
634 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
635 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 636 if (recv_bytes > recv_size)
637 recv_bytes = recv_size;
0206e353 638
4f7f7b7e
CW		 639 for (i = 0; i < recv_bytes; i += 4)
640 unpack_aux(I915_READ(ch_data + i),
641 recv + i, recv_bytes - i);
a4fc5ed6 642
9ee32fea
DV		 643 ret = recv_bytes;
644out:
645 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 646 intel_aux_display_runtime_put(dev_priv);
9ee32fea 647
884f19e9
JN		 648 if (vdd)
649 edp_panel_vdd_off(intel_dp, false);
650
9ee32fea 651 return ret;
a4fc5ed6
KP		 652}
653
a6c8aff0
JN		 654#define BARE_ADDRESS_SIZE 3
655#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 656static ssize_t
657intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 658{
9d1a1031
JN		 659 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
660 uint8_t txbuf[20], rxbuf[20];
661 size_t txsize, rxsize;
a4fc5ed6 662 int ret;
a4fc5ed6 663
9d1a1031
JN		 664 txbuf[0] = msg->request << 4;
665 txbuf[1] = msg->address >> 8;
666 txbuf[2] = msg->address & 0xff;
667 txbuf[3] = msg->size - 1;
46a5ae9f 668
9d1a1031
JN		 669 switch (msg->request & ~DP_AUX_I2C_MOT) {
670 case DP_AUX_NATIVE_WRITE:
671 case DP_AUX_I2C_WRITE:
a6c8aff0 672 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 673 rxsize = 1;
f51a44b9 674
9d1a1031
JN		 675 if (WARN_ON(txsize > 20))
676 return -E2BIG;
a4fc5ed6 677
9d1a1031 678 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 679
9d1a1031
JN		 680 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
681 if (ret > 0) {
682 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 683
9d1a1031
JN		 684 /* Return payload size. */
685 ret = msg->size;
686 }
687 break;
46a5ae9f 688
9d1a1031
JN		 689 case DP_AUX_NATIVE_READ:
690 case DP_AUX_I2C_READ:
a6c8aff0 691 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 692 rxsize = msg->size + 1;
a4fc5ed6 693
9d1a1031
JN		 694 if (WARN_ON(rxsize > 20))
695 return -E2BIG;
a4fc5ed6 696
9d1a1031
JN		 697 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
698 if (ret > 0) {
699 msg->reply = rxbuf[0] >> 4;
700 /*
701 * Assume happy day, and copy the data. The caller is
702 * expected to check msg->reply before touching it.
703 *
704 * Return payload size.
705 */
706 ret--;
707 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 708 }
9d1a1031
JN		 709 break;
710
711 default:
712 ret = -EINVAL;
713 break;
a4fc5ed6 714 }
f51a44b9 715
9d1a1031 716 return ret;
a4fc5ed6
KP		 717}
718
9d1a1031
JN		 719static void
720intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
721{
722 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 723 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
724 enum port port = intel_dig_port->port;
0b99836f 725 const char *name = NULL;
ab2c0672
DA		 726 int ret;
727
33ad6626
JN		 728 switch (port) {
729 case PORT_A:
730 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 731 name = "DPDDC-A";
ab2c0672 732 break;
33ad6626
JN		 733 case PORT_B:
734 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 735 name = "DPDDC-B";
ab2c0672 736 break;
33ad6626
JN		 737 case PORT_C:
738 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 739 name = "DPDDC-C";
ab2c0672 740 break;
33ad6626
JN		 741 case PORT_D:
742 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 743 name = "DPDDC-D";
33ad6626
JN		 744 break;
745 default:
746 BUG();
ab2c0672
DA		 747 }
748
33ad6626
JN		 749 if (!HAS_DDI(dev))
750 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 751
0b99836f 752 intel_dp->aux.name = name;
9d1a1031
JN		 753 intel_dp->aux.dev = dev->dev;
754 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 755
0b99836f
JN		 756 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
757 connector->base.kdev->kobj.name);
8316f337 758
4f71d0cb 759 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 760 if (ret < 0) {
4f71d0cb 761 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 762 name, ret);
763 return;
ab2c0672 764 }
8a5e6aeb 765
0b99836f
JN		 766 ret = sysfs_create_link(&connector->base.kdev->kobj,
767 &intel_dp->aux.ddc.dev.kobj,
768 intel_dp->aux.ddc.dev.kobj.name);
769 if (ret < 0) {
770 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 771 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 772 }
a4fc5ed6
KP		 773}
774
80f65de3
ID		 775static void
776intel_dp_connector_unregister(struct intel_connector *intel_connector)
777{
778 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
779
0e32b39c
DA		 780 if (!intel_connector->mst_port)
781 sysfs_remove_link(&intel_connector->base.kdev->kobj,
782 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 783 intel_connector_unregister(intel_connector);
784}
785
0e50338c
DV		 786static void
787hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
788{
789 switch (link_bw) {
790 case DP_LINK_BW_1_62:
791 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
792 break;
793 case DP_LINK_BW_2_7:
794 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
795 break;
796 case DP_LINK_BW_5_4:
797 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
798 break;
799 }
800}
801
c6bb3538
DV		 802static void
803intel_dp_set_clock(struct intel_encoder *encoder,
804 struct intel_crtc_config *pipe_config, int link_bw)
805{
806 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 807 const struct dp_link_dpll *divisor = NULL;
808 int i, count = 0;
c6bb3538
DV		 809
810 if (IS_G4X(dev)) {
9dd4ffdf
CML		 811 divisor = gen4_dpll;
812 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 813 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 814 divisor = pch_dpll;
815 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 816 } else if (IS_CHERRYVIEW(dev)) {
817 divisor = chv_dpll;
818 count = ARRAY_SIZE(chv_dpll);
c6bb3538 819 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 820 divisor = vlv_dpll;
821 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 822 }
9dd4ffdf
CML		 823
824 if (divisor && count) {
825 for (i = 0; i < count; i++) {
826 if (link_bw == divisor[i].link_bw) {
827 pipe_config->dpll = divisor[i].dpll;
828 pipe_config->clock_set = true;
829 break;
830 }
831 }
c6bb3538
DV		 832 }
833}
834
00c09d70 835bool
5bfe2ac0
DV		 836intel_dp_compute_config(struct intel_encoder *encoder,
837 struct intel_crtc_config *pipe_config)
a4fc5ed6 838{
5bfe2ac0 839 struct drm_device *dev = encoder->base.dev;
36008365 840 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 841 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 843 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 844 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 845 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 846 int lane_count, clock;
56071a20 847 int min_lane_count = 1;
eeb6324d 848 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 849 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 850 int min_clock = 0;
06ea66b6 851 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 852 int bpp, mode_rate;
06ea66b6 853 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 854 int link_avail, link_clock;
a4fc5ed6 855
bc7d38a4 856 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 857 pipe_config->has_pch_encoder = true;
858
03afc4a2 859 pipe_config->has_dp_encoder = true;
f769cd24 860 pipe_config->has_drrs = false;
9ed109a7 861 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 862
dd06f90e
JN		 863 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
864 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
865 adjusted_mode);
2dd24552
JB		 866 if (!HAS_PCH_SPLIT(dev))
867 intel_gmch_panel_fitting(intel_crtc, pipe_config,
868 intel_connector->panel.fitting_mode);
869 else
b074cec8
JB		 870 intel_pch_panel_fitting(intel_crtc, pipe_config,
871 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 872 }
873
cb1793ce 874 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 875 return false;
876
083f9560
DV		 877 DRM_DEBUG_KMS("DP link computation with max lane count %i "
878 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 879 max_lane_count, bws[max_clock],
880 adjusted_mode->crtc_clock);
083f9560 881
36008365
DV		 882 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
883 * bpc in between. */
3e7ca985 884 bpp = pipe_config->pipe_bpp;
56071a20
JN		 885 if (is_edp(intel_dp)) {
886 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
887 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
888 dev_priv->vbt.edp_bpp);
889 bpp = dev_priv->vbt.edp_bpp;
890 }
891
f4cdbc21
JN		 892 if (IS_BROADWELL(dev)) {
893 /* Yes, it's an ugly hack. */
894 min_lane_count = max_lane_count;
895 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
896 min_lane_count);
897 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 898 min_lane_count = min(dev_priv->vbt.edp_lanes,
899 max_lane_count);
900 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
901 min_lane_count);
902 }
903
904 if (dev_priv->vbt.edp_rate) {
905 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
906 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
907 bws[min_clock]);
908 }
7984211e 909 }
657445fe 910
36008365 911 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 912 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
913 bpp);
36008365 914
c6930992
DA		 915 for (clock = min_clock; clock <= max_clock; clock++) {
916 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 917 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
918 link_avail = intel_dp_max_data_rate(link_clock,
919 lane_count);
920
921 if (mode_rate <= link_avail) {
922 goto found;
923 }
924 }
925 }
926 }
c4867936 927
36008365 928 return false;
3685a8f3 929
36008365 930found:
55bc60db
VS		 931 if (intel_dp->color_range_auto) {
932 /*
933 * See:
934 * CEA-861-E - 5.1 Default Encoding Parameters
935 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
936 */
18316c8c 937 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 938 intel_dp->color_range = DP_COLOR_RANGE_16_235;
939 else
940 intel_dp->color_range = 0;
941 }
942
3685a8f3 943 if (intel_dp->color_range)
50f3b016 944 pipe_config->limited_color_range = true;
a4fc5ed6 945
36008365
DV		 946 intel_dp->link_bw = bws[clock];
947 intel_dp->lane_count = lane_count;
657445fe 948 pipe_config->pipe_bpp = bpp;
ff9a6750 949 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 950
36008365
DV		 951 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
952 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 953 pipe_config->port_clock, bpp);
36008365
DV		 954 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
955 mode_rate, link_avail);
a4fc5ed6 956
03afc4a2 957 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 958 adjusted_mode->crtc_clock,
959 pipe_config->port_clock,
03afc4a2 960 &pipe_config->dp_m_n);
9d1a455b 961
439d7ac0
PB		 962 if (intel_connector->panel.downclock_mode != NULL &&
963 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 964 pipe_config->has_drrs = true;
439d7ac0
PB		 965 intel_link_compute_m_n(bpp, lane_count,
966 intel_connector->panel.downclock_mode->clock,
967 pipe_config->port_clock,
968 &pipe_config->dp_m2_n2);
969 }
970
ea155f32 971 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 972 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
973 else
974 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 975
03afc4a2 976 return true;
a4fc5ed6
KP		 977}
978
7c62a164 979static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 980{
7c62a164
DV		 981 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
982 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
983 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u32 dpa_ctl;
986
ff9a6750 987 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 988 dpa_ctl = I915_READ(DP_A);
989 dpa_ctl &= ~DP_PLL_FREQ_MASK;
990
ff9a6750 991 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 992 /* For a long time we've carried around a ILK-DevA w/a for the
993 * 160MHz clock. If we're really unlucky, it's still required.
994 */
995 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 996 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 997 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 998 } else {
999 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1000 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1001 }
1ce17038 1002
ea9b6006
DV		 1003 I915_WRITE(DP_A, dpa_ctl);
1004
1005 POSTING_READ(DP_A);
1006 udelay(500);
1007}
1008
8ac33ed3 1009static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1010{
b934223d 1011 struct drm_device *dev = encoder->base.dev;
417e822d 1012 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1013 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1014 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1015 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1016 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1017
417e822d 1018 /*
1a2eb460 1019 * There are four kinds of DP registers:
417e822d
KP		 1020 *
1021 * IBX PCH
1a2eb460
KP		 1022 * SNB CPU
1023 * IVB CPU
417e822d
KP		 1024 * CPT PCH
1025 *
1026 * IBX PCH and CPU are the same for almost everything,
1027 * except that the CPU DP PLL is configured in this
1028 * register
1029 *
1030 * CPT PCH is quite different, having many bits moved
1031 * to the TRANS_DP_CTL register instead. That
1032 * configuration happens (oddly) in ironlake_pch_enable
1033 */
9c9e7927 1034
417e822d
KP		 1035 /* Preserve the BIOS-computed detected bit. This is
1036 * supposed to be read-only.
1037 */
1038 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1039
417e822d 1040 /* Handle DP bits in common between all three register formats */
417e822d 1041 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1042 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1043
9ed109a7 1044 if (crtc->config.has_audio) {
e0dac65e 1045 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1046 pipe_name(crtc->pipe));
ea5b213a 1047 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1048 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1049 }
247d89f6 1050
417e822d 1051 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1052
bc7d38a4 1053 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1054 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1055 intel_dp->DP |= DP_SYNC_HS_HIGH;
1056 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1057 intel_dp->DP |= DP_SYNC_VS_HIGH;
1058 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1059
6aba5b6c 1060 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1061 intel_dp->DP |= DP_ENHANCED_FRAMING;
1062
7c62a164 1063 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1064 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1065 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1066 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1067
1068 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1069 intel_dp->DP |= DP_SYNC_HS_HIGH;
1070 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1071 intel_dp->DP |= DP_SYNC_VS_HIGH;
1072 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1073
6aba5b6c 1074 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1075 intel_dp->DP |= DP_ENHANCED_FRAMING;
1076
44f37d1f
CML		 1077 if (!IS_CHERRYVIEW(dev)) {
1078 if (crtc->pipe == 1)
1079 intel_dp->DP |= DP_PIPEB_SELECT;
1080 } else {
1081 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1082 }
417e822d
KP		 1083 } else {
1084 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1085 }
a4fc5ed6
KP		 1086}
1087
ffd6749d
PZ		 1088#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1089#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1090
1a5ef5b7
PZ		 1091#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1092#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1093
ffd6749d
PZ		 1094#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1095#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1096
4be73780 1097static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1098 u32 mask,
1099 u32 value)
bd943159 1100{
30add22d 1101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1102 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1103 u32 pp_stat_reg, pp_ctrl_reg;
1104
bf13e81b
JN		 1105 pp_stat_reg = _pp_stat_reg(intel_dp);
1106 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1107
99ea7127 1108 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1109 mask, value,
1110 I915_READ(pp_stat_reg),
1111 I915_READ(pp_ctrl_reg));
32ce697c 1112
453c5420 1113 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1114 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1115 I915_READ(pp_stat_reg),
1116 I915_READ(pp_ctrl_reg));
32ce697c 1117 }
54c136d4
CW		 1118
1119 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1120}
32ce697c 1121
4be73780 1122static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1123{
1124 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1125 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1126}
1127
4be73780 1128static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1129{
1130 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1131 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1132}
1133
4be73780 1134static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1135{
1136 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1137
1138 /* When we disable the VDD override bit last we have to do the manual
1139 * wait. */
1140 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1141 intel_dp->panel_power_cycle_delay);
1142
4be73780 1143 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1144}
1145
4be73780 1146static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1147{
1148 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1149 intel_dp->backlight_on_delay);
1150}
1151
4be73780 1152static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1153{
1154 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1155 intel_dp->backlight_off_delay);
1156}
99ea7127 1157
832dd3c1
KP		 1158/* Read the current pp_control value, unlocking the register if it
1159 * is locked
1160 */
1161
453c5420 1162static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1163{
453c5420
JB		 1164 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 control;
832dd3c1 1167
bf13e81b 1168 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1169 control &= ~PANEL_UNLOCK_MASK;
1170 control |= PANEL_UNLOCK_REGS;
1171 return control;
bd943159
KP		 1172}
1173
1e0560e0 1174static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1175{
30add22d 1176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1177 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1178 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1179 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1180 enum intel_display_power_domain power_domain;
5d613501 1181 u32 pp;
453c5420 1182 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1183 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1184
97af61f5 1185 if (!is_edp(intel_dp))
adddaaf4 1186 return false;
bd943159
KP		 1187
1188 intel_dp->want_panel_vdd = true;
99ea7127 1189
4be73780 1190 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1191 return need_to_disable;
b0665d57 1192
4e6e1a54
ID		 1193 power_domain = intel_display_port_power_domain(intel_encoder);
1194 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1195
b0665d57 1196 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1197
4be73780
DV		 1198 if (!edp_have_panel_power(intel_dp))
1199 wait_panel_power_cycle(intel_dp);
99ea7127 1200
453c5420 1201 pp = ironlake_get_pp_control(intel_dp);
5d613501 1202 pp |= EDP_FORCE_VDD;
ebf33b18 1203
bf13e81b
JN		 1204 pp_stat_reg = _pp_stat_reg(intel_dp);
1205 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1206
1207 I915_WRITE(pp_ctrl_reg, pp);
1208 POSTING_READ(pp_ctrl_reg);
1209 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1210 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1211 /*
1212 * If the panel wasn't on, delay before accessing aux channel
1213 */
4be73780 1214 if (!edp_have_panel_power(intel_dp)) {
bd943159 1215 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1216 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1217 }
adddaaf4
JN		 1218
1219 return need_to_disable;
1220}
1221
b80d6c78 1222void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1223{
c695b6b6 1224 bool vdd;
adddaaf4 1225
c695b6b6
VS		 1226 if (!is_edp(intel_dp))
1227 return;
1228
1229 vdd = edp_panel_vdd_on(intel_dp);
1230
1231 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1232}
1233
4be73780 1234static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1235{
30add22d 1236 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1237 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1238 struct intel_digital_port *intel_dig_port =
1239 dp_to_dig_port(intel_dp);
1240 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1241 enum intel_display_power_domain power_domain;
5d613501 1242 u32 pp;
453c5420 1243 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1244
51fd371b 1245 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1246
15e899a0
VS		 1247 WARN_ON(intel_dp->want_panel_vdd);
1248
1249 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1250 return;
4e6e1a54 1251
be2c9196 1252 DRM_DEBUG_KMS("Turning eDP VDD off\n");
b0665d57 1253
be2c9196
VS		 1254 pp = ironlake_get_pp_control(intel_dp);
1255 pp &= ~EDP_FORCE_VDD;
bd943159 1256
be2c9196
VS		 1257 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1258 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1259
be2c9196
VS		 1260 I915_WRITE(pp_ctrl_reg, pp);
1261 POSTING_READ(pp_ctrl_reg);
99ea7127 1262
be2c9196
VS		 1263 /* Make sure sequencer is idle before allowing subsequent activity */
1264 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1265 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1266
be2c9196
VS		 1267 if ((pp & POWER_TARGET_ON) == 0)
1268 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1269
be2c9196
VS		 1270 power_domain = intel_display_port_power_domain(intel_encoder);
1271 intel_display_power_put(dev_priv, power_domain);
bd943159 1272}
5d613501 1273
4be73780 1274static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1275{
1276 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1277 struct intel_dp, panel_vdd_work);
30add22d 1278 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1279
51fd371b 1280 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
15e899a0
VS		 1281 if (!intel_dp->want_panel_vdd)
1282 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1283 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1284}
1285
aba86890
ID		 1286static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1287{
1288 unsigned long delay;
1289
1290 /*
1291 * Queue the timer to fire a long time from now (relative to the power
1292 * down delay) to keep the panel power up across a sequence of
1293 * operations.
1294 */
1295 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1296 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1297}
1298
4be73780 1299static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1300{
97af61f5
KP		 1301 if (!is_edp(intel_dp))
1302 return;
5d613501 1303
bd943159 1304 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1305
bd943159
KP		 1306 intel_dp->want_panel_vdd = false;
1307
aba86890 1308 if (sync)
4be73780 1309 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1310 else
1311 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1312}
1313
1e0560e0
VS		 1314static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1315{
1316 edp_panel_vdd_off(intel_dp, sync);
1317}
1318
4be73780 1319void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1320{
30add22d 1321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1322 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1323 u32 pp;
453c5420 1324 u32 pp_ctrl_reg;
9934c132 1325
97af61f5 1326 if (!is_edp(intel_dp))
bd943159 1327 return;
99ea7127
KP		 1328
1329 DRM_DEBUG_KMS("Turn eDP power on\n");
1330
4be73780 1331 if (edp_have_panel_power(intel_dp)) {
99ea7127 1332 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1333 return;
99ea7127 1334 }
9934c132 1335
4be73780 1336 wait_panel_power_cycle(intel_dp);
37c6c9b0 1337
bf13e81b 1338 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1339 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1340 if (IS_GEN5(dev)) {
1341 /* ILK workaround: disable reset around power sequence */
1342 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1343 I915_WRITE(pp_ctrl_reg, pp);
1344 POSTING_READ(pp_ctrl_reg);
05ce1a49 1345 }
37c6c9b0 1346
1c0ae80a 1347 pp |= POWER_TARGET_ON;
99ea7127
KP		 1348 if (!IS_GEN5(dev))
1349 pp |= PANEL_POWER_RESET;
1350
453c5420
JB		 1351 I915_WRITE(pp_ctrl_reg, pp);
1352 POSTING_READ(pp_ctrl_reg);
9934c132 1353
4be73780 1354 wait_panel_on(intel_dp);
dce56b3c 1355 intel_dp->last_power_on = jiffies;
9934c132 1356
05ce1a49
KP		 1357 if (IS_GEN5(dev)) {
1358 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1359 I915_WRITE(pp_ctrl_reg, pp);
1360 POSTING_READ(pp_ctrl_reg);
05ce1a49 1361 }
9934c132
JB		 1362}
1363
4be73780 1364void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1365{
4e6e1a54
ID		 1366 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1367 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1368 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1369 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1370 enum intel_display_power_domain power_domain;
99ea7127 1371 u32 pp;
453c5420 1372 u32 pp_ctrl_reg;
9934c132 1373
97af61f5
KP		 1374 if (!is_edp(intel_dp))
1375 return;
37c6c9b0 1376
99ea7127 1377 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1378
24f3e092
JN		 1379 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1380
453c5420 1381 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1382 /* We need to switch off panel power _and_ force vdd, for otherwise some
1383 * panels get very unhappy and cease to work. */
b3064154
PJ		 1384 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1385 EDP_BLC_ENABLE);
453c5420 1386
bf13e81b 1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1388
849e39f5
PZ		 1389 intel_dp->want_panel_vdd = false;
1390
453c5420
JB		 1391 I915_WRITE(pp_ctrl_reg, pp);
1392 POSTING_READ(pp_ctrl_reg);
9934c132 1393
dce56b3c 1394 intel_dp->last_power_cycle = jiffies;
4be73780 1395 wait_panel_off(intel_dp);
849e39f5
PZ		 1396
1397 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1398 power_domain = intel_display_port_power_domain(intel_encoder);
1399 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1400}
1401
1250d107
JN		 1402/* Enable backlight in the panel power control. */
1403static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1404{
da63a9f2
PZ		 1405 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1406 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 u32 pp;
453c5420 1409 u32 pp_ctrl_reg;
32f9d658 1410
01cb9ea6
JB		 1411 /*
1412 * If we enable the backlight right away following a panel power
1413 * on, we may see slight flicker as the panel syncs with the eDP
1414 * link. So delay a bit to make sure the image is solid before
1415 * allowing it to appear.
1416 */
4be73780 1417 wait_backlight_on(intel_dp);
453c5420 1418 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1419 pp |= EDP_BLC_ENABLE;
453c5420 1420
bf13e81b 1421 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1422
1423 I915_WRITE(pp_ctrl_reg, pp);
1424 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1425}
1426
1250d107
JN		 1427/* Enable backlight PWM and backlight PP control. */
1428void intel_edp_backlight_on(struct intel_dp *intel_dp)
1429{
1430 if (!is_edp(intel_dp))
1431 return;
1432
1433 DRM_DEBUG_KMS("\n");
1434
1435 intel_panel_enable_backlight(intel_dp->attached_connector);
1436 _intel_edp_backlight_on(intel_dp);
1437}
1438
1439/* Disable backlight in the panel power control. */
1440static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1441{
30add22d 1442 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 u32 pp;
453c5420 1445 u32 pp_ctrl_reg;
32f9d658 1446
453c5420 1447 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1448 pp &= ~EDP_BLC_ENABLE;
453c5420 1449
bf13e81b 1450 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1451
1452 I915_WRITE(pp_ctrl_reg, pp);
1453 POSTING_READ(pp_ctrl_reg);
dce56b3c 1454 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1455
1456 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1457}
1458
1459/* Disable backlight PP control and backlight PWM. */
1460void intel_edp_backlight_off(struct intel_dp *intel_dp)
1461{
1462 if (!is_edp(intel_dp))
1463 return;
1464
1465 DRM_DEBUG_KMS("\n");
f7d2323c 1466
1250d107 1467 _intel_edp_backlight_off(intel_dp);
f7d2323c 1468 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1469}
a4fc5ed6 1470
73580fb7
JN		 1471/*
1472 * Hook for controlling the panel power control backlight through the bl_power
1473 * sysfs attribute. Take care to handle multiple calls.
1474 */
1475static void intel_edp_backlight_power(struct intel_connector *connector,
1476 bool enable)
1477{
1478 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1479 bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1480
1481 if (is_enabled == enable)
1482 return;
1483
23ba9373
JN		 1484 DRM_DEBUG_KMS("panel power control backlight %s\n",
1485 enable ? "enable" : "disable");
73580fb7
JN		 1486
1487 if (enable)
1488 _intel_edp_backlight_on(intel_dp);
1489 else
1490 _intel_edp_backlight_off(intel_dp);
1491}
1492
2bd2ad64 1493static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1494{
da63a9f2
PZ		 1495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1496 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1497 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499 u32 dpa_ctl;
1500
2bd2ad64
DV		 1501 assert_pipe_disabled(dev_priv,
1502 to_intel_crtc(crtc)->pipe);
1503
d240f20f
JB		 1504 DRM_DEBUG_KMS("\n");
1505 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1506 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1507 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1508
1509 /* We don't adjust intel_dp->DP while tearing down the link, to
1510 * facilitate link retraining (e.g. after hotplug). Hence clear all
1511 * enable bits here to ensure that we don't enable too much. */
1512 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1513 intel_dp->DP |= DP_PLL_ENABLE;
1514 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1515 POSTING_READ(DP_A);
1516 udelay(200);
d240f20f
JB		 1517}
1518
2bd2ad64 1519static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1520{
da63a9f2
PZ		 1521 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1522 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1523 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 u32 dpa_ctl;
1526
2bd2ad64
DV		 1527 assert_pipe_disabled(dev_priv,
1528 to_intel_crtc(crtc)->pipe);
1529
d240f20f 1530 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1531 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1532 "dp pll off, should be on\n");
1533 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1534
1535 /* We can't rely on the value tracked for the DP register in
1536 * intel_dp->DP because link_down must not change that (otherwise link
1537 * re-training will fail. */
298b0b39 1538 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1539 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1540 POSTING_READ(DP_A);
d240f20f
JB		 1541 udelay(200);
1542}
1543
c7ad3810 1544/* If the sink supports it, try to set the power state appropriately */
c19b0669 1545void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1546{
1547 int ret, i;
1548
1549 /* Should have a valid DPCD by this point */
1550 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1551 return;
1552
1553 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1554 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1555 DP_SET_POWER_D3);
c7ad3810
JB		 1556 } else {
1557 /*
1558 * When turning on, we need to retry for 1ms to give the sink
1559 * time to wake up.
1560 */
1561 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1562 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1563 DP_SET_POWER_D0);
c7ad3810
JB		 1564 if (ret == 1)
1565 break;
1566 msleep(1);
1567 }
1568 }
f9cac721
JN		 1569
1570 if (ret != 1)
1571 DRM_DEBUG_KMS("failed to %s sink power state\n",
1572 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1573}
1574
19d8fe15
DV		 1575static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1576 enum pipe *pipe)
d240f20f 1577{
19d8fe15 1578 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1579 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1580 struct drm_device *dev = encoder->base.dev;
1581 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1582 enum intel_display_power_domain power_domain;
1583 u32 tmp;
1584
1585 power_domain = intel_display_port_power_domain(encoder);
1586 if (!intel_display_power_enabled(dev_priv, power_domain))
1587 return false;
1588
1589 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1590
1591 if (!(tmp & DP_PORT_EN))
1592 return false;
1593
bc7d38a4 1594 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1595 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1596 } else if (IS_CHERRYVIEW(dev)) {
1597 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1598 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1599 *pipe = PORT_TO_PIPE(tmp);
1600 } else {
1601 u32 trans_sel;
1602 u32 trans_dp;
1603 int i;
1604
1605 switch (intel_dp->output_reg) {
1606 case PCH_DP_B:
1607 trans_sel = TRANS_DP_PORT_SEL_B;
1608 break;
1609 case PCH_DP_C:
1610 trans_sel = TRANS_DP_PORT_SEL_C;
1611 break;
1612 case PCH_DP_D:
1613 trans_sel = TRANS_DP_PORT_SEL_D;
1614 break;
1615 default:
1616 return true;
1617 }
1618
055e393f 1619 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1620 trans_dp = I915_READ(TRANS_DP_CTL(i));
1621 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1622 *pipe = i;
1623 return true;
1624 }
1625 }
19d8fe15 1626
4a0833ec
DV		 1627 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1628 intel_dp->output_reg);
1629 }
d240f20f 1630
19d8fe15
DV		 1631 return true;
1632}
d240f20f 1633
045ac3b5
JB		 1634static void intel_dp_get_config(struct intel_encoder *encoder,
1635 struct intel_crtc_config *pipe_config)
1636{
1637 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1638 u32 tmp, flags = 0;
63000ef6
XZ		 1639 struct drm_device *dev = encoder->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 enum port port = dp_to_dig_port(intel_dp)->port;
1642 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1643 int dotclock;
045ac3b5 1644
9ed109a7
DV		 1645 tmp = I915_READ(intel_dp->output_reg);
1646 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1647 pipe_config->has_audio = true;
1648
63000ef6 1649 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1650 if (tmp & DP_SYNC_HS_HIGH)
1651 flags |= DRM_MODE_FLAG_PHSYNC;
1652 else
1653 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1654
63000ef6
XZ		 1655 if (tmp & DP_SYNC_VS_HIGH)
1656 flags |= DRM_MODE_FLAG_PVSYNC;
1657 else
1658 flags |= DRM_MODE_FLAG_NVSYNC;
1659 } else {
1660 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1661 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1662 flags |= DRM_MODE_FLAG_PHSYNC;
1663 else
1664 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1665
63000ef6
XZ		 1666 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1667 flags |= DRM_MODE_FLAG_PVSYNC;
1668 else
1669 flags |= DRM_MODE_FLAG_NVSYNC;
1670 }
045ac3b5
JB		 1671
1672 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1673
eb14cb74
VS		 1674 pipe_config->has_dp_encoder = true;
1675
1676 intel_dp_get_m_n(crtc, pipe_config);
1677
18442d08 1678 if (port == PORT_A) {
f1f644dc
JB		 1679 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1680 pipe_config->port_clock = 162000;
1681 else
1682 pipe_config->port_clock = 270000;
1683 }
18442d08
VS		 1684
1685 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1686 &pipe_config->dp_m_n);
1687
1688 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1689 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1690
241bfc38 1691 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1692
c6cd2ee2
JN		 1693 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1694 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1695 /*
1696 * This is a big fat ugly hack.
1697 *
1698 * Some machines in UEFI boot mode provide us a VBT that has 18
1699 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1700 * unknown we fail to light up. Yet the same BIOS boots up with
1701 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1702 * max, not what it tells us to use.
1703 *
1704 * Note: This will still be broken if the eDP panel is not lit
1705 * up by the BIOS, and thus we can't get the mode at module
1706 * load.
1707 */
1708 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1709 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1710 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1711 }
045ac3b5
JB		 1712}
1713
34eb7579 1714static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1715{
34eb7579 1716 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1717}
1718
2b28bb1b
RV		 1719static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1720{
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722
18b5992c 1723 if (!HAS_PSR(dev))
2b28bb1b
RV		 1724 return false;
1725
18b5992c 1726 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1727}
1728
1729static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1730 struct edp_vsc_psr *vsc_psr)
1731{
1732 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1733 struct drm_device *dev = dig_port->base.base.dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1736 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1737 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1738 uint32_t *data = (uint32_t *) vsc_psr;
1739 unsigned int i;
1740
1741 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1742 the video DIP being updated before program video DIP data buffer
1743 registers for DIP being updated. */
1744 I915_WRITE(ctl_reg, 0);
1745 POSTING_READ(ctl_reg);
1746
1747 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1748 if (i < sizeof(struct edp_vsc_psr))
1749 I915_WRITE(data_reg + i, *data++);
1750 else
1751 I915_WRITE(data_reg + i, 0);
1752 }
1753
1754 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1755 POSTING_READ(ctl_reg);
1756}
1757
1758static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1759{
1760 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 struct edp_vsc_psr psr_vsc;
1763
2b28bb1b
RV		 1764 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1765 memset(&psr_vsc, 0, sizeof(psr_vsc));
1766 psr_vsc.sdp_header.HB0 = 0;
1767 psr_vsc.sdp_header.HB1 = 0x7;
1768 psr_vsc.sdp_header.HB2 = 0x2;
1769 psr_vsc.sdp_header.HB3 = 0x8;
1770 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1771
1772 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1773 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1774 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1775}
1776
1777static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1778{
0e0ae652
RV		 1779 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1780 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1781 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1782 uint32_t aux_clock_divider;
2b28bb1b
RV		 1783 int precharge = 0x3;
1784 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1785 bool only_standby = false;
2b28bb1b 1786
ec5b01dd
DL		 1787 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1788
0e0ae652
RV		 1789 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1790 only_standby = true;
1791
2b28bb1b 1792 /* Enable PSR in sink */
0e0ae652 1793 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1794 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1795 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1796 else
9d1a1031
JN		 1797 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1798 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1799
1800 /* Setup AUX registers */
18b5992c
BW		 1801 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1802 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1803 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1804 DP_AUX_CH_CTL_TIME_OUT_400us |
1805 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1806 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1807 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1808}
1809
1810static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1811{
0e0ae652
RV		 1812 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1813 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1814 struct drm_i915_private *dev_priv = dev->dev_private;
1815 uint32_t max_sleep_time = 0x1f;
1816 uint32_t idle_frames = 1;
1817 uint32_t val = 0x0;
ed8546ac 1818 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1819 bool only_standby = false;
1820
1821 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1822 only_standby = true;
2b28bb1b 1823
0e0ae652 1824 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1825 val |= EDP_PSR_LINK_STANDBY;
1826 val |= EDP_PSR_TP2_TP3_TIME_0us;
1827 val |= EDP_PSR_TP1_TIME_0us;
1828 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1829 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1830 } else
1831 val |= EDP_PSR_LINK_DISABLE;
1832
18b5992c 1833 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1834 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1835 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1836 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1837 EDP_PSR_ENABLE);
1838}
1839
3f51e471
RV		 1840static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1841{
1842 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1843 struct drm_device *dev = dig_port->base.base.dev;
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845 struct drm_crtc *crtc = dig_port->base.base.crtc;
1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1847
f0355c4a 1848 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1849 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1850 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1851
a031d709
RV		 1852 dev_priv->psr.source_ok = false;
1853
9ca15301 1854 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1855 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1856 return false;
1857 }
1858
d330a953 1859 if (!i915.enable_psr) {
105b7c11 1860 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1861 return false;
1862 }
1863
4c8c7000
RV		 1864 /* Below limitations aren't valid for Broadwell */
1865 if (IS_BROADWELL(dev))
1866 goto out;
1867
3f51e471
RV		 1868 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1869 S3D_ENABLE) {
1870 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1871 return false;
1872 }
1873
ca73b4f0 1874 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1875 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1876 return false;
1877 }
1878
4c8c7000 1879 out:
a031d709 1880 dev_priv->psr.source_ok = true;
3f51e471
RV		 1881 return true;
1882}
1883
3d739d92 1884static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1885{
7c8f8a70
RV		 1886 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1887 struct drm_device *dev = intel_dig_port->base.base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1889
3638379c
DV		 1890 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1891 WARN_ON(dev_priv->psr.active);
f0355c4a 1892 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1893
2b28bb1b
RV		 1894 /* Enable PSR on the panel */
1895 intel_edp_psr_enable_sink(intel_dp);
1896
1897 /* Enable PSR on the host */
1898 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1899
7c8f8a70 1900 dev_priv->psr.active = true;
2b28bb1b
RV		 1901}
1902
3d739d92
RV		 1903void intel_edp_psr_enable(struct intel_dp *intel_dp)
1904{
1905 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1906 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1907
4704c573
RV		 1908 if (!HAS_PSR(dev)) {
1909 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1910 return;
1911 }
1912
34eb7579
RV		 1913 if (!is_edp_psr(intel_dp)) {
1914 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1915 return;
1916 }
1917
f0355c4a 1918 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1919 if (dev_priv->psr.enabled) {
1920 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1921 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1922 return;
1923 }
1924
9ca15301
DV		 1925 dev_priv->psr.busy_frontbuffer_bits = 0;
1926
16487254
RV		 1927 /* Setup PSR once */
1928 intel_edp_psr_setup(intel_dp);
1929
7c8f8a70 1930 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1931 dev_priv->psr.enabled = intel_dp;
f0355c4a 1932 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1933}
1934
2b28bb1b
RV		 1935void intel_edp_psr_disable(struct intel_dp *intel_dp)
1936{
1937 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1938 struct drm_i915_private *dev_priv = dev->dev_private;
1939
f0355c4a
DV		 1940 mutex_lock(&dev_priv->psr.lock);
1941 if (!dev_priv->psr.enabled) {
1942 mutex_unlock(&dev_priv->psr.lock);
1943 return;
1944 }
1945
3638379c
DV		 1946 if (dev_priv->psr.active) {
1947 I915_WRITE(EDP_PSR_CTL(dev),
1948 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1949
1950 /* Wait till PSR is idle */
1951 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1952 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1953 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 1954
3638379c
DV		 1955 dev_priv->psr.active = false;
1956 } else {
1957 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1958 }
7c8f8a70 1959
2807cf69 1960 dev_priv->psr.enabled = NULL;
f0355c4a 1961 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 1962
1963 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 1964}
1965
f02a326e 1966static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1967{
1968 struct drm_i915_private *dev_priv =
1969 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 1970 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1971
f0355c4a
DV		 1972 mutex_lock(&dev_priv->psr.lock);
1973 intel_dp = dev_priv->psr.enabled;
1974
2807cf69 1975 if (!intel_dp)
f0355c4a 1976 goto unlock;
2807cf69 1977
9ca15301
DV		 1978 /*
1979 * The delayed work can race with an invalidate hence we need to
1980 * recheck. Since psr_flush first clears this and then reschedules we
1981 * won't ever miss a flush when bailing out here.
1982 */
1983 if (dev_priv->psr.busy_frontbuffer_bits)
1984 goto unlock;
1985
1986 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 1987unlock:
1988 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1989}
1990
9ca15301 1991static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 1992{
1993 struct drm_i915_private *dev_priv = dev->dev_private;
1994
3638379c
DV		 1995 if (dev_priv->psr.active) {
1996 u32 val = I915_READ(EDP_PSR_CTL(dev));
1997
1998 WARN_ON(!(val & EDP_PSR_ENABLE));
1999
2000 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2001
2002 dev_priv->psr.active = false;
2003 }
7c8f8a70 2004
9ca15301
DV		 2005}
2006
2007void intel_edp_psr_invalidate(struct drm_device *dev,
2008 unsigned frontbuffer_bits)
2009{
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 struct drm_crtc *crtc;
2012 enum pipe pipe;
2013
9ca15301
DV		 2014 mutex_lock(&dev_priv->psr.lock);
2015 if (!dev_priv->psr.enabled) {
2016 mutex_unlock(&dev_priv->psr.lock);
2017 return;
2018 }
2019
2020 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2021 pipe = to_intel_crtc(crtc)->pipe;
2022
2023 intel_edp_psr_do_exit(dev);
2024
2025 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2026
2027 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2028 mutex_unlock(&dev_priv->psr.lock);
2029}
2030
2031void intel_edp_psr_flush(struct drm_device *dev,
2032 unsigned frontbuffer_bits)
2033{
2034 struct drm_i915_private *dev_priv = dev->dev_private;
2035 struct drm_crtc *crtc;
2036 enum pipe pipe;
2037
9ca15301
DV		 2038 mutex_lock(&dev_priv->psr.lock);
2039 if (!dev_priv->psr.enabled) {
2040 mutex_unlock(&dev_priv->psr.lock);
2041 return;
2042 }
2043
2044 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2045 pipe = to_intel_crtc(crtc)->pipe;
2046 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2047
2048 /*
2049 * On Haswell sprite plane updates don't result in a psr invalidating
2050 * signal in the hardware. Which means we need to manually fake this in
2051 * software for all flushes, not just when we've seen a preceding
2052 * invalidation through frontbuffer rendering.
2053 */
2054 if (IS_HASWELL(dev) &&
2055 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2056 intel_edp_psr_do_exit(dev);
2057
2058 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2059 schedule_delayed_work(&dev_priv->psr.work,
2060 msecs_to_jiffies(100));
f0355c4a 2061 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2062}
2063
2064void intel_edp_psr_init(struct drm_device *dev)
2065{
2066 struct drm_i915_private *dev_priv = dev->dev_private;
2067
7c8f8a70 2068 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2069 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2070}
2071
e8cb4558 2072static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2073{
e8cb4558 2074 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2075 enum port port = dp_to_dig_port(intel_dp)->port;
2076 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2077
2078 /* Make sure the panel is off before trying to change the mode. But also
2079 * ensure that we have vdd while we switch off the panel. */
24f3e092 2080 intel_edp_panel_vdd_on(intel_dp);
4be73780 2081 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2082 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2083 intel_edp_panel_off(intel_dp);
3739850b
DV		 2084
2085 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2086 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2087 intel_dp_link_down(intel_dp);
d240f20f
JB		 2088}
2089
49277c31 2090static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2091{
2bd2ad64 2092 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2093 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2094
49277c31
VS		 2095 if (port != PORT_A)
2096 return;
2097
2098 intel_dp_link_down(intel_dp);
2099 ironlake_edp_pll_off(intel_dp);
2100}
2101
2102static void vlv_post_disable_dp(struct intel_encoder *encoder)
2103{
2104 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2105
2106 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2107}
2108
580d3811
VS		 2109static void chv_post_disable_dp(struct intel_encoder *encoder)
2110{
2111 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2112 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2113 struct drm_device *dev = encoder->base.dev;
2114 struct drm_i915_private *dev_priv = dev->dev_private;
2115 struct intel_crtc *intel_crtc =
2116 to_intel_crtc(encoder->base.crtc);
2117 enum dpio_channel ch = vlv_dport_to_channel(dport);
2118 enum pipe pipe = intel_crtc->pipe;
2119 u32 val;
2120
2121 intel_dp_link_down(intel_dp);
2122
2123 mutex_lock(&dev_priv->dpio_lock);
2124
2125 /* Propagate soft reset to data lane reset */
97fd4d5c 2126 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2127 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2128 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2129
97fd4d5c
VS		 2130 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2131 val |= CHV_PCS_REQ_SOFTRESET_EN;
2132 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2133
2134 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2135 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2136 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2137
2138 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2139 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2140 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2141
2142 mutex_unlock(&dev_priv->dpio_lock);
2143}
2144
e8cb4558 2145static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2146{
e8cb4558
DV		 2147 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2148 struct drm_device *dev = encoder->base.dev;
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2151
0c33d8d7
DV		 2152 if (WARN_ON(dp_reg & DP_PORT_EN))
2153 return;
5d613501 2154
24f3e092 2155 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2156 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2157 intel_dp_start_link_train(intel_dp);
4be73780 2158 intel_edp_panel_on(intel_dp);
1e0560e0 2159 intel_edp_panel_vdd_off(intel_dp, true);
33a34e4e 2160 intel_dp_complete_link_train(intel_dp);
3ab9c637 2161 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2162}
89b667f8 2163
ecff4f3b
JN		 2164static void g4x_enable_dp(struct intel_encoder *encoder)
2165{
828f5c6e
JN		 2166 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2167
ecff4f3b 2168 intel_enable_dp(encoder);
4be73780 2169 intel_edp_backlight_on(intel_dp);
ab1f90f9 2170}
89b667f8 2171
ab1f90f9
JN		 2172static void vlv_enable_dp(struct intel_encoder *encoder)
2173{
828f5c6e
JN		 2174 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2175
4be73780 2176 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2177}
2178
ecff4f3b 2179static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2180{
2181 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2182 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2183
8ac33ed3
DV		 2184 intel_dp_prepare(encoder);
2185
d41f1efb
DV		 2186 /* Only ilk+ has port A */
2187 if (dport->port == PORT_A) {
2188 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2189 ironlake_edp_pll_on(intel_dp);
d41f1efb 2190 }
ab1f90f9
JN		 2191}
2192
2193static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2194{
2bd2ad64 2195 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2196 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2197 struct drm_device *dev = encoder->base.dev;
89b667f8 2198 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2199 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2200 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2201 int pipe = intel_crtc->pipe;
bf13e81b 2202 struct edp_power_seq power_seq;
ab1f90f9 2203 u32 val;
a4fc5ed6 2204
ab1f90f9 2205 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2206
ab3c759a 2207 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2208 val = 0;
2209 if (pipe)
2210 val |= (1<<21);
2211 else
2212 val &= ~(1<<21);
2213 val |= 0x001000c4;
ab3c759a
CML		 2214 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2215 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2216 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2217
ab1f90f9
JN		 2218 mutex_unlock(&dev_priv->dpio_lock);
2219
2cac613b
ID		 2220 if (is_edp(intel_dp)) {
2221 /* init power sequencer on this pipe and port */
2222 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2223 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2224 &power_seq);
2225 }
bf13e81b 2226
ab1f90f9
JN		 2227 intel_enable_dp(encoder);
2228
e4607fcf 2229 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2230}
2231
ecff4f3b 2232static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2233{
2234 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2235 struct drm_device *dev = encoder->base.dev;
2236 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2237 struct intel_crtc *intel_crtc =
2238 to_intel_crtc(encoder->base.crtc);
e4607fcf 2239 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2240 int pipe = intel_crtc->pipe;
89b667f8 2241
8ac33ed3
DV		 2242 intel_dp_prepare(encoder);
2243
89b667f8 2244 /* Program Tx lane resets to default */
0980a60f 2245 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2246 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2247 DPIO_PCS_TX_LANE2_RESET |
2248 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2249 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2250 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2251 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2252 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2253 DPIO_PCS_CLK_SOFT_RESET);
2254
2255 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2256 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2257 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2258 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2259 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2260}
2261
e4a1d846
CML		 2262static void chv_pre_enable_dp(struct intel_encoder *encoder)
2263{
2264 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2265 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2266 struct drm_device *dev = encoder->base.dev;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct edp_power_seq power_seq;
2269 struct intel_crtc *intel_crtc =
2270 to_intel_crtc(encoder->base.crtc);
2271 enum dpio_channel ch = vlv_dport_to_channel(dport);
2272 int pipe = intel_crtc->pipe;
2273 int data, i;
949c1d43 2274 u32 val;
e4a1d846 2275
e4a1d846 2276 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2277
2278 /* Deassert soft data lane reset*/
97fd4d5c 2279 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2280 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2281 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2282
2283 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2284 val |= CHV_PCS_REQ_SOFTRESET_EN;
2285 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2286
2287 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2288 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2289 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2290
97fd4d5c 2291 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2292 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2293 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2294
2295 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2296 for (i = 0; i < 4; i++) {
2297 /* Set the latency optimal bit */
2298 data = (i == 1) ? 0x0 : 0x6;
2299 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2300 data << DPIO_FRC_LATENCY_SHFIT);
2301
2302 /* Set the upar bit */
2303 data = (i == 1) ? 0x0 : 0x1;
2304 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2305 data << DPIO_UPAR_SHIFT);
2306 }
2307
2308 /* Data lane stagger programming */
2309 /* FIXME: Fix up value only after power analysis */
2310
2311 mutex_unlock(&dev_priv->dpio_lock);
2312
2313 if (is_edp(intel_dp)) {
2314 /* init power sequencer on this pipe and port */
2315 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2316 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2317 &power_seq);
2318 }
2319
2320 intel_enable_dp(encoder);
2321
2322 vlv_wait_port_ready(dev_priv, dport);
2323}
2324
9197c88b
VS		 2325static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2326{
2327 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2328 struct drm_device *dev = encoder->base.dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 struct intel_crtc *intel_crtc =
2331 to_intel_crtc(encoder->base.crtc);
2332 enum dpio_channel ch = vlv_dport_to_channel(dport);
2333 enum pipe pipe = intel_crtc->pipe;
2334 u32 val;
2335
625695f8
VS		 2336 intel_dp_prepare(encoder);
2337
9197c88b
VS		 2338 mutex_lock(&dev_priv->dpio_lock);
2339
b9e5ac3c
VS		 2340 /* program left/right clock distribution */
2341 if (pipe != PIPE_B) {
2342 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2343 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2344 if (ch == DPIO_CH0)
2345 val |= CHV_BUFLEFTENA1_FORCE;
2346 if (ch == DPIO_CH1)
2347 val |= CHV_BUFRIGHTENA1_FORCE;
2348 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2349 } else {
2350 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2351 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2352 if (ch == DPIO_CH0)
2353 val |= CHV_BUFLEFTENA2_FORCE;
2354 if (ch == DPIO_CH1)
2355 val |= CHV_BUFRIGHTENA2_FORCE;
2356 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2357 }
2358
9197c88b
VS		 2359 /* program clock channel usage */
2360 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2361 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2362 if (pipe != PIPE_B)
2363 val &= ~CHV_PCS_USEDCLKCHANNEL;
2364 else
2365 val |= CHV_PCS_USEDCLKCHANNEL;
2366 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2367
2368 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2369 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2370 if (pipe != PIPE_B)
2371 val &= ~CHV_PCS_USEDCLKCHANNEL;
2372 else
2373 val |= CHV_PCS_USEDCLKCHANNEL;
2374 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2375
2376 /*
2377 * This a a bit weird since generally CL
2378 * matches the pipe, but here we need to
2379 * pick the CL based on the port.
2380 */
2381 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2382 if (pipe != PIPE_B)
2383 val &= ~CHV_CMN_USEDCLKCHANNEL;
2384 else
2385 val |= CHV_CMN_USEDCLKCHANNEL;
2386 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2387
2388 mutex_unlock(&dev_priv->dpio_lock);
2389}
2390
a4fc5ed6 2391/*
df0c237d
JB		 2392 * Native read with retry for link status and receiver capability reads for
2393 * cases where the sink may still be asleep.
9d1a1031
JN		 2394 *
2395 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2396 * supposed to retry 3 times per the spec.
a4fc5ed6 2397 */
9d1a1031
JN		 2398static ssize_t
2399intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2400 void *buffer, size_t size)
a4fc5ed6 2401{
9d1a1031
JN		 2402 ssize_t ret;
2403 int i;
61da5fab 2404
61da5fab 2405 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2406 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2407 if (ret == size)
2408 return ret;
61da5fab
JB		 2409 msleep(1);
2410 }
a4fc5ed6 2411
9d1a1031 2412 return ret;
a4fc5ed6
KP		 2413}
2414
2415/*
2416 * Fetch AUX CH registers 0x202 - 0x207 which contain
2417 * link status information
2418 */
2419static bool
93f62dad 2420intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2421{
9d1a1031
JN		 2422 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2423 DP_LANE0_1_STATUS,
2424 link_status,
2425 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2426}
2427
1100244e 2428/* These are source-specific values. */
a4fc5ed6 2429static uint8_t
1a2eb460 2430intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2431{
30add22d 2432 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2433 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2434
9576c27f 2435 if (IS_VALLEYVIEW(dev))
bd60018a 2436 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2437 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2438 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2439 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2440 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2441 else
bd60018a 2442 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2443}
2444
2445static uint8_t
2446intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2447{
30add22d 2448 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2449 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2450
9576c27f 2451 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2452 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2454 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2455 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2456 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2458 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2460 default:
bd60018a 2461 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2462 }
e2fa6fba
P		 2463 } else if (IS_VALLEYVIEW(dev)) {
2464 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2465 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2466 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2467 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2468 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2469 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2470 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2471 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2472 default:
bd60018a 2473 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2474 }
bc7d38a4 2475 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2476 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2477 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2478 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2479 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2480 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2481 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2482 default:
bd60018a 2483 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2484 }
2485 } else {
2486 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2487 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2488 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2489 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2490 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2491 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2492 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2493 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2494 default:
bd60018a 2495 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2496 }
a4fc5ed6
KP		 2497 }
2498}
2499
e2fa6fba
P		 2500static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2501{
2502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2505 struct intel_crtc *intel_crtc =
2506 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2507 unsigned long demph_reg_value, preemph_reg_value,
2508 uniqtranscale_reg_value;
2509 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2510 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2511 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2512
2513 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2514 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2515 preemph_reg_value = 0x0004000;
2516 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2517 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2518 demph_reg_value = 0x2B405555;
2519 uniqtranscale_reg_value = 0x552AB83A;
2520 break;
bd60018a 2521 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2522 demph_reg_value = 0x2B404040;
2523 uniqtranscale_reg_value = 0x5548B83A;
2524 break;
bd60018a 2525 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2526 demph_reg_value = 0x2B245555;
2527 uniqtranscale_reg_value = 0x5560B83A;
2528 break;
bd60018a 2529 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2530 demph_reg_value = 0x2B405555;
2531 uniqtranscale_reg_value = 0x5598DA3A;
2532 break;
2533 default:
2534 return 0;
2535 }
2536 break;
bd60018a 2537 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2538 preemph_reg_value = 0x0002000;
2539 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2540 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2541 demph_reg_value = 0x2B404040;
2542 uniqtranscale_reg_value = 0x5552B83A;
2543 break;
bd60018a 2544 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2545 demph_reg_value = 0x2B404848;
2546 uniqtranscale_reg_value = 0x5580B83A;
2547 break;
bd60018a 2548 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2549 demph_reg_value = 0x2B404040;
2550 uniqtranscale_reg_value = 0x55ADDA3A;
2551 break;
2552 default:
2553 return 0;
2554 }
2555 break;
bd60018a 2556 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2557 preemph_reg_value = 0x0000000;
2558 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2559 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2560 demph_reg_value = 0x2B305555;
2561 uniqtranscale_reg_value = 0x5570B83A;
2562 break;
bd60018a 2563 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2564 demph_reg_value = 0x2B2B4040;
2565 uniqtranscale_reg_value = 0x55ADDA3A;
2566 break;
2567 default:
2568 return 0;
2569 }
2570 break;
bd60018a 2571 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2572 preemph_reg_value = 0x0006000;
2573 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2574 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2575 demph_reg_value = 0x1B405555;
2576 uniqtranscale_reg_value = 0x55ADDA3A;
2577 break;
2578 default:
2579 return 0;
2580 }
2581 break;
2582 default:
2583 return 0;
2584 }
2585
0980a60f 2586 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2587 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2588 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2589 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2590 uniqtranscale_reg_value);
ab3c759a
CML		 2591 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2592 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2593 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2594 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2595 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2596
2597 return 0;
2598}
2599
e4a1d846
CML		 2600static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2601{
2602 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2605 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2606 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2607 uint8_t train_set = intel_dp->train_set[0];
2608 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2609 enum pipe pipe = intel_crtc->pipe;
2610 int i;
e4a1d846
CML		 2611
2612 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2613 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2614 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2615 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2616 deemph_reg_value = 128;
2617 margin_reg_value = 52;
2618 break;
bd60018a 2619 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2620 deemph_reg_value = 128;
2621 margin_reg_value = 77;
2622 break;
bd60018a 2623 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2624 deemph_reg_value = 128;
2625 margin_reg_value = 102;
2626 break;
bd60018a 2627 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2628 deemph_reg_value = 128;
2629 margin_reg_value = 154;
2630 /* FIXME extra to set for 1200 */
2631 break;
2632 default:
2633 return 0;
2634 }
2635 break;
bd60018a 2636 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2637 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2638 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2639 deemph_reg_value = 85;
2640 margin_reg_value = 78;
2641 break;
bd60018a 2642 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2643 deemph_reg_value = 85;
2644 margin_reg_value = 116;
2645 break;
bd60018a 2646 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2647 deemph_reg_value = 85;
2648 margin_reg_value = 154;
2649 break;
2650 default:
2651 return 0;
2652 }
2653 break;
bd60018a 2654 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2655 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2656 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2657 deemph_reg_value = 64;
2658 margin_reg_value = 104;
2659 break;
bd60018a 2660 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2661 deemph_reg_value = 64;
2662 margin_reg_value = 154;
2663 break;
2664 default:
2665 return 0;
2666 }
2667 break;
bd60018a 2668 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2669 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2670 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2671 deemph_reg_value = 43;
2672 margin_reg_value = 154;
2673 break;
2674 default:
2675 return 0;
2676 }
2677 break;
2678 default:
2679 return 0;
2680 }
2681
2682 mutex_lock(&dev_priv->dpio_lock);
2683
2684 /* Clear calc init */
1966e59e
VS		 2685 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2686 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2687 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2688
2689 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2690 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2691 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2692
2693 /* Program swing deemph */
f72df8db
VS		 2694 for (i = 0; i < 4; i++) {
2695 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2696 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2697 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2698 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2699 }
e4a1d846
CML		 2700
2701 /* Program swing margin */
f72df8db
VS		 2702 for (i = 0; i < 4; i++) {
2703 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2704 val &= ~DPIO_SWING_MARGIN000_MASK;
2705 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2706 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2707 }
e4a1d846
CML		 2708
2709 /* Disable unique transition scale */
f72df8db
VS		 2710 for (i = 0; i < 4; i++) {
2711 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2712 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2713 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2714 }
e4a1d846
CML		 2715
2716 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 2717 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 2718 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 2719 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 2720
2721 /*
2722 * The document said it needs to set bit 27 for ch0 and bit 26
2723 * for ch1. Might be a typo in the doc.
2724 * For now, for this unique transition scale selection, set bit
2725 * 27 for ch0 and ch1.
2726 */
f72df8db
VS		 2727 for (i = 0; i < 4; i++) {
2728 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2729 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2730 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2731 }
e4a1d846 2732
f72df8db
VS		 2733 for (i = 0; i < 4; i++) {
2734 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2735 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2736 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2737 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2738 }
e4a1d846
CML		 2739 }
2740
2741 /* Start swing calculation */
1966e59e
VS		 2742 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2743 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2744 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2745
2746 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2747 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2748 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2749
2750 /* LRC Bypass */
2751 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2752 val |= DPIO_LRC_BYPASS;
2753 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2754
2755 mutex_unlock(&dev_priv->dpio_lock);
2756
2757 return 0;
2758}
2759
a4fc5ed6 2760static void
0301b3ac
JN		 2761intel_get_adjust_train(struct intel_dp *intel_dp,
2762 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2763{
2764 uint8_t v = 0;
2765 uint8_t p = 0;
2766 int lane;
1a2eb460
KP		 2767 uint8_t voltage_max;
2768 uint8_t preemph_max;
a4fc5ed6 2769
33a34e4e 2770 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2771 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2772 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2773
2774 if (this_v > v)
2775 v = this_v;
2776 if (this_p > p)
2777 p = this_p;
2778 }
2779
1a2eb460 2780 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2781 if (v >= voltage_max)
2782 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2783
1a2eb460
KP		 2784 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2785 if (p >= preemph_max)
2786 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2787
2788 for (lane = 0; lane < 4; lane++)
33a34e4e 2789 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2790}
2791
2792static uint32_t
f0a3424e 2793intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2794{
3cf2efb1 2795 uint32_t signal_levels = 0;
a4fc5ed6 2796
3cf2efb1 2797 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2798 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 2799 default:
2800 signal_levels |= DP_VOLTAGE_0_4;
2801 break;
bd60018a 2802 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 2803 signal_levels |= DP_VOLTAGE_0_6;
2804 break;
bd60018a 2805 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 2806 signal_levels |= DP_VOLTAGE_0_8;
2807 break;
bd60018a 2808 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 2809 signal_levels |= DP_VOLTAGE_1_2;
2810 break;
2811 }
3cf2efb1 2812 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2813 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 2814 default:
2815 signal_levels |= DP_PRE_EMPHASIS_0;
2816 break;
bd60018a 2817 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 2818 signal_levels |= DP_PRE_EMPHASIS_3_5;
2819 break;
bd60018a 2820 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 2821 signal_levels |= DP_PRE_EMPHASIS_6;
2822 break;
bd60018a 2823 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 2824 signal_levels |= DP_PRE_EMPHASIS_9_5;
2825 break;
2826 }
2827 return signal_levels;
2828}
2829
e3421a18
ZW		 2830/* Gen6's DP voltage swing and pre-emphasis control */
2831static uint32_t
2832intel_gen6_edp_signal_levels(uint8_t train_set)
2833{
3c5a62b5
YL		 2834 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2835 DP_TRAIN_PRE_EMPHASIS_MASK);
2836 switch (signal_levels) {
bd60018a
SJ		 2837 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2838 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 2839 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 2840 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 2841 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 2842 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2843 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 2844 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 2845 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2846 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 2847 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 2848 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2849 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 2850 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2851 default:
3c5a62b5
YL		 2852 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2853 "0x%x\n", signal_levels);
2854 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2855 }
2856}
2857
1a2eb460
KP		 2858/* Gen7's DP voltage swing and pre-emphasis control */
2859static uint32_t
2860intel_gen7_edp_signal_levels(uint8_t train_set)
2861{
2862 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2863 DP_TRAIN_PRE_EMPHASIS_MASK);
2864 switch (signal_levels) {
bd60018a 2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 2866 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 2867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 2868 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 2869 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 2870 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2871
bd60018a 2872 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 2873 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 2874 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 2875 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2876
bd60018a 2877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 2878 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 2879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 2880 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2881
2882 default:
2883 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2884 "0x%x\n", signal_levels);
2885 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2886 }
2887}
2888
d6c0d722
PZ		 2889/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2890static uint32_t
f0a3424e 2891intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2892{
d6c0d722
PZ		 2893 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2894 DP_TRAIN_PRE_EMPHASIS_MASK);
2895 switch (signal_levels) {
bd60018a 2896 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 2897 return DDI_BUF_TRANS_SELECT(0);
bd60018a 2898 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 2899 return DDI_BUF_TRANS_SELECT(1);
bd60018a 2900 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 2901 return DDI_BUF_TRANS_SELECT(2);
bd60018a 2902 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 2903 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 2904
bd60018a 2905 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 2906 return DDI_BUF_TRANS_SELECT(4);
bd60018a 2907 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 2908 return DDI_BUF_TRANS_SELECT(5);
bd60018a 2909 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 2910 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 2911
bd60018a 2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 2913 return DDI_BUF_TRANS_SELECT(7);
bd60018a 2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 2915 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 2916 default:
2917 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2918 "0x%x\n", signal_levels);
c5fe6a06 2919 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 2920 }
a4fc5ed6
KP		 2921}
2922
f0a3424e
PZ		 2923/* Properly updates "DP" with the correct signal levels. */
2924static void
2925intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2926{
2927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2928 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2929 struct drm_device *dev = intel_dig_port->base.base.dev;
2930 uint32_t signal_levels, mask;
2931 uint8_t train_set = intel_dp->train_set[0];
2932
9576c27f 2933 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2934 signal_levels = intel_hsw_signal_levels(train_set);
2935 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2936 } else if (IS_CHERRYVIEW(dev)) {
2937 signal_levels = intel_chv_signal_levels(intel_dp);
2938 mask = 0;
e2fa6fba
P		 2939 } else if (IS_VALLEYVIEW(dev)) {
2940 signal_levels = intel_vlv_signal_levels(intel_dp);
2941 mask = 0;
bc7d38a4 2942 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2943 signal_levels = intel_gen7_edp_signal_levels(train_set);
2944 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2945 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2946 signal_levels = intel_gen6_edp_signal_levels(train_set);
2947 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2948 } else {
2949 signal_levels = intel_gen4_signal_levels(train_set);
2950 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2951 }
2952
2953 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2954
2955 *DP = (*DP & ~mask) | signal_levels;
2956}
2957
a4fc5ed6 2958static bool
ea5b213a 2959intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2960 uint32_t *DP,
58e10eb9 2961 uint8_t dp_train_pat)
a4fc5ed6 2962{
174edf1f
PZ		 2963 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2964 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2965 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2966 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2967 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2968 int ret, len;
a4fc5ed6 2969
22b8bf17 2970 if (HAS_DDI(dev)) {
3ab9c637 2971 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2972
2973 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2974 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2975 else
2976 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2977
2978 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2979 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2980 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2981 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2982
2983 break;
2984 case DP_TRAINING_PATTERN_1:
2985 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2986 break;
2987 case DP_TRAINING_PATTERN_2:
2988 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2989 break;
2990 case DP_TRAINING_PATTERN_3:
2991 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2992 break;
2993 }
174edf1f 2994 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2995
bc7d38a4 2996 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2997 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2998
2999 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3000 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3001 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 3002 break;
3003 case DP_TRAINING_PATTERN_1:
70aff66c 3004 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 3005 break;
3006 case DP_TRAINING_PATTERN_2:
70aff66c 3007 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3008 break;
3009 case DP_TRAINING_PATTERN_3:
3010 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 3011 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3012 break;
3013 }
3014
3015 } else {
aad3d14d
VS		 3016 if (IS_CHERRYVIEW(dev))
3017 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3018 else
3019 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 3020
3021 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3022 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3023 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 3024 break;
3025 case DP_TRAINING_PATTERN_1:
70aff66c 3026 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 3027 break;
3028 case DP_TRAINING_PATTERN_2:
70aff66c 3029 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 3030 break;
3031 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 3032 if (IS_CHERRYVIEW(dev)) {
3033 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3034 } else {
3035 DRM_ERROR("DP training pattern 3 not supported\n");
3036 *DP |= DP_LINK_TRAIN_PAT_2;
3037 }
47ea7542
PZ		 3038 break;
3039 }
3040 }
3041
70aff66c 3042 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3043 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3044
2cdfe6c8
JN		 3045 buf[0] = dp_train_pat;
3046 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3047 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3048 /* don't write DP_TRAINING_LANEx_SET on disable */
3049 len = 1;
3050 } else {
3051 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3052 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3053 len = intel_dp->lane_count + 1;
47ea7542 3054 }
a4fc5ed6 3055
9d1a1031
JN		 3056 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3057 buf, len);
2cdfe6c8
JN		 3058
3059 return ret == len;
a4fc5ed6
KP		 3060}
3061
70aff66c
JN		 3062static bool
3063intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3064 uint8_t dp_train_pat)
3065{
953d22e8 3066 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3067 intel_dp_set_signal_levels(intel_dp, DP);
3068 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3069}
3070
3071static bool
3072intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3073 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3074{
3075 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3076 struct drm_device *dev = intel_dig_port->base.base.dev;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 int ret;
3079
3080 intel_get_adjust_train(intel_dp, link_status);
3081 intel_dp_set_signal_levels(intel_dp, DP);
3082
3083 I915_WRITE(intel_dp->output_reg, *DP);
3084 POSTING_READ(intel_dp->output_reg);
3085
9d1a1031
JN		 3086 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3087 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3088
3089 return ret == intel_dp->lane_count;
3090}
3091
3ab9c637
ID		 3092static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3093{
3094 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3095 struct drm_device *dev = intel_dig_port->base.base.dev;
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3097 enum port port = intel_dig_port->port;
3098 uint32_t val;
3099
3100 if (!HAS_DDI(dev))
3101 return;
3102
3103 val = I915_READ(DP_TP_CTL(port));
3104 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3105 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3106 I915_WRITE(DP_TP_CTL(port), val);
3107
3108 /*
3109 * On PORT_A we can have only eDP in SST mode. There the only reason
3110 * we need to set idle transmission mode is to work around a HW issue
3111 * where we enable the pipe while not in idle link-training mode.
3112 * In this case there is requirement to wait for a minimum number of
3113 * idle patterns to be sent.
3114 */
3115 if (port == PORT_A)
3116 return;
3117
3118 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3119 1))
3120 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3121}
3122
33a34e4e 3123/* Enable corresponding port and start training pattern 1 */
c19b0669 3124void
33a34e4e 3125intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3126{
da63a9f2 3127 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3128 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3129 int i;
3130 uint8_t voltage;
cdb0e95b 3131 int voltage_tries, loop_tries;
ea5b213a 3132 uint32_t DP = intel_dp->DP;
6aba5b6c 3133 uint8_t link_config[2];
a4fc5ed6 3134
affa9354 3135 if (HAS_DDI(dev))
c19b0669
PZ		 3136 intel_ddi_prepare_link_retrain(encoder);
3137
3cf2efb1 3138 /* Write the link configuration data */
6aba5b6c
JN		 3139 link_config[0] = intel_dp->link_bw;
3140 link_config[1] = intel_dp->lane_count;
3141 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3142 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3143 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3144
3145 link_config[0] = 0;
3146 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3147 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3148
3149 DP |= DP_PORT_EN;
1a2eb460 3150
70aff66c
JN		 3151 /* clock recovery */
3152 if (!intel_dp_reset_link_train(intel_dp, &DP,
3153 DP_TRAINING_PATTERN_1 |
3154 DP_LINK_SCRAMBLING_DISABLE)) {
3155 DRM_ERROR("failed to enable link training\n");
3156 return;
3157 }
3158
a4fc5ed6 3159 voltage = 0xff;
cdb0e95b
KP		 3160 voltage_tries = 0;
3161 loop_tries = 0;
a4fc5ed6 3162 for (;;) {
70aff66c 3163 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3164
a7c9655f 3165 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3166 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3167 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3168 break;
93f62dad 3169 }
a4fc5ed6 3170
01916270 3171 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3172 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3173 break;
3174 }
3175
3176 /* Check to see if we've tried the max voltage */
3177 for (i = 0; i < intel_dp->lane_count; i++)
3178 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3179 break;
3b4f819d 3180 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3181 ++loop_tries;
3182 if (loop_tries == 5) {
3def84b3 3183 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3184 break;
3185 }
70aff66c
JN		 3186 intel_dp_reset_link_train(intel_dp, &DP,
3187 DP_TRAINING_PATTERN_1 |
3188 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3189 voltage_tries = 0;
3190 continue;
3191 }
a4fc5ed6 3192
3cf2efb1 3193 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3194 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3195 ++voltage_tries;
b06fbda3 3196 if (voltage_tries == 5) {
3def84b3 3197 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3198 break;
3199 }
3200 } else
3201 voltage_tries = 0;
3202 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3203
70aff66c
JN		 3204 /* Update training set as requested by target */
3205 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3206 DRM_ERROR("failed to update link training\n");
3207 break;
3208 }
a4fc5ed6
KP		 3209 }
3210
33a34e4e
JB		 3211 intel_dp->DP = DP;
3212}
3213
c19b0669 3214void
33a34e4e
JB		 3215intel_dp_complete_link_train(struct intel_dp *intel_dp)
3216{
33a34e4e 3217 bool channel_eq = false;
37f80975 3218 int tries, cr_tries;
33a34e4e 3219 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3220 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3221
3222 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3223 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3224 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3225
a4fc5ed6 3226 /* channel equalization */
70aff66c 3227 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3228 training_pattern |
70aff66c
JN		 3229 DP_LINK_SCRAMBLING_DISABLE)) {
3230 DRM_ERROR("failed to start channel equalization\n");
3231 return;
3232 }
3233
a4fc5ed6 3234 tries = 0;
37f80975 3235 cr_tries = 0;
a4fc5ed6
KP		 3236 channel_eq = false;
3237 for (;;) {
70aff66c 3238 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3239
37f80975
JB		 3240 if (cr_tries > 5) {
3241 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3242 break;
3243 }
3244
a7c9655f 3245 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3246 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3247 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3248 break;
70aff66c 3249 }
a4fc5ed6 3250
37f80975 3251 /* Make sure clock is still ok */
01916270 3252 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3253 intel_dp_start_link_train(intel_dp);
70aff66c 3254 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3255 training_pattern |
70aff66c 3256 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3257 cr_tries++;
3258 continue;
3259 }
3260
1ffdff13 3261 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3262 channel_eq = true;
3263 break;
3264 }
a4fc5ed6 3265
37f80975
JB		 3266 /* Try 5 times, then try clock recovery if that fails */
3267 if (tries > 5) {
3268 intel_dp_link_down(intel_dp);
3269 intel_dp_start_link_train(intel_dp);
70aff66c 3270 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3271 training_pattern |
70aff66c 3272 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3273 tries = 0;
3274 cr_tries++;
3275 continue;
3276 }
a4fc5ed6 3277
70aff66c
JN		 3278 /* Update training set as requested by target */
3279 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3280 DRM_ERROR("failed to update link training\n");
3281 break;
3282 }
3cf2efb1 3283 ++tries;
869184a6 3284 }
3cf2efb1 3285
3ab9c637
ID		 3286 intel_dp_set_idle_link_train(intel_dp);
3287
3288 intel_dp->DP = DP;
3289
d6c0d722 3290 if (channel_eq)
07f42258 3291 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3292
3ab9c637
ID		 3293}
3294
3295void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3296{
70aff66c 3297 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3298 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3299}
3300
3301static void
ea5b213a 3302intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3303{
da63a9f2 3304 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3305 enum port port = intel_dig_port->port;
da63a9f2 3306 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3307 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3308 struct intel_crtc *intel_crtc =
3309 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3310 uint32_t DP = intel_dp->DP;
a4fc5ed6 3311
bc76e320 3312 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3313 return;
3314
0c33d8d7 3315 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3316 return;
3317
28c97730 3318 DRM_DEBUG_KMS("\n");
32f9d658 3319
bc7d38a4 3320 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3321 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3322 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3323 } else {
aad3d14d
VS		 3324 if (IS_CHERRYVIEW(dev))
3325 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3326 else
3327 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3328 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3329 }
fe255d00 3330 POSTING_READ(intel_dp->output_reg);
5eb08b69 3331
493a7081 3332 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3333 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3334 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3335
5bddd17f
EA		 3336 /* Hardware workaround: leaving our transcoder select
3337 * set to transcoder B while it's off will prevent the
3338 * corresponding HDMI output on transcoder A.
3339 *
3340 * Combine this with another hardware workaround:
3341 * transcoder select bit can only be cleared while the
3342 * port is enabled.
3343 */
3344 DP &= ~DP_PIPEB_SELECT;
3345 I915_WRITE(intel_dp->output_reg, DP);
3346
3347 /* Changes to enable or select take place the vblank
3348 * after being written.
3349 */
ff50afe9
DV		 3350 if (WARN_ON(crtc == NULL)) {
3351 /* We should never try to disable a port without a crtc
3352 * attached. For paranoia keep the code around for a
3353 * bit. */
31acbcc4
CW		 3354 POSTING_READ(intel_dp->output_reg);
3355 msleep(50);
3356 } else
ab527efc 3357 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3358 }
3359
832afda6 3360 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3361 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3362 POSTING_READ(intel_dp->output_reg);
f01eca2e 3363 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3364}
3365
26d61aad
KP		 3366static bool
3367intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3368{
a031d709
RV		 3369 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3370 struct drm_device *dev = dig_port->base.base.dev;
3371 struct drm_i915_private *dev_priv = dev->dev_private;
3372
9d1a1031
JN		 3373 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3374 sizeof(intel_dp->dpcd)) < 0)
edb39244 3375 return false; /* aux transfer failed */
92fd8fd1 3376
a8e98153 3377 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3378
edb39244
AJ		 3379 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3380 return false; /* DPCD not present */
3381
2293bb5c
SK		 3382 /* Check if the panel supports PSR */
3383 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3384 if (is_edp(intel_dp)) {
9d1a1031
JN		 3385 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3386 intel_dp->psr_dpcd,
3387 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3388 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3389 dev_priv->psr.sink_support = true;
50003939 3390 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3391 }
50003939
JN		 3392 }
3393
06ea66b6
TP		 3394 /* Training Pattern 3 support */
3395 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3396 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3397 intel_dp->use_tps3 = true;
3398 DRM_DEBUG_KMS("Displayport TPS3 supported");
3399 } else
3400 intel_dp->use_tps3 = false;
3401
edb39244
AJ		 3402 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3403 DP_DWN_STRM_PORT_PRESENT))
3404 return true; /* native DP sink */
3405
3406 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3407 return true; /* no per-port downstream info */
3408
9d1a1031
JN		 3409 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3410 intel_dp->downstream_ports,
3411 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3412 return false; /* downstream port status fetch failed */
3413
3414 return true;
92fd8fd1
KP		 3415}
3416
0d198328
AJ		 3417static void
3418intel_dp_probe_oui(struct intel_dp *intel_dp)
3419{
3420 u8 buf[3];
3421
3422 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3423 return;
3424
24f3e092 3425 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3426
9d1a1031 3427 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3428 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3429 buf[0], buf[1], buf[2]);
3430
9d1a1031 3431 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3432 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3433 buf[0], buf[1], buf[2]);
351cfc34 3434
1e0560e0 3435 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3436}
3437
0e32b39c
DA		 3438static bool
3439intel_dp_probe_mst(struct intel_dp *intel_dp)
3440{
3441 u8 buf[1];
3442
3443 if (!intel_dp->can_mst)
3444 return false;
3445
3446 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3447 return false;
3448
d337a341 3449 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3450 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3451 if (buf[0] & DP_MST_CAP) {
3452 DRM_DEBUG_KMS("Sink is MST capable\n");
3453 intel_dp->is_mst = true;
3454 } else {
3455 DRM_DEBUG_KMS("Sink is not MST capable\n");
3456 intel_dp->is_mst = false;
3457 }
3458 }
1e0560e0 3459 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3460
3461 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3462 return intel_dp->is_mst;
3463}
3464
d2e216d0
RV		 3465int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3466{
3467 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3468 struct drm_device *dev = intel_dig_port->base.base.dev;
3469 struct intel_crtc *intel_crtc =
3470 to_intel_crtc(intel_dig_port->base.base.crtc);
3471 u8 buf[1];
3472
9d1a1031 3473 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3474 return -EAGAIN;
3475
3476 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3477 return -ENOTTY;
3478
9d1a1031
JN		 3479 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3480 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3481 return -EAGAIN;
3482
3483 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3484 intel_wait_for_vblank(dev, intel_crtc->pipe);
3485 intel_wait_for_vblank(dev, intel_crtc->pipe);
3486
9d1a1031 3487 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3488 return -EAGAIN;
3489
9d1a1031 3490 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3491 return 0;
3492}
3493
a60f0e38
JB		 3494static bool
3495intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3496{
9d1a1031
JN		 3497 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3498 DP_DEVICE_SERVICE_IRQ_VECTOR,
3499 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3500}
3501
0e32b39c
DA		 3502static bool
3503intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3504{
3505 int ret;
3506
3507 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3508 DP_SINK_COUNT_ESI,
3509 sink_irq_vector, 14);
3510 if (ret != 14)
3511 return false;
3512
3513 return true;
3514}
3515
a60f0e38
JB		 3516static void
3517intel_dp_handle_test_request(struct intel_dp *intel_dp)
3518{
3519 /* NAK by default */
9d1a1031 3520 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3521}
3522
0e32b39c
DA		 3523static int
3524intel_dp_check_mst_status(struct intel_dp *intel_dp)
3525{
3526 bool bret;
3527
3528 if (intel_dp->is_mst) {
3529 u8 esi[16] = { 0 };
3530 int ret = 0;
3531 int retry;
3532 bool handled;
3533 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3534go_again:
3535 if (bret == true) {
3536
3537 /* check link status - esi[10] = 0x200c */
3538 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3539 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3540 intel_dp_start_link_train(intel_dp);
3541 intel_dp_complete_link_train(intel_dp);
3542 intel_dp_stop_link_train(intel_dp);
3543 }
3544
3545 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3546 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3547
3548 if (handled) {
3549 for (retry = 0; retry < 3; retry++) {
3550 int wret;
3551 wret = drm_dp_dpcd_write(&intel_dp->aux,
3552 DP_SINK_COUNT_ESI+1,
3553 &esi[1], 3);
3554 if (wret == 3) {
3555 break;
3556 }
3557 }
3558
3559 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3560 if (bret == true) {
3561 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3562 goto go_again;
3563 }
3564 } else
3565 ret = 0;
3566
3567 return ret;
3568 } else {
3569 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3570 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3571 intel_dp->is_mst = false;
3572 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3573 /* send a hotplug event */
3574 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3575 }
3576 }
3577 return -EINVAL;
3578}
3579
a4fc5ed6
KP		 3580/*
3581 * According to DP spec
3582 * 5.1.2:
3583 * 1. Read DPCD
3584 * 2. Configure link according to Receiver Capabilities
3585 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3586 * 4. Check link status on receipt of hot-plug interrupt
3587 */
00c09d70 3588void
ea5b213a 3589intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3590{
5b215bcf 3591 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3592 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3593 u8 sink_irq_vector;
93f62dad 3594 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3595
5b215bcf
DA		 3596 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3597
da63a9f2 3598 if (!intel_encoder->connectors_active)
d2b996ac 3599 return;
59cd09e1 3600
da63a9f2 3601 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3602 return;
3603
1a125d8a
ID		 3604 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3605 return;
3606
92fd8fd1 3607 /* Try to read receiver status if the link appears to be up */
93f62dad 3608 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3609 return;
3610 }
3611
92fd8fd1 3612 /* Now read the DPCD to see if it's actually running */
26d61aad 3613 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3614 return;
3615 }
3616
a60f0e38
JB		 3617 /* Try to read the source of the interrupt */
3618 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3619 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3620 /* Clear interrupt source */
9d1a1031
JN		 3621 drm_dp_dpcd_writeb(&intel_dp->aux,
3622 DP_DEVICE_SERVICE_IRQ_VECTOR,
3623 sink_irq_vector);
a60f0e38
JB		 3624
3625 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3626 intel_dp_handle_test_request(intel_dp);
3627 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3628 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3629 }
3630
1ffdff13 3631 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3632 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3633 intel_encoder->base.name);
33a34e4e
JB		 3634 intel_dp_start_link_train(intel_dp);
3635 intel_dp_complete_link_train(intel_dp);
3ab9c637 3636 intel_dp_stop_link_train(intel_dp);
33a34e4e 3637 }
a4fc5ed6 3638}
a4fc5ed6 3639
caf9ab24 3640/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3641static enum drm_connector_status
26d61aad 3642intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3643{
caf9ab24 3644 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3645 uint8_t type;
3646
3647 if (!intel_dp_get_dpcd(intel_dp))
3648 return connector_status_disconnected;
3649
3650 /* if there's no downstream port, we're done */
3651 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3652 return connector_status_connected;
caf9ab24
AJ		 3653
3654 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3655 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3656 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3657 uint8_t reg;
9d1a1031
JN		 3658
3659 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3660 &reg, 1) < 0)
caf9ab24 3661 return connector_status_unknown;
9d1a1031 3662
23235177
AJ		 3663 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3664 : connector_status_disconnected;
caf9ab24
AJ		 3665 }
3666
3667 /* If no HPD, poke DDC gently */
0b99836f 3668 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3669 return connector_status_connected;
caf9ab24
AJ		 3670
3671 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3672 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3673 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3674 if (type == DP_DS_PORT_TYPE_VGA ||
3675 type == DP_DS_PORT_TYPE_NON_EDID)
3676 return connector_status_unknown;
3677 } else {
3678 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3679 DP_DWN_STRM_PORT_TYPE_MASK;
3680 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3681 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3682 return connector_status_unknown;
3683 }
caf9ab24
AJ		 3684
3685 /* Anything else is out of spec, warn and ignore */
3686 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3687 return connector_status_disconnected;
71ba9000
AJ		 3688}
3689
d410b56d
CW		 3690static enum drm_connector_status
3691edp_detect(struct intel_dp *intel_dp)
3692{
3693 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3694 enum drm_connector_status status;
3695
3696 status = intel_panel_detect(dev);
3697 if (status == connector_status_unknown)
3698 status = connector_status_connected;
3699
3700 return status;
3701}
3702
5eb08b69 3703static enum drm_connector_status
a9756bb5 3704ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3705{
30add22d 3706 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3709
1b469639
DL		 3710 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3711 return connector_status_disconnected;
3712
26d61aad 3713 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3714}
3715
a4fc5ed6 3716static enum drm_connector_status
a9756bb5 3717g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3718{
30add22d 3719 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3720 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3721 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3722 uint32_t bit;
5eb08b69 3723
232a6ee9
TP		 3724 if (IS_VALLEYVIEW(dev)) {
3725 switch (intel_dig_port->port) {
3726 case PORT_B:
3727 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3728 break;
3729 case PORT_C:
3730 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3731 break;
3732 case PORT_D:
3733 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3734 break;
3735 default:
3736 return connector_status_unknown;
3737 }
3738 } else {
3739 switch (intel_dig_port->port) {
3740 case PORT_B:
3741 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3742 break;
3743 case PORT_C:
3744 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3745 break;
3746 case PORT_D:
3747 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3748 break;
3749 default:
3750 return connector_status_unknown;
3751 }
a4fc5ed6
KP		 3752 }
3753
10f76a38 3754 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3755 return connector_status_disconnected;
3756
26d61aad 3757 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3758}
3759
8c241fef 3760static struct edid *
beb60608 3761intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 3762{
beb60608 3763 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 3764
9cd300e0
JN		 3765 /* use cached edid if we have one */
3766 if (intel_connector->edid) {
9cd300e0
JN		 3767 /* invalid edid */
3768 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3769 return NULL;
3770
55e9edeb 3771 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 3772 } else
3773 return drm_get_edid(&intel_connector->base,
3774 &intel_dp->aux.ddc);
3775}
8c241fef 3776
beb60608
CW		 3777static void
3778intel_dp_set_edid(struct intel_dp *intel_dp)
3779{
3780 struct intel_connector *intel_connector = intel_dp->attached_connector;
3781 struct edid *edid;
3782
3783 edid = intel_dp_get_edid(intel_dp);
3784 intel_connector->detect_edid = edid;
3785
3786 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
3787 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
3788 else
3789 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 3790}
3791
beb60608
CW		 3792static void
3793intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 3794{
beb60608 3795 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 3796
beb60608
CW		 3797 kfree(intel_connector->detect_edid);
3798 intel_connector->detect_edid = NULL;
9cd300e0 3799
beb60608
CW		 3800 intel_dp->has_audio = false;
3801}
d6f24d0f 3802
beb60608
CW		 3803static enum intel_display_power_domain
3804intel_dp_power_get(struct intel_dp *dp)
3805{
3806 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
3807 enum intel_display_power_domain power_domain;
3808
3809 power_domain = intel_display_port_power_domain(encoder);
3810 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
3811
3812 return power_domain;
3813}
3814
3815static void
3816intel_dp_power_put(struct intel_dp *dp,
3817 enum intel_display_power_domain power_domain)
3818{
3819 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
3820 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 3821}
3822
a9756bb5
ZW		 3823static enum drm_connector_status
3824intel_dp_detect(struct drm_connector *connector, bool force)
3825{
3826 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3827 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3828 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3829 struct drm_device *dev = connector->dev;
a9756bb5 3830 enum drm_connector_status status;
671dedd2 3831 enum intel_display_power_domain power_domain;
0e32b39c 3832 bool ret;
a9756bb5 3833
164c8598 3834 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3835 connector->base.id, connector->name);
beb60608 3836 intel_dp_unset_edid(intel_dp);
164c8598 3837
0e32b39c
DA		 3838 if (intel_dp->is_mst) {
3839 /* MST devices are disconnected from a monitor POV */
3840 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3841 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 3842 return connector_status_disconnected;
0e32b39c
DA		 3843 }
3844
beb60608 3845 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 3846
d410b56d
CW		 3847 /* Can't disconnect eDP, but you can close the lid... */
3848 if (is_edp(intel_dp))
3849 status = edp_detect(intel_dp);
3850 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 3851 status = ironlake_dp_detect(intel_dp);
3852 else
3853 status = g4x_dp_detect(intel_dp);
3854 if (status != connector_status_connected)
c8c8fb33 3855 goto out;
a9756bb5 3856
0d198328
AJ		 3857 intel_dp_probe_oui(intel_dp);
3858
0e32b39c
DA		 3859 ret = intel_dp_probe_mst(intel_dp);
3860 if (ret) {
3861 /* if we are in MST mode then this connector
3862 won't appear connected or have anything with EDID on it */
3863 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3864 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3865 status = connector_status_disconnected;
3866 goto out;
3867 }
3868
beb60608 3869 intel_dp_set_edid(intel_dp);
a9756bb5 3870
d63885da
PZ		 3871 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3872 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3873 status = connector_status_connected;
3874
3875out:
beb60608 3876 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 3877 return status;
a4fc5ed6
KP		 3878}
3879
beb60608
CW		 3880static void
3881intel_dp_force(struct drm_connector *connector)
a4fc5ed6 3882{
df0e9248 3883 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 3884 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 3885 enum intel_display_power_domain power_domain;
a4fc5ed6 3886
beb60608
CW		 3887 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3888 connector->base.id, connector->name);
3889 intel_dp_unset_edid(intel_dp);
a4fc5ed6 3890
beb60608
CW		 3891 if (connector->status != connector_status_connected)
3892 return;
671dedd2 3893
beb60608
CW		 3894 power_domain = intel_dp_power_get(intel_dp);
3895
3896 intel_dp_set_edid(intel_dp);
3897
3898 intel_dp_power_put(intel_dp, power_domain);
3899
3900 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3901 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3902}
3903
3904static int intel_dp_get_modes(struct drm_connector *connector)
3905{
3906 struct intel_connector *intel_connector = to_intel_connector(connector);
3907 struct edid *edid;
3908
3909 edid = intel_connector->detect_edid;
3910 if (edid) {
3911 int ret = intel_connector_update_modes(connector, edid);
3912 if (ret)
3913 return ret;
3914 }
32f9d658 3915
f8779fda 3916 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 3917 if (is_edp(intel_attached_dp(connector)) &&
3918 intel_connector->panel.fixed_mode) {
f8779fda 3919 struct drm_display_mode *mode;
beb60608
CW		 3920
3921 mode = drm_mode_duplicate(connector->dev,
dd06f90e 3922 intel_connector->panel.fixed_mode);
f8779fda 3923 if (mode) {
32f9d658
ZW		 3924 drm_mode_probed_add(connector, mode);
3925 return 1;
3926 }
3927 }
beb60608 3928
32f9d658 3929 return 0;
a4fc5ed6
KP		 3930}
3931
1aad7ac0
CW		 3932static bool
3933intel_dp_detect_audio(struct drm_connector *connector)
3934{
1aad7ac0 3935 bool has_audio = false;
beb60608 3936 struct edid *edid;
1aad7ac0 3937
beb60608
CW		 3938 edid = to_intel_connector(connector)->detect_edid;
3939 if (edid)
1aad7ac0 3940 has_audio = drm_detect_monitor_audio(edid);
671dedd2 3941
1aad7ac0
CW		 3942 return has_audio;
3943}
3944
f684960e
CW		 3945static int
3946intel_dp_set_property(struct drm_connector *connector,
3947 struct drm_property *property,
3948 uint64_t val)
3949{
e953fd7b 3950 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3951 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3952 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3953 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3954 int ret;
3955
662595df 3956 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3957 if (ret)
3958 return ret;
3959
3f43c48d 3960 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3961 int i = val;
3962 bool has_audio;
3963
3964 if (i == intel_dp->force_audio)
f684960e
CW		 3965 return 0;
3966
1aad7ac0 3967 intel_dp->force_audio = i;
f684960e 3968
c3e5f67b 3969 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3970 has_audio = intel_dp_detect_audio(connector);
3971 else
c3e5f67b 3972 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3973
3974 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3975 return 0;
3976
1aad7ac0 3977 intel_dp->has_audio = has_audio;
f684960e
CW		 3978 goto done;
3979 }
3980
e953fd7b 3981 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3982 bool old_auto = intel_dp->color_range_auto;
3983 uint32_t old_range = intel_dp->color_range;
3984
55bc60db
VS		 3985 switch (val) {
3986 case INTEL_BROADCAST_RGB_AUTO:
3987 intel_dp->color_range_auto = true;
3988 break;
3989 case INTEL_BROADCAST_RGB_FULL:
3990 intel_dp->color_range_auto = false;
3991 intel_dp->color_range = 0;
3992 break;
3993 case INTEL_BROADCAST_RGB_LIMITED:
3994 intel_dp->color_range_auto = false;
3995 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3996 break;
3997 default:
3998 return -EINVAL;
3999 }
ae4edb80
DV		 4000
4001 if (old_auto == intel_dp->color_range_auto &&
4002 old_range == intel_dp->color_range)
4003 return 0;
4004
e953fd7b
CW		 4005 goto done;
4006 }
4007
53b41837
YN		 4008 if (is_edp(intel_dp) &&
4009 property == connector->dev->mode_config.scaling_mode_property) {
4010 if (val == DRM_MODE_SCALE_NONE) {
4011 DRM_DEBUG_KMS("no scaling not supported\n");
4012 return -EINVAL;
4013 }
4014
4015 if (intel_connector->panel.fitting_mode == val) {
4016 /* the eDP scaling property is not changed */
4017 return 0;
4018 }
4019 intel_connector->panel.fitting_mode = val;
4020
4021 goto done;
4022 }
4023
f684960e
CW		 4024 return -EINVAL;
4025
4026done:
c0c36b94
CW		 4027 if (intel_encoder->base.crtc)
4028 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4029
4030 return 0;
4031}
4032
a4fc5ed6 4033static void
73845adf 4034intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4035{
1d508706 4036 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4037
beb60608
CW		 4038 intel_dp_unset_edid(intel_attached_dp(connector));
4039
9cd300e0
JN		 4040 if (!IS_ERR_OR_NULL(intel_connector->edid))
4041 kfree(intel_connector->edid);
4042
acd8db10
PZ		 4043 /* Can't call is_edp() since the encoder may have been destroyed
4044 * already. */
4045 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4046 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4047
a4fc5ed6 4048 drm_connector_cleanup(connector);
55f78c43 4049 kfree(connector);
a4fc5ed6
KP		 4050}
4051
00c09d70 4052void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4053{
da63a9f2
PZ		 4054 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4055 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 4056 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 4057
4f71d0cb 4058 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4059 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4060 drm_encoder_cleanup(encoder);
bd943159
KP		 4061 if (is_edp(intel_dp)) {
4062 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4063 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4064 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4065 drm_modeset_unlock(&dev->mode_config.connection_mutex);
01527b31
CT		 4066 if (intel_dp->edp_notifier.notifier_call) {
4067 unregister_reboot_notifier(&intel_dp->edp_notifier);
4068 intel_dp->edp_notifier.notifier_call = NULL;
4069 }
bd943159 4070 }
da63a9f2 4071 kfree(intel_dig_port);
24d05927
DV		 4072}
4073
07f9cd0b
ID		 4074static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4075{
4076 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4077
4078 if (!is_edp(intel_dp))
4079 return;
4080
4081 edp_panel_vdd_off_sync(intel_dp);
4082}
4083
6d93c0c4
ID		 4084static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4085{
4086 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4087}
4088
a4fc5ed6 4089static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4090 .dpms = intel_connector_dpms,
a4fc5ed6 4091 .detect = intel_dp_detect,
beb60608 4092 .force = intel_dp_force,
a4fc5ed6 4093 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4094 .set_property = intel_dp_set_property,
73845adf 4095 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4096};
4097
4098static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4099 .get_modes = intel_dp_get_modes,
4100 .mode_valid = intel_dp_mode_valid,
df0e9248 4101 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4102};
4103
a4fc5ed6 4104static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4105 .reset = intel_dp_encoder_reset,
24d05927 4106 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4107};
4108
0e32b39c 4109void
21d40d37 4110intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4111{
0e32b39c 4112 return;
c8110e52 4113}
6207937d 4114
13cf5504
DA		 4115bool
4116intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4117{
4118 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4119 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4120 struct drm_device *dev = intel_dig_port->base.base.dev;
4121 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4122 enum intel_display_power_domain power_domain;
4123 bool ret = true;
4124
0e32b39c
DA		 4125 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4126 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4127
26fbb774
VS		 4128 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4129 port_name(intel_dig_port->port),
0e32b39c 4130 long_hpd ? "long" : "short");
13cf5504 4131
1c767b33
ID		 4132 power_domain = intel_display_port_power_domain(intel_encoder);
4133 intel_display_power_get(dev_priv, power_domain);
4134
0e32b39c
DA		 4135 if (long_hpd) {
4136 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4137 goto mst_fail;
4138
4139 if (!intel_dp_get_dpcd(intel_dp)) {
4140 goto mst_fail;
4141 }
4142
4143 intel_dp_probe_oui(intel_dp);
4144
4145 if (!intel_dp_probe_mst(intel_dp))
4146 goto mst_fail;
4147
4148 } else {
4149 if (intel_dp->is_mst) {
1c767b33 4150 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4151 goto mst_fail;
4152 }
4153
4154 if (!intel_dp->is_mst) {
4155 /*
4156 * we'll check the link status via the normal hot plug path later -
4157 * but for short hpds we should check it now
4158 */
5b215bcf 4159 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4160 intel_dp_check_link_status(intel_dp);
5b215bcf 4161 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4162 }
4163 }
1c767b33
ID		 4164 ret = false;
4165 goto put_power;
0e32b39c
DA		 4166mst_fail:
4167 /* if we were in MST mode, and device is not there get out of MST mode */
4168 if (intel_dp->is_mst) {
4169 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4170 intel_dp->is_mst = false;
4171 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4172 }
1c767b33
ID		 4173put_power:
4174 intel_display_power_put(dev_priv, power_domain);
4175
4176 return ret;
13cf5504
DA		 4177}
4178
e3421a18
ZW		 4179/* Return which DP Port should be selected for Transcoder DP control */
4180int
0206e353 4181intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4182{
4183 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4184 struct intel_encoder *intel_encoder;
4185 struct intel_dp *intel_dp;
e3421a18 4186
fa90ecef
PZ		 4187 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4188 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4189
fa90ecef
PZ		 4190 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4191 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4192 return intel_dp->output_reg;
e3421a18 4193 }
ea5b213a 4194
e3421a18
ZW		 4195 return -1;
4196}
4197
36e83a18 4198/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4199bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4200{
4201 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4202 union child_device_config *p_child;
36e83a18 4203 int i;
5d8a7752
VS		 4204 static const short port_mapping[] = {
4205 [PORT_B] = PORT_IDPB,
4206 [PORT_C] = PORT_IDPC,
4207 [PORT_D] = PORT_IDPD,
4208 };
36e83a18 4209
3b32a35b
VS		 4210 if (port == PORT_A)
4211 return true;
4212
41aa3448 4213 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4214 return false;
4215
41aa3448
RV		 4216 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4217 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4218
5d8a7752 4219 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4220 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4221 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4222 return true;
4223 }
4224 return false;
4225}
4226
0e32b39c 4227void
f684960e
CW		 4228intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4229{
53b41837
YN		 4230 struct intel_connector *intel_connector = to_intel_connector(connector);
4231
3f43c48d 4232 intel_attach_force_audio_property(connector);
e953fd7b 4233 intel_attach_broadcast_rgb_property(connector);
55bc60db 4234 intel_dp->color_range_auto = true;
53b41837
YN		 4235
4236 if (is_edp(intel_dp)) {
4237 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4238 drm_object_attach_property(
4239 &connector->base,
53b41837 4240 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4241 DRM_MODE_SCALE_ASPECT);
4242 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4243 }
f684960e
CW		 4244}
4245
dada1a9f
ID		 4246static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4247{
4248 intel_dp->last_power_cycle = jiffies;
4249 intel_dp->last_power_on = jiffies;
4250 intel_dp->last_backlight_off = jiffies;
4251}
4252
67a54566
DV		 4253static void
4254intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4255 struct intel_dp *intel_dp,
4256 struct edp_power_seq *out)
67a54566
DV		 4257{
4258 struct drm_i915_private *dev_priv = dev->dev_private;
4259 struct edp_power_seq cur, vbt, spec, final;
4260 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4261 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4262
4263 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4264 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4265 pp_on_reg = PCH_PP_ON_DELAYS;
4266 pp_off_reg = PCH_PP_OFF_DELAYS;
4267 pp_div_reg = PCH_PP_DIVISOR;
4268 } else {
bf13e81b
JN		 4269 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4270
4271 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4272 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4273 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4274 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4275 }
67a54566
DV		 4276
4277 /* Workaround: Need to write PP_CONTROL with the unlock key as
4278 * the very first thing. */
453c5420 4279 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4280 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4281
453c5420
JB		 4282 pp_on = I915_READ(pp_on_reg);
4283 pp_off = I915_READ(pp_off_reg);
4284 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4285
4286 /* Pull timing values out of registers */
4287 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4288 PANEL_POWER_UP_DELAY_SHIFT;
4289
4290 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4291 PANEL_LIGHT_ON_DELAY_SHIFT;
4292
4293 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4294 PANEL_LIGHT_OFF_DELAY_SHIFT;
4295
4296 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4297 PANEL_POWER_DOWN_DELAY_SHIFT;
4298
4299 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4300 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4301
4302 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4303 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4304
41aa3448 4305 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4306
4307 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4308 * our hw here, which are all in 100usec. */
4309 spec.t1_t3 = 210 * 10;
4310 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4311 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4312 spec.t10 = 500 * 10;
4313 /* This one is special and actually in units of 100ms, but zero
4314 * based in the hw (so we need to add 100 ms). But the sw vbt
4315 * table multiplies it with 1000 to make it in units of 100usec,
4316 * too. */
4317 spec.t11_t12 = (510 + 100) * 10;
4318
4319 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4320 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4321
4322 /* Use the max of the register settings and vbt. If both are
4323 * unset, fall back to the spec limits. */
4324#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4325 spec.field : \
4326 max(cur.field, vbt.field))
4327 assign_final(t1_t3);
4328 assign_final(t8);
4329 assign_final(t9);
4330 assign_final(t10);
4331 assign_final(t11_t12);
4332#undef assign_final
4333
4334#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4335 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4336 intel_dp->backlight_on_delay = get_delay(t8);
4337 intel_dp->backlight_off_delay = get_delay(t9);
4338 intel_dp->panel_power_down_delay = get_delay(t10);
4339 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4340#undef get_delay
4341
f30d26e4
JN		 4342 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4343 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4344 intel_dp->panel_power_cycle_delay);
4345
4346 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4347 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4348
4349 if (out)
4350 *out = final;
4351}
4352
4353static void
4354intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4355 struct intel_dp *intel_dp,
4356 struct edp_power_seq *seq)
4357{
4358 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4359 u32 pp_on, pp_off, pp_div, port_sel = 0;
4360 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4361 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4362 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420
JB		 4363
4364 if (HAS_PCH_SPLIT(dev)) {
4365 pp_on_reg = PCH_PP_ON_DELAYS;
4366 pp_off_reg = PCH_PP_OFF_DELAYS;
4367 pp_div_reg = PCH_PP_DIVISOR;
4368 } else {
bf13e81b
JN		 4369 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4370
4371 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4372 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4373 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4374 }
4375
b2f19d1a
PZ		 4376 /*
4377 * And finally store the new values in the power sequencer. The
4378 * backlight delays are set to 1 because we do manual waits on them. For
4379 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4380 * we'll end up waiting for the backlight off delay twice: once when we
4381 * do the manual sleep, and once when we disable the panel and wait for
4382 * the PP_STATUS bit to become zero.
4383 */
f30d26e4 4384 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4385 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4386 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4387 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4388 /* Compute the divisor for the pp clock, simply match the Bspec
4389 * formula. */
453c5420 4390 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4391 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4392 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4393
4394 /* Haswell doesn't have any port selection bits for the panel
4395 * power sequencer any more. */
bc7d38a4 4396 if (IS_VALLEYVIEW(dev)) {
ad933b56 4397 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4398 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4399 if (port == PORT_A)
a24c144c 4400 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4401 else
a24c144c 4402 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4403 }
4404
453c5420
JB		 4405 pp_on |= port_sel;
4406
4407 I915_WRITE(pp_on_reg, pp_on);
4408 I915_WRITE(pp_off_reg, pp_off);
4409 I915_WRITE(pp_div_reg, pp_div);
67a54566 4410
67a54566 4411 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4412 I915_READ(pp_on_reg),
4413 I915_READ(pp_off_reg),
4414 I915_READ(pp_div_reg));
f684960e
CW		 4415}
4416
439d7ac0
PB		 4417void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4418{
4419 struct drm_i915_private *dev_priv = dev->dev_private;
4420 struct intel_encoder *encoder;
4421 struct intel_dp *intel_dp = NULL;
4422 struct intel_crtc_config *config = NULL;
4423 struct intel_crtc *intel_crtc = NULL;
4424 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4425 u32 reg, val;
4426 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4427
4428 if (refresh_rate <= 0) {
4429 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4430 return;
4431 }
4432
4433 if (intel_connector == NULL) {
4434 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4435 return;
4436 }
4437
1fcc9d1c
DV		 4438 /*
4439 * FIXME: This needs proper synchronization with psr state. But really
4440 * hard to tell without seeing the user of this function of this code.
4441 * Check locking and ordering once that lands.
4442 */
439d7ac0
PB		 4443 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4444 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4445 return;
4446 }
4447
4448 encoder = intel_attached_encoder(&intel_connector->base);
4449 intel_dp = enc_to_intel_dp(&encoder->base);
4450 intel_crtc = encoder->new_crtc;
4451
4452 if (!intel_crtc) {
4453 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4454 return;
4455 }
4456
4457 config = &intel_crtc->config;
4458
4459 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4460 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4461 return;
4462 }
4463
4464 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4465 index = DRRS_LOW_RR;
4466
4467 if (index == intel_dp->drrs_state.refresh_rate_type) {
4468 DRM_DEBUG_KMS(
4469 "DRRS requested for previously set RR...ignoring\n");
4470 return;
4471 }
4472
4473 if (!intel_crtc->active) {
4474 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4475 return;
4476 }
4477
4478 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4479 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4480 val = I915_READ(reg);
4481 if (index > DRRS_HIGH_RR) {
4482 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4483 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4484 } else {
4485 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4486 }
4487 I915_WRITE(reg, val);
4488 }
4489
4490 /*
4491 * mutex taken to ensure that there is no race between differnt
4492 * drrs calls trying to update refresh rate. This scenario may occur
4493 * in future when idleness detection based DRRS in kernel and
4494 * possible calls from user space to set differnt RR are made.
4495 */
4496
4497 mutex_lock(&intel_dp->drrs_state.mutex);
4498
4499 intel_dp->drrs_state.refresh_rate_type = index;
4500
4501 mutex_unlock(&intel_dp->drrs_state.mutex);
4502
4503 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4504}
4505
4f9db5b5
PB		 4506static struct drm_display_mode *
4507intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4508 struct intel_connector *intel_connector,
4509 struct drm_display_mode *fixed_mode)
4510{
4511 struct drm_connector *connector = &intel_connector->base;
4512 struct intel_dp *intel_dp = &intel_dig_port->dp;
4513 struct drm_device *dev = intel_dig_port->base.base.dev;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 struct drm_display_mode *downclock_mode = NULL;
4516
4517 if (INTEL_INFO(dev)->gen <= 6) {
4518 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4519 return NULL;
4520 }
4521
4522 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4523 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4524 return NULL;
4525 }
4526
4527 downclock_mode = intel_find_panel_downclock
4528 (dev, fixed_mode, connector);
4529
4530 if (!downclock_mode) {
4079b8d1 4531 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4532 return NULL;
4533 }
4534
439d7ac0
PB		 4535 dev_priv->drrs.connector = intel_connector;
4536
4537 mutex_init(&intel_dp->drrs_state.mutex);
4538
4f9db5b5
PB		 4539 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4540
4541 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4542 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4543 return downclock_mode;
4544}
4545
aba86890
ID		 4546void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4547{
4548 struct drm_device *dev = intel_encoder->base.dev;
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550 struct intel_dp *intel_dp;
4551 enum intel_display_power_domain power_domain;
4552
4553 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4554 return;
4555
4556 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4557 if (!edp_have_panel_vdd(intel_dp))
4558 return;
4559 /*
4560 * The VDD bit needs a power domain reference, so if the bit is
4561 * already enabled when we boot or resume, grab this reference and
4562 * schedule a vdd off, so we don't hold on to the reference
4563 * indefinitely.
4564 */
4565 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4566 power_domain = intel_display_port_power_domain(intel_encoder);
4567 intel_display_power_get(dev_priv, power_domain);
4568
4569 edp_panel_vdd_schedule_off(intel_dp);
4570}
4571
ed92f0b2 4572static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4573 struct intel_connector *intel_connector,
4574 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4575{
4576 struct drm_connector *connector = &intel_connector->base;
4577 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4578 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4579 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4582 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4583 bool has_dpcd;
4584 struct drm_display_mode *scan;
4585 struct edid *edid;
4586
4f9db5b5
PB		 4587 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4588
ed92f0b2
PZ		 4589 if (!is_edp(intel_dp))
4590 return true;
4591
aba86890 4592 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4593
ed92f0b2 4594 /* Cache DPCD and EDID for edp. */
24f3e092 4595 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4596 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4597 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4598
4599 if (has_dpcd) {
4600 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4601 dev_priv->no_aux_handshake =
4602 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4603 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4604 } else {
4605 /* if this fails, presume the device is a ghost */
4606 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4607 return false;
4608 }
4609
4610 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4611 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4612
060c8778 4613 mutex_lock(&dev->mode_config.mutex);
0b99836f 4614 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4615 if (edid) {
4616 if (drm_add_edid_modes(connector, edid)) {
4617 drm_mode_connector_update_edid_property(connector,
4618 edid);
4619 drm_edid_to_eld(connector, edid);
4620 } else {
4621 kfree(edid);
4622 edid = ERR_PTR(-EINVAL);
4623 }
4624 } else {
4625 edid = ERR_PTR(-ENOENT);
4626 }
4627 intel_connector->edid = edid;
4628
4629 /* prefer fixed mode from EDID if available */
4630 list_for_each_entry(scan, &connector->probed_modes, head) {
4631 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4632 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4633 downclock_mode = intel_dp_drrs_init(
4634 intel_dig_port,
4635 intel_connector, fixed_mode);
ed92f0b2
PZ		 4636 break;
4637 }
4638 }
4639
4640 /* fallback to VBT if available for eDP */
4641 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4642 fixed_mode = drm_mode_duplicate(dev,
4643 dev_priv->vbt.lfp_lvds_vbt_mode);
4644 if (fixed_mode)
4645 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4646 }
060c8778 4647 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4648
01527b31
CT		 4649 if (IS_VALLEYVIEW(dev)) {
4650 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4651 register_reboot_notifier(&intel_dp->edp_notifier);
4652 }
4653
4f9db5b5 4654 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4655 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 4656 intel_panel_setup_backlight(connector);
4657
4658 return true;
4659}
4660
16c25533 4661bool
f0fec3f2
PZ		 4662intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4663 struct intel_connector *intel_connector)
a4fc5ed6 4664{
f0fec3f2
PZ		 4665 struct drm_connector *connector = &intel_connector->base;
4666 struct intel_dp *intel_dp = &intel_dig_port->dp;
4667 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4668 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4669 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4670 enum port port = intel_dig_port->port;
0095e6dc 4671 struct edp_power_seq power_seq = { 0 };
0b99836f 4672 int type;
a4fc5ed6 4673
ec5b01dd
DL		 4674 /* intel_dp vfuncs */
4675 if (IS_VALLEYVIEW(dev))
4676 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4677 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4678 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4679 else if (HAS_PCH_SPLIT(dev))
4680 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4681 else
4682 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4683
153b1100
DL		 4684 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4685
0767935e
DV		 4686 /* Preserve the current hw state. */
4687 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4688 intel_dp->attached_connector = intel_connector;
3d3dc149 4689
3b32a35b 4690 if (intel_dp_is_edp(dev, port))
b329530c 4691 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4692 else
4693 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4694
f7d24902
ID		 4695 /*
4696 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4697 * for DP the encoder type can be set by the caller to
4698 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4699 */
4700 if (type == DRM_MODE_CONNECTOR_eDP)
4701 intel_encoder->type = INTEL_OUTPUT_EDP;
4702
e7281eab
ID		 4703 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4704 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4705 port_name(port));
4706
b329530c 4707 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4708 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4709
a4fc5ed6
KP		 4710 connector->interlace_allowed = true;
4711 connector->doublescan_allowed = 0;
4712
f0fec3f2 4713 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4714 edp_panel_vdd_work);
a4fc5ed6 4715
df0e9248 4716 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4717 drm_connector_register(connector);
a4fc5ed6 4718
affa9354 4719 if (HAS_DDI(dev))
bcbc889b
PZ		 4720 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4721 else
4722 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4723 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4724
0b99836f 4725 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4726 switch (port) {
4727 case PORT_A:
1d843f9d 4728 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4729 break;
4730 case PORT_B:
1d843f9d 4731 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4732 break;
4733 case PORT_C:
1d843f9d 4734 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4735 break;
4736 case PORT_D:
1d843f9d 4737 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4738 break;
4739 default:
ad1c0b19 4740 BUG();
5eb08b69
ZW		 4741 }
4742
dada1a9f
ID		 4743 if (is_edp(intel_dp)) {
4744 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4745 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4746 }
0095e6dc 4747
9d1a1031 4748 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4749
0e32b39c
DA		 4750 /* init MST on ports that can support it */
4751 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4752 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4753 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4754 }
4755 }
4756
0095e6dc 4757 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4758 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4759 if (is_edp(intel_dp)) {
4760 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4761 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4762 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4763 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4764 }
34ea3d38 4765 drm_connector_unregister(connector);
b2f246a8 4766 drm_connector_cleanup(connector);
16c25533 4767 return false;
b2f246a8 4768 }
32f9d658 4769
f684960e
CW		 4770 intel_dp_add_properties(intel_dp, connector);
4771
a4fc5ed6
KP		 4772 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4773 * 0xd. Failure to do so will result in spurious interrupts being
4774 * generated on the port when a cable is not attached.
4775 */
4776 if (IS_G4X(dev) && !IS_GM45(dev)) {
4777 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4778 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4779 }
16c25533
PZ		 4780
4781 return true;
a4fc5ed6 4782}
f0fec3f2
PZ		 4783
4784void
4785intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4786{
13cf5504 4787 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4788 struct intel_digital_port *intel_dig_port;
4789 struct intel_encoder *intel_encoder;
4790 struct drm_encoder *encoder;
4791 struct intel_connector *intel_connector;
4792
b14c5679 4793 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4794 if (!intel_dig_port)
4795 return;
4796
b14c5679 4797 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4798 if (!intel_connector) {
4799 kfree(intel_dig_port);
4800 return;
4801 }
4802
4803 intel_encoder = &intel_dig_port->base;
4804 encoder = &intel_encoder->base;
4805
4806 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4807 DRM_MODE_ENCODER_TMDS);
4808
5bfe2ac0 4809 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4810 intel_encoder->disable = intel_disable_dp;
00c09d70 4811 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4812 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 4813 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 4814 if (IS_CHERRYVIEW(dev)) {
9197c88b 4815 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4816 intel_encoder->pre_enable = chv_pre_enable_dp;
4817 intel_encoder->enable = vlv_enable_dp;
580d3811 4818 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4819 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4820 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4821 intel_encoder->pre_enable = vlv_pre_enable_dp;
4822 intel_encoder->enable = vlv_enable_dp;
49277c31 4823 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4824 } else {
ecff4f3b
JN		 4825 intel_encoder->pre_enable = g4x_pre_enable_dp;
4826 intel_encoder->enable = g4x_enable_dp;
49277c31 4827 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4828 }
f0fec3f2 4829
174edf1f 4830 intel_dig_port->port = port;
f0fec3f2
PZ		 4831 intel_dig_port->dp.output_reg = output_reg;
4832
00c09d70 4833 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4834 if (IS_CHERRYVIEW(dev)) {
4835 if (port == PORT_D)
4836 intel_encoder->crtc_mask = 1 << 2;
4837 else
4838 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4839 } else {
4840 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4841 }
bc079e8b 4842 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4843 intel_encoder->hot_plug = intel_dp_hot_plug;
4844
13cf5504
DA		 4845 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4846 dev_priv->hpd_irq_port[port] = intel_dig_port;
4847
15b1d171
PZ		 4848 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4849 drm_encoder_cleanup(encoder);
4850 kfree(intel_dig_port);
b2f246a8 4851 kfree(intel_connector);
15b1d171 4852 }
f0fec3f2 4853}
0e32b39c
DA		 4854
4855void intel_dp_mst_suspend(struct drm_device *dev)
4856{
4857 struct drm_i915_private *dev_priv = dev->dev_private;
4858 int i;
4859
4860 /* disable MST */
4861 for (i = 0; i < I915_MAX_PORTS; i++) {
4862 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4863 if (!intel_dig_port)
4864 continue;
4865
4866 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4867 if (!intel_dig_port->dp.can_mst)
4868 continue;
4869 if (intel_dig_port->dp.is_mst)
4870 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4871 }
4872 }
4873}
4874
4875void intel_dp_mst_resume(struct drm_device *dev)
4876{
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 int i;
4879
4880 for (i = 0; i < I915_MAX_PORTS; i++) {
4881 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4882 if (!intel_dig_port)
4883 continue;
4884 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4885 int ret;
4886
4887 if (!intel_dig_port->dp.can_mst)
4888 continue;
4889
4890 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4891 if (ret != 0) {
4892 intel_dp_check_mst_status(&intel_dig_port->dp);
4893 }
4894 }
4895 }
4896}
Linux 6.x block layer and io_uring tree(s)