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drm/i915/skl: Add support for edp1.4 low vswing
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
9dd4ffdf
CML		 44struct dp_link_dpll {
45 int link_bw;
46 struct dpll dpll;
47};
48
49static const struct dp_link_dpll gen4_dpll[] = {
50 { DP_LINK_BW_1_62,
51 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
52 { DP_LINK_BW_2_7,
53 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
54};
55
56static const struct dp_link_dpll pch_dpll[] = {
57 { DP_LINK_BW_1_62,
58 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
59 { DP_LINK_BW_2_7,
60 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
61};
62
65ce4bf5
CML		 63static const struct dp_link_dpll vlv_dpll[] = {
64 { DP_LINK_BW_1_62,
58f6e632 65 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 66 { DP_LINK_BW_2_7,
67 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68};
69
ef9348c8
CML		 70/*
71 * CHV supports eDP 1.4 that have more link rates.
72 * Below only provides the fixed rate but exclude variable rate.
73 */
74static const struct dp_link_dpll chv_dpll[] = {
75 /*
76 * CHV requires to program fractional division for m2.
77 * m2 is stored in fixed point format using formula below
78 * (m2_int << 22) | m2_fraction
79 */
80 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
81 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
82 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
83 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
84 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
85 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
86};
87
cfcb0fc9
JB		 88/**
89 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
90 * @intel_dp: DP struct
91 *
92 * If a CPU or PCH DP output is attached to an eDP panel, this function
93 * will return true, and false otherwise.
94 */
95static bool is_edp(struct intel_dp *intel_dp)
96{
da63a9f2
PZ		 97 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
98
99 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 100}
101
68b4d824 102static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 103{
68b4d824
ID		 104 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
105
106 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 107}
108
df0e9248
CW		 109static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
110{
fa90ecef 111 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 112}
113
ea5b213a 114static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 115static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 116static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 117static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 118static void vlv_steal_power_sequencer(struct drm_device *dev,
119 enum pipe pipe);
a4fc5ed6 120
0e32b39c 121int
ea5b213a 122intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 123{
7183dc29 124 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 125 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 126
127 switch (max_link_bw) {
128 case DP_LINK_BW_1_62:
129 case DP_LINK_BW_2_7:
130 break;
d4eead50 131 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 132 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
133 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 134 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
135 max_link_bw = DP_LINK_BW_5_4;
136 else
137 max_link_bw = DP_LINK_BW_2_7;
d4eead50 138 break;
a4fc5ed6 139 default:
d4eead50
ID		 140 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
141 max_link_bw);
a4fc5ed6
KP		 142 max_link_bw = DP_LINK_BW_1_62;
143 break;
144 }
145 return max_link_bw;
146}
147
eeb6324d
PZ		 148static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
149{
150 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
151 struct drm_device *dev = intel_dig_port->base.base.dev;
152 u8 source_max, sink_max;
153
154 source_max = 4;
155 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
156 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
157 source_max = 2;
158
159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
c19de8eb 193static enum drm_mode_status
a4fc5ed6
KP		 194intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
196{
df0e9248 197 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 202
dd06f90e
JN		 203 if (is_edp(intel_dp) && fixed_mode) {
204 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 205 return MODE_PANEL;
206
dd06f90e 207 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 208 return MODE_PANEL;
03afc4a2
DV		 209
210 target_clock = fixed_mode->clock;
7de56f43
ZY		 211 }
212
36008365 213 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 214 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 215
216 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
217 mode_rate = intel_dp_link_required(target_clock, 18);
218
219 if (mode_rate > max_rate)
c4867936 220 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 221
222 if (mode->clock < 10000)
223 return MODE_CLOCK_LOW;
224
0af78a2b
DV		 225 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
226 return MODE_H_ILLEGAL;
227
a4fc5ed6
KP		 228 return MODE_OK;
229}
230
a4f1289e 231uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 232{
233 int i;
234 uint32_t v = 0;
235
236 if (src_bytes > 4)
237 src_bytes = 4;
238 for (i = 0; i < src_bytes; i++)
239 v |= ((uint32_t) src[i]) << ((3-i) * 8);
240 return v;
241}
242
c2af70e2 243static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 244{
245 int i;
246 if (dst_bytes > 4)
247 dst_bytes = 4;
248 for (i = 0; i < dst_bytes; i++)
249 dst[i] = src >> ((3-i) * 8);
250}
251
fb0f8fbf
KP		 252/* hrawclock is 1/4 the FSB frequency */
253static int
254intel_hrawclk(struct drm_device *dev)
255{
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 uint32_t clkcfg;
258
9473c8f4
VP		 259 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
260 if (IS_VALLEYVIEW(dev))
261 return 200;
262
fb0f8fbf
KP		 263 clkcfg = I915_READ(CLKCFG);
264 switch (clkcfg & CLKCFG_FSB_MASK) {
265 case CLKCFG_FSB_400:
266 return 100;
267 case CLKCFG_FSB_533:
268 return 133;
269 case CLKCFG_FSB_667:
270 return 166;
271 case CLKCFG_FSB_800:
272 return 200;
273 case CLKCFG_FSB_1067:
274 return 266;
275 case CLKCFG_FSB_1333:
276 return 333;
277 /* these two are just a guess; one of them might be right */
278 case CLKCFG_FSB_1600:
279 case CLKCFG_FSB_1600_ALT:
280 return 400;
281 default:
282 return 133;
283 }
284}
285
bf13e81b
JN		 286static void
287intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 288 struct intel_dp *intel_dp);
bf13e81b
JN		 289static void
290intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 291 struct intel_dp *intel_dp);
bf13e81b 292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
961a0db0
VS		 325static void
326vlv_power_sequencer_kick(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 332 bool pll_enabled;
961a0db0
VS		 333 uint32_t DP;
334
335 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
336 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
337 pipe_name(pipe), port_name(intel_dig_port->port)))
338 return;
339
340 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
341 pipe_name(pipe), port_name(intel_dig_port->port));
342
343 /* Preserve the BIOS-computed detected bit. This is
344 * supposed to be read-only.
345 */
346 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
347 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
348 DP |= DP_PORT_WIDTH(1);
349 DP |= DP_LINK_TRAIN_PAT_1;
350
351 if (IS_CHERRYVIEW(dev))
352 DP |= DP_PIPE_SELECT_CHV(pipe);
353 else if (pipe == PIPE_B)
354 DP |= DP_PIPEB_SELECT;
355
d288f65f
VS		 356 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
357
358 /*
359 * The DPLL for the pipe must be enabled for this to work.
360 * So enable temporarily it if it's not already enabled.
361 */
362 if (!pll_enabled)
363 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
364 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
365
961a0db0
VS		 366 /*
367 * Similar magic as in intel_dp_enable_port().
368 * We _must_ do this port enable + disable trick
369 * to make this power seqeuencer lock onto the port.
370 * Otherwise even VDD force bit won't work.
371 */
372 I915_WRITE(intel_dp->output_reg, DP);
373 POSTING_READ(intel_dp->output_reg);
374
375 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
376 POSTING_READ(intel_dp->output_reg);
377
378 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
379 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 380
381 if (!pll_enabled)
382 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 383}
384
bf13e81b
JN		 385static enum pipe
386vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
387{
388 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 389 struct drm_device *dev = intel_dig_port->base.base.dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 391 struct intel_encoder *encoder;
392 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 393 enum pipe pipe;
bf13e81b 394
e39b999a 395 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 396
a8c3344e
VS		 397 /* We should never land here with regular DP ports */
398 WARN_ON(!is_edp(intel_dp));
399
a4a5d2f8
VS		 400 if (intel_dp->pps_pipe != INVALID_PIPE)
401 return intel_dp->pps_pipe;
402
403 /*
404 * We don't have power sequencer currently.
405 * Pick one that's not used by other ports.
406 */
407 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
408 base.head) {
409 struct intel_dp *tmp;
410
411 if (encoder->type != INTEL_OUTPUT_EDP)
412 continue;
413
414 tmp = enc_to_intel_dp(&encoder->base);
415
416 if (tmp->pps_pipe != INVALID_PIPE)
417 pipes &= ~(1 << tmp->pps_pipe);
418 }
419
420 /*
421 * Didn't find one. This should not happen since there
422 * are two power sequencers and up to two eDP ports.
423 */
424 if (WARN_ON(pipes == 0))
a8c3344e
VS		 425 pipe = PIPE_A;
426 else
427 pipe = ffs(pipes) - 1;
a4a5d2f8 428
a8c3344e
VS		 429 vlv_steal_power_sequencer(dev, pipe);
430 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 431
432 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
433 pipe_name(intel_dp->pps_pipe),
434 port_name(intel_dig_port->port));
435
436 /* init power sequencer on this pipe and port */
36b5f425
VS		 437 intel_dp_init_panel_power_sequencer(dev, intel_dp);
438 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 439
961a0db0
VS		 440 /*
441 * Even vdd force doesn't work until we've made
442 * the power sequencer lock in on the port.
443 */
444 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 445
446 return intel_dp->pps_pipe;
447}
448
6491ab27
VS		 449typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
450 enum pipe pipe);
451
452static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
453 enum pipe pipe)
454{
455 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
456}
457
458static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
459 enum pipe pipe)
460{
461 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
462}
463
464static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
465 enum pipe pipe)
466{
467 return true;
468}
bf13e81b 469
a4a5d2f8 470static enum pipe
6491ab27
VS		 471vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
472 enum port port,
473 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 474{
475 enum pipe pipe;
bf13e81b 476
bf13e81b
JN		 477 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
478 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
479 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 480
481 if (port_sel != PANEL_PORT_SELECT_VLV(port))
482 continue;
483
6491ab27
VS		 484 if (!pipe_check(dev_priv, pipe))
485 continue;
486
a4a5d2f8 487 return pipe;
bf13e81b
JN		 488 }
489
a4a5d2f8
VS		 490 return INVALID_PIPE;
491}
492
493static void
494vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
495{
496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
497 struct drm_device *dev = intel_dig_port->base.base.dev;
498 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 499 enum port port = intel_dig_port->port;
500
501 lockdep_assert_held(&dev_priv->pps_mutex);
502
503 /* try to find a pipe with this port selected */
6491ab27
VS		 504 /* first pick one where the panel is on */
505 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
506 vlv_pipe_has_pp_on);
507 /* didn't find one? pick one where vdd is on */
508 if (intel_dp->pps_pipe == INVALID_PIPE)
509 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
510 vlv_pipe_has_vdd_on);
511 /* didn't find one? pick one with just the correct port */
512 if (intel_dp->pps_pipe == INVALID_PIPE)
513 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
514 vlv_pipe_any);
a4a5d2f8
VS		 515
516 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
517 if (intel_dp->pps_pipe == INVALID_PIPE) {
518 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
519 port_name(port));
520 return;
bf13e81b
JN		 521 }
522
a4a5d2f8
VS		 523 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
524 port_name(port), pipe_name(intel_dp->pps_pipe));
525
36b5f425
VS		 526 intel_dp_init_panel_power_sequencer(dev, intel_dp);
527 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 528}
529
773538e8
VS		 530void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
531{
532 struct drm_device *dev = dev_priv->dev;
533 struct intel_encoder *encoder;
534
535 if (WARN_ON(!IS_VALLEYVIEW(dev)))
536 return;
537
538 /*
539 * We can't grab pps_mutex here due to deadlock with power_domain
540 * mutex when power_domain functions are called while holding pps_mutex.
541 * That also means that in order to use pps_pipe the code needs to
542 * hold both a power domain reference and pps_mutex, and the power domain
543 * reference get/put must be done while _not_ holding pps_mutex.
544 * pps_{lock,unlock}() do these steps in the correct order, so one
545 * should use them always.
546 */
547
548 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
549 struct intel_dp *intel_dp;
550
551 if (encoder->type != INTEL_OUTPUT_EDP)
552 continue;
553
554 intel_dp = enc_to_intel_dp(&encoder->base);
555 intel_dp->pps_pipe = INVALID_PIPE;
556 }
bf13e81b
JN		 557}
558
559static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
560{
561 struct drm_device *dev = intel_dp_to_dev(intel_dp);
562
563 if (HAS_PCH_SPLIT(dev))
564 return PCH_PP_CONTROL;
565 else
566 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
567}
568
569static u32 _pp_stat_reg(struct intel_dp *intel_dp)
570{
571 struct drm_device *dev = intel_dp_to_dev(intel_dp);
572
573 if (HAS_PCH_SPLIT(dev))
574 return PCH_PP_STATUS;
575 else
576 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
577}
578
01527b31
CT		 579/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
580 This function only applicable when panel PM state is not to be tracked */
581static int edp_notify_handler(struct notifier_block *this, unsigned long code,
582 void *unused)
583{
584 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
585 edp_notifier);
586 struct drm_device *dev = intel_dp_to_dev(intel_dp);
587 struct drm_i915_private *dev_priv = dev->dev_private;
588 u32 pp_div;
589 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 590
591 if (!is_edp(intel_dp) || code != SYS_RESTART)
592 return 0;
593
773538e8 594 pps_lock(intel_dp);
e39b999a 595
01527b31 596 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 597 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
598
01527b31
CT		 599 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
600 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
601 pp_div = I915_READ(pp_div_reg);
602 pp_div &= PP_REFERENCE_DIVIDER_MASK;
603
604 /* 0x1F write to PP_DIV_REG sets max cycle delay */
605 I915_WRITE(pp_div_reg, pp_div | 0x1F);
606 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
607 msleep(intel_dp->panel_power_cycle_delay);
608 }
609
773538e8 610 pps_unlock(intel_dp);
e39b999a 611
01527b31
CT		 612 return 0;
613}
614
4be73780 615static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 616{
30add22d 617 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 618 struct drm_i915_private *dev_priv = dev->dev_private;
619
e39b999a
VS		 620 lockdep_assert_held(&dev_priv->pps_mutex);
621
9a42356b
VS		 622 if (IS_VALLEYVIEW(dev) &&
623 intel_dp->pps_pipe == INVALID_PIPE)
624 return false;
625
bf13e81b 626 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 627}
628
4be73780 629static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 630{
30add22d 631 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 632 struct drm_i915_private *dev_priv = dev->dev_private;
633
e39b999a
VS		 634 lockdep_assert_held(&dev_priv->pps_mutex);
635
9a42356b
VS		 636 if (IS_VALLEYVIEW(dev) &&
637 intel_dp->pps_pipe == INVALID_PIPE)
638 return false;
639
773538e8 640 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 641}
642
9b984dae
KP		 643static void
644intel_dp_check_edp(struct intel_dp *intel_dp)
645{
30add22d 646 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 647 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 648
9b984dae
KP		 649 if (!is_edp(intel_dp))
650 return;
453c5420 651
4be73780 652 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 653 WARN(1, "eDP powered off while attempting aux channel communication.\n");
654 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 655 I915_READ(_pp_stat_reg(intel_dp)),
656 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 657 }
658}
659
9ee32fea
DV		 660static uint32_t
661intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
662{
663 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
664 struct drm_device *dev = intel_dig_port->base.base.dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 666 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 667 uint32_t status;
668 bool done;
669
ef04f00d 670#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 671 if (has_aux_irq)
b18ac466 672 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 673 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 674 else
675 done = wait_for_atomic(C, 10) == 0;
676 if (!done)
677 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
678 has_aux_irq);
679#undef C
680
681 return status;
682}
683
ec5b01dd 684static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 685{
174edf1f
PZ		 686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 688
ec5b01dd
DL		 689 /*
690 * The clock divider is based off the hrawclk, and would like to run at
691 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 692 */
ec5b01dd
DL		 693 return index ? 0 : intel_hrawclk(dev) / 2;
694}
695
696static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
697{
698 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
699 struct drm_device *dev = intel_dig_port->base.base.dev;
700
701 if (index)
702 return 0;
703
704 if (intel_dig_port->port == PORT_A) {
705 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 706 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 707 else
b84a1cf8 708 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 709 } else {
710 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
711 }
712}
713
714static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
715{
716 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
717 struct drm_device *dev = intel_dig_port->base.base.dev;
718 struct drm_i915_private *dev_priv = dev->dev_private;
719
720 if (intel_dig_port->port == PORT_A) {
721 if (index)
722 return 0;
723 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 724 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
725 /* Workaround for non-ULT HSW */
bc86625a
CW		 726 switch (index) {
727 case 0: return 63;
728 case 1: return 72;
729 default: return 0;
730 }
ec5b01dd 731 } else {
bc86625a 732 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 733 }
b84a1cf8
RV		 734}
735
ec5b01dd
DL		 736static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
737{
738 return index ? 0 : 100;
739}
740
b6b5e383
DL		 741static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
742{
743 /*
744 * SKL doesn't need us to program the AUX clock divider (Hardware will
745 * derive the clock from CDCLK automatically). We still implement the
746 * get_aux_clock_divider vfunc to plug-in into the existing code.
747 */
748 return index ? 0 : 1;
749}
750
5ed12a19
DL		 751static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
752 bool has_aux_irq,
753 int send_bytes,
754 uint32_t aux_clock_divider)
755{
756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
757 struct drm_device *dev = intel_dig_port->base.base.dev;
758 uint32_t precharge, timeout;
759
760 if (IS_GEN6(dev))
761 precharge = 3;
762 else
763 precharge = 5;
764
765 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
766 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
767 else
768 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
769
770 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 771 DP_AUX_CH_CTL_DONE |
5ed12a19 772 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 773 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 774 timeout |
788d4433 775 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 776 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
777 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 778 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 779}
780
b9ca5fad
DL		 781static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
782 bool has_aux_irq,
783 int send_bytes,
784 uint32_t unused)
785{
786 return DP_AUX_CH_CTL_SEND_BUSY |
787 DP_AUX_CH_CTL_DONE |
788 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
789 DP_AUX_CH_CTL_TIME_OUT_ERROR |
790 DP_AUX_CH_CTL_TIME_OUT_1600us |
791 DP_AUX_CH_CTL_RECEIVE_ERROR |
792 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
793 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
794}
795
b84a1cf8
RV		 796static int
797intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 798 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 799 uint8_t *recv, int recv_size)
800{
801 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
802 struct drm_device *dev = intel_dig_port->base.base.dev;
803 struct drm_i915_private *dev_priv = dev->dev_private;
804 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
805 uint32_t ch_data = ch_ctl + 4;
bc86625a 806 uint32_t aux_clock_divider;
b84a1cf8
RV		 807 int i, ret, recv_bytes;
808 uint32_t status;
5ed12a19 809 int try, clock = 0;
4e6b788c 810 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 811 bool vdd;
812
773538e8 813 pps_lock(intel_dp);
e39b999a 814
72c3500a
VS		 815 /*
816 * We will be called with VDD already enabled for dpcd/edid/oui reads.
817 * In such cases we want to leave VDD enabled and it's up to upper layers
818 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
819 * ourselves.
820 */
1e0560e0 821 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 822
823 /* dp aux is extremely sensitive to irq latency, hence request the
824 * lowest possible wakeup latency and so prevent the cpu from going into
825 * deep sleep states.
826 */
827 pm_qos_update_request(&dev_priv->pm_qos, 0);
828
829 intel_dp_check_edp(intel_dp);
5eb08b69 830
c67a470b
PZ		 831 intel_aux_display_runtime_get(dev_priv);
832
11bee43e
JB		 833 /* Try to wait for any previous AUX channel activity */
834 for (try = 0; try < 3; try++) {
ef04f00d 835 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 836 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
837 break;
838 msleep(1);
839 }
840
841 if (try == 3) {
842 WARN(1, "dp_aux_ch not started status 0x%08x\n",
843 I915_READ(ch_ctl));
9ee32fea
DV		 844 ret = -EBUSY;
845 goto out;
4f7f7b7e
CW		 846 }
847
46a5ae9f
PZ		 848 /* Only 5 data registers! */
849 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
850 ret = -E2BIG;
851 goto out;
852 }
853
ec5b01dd 854 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 855 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
856 has_aux_irq,
857 send_bytes,
858 aux_clock_divider);
5ed12a19 859
bc86625a
CW		 860 /* Must try at least 3 times according to DP spec */
861 for (try = 0; try < 5; try++) {
862 /* Load the send data into the aux channel data registers */
863 for (i = 0; i < send_bytes; i += 4)
864 I915_WRITE(ch_data + i,
a4f1289e
RV		 865 intel_dp_pack_aux(send + i,
866 send_bytes - i));
bc86625a
CW		 867
868 /* Send the command and wait for it to complete */
5ed12a19 869 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 870
871 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
872
873 /* Clear done status and any errors */
874 I915_WRITE(ch_ctl,
875 status |
876 DP_AUX_CH_CTL_DONE |
877 DP_AUX_CH_CTL_TIME_OUT_ERROR |
878 DP_AUX_CH_CTL_RECEIVE_ERROR);
879
880 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
881 DP_AUX_CH_CTL_RECEIVE_ERROR))
882 continue;
883 if (status & DP_AUX_CH_CTL_DONE)
884 break;
885 }
4f7f7b7e 886 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 887 break;
888 }
889
a4fc5ed6 890 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 891 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 892 ret = -EBUSY;
893 goto out;
a4fc5ed6
KP		 894 }
895
896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
898 */
a5b3da54 899 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 901 ret = -EIO;
902 goto out;
a5b3da54 903 }
1ae8c0a5
KP		 904
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
a5b3da54 907 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 909 ret = -ETIMEDOUT;
910 goto out;
a4fc5ed6
KP		 911 }
912
913 /* Unload any bytes sent back from the other side */
914 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 916 if (recv_bytes > recv_size)
917 recv_bytes = recv_size;
0206e353 918
4f7f7b7e 919 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 920 intel_dp_unpack_aux(I915_READ(ch_data + i),
921 recv + i, recv_bytes - i);
a4fc5ed6 922
9ee32fea
DV		 923 ret = recv_bytes;
924out:
925 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 926 intel_aux_display_runtime_put(dev_priv);
9ee32fea 927
884f19e9
JN		 928 if (vdd)
929 edp_panel_vdd_off(intel_dp, false);
930
773538e8 931 pps_unlock(intel_dp);
e39b999a 932
9ee32fea 933 return ret;
a4fc5ed6
KP		 934}
935
a6c8aff0
JN		 936#define BARE_ADDRESS_SIZE 3
937#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 938static ssize_t
939intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 940{
9d1a1031
JN		 941 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
942 uint8_t txbuf[20], rxbuf[20];
943 size_t txsize, rxsize;
a4fc5ed6 944 int ret;
a4fc5ed6 945
9d1a1031
JN		 946 txbuf[0] = msg->request << 4;
947 txbuf[1] = msg->address >> 8;
948 txbuf[2] = msg->address & 0xff;
949 txbuf[3] = msg->size - 1;
46a5ae9f 950
9d1a1031
JN		 951 switch (msg->request & ~DP_AUX_I2C_MOT) {
952 case DP_AUX_NATIVE_WRITE:
953 case DP_AUX_I2C_WRITE:
a6c8aff0 954 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 955 rxsize = 1;
f51a44b9 956
9d1a1031
JN		 957 if (WARN_ON(txsize > 20))
958 return -E2BIG;
a4fc5ed6 959
9d1a1031 960 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 961
9d1a1031
JN		 962 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
963 if (ret > 0) {
964 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 965
9d1a1031
JN		 966 /* Return payload size. */
967 ret = msg->size;
968 }
969 break;
46a5ae9f 970
9d1a1031
JN		 971 case DP_AUX_NATIVE_READ:
972 case DP_AUX_I2C_READ:
a6c8aff0 973 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 974 rxsize = msg->size + 1;
a4fc5ed6 975
9d1a1031
JN		 976 if (WARN_ON(rxsize > 20))
977 return -E2BIG;
a4fc5ed6 978
9d1a1031
JN		 979 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
980 if (ret > 0) {
981 msg->reply = rxbuf[0] >> 4;
982 /*
983 * Assume happy day, and copy the data. The caller is
984 * expected to check msg->reply before touching it.
985 *
986 * Return payload size.
987 */
988 ret--;
989 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 990 }
9d1a1031
JN		 991 break;
992
993 default:
994 ret = -EINVAL;
995 break;
a4fc5ed6 996 }
f51a44b9 997
9d1a1031 998 return ret;
a4fc5ed6
KP		 999}
1000
9d1a1031
JN		 1001static void
1002intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1003{
1004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1005 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1006 enum port port = intel_dig_port->port;
0b99836f 1007 const char *name = NULL;
ab2c0672
DA		 1008 int ret;
1009
33ad6626
JN		 1010 switch (port) {
1011 case PORT_A:
1012 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1013 name = "DPDDC-A";
ab2c0672 1014 break;
33ad6626
JN		 1015 case PORT_B:
1016 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1017 name = "DPDDC-B";
ab2c0672 1018 break;
33ad6626
JN		 1019 case PORT_C:
1020 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1021 name = "DPDDC-C";
ab2c0672 1022 break;
33ad6626
JN		 1023 case PORT_D:
1024 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1025 name = "DPDDC-D";
33ad6626
JN		 1026 break;
1027 default:
1028 BUG();
ab2c0672
DA		 1029 }
1030
1b1aad75
DL		 1031 /*
1032 * The AUX_CTL register is usually DP_CTL + 0x10.
1033 *
1034 * On Haswell and Broadwell though:
1035 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1036 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1037 *
1038 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1039 */
1040 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1041 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1042
0b99836f 1043 intel_dp->aux.name = name;
9d1a1031
JN		 1044 intel_dp->aux.dev = dev->dev;
1045 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1046
0b99836f
JN		 1047 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1048 connector->base.kdev->kobj.name);
8316f337 1049
4f71d0cb 1050 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1051 if (ret < 0) {
4f71d0cb 1052 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1053 name, ret);
1054 return;
ab2c0672 1055 }
8a5e6aeb 1056
0b99836f
JN		 1057 ret = sysfs_create_link(&connector->base.kdev->kobj,
1058 &intel_dp->aux.ddc.dev.kobj,
1059 intel_dp->aux.ddc.dev.kobj.name);
1060 if (ret < 0) {
1061 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1062 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1063 }
a4fc5ed6
KP		 1064}
1065
80f65de3
ID		 1066static void
1067intel_dp_connector_unregister(struct intel_connector *intel_connector)
1068{
1069 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1070
0e32b39c
DA		 1071 if (!intel_connector->mst_port)
1072 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1073 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1074 intel_connector_unregister(intel_connector);
1075}
1076
5416d871 1077static void
5cec258b 1078skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
5416d871
DL		 1079{
1080 u32 ctrl1;
1081
1082 pipe_config->ddi_pll_sel = SKL_DPLL0;
1083 pipe_config->dpll_hw_state.cfgcr1 = 0;
1084 pipe_config->dpll_hw_state.cfgcr2 = 0;
1085
1086 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1087 switch (link_bw) {
1088 case DP_LINK_BW_1_62:
1089 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1090 SKL_DPLL0);
1091 break;
1092 case DP_LINK_BW_2_7:
1093 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1094 SKL_DPLL0);
1095 break;
1096 case DP_LINK_BW_5_4:
1097 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1098 SKL_DPLL0);
1099 break;
1100 }
1101 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1102}
1103
0e50338c 1104static void
5cec258b 1105hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c
DV		 1106{
1107 switch (link_bw) {
1108 case DP_LINK_BW_1_62:
1109 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1110 break;
1111 case DP_LINK_BW_2_7:
1112 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1113 break;
1114 case DP_LINK_BW_5_4:
1115 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1116 break;
1117 }
1118}
1119
c6bb3538
DV		 1120static void
1121intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1122 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1123{
1124 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1125 const struct dp_link_dpll *divisor = NULL;
1126 int i, count = 0;
c6bb3538
DV		 1127
1128 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1129 divisor = gen4_dpll;
1130 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1131 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1132 divisor = pch_dpll;
1133 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1134 } else if (IS_CHERRYVIEW(dev)) {
1135 divisor = chv_dpll;
1136 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1137 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1138 divisor = vlv_dpll;
1139 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1140 }
9dd4ffdf
CML		 1141
1142 if (divisor && count) {
1143 for (i = 0; i < count; i++) {
1144 if (link_bw == divisor[i].link_bw) {
1145 pipe_config->dpll = divisor[i].dpll;
1146 pipe_config->clock_set = true;
1147 break;
1148 }
1149 }
c6bb3538
DV		 1150 }
1151}
1152
00c09d70 1153bool
5bfe2ac0 1154intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1155 struct intel_crtc_state *pipe_config)
a4fc5ed6 1156{
5bfe2ac0 1157 struct drm_device *dev = encoder->base.dev;
36008365 1158 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1159 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1160 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1161 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1162 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1163 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1164 int lane_count, clock;
56071a20 1165 int min_lane_count = 1;
eeb6324d 1166 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1167 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1168 int min_clock = 0;
06ea66b6 1169 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1170 int bpp, mode_rate;
06ea66b6 1171 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1172 int link_avail, link_clock;
a4fc5ed6 1173
bc7d38a4 1174 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1175 pipe_config->has_pch_encoder = true;
1176
03afc4a2 1177 pipe_config->has_dp_encoder = true;
f769cd24 1178 pipe_config->has_drrs = false;
9ed109a7 1179 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1180
dd06f90e
JN		 1181 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1182 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1183 adjusted_mode);
2dd24552
JB		 1184 if (!HAS_PCH_SPLIT(dev))
1185 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1186 intel_connector->panel.fitting_mode);
1187 else
b074cec8
JB		 1188 intel_pch_panel_fitting(intel_crtc, pipe_config,
1189 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1190 }
1191
cb1793ce 1192 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1193 return false;
1194
083f9560
DV		 1195 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1196 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1197 max_lane_count, bws[max_clock],
1198 adjusted_mode->crtc_clock);
083f9560 1199
36008365
DV		 1200 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1201 * bpc in between. */
3e7ca985 1202 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1203 if (is_edp(intel_dp)) {
1204 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1205 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1206 dev_priv->vbt.edp_bpp);
1207 bpp = dev_priv->vbt.edp_bpp;
1208 }
1209
344c5bbc
JN		 1210 /*
1211 * Use the maximum clock and number of lanes the eDP panel
1212 * advertizes being capable of. The panels are generally
1213 * designed to support only a single clock and lane
1214 * configuration, and typically these values correspond to the
1215 * native resolution of the panel.
1216 */
1217 min_lane_count = max_lane_count;
1218 min_clock = max_clock;
7984211e 1219 }
657445fe 1220
36008365 1221 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1222 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1223 bpp);
36008365 1224
c6930992
DA		 1225 for (clock = min_clock; clock <= max_clock; clock++) {
1226 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1227 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1228 link_avail = intel_dp_max_data_rate(link_clock,
1229 lane_count);
1230
1231 if (mode_rate <= link_avail) {
1232 goto found;
1233 }
1234 }
1235 }
1236 }
c4867936 1237
36008365 1238 return false;
3685a8f3 1239
36008365 1240found:
55bc60db
VS		 1241 if (intel_dp->color_range_auto) {
1242 /*
1243 * See:
1244 * CEA-861-E - 5.1 Default Encoding Parameters
1245 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1246 */
18316c8c 1247 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1248 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1249 else
1250 intel_dp->color_range = 0;
1251 }
1252
3685a8f3 1253 if (intel_dp->color_range)
50f3b016 1254 pipe_config->limited_color_range = true;
a4fc5ed6 1255
36008365
DV		 1256 intel_dp->link_bw = bws[clock];
1257 intel_dp->lane_count = lane_count;
657445fe 1258 pipe_config->pipe_bpp = bpp;
ff9a6750 1259 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1260
36008365
DV		 1261 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1262 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1263 pipe_config->port_clock, bpp);
36008365
DV		 1264 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1265 mode_rate, link_avail);
a4fc5ed6 1266
03afc4a2 1267 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1268 adjusted_mode->crtc_clock,
1269 pipe_config->port_clock,
03afc4a2 1270 &pipe_config->dp_m_n);
9d1a455b 1271
439d7ac0 1272 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1273 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1274 pipe_config->has_drrs = true;
439d7ac0
PB		 1275 intel_link_compute_m_n(bpp, lane_count,
1276 intel_connector->panel.downclock_mode->clock,
1277 pipe_config->port_clock,
1278 &pipe_config->dp_m2_n2);
1279 }
1280
5416d871
DL		 1281 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1282 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1283 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1284 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1285 else
1286 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1287
03afc4a2 1288 return true;
a4fc5ed6
KP		 1289}
1290
7c62a164 1291static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1292{
7c62a164
DV		 1293 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1294 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1295 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 u32 dpa_ctl;
1298
6e3c9717
ACO		 1299 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1300 crtc->config->port_clock);
ea9b6006
DV		 1301 dpa_ctl = I915_READ(DP_A);
1302 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1303
6e3c9717 1304 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1305 /* For a long time we've carried around a ILK-DevA w/a for the
1306 * 160MHz clock. If we're really unlucky, it's still required.
1307 */
1308 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1309 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1310 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1311 } else {
1312 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1313 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1314 }
1ce17038 1315
ea9b6006
DV		 1316 I915_WRITE(DP_A, dpa_ctl);
1317
1318 POSTING_READ(DP_A);
1319 udelay(500);
1320}
1321
8ac33ed3 1322static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1323{
b934223d 1324 struct drm_device *dev = encoder->base.dev;
417e822d 1325 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1327 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1328 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1329 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1330
417e822d 1331 /*
1a2eb460 1332 * There are four kinds of DP registers:
417e822d
KP		 1333 *
1334 * IBX PCH
1a2eb460
KP		 1335 * SNB CPU
1336 * IVB CPU
417e822d
KP		 1337 * CPT PCH
1338 *
1339 * IBX PCH and CPU are the same for almost everything,
1340 * except that the CPU DP PLL is configured in this
1341 * register
1342 *
1343 * CPT PCH is quite different, having many bits moved
1344 * to the TRANS_DP_CTL register instead. That
1345 * configuration happens (oddly) in ironlake_pch_enable
1346 */
9c9e7927 1347
417e822d
KP		 1348 /* Preserve the BIOS-computed detected bit. This is
1349 * supposed to be read-only.
1350 */
1351 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1352
417e822d 1353 /* Handle DP bits in common between all three register formats */
417e822d 1354 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1355 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1356
6e3c9717 1357 if (crtc->config->has_audio)
ea5b213a 1358 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1359
417e822d 1360 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1361
bc7d38a4 1362 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1363 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1364 intel_dp->DP |= DP_SYNC_HS_HIGH;
1365 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1366 intel_dp->DP |= DP_SYNC_VS_HIGH;
1367 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1368
6aba5b6c 1369 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1370 intel_dp->DP |= DP_ENHANCED_FRAMING;
1371
7c62a164 1372 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1373 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1374 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1375 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1376
1377 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1378 intel_dp->DP |= DP_SYNC_HS_HIGH;
1379 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1380 intel_dp->DP |= DP_SYNC_VS_HIGH;
1381 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1382
6aba5b6c 1383 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1384 intel_dp->DP |= DP_ENHANCED_FRAMING;
1385
44f37d1f
CML		 1386 if (!IS_CHERRYVIEW(dev)) {
1387 if (crtc->pipe == 1)
1388 intel_dp->DP |= DP_PIPEB_SELECT;
1389 } else {
1390 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1391 }
417e822d
KP		 1392 } else {
1393 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1394 }
a4fc5ed6
KP		 1395}
1396
ffd6749d
PZ		 1397#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1398#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1399
1a5ef5b7
PZ		 1400#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1401#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1402
ffd6749d
PZ		 1403#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1404#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1405
4be73780 1406static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1407 u32 mask,
1408 u32 value)
bd943159 1409{
30add22d 1410 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1411 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1412 u32 pp_stat_reg, pp_ctrl_reg;
1413
e39b999a
VS		 1414 lockdep_assert_held(&dev_priv->pps_mutex);
1415
bf13e81b
JN		 1416 pp_stat_reg = _pp_stat_reg(intel_dp);
1417 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1418
99ea7127 1419 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1420 mask, value,
1421 I915_READ(pp_stat_reg),
1422 I915_READ(pp_ctrl_reg));
32ce697c 1423
453c5420 1424 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1425 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1426 I915_READ(pp_stat_reg),
1427 I915_READ(pp_ctrl_reg));
32ce697c 1428 }
54c136d4
CW		 1429
1430 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1431}
32ce697c 1432
4be73780 1433static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1434{
1435 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1436 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1437}
1438
4be73780 1439static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1440{
1441 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1442 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1443}
1444
4be73780 1445static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1446{
1447 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1448
1449 /* When we disable the VDD override bit last we have to do the manual
1450 * wait. */
1451 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1452 intel_dp->panel_power_cycle_delay);
1453
4be73780 1454 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1455}
1456
4be73780 1457static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1458{
1459 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1460 intel_dp->backlight_on_delay);
1461}
1462
4be73780 1463static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1464{
1465 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1466 intel_dp->backlight_off_delay);
1467}
99ea7127 1468
832dd3c1
KP		 1469/* Read the current pp_control value, unlocking the register if it
1470 * is locked
1471 */
1472
453c5420 1473static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1474{
453c5420
JB		 1475 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1477 u32 control;
832dd3c1 1478
e39b999a
VS		 1479 lockdep_assert_held(&dev_priv->pps_mutex);
1480
bf13e81b 1481 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1482 control &= ~PANEL_UNLOCK_MASK;
1483 control |= PANEL_UNLOCK_REGS;
1484 return control;
bd943159
KP		 1485}
1486
951468f3
VS		 1487/*
1488 * Must be paired with edp_panel_vdd_off().
1489 * Must hold pps_mutex around the whole on/off sequence.
1490 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1491 */
1e0560e0 1492static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1493{
30add22d 1494 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1496 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1497 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1498 enum intel_display_power_domain power_domain;
5d613501 1499 u32 pp;
453c5420 1500 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1501 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1502
e39b999a
VS		 1503 lockdep_assert_held(&dev_priv->pps_mutex);
1504
97af61f5 1505 if (!is_edp(intel_dp))
adddaaf4 1506 return false;
bd943159 1507
2c623c11 1508 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1509 intel_dp->want_panel_vdd = true;
99ea7127 1510
4be73780 1511 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1512 return need_to_disable;
b0665d57 1513
4e6e1a54
ID		 1514 power_domain = intel_display_port_power_domain(intel_encoder);
1515 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1516
3936fcf4
VS		 1517 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1518 port_name(intel_dig_port->port));
bd943159 1519
4be73780
DV		 1520 if (!edp_have_panel_power(intel_dp))
1521 wait_panel_power_cycle(intel_dp);
99ea7127 1522
453c5420 1523 pp = ironlake_get_pp_control(intel_dp);
5d613501 1524 pp |= EDP_FORCE_VDD;
ebf33b18 1525
bf13e81b
JN		 1526 pp_stat_reg = _pp_stat_reg(intel_dp);
1527 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1528
1529 I915_WRITE(pp_ctrl_reg, pp);
1530 POSTING_READ(pp_ctrl_reg);
1531 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1532 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1533 /*
1534 * If the panel wasn't on, delay before accessing aux channel
1535 */
4be73780 1536 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1537 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1538 port_name(intel_dig_port->port));
f01eca2e 1539 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1540 }
adddaaf4
JN		 1541
1542 return need_to_disable;
1543}
1544
951468f3
VS		 1545/*
1546 * Must be paired with intel_edp_panel_vdd_off() or
1547 * intel_edp_panel_off().
1548 * Nested calls to these functions are not allowed since
1549 * we drop the lock. Caller must use some higher level
1550 * locking to prevent nested calls from other threads.
1551 */
b80d6c78 1552void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1553{
c695b6b6 1554 bool vdd;
adddaaf4 1555
c695b6b6
VS		 1556 if (!is_edp(intel_dp))
1557 return;
1558
773538e8 1559 pps_lock(intel_dp);
c695b6b6 1560 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1561 pps_unlock(intel_dp);
c695b6b6 1562
e2c719b7 1563 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1564 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1565}
1566
4be73780 1567static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1568{
30add22d 1569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1570 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1571 struct intel_digital_port *intel_dig_port =
1572 dp_to_dig_port(intel_dp);
1573 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1574 enum intel_display_power_domain power_domain;
5d613501 1575 u32 pp;
453c5420 1576 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1577
e39b999a 1578 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1579
15e899a0 1580 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1581
15e899a0 1582 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1583 return;
b0665d57 1584
3936fcf4
VS		 1585 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1586 port_name(intel_dig_port->port));
bd943159 1587
be2c9196
VS		 1588 pp = ironlake_get_pp_control(intel_dp);
1589 pp &= ~EDP_FORCE_VDD;
453c5420 1590
be2c9196
VS		 1591 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1592 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1593
be2c9196
VS		 1594 I915_WRITE(pp_ctrl_reg, pp);
1595 POSTING_READ(pp_ctrl_reg);
90791a5c 1596
be2c9196
VS		 1597 /* Make sure sequencer is idle before allowing subsequent activity */
1598 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1599 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1600
be2c9196
VS		 1601 if ((pp & POWER_TARGET_ON) == 0)
1602 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1603
be2c9196
VS		 1604 power_domain = intel_display_port_power_domain(intel_encoder);
1605 intel_display_power_put(dev_priv, power_domain);
bd943159 1606}
5d613501 1607
4be73780 1608static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1609{
1610 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1611 struct intel_dp, panel_vdd_work);
bd943159 1612
773538e8 1613 pps_lock(intel_dp);
15e899a0
VS		 1614 if (!intel_dp->want_panel_vdd)
1615 edp_panel_vdd_off_sync(intel_dp);
773538e8 1616 pps_unlock(intel_dp);
bd943159
KP		 1617}
1618
aba86890
ID		 1619static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1620{
1621 unsigned long delay;
1622
1623 /*
1624 * Queue the timer to fire a long time from now (relative to the power
1625 * down delay) to keep the panel power up across a sequence of
1626 * operations.
1627 */
1628 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1629 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1630}
1631
951468f3
VS		 1632/*
1633 * Must be paired with edp_panel_vdd_on().
1634 * Must hold pps_mutex around the whole on/off sequence.
1635 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1636 */
4be73780 1637static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1638{
e39b999a
VS		 1639 struct drm_i915_private *dev_priv =
1640 intel_dp_to_dev(intel_dp)->dev_private;
1641
1642 lockdep_assert_held(&dev_priv->pps_mutex);
1643
97af61f5
KP		 1644 if (!is_edp(intel_dp))
1645 return;
5d613501 1646
e2c719b7 1647 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1648 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1649
bd943159
KP		 1650 intel_dp->want_panel_vdd = false;
1651
aba86890 1652 if (sync)
4be73780 1653 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1654 else
1655 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1656}
1657
9f0fb5be 1658static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1659{
30add22d 1660 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1661 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1662 u32 pp;
453c5420 1663 u32 pp_ctrl_reg;
9934c132 1664
9f0fb5be
VS		 1665 lockdep_assert_held(&dev_priv->pps_mutex);
1666
97af61f5 1667 if (!is_edp(intel_dp))
bd943159 1668 return;
99ea7127 1669
3936fcf4
VS		 1670 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1671 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1672
e7a89ace
VS		 1673 if (WARN(edp_have_panel_power(intel_dp),
1674 "eDP port %c panel power already on\n",
1675 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1676 return;
9934c132 1677
4be73780 1678 wait_panel_power_cycle(intel_dp);
37c6c9b0 1679
bf13e81b 1680 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1681 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1682 if (IS_GEN5(dev)) {
1683 /* ILK workaround: disable reset around power sequence */
1684 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1685 I915_WRITE(pp_ctrl_reg, pp);
1686 POSTING_READ(pp_ctrl_reg);
05ce1a49 1687 }
37c6c9b0 1688
1c0ae80a 1689 pp |= POWER_TARGET_ON;
99ea7127
KP		 1690 if (!IS_GEN5(dev))
1691 pp |= PANEL_POWER_RESET;
1692
453c5420
JB		 1693 I915_WRITE(pp_ctrl_reg, pp);
1694 POSTING_READ(pp_ctrl_reg);
9934c132 1695
4be73780 1696 wait_panel_on(intel_dp);
dce56b3c 1697 intel_dp->last_power_on = jiffies;
9934c132 1698
05ce1a49
KP		 1699 if (IS_GEN5(dev)) {
1700 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1701 I915_WRITE(pp_ctrl_reg, pp);
1702 POSTING_READ(pp_ctrl_reg);
05ce1a49 1703 }
9f0fb5be 1704}
e39b999a 1705
9f0fb5be
VS		 1706void intel_edp_panel_on(struct intel_dp *intel_dp)
1707{
1708 if (!is_edp(intel_dp))
1709 return;
1710
1711 pps_lock(intel_dp);
1712 edp_panel_on(intel_dp);
773538e8 1713 pps_unlock(intel_dp);
9934c132
JB		 1714}
1715
9f0fb5be
VS		 1716
1717static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1718{
4e6e1a54
ID		 1719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1720 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1721 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1722 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1723 enum intel_display_power_domain power_domain;
99ea7127 1724 u32 pp;
453c5420 1725 u32 pp_ctrl_reg;
9934c132 1726
9f0fb5be
VS		 1727 lockdep_assert_held(&dev_priv->pps_mutex);
1728
97af61f5
KP		 1729 if (!is_edp(intel_dp))
1730 return;
37c6c9b0 1731
3936fcf4
VS		 1732 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1733 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1734
3936fcf4
VS		 1735 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1736 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1737
453c5420 1738 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1739 /* We need to switch off panel power _and_ force vdd, for otherwise some
1740 * panels get very unhappy and cease to work. */
b3064154
PJ		 1741 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1742 EDP_BLC_ENABLE);
453c5420 1743
bf13e81b 1744 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1745
849e39f5
PZ		 1746 intel_dp->want_panel_vdd = false;
1747
453c5420
JB		 1748 I915_WRITE(pp_ctrl_reg, pp);
1749 POSTING_READ(pp_ctrl_reg);
9934c132 1750
dce56b3c 1751 intel_dp->last_power_cycle = jiffies;
4be73780 1752 wait_panel_off(intel_dp);
849e39f5
PZ		 1753
1754 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1755 power_domain = intel_display_port_power_domain(intel_encoder);
1756 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1757}
e39b999a 1758
9f0fb5be
VS		 1759void intel_edp_panel_off(struct intel_dp *intel_dp)
1760{
1761 if (!is_edp(intel_dp))
1762 return;
e39b999a 1763
9f0fb5be
VS		 1764 pps_lock(intel_dp);
1765 edp_panel_off(intel_dp);
773538e8 1766 pps_unlock(intel_dp);
9934c132
JB		 1767}
1768
1250d107
JN		 1769/* Enable backlight in the panel power control. */
1770static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1771{
da63a9f2
PZ		 1772 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1773 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 u32 pp;
453c5420 1776 u32 pp_ctrl_reg;
32f9d658 1777
01cb9ea6
JB		 1778 /*
1779 * If we enable the backlight right away following a panel power
1780 * on, we may see slight flicker as the panel syncs with the eDP
1781 * link. So delay a bit to make sure the image is solid before
1782 * allowing it to appear.
1783 */
4be73780 1784 wait_backlight_on(intel_dp);
e39b999a 1785
773538e8 1786 pps_lock(intel_dp);
e39b999a 1787
453c5420 1788 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1789 pp |= EDP_BLC_ENABLE;
453c5420 1790
bf13e81b 1791 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1792
1793 I915_WRITE(pp_ctrl_reg, pp);
1794 POSTING_READ(pp_ctrl_reg);
e39b999a 1795
773538e8 1796 pps_unlock(intel_dp);
32f9d658
ZW		 1797}
1798
1250d107
JN		 1799/* Enable backlight PWM and backlight PP control. */
1800void intel_edp_backlight_on(struct intel_dp *intel_dp)
1801{
1802 if (!is_edp(intel_dp))
1803 return;
1804
1805 DRM_DEBUG_KMS("\n");
1806
1807 intel_panel_enable_backlight(intel_dp->attached_connector);
1808 _intel_edp_backlight_on(intel_dp);
1809}
1810
1811/* Disable backlight in the panel power control. */
1812static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1813{
30add22d 1814 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1815 struct drm_i915_private *dev_priv = dev->dev_private;
1816 u32 pp;
453c5420 1817 u32 pp_ctrl_reg;
32f9d658 1818
f01eca2e
KP		 1819 if (!is_edp(intel_dp))
1820 return;
1821
773538e8 1822 pps_lock(intel_dp);
e39b999a 1823
453c5420 1824 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1825 pp &= ~EDP_BLC_ENABLE;
453c5420 1826
bf13e81b 1827 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1828
1829 I915_WRITE(pp_ctrl_reg, pp);
1830 POSTING_READ(pp_ctrl_reg);
f7d2323c 1831
773538e8 1832 pps_unlock(intel_dp);
e39b999a
VS		 1833
1834 intel_dp->last_backlight_off = jiffies;
f7d2323c 1835 edp_wait_backlight_off(intel_dp);
1250d107 1836}
f7d2323c 1837
1250d107
JN		 1838/* Disable backlight PP control and backlight PWM. */
1839void intel_edp_backlight_off(struct intel_dp *intel_dp)
1840{
1841 if (!is_edp(intel_dp))
1842 return;
1843
1844 DRM_DEBUG_KMS("\n");
f7d2323c 1845
1250d107 1846 _intel_edp_backlight_off(intel_dp);
f7d2323c 1847 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1848}
a4fc5ed6 1849
73580fb7
JN		 1850/*
1851 * Hook for controlling the panel power control backlight through the bl_power
1852 * sysfs attribute. Take care to handle multiple calls.
1853 */
1854static void intel_edp_backlight_power(struct intel_connector *connector,
1855 bool enable)
1856{
1857 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1858 bool is_enabled;
1859
773538e8 1860 pps_lock(intel_dp);
e39b999a 1861 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1862 pps_unlock(intel_dp);
73580fb7
JN		 1863
1864 if (is_enabled == enable)
1865 return;
1866
23ba9373
JN		 1867 DRM_DEBUG_KMS("panel power control backlight %s\n",
1868 enable ? "enable" : "disable");
73580fb7
JN		 1869
1870 if (enable)
1871 _intel_edp_backlight_on(intel_dp);
1872 else
1873 _intel_edp_backlight_off(intel_dp);
1874}
1875
2bd2ad64 1876static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1877{
da63a9f2
PZ		 1878 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1879 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1880 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 u32 dpa_ctl;
1883
2bd2ad64
DV		 1884 assert_pipe_disabled(dev_priv,
1885 to_intel_crtc(crtc)->pipe);
1886
d240f20f
JB		 1887 DRM_DEBUG_KMS("\n");
1888 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1889 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1890 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1891
1892 /* We don't adjust intel_dp->DP while tearing down the link, to
1893 * facilitate link retraining (e.g. after hotplug). Hence clear all
1894 * enable bits here to ensure that we don't enable too much. */
1895 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1896 intel_dp->DP |= DP_PLL_ENABLE;
1897 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1898 POSTING_READ(DP_A);
1899 udelay(200);
d240f20f
JB		 1900}
1901
2bd2ad64 1902static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1903{
da63a9f2
PZ		 1904 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1905 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1906 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1907 struct drm_i915_private *dev_priv = dev->dev_private;
1908 u32 dpa_ctl;
1909
2bd2ad64
DV		 1910 assert_pipe_disabled(dev_priv,
1911 to_intel_crtc(crtc)->pipe);
1912
d240f20f 1913 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1914 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1915 "dp pll off, should be on\n");
1916 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1917
1918 /* We can't rely on the value tracked for the DP register in
1919 * intel_dp->DP because link_down must not change that (otherwise link
1920 * re-training will fail. */
298b0b39 1921 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1922 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1923 POSTING_READ(DP_A);
d240f20f
JB		 1924 udelay(200);
1925}
1926
c7ad3810 1927/* If the sink supports it, try to set the power state appropriately */
c19b0669 1928void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1929{
1930 int ret, i;
1931
1932 /* Should have a valid DPCD by this point */
1933 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1934 return;
1935
1936 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1937 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1938 DP_SET_POWER_D3);
c7ad3810
JB		 1939 } else {
1940 /*
1941 * When turning on, we need to retry for 1ms to give the sink
1942 * time to wake up.
1943 */
1944 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1945 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1946 DP_SET_POWER_D0);
c7ad3810
JB		 1947 if (ret == 1)
1948 break;
1949 msleep(1);
1950 }
1951 }
f9cac721
JN		 1952
1953 if (ret != 1)
1954 DRM_DEBUG_KMS("failed to %s sink power state\n",
1955 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1956}
1957
19d8fe15
DV		 1958static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1959 enum pipe *pipe)
d240f20f 1960{
19d8fe15 1961 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1962 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1963 struct drm_device *dev = encoder->base.dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1965 enum intel_display_power_domain power_domain;
1966 u32 tmp;
1967
1968 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1969 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1970 return false;
1971
1972 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1973
1974 if (!(tmp & DP_PORT_EN))
1975 return false;
1976
bc7d38a4 1977 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1978 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1979 } else if (IS_CHERRYVIEW(dev)) {
1980 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1981 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1982 *pipe = PORT_TO_PIPE(tmp);
1983 } else {
1984 u32 trans_sel;
1985 u32 trans_dp;
1986 int i;
1987
1988 switch (intel_dp->output_reg) {
1989 case PCH_DP_B:
1990 trans_sel = TRANS_DP_PORT_SEL_B;
1991 break;
1992 case PCH_DP_C:
1993 trans_sel = TRANS_DP_PORT_SEL_C;
1994 break;
1995 case PCH_DP_D:
1996 trans_sel = TRANS_DP_PORT_SEL_D;
1997 break;
1998 default:
1999 return true;
2000 }
2001
055e393f 2002 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2003 trans_dp = I915_READ(TRANS_DP_CTL(i));
2004 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2005 *pipe = i;
2006 return true;
2007 }
2008 }
19d8fe15 2009
4a0833ec
DV		 2010 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2011 intel_dp->output_reg);
2012 }
d240f20f 2013
19d8fe15
DV		 2014 return true;
2015}
d240f20f 2016
045ac3b5 2017static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2018 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2019{
2020 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2021 u32 tmp, flags = 0;
63000ef6
XZ		 2022 struct drm_device *dev = encoder->base.dev;
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 enum port port = dp_to_dig_port(intel_dp)->port;
2025 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2026 int dotclock;
045ac3b5 2027
9ed109a7
DV		 2028 tmp = I915_READ(intel_dp->output_reg);
2029 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2030 pipe_config->has_audio = true;
2031
63000ef6 2032 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2033 if (tmp & DP_SYNC_HS_HIGH)
2034 flags |= DRM_MODE_FLAG_PHSYNC;
2035 else
2036 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2037
63000ef6
XZ		 2038 if (tmp & DP_SYNC_VS_HIGH)
2039 flags |= DRM_MODE_FLAG_PVSYNC;
2040 else
2041 flags |= DRM_MODE_FLAG_NVSYNC;
2042 } else {
2043 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2044 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2045 flags |= DRM_MODE_FLAG_PHSYNC;
2046 else
2047 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2048
63000ef6
XZ		 2049 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2050 flags |= DRM_MODE_FLAG_PVSYNC;
2051 else
2052 flags |= DRM_MODE_FLAG_NVSYNC;
2053 }
045ac3b5 2054
2d112de7 2055 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2056
8c875fca
VS		 2057 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2058 tmp & DP_COLOR_RANGE_16_235)
2059 pipe_config->limited_color_range = true;
2060
eb14cb74
VS		 2061 pipe_config->has_dp_encoder = true;
2062
2063 intel_dp_get_m_n(crtc, pipe_config);
2064
18442d08 2065 if (port == PORT_A) {
f1f644dc
JB		 2066 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2067 pipe_config->port_clock = 162000;
2068 else
2069 pipe_config->port_clock = 270000;
2070 }
18442d08
VS		 2071
2072 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2073 &pipe_config->dp_m_n);
2074
2075 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2076 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2077
2d112de7 2078 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2079
c6cd2ee2
JN		 2080 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2081 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2082 /*
2083 * This is a big fat ugly hack.
2084 *
2085 * Some machines in UEFI boot mode provide us a VBT that has 18
2086 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2087 * unknown we fail to light up. Yet the same BIOS boots up with
2088 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2089 * max, not what it tells us to use.
2090 *
2091 * Note: This will still be broken if the eDP panel is not lit
2092 * up by the BIOS, and thus we can't get the mode at module
2093 * load.
2094 */
2095 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2096 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2097 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2098 }
045ac3b5
JB		 2099}
2100
e8cb4558 2101static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2102{
e8cb4558 2103 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2104 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2105 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2106
6e3c9717 2107 if (crtc->config->has_audio)
495a5bb8 2108 intel_audio_codec_disable(encoder);
6cb49835 2109
b32c6f48
RV		 2110 if (HAS_PSR(dev) && !HAS_DDI(dev))
2111 intel_psr_disable(intel_dp);
2112
6cb49835
DV		 2113 /* Make sure the panel is off before trying to change the mode. But also
2114 * ensure that we have vdd while we switch off the panel. */
24f3e092 2115 intel_edp_panel_vdd_on(intel_dp);
4be73780 2116 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2117 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2118 intel_edp_panel_off(intel_dp);
3739850b 2119
08aff3fe
VS		 2120 /* disable the port before the pipe on g4x */
2121 if (INTEL_INFO(dev)->gen < 5)
3739850b 2122 intel_dp_link_down(intel_dp);
d240f20f
JB		 2123}
2124
08aff3fe 2125static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2126{
2bd2ad64 2127 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2128 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2129
49277c31 2130 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2131 if (port == PORT_A)
2132 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2133}
2134
2135static void vlv_post_disable_dp(struct intel_encoder *encoder)
2136{
2137 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2138
2139 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2140}
2141
580d3811
VS		 2142static void chv_post_disable_dp(struct intel_encoder *encoder)
2143{
2144 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2145 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2146 struct drm_device *dev = encoder->base.dev;
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2148 struct intel_crtc *intel_crtc =
2149 to_intel_crtc(encoder->base.crtc);
2150 enum dpio_channel ch = vlv_dport_to_channel(dport);
2151 enum pipe pipe = intel_crtc->pipe;
2152 u32 val;
2153
2154 intel_dp_link_down(intel_dp);
2155
2156 mutex_lock(&dev_priv->dpio_lock);
2157
2158 /* Propagate soft reset to data lane reset */
97fd4d5c 2159 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2160 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2161 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2162
97fd4d5c
VS		 2163 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2164 val |= CHV_PCS_REQ_SOFTRESET_EN;
2165 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2166
2167 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2168 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2169 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2170
2171 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2172 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2173 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2174
2175 mutex_unlock(&dev_priv->dpio_lock);
2176}
2177
7b13b58a
VS		 2178static void
2179_intel_dp_set_link_train(struct intel_dp *intel_dp,
2180 uint32_t *DP,
2181 uint8_t dp_train_pat)
2182{
2183 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2184 struct drm_device *dev = intel_dig_port->base.base.dev;
2185 struct drm_i915_private *dev_priv = dev->dev_private;
2186 enum port port = intel_dig_port->port;
2187
2188 if (HAS_DDI(dev)) {
2189 uint32_t temp = I915_READ(DP_TP_CTL(port));
2190
2191 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2192 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2193 else
2194 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2195
2196 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2197 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2198 case DP_TRAINING_PATTERN_DISABLE:
2199 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2200
2201 break;
2202 case DP_TRAINING_PATTERN_1:
2203 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2204 break;
2205 case DP_TRAINING_PATTERN_2:
2206 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2207 break;
2208 case DP_TRAINING_PATTERN_3:
2209 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2210 break;
2211 }
2212 I915_WRITE(DP_TP_CTL(port), temp);
2213
2214 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2215 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2216
2217 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2218 case DP_TRAINING_PATTERN_DISABLE:
2219 *DP |= DP_LINK_TRAIN_OFF_CPT;
2220 break;
2221 case DP_TRAINING_PATTERN_1:
2222 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2223 break;
2224 case DP_TRAINING_PATTERN_2:
2225 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2226 break;
2227 case DP_TRAINING_PATTERN_3:
2228 DRM_ERROR("DP training pattern 3 not supported\n");
2229 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2230 break;
2231 }
2232
2233 } else {
2234 if (IS_CHERRYVIEW(dev))
2235 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2236 else
2237 *DP &= ~DP_LINK_TRAIN_MASK;
2238
2239 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2240 case DP_TRAINING_PATTERN_DISABLE:
2241 *DP |= DP_LINK_TRAIN_OFF;
2242 break;
2243 case DP_TRAINING_PATTERN_1:
2244 *DP |= DP_LINK_TRAIN_PAT_1;
2245 break;
2246 case DP_TRAINING_PATTERN_2:
2247 *DP |= DP_LINK_TRAIN_PAT_2;
2248 break;
2249 case DP_TRAINING_PATTERN_3:
2250 if (IS_CHERRYVIEW(dev)) {
2251 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2252 } else {
2253 DRM_ERROR("DP training pattern 3 not supported\n");
2254 *DP |= DP_LINK_TRAIN_PAT_2;
2255 }
2256 break;
2257 }
2258 }
2259}
2260
2261static void intel_dp_enable_port(struct intel_dp *intel_dp)
2262{
2263 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265
7b13b58a
VS		 2266 /* enable with pattern 1 (as per spec) */
2267 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2268 DP_TRAINING_PATTERN_1);
2269
2270 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2271 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2272
2273 /*
2274 * Magic for VLV/CHV. We _must_ first set up the register
2275 * without actually enabling the port, and then do another
2276 * write to enable the port. Otherwise link training will
2277 * fail when the power sequencer is freshly used for this port.
2278 */
2279 intel_dp->DP |= DP_PORT_EN;
2280
2281 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2282 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2283}
2284
e8cb4558 2285static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2286{
e8cb4558
DV		 2287 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2288 struct drm_device *dev = encoder->base.dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2290 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2291 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2292
0c33d8d7
DV		 2293 if (WARN_ON(dp_reg & DP_PORT_EN))
2294 return;
5d613501 2295
093e3f13
VS		 2296 pps_lock(intel_dp);
2297
2298 if (IS_VALLEYVIEW(dev))
2299 vlv_init_panel_power_sequencer(intel_dp);
2300
7b13b58a 2301 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2302
2303 edp_panel_vdd_on(intel_dp);
2304 edp_panel_on(intel_dp);
2305 edp_panel_vdd_off(intel_dp, true);
2306
2307 pps_unlock(intel_dp);
2308
61234fa5
VS		 2309 if (IS_VALLEYVIEW(dev))
2310 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2311
f01eca2e 2312 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2313 intel_dp_start_link_train(intel_dp);
33a34e4e 2314 intel_dp_complete_link_train(intel_dp);
3ab9c637 2315 intel_dp_stop_link_train(intel_dp);
c1dec79a 2316
6e3c9717 2317 if (crtc->config->has_audio) {
c1dec79a
JN		 2318 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2319 pipe_name(crtc->pipe));
2320 intel_audio_codec_enable(encoder);
2321 }
ab1f90f9 2322}
89b667f8 2323
ecff4f3b
JN		 2324static void g4x_enable_dp(struct intel_encoder *encoder)
2325{
828f5c6e
JN		 2326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2327
ecff4f3b 2328 intel_enable_dp(encoder);
4be73780 2329 intel_edp_backlight_on(intel_dp);
ab1f90f9 2330}
89b667f8 2331
ab1f90f9
JN		 2332static void vlv_enable_dp(struct intel_encoder *encoder)
2333{
828f5c6e
JN		 2334 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2335
4be73780 2336 intel_edp_backlight_on(intel_dp);
b32c6f48 2337 intel_psr_enable(intel_dp);
d240f20f
JB		 2338}
2339
ecff4f3b 2340static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2341{
2342 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2343 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2344
8ac33ed3
DV		 2345 intel_dp_prepare(encoder);
2346
d41f1efb
DV		 2347 /* Only ilk+ has port A */
2348 if (dport->port == PORT_A) {
2349 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2350 ironlake_edp_pll_on(intel_dp);
d41f1efb 2351 }
ab1f90f9
JN		 2352}
2353
83b84597
VS		 2354static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2355{
2356 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2357 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2358 enum pipe pipe = intel_dp->pps_pipe;
2359 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2360
2361 edp_panel_vdd_off_sync(intel_dp);
2362
2363 /*
2364 * VLV seems to get confused when multiple power seqeuencers
2365 * have the same port selected (even if only one has power/vdd
2366 * enabled). The failure manifests as vlv_wait_port_ready() failing
2367 * CHV on the other hand doesn't seem to mind having the same port
2368 * selected in multiple power seqeuencers, but let's clear the
2369 * port select always when logically disconnecting a power sequencer
2370 * from a port.
2371 */
2372 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2373 pipe_name(pipe), port_name(intel_dig_port->port));
2374 I915_WRITE(pp_on_reg, 0);
2375 POSTING_READ(pp_on_reg);
2376
2377 intel_dp->pps_pipe = INVALID_PIPE;
2378}
2379
a4a5d2f8
VS		 2380static void vlv_steal_power_sequencer(struct drm_device *dev,
2381 enum pipe pipe)
2382{
2383 struct drm_i915_private *dev_priv = dev->dev_private;
2384 struct intel_encoder *encoder;
2385
2386 lockdep_assert_held(&dev_priv->pps_mutex);
2387
ac3c12e4
VS		 2388 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2389 return;
2390
a4a5d2f8
VS		 2391 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2392 base.head) {
2393 struct intel_dp *intel_dp;
773538e8 2394 enum port port;
a4a5d2f8
VS		 2395
2396 if (encoder->type != INTEL_OUTPUT_EDP)
2397 continue;
2398
2399 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2400 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2401
2402 if (intel_dp->pps_pipe != pipe)
2403 continue;
2404
2405 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2406 pipe_name(pipe), port_name(port));
a4a5d2f8 2407
034e43c6
VS		 2408 WARN(encoder->connectors_active,
2409 "stealing pipe %c power sequencer from active eDP port %c\n",
2410 pipe_name(pipe), port_name(port));
a4a5d2f8 2411
a4a5d2f8 2412 /* make sure vdd is off before we steal it */
83b84597 2413 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2414 }
2415}
2416
2417static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2418{
2419 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2420 struct intel_encoder *encoder = &intel_dig_port->base;
2421 struct drm_device *dev = encoder->base.dev;
2422 struct drm_i915_private *dev_priv = dev->dev_private;
2423 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2424
2425 lockdep_assert_held(&dev_priv->pps_mutex);
2426
093e3f13
VS		 2427 if (!is_edp(intel_dp))
2428 return;
2429
a4a5d2f8
VS		 2430 if (intel_dp->pps_pipe == crtc->pipe)
2431 return;
2432
2433 /*
2434 * If another power sequencer was being used on this
2435 * port previously make sure to turn off vdd there while
2436 * we still have control of it.
2437 */
2438 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2439 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2440
2441 /*
2442 * We may be stealing the power
2443 * sequencer from another port.
2444 */
2445 vlv_steal_power_sequencer(dev, crtc->pipe);
2446
2447 /* now it's all ours */
2448 intel_dp->pps_pipe = crtc->pipe;
2449
2450 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2451 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2452
2453 /* init power sequencer on this pipe and port */
36b5f425
VS		 2454 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2456}
2457
ab1f90f9 2458static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2459{
2bd2ad64 2460 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2461 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2462 struct drm_device *dev = encoder->base.dev;
89b667f8 2463 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2464 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2465 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2466 int pipe = intel_crtc->pipe;
2467 u32 val;
a4fc5ed6 2468
ab1f90f9 2469 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2470
ab3c759a 2471 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2472 val = 0;
2473 if (pipe)
2474 val |= (1<<21);
2475 else
2476 val &= ~(1<<21);
2477 val |= 0x001000c4;
ab3c759a
CML		 2478 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2479 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2480 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2481
ab1f90f9
JN		 2482 mutex_unlock(&dev_priv->dpio_lock);
2483
2484 intel_enable_dp(encoder);
89b667f8
JB		 2485}
2486
ecff4f3b 2487static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2488{
2489 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2490 struct drm_device *dev = encoder->base.dev;
2491 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2492 struct intel_crtc *intel_crtc =
2493 to_intel_crtc(encoder->base.crtc);
e4607fcf 2494 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2495 int pipe = intel_crtc->pipe;
89b667f8 2496
8ac33ed3
DV		 2497 intel_dp_prepare(encoder);
2498
89b667f8 2499 /* Program Tx lane resets to default */
0980a60f 2500 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2501 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2502 DPIO_PCS_TX_LANE2_RESET |
2503 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2504 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2505 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2506 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2507 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2508 DPIO_PCS_CLK_SOFT_RESET);
2509
2510 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2511 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2512 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2513 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2514 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2515}
2516
e4a1d846
CML		 2517static void chv_pre_enable_dp(struct intel_encoder *encoder)
2518{
2519 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2520 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2521 struct drm_device *dev = encoder->base.dev;
2522 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2523 struct intel_crtc *intel_crtc =
2524 to_intel_crtc(encoder->base.crtc);
2525 enum dpio_channel ch = vlv_dport_to_channel(dport);
2526 int pipe = intel_crtc->pipe;
2527 int data, i;
949c1d43 2528 u32 val;
e4a1d846 2529
e4a1d846 2530 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2531
570e2a74
VS		 2532 /* allow hardware to manage TX FIFO reset source */
2533 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2534 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2535 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2536
2537 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2538 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2539 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2540
949c1d43 2541 /* Deassert soft data lane reset*/
97fd4d5c 2542 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2543 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2544 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2545
2546 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2547 val |= CHV_PCS_REQ_SOFTRESET_EN;
2548 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2549
2550 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2551 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2552 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2553
97fd4d5c 2554 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2555 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2556 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2557
2558 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2559 for (i = 0; i < 4; i++) {
2560 /* Set the latency optimal bit */
2561 data = (i == 1) ? 0x0 : 0x6;
2562 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2563 data << DPIO_FRC_LATENCY_SHFIT);
2564
2565 /* Set the upar bit */
2566 data = (i == 1) ? 0x0 : 0x1;
2567 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2568 data << DPIO_UPAR_SHIFT);
2569 }
2570
2571 /* Data lane stagger programming */
2572 /* FIXME: Fix up value only after power analysis */
2573
2574 mutex_unlock(&dev_priv->dpio_lock);
2575
e4a1d846 2576 intel_enable_dp(encoder);
e4a1d846
CML		 2577}
2578
9197c88b
VS		 2579static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2580{
2581 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2582 struct drm_device *dev = encoder->base.dev;
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584 struct intel_crtc *intel_crtc =
2585 to_intel_crtc(encoder->base.crtc);
2586 enum dpio_channel ch = vlv_dport_to_channel(dport);
2587 enum pipe pipe = intel_crtc->pipe;
2588 u32 val;
2589
625695f8
VS		 2590 intel_dp_prepare(encoder);
2591
9197c88b
VS		 2592 mutex_lock(&dev_priv->dpio_lock);
2593
b9e5ac3c
VS		 2594 /* program left/right clock distribution */
2595 if (pipe != PIPE_B) {
2596 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2597 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2598 if (ch == DPIO_CH0)
2599 val |= CHV_BUFLEFTENA1_FORCE;
2600 if (ch == DPIO_CH1)
2601 val |= CHV_BUFRIGHTENA1_FORCE;
2602 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2603 } else {
2604 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2605 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2606 if (ch == DPIO_CH0)
2607 val |= CHV_BUFLEFTENA2_FORCE;
2608 if (ch == DPIO_CH1)
2609 val |= CHV_BUFRIGHTENA2_FORCE;
2610 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2611 }
2612
9197c88b
VS		 2613 /* program clock channel usage */
2614 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2615 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2616 if (pipe != PIPE_B)
2617 val &= ~CHV_PCS_USEDCLKCHANNEL;
2618 else
2619 val |= CHV_PCS_USEDCLKCHANNEL;
2620 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2621
2622 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2623 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2624 if (pipe != PIPE_B)
2625 val &= ~CHV_PCS_USEDCLKCHANNEL;
2626 else
2627 val |= CHV_PCS_USEDCLKCHANNEL;
2628 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2629
2630 /*
2631 * This a a bit weird since generally CL
2632 * matches the pipe, but here we need to
2633 * pick the CL based on the port.
2634 */
2635 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2636 if (pipe != PIPE_B)
2637 val &= ~CHV_CMN_USEDCLKCHANNEL;
2638 else
2639 val |= CHV_CMN_USEDCLKCHANNEL;
2640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2641
2642 mutex_unlock(&dev_priv->dpio_lock);
2643}
2644
a4fc5ed6 2645/*
df0c237d
JB		 2646 * Native read with retry for link status and receiver capability reads for
2647 * cases where the sink may still be asleep.
9d1a1031
JN		 2648 *
2649 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2650 * supposed to retry 3 times per the spec.
a4fc5ed6 2651 */
9d1a1031
JN		 2652static ssize_t
2653intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2654 void *buffer, size_t size)
a4fc5ed6 2655{
9d1a1031
JN		 2656 ssize_t ret;
2657 int i;
61da5fab 2658
f6a19066
VS		 2659 /*
2660 * Sometime we just get the same incorrect byte repeated
2661 * over the entire buffer. Doing just one throw away read
2662 * initially seems to "solve" it.
2663 */
2664 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2665
61da5fab 2666 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2667 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2668 if (ret == size)
2669 return ret;
61da5fab
JB		 2670 msleep(1);
2671 }
a4fc5ed6 2672
9d1a1031 2673 return ret;
a4fc5ed6
KP		 2674}
2675
2676/*
2677 * Fetch AUX CH registers 0x202 - 0x207 which contain
2678 * link status information
2679 */
2680static bool
93f62dad 2681intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2682{
9d1a1031
JN		 2683 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2684 DP_LANE0_1_STATUS,
2685 link_status,
2686 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2687}
2688
1100244e 2689/* These are source-specific values. */
a4fc5ed6 2690static uint8_t
1a2eb460 2691intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2692{
30add22d 2693 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2694 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2695 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2696
7ad14a29
SJ		 2697 if (INTEL_INFO(dev)->gen >= 9) {
2698 if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
2699 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2700 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2701 } else if (IS_VALLEYVIEW(dev))
bd60018a 2702 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2703 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2704 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2705 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2706 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2707 else
bd60018a 2708 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2709}
2710
2711static uint8_t
2712intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2713{
30add22d 2714 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2715 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2716
5a9d1f1a
DL		 2717 if (INTEL_INFO(dev)->gen >= 9) {
2718 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2719 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2720 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2721 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2722 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2723 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2724 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2725 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2726 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2727 default:
2728 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2729 }
2730 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2731 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2732 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2733 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2734 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2735 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2736 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2737 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2738 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2739 default:
bd60018a 2740 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2741 }
e2fa6fba
P		 2742 } else if (IS_VALLEYVIEW(dev)) {
2743 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2744 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2745 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2746 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2747 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2748 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2749 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2750 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2751 default:
bd60018a 2752 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2753 }
bc7d38a4 2754 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2755 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2756 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2757 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2758 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2759 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2760 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2761 default:
bd60018a 2762 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2763 }
2764 } else {
2765 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2766 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2767 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2768 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2769 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2770 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2771 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2772 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2773 default:
bd60018a 2774 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2775 }
a4fc5ed6
KP		 2776 }
2777}
2778
e2fa6fba
P		 2779static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2780{
2781 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2782 struct drm_i915_private *dev_priv = dev->dev_private;
2783 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2784 struct intel_crtc *intel_crtc =
2785 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2786 unsigned long demph_reg_value, preemph_reg_value,
2787 uniqtranscale_reg_value;
2788 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2789 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2790 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2791
2792 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2793 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2794 preemph_reg_value = 0x0004000;
2795 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2796 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2797 demph_reg_value = 0x2B405555;
2798 uniqtranscale_reg_value = 0x552AB83A;
2799 break;
bd60018a 2800 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2801 demph_reg_value = 0x2B404040;
2802 uniqtranscale_reg_value = 0x5548B83A;
2803 break;
bd60018a 2804 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2805 demph_reg_value = 0x2B245555;
2806 uniqtranscale_reg_value = 0x5560B83A;
2807 break;
bd60018a 2808 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2809 demph_reg_value = 0x2B405555;
2810 uniqtranscale_reg_value = 0x5598DA3A;
2811 break;
2812 default:
2813 return 0;
2814 }
2815 break;
bd60018a 2816 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2817 preemph_reg_value = 0x0002000;
2818 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2819 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2820 demph_reg_value = 0x2B404040;
2821 uniqtranscale_reg_value = 0x5552B83A;
2822 break;
bd60018a 2823 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2824 demph_reg_value = 0x2B404848;
2825 uniqtranscale_reg_value = 0x5580B83A;
2826 break;
bd60018a 2827 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2828 demph_reg_value = 0x2B404040;
2829 uniqtranscale_reg_value = 0x55ADDA3A;
2830 break;
2831 default:
2832 return 0;
2833 }
2834 break;
bd60018a 2835 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2836 preemph_reg_value = 0x0000000;
2837 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2838 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2839 demph_reg_value = 0x2B305555;
2840 uniqtranscale_reg_value = 0x5570B83A;
2841 break;
bd60018a 2842 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2843 demph_reg_value = 0x2B2B4040;
2844 uniqtranscale_reg_value = 0x55ADDA3A;
2845 break;
2846 default:
2847 return 0;
2848 }
2849 break;
bd60018a 2850 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2851 preemph_reg_value = 0x0006000;
2852 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2853 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2854 demph_reg_value = 0x1B405555;
2855 uniqtranscale_reg_value = 0x55ADDA3A;
2856 break;
2857 default:
2858 return 0;
2859 }
2860 break;
2861 default:
2862 return 0;
2863 }
2864
0980a60f 2865 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2866 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2867 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2868 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2869 uniqtranscale_reg_value);
ab3c759a
CML		 2870 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2871 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2872 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2873 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2874 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2875
2876 return 0;
2877}
2878
e4a1d846
CML		 2879static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2880{
2881 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2884 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2885 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2886 uint8_t train_set = intel_dp->train_set[0];
2887 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2888 enum pipe pipe = intel_crtc->pipe;
2889 int i;
e4a1d846
CML		 2890
2891 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2892 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2893 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2894 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2895 deemph_reg_value = 128;
2896 margin_reg_value = 52;
2897 break;
bd60018a 2898 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2899 deemph_reg_value = 128;
2900 margin_reg_value = 77;
2901 break;
bd60018a 2902 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2903 deemph_reg_value = 128;
2904 margin_reg_value = 102;
2905 break;
bd60018a 2906 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2907 deemph_reg_value = 128;
2908 margin_reg_value = 154;
2909 /* FIXME extra to set for 1200 */
2910 break;
2911 default:
2912 return 0;
2913 }
2914 break;
bd60018a 2915 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2916 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2918 deemph_reg_value = 85;
2919 margin_reg_value = 78;
2920 break;
bd60018a 2921 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2922 deemph_reg_value = 85;
2923 margin_reg_value = 116;
2924 break;
bd60018a 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2926 deemph_reg_value = 85;
2927 margin_reg_value = 154;
2928 break;
2929 default:
2930 return 0;
2931 }
2932 break;
bd60018a 2933 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2934 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2936 deemph_reg_value = 64;
2937 margin_reg_value = 104;
2938 break;
bd60018a 2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2940 deemph_reg_value = 64;
2941 margin_reg_value = 154;
2942 break;
2943 default:
2944 return 0;
2945 }
2946 break;
bd60018a 2947 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2948 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2950 deemph_reg_value = 43;
2951 margin_reg_value = 154;
2952 break;
2953 default:
2954 return 0;
2955 }
2956 break;
2957 default:
2958 return 0;
2959 }
2960
2961 mutex_lock(&dev_priv->dpio_lock);
2962
2963 /* Clear calc init */
1966e59e
VS		 2964 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2965 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2966 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2967 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 2968 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2969
2970 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2971 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2972 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2973 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 2974 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 2975
a02ef3c7
VS		 2976 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2977 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2978 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2979 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2980
2981 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2982 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2983 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2984 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2985
e4a1d846 2986 /* Program swing deemph */
f72df8db
VS		 2987 for (i = 0; i < 4; i++) {
2988 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2989 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2990 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2991 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2992 }
e4a1d846
CML		 2993
2994 /* Program swing margin */
f72df8db
VS		 2995 for (i = 0; i < 4; i++) {
2996 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2997 val &= ~DPIO_SWING_MARGIN000_MASK;
2998 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2999 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3000 }
e4a1d846
CML		 3001
3002 /* Disable unique transition scale */
f72df8db
VS		 3003 for (i = 0; i < 4; i++) {
3004 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3005 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3006 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3007 }
e4a1d846
CML		 3008
3009 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3010 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3011 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3012 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3013
3014 /*
3015 * The document said it needs to set bit 27 for ch0 and bit 26
3016 * for ch1. Might be a typo in the doc.
3017 * For now, for this unique transition scale selection, set bit
3018 * 27 for ch0 and ch1.
3019 */
f72df8db
VS		 3020 for (i = 0; i < 4; i++) {
3021 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3022 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3023 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3024 }
e4a1d846 3025
f72df8db
VS		 3026 for (i = 0; i < 4; i++) {
3027 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3028 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3029 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3030 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3031 }
e4a1d846
CML		 3032 }
3033
3034 /* Start swing calculation */
1966e59e
VS		 3035 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3036 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3037 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3038
3039 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3040 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3041 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3042
3043 /* LRC Bypass */
3044 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3045 val |= DPIO_LRC_BYPASS;
3046 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3047
3048 mutex_unlock(&dev_priv->dpio_lock);
3049
3050 return 0;
3051}
3052
a4fc5ed6 3053static void
0301b3ac
JN		 3054intel_get_adjust_train(struct intel_dp *intel_dp,
3055 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3056{
3057 uint8_t v = 0;
3058 uint8_t p = 0;
3059 int lane;
1a2eb460
KP		 3060 uint8_t voltage_max;
3061 uint8_t preemph_max;
a4fc5ed6 3062
33a34e4e 3063 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3064 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3065 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3066
3067 if (this_v > v)
3068 v = this_v;
3069 if (this_p > p)
3070 p = this_p;
3071 }
3072
1a2eb460 3073 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3074 if (v >= voltage_max)
3075 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3076
1a2eb460
KP		 3077 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3078 if (p >= preemph_max)
3079 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3080
3081 for (lane = 0; lane < 4; lane++)
33a34e4e 3082 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3083}
3084
3085static uint32_t
f0a3424e 3086intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3087{
3cf2efb1 3088 uint32_t signal_levels = 0;
a4fc5ed6 3089
3cf2efb1 3090 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3092 default:
3093 signal_levels |= DP_VOLTAGE_0_4;
3094 break;
bd60018a 3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3096 signal_levels |= DP_VOLTAGE_0_6;
3097 break;
bd60018a 3098 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3099 signal_levels |= DP_VOLTAGE_0_8;
3100 break;
bd60018a 3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3102 signal_levels |= DP_VOLTAGE_1_2;
3103 break;
3104 }
3cf2efb1 3105 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3106 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3107 default:
3108 signal_levels |= DP_PRE_EMPHASIS_0;
3109 break;
bd60018a 3110 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3111 signal_levels |= DP_PRE_EMPHASIS_3_5;
3112 break;
bd60018a 3113 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3114 signal_levels |= DP_PRE_EMPHASIS_6;
3115 break;
bd60018a 3116 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3117 signal_levels |= DP_PRE_EMPHASIS_9_5;
3118 break;
3119 }
3120 return signal_levels;
3121}
3122
e3421a18
ZW		 3123/* Gen6's DP voltage swing and pre-emphasis control */
3124static uint32_t
3125intel_gen6_edp_signal_levels(uint8_t train_set)
3126{
3c5a62b5
YL		 3127 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3128 DP_TRAIN_PRE_EMPHASIS_MASK);
3129 switch (signal_levels) {
bd60018a
SJ		 3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3132 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3134 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3136 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3137 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3140 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3142 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3143 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3144 default:
3c5a62b5
YL		 3145 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3146 "0x%x\n", signal_levels);
3147 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3148 }
3149}
3150
1a2eb460
KP		 3151/* Gen7's DP voltage swing and pre-emphasis control */
3152static uint32_t
3153intel_gen7_edp_signal_levels(uint8_t train_set)
3154{
3155 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3156 DP_TRAIN_PRE_EMPHASIS_MASK);
3157 switch (signal_levels) {
bd60018a 3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3159 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3161 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3163 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3164
bd60018a 3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3166 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3168 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3169
bd60018a 3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3171 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3173 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3174
3175 default:
3176 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3177 "0x%x\n", signal_levels);
3178 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3179 }
3180}
3181
d6c0d722
PZ		 3182/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3183static uint32_t
f0a3424e 3184intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3185{
d6c0d722
PZ		 3186 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3187 DP_TRAIN_PRE_EMPHASIS_MASK);
3188 switch (signal_levels) {
bd60018a 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3190 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3192 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3194 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3196 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3197
bd60018a 3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3199 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3200 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3201 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3203 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3204
bd60018a 3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3206 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3208 return DDI_BUF_TRANS_SELECT(8);
7ad14a29
SJ		 3209
3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3211 return DDI_BUF_TRANS_SELECT(9);
d6c0d722
PZ		 3212 default:
3213 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3214 "0x%x\n", signal_levels);
c5fe6a06 3215 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3216 }
a4fc5ed6
KP		 3217}
3218
f0a3424e
PZ		 3219/* Properly updates "DP" with the correct signal levels. */
3220static void
3221intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3222{
3223 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3224 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3225 struct drm_device *dev = intel_dig_port->base.base.dev;
3226 uint32_t signal_levels, mask;
3227 uint8_t train_set = intel_dp->train_set[0];
3228
5a9d1f1a 3229 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3230 signal_levels = intel_hsw_signal_levels(train_set);
3231 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3232 } else if (IS_CHERRYVIEW(dev)) {
3233 signal_levels = intel_chv_signal_levels(intel_dp);
3234 mask = 0;
e2fa6fba
P		 3235 } else if (IS_VALLEYVIEW(dev)) {
3236 signal_levels = intel_vlv_signal_levels(intel_dp);
3237 mask = 0;
bc7d38a4 3238 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3239 signal_levels = intel_gen7_edp_signal_levels(train_set);
3240 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3241 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3242 signal_levels = intel_gen6_edp_signal_levels(train_set);
3243 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3244 } else {
3245 signal_levels = intel_gen4_signal_levels(train_set);
3246 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3247 }
3248
3249 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3250
3251 *DP = (*DP & ~mask) | signal_levels;
3252}
3253
a4fc5ed6 3254static bool
ea5b213a 3255intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3256 uint32_t *DP,
58e10eb9 3257 uint8_t dp_train_pat)
a4fc5ed6 3258{
174edf1f
PZ		 3259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3260 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3261 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3262 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3263 int ret, len;
a4fc5ed6 3264
7b13b58a 3265 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3266
70aff66c 3267 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3268 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3269
2cdfe6c8
JN		 3270 buf[0] = dp_train_pat;
3271 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3272 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3273 /* don't write DP_TRAINING_LANEx_SET on disable */
3274 len = 1;
3275 } else {
3276 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3277 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3278 len = intel_dp->lane_count + 1;
47ea7542 3279 }
a4fc5ed6 3280
9d1a1031
JN		 3281 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3282 buf, len);
2cdfe6c8
JN		 3283
3284 return ret == len;
a4fc5ed6
KP		 3285}
3286
70aff66c
JN		 3287static bool
3288intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3289 uint8_t dp_train_pat)
3290{
953d22e8 3291 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3292 intel_dp_set_signal_levels(intel_dp, DP);
3293 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3294}
3295
3296static bool
3297intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3298 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3299{
3300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3301 struct drm_device *dev = intel_dig_port->base.base.dev;
3302 struct drm_i915_private *dev_priv = dev->dev_private;
3303 int ret;
3304
3305 intel_get_adjust_train(intel_dp, link_status);
3306 intel_dp_set_signal_levels(intel_dp, DP);
3307
3308 I915_WRITE(intel_dp->output_reg, *DP);
3309 POSTING_READ(intel_dp->output_reg);
3310
9d1a1031
JN		 3311 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3312 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3313
3314 return ret == intel_dp->lane_count;
3315}
3316
3ab9c637
ID		 3317static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3318{
3319 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3320 struct drm_device *dev = intel_dig_port->base.base.dev;
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 enum port port = intel_dig_port->port;
3323 uint32_t val;
3324
3325 if (!HAS_DDI(dev))
3326 return;
3327
3328 val = I915_READ(DP_TP_CTL(port));
3329 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3330 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3331 I915_WRITE(DP_TP_CTL(port), val);
3332
3333 /*
3334 * On PORT_A we can have only eDP in SST mode. There the only reason
3335 * we need to set idle transmission mode is to work around a HW issue
3336 * where we enable the pipe while not in idle link-training mode.
3337 * In this case there is requirement to wait for a minimum number of
3338 * idle patterns to be sent.
3339 */
3340 if (port == PORT_A)
3341 return;
3342
3343 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3344 1))
3345 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3346}
3347
33a34e4e 3348/* Enable corresponding port and start training pattern 1 */
c19b0669 3349void
33a34e4e 3350intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3351{
da63a9f2 3352 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3353 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3354 int i;
3355 uint8_t voltage;
cdb0e95b 3356 int voltage_tries, loop_tries;
ea5b213a 3357 uint32_t DP = intel_dp->DP;
6aba5b6c 3358 uint8_t link_config[2];
a4fc5ed6 3359
affa9354 3360 if (HAS_DDI(dev))
c19b0669
PZ		 3361 intel_ddi_prepare_link_retrain(encoder);
3362
3cf2efb1 3363 /* Write the link configuration data */
6aba5b6c
JN		 3364 link_config[0] = intel_dp->link_bw;
3365 link_config[1] = intel_dp->lane_count;
3366 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3367 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3368 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3369
3370 link_config[0] = 0;
3371 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3372 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3373
3374 DP |= DP_PORT_EN;
1a2eb460 3375
70aff66c
JN		 3376 /* clock recovery */
3377 if (!intel_dp_reset_link_train(intel_dp, &DP,
3378 DP_TRAINING_PATTERN_1 |
3379 DP_LINK_SCRAMBLING_DISABLE)) {
3380 DRM_ERROR("failed to enable link training\n");
3381 return;
3382 }
3383
a4fc5ed6 3384 voltage = 0xff;
cdb0e95b
KP		 3385 voltage_tries = 0;
3386 loop_tries = 0;
a4fc5ed6 3387 for (;;) {
70aff66c 3388 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3389
a7c9655f 3390 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3391 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3392 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3393 break;
93f62dad 3394 }
a4fc5ed6 3395
01916270 3396 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3397 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3398 break;
3399 }
3400
3401 /* Check to see if we've tried the max voltage */
3402 for (i = 0; i < intel_dp->lane_count; i++)
3403 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3404 break;
3b4f819d 3405 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3406 ++loop_tries;
3407 if (loop_tries == 5) {
3def84b3 3408 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3409 break;
3410 }
70aff66c
JN		 3411 intel_dp_reset_link_train(intel_dp, &DP,
3412 DP_TRAINING_PATTERN_1 |
3413 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3414 voltage_tries = 0;
3415 continue;
3416 }
a4fc5ed6 3417
3cf2efb1 3418 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3419 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3420 ++voltage_tries;
b06fbda3 3421 if (voltage_tries == 5) {
3def84b3 3422 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3423 break;
3424 }
3425 } else
3426 voltage_tries = 0;
3427 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3428
70aff66c
JN		 3429 /* Update training set as requested by target */
3430 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3431 DRM_ERROR("failed to update link training\n");
3432 break;
3433 }
a4fc5ed6
KP		 3434 }
3435
33a34e4e
JB		 3436 intel_dp->DP = DP;
3437}
3438
c19b0669 3439void
33a34e4e
JB		 3440intel_dp_complete_link_train(struct intel_dp *intel_dp)
3441{
33a34e4e 3442 bool channel_eq = false;
37f80975 3443 int tries, cr_tries;
33a34e4e 3444 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3445 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3446
3447 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3448 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3449 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3450
a4fc5ed6 3451 /* channel equalization */
70aff66c 3452 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3453 training_pattern |
70aff66c
JN		 3454 DP_LINK_SCRAMBLING_DISABLE)) {
3455 DRM_ERROR("failed to start channel equalization\n");
3456 return;
3457 }
3458
a4fc5ed6 3459 tries = 0;
37f80975 3460 cr_tries = 0;
a4fc5ed6
KP		 3461 channel_eq = false;
3462 for (;;) {
70aff66c 3463 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3464
37f80975
JB		 3465 if (cr_tries > 5) {
3466 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3467 break;
3468 }
3469
a7c9655f 3470 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3471 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3472 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3473 break;
70aff66c 3474 }
a4fc5ed6 3475
37f80975 3476 /* Make sure clock is still ok */
01916270 3477 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3478 intel_dp_start_link_train(intel_dp);
70aff66c 3479 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3480 training_pattern |
70aff66c 3481 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3482 cr_tries++;
3483 continue;
3484 }
3485
1ffdff13 3486 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3487 channel_eq = true;
3488 break;
3489 }
a4fc5ed6 3490
37f80975
JB		 3491 /* Try 5 times, then try clock recovery if that fails */
3492 if (tries > 5) {
37f80975 3493 intel_dp_start_link_train(intel_dp);
70aff66c 3494 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3495 training_pattern |
70aff66c 3496 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3497 tries = 0;
3498 cr_tries++;
3499 continue;
3500 }
a4fc5ed6 3501
70aff66c
JN		 3502 /* Update training set as requested by target */
3503 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3504 DRM_ERROR("failed to update link training\n");
3505 break;
3506 }
3cf2efb1 3507 ++tries;
869184a6 3508 }
3cf2efb1 3509
3ab9c637
ID		 3510 intel_dp_set_idle_link_train(intel_dp);
3511
3512 intel_dp->DP = DP;
3513
d6c0d722 3514 if (channel_eq)
07f42258 3515 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3516
3ab9c637
ID		 3517}
3518
3519void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3520{
70aff66c 3521 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3522 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3523}
3524
3525static void
ea5b213a 3526intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3527{
da63a9f2 3528 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3529 enum port port = intel_dig_port->port;
da63a9f2 3530 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3531 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3532 struct intel_crtc *intel_crtc =
3533 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3534 uint32_t DP = intel_dp->DP;
a4fc5ed6 3535
bc76e320 3536 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3537 return;
3538
0c33d8d7 3539 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3540 return;
3541
28c97730 3542 DRM_DEBUG_KMS("\n");
32f9d658 3543
bc7d38a4 3544 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3545 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3546 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3547 } else {
aad3d14d
VS		 3548 if (IS_CHERRYVIEW(dev))
3549 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3550 else
3551 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3552 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3553 }
fe255d00 3554 POSTING_READ(intel_dp->output_reg);
5eb08b69 3555
493a7081 3556 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3557 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3558 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3559
5bddd17f
EA		 3560 /* Hardware workaround: leaving our transcoder select
3561 * set to transcoder B while it's off will prevent the
3562 * corresponding HDMI output on transcoder A.
3563 *
3564 * Combine this with another hardware workaround:
3565 * transcoder select bit can only be cleared while the
3566 * port is enabled.
3567 */
3568 DP &= ~DP_PIPEB_SELECT;
3569 I915_WRITE(intel_dp->output_reg, DP);
3570
3571 /* Changes to enable or select take place the vblank
3572 * after being written.
3573 */
ff50afe9
DV		 3574 if (WARN_ON(crtc == NULL)) {
3575 /* We should never try to disable a port without a crtc
3576 * attached. For paranoia keep the code around for a
3577 * bit. */
31acbcc4
CW		 3578 POSTING_READ(intel_dp->output_reg);
3579 msleep(50);
3580 } else
ab527efc 3581 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3582 }
3583
832afda6 3584 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3585 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3586 POSTING_READ(intel_dp->output_reg);
f01eca2e 3587 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3588}
3589
26d61aad
KP		 3590static bool
3591intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3592{
a031d709
RV		 3593 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3594 struct drm_device *dev = dig_port->base.base.dev;
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596
9d1a1031
JN		 3597 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3598 sizeof(intel_dp->dpcd)) < 0)
edb39244 3599 return false; /* aux transfer failed */
92fd8fd1 3600
a8e98153 3601 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3602
edb39244
AJ		 3603 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3604 return false; /* DPCD not present */
3605
2293bb5c
SK		 3606 /* Check if the panel supports PSR */
3607 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3608 if (is_edp(intel_dp)) {
9d1a1031
JN		 3609 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3610 intel_dp->psr_dpcd,
3611 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3612 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3613 dev_priv->psr.sink_support = true;
50003939 3614 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3615 }
50003939
JN		 3616 }
3617
7809a611 3618 /* Training Pattern 3 support, both source and sink */
06ea66b6 3619 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3620 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3621 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3622 intel_dp->use_tps3 = true;
f8d8a672 3623 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3624 } else
3625 intel_dp->use_tps3 = false;
3626
edb39244
AJ		 3627 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3628 DP_DWN_STRM_PORT_PRESENT))
3629 return true; /* native DP sink */
3630
3631 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3632 return true; /* no per-port downstream info */
3633
9d1a1031
JN		 3634 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3635 intel_dp->downstream_ports,
3636 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3637 return false; /* downstream port status fetch failed */
3638
3639 return true;
92fd8fd1
KP		 3640}
3641
0d198328
AJ		 3642static void
3643intel_dp_probe_oui(struct intel_dp *intel_dp)
3644{
3645 u8 buf[3];
3646
3647 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3648 return;
3649
9d1a1031 3650 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3651 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3652 buf[0], buf[1], buf[2]);
3653
9d1a1031 3654 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3655 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3656 buf[0], buf[1], buf[2]);
3657}
3658
0e32b39c
DA		 3659static bool
3660intel_dp_probe_mst(struct intel_dp *intel_dp)
3661{
3662 u8 buf[1];
3663
3664 if (!intel_dp->can_mst)
3665 return false;
3666
3667 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3668 return false;
3669
0e32b39c
DA		 3670 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3671 if (buf[0] & DP_MST_CAP) {
3672 DRM_DEBUG_KMS("Sink is MST capable\n");
3673 intel_dp->is_mst = true;
3674 } else {
3675 DRM_DEBUG_KMS("Sink is not MST capable\n");
3676 intel_dp->is_mst = false;
3677 }
3678 }
0e32b39c
DA		 3679
3680 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3681 return intel_dp->is_mst;
3682}
3683
d2e216d0
RV		 3684int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3685{
3686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3687 struct drm_device *dev = intel_dig_port->base.base.dev;
3688 struct intel_crtc *intel_crtc =
3689 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3690 u8 buf;
3691 int test_crc_count;
3692 int attempts = 6;
d2e216d0 3693
ad9dc91b 3694 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3695 return -EIO;
d2e216d0 3696
ad9dc91b 3697 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3698 return -ENOTTY;
3699
1dda5f93
RV		 3700 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3701 return -EIO;
3702
9d1a1031 3703 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3704 buf | DP_TEST_SINK_START) < 0)
bda0381e 3705 return -EIO;
d2e216d0 3706
1dda5f93 3707 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3708 return -EIO;
ad9dc91b 3709 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3710
ad9dc91b 3711 do {
1dda5f93
RV		 3712 if (drm_dp_dpcd_readb(&intel_dp->aux,
3713 DP_TEST_SINK_MISC, &buf) < 0)
3714 return -EIO;
ad9dc91b
RV		 3715 intel_wait_for_vblank(dev, intel_crtc->pipe);
3716 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3717
3718 if (attempts == 0) {
90bd1f46
DV		 3719 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3720 return -ETIMEDOUT;
ad9dc91b 3721 }
d2e216d0 3722
9d1a1031 3723 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3724 return -EIO;
d2e216d0 3725
1dda5f93
RV		 3726 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3727 return -EIO;
3728 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3729 buf & ~DP_TEST_SINK_START) < 0)
3730 return -EIO;
ce31d9f4 3731
d2e216d0
RV		 3732 return 0;
3733}
3734
a60f0e38
JB		 3735static bool
3736intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3737{
9d1a1031
JN		 3738 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3739 DP_DEVICE_SERVICE_IRQ_VECTOR,
3740 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3741}
3742
0e32b39c
DA		 3743static bool
3744intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3745{
3746 int ret;
3747
3748 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3749 DP_SINK_COUNT_ESI,
3750 sink_irq_vector, 14);
3751 if (ret != 14)
3752 return false;
3753
3754 return true;
3755}
3756
a60f0e38
JB		 3757static void
3758intel_dp_handle_test_request(struct intel_dp *intel_dp)
3759{
3760 /* NAK by default */
9d1a1031 3761 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3762}
3763
0e32b39c
DA		 3764static int
3765intel_dp_check_mst_status(struct intel_dp *intel_dp)
3766{
3767 bool bret;
3768
3769 if (intel_dp->is_mst) {
3770 u8 esi[16] = { 0 };
3771 int ret = 0;
3772 int retry;
3773 bool handled;
3774 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3775go_again:
3776 if (bret == true) {
3777
3778 /* check link status - esi[10] = 0x200c */
3779 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3780 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3781 intel_dp_start_link_train(intel_dp);
3782 intel_dp_complete_link_train(intel_dp);
3783 intel_dp_stop_link_train(intel_dp);
3784 }
3785
6f34cc39 3786 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3787 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3788
3789 if (handled) {
3790 for (retry = 0; retry < 3; retry++) {
3791 int wret;
3792 wret = drm_dp_dpcd_write(&intel_dp->aux,
3793 DP_SINK_COUNT_ESI+1,
3794 &esi[1], 3);
3795 if (wret == 3) {
3796 break;
3797 }
3798 }
3799
3800 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3801 if (bret == true) {
6f34cc39 3802 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3803 goto go_again;
3804 }
3805 } else
3806 ret = 0;
3807
3808 return ret;
3809 } else {
3810 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3811 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3812 intel_dp->is_mst = false;
3813 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3814 /* send a hotplug event */
3815 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3816 }
3817 }
3818 return -EINVAL;
3819}
3820
a4fc5ed6
KP		 3821/*
3822 * According to DP spec
3823 * 5.1.2:
3824 * 1. Read DPCD
3825 * 2. Configure link according to Receiver Capabilities
3826 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3827 * 4. Check link status on receipt of hot-plug interrupt
3828 */
a5146200 3829static void
ea5b213a 3830intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3831{
5b215bcf 3832 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3833 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3834 u8 sink_irq_vector;
93f62dad 3835 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3836
5b215bcf
DA		 3837 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3838
da63a9f2 3839 if (!intel_encoder->connectors_active)
d2b996ac 3840 return;
59cd09e1 3841
da63a9f2 3842 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3843 return;
3844
1a125d8a
ID		 3845 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3846 return;
3847
92fd8fd1 3848 /* Try to read receiver status if the link appears to be up */
93f62dad 3849 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3850 return;
3851 }
3852
92fd8fd1 3853 /* Now read the DPCD to see if it's actually running */
26d61aad 3854 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3855 return;
3856 }
3857
a60f0e38
JB		 3858 /* Try to read the source of the interrupt */
3859 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3860 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3861 /* Clear interrupt source */
9d1a1031
JN		 3862 drm_dp_dpcd_writeb(&intel_dp->aux,
3863 DP_DEVICE_SERVICE_IRQ_VECTOR,
3864 sink_irq_vector);
a60f0e38
JB		 3865
3866 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3867 intel_dp_handle_test_request(intel_dp);
3868 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3869 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3870 }
3871
1ffdff13 3872 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3873 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3874 intel_encoder->base.name);
33a34e4e
JB		 3875 intel_dp_start_link_train(intel_dp);
3876 intel_dp_complete_link_train(intel_dp);
3ab9c637 3877 intel_dp_stop_link_train(intel_dp);
33a34e4e 3878 }
a4fc5ed6 3879}
a4fc5ed6 3880
caf9ab24 3881/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3882static enum drm_connector_status
26d61aad 3883intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3884{
caf9ab24 3885 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3886 uint8_t type;
3887
3888 if (!intel_dp_get_dpcd(intel_dp))
3889 return connector_status_disconnected;
3890
3891 /* if there's no downstream port, we're done */
3892 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3893 return connector_status_connected;
caf9ab24
AJ		 3894
3895 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3896 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3897 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3898 uint8_t reg;
9d1a1031
JN		 3899
3900 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3901 &reg, 1) < 0)
caf9ab24 3902 return connector_status_unknown;
9d1a1031 3903
23235177
AJ		 3904 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3905 : connector_status_disconnected;
caf9ab24
AJ		 3906 }
3907
3908 /* If no HPD, poke DDC gently */
0b99836f 3909 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3910 return connector_status_connected;
caf9ab24
AJ		 3911
3912 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3913 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3914 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3915 if (type == DP_DS_PORT_TYPE_VGA ||
3916 type == DP_DS_PORT_TYPE_NON_EDID)
3917 return connector_status_unknown;
3918 } else {
3919 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3920 DP_DWN_STRM_PORT_TYPE_MASK;
3921 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3922 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3923 return connector_status_unknown;
3924 }
caf9ab24
AJ		 3925
3926 /* Anything else is out of spec, warn and ignore */
3927 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3928 return connector_status_disconnected;
71ba9000
AJ		 3929}
3930
d410b56d
CW		 3931static enum drm_connector_status
3932edp_detect(struct intel_dp *intel_dp)
3933{
3934 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3935 enum drm_connector_status status;
3936
3937 status = intel_panel_detect(dev);
3938 if (status == connector_status_unknown)
3939 status = connector_status_connected;
3940
3941 return status;
3942}
3943
5eb08b69 3944static enum drm_connector_status
a9756bb5 3945ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3946{
30add22d 3947 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3948 struct drm_i915_private *dev_priv = dev->dev_private;
3949 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3950
1b469639
DL		 3951 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3952 return connector_status_disconnected;
3953
26d61aad 3954 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3955}
3956
2a592bec
DA		 3957static int g4x_digital_port_connected(struct drm_device *dev,
3958 struct intel_digital_port *intel_dig_port)
a4fc5ed6 3959{
a4fc5ed6 3960 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 3961 uint32_t bit;
5eb08b69 3962
232a6ee9
TP		 3963 if (IS_VALLEYVIEW(dev)) {
3964 switch (intel_dig_port->port) {
3965 case PORT_B:
3966 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3967 break;
3968 case PORT_C:
3969 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3970 break;
3971 case PORT_D:
3972 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3973 break;
3974 default:
2a592bec 3975 return -EINVAL;
232a6ee9
TP		 3976 }
3977 } else {
3978 switch (intel_dig_port->port) {
3979 case PORT_B:
3980 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3981 break;
3982 case PORT_C:
3983 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3984 break;
3985 case PORT_D:
3986 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3987 break;
3988 default:
2a592bec 3989 return -EINVAL;
232a6ee9 3990 }
a4fc5ed6
KP		 3991 }
3992
10f76a38 3993 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 3994 return 0;
3995 return 1;
3996}
3997
3998static enum drm_connector_status
3999g4x_dp_detect(struct intel_dp *intel_dp)
4000{
4001 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4002 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4003 int ret;
4004
4005 /* Can't disconnect eDP, but you can close the lid... */
4006 if (is_edp(intel_dp)) {
4007 enum drm_connector_status status;
4008
4009 status = intel_panel_detect(dev);
4010 if (status == connector_status_unknown)
4011 status = connector_status_connected;
4012 return status;
4013 }
4014
4015 ret = g4x_digital_port_connected(dev, intel_dig_port);
4016 if (ret == -EINVAL)
4017 return connector_status_unknown;
4018 else if (ret == 0)
a4fc5ed6
KP		 4019 return connector_status_disconnected;
4020
26d61aad 4021 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4022}
4023
8c241fef 4024static struct edid *
beb60608 4025intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4026{
beb60608 4027 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4028
9cd300e0
JN		 4029 /* use cached edid if we have one */
4030 if (intel_connector->edid) {
9cd300e0
JN		 4031 /* invalid edid */
4032 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4033 return NULL;
4034
55e9edeb 4035 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4036 } else
4037 return drm_get_edid(&intel_connector->base,
4038 &intel_dp->aux.ddc);
4039}
8c241fef 4040
beb60608
CW		 4041static void
4042intel_dp_set_edid(struct intel_dp *intel_dp)
4043{
4044 struct intel_connector *intel_connector = intel_dp->attached_connector;
4045 struct edid *edid;
8c241fef 4046
beb60608
CW		 4047 edid = intel_dp_get_edid(intel_dp);
4048 intel_connector->detect_edid = edid;
4049
4050 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4051 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4052 else
4053 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4054}
4055
beb60608
CW		 4056static void
4057intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4058{
beb60608 4059 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4060
beb60608
CW		 4061 kfree(intel_connector->detect_edid);
4062 intel_connector->detect_edid = NULL;
9cd300e0 4063
beb60608
CW		 4064 intel_dp->has_audio = false;
4065}
d6f24d0f 4066
beb60608
CW		 4067static enum intel_display_power_domain
4068intel_dp_power_get(struct intel_dp *dp)
4069{
4070 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4071 enum intel_display_power_domain power_domain;
4072
4073 power_domain = intel_display_port_power_domain(encoder);
4074 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4075
4076 return power_domain;
4077}
d6f24d0f 4078
beb60608
CW		 4079static void
4080intel_dp_power_put(struct intel_dp *dp,
4081 enum intel_display_power_domain power_domain)
4082{
4083 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4084 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4085}
4086
a9756bb5
ZW		 4087static enum drm_connector_status
4088intel_dp_detect(struct drm_connector *connector, bool force)
4089{
4090 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4091 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4092 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4093 struct drm_device *dev = connector->dev;
a9756bb5 4094 enum drm_connector_status status;
671dedd2 4095 enum intel_display_power_domain power_domain;
0e32b39c 4096 bool ret;
a9756bb5 4097
164c8598 4098 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4099 connector->base.id, connector->name);
beb60608 4100 intel_dp_unset_edid(intel_dp);
164c8598 4101
0e32b39c
DA		 4102 if (intel_dp->is_mst) {
4103 /* MST devices are disconnected from a monitor POV */
4104 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4105 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4106 return connector_status_disconnected;
0e32b39c
DA		 4107 }
4108
beb60608 4109 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4110
d410b56d
CW		 4111 /* Can't disconnect eDP, but you can close the lid... */
4112 if (is_edp(intel_dp))
4113 status = edp_detect(intel_dp);
4114 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4115 status = ironlake_dp_detect(intel_dp);
4116 else
4117 status = g4x_dp_detect(intel_dp);
4118 if (status != connector_status_connected)
c8c8fb33 4119 goto out;
a9756bb5 4120
0d198328
AJ		 4121 intel_dp_probe_oui(intel_dp);
4122
0e32b39c
DA		 4123 ret = intel_dp_probe_mst(intel_dp);
4124 if (ret) {
4125 /* if we are in MST mode then this connector
4126 won't appear connected or have anything with EDID on it */
4127 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4128 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4129 status = connector_status_disconnected;
4130 goto out;
4131 }
4132
beb60608 4133 intel_dp_set_edid(intel_dp);
a9756bb5 4134
d63885da
PZ		 4135 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4136 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4137 status = connector_status_connected;
4138
4139out:
beb60608 4140 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4141 return status;
a4fc5ed6
KP		 4142}
4143
beb60608
CW		 4144static void
4145intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4146{
df0e9248 4147 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4148 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4149 enum intel_display_power_domain power_domain;
a4fc5ed6 4150
beb60608
CW		 4151 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4152 connector->base.id, connector->name);
4153 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4154
beb60608
CW		 4155 if (connector->status != connector_status_connected)
4156 return;
671dedd2 4157
beb60608
CW		 4158 power_domain = intel_dp_power_get(intel_dp);
4159
4160 intel_dp_set_edid(intel_dp);
4161
4162 intel_dp_power_put(intel_dp, power_domain);
4163
4164 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4165 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4166}
4167
4168static int intel_dp_get_modes(struct drm_connector *connector)
4169{
4170 struct intel_connector *intel_connector = to_intel_connector(connector);
4171 struct edid *edid;
4172
4173 edid = intel_connector->detect_edid;
4174 if (edid) {
4175 int ret = intel_connector_update_modes(connector, edid);
4176 if (ret)
4177 return ret;
4178 }
32f9d658 4179
f8779fda 4180 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4181 if (is_edp(intel_attached_dp(connector)) &&
4182 intel_connector->panel.fixed_mode) {
f8779fda 4183 struct drm_display_mode *mode;
beb60608
CW		 4184
4185 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4186 intel_connector->panel.fixed_mode);
f8779fda 4187 if (mode) {
32f9d658
ZW		 4188 drm_mode_probed_add(connector, mode);
4189 return 1;
4190 }
4191 }
beb60608 4192
32f9d658 4193 return 0;
a4fc5ed6
KP		 4194}
4195
1aad7ac0
CW		 4196static bool
4197intel_dp_detect_audio(struct drm_connector *connector)
4198{
1aad7ac0 4199 bool has_audio = false;
beb60608 4200 struct edid *edid;
1aad7ac0 4201
beb60608
CW		 4202 edid = to_intel_connector(connector)->detect_edid;
4203 if (edid)
1aad7ac0 4204 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4205
1aad7ac0
CW		 4206 return has_audio;
4207}
4208
f684960e
CW		 4209static int
4210intel_dp_set_property(struct drm_connector *connector,
4211 struct drm_property *property,
4212 uint64_t val)
4213{
e953fd7b 4214 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4215 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4216 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4217 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4218 int ret;
4219
662595df 4220 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4221 if (ret)
4222 return ret;
4223
3f43c48d 4224 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4225 int i = val;
4226 bool has_audio;
4227
4228 if (i == intel_dp->force_audio)
f684960e
CW		 4229 return 0;
4230
1aad7ac0 4231 intel_dp->force_audio = i;
f684960e 4232
c3e5f67b 4233 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4234 has_audio = intel_dp_detect_audio(connector);
4235 else
c3e5f67b 4236 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4237
4238 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4239 return 0;
4240
1aad7ac0 4241 intel_dp->has_audio = has_audio;
f684960e
CW		 4242 goto done;
4243 }
4244
e953fd7b 4245 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4246 bool old_auto = intel_dp->color_range_auto;
4247 uint32_t old_range = intel_dp->color_range;
4248
55bc60db
VS		 4249 switch (val) {
4250 case INTEL_BROADCAST_RGB_AUTO:
4251 intel_dp->color_range_auto = true;
4252 break;
4253 case INTEL_BROADCAST_RGB_FULL:
4254 intel_dp->color_range_auto = false;
4255 intel_dp->color_range = 0;
4256 break;
4257 case INTEL_BROADCAST_RGB_LIMITED:
4258 intel_dp->color_range_auto = false;
4259 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4260 break;
4261 default:
4262 return -EINVAL;
4263 }
ae4edb80
DV		 4264
4265 if (old_auto == intel_dp->color_range_auto &&
4266 old_range == intel_dp->color_range)
4267 return 0;
4268
e953fd7b
CW		 4269 goto done;
4270 }
4271
53b41837
YN		 4272 if (is_edp(intel_dp) &&
4273 property == connector->dev->mode_config.scaling_mode_property) {
4274 if (val == DRM_MODE_SCALE_NONE) {
4275 DRM_DEBUG_KMS("no scaling not supported\n");
4276 return -EINVAL;
4277 }
4278
4279 if (intel_connector->panel.fitting_mode == val) {
4280 /* the eDP scaling property is not changed */
4281 return 0;
4282 }
4283 intel_connector->panel.fitting_mode = val;
4284
4285 goto done;
4286 }
4287
f684960e
CW		 4288 return -EINVAL;
4289
4290done:
c0c36b94
CW		 4291 if (intel_encoder->base.crtc)
4292 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4293
4294 return 0;
4295}
4296
a4fc5ed6 4297static void
73845adf 4298intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4299{
1d508706 4300 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4301
10e972d3 4302 kfree(intel_connector->detect_edid);
beb60608 4303
9cd300e0
JN		 4304 if (!IS_ERR_OR_NULL(intel_connector->edid))
4305 kfree(intel_connector->edid);
4306
acd8db10
PZ		 4307 /* Can't call is_edp() since the encoder may have been destroyed
4308 * already. */
4309 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4310 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4311
a4fc5ed6 4312 drm_connector_cleanup(connector);
55f78c43 4313 kfree(connector);
a4fc5ed6
KP		 4314}
4315
00c09d70 4316void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4317{
da63a9f2
PZ		 4318 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4319 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4320
4f71d0cb 4321 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4322 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4323 if (is_edp(intel_dp)) {
4324 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4325 /*
4326 * vdd might still be enabled do to the delayed vdd off.
4327 * Make sure vdd is actually turned off here.
4328 */
773538e8 4329 pps_lock(intel_dp);
4be73780 4330 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4331 pps_unlock(intel_dp);
4332
01527b31
CT		 4333 if (intel_dp->edp_notifier.notifier_call) {
4334 unregister_reboot_notifier(&intel_dp->edp_notifier);
4335 intel_dp->edp_notifier.notifier_call = NULL;
4336 }
bd943159 4337 }
c8bd0e49 4338 drm_encoder_cleanup(encoder);
da63a9f2 4339 kfree(intel_dig_port);
24d05927
DV		 4340}
4341
07f9cd0b
ID		 4342static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4343{
4344 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4345
4346 if (!is_edp(intel_dp))
4347 return;
4348
951468f3
VS		 4349 /*
4350 * vdd might still be enabled do to the delayed vdd off.
4351 * Make sure vdd is actually turned off here.
4352 */
afa4e53a 4353 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4354 pps_lock(intel_dp);
07f9cd0b 4355 edp_panel_vdd_off_sync(intel_dp);
773538e8 4356 pps_unlock(intel_dp);
07f9cd0b
ID		 4357}
4358
49e6bc51
VS		 4359static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4360{
4361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4362 struct drm_device *dev = intel_dig_port->base.base.dev;
4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364 enum intel_display_power_domain power_domain;
4365
4366 lockdep_assert_held(&dev_priv->pps_mutex);
4367
4368 if (!edp_have_panel_vdd(intel_dp))
4369 return;
4370
4371 /*
4372 * The VDD bit needs a power domain reference, so if the bit is
4373 * already enabled when we boot or resume, grab this reference and
4374 * schedule a vdd off, so we don't hold on to the reference
4375 * indefinitely.
4376 */
4377 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4378 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4379 intel_display_power_get(dev_priv, power_domain);
4380
4381 edp_panel_vdd_schedule_off(intel_dp);
4382}
4383
6d93c0c4
ID		 4384static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4385{
49e6bc51
VS		 4386 struct intel_dp *intel_dp;
4387
4388 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4389 return;
4390
4391 intel_dp = enc_to_intel_dp(encoder);
4392
4393 pps_lock(intel_dp);
4394
4395 /*
4396 * Read out the current power sequencer assignment,
4397 * in case the BIOS did something with it.
4398 */
4399 if (IS_VALLEYVIEW(encoder->dev))
4400 vlv_initial_power_sequencer_setup(intel_dp);
4401
4402 intel_edp_panel_vdd_sanitize(intel_dp);
4403
4404 pps_unlock(intel_dp);
6d93c0c4
ID		 4405}
4406
a4fc5ed6 4407static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4408 .dpms = intel_connector_dpms,
a4fc5ed6 4409 .detect = intel_dp_detect,
beb60608 4410 .force = intel_dp_force,
a4fc5ed6 4411 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4412 .set_property = intel_dp_set_property,
2545e4a6 4413 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4414 .destroy = intel_dp_connector_destroy,
c6f95f27 4415 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
a4fc5ed6
KP		 4416};
4417
4418static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4419 .get_modes = intel_dp_get_modes,
4420 .mode_valid = intel_dp_mode_valid,
df0e9248 4421 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4422};
4423
a4fc5ed6 4424static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4425 .reset = intel_dp_encoder_reset,
24d05927 4426 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4427};
4428
0e32b39c 4429void
21d40d37 4430intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4431{
0e32b39c 4432 return;
c8110e52 4433}
6207937d 4434
b2c5c181 4435enum irqreturn
13cf5504
DA		 4436intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4437{
4438 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4439 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4440 struct drm_device *dev = intel_dig_port->base.base.dev;
4441 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4442 enum intel_display_power_domain power_domain;
b2c5c181 4443 enum irqreturn ret = IRQ_NONE;
1c767b33 4444
0e32b39c
DA		 4445 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4446 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4447
7a7f84cc
VS		 4448 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4449 /*
4450 * vdd off can generate a long pulse on eDP which
4451 * would require vdd on to handle it, and thus we
4452 * would end up in an endless cycle of
4453 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4454 */
4455 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4456 port_name(intel_dig_port->port));
4457 return false;
4458 }
4459
26fbb774
VS		 4460 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4461 port_name(intel_dig_port->port),
0e32b39c 4462 long_hpd ? "long" : "short");
13cf5504 4463
1c767b33
ID		 4464 power_domain = intel_display_port_power_domain(intel_encoder);
4465 intel_display_power_get(dev_priv, power_domain);
4466
0e32b39c 4467 if (long_hpd) {
2a592bec
DA		 4468
4469 if (HAS_PCH_SPLIT(dev)) {
4470 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4471 goto mst_fail;
4472 } else {
4473 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4474 goto mst_fail;
4475 }
0e32b39c
DA		 4476
4477 if (!intel_dp_get_dpcd(intel_dp)) {
4478 goto mst_fail;
4479 }
4480
4481 intel_dp_probe_oui(intel_dp);
4482
4483 if (!intel_dp_probe_mst(intel_dp))
4484 goto mst_fail;
4485
4486 } else {
4487 if (intel_dp->is_mst) {
1c767b33 4488 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4489 goto mst_fail;
4490 }
4491
4492 if (!intel_dp->is_mst) {
4493 /*
4494 * we'll check the link status via the normal hot plug path later -
4495 * but for short hpds we should check it now
4496 */
5b215bcf 4497 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4498 intel_dp_check_link_status(intel_dp);
5b215bcf 4499 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4500 }
4501 }
b2c5c181
DV		 4502
4503 ret = IRQ_HANDLED;
4504
1c767b33 4505 goto put_power;
0e32b39c
DA		 4506mst_fail:
4507 /* if we were in MST mode, and device is not there get out of MST mode */
4508 if (intel_dp->is_mst) {
4509 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4510 intel_dp->is_mst = false;
4511 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4512 }
1c767b33
ID		 4513put_power:
4514 intel_display_power_put(dev_priv, power_domain);
4515
4516 return ret;
13cf5504
DA		 4517}
4518
e3421a18
ZW		 4519/* Return which DP Port should be selected for Transcoder DP control */
4520int
0206e353 4521intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4522{
4523 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4524 struct intel_encoder *intel_encoder;
4525 struct intel_dp *intel_dp;
e3421a18 4526
fa90ecef
PZ		 4527 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4528 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4529
fa90ecef
PZ		 4530 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4531 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4532 return intel_dp->output_reg;
e3421a18 4533 }
ea5b213a 4534
e3421a18
ZW		 4535 return -1;
4536}
4537
36e83a18 4538/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4539bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4540{
4541 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4542 union child_device_config *p_child;
36e83a18 4543 int i;
5d8a7752
VS		 4544 static const short port_mapping[] = {
4545 [PORT_B] = PORT_IDPB,
4546 [PORT_C] = PORT_IDPC,
4547 [PORT_D] = PORT_IDPD,
4548 };
36e83a18 4549
3b32a35b
VS		 4550 if (port == PORT_A)
4551 return true;
4552
41aa3448 4553 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4554 return false;
4555
41aa3448
RV		 4556 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4557 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4558
5d8a7752 4559 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4560 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4561 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4562 return true;
4563 }
4564 return false;
4565}
4566
0e32b39c 4567void
f684960e
CW		 4568intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4569{
53b41837
YN		 4570 struct intel_connector *intel_connector = to_intel_connector(connector);
4571
3f43c48d 4572 intel_attach_force_audio_property(connector);
e953fd7b 4573 intel_attach_broadcast_rgb_property(connector);
55bc60db 4574 intel_dp->color_range_auto = true;
53b41837
YN		 4575
4576 if (is_edp(intel_dp)) {
4577 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4578 drm_object_attach_property(
4579 &connector->base,
53b41837 4580 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4581 DRM_MODE_SCALE_ASPECT);
4582 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4583 }
f684960e
CW		 4584}
4585
dada1a9f
ID		 4586static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4587{
4588 intel_dp->last_power_cycle = jiffies;
4589 intel_dp->last_power_on = jiffies;
4590 intel_dp->last_backlight_off = jiffies;
4591}
4592
67a54566
DV		 4593static void
4594intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4595 struct intel_dp *intel_dp)
67a54566
DV		 4596{
4597 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4598 struct edp_power_seq cur, vbt, spec,
4599 *final = &intel_dp->pps_delays;
67a54566 4600 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4601 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4602
e39b999a
VS		 4603 lockdep_assert_held(&dev_priv->pps_mutex);
4604
81ddbc69
VS		 4605 /* already initialized? */
4606 if (final->t11_t12 != 0)
4607 return;
4608
453c5420 4609 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4610 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4611 pp_on_reg = PCH_PP_ON_DELAYS;
4612 pp_off_reg = PCH_PP_OFF_DELAYS;
4613 pp_div_reg = PCH_PP_DIVISOR;
4614 } else {
bf13e81b
JN		 4615 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4616
4617 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4618 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4619 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4620 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4621 }
67a54566
DV		 4622
4623 /* Workaround: Need to write PP_CONTROL with the unlock key as
4624 * the very first thing. */
453c5420 4625 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4626 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4627
453c5420
JB		 4628 pp_on = I915_READ(pp_on_reg);
4629 pp_off = I915_READ(pp_off_reg);
4630 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4631
4632 /* Pull timing values out of registers */
4633 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4634 PANEL_POWER_UP_DELAY_SHIFT;
4635
4636 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4637 PANEL_LIGHT_ON_DELAY_SHIFT;
4638
4639 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4640 PANEL_LIGHT_OFF_DELAY_SHIFT;
4641
4642 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4643 PANEL_POWER_DOWN_DELAY_SHIFT;
4644
4645 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4646 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4647
4648 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4649 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4650
41aa3448 4651 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4652
4653 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4654 * our hw here, which are all in 100usec. */
4655 spec.t1_t3 = 210 * 10;
4656 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4657 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4658 spec.t10 = 500 * 10;
4659 /* This one is special and actually in units of 100ms, but zero
4660 * based in the hw (so we need to add 100 ms). But the sw vbt
4661 * table multiplies it with 1000 to make it in units of 100usec,
4662 * too. */
4663 spec.t11_t12 = (510 + 100) * 10;
4664
4665 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4666 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4667
4668 /* Use the max of the register settings and vbt. If both are
4669 * unset, fall back to the spec limits. */
36b5f425 4670#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4671 spec.field : \
4672 max(cur.field, vbt.field))
4673 assign_final(t1_t3);
4674 assign_final(t8);
4675 assign_final(t9);
4676 assign_final(t10);
4677 assign_final(t11_t12);
4678#undef assign_final
4679
36b5f425 4680#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4681 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4682 intel_dp->backlight_on_delay = get_delay(t8);
4683 intel_dp->backlight_off_delay = get_delay(t9);
4684 intel_dp->panel_power_down_delay = get_delay(t10);
4685 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4686#undef get_delay
4687
f30d26e4
JN		 4688 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4689 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4690 intel_dp->panel_power_cycle_delay);
4691
4692 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4693 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4694}
4695
4696static void
4697intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4698 struct intel_dp *intel_dp)
f30d26e4
JN		 4699{
4700 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4701 u32 pp_on, pp_off, pp_div, port_sel = 0;
4702 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4703 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4704 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4705 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4706
e39b999a 4707 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4708
4709 if (HAS_PCH_SPLIT(dev)) {
4710 pp_on_reg = PCH_PP_ON_DELAYS;
4711 pp_off_reg = PCH_PP_OFF_DELAYS;
4712 pp_div_reg = PCH_PP_DIVISOR;
4713 } else {
bf13e81b
JN		 4714 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4715
4716 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4717 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4718 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4719 }
4720
b2f19d1a
PZ		 4721 /*
4722 * And finally store the new values in the power sequencer. The
4723 * backlight delays are set to 1 because we do manual waits on them. For
4724 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4725 * we'll end up waiting for the backlight off delay twice: once when we
4726 * do the manual sleep, and once when we disable the panel and wait for
4727 * the PP_STATUS bit to become zero.
4728 */
f30d26e4 4729 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4730 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4731 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4732 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4733 /* Compute the divisor for the pp clock, simply match the Bspec
4734 * formula. */
453c5420 4735 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4736 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4737 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4738
4739 /* Haswell doesn't have any port selection bits for the panel
4740 * power sequencer any more. */
bc7d38a4 4741 if (IS_VALLEYVIEW(dev)) {
ad933b56 4742 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4743 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4744 if (port == PORT_A)
a24c144c 4745 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4746 else
a24c144c 4747 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4748 }
4749
453c5420
JB		 4750 pp_on |= port_sel;
4751
4752 I915_WRITE(pp_on_reg, pp_on);
4753 I915_WRITE(pp_off_reg, pp_off);
4754 I915_WRITE(pp_div_reg, pp_div);
67a54566 4755
67a54566 4756 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4757 I915_READ(pp_on_reg),
4758 I915_READ(pp_off_reg),
4759 I915_READ(pp_div_reg));
f684960e
CW		 4760}
4761
b33a2815
VK		 4762/**
4763 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4764 * @dev: DRM device
4765 * @refresh_rate: RR to be programmed
4766 *
4767 * This function gets called when refresh rate (RR) has to be changed from
4768 * one frequency to another. Switches can be between high and low RR
4769 * supported by the panel or to any other RR based on media playback (in
4770 * this case, RR value needs to be passed from user space).
4771 *
4772 * The caller of this function needs to take a lock on dev_priv->drrs.
4773 */
96178eeb 4774static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 4775{
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct intel_encoder *encoder;
96178eeb
VK		 4778 struct intel_digital_port *dig_port = NULL;
4779 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 4780 struct intel_crtc_state *config = NULL;
439d7ac0 4781 struct intel_crtc *intel_crtc = NULL;
439d7ac0 4782 u32 reg, val;
96178eeb 4783 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 4784
4785 if (refresh_rate <= 0) {
4786 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4787 return;
4788 }
4789
96178eeb
VK		 4790 if (intel_dp == NULL) {
4791 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 4792 return;
4793 }
4794
1fcc9d1c 4795 /*
e4d59f6b
RV		 4796 * FIXME: This needs proper synchronization with psr state for some
4797 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 4798 */
439d7ac0 4799
96178eeb
VK		 4800 dig_port = dp_to_dig_port(intel_dp);
4801 encoder = &dig_port->base;
439d7ac0
PB		 4802 intel_crtc = encoder->new_crtc;
4803
4804 if (!intel_crtc) {
4805 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4806 return;
4807 }
4808
6e3c9717 4809 config = intel_crtc->config;
439d7ac0 4810
96178eeb 4811 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 4812 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4813 return;
4814 }
4815
96178eeb
VK		 4816 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4817 refresh_rate)
439d7ac0
PB		 4818 index = DRRS_LOW_RR;
4819
96178eeb 4820 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 4821 DRM_DEBUG_KMS(
4822 "DRRS requested for previously set RR...ignoring\n");
4823 return;
4824 }
4825
4826 if (!intel_crtc->active) {
4827 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4828 return;
4829 }
4830
44395bfe 4831 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 4832 switch (index) {
4833 case DRRS_HIGH_RR:
4834 intel_dp_set_m_n(intel_crtc, M1_N1);
4835 break;
4836 case DRRS_LOW_RR:
4837 intel_dp_set_m_n(intel_crtc, M2_N2);
4838 break;
4839 case DRRS_MAX_RR:
4840 default:
4841 DRM_ERROR("Unsupported refreshrate type\n");
4842 }
4843 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 4844 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 4845 val = I915_READ(reg);
a4c30b1d 4846
439d7ac0 4847 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 4848 if (IS_VALLEYVIEW(dev))
4849 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4850 else
4851 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 4852 } else {
6fa7aec1
VK		 4853 if (IS_VALLEYVIEW(dev))
4854 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4855 else
4856 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 4857 }
4858 I915_WRITE(reg, val);
4859 }
4860
4e9ac947
VK		 4861 dev_priv->drrs.refresh_rate_type = index;
4862
4863 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4864}
4865
b33a2815
VK		 4866/**
4867 * intel_edp_drrs_enable - init drrs struct if supported
4868 * @intel_dp: DP struct
4869 *
4870 * Initializes frontbuffer_bits and drrs.dp
4871 */
c395578e
VK		 4872void intel_edp_drrs_enable(struct intel_dp *intel_dp)
4873{
4874 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4877 struct drm_crtc *crtc = dig_port->base.base.crtc;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879
4880 if (!intel_crtc->config->has_drrs) {
4881 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
4882 return;
4883 }
4884
4885 mutex_lock(&dev_priv->drrs.mutex);
4886 if (WARN_ON(dev_priv->drrs.dp)) {
4887 DRM_ERROR("DRRS already enabled\n");
4888 goto unlock;
4889 }
4890
4891 dev_priv->drrs.busy_frontbuffer_bits = 0;
4892
4893 dev_priv->drrs.dp = intel_dp;
4894
4895unlock:
4896 mutex_unlock(&dev_priv->drrs.mutex);
4897}
4898
b33a2815
VK		 4899/**
4900 * intel_edp_drrs_disable - Disable DRRS
4901 * @intel_dp: DP struct
4902 *
4903 */
c395578e
VK		 4904void intel_edp_drrs_disable(struct intel_dp *intel_dp)
4905{
4906 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4907 struct drm_i915_private *dev_priv = dev->dev_private;
4908 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4909 struct drm_crtc *crtc = dig_port->base.base.crtc;
4910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4911
4912 if (!intel_crtc->config->has_drrs)
4913 return;
4914
4915 mutex_lock(&dev_priv->drrs.mutex);
4916 if (!dev_priv->drrs.dp) {
4917 mutex_unlock(&dev_priv->drrs.mutex);
4918 return;
4919 }
4920
4921 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
4922 intel_dp_set_drrs_state(dev_priv->dev,
4923 intel_dp->attached_connector->panel.
4924 fixed_mode->vrefresh);
4925
4926 dev_priv->drrs.dp = NULL;
4927 mutex_unlock(&dev_priv->drrs.mutex);
4928
4929 cancel_delayed_work_sync(&dev_priv->drrs.work);
4930}
4931
4e9ac947
VK		 4932static void intel_edp_drrs_downclock_work(struct work_struct *work)
4933{
4934 struct drm_i915_private *dev_priv =
4935 container_of(work, typeof(*dev_priv), drrs.work.work);
4936 struct intel_dp *intel_dp;
4937
4938 mutex_lock(&dev_priv->drrs.mutex);
4939
4940 intel_dp = dev_priv->drrs.dp;
4941
4942 if (!intel_dp)
4943 goto unlock;
4944
439d7ac0 4945 /*
4e9ac947
VK		 4946 * The delayed work can race with an invalidate hence we need to
4947 * recheck.
439d7ac0
PB		 4948 */
4949
4e9ac947
VK		 4950 if (dev_priv->drrs.busy_frontbuffer_bits)
4951 goto unlock;
439d7ac0 4952
4e9ac947
VK		 4953 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
4954 intel_dp_set_drrs_state(dev_priv->dev,
4955 intel_dp->attached_connector->panel.
4956 downclock_mode->vrefresh);
439d7ac0 4957
4e9ac947 4958unlock:
439d7ac0 4959
4e9ac947 4960 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 4961}
4962
b33a2815
VK		 4963/**
4964 * intel_edp_drrs_invalidate - Invalidate DRRS
4965 * @dev: DRM device
4966 * @frontbuffer_bits: frontbuffer plane tracking bits
4967 *
4968 * When there is a disturbance on screen (due to cursor movement/time
4969 * update etc), DRRS needs to be invalidated, i.e. need to switch to
4970 * high RR.
4971 *
4972 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
4973 */
a93fad0f
VK		 4974void intel_edp_drrs_invalidate(struct drm_device *dev,
4975 unsigned frontbuffer_bits)
4976{
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978 struct drm_crtc *crtc;
4979 enum pipe pipe;
4980
4981 if (!dev_priv->drrs.dp)
4982 return;
4983
4984 mutex_lock(&dev_priv->drrs.mutex);
4985 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
4986 pipe = to_intel_crtc(crtc)->pipe;
4987
4988 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
4989 cancel_delayed_work_sync(&dev_priv->drrs.work);
4990 intel_dp_set_drrs_state(dev_priv->dev,
4991 dev_priv->drrs.dp->attached_connector->panel.
4992 fixed_mode->vrefresh);
4993 }
4994
4995 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
4996
4997 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
4998 mutex_unlock(&dev_priv->drrs.mutex);
4999}
5000
b33a2815
VK		 5001/**
5002 * intel_edp_drrs_flush - Flush DRRS
5003 * @dev: DRM device
5004 * @frontbuffer_bits: frontbuffer plane tracking bits
5005 *
5006 * When there is no movement on screen, DRRS work can be scheduled.
5007 * This DRRS work is responsible for setting relevant registers after a
5008 * timeout of 1 second.
5009 *
5010 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5011 */
a93fad0f
VK		 5012void intel_edp_drrs_flush(struct drm_device *dev,
5013 unsigned frontbuffer_bits)
5014{
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5016 struct drm_crtc *crtc;
5017 enum pipe pipe;
5018
5019 if (!dev_priv->drrs.dp)
5020 return;
5021
5022 mutex_lock(&dev_priv->drrs.mutex);
5023 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5024 pipe = to_intel_crtc(crtc)->pipe;
5025 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5026
5027 cancel_delayed_work_sync(&dev_priv->drrs.work);
5028
5029 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5030 !dev_priv->drrs.busy_frontbuffer_bits)
5031 schedule_delayed_work(&dev_priv->drrs.work,
5032 msecs_to_jiffies(1000));
5033 mutex_unlock(&dev_priv->drrs.mutex);
5034}
5035
b33a2815
VK		 5036/**
5037 * DOC: Display Refresh Rate Switching (DRRS)
5038 *
5039 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5040 * which enables swtching between low and high refresh rates,
5041 * dynamically, based on the usage scenario. This feature is applicable
5042 * for internal panels.
5043 *
5044 * Indication that the panel supports DRRS is given by the panel EDID, which
5045 * would list multiple refresh rates for one resolution.
5046 *
5047 * DRRS is of 2 types - static and seamless.
5048 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5049 * (may appear as a blink on screen) and is used in dock-undock scenario.
5050 * Seamless DRRS involves changing RR without any visual effect to the user
5051 * and can be used during normal system usage. This is done by programming
5052 * certain registers.
5053 *
5054 * Support for static/seamless DRRS may be indicated in the VBT based on
5055 * inputs from the panel spec.
5056 *
5057 * DRRS saves power by switching to low RR based on usage scenarios.
5058 *
5059 * eDP DRRS:-
5060 * The implementation is based on frontbuffer tracking implementation.
5061 * When there is a disturbance on the screen triggered by user activity or a
5062 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5063 * When there is no movement on screen, after a timeout of 1 second, a switch
5064 * to low RR is made.
5065 * For integration with frontbuffer tracking code,
5066 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5067 *
5068 * DRRS can be further extended to support other internal panels and also
5069 * the scenario of video playback wherein RR is set based on the rate
5070 * requested by userspace.
5071 */
5072
5073/**
5074 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5075 * @intel_connector: eDP connector
5076 * @fixed_mode: preferred mode of panel
5077 *
5078 * This function is called only once at driver load to initialize basic
5079 * DRRS stuff.
5080 *
5081 * Returns:
5082 * Downclock mode if panel supports it, else return NULL.
5083 * DRRS support is determined by the presence of downclock mode (apart
5084 * from VBT setting).
5085 */
4f9db5b5 5086static struct drm_display_mode *
96178eeb
VK		 5087intel_dp_drrs_init(struct intel_connector *intel_connector,
5088 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5089{
5090 struct drm_connector *connector = &intel_connector->base;
96178eeb 5091 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5092 struct drm_i915_private *dev_priv = dev->dev_private;
5093 struct drm_display_mode *downclock_mode = NULL;
5094
5095 if (INTEL_INFO(dev)->gen <= 6) {
5096 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5097 return NULL;
5098 }
5099
5100 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5101 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5102 return NULL;
5103 }
5104
5105 downclock_mode = intel_find_panel_downclock
5106 (dev, fixed_mode, connector);
5107
5108 if (!downclock_mode) {
a1d26342 5109 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5110 return NULL;
5111 }
5112
4e9ac947
VK		 5113 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5114
96178eeb 5115 mutex_init(&dev_priv->drrs.mutex);
439d7ac0 5116
96178eeb 5117 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5118
96178eeb 5119 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5120 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5121 return downclock_mode;
5122}
5123
ed92f0b2 5124static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5125 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5126{
5127 struct drm_connector *connector = &intel_connector->base;
5128 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5129 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5130 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5131 struct drm_i915_private *dev_priv = dev->dev_private;
5132 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5133 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5134 bool has_dpcd;
5135 struct drm_display_mode *scan;
5136 struct edid *edid;
6517d273 5137 enum pipe pipe = INVALID_PIPE;
ed92f0b2 5138
96178eeb 5139 dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
4f9db5b5 5140
ed92f0b2
PZ		 5141 if (!is_edp(intel_dp))
5142 return true;
5143
49e6bc51
VS		 5144 pps_lock(intel_dp);
5145 intel_edp_panel_vdd_sanitize(intel_dp);
5146 pps_unlock(intel_dp);
63635217 5147
ed92f0b2 5148 /* Cache DPCD and EDID for edp. */
ed92f0b2 5149 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5150
5151 if (has_dpcd) {
5152 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5153 dev_priv->no_aux_handshake =
5154 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5155 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5156 } else {
5157 /* if this fails, presume the device is a ghost */
5158 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5159 return false;
5160 }
5161
5162 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5163 pps_lock(intel_dp);
36b5f425 5164 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5165 pps_unlock(intel_dp);
ed92f0b2 5166
060c8778 5167 mutex_lock(&dev->mode_config.mutex);
0b99836f 5168 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5169 if (edid) {
5170 if (drm_add_edid_modes(connector, edid)) {
5171 drm_mode_connector_update_edid_property(connector,
5172 edid);
5173 drm_edid_to_eld(connector, edid);
5174 } else {
5175 kfree(edid);
5176 edid = ERR_PTR(-EINVAL);
5177 }
5178 } else {
5179 edid = ERR_PTR(-ENOENT);
5180 }
5181 intel_connector->edid = edid;
5182
5183 /* prefer fixed mode from EDID if available */
5184 list_for_each_entry(scan, &connector->probed_modes, head) {
5185 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5186 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5187 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5188 intel_connector, fixed_mode);
ed92f0b2
PZ		 5189 break;
5190 }
5191 }
5192
5193 /* fallback to VBT if available for eDP */
5194 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5195 fixed_mode = drm_mode_duplicate(dev,
5196 dev_priv->vbt.lfp_lvds_vbt_mode);
5197 if (fixed_mode)
5198 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5199 }
060c8778 5200 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5201
01527b31
CT		 5202 if (IS_VALLEYVIEW(dev)) {
5203 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5204 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5205
5206 /*
5207 * Figure out the current pipe for the initial backlight setup.
5208 * If the current pipe isn't valid, try the PPS pipe, and if that
5209 * fails just assume pipe A.
5210 */
5211 if (IS_CHERRYVIEW(dev))
5212 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5213 else
5214 pipe = PORT_TO_PIPE(intel_dp->DP);
5215
5216 if (pipe != PIPE_A && pipe != PIPE_B)
5217 pipe = intel_dp->pps_pipe;
5218
5219 if (pipe != PIPE_A && pipe != PIPE_B)
5220 pipe = PIPE_A;
5221
5222 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5223 pipe_name(pipe));
01527b31
CT		 5224 }
5225
4f9db5b5 5226 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5227 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5228 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5229
5230 return true;
5231}
5232
16c25533 5233bool
f0fec3f2
PZ		 5234intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5235 struct intel_connector *intel_connector)
a4fc5ed6 5236{
f0fec3f2
PZ		 5237 struct drm_connector *connector = &intel_connector->base;
5238 struct intel_dp *intel_dp = &intel_dig_port->dp;
5239 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5240 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5241 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5242 enum port port = intel_dig_port->port;
0b99836f 5243 int type;
a4fc5ed6 5244
a4a5d2f8
VS		 5245 intel_dp->pps_pipe = INVALID_PIPE;
5246
ec5b01dd 5247 /* intel_dp vfuncs */
b6b5e383
DL		 5248 if (INTEL_INFO(dev)->gen >= 9)
5249 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5250 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5251 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5252 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5253 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5254 else if (HAS_PCH_SPLIT(dev))
5255 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5256 else
5257 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5258
b9ca5fad
DL		 5259 if (INTEL_INFO(dev)->gen >= 9)
5260 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5261 else
5262 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5263
0767935e
DV		 5264 /* Preserve the current hw state. */
5265 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5266 intel_dp->attached_connector = intel_connector;
3d3dc149 5267
3b32a35b 5268 if (intel_dp_is_edp(dev, port))
b329530c 5269 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5270 else
5271 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5272
f7d24902
ID		 5273 /*
5274 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5275 * for DP the encoder type can be set by the caller to
5276 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5277 */
5278 if (type == DRM_MODE_CONNECTOR_eDP)
5279 intel_encoder->type = INTEL_OUTPUT_EDP;
5280
c17ed5b5
VS		 5281 /* eDP only on port B and/or C on vlv/chv */
5282 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5283 port != PORT_B && port != PORT_C))
5284 return false;
5285
e7281eab
ID		 5286 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5287 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5288 port_name(port));
5289
b329530c 5290 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5291 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5292
a4fc5ed6
KP		 5293 connector->interlace_allowed = true;
5294 connector->doublescan_allowed = 0;
5295
f0fec3f2 5296 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5297 edp_panel_vdd_work);
a4fc5ed6 5298
df0e9248 5299 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5300 drm_connector_register(connector);
a4fc5ed6 5301
affa9354 5302 if (HAS_DDI(dev))
bcbc889b
PZ		 5303 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5304 else
5305 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5306 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5307
0b99836f 5308 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5309 switch (port) {
5310 case PORT_A:
1d843f9d 5311 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5312 break;
5313 case PORT_B:
1d843f9d 5314 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5315 break;
5316 case PORT_C:
1d843f9d 5317 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5318 break;
5319 case PORT_D:
1d843f9d 5320 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5321 break;
5322 default:
ad1c0b19 5323 BUG();
5eb08b69
ZW		 5324 }
5325
dada1a9f 5326 if (is_edp(intel_dp)) {
773538e8 5327 pps_lock(intel_dp);
1e74a324
VS		 5328 intel_dp_init_panel_power_timestamps(intel_dp);
5329 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5330 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5331 else
36b5f425 5332 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5333 pps_unlock(intel_dp);
dada1a9f 5334 }
0095e6dc 5335
9d1a1031 5336 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5337
0e32b39c 5338 /* init MST on ports that can support it */
c86ea3d0 5339 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
0e32b39c 5340 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5341 intel_dp_mst_encoder_init(intel_dig_port,
5342 intel_connector->base.base.id);
0e32b39c
DA		 5343 }
5344 }
5345
36b5f425 5346 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5347 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5348 if (is_edp(intel_dp)) {
5349 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5350 /*
5351 * vdd might still be enabled do to the delayed vdd off.
5352 * Make sure vdd is actually turned off here.
5353 */
773538e8 5354 pps_lock(intel_dp);
4be73780 5355 edp_panel_vdd_off_sync(intel_dp);
773538e8 5356 pps_unlock(intel_dp);
15b1d171 5357 }
34ea3d38 5358 drm_connector_unregister(connector);
b2f246a8 5359 drm_connector_cleanup(connector);
16c25533 5360 return false;
b2f246a8 5361 }
32f9d658 5362
f684960e
CW		 5363 intel_dp_add_properties(intel_dp, connector);
5364
a4fc5ed6
KP		 5365 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5366 * 0xd. Failure to do so will result in spurious interrupts being
5367 * generated on the port when a cable is not attached.
5368 */
5369 if (IS_G4X(dev) && !IS_GM45(dev)) {
5370 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5371 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5372 }
16c25533
PZ		 5373
5374 return true;
a4fc5ed6 5375}
f0fec3f2
PZ		 5376
5377void
5378intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5379{
13cf5504 5380 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5381 struct intel_digital_port *intel_dig_port;
5382 struct intel_encoder *intel_encoder;
5383 struct drm_encoder *encoder;
5384 struct intel_connector *intel_connector;
5385
b14c5679 5386 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5387 if (!intel_dig_port)
5388 return;
5389
b14c5679 5390 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5391 if (!intel_connector) {
5392 kfree(intel_dig_port);
5393 return;
5394 }
5395
5396 intel_encoder = &intel_dig_port->base;
5397 encoder = &intel_encoder->base;
5398
5399 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5400 DRM_MODE_ENCODER_TMDS);
5401
5bfe2ac0 5402 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5403 intel_encoder->disable = intel_disable_dp;
00c09d70 5404 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5405 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5406 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5407 if (IS_CHERRYVIEW(dev)) {
9197c88b 5408 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5409 intel_encoder->pre_enable = chv_pre_enable_dp;
5410 intel_encoder->enable = vlv_enable_dp;
580d3811 5411 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5412 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5413 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5414 intel_encoder->pre_enable = vlv_pre_enable_dp;
5415 intel_encoder->enable = vlv_enable_dp;
49277c31 5416 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5417 } else {
ecff4f3b
JN		 5418 intel_encoder->pre_enable = g4x_pre_enable_dp;
5419 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5420 if (INTEL_INFO(dev)->gen >= 5)
5421 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5422 }
f0fec3f2 5423
174edf1f 5424 intel_dig_port->port = port;
f0fec3f2
PZ		 5425 intel_dig_port->dp.output_reg = output_reg;
5426
00c09d70 5427 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5428 if (IS_CHERRYVIEW(dev)) {
5429 if (port == PORT_D)
5430 intel_encoder->crtc_mask = 1 << 2;
5431 else
5432 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5433 } else {
5434 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5435 }
bc079e8b 5436 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5437 intel_encoder->hot_plug = intel_dp_hot_plug;
5438
13cf5504
DA		 5439 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5440 dev_priv->hpd_irq_port[port] = intel_dig_port;
5441
15b1d171
PZ		 5442 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5443 drm_encoder_cleanup(encoder);
5444 kfree(intel_dig_port);
b2f246a8 5445 kfree(intel_connector);
15b1d171 5446 }
f0fec3f2 5447}
0e32b39c
DA		 5448
5449void intel_dp_mst_suspend(struct drm_device *dev)
5450{
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 int i;
5453
5454 /* disable MST */
5455 for (i = 0; i < I915_MAX_PORTS; i++) {
5456 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5457 if (!intel_dig_port)
5458 continue;
5459
5460 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5461 if (!intel_dig_port->dp.can_mst)
5462 continue;
5463 if (intel_dig_port->dp.is_mst)
5464 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5465 }
5466 }
5467}
5468
5469void intel_dp_mst_resume(struct drm_device *dev)
5470{
5471 struct drm_i915_private *dev_priv = dev->dev_private;
5472 int i;
5473
5474 for (i = 0; i < I915_MAX_PORTS; i++) {
5475 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5476 if (!intel_dig_port)
5477 continue;
5478 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5479 int ret;
5480
5481 if (!intel_dig_port->dp.can_mst)
5482 continue;
5483
5484 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5485 if (ret != 0) {
5486 intel_dp_check_mst_status(&intel_dig_port->dp);
5487 }
5488 }
5489 }
5490}
Linux 6.x block layer and io_uring tree(s)