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drm/i915: transform INTEL_OUTPUT_* into an enum
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
5ca476f8 228pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a 335 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
bf13e81b 398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
bf13e81b
JN		 451 }
452
a4a5d2f8
VS		 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
bf13e81b
JN		 488}
489
490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
b6b5e383
DL		 664static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
665{
666 /*
667 * SKL doesn't need us to program the AUX clock divider (Hardware will
668 * derive the clock from CDCLK automatically). We still implement the
669 * get_aux_clock_divider vfunc to plug-in into the existing code.
670 */
671 return index ? 0 : 1;
672}
673
5ed12a19
DL		 674static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
675 bool has_aux_irq,
676 int send_bytes,
677 uint32_t aux_clock_divider)
678{
679 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
680 struct drm_device *dev = intel_dig_port->base.base.dev;
681 uint32_t precharge, timeout;
682
683 if (IS_GEN6(dev))
684 precharge = 3;
685 else
686 precharge = 5;
687
688 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
689 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
690 else
691 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
692
693 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 694 DP_AUX_CH_CTL_DONE |
5ed12a19 695 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 696 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 697 timeout |
788d4433 698 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 699 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
700 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 701 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 702}
703
b9ca5fad
DL		 704static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
705 bool has_aux_irq,
706 int send_bytes,
707 uint32_t unused)
708{
709 return DP_AUX_CH_CTL_SEND_BUSY |
710 DP_AUX_CH_CTL_DONE |
711 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
712 DP_AUX_CH_CTL_TIME_OUT_ERROR |
713 DP_AUX_CH_CTL_TIME_OUT_1600us |
714 DP_AUX_CH_CTL_RECEIVE_ERROR |
715 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
716 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
717}
718
b84a1cf8
RV		 719static int
720intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 721 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 722 uint8_t *recv, int recv_size)
723{
724 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
725 struct drm_device *dev = intel_dig_port->base.base.dev;
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
728 uint32_t ch_data = ch_ctl + 4;
bc86625a 729 uint32_t aux_clock_divider;
b84a1cf8
RV		 730 int i, ret, recv_bytes;
731 uint32_t status;
5ed12a19 732 int try, clock = 0;
4e6b788c 733 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 734 bool vdd;
735
773538e8 736 pps_lock(intel_dp);
e39b999a 737
72c3500a
VS		 738 /*
739 * We will be called with VDD already enabled for dpcd/edid/oui reads.
740 * In such cases we want to leave VDD enabled and it's up to upper layers
741 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
742 * ourselves.
743 */
1e0560e0 744 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 745
746 /* dp aux is extremely sensitive to irq latency, hence request the
747 * lowest possible wakeup latency and so prevent the cpu from going into
748 * deep sleep states.
749 */
750 pm_qos_update_request(&dev_priv->pm_qos, 0);
751
752 intel_dp_check_edp(intel_dp);
5eb08b69 753
c67a470b
PZ		 754 intel_aux_display_runtime_get(dev_priv);
755
11bee43e
JB		 756 /* Try to wait for any previous AUX channel activity */
757 for (try = 0; try < 3; try++) {
ef04f00d 758 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 759 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
760 break;
761 msleep(1);
762 }
763
764 if (try == 3) {
765 WARN(1, "dp_aux_ch not started status 0x%08x\n",
766 I915_READ(ch_ctl));
9ee32fea
DV		 767 ret = -EBUSY;
768 goto out;
4f7f7b7e
CW		 769 }
770
46a5ae9f
PZ		 771 /* Only 5 data registers! */
772 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
773 ret = -E2BIG;
774 goto out;
775 }
776
ec5b01dd 777 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 778 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
779 has_aux_irq,
780 send_bytes,
781 aux_clock_divider);
5ed12a19 782
bc86625a
CW		 783 /* Must try at least 3 times according to DP spec */
784 for (try = 0; try < 5; try++) {
785 /* Load the send data into the aux channel data registers */
786 for (i = 0; i < send_bytes; i += 4)
787 I915_WRITE(ch_data + i,
788 pack_aux(send + i, send_bytes - i));
789
790 /* Send the command and wait for it to complete */
5ed12a19 791 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 792
793 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
794
795 /* Clear done status and any errors */
796 I915_WRITE(ch_ctl,
797 status |
798 DP_AUX_CH_CTL_DONE |
799 DP_AUX_CH_CTL_TIME_OUT_ERROR |
800 DP_AUX_CH_CTL_RECEIVE_ERROR);
801
802 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
803 DP_AUX_CH_CTL_RECEIVE_ERROR))
804 continue;
805 if (status & DP_AUX_CH_CTL_DONE)
806 break;
807 }
4f7f7b7e 808 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 809 break;
810 }
811
a4fc5ed6 812 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 813 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 814 ret = -EBUSY;
815 goto out;
a4fc5ed6
KP		 816 }
817
818 /* Check for timeout or receive error.
819 * Timeouts occur when the sink is not connected
820 */
a5b3da54 821 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 822 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 823 ret = -EIO;
824 goto out;
a5b3da54 825 }
1ae8c0a5
KP		 826
827 /* Timeouts occur when the device isn't connected, so they're
828 * "normal" -- don't fill the kernel log with these */
a5b3da54 829 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 830 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 831 ret = -ETIMEDOUT;
832 goto out;
a4fc5ed6
KP		 833 }
834
835 /* Unload any bytes sent back from the other side */
836 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
837 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 838 if (recv_bytes > recv_size)
839 recv_bytes = recv_size;
0206e353 840
4f7f7b7e
CW		 841 for (i = 0; i < recv_bytes; i += 4)
842 unpack_aux(I915_READ(ch_data + i),
843 recv + i, recv_bytes - i);
a4fc5ed6 844
9ee32fea
DV		 845 ret = recv_bytes;
846out:
847 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 848 intel_aux_display_runtime_put(dev_priv);
9ee32fea 849
884f19e9
JN		 850 if (vdd)
851 edp_panel_vdd_off(intel_dp, false);
852
773538e8 853 pps_unlock(intel_dp);
e39b999a 854
9ee32fea 855 return ret;
a4fc5ed6
KP		 856}
857
a6c8aff0
JN		 858#define BARE_ADDRESS_SIZE 3
859#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 860static ssize_t
861intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 862{
9d1a1031
JN		 863 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
864 uint8_t txbuf[20], rxbuf[20];
865 size_t txsize, rxsize;
a4fc5ed6 866 int ret;
a4fc5ed6 867
9d1a1031
JN		 868 txbuf[0] = msg->request << 4;
869 txbuf[1] = msg->address >> 8;
870 txbuf[2] = msg->address & 0xff;
871 txbuf[3] = msg->size - 1;
46a5ae9f 872
9d1a1031
JN		 873 switch (msg->request & ~DP_AUX_I2C_MOT) {
874 case DP_AUX_NATIVE_WRITE:
875 case DP_AUX_I2C_WRITE:
a6c8aff0 876 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 877 rxsize = 1;
f51a44b9 878
9d1a1031
JN		 879 if (WARN_ON(txsize > 20))
880 return -E2BIG;
a4fc5ed6 881
9d1a1031 882 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 883
9d1a1031
JN		 884 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
885 if (ret > 0) {
886 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 887
9d1a1031
JN		 888 /* Return payload size. */
889 ret = msg->size;
890 }
891 break;
46a5ae9f 892
9d1a1031
JN		 893 case DP_AUX_NATIVE_READ:
894 case DP_AUX_I2C_READ:
a6c8aff0 895 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 896 rxsize = msg->size + 1;
a4fc5ed6 897
9d1a1031
JN		 898 if (WARN_ON(rxsize > 20))
899 return -E2BIG;
a4fc5ed6 900
9d1a1031
JN		 901 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
902 if (ret > 0) {
903 msg->reply = rxbuf[0] >> 4;
904 /*
905 * Assume happy day, and copy the data. The caller is
906 * expected to check msg->reply before touching it.
907 *
908 * Return payload size.
909 */
910 ret--;
911 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 912 }
9d1a1031
JN		 913 break;
914
915 default:
916 ret = -EINVAL;
917 break;
a4fc5ed6 918 }
f51a44b9 919
9d1a1031 920 return ret;
a4fc5ed6
KP		 921}
922
9d1a1031
JN		 923static void
924intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
925{
926 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
928 enum port port = intel_dig_port->port;
0b99836f 929 const char *name = NULL;
ab2c0672
DA		 930 int ret;
931
33ad6626
JN		 932 switch (port) {
933 case PORT_A:
934 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 935 name = "DPDDC-A";
ab2c0672 936 break;
33ad6626
JN		 937 case PORT_B:
938 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 939 name = "DPDDC-B";
ab2c0672 940 break;
33ad6626
JN		 941 case PORT_C:
942 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 943 name = "DPDDC-C";
ab2c0672 944 break;
33ad6626
JN		 945 case PORT_D:
946 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 947 name = "DPDDC-D";
33ad6626
JN		 948 break;
949 default:
950 BUG();
ab2c0672
DA		 951 }
952
1b1aad75
DL		 953 /*
954 * The AUX_CTL register is usually DP_CTL + 0x10.
955 *
956 * On Haswell and Broadwell though:
957 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
958 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
959 *
960 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
961 */
962 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 963 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 964
0b99836f 965 intel_dp->aux.name = name;
9d1a1031
JN		 966 intel_dp->aux.dev = dev->dev;
967 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 968
0b99836f
JN		 969 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
970 connector->base.kdev->kobj.name);
8316f337 971
4f71d0cb 972 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 973 if (ret < 0) {
4f71d0cb 974 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 975 name, ret);
976 return;
ab2c0672 977 }
8a5e6aeb 978
0b99836f
JN		 979 ret = sysfs_create_link(&connector->base.kdev->kobj,
980 &intel_dp->aux.ddc.dev.kobj,
981 intel_dp->aux.ddc.dev.kobj.name);
982 if (ret < 0) {
983 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 984 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 985 }
a4fc5ed6
KP		 986}
987
80f65de3
ID		 988static void
989intel_dp_connector_unregister(struct intel_connector *intel_connector)
990{
991 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
992
0e32b39c
DA		 993 if (!intel_connector->mst_port)
994 sysfs_remove_link(&intel_connector->base.kdev->kobj,
995 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 996 intel_connector_unregister(intel_connector);
997}
998
0e50338c
DV		 999static void
1000hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1001{
1002 switch (link_bw) {
1003 case DP_LINK_BW_1_62:
1004 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1005 break;
1006 case DP_LINK_BW_2_7:
1007 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1008 break;
1009 case DP_LINK_BW_5_4:
1010 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1011 break;
1012 }
1013}
1014
c6bb3538
DV		 1015static void
1016intel_dp_set_clock(struct intel_encoder *encoder,
1017 struct intel_crtc_config *pipe_config, int link_bw)
1018{
1019 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1020 const struct dp_link_dpll *divisor = NULL;
1021 int i, count = 0;
c6bb3538
DV		 1022
1023 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1024 divisor = gen4_dpll;
1025 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1026 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1027 divisor = pch_dpll;
1028 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1029 } else if (IS_CHERRYVIEW(dev)) {
1030 divisor = chv_dpll;
1031 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1032 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1033 divisor = vlv_dpll;
1034 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1035 }
9dd4ffdf
CML		 1036
1037 if (divisor && count) {
1038 for (i = 0; i < count; i++) {
1039 if (link_bw == divisor[i].link_bw) {
1040 pipe_config->dpll = divisor[i].dpll;
1041 pipe_config->clock_set = true;
1042 break;
1043 }
1044 }
c6bb3538
DV		 1045 }
1046}
1047
00c09d70 1048bool
5bfe2ac0
DV		 1049intel_dp_compute_config(struct intel_encoder *encoder,
1050 struct intel_crtc_config *pipe_config)
a4fc5ed6 1051{
5bfe2ac0 1052 struct drm_device *dev = encoder->base.dev;
36008365 1053 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1054 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1055 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1056 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1057 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1058 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1059 int lane_count, clock;
56071a20 1060 int min_lane_count = 1;
eeb6324d 1061 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1062 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1063 int min_clock = 0;
06ea66b6 1064 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1065 int bpp, mode_rate;
06ea66b6 1066 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1067 int link_avail, link_clock;
a4fc5ed6 1068
bc7d38a4 1069 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1070 pipe_config->has_pch_encoder = true;
1071
03afc4a2 1072 pipe_config->has_dp_encoder = true;
f769cd24 1073 pipe_config->has_drrs = false;
9ed109a7 1074 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1075
dd06f90e
JN		 1076 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1077 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1078 adjusted_mode);
2dd24552
JB		 1079 if (!HAS_PCH_SPLIT(dev))
1080 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1081 intel_connector->panel.fitting_mode);
1082 else
b074cec8
JB		 1083 intel_pch_panel_fitting(intel_crtc, pipe_config,
1084 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1085 }
1086
cb1793ce 1087 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1088 return false;
1089
083f9560
DV		 1090 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1091 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1092 max_lane_count, bws[max_clock],
1093 adjusted_mode->crtc_clock);
083f9560 1094
36008365
DV		 1095 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1096 * bpc in between. */
3e7ca985 1097 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1098 if (is_edp(intel_dp)) {
1099 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1100 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1101 dev_priv->vbt.edp_bpp);
1102 bpp = dev_priv->vbt.edp_bpp;
1103 }
1104
344c5bbc
JN		 1105 /*
1106 * Use the maximum clock and number of lanes the eDP panel
1107 * advertizes being capable of. The panels are generally
1108 * designed to support only a single clock and lane
1109 * configuration, and typically these values correspond to the
1110 * native resolution of the panel.
1111 */
1112 min_lane_count = max_lane_count;
1113 min_clock = max_clock;
7984211e 1114 }
657445fe 1115
36008365 1116 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1117 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1118 bpp);
36008365 1119
c6930992
DA		 1120 for (clock = min_clock; clock <= max_clock; clock++) {
1121 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1122 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1123 link_avail = intel_dp_max_data_rate(link_clock,
1124 lane_count);
1125
1126 if (mode_rate <= link_avail) {
1127 goto found;
1128 }
1129 }
1130 }
1131 }
c4867936 1132
36008365 1133 return false;
3685a8f3 1134
36008365 1135found:
55bc60db
VS		 1136 if (intel_dp->color_range_auto) {
1137 /*
1138 * See:
1139 * CEA-861-E - 5.1 Default Encoding Parameters
1140 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1141 */
18316c8c 1142 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1143 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1144 else
1145 intel_dp->color_range = 0;
1146 }
1147
3685a8f3 1148 if (intel_dp->color_range)
50f3b016 1149 pipe_config->limited_color_range = true;
a4fc5ed6 1150
36008365
DV		 1151 intel_dp->link_bw = bws[clock];
1152 intel_dp->lane_count = lane_count;
657445fe 1153 pipe_config->pipe_bpp = bpp;
ff9a6750 1154 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1155
36008365
DV		 1156 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1157 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1158 pipe_config->port_clock, bpp);
36008365
DV		 1159 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1160 mode_rate, link_avail);
a4fc5ed6 1161
03afc4a2 1162 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1163 adjusted_mode->crtc_clock,
1164 pipe_config->port_clock,
03afc4a2 1165 &pipe_config->dp_m_n);
9d1a455b 1166
439d7ac0
PB		 1167 if (intel_connector->panel.downclock_mode != NULL &&
1168 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1169 pipe_config->has_drrs = true;
439d7ac0
PB		 1170 intel_link_compute_m_n(bpp, lane_count,
1171 intel_connector->panel.downclock_mode->clock,
1172 pipe_config->port_clock,
1173 &pipe_config->dp_m2_n2);
1174 }
1175
ea155f32 1176 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1177 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1178 else
1179 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1180
03afc4a2 1181 return true;
a4fc5ed6
KP		 1182}
1183
7c62a164 1184static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1185{
7c62a164
DV		 1186 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1187 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1188 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190 u32 dpa_ctl;
1191
ff9a6750 1192 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1193 dpa_ctl = I915_READ(DP_A);
1194 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1195
ff9a6750 1196 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1197 /* For a long time we've carried around a ILK-DevA w/a for the
1198 * 160MHz clock. If we're really unlucky, it's still required.
1199 */
1200 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1201 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1202 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1203 } else {
1204 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1205 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1206 }
1ce17038 1207
ea9b6006
DV		 1208 I915_WRITE(DP_A, dpa_ctl);
1209
1210 POSTING_READ(DP_A);
1211 udelay(500);
1212}
1213
8ac33ed3 1214static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1215{
b934223d 1216 struct drm_device *dev = encoder->base.dev;
417e822d 1217 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1218 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1219 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1220 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1221 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1222
417e822d 1223 /*
1a2eb460 1224 * There are four kinds of DP registers:
417e822d
KP		 1225 *
1226 * IBX PCH
1a2eb460
KP		 1227 * SNB CPU
1228 * IVB CPU
417e822d
KP		 1229 * CPT PCH
1230 *
1231 * IBX PCH and CPU are the same for almost everything,
1232 * except that the CPU DP PLL is configured in this
1233 * register
1234 *
1235 * CPT PCH is quite different, having many bits moved
1236 * to the TRANS_DP_CTL register instead. That
1237 * configuration happens (oddly) in ironlake_pch_enable
1238 */
9c9e7927 1239
417e822d
KP		 1240 /* Preserve the BIOS-computed detected bit. This is
1241 * supposed to be read-only.
1242 */
1243 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1244
417e822d 1245 /* Handle DP bits in common between all three register formats */
417e822d 1246 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1247 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1248
9ed109a7 1249 if (crtc->config.has_audio) {
e0dac65e 1250 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1251 pipe_name(crtc->pipe));
ea5b213a 1252 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
33d1e7c6 1253 intel_write_eld(encoder);
e0dac65e 1254 }
247d89f6 1255
417e822d 1256 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1257
bc7d38a4 1258 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1259 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1260 intel_dp->DP |= DP_SYNC_HS_HIGH;
1261 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1262 intel_dp->DP |= DP_SYNC_VS_HIGH;
1263 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1264
6aba5b6c 1265 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1266 intel_dp->DP |= DP_ENHANCED_FRAMING;
1267
7c62a164 1268 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1269 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1270 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1271 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1272
1273 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1274 intel_dp->DP |= DP_SYNC_HS_HIGH;
1275 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1276 intel_dp->DP |= DP_SYNC_VS_HIGH;
1277 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1278
6aba5b6c 1279 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1280 intel_dp->DP |= DP_ENHANCED_FRAMING;
1281
44f37d1f
CML		 1282 if (!IS_CHERRYVIEW(dev)) {
1283 if (crtc->pipe == 1)
1284 intel_dp->DP |= DP_PIPEB_SELECT;
1285 } else {
1286 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1287 }
417e822d
KP		 1288 } else {
1289 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1290 }
a4fc5ed6
KP		 1291}
1292
ffd6749d
PZ		 1293#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1294#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1295
1a5ef5b7
PZ		 1296#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1297#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1298
ffd6749d
PZ		 1299#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1300#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1301
4be73780 1302static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1303 u32 mask,
1304 u32 value)
bd943159 1305{
30add22d 1306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1307 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1308 u32 pp_stat_reg, pp_ctrl_reg;
1309
e39b999a
VS		 1310 lockdep_assert_held(&dev_priv->pps_mutex);
1311
bf13e81b
JN		 1312 pp_stat_reg = _pp_stat_reg(intel_dp);
1313 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1314
99ea7127 1315 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1316 mask, value,
1317 I915_READ(pp_stat_reg),
1318 I915_READ(pp_ctrl_reg));
32ce697c 1319
453c5420 1320 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1321 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1322 I915_READ(pp_stat_reg),
1323 I915_READ(pp_ctrl_reg));
32ce697c 1324 }
54c136d4
CW		 1325
1326 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1327}
32ce697c 1328
4be73780 1329static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1330{
1331 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1332 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1333}
1334
4be73780 1335static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1336{
1337 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1338 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1339}
1340
4be73780 1341static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1342{
1343 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1344
1345 /* When we disable the VDD override bit last we have to do the manual
1346 * wait. */
1347 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1348 intel_dp->panel_power_cycle_delay);
1349
4be73780 1350 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1351}
1352
4be73780 1353static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1354{
1355 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1356 intel_dp->backlight_on_delay);
1357}
1358
4be73780 1359static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1360{
1361 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1362 intel_dp->backlight_off_delay);
1363}
99ea7127 1364
832dd3c1
KP		 1365/* Read the current pp_control value, unlocking the register if it
1366 * is locked
1367 */
1368
453c5420 1369static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1370{
453c5420
JB		 1371 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1372 struct drm_i915_private *dev_priv = dev->dev_private;
1373 u32 control;
832dd3c1 1374
e39b999a
VS		 1375 lockdep_assert_held(&dev_priv->pps_mutex);
1376
bf13e81b 1377 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1378 control &= ~PANEL_UNLOCK_MASK;
1379 control |= PANEL_UNLOCK_REGS;
1380 return control;
bd943159
KP		 1381}
1382
951468f3
VS		 1383/*
1384 * Must be paired with edp_panel_vdd_off().
1385 * Must hold pps_mutex around the whole on/off sequence.
1386 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1387 */
1e0560e0 1388static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1389{
30add22d 1390 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1391 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1392 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1393 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1394 enum intel_display_power_domain power_domain;
5d613501 1395 u32 pp;
453c5420 1396 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1397 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1398
e39b999a
VS		 1399 lockdep_assert_held(&dev_priv->pps_mutex);
1400
97af61f5 1401 if (!is_edp(intel_dp))
adddaaf4 1402 return false;
bd943159
KP		 1403
1404 intel_dp->want_panel_vdd = true;
99ea7127 1405
4be73780 1406 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1407 return need_to_disable;
b0665d57 1408
4e6e1a54
ID		 1409 power_domain = intel_display_port_power_domain(intel_encoder);
1410 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1411
b0665d57 1412 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1413
4be73780
DV		 1414 if (!edp_have_panel_power(intel_dp))
1415 wait_panel_power_cycle(intel_dp);
99ea7127 1416
453c5420 1417 pp = ironlake_get_pp_control(intel_dp);
5d613501 1418 pp |= EDP_FORCE_VDD;
ebf33b18 1419
bf13e81b
JN		 1420 pp_stat_reg = _pp_stat_reg(intel_dp);
1421 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1422
1423 I915_WRITE(pp_ctrl_reg, pp);
1424 POSTING_READ(pp_ctrl_reg);
1425 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1426 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1427 /*
1428 * If the panel wasn't on, delay before accessing aux channel
1429 */
4be73780 1430 if (!edp_have_panel_power(intel_dp)) {
bd943159 1431 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1432 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1433 }
adddaaf4
JN		 1434
1435 return need_to_disable;
1436}
1437
951468f3
VS		 1438/*
1439 * Must be paired with intel_edp_panel_vdd_off() or
1440 * intel_edp_panel_off().
1441 * Nested calls to these functions are not allowed since
1442 * we drop the lock. Caller must use some higher level
1443 * locking to prevent nested calls from other threads.
1444 */
b80d6c78 1445void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1446{
c695b6b6 1447 bool vdd;
adddaaf4 1448
c695b6b6
VS		 1449 if (!is_edp(intel_dp))
1450 return;
1451
773538e8 1452 pps_lock(intel_dp);
c695b6b6 1453 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1454 pps_unlock(intel_dp);
c695b6b6
VS		 1455
1456 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1457}
1458
4be73780 1459static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1460{
30add22d 1461 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1462 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1463 struct intel_digital_port *intel_dig_port =
1464 dp_to_dig_port(intel_dp);
1465 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1466 enum intel_display_power_domain power_domain;
5d613501 1467 u32 pp;
453c5420 1468 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1469
e39b999a 1470 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1471
15e899a0 1472 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1473
15e899a0 1474 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1475 return;
b0665d57 1476
be2c9196 1477 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1478
be2c9196
VS		 1479 pp = ironlake_get_pp_control(intel_dp);
1480 pp &= ~EDP_FORCE_VDD;
453c5420 1481
be2c9196
VS		 1482 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1483 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1484
be2c9196
VS		 1485 I915_WRITE(pp_ctrl_reg, pp);
1486 POSTING_READ(pp_ctrl_reg);
90791a5c 1487
be2c9196
VS		 1488 /* Make sure sequencer is idle before allowing subsequent activity */
1489 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1490 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1491
be2c9196
VS		 1492 if ((pp & POWER_TARGET_ON) == 0)
1493 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1494
be2c9196
VS		 1495 power_domain = intel_display_port_power_domain(intel_encoder);
1496 intel_display_power_put(dev_priv, power_domain);
bd943159 1497}
5d613501 1498
4be73780 1499static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1500{
1501 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1502 struct intel_dp, panel_vdd_work);
bd943159 1503
773538e8 1504 pps_lock(intel_dp);
15e899a0
VS		 1505 if (!intel_dp->want_panel_vdd)
1506 edp_panel_vdd_off_sync(intel_dp);
773538e8 1507 pps_unlock(intel_dp);
bd943159
KP		 1508}
1509
aba86890
ID		 1510static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1511{
1512 unsigned long delay;
1513
1514 /*
1515 * Queue the timer to fire a long time from now (relative to the power
1516 * down delay) to keep the panel power up across a sequence of
1517 * operations.
1518 */
1519 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1520 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1521}
1522
951468f3
VS		 1523/*
1524 * Must be paired with edp_panel_vdd_on().
1525 * Must hold pps_mutex around the whole on/off sequence.
1526 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1527 */
4be73780 1528static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1529{
e39b999a
VS		 1530 struct drm_i915_private *dev_priv =
1531 intel_dp_to_dev(intel_dp)->dev_private;
1532
1533 lockdep_assert_held(&dev_priv->pps_mutex);
1534
97af61f5
KP		 1535 if (!is_edp(intel_dp))
1536 return;
5d613501 1537
bd943159 1538 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1539
bd943159
KP		 1540 intel_dp->want_panel_vdd = false;
1541
aba86890 1542 if (sync)
4be73780 1543 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1544 else
1545 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1546}
1547
951468f3
VS		 1548/*
1549 * Must be paired with intel_edp_panel_vdd_on().
1550 * Nested calls to these functions are not allowed since
1551 * we drop the lock. Caller must use some higher level
1552 * locking to prevent nested calls from other threads.
1553 */
1e0560e0
VS		 1554static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1555{
e39b999a
VS		 1556 if (!is_edp(intel_dp))
1557 return;
1558
773538e8 1559 pps_lock(intel_dp);
1e0560e0 1560 edp_panel_vdd_off(intel_dp, sync);
773538e8 1561 pps_unlock(intel_dp);
1e0560e0
VS		 1562}
1563
4be73780 1564void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1565{
30add22d 1566 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1567 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1568 u32 pp;
453c5420 1569 u32 pp_ctrl_reg;
9934c132 1570
97af61f5 1571 if (!is_edp(intel_dp))
bd943159 1572 return;
99ea7127
KP		 1573
1574 DRM_DEBUG_KMS("Turn eDP power on\n");
1575
773538e8 1576 pps_lock(intel_dp);
e39b999a 1577
4be73780 1578 if (edp_have_panel_power(intel_dp)) {
99ea7127 1579 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1580 goto out;
99ea7127 1581 }
9934c132 1582
4be73780 1583 wait_panel_power_cycle(intel_dp);
37c6c9b0 1584
bf13e81b 1585 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1586 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1587 if (IS_GEN5(dev)) {
1588 /* ILK workaround: disable reset around power sequence */
1589 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1590 I915_WRITE(pp_ctrl_reg, pp);
1591 POSTING_READ(pp_ctrl_reg);
05ce1a49 1592 }
37c6c9b0 1593
1c0ae80a 1594 pp |= POWER_TARGET_ON;
99ea7127
KP		 1595 if (!IS_GEN5(dev))
1596 pp |= PANEL_POWER_RESET;
1597
453c5420
JB		 1598 I915_WRITE(pp_ctrl_reg, pp);
1599 POSTING_READ(pp_ctrl_reg);
9934c132 1600
4be73780 1601 wait_panel_on(intel_dp);
dce56b3c 1602 intel_dp->last_power_on = jiffies;
9934c132 1603
05ce1a49
KP		 1604 if (IS_GEN5(dev)) {
1605 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1606 I915_WRITE(pp_ctrl_reg, pp);
1607 POSTING_READ(pp_ctrl_reg);
05ce1a49 1608 }
e39b999a
VS		 1609
1610 out:
773538e8 1611 pps_unlock(intel_dp);
9934c132
JB		 1612}
1613
4be73780 1614void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1615{
4e6e1a54
ID		 1616 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1617 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1618 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1619 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1620 enum intel_display_power_domain power_domain;
99ea7127 1621 u32 pp;
453c5420 1622 u32 pp_ctrl_reg;
9934c132 1623
97af61f5
KP		 1624 if (!is_edp(intel_dp))
1625 return;
37c6c9b0 1626
99ea7127 1627 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1628
773538e8 1629 pps_lock(intel_dp);
e39b999a 1630
24f3e092
JN		 1631 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1632
453c5420 1633 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1634 /* We need to switch off panel power _and_ force vdd, for otherwise some
1635 * panels get very unhappy and cease to work. */
b3064154
PJ		 1636 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1637 EDP_BLC_ENABLE);
453c5420 1638
bf13e81b 1639 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1640
849e39f5
PZ		 1641 intel_dp->want_panel_vdd = false;
1642
453c5420
JB		 1643 I915_WRITE(pp_ctrl_reg, pp);
1644 POSTING_READ(pp_ctrl_reg);
9934c132 1645
dce56b3c 1646 intel_dp->last_power_cycle = jiffies;
4be73780 1647 wait_panel_off(intel_dp);
849e39f5
PZ		 1648
1649 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1650 power_domain = intel_display_port_power_domain(intel_encoder);
1651 intel_display_power_put(dev_priv, power_domain);
e39b999a 1652
773538e8 1653 pps_unlock(intel_dp);
9934c132
JB		 1654}
1655
1250d107
JN		 1656/* Enable backlight in the panel power control. */
1657static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1658{
da63a9f2
PZ		 1659 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1660 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 u32 pp;
453c5420 1663 u32 pp_ctrl_reg;
32f9d658 1664
01cb9ea6
JB		 1665 /*
1666 * If we enable the backlight right away following a panel power
1667 * on, we may see slight flicker as the panel syncs with the eDP
1668 * link. So delay a bit to make sure the image is solid before
1669 * allowing it to appear.
1670 */
4be73780 1671 wait_backlight_on(intel_dp);
e39b999a 1672
773538e8 1673 pps_lock(intel_dp);
e39b999a 1674
453c5420 1675 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1676 pp |= EDP_BLC_ENABLE;
453c5420 1677
bf13e81b 1678 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1679
1680 I915_WRITE(pp_ctrl_reg, pp);
1681 POSTING_READ(pp_ctrl_reg);
e39b999a 1682
773538e8 1683 pps_unlock(intel_dp);
32f9d658
ZW		 1684}
1685
1250d107
JN		 1686/* Enable backlight PWM and backlight PP control. */
1687void intel_edp_backlight_on(struct intel_dp *intel_dp)
1688{
1689 if (!is_edp(intel_dp))
1690 return;
1691
1692 DRM_DEBUG_KMS("\n");
1693
1694 intel_panel_enable_backlight(intel_dp->attached_connector);
1695 _intel_edp_backlight_on(intel_dp);
1696}
1697
1698/* Disable backlight in the panel power control. */
1699static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1700{
30add22d 1701 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1702 struct drm_i915_private *dev_priv = dev->dev_private;
1703 u32 pp;
453c5420 1704 u32 pp_ctrl_reg;
32f9d658 1705
f01eca2e
KP		 1706 if (!is_edp(intel_dp))
1707 return;
1708
773538e8 1709 pps_lock(intel_dp);
e39b999a 1710
453c5420 1711 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1712 pp &= ~EDP_BLC_ENABLE;
453c5420 1713
bf13e81b 1714 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1715
1716 I915_WRITE(pp_ctrl_reg, pp);
1717 POSTING_READ(pp_ctrl_reg);
f7d2323c 1718
773538e8 1719 pps_unlock(intel_dp);
e39b999a
VS		 1720
1721 intel_dp->last_backlight_off = jiffies;
f7d2323c 1722 edp_wait_backlight_off(intel_dp);
1250d107 1723}
f7d2323c 1724
1250d107
JN		 1725/* Disable backlight PP control and backlight PWM. */
1726void intel_edp_backlight_off(struct intel_dp *intel_dp)
1727{
1728 if (!is_edp(intel_dp))
1729 return;
1730
1731 DRM_DEBUG_KMS("\n");
f7d2323c 1732
1250d107 1733 _intel_edp_backlight_off(intel_dp);
f7d2323c 1734 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1735}
a4fc5ed6 1736
73580fb7
JN		 1737/*
1738 * Hook for controlling the panel power control backlight through the bl_power
1739 * sysfs attribute. Take care to handle multiple calls.
1740 */
1741static void intel_edp_backlight_power(struct intel_connector *connector,
1742 bool enable)
1743{
1744 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1745 bool is_enabled;
1746
773538e8 1747 pps_lock(intel_dp);
e39b999a 1748 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1749 pps_unlock(intel_dp);
73580fb7
JN		 1750
1751 if (is_enabled == enable)
1752 return;
1753
23ba9373
JN		 1754 DRM_DEBUG_KMS("panel power control backlight %s\n",
1755 enable ? "enable" : "disable");
73580fb7
JN		 1756
1757 if (enable)
1758 _intel_edp_backlight_on(intel_dp);
1759 else
1760 _intel_edp_backlight_off(intel_dp);
1761}
1762
2bd2ad64 1763static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1764{
da63a9f2
PZ		 1765 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1766 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1767 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 u32 dpa_ctl;
1770
2bd2ad64
DV		 1771 assert_pipe_disabled(dev_priv,
1772 to_intel_crtc(crtc)->pipe);
1773
d240f20f
JB		 1774 DRM_DEBUG_KMS("\n");
1775 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1776 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1777 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1778
1779 /* We don't adjust intel_dp->DP while tearing down the link, to
1780 * facilitate link retraining (e.g. after hotplug). Hence clear all
1781 * enable bits here to ensure that we don't enable too much. */
1782 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1783 intel_dp->DP |= DP_PLL_ENABLE;
1784 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1785 POSTING_READ(DP_A);
1786 udelay(200);
d240f20f
JB		 1787}
1788
2bd2ad64 1789static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1790{
da63a9f2
PZ		 1791 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1792 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1793 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1794 struct drm_i915_private *dev_priv = dev->dev_private;
1795 u32 dpa_ctl;
1796
2bd2ad64
DV		 1797 assert_pipe_disabled(dev_priv,
1798 to_intel_crtc(crtc)->pipe);
1799
d240f20f 1800 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1801 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1802 "dp pll off, should be on\n");
1803 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1804
1805 /* We can't rely on the value tracked for the DP register in
1806 * intel_dp->DP because link_down must not change that (otherwise link
1807 * re-training will fail. */
298b0b39 1808 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1809 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1810 POSTING_READ(DP_A);
d240f20f
JB		 1811 udelay(200);
1812}
1813
c7ad3810 1814/* If the sink supports it, try to set the power state appropriately */
c19b0669 1815void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1816{
1817 int ret, i;
1818
1819 /* Should have a valid DPCD by this point */
1820 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1821 return;
1822
1823 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1824 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1825 DP_SET_POWER_D3);
c7ad3810
JB		 1826 } else {
1827 /*
1828 * When turning on, we need to retry for 1ms to give the sink
1829 * time to wake up.
1830 */
1831 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1832 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1833 DP_SET_POWER_D0);
c7ad3810
JB		 1834 if (ret == 1)
1835 break;
1836 msleep(1);
1837 }
1838 }
f9cac721
JN		 1839
1840 if (ret != 1)
1841 DRM_DEBUG_KMS("failed to %s sink power state\n",
1842 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1843}
1844
19d8fe15
DV		 1845static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1846 enum pipe *pipe)
d240f20f 1847{
19d8fe15 1848 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1849 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1850 struct drm_device *dev = encoder->base.dev;
1851 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1852 enum intel_display_power_domain power_domain;
1853 u32 tmp;
1854
1855 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1856 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1857 return false;
1858
1859 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1860
1861 if (!(tmp & DP_PORT_EN))
1862 return false;
1863
bc7d38a4 1864 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1865 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1866 } else if (IS_CHERRYVIEW(dev)) {
1867 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1868 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1869 *pipe = PORT_TO_PIPE(tmp);
1870 } else {
1871 u32 trans_sel;
1872 u32 trans_dp;
1873 int i;
1874
1875 switch (intel_dp->output_reg) {
1876 case PCH_DP_B:
1877 trans_sel = TRANS_DP_PORT_SEL_B;
1878 break;
1879 case PCH_DP_C:
1880 trans_sel = TRANS_DP_PORT_SEL_C;
1881 break;
1882 case PCH_DP_D:
1883 trans_sel = TRANS_DP_PORT_SEL_D;
1884 break;
1885 default:
1886 return true;
1887 }
1888
055e393f 1889 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1890 trans_dp = I915_READ(TRANS_DP_CTL(i));
1891 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1892 *pipe = i;
1893 return true;
1894 }
1895 }
19d8fe15 1896
4a0833ec
DV		 1897 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1898 intel_dp->output_reg);
1899 }
d240f20f 1900
19d8fe15
DV		 1901 return true;
1902}
d240f20f 1903
045ac3b5
JB		 1904static void intel_dp_get_config(struct intel_encoder *encoder,
1905 struct intel_crtc_config *pipe_config)
1906{
1907 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1908 u32 tmp, flags = 0;
63000ef6
XZ		 1909 struct drm_device *dev = encoder->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 enum port port = dp_to_dig_port(intel_dp)->port;
1912 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1913 int dotclock;
045ac3b5 1914
9ed109a7
DV		 1915 tmp = I915_READ(intel_dp->output_reg);
1916 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1917 pipe_config->has_audio = true;
1918
63000ef6 1919 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1920 if (tmp & DP_SYNC_HS_HIGH)
1921 flags |= DRM_MODE_FLAG_PHSYNC;
1922 else
1923 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1924
63000ef6
XZ		 1925 if (tmp & DP_SYNC_VS_HIGH)
1926 flags |= DRM_MODE_FLAG_PVSYNC;
1927 else
1928 flags |= DRM_MODE_FLAG_NVSYNC;
1929 } else {
1930 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1931 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1932 flags |= DRM_MODE_FLAG_PHSYNC;
1933 else
1934 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1935
63000ef6
XZ		 1936 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1937 flags |= DRM_MODE_FLAG_PVSYNC;
1938 else
1939 flags |= DRM_MODE_FLAG_NVSYNC;
1940 }
045ac3b5
JB		 1941
1942 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1943
8c875fca
VS		 1944 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1945 tmp & DP_COLOR_RANGE_16_235)
1946 pipe_config->limited_color_range = true;
1947
eb14cb74
VS		 1948 pipe_config->has_dp_encoder = true;
1949
1950 intel_dp_get_m_n(crtc, pipe_config);
1951
18442d08 1952 if (port == PORT_A) {
f1f644dc
JB		 1953 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1954 pipe_config->port_clock = 162000;
1955 else
1956 pipe_config->port_clock = 270000;
1957 }
18442d08
VS		 1958
1959 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1960 &pipe_config->dp_m_n);
1961
1962 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1963 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1964
241bfc38 1965 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1966
c6cd2ee2
JN		 1967 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1968 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1969 /*
1970 * This is a big fat ugly hack.
1971 *
1972 * Some machines in UEFI boot mode provide us a VBT that has 18
1973 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1974 * unknown we fail to light up. Yet the same BIOS boots up with
1975 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1976 * max, not what it tells us to use.
1977 *
1978 * Note: This will still be broken if the eDP panel is not lit
1979 * up by the BIOS, and thus we can't get the mode at module
1980 * load.
1981 */
1982 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1983 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1984 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1985 }
045ac3b5
JB		 1986}
1987
34eb7579 1988static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1989{
34eb7579 1990 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1991}
1992
2b28bb1b
RV		 1993static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1994{
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996
18b5992c 1997 if (!HAS_PSR(dev))
2b28bb1b
RV		 1998 return false;
1999
18b5992c 2000 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 2001}
2002
2003static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2004 struct edp_vsc_psr *vsc_psr)
2005{
2006 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2007 struct drm_device *dev = dig_port->base.base.dev;
2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2010 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2011 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2012 uint32_t *data = (uint32_t *) vsc_psr;
2013 unsigned int i;
2014
2015 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2016 the video DIP being updated before program video DIP data buffer
2017 registers for DIP being updated. */
2018 I915_WRITE(ctl_reg, 0);
2019 POSTING_READ(ctl_reg);
2020
2021 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2022 if (i < sizeof(struct edp_vsc_psr))
2023 I915_WRITE(data_reg + i, *data++);
2024 else
2025 I915_WRITE(data_reg + i, 0);
2026 }
2027
2028 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2029 POSTING_READ(ctl_reg);
2030}
2031
ba80f4d4 2032static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2033{
2b28bb1b
RV		 2034 struct edp_vsc_psr psr_vsc;
2035
2b28bb1b
RV		 2036 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2037 memset(&psr_vsc, 0, sizeof(psr_vsc));
2038 psr_vsc.sdp_header.HB0 = 0;
2039 psr_vsc.sdp_header.HB1 = 0x7;
2040 psr_vsc.sdp_header.HB2 = 0x2;
2041 psr_vsc.sdp_header.HB3 = 0x8;
2042 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2043}
2044
2045static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2046{
0e0ae652
RV		 2047 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2048 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2049 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2050 uint32_t aux_clock_divider;
2b28bb1b 2051 int precharge = 0x3;
0e0ae652 2052 bool only_standby = false;
5ca476f8
VS		 2053 static const uint8_t aux_msg[] = {
2054 [0] = DP_AUX_NATIVE_WRITE << 4,
2055 [1] = DP_SET_POWER >> 8,
2056 [2] = DP_SET_POWER & 0xff,
2057 [3] = 1 - 1,
2058 [4] = DP_SET_POWER_D0,
2059 };
2060 int i;
2061
2062 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2063
ec5b01dd
DL		 2064 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2065
0e0ae652
RV		 2066 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2067 only_standby = true;
2068
2b28bb1b 2069 /* Enable PSR in sink */
0e0ae652 2070 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2071 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2072 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2073 else
9d1a1031
JN		 2074 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2075 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2076
2077 /* Setup AUX registers */
5ca476f8
VS		 2078 for (i = 0; i < sizeof(aux_msg); i += 4)
2079 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2080 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2081
18b5992c 2082 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2083 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2084 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2085 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2086 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2087}
2088
2089static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2090{
0e0ae652
RV		 2091 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2092 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2093 struct drm_i915_private *dev_priv = dev->dev_private;
2094 uint32_t max_sleep_time = 0x1f;
2095 uint32_t idle_frames = 1;
2096 uint32_t val = 0x0;
ed8546ac 2097 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2098 bool only_standby = false;
2099
2100 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2101 only_standby = true;
2b28bb1b 2102
0e0ae652 2103 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2104 val |= EDP_PSR_LINK_STANDBY;
2105 val |= EDP_PSR_TP2_TP3_TIME_0us;
2106 val |= EDP_PSR_TP1_TIME_0us;
2107 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2108 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2109 } else
2110 val |= EDP_PSR_LINK_DISABLE;
2111
18b5992c 2112 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2113 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2114 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2115 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2116 EDP_PSR_ENABLE);
2117}
2118
3f51e471
RV		 2119static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2120{
2121 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2122 struct drm_device *dev = dig_port->base.base.dev;
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 struct drm_crtc *crtc = dig_port->base.base.crtc;
2125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2126
f0355c4a 2127 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2128 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2129 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2130
a031d709
RV		 2131 dev_priv->psr.source_ok = false;
2132
9ca15301 2133 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2134 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2135 return false;
2136 }
2137
d330a953 2138 if (!i915.enable_psr) {
105b7c11 2139 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2140 return false;
2141 }
2142
4c8c7000
RV		 2143 /* Below limitations aren't valid for Broadwell */
2144 if (IS_BROADWELL(dev))
2145 goto out;
2146
3f51e471
RV		 2147 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2148 S3D_ENABLE) {
2149 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2150 return false;
2151 }
2152
ca73b4f0 2153 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2154 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2155 return false;
2156 }
2157
4c8c7000 2158 out:
a031d709 2159 dev_priv->psr.source_ok = true;
3f51e471
RV		 2160 return true;
2161}
2162
3d739d92 2163static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2164{
7c8f8a70
RV		 2165 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2166 struct drm_device *dev = intel_dig_port->base.base.dev;
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2168
3638379c
DV		 2169 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2170 WARN_ON(dev_priv->psr.active);
f0355c4a 2171 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2172
7ca5a41f 2173 /* Enable/Re-enable PSR on the host */
2b28bb1b 2174 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2175
7c8f8a70 2176 dev_priv->psr.active = true;
2b28bb1b
RV		 2177}
2178
3d739d92
RV		 2179void intel_edp_psr_enable(struct intel_dp *intel_dp)
2180{
2181 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2182 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2183
4704c573
RV		 2184 if (!HAS_PSR(dev)) {
2185 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2186 return;
2187 }
2188
34eb7579
RV		 2189 if (!is_edp_psr(intel_dp)) {
2190 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2191 return;
2192 }
2193
f0355c4a 2194 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2195 if (dev_priv->psr.enabled) {
2196 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2197 goto unlock;
109fc2ad
DV		 2198 }
2199
0aa48783
RV		 2200 if (!intel_edp_psr_match_conditions(intel_dp))
2201 goto unlock;
2202
9ca15301
DV		 2203 dev_priv->psr.busy_frontbuffer_bits = 0;
2204
ba80f4d4 2205 intel_edp_psr_setup_vsc(intel_dp);
16487254 2206
ba80f4d4
RV		 2207 /* Avoid continuous PSR exit by masking memup and hpd */
2208 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2209 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2210
7ca5a41f
RV		 2211 /* Enable PSR on the panel */
2212 intel_edp_psr_enable_sink(intel_dp);
2213
0aa48783
RV		 2214 dev_priv->psr.enabled = intel_dp;
2215unlock:
f0355c4a 2216 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2217}
2218
2b28bb1b
RV		 2219void intel_edp_psr_disable(struct intel_dp *intel_dp)
2220{
2221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2222 struct drm_i915_private *dev_priv = dev->dev_private;
2223
f0355c4a
DV		 2224 mutex_lock(&dev_priv->psr.lock);
2225 if (!dev_priv->psr.enabled) {
2226 mutex_unlock(&dev_priv->psr.lock);
2227 return;
2228 }
2229
3638379c
DV		 2230 if (dev_priv->psr.active) {
2231 I915_WRITE(EDP_PSR_CTL(dev),
2232 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2233
2234 /* Wait till PSR is idle */
2235 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2236 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2237 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2238
3638379c
DV		 2239 dev_priv->psr.active = false;
2240 } else {
2241 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2242 }
7c8f8a70 2243
2807cf69 2244 dev_priv->psr.enabled = NULL;
f0355c4a 2245 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2246
2247 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2248}
2249
f02a326e 2250static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2251{
2252 struct drm_i915_private *dev_priv =
2253 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2254 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2255
8d7f4fe9
RV		 2256 /* We have to make sure PSR is ready for re-enable
2257 * otherwise it keeps disabled until next full enable/disable cycle.
2258 * PSR might take some time to get fully disabled
2259 * and be ready for re-enable.
2260 */
2261 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2262 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2263 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2264 return;
2265 }
2266
f0355c4a
DV		 2267 mutex_lock(&dev_priv->psr.lock);
2268 intel_dp = dev_priv->psr.enabled;
2269
2807cf69 2270 if (!intel_dp)
f0355c4a 2271 goto unlock;
2807cf69 2272
9ca15301
DV		 2273 /*
2274 * The delayed work can race with an invalidate hence we need to
2275 * recheck. Since psr_flush first clears this and then reschedules we
2276 * won't ever miss a flush when bailing out here.
2277 */
2278 if (dev_priv->psr.busy_frontbuffer_bits)
2279 goto unlock;
2280
2281 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2282unlock:
2283 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2284}
2285
9ca15301 2286static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2287{
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2289
3638379c
DV		 2290 if (dev_priv->psr.active) {
2291 u32 val = I915_READ(EDP_PSR_CTL(dev));
2292
2293 WARN_ON(!(val & EDP_PSR_ENABLE));
2294
2295 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2296
2297 dev_priv->psr.active = false;
2298 }
7c8f8a70 2299
9ca15301
DV		 2300}
2301
2302void intel_edp_psr_invalidate(struct drm_device *dev,
2303 unsigned frontbuffer_bits)
2304{
2305 struct drm_i915_private *dev_priv = dev->dev_private;
2306 struct drm_crtc *crtc;
2307 enum pipe pipe;
2308
9ca15301
DV		 2309 mutex_lock(&dev_priv->psr.lock);
2310 if (!dev_priv->psr.enabled) {
2311 mutex_unlock(&dev_priv->psr.lock);
2312 return;
2313 }
2314
2315 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2316 pipe = to_intel_crtc(crtc)->pipe;
2317
2318 intel_edp_psr_do_exit(dev);
2319
2320 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2321
2322 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2323 mutex_unlock(&dev_priv->psr.lock);
2324}
2325
2326void intel_edp_psr_flush(struct drm_device *dev,
2327 unsigned frontbuffer_bits)
2328{
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 struct drm_crtc *crtc;
2331 enum pipe pipe;
2332
9ca15301
DV		 2333 mutex_lock(&dev_priv->psr.lock);
2334 if (!dev_priv->psr.enabled) {
2335 mutex_unlock(&dev_priv->psr.lock);
2336 return;
2337 }
2338
2339 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2340 pipe = to_intel_crtc(crtc)->pipe;
2341 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2342
2343 /*
2344 * On Haswell sprite plane updates don't result in a psr invalidating
2345 * signal in the hardware. Which means we need to manually fake this in
2346 * software for all flushes, not just when we've seen a preceding
2347 * invalidation through frontbuffer rendering.
2348 */
2349 if (IS_HASWELL(dev) &&
2350 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2351 intel_edp_psr_do_exit(dev);
2352
2353 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2354 schedule_delayed_work(&dev_priv->psr.work,
2355 msecs_to_jiffies(100));
f0355c4a 2356 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2357}
2358
2359void intel_edp_psr_init(struct drm_device *dev)
2360{
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362
7c8f8a70 2363 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2364 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2365}
2366
e8cb4558 2367static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2368{
e8cb4558 2369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2370 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2371
2372 /* Make sure the panel is off before trying to change the mode. But also
2373 * ensure that we have vdd while we switch off the panel. */
24f3e092 2374 intel_edp_panel_vdd_on(intel_dp);
4be73780 2375 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2376 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2377 intel_edp_panel_off(intel_dp);
3739850b 2378
08aff3fe
VS		 2379 /* disable the port before the pipe on g4x */
2380 if (INTEL_INFO(dev)->gen < 5)
3739850b 2381 intel_dp_link_down(intel_dp);
d240f20f
JB		 2382}
2383
08aff3fe 2384static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2385{
2bd2ad64 2386 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2387 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2388
49277c31 2389 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2390 if (port == PORT_A)
2391 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2392}
2393
2394static void vlv_post_disable_dp(struct intel_encoder *encoder)
2395{
2396 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2397
2398 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2399}
2400
580d3811
VS		 2401static void chv_post_disable_dp(struct intel_encoder *encoder)
2402{
2403 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2404 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2405 struct drm_device *dev = encoder->base.dev;
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 struct intel_crtc *intel_crtc =
2408 to_intel_crtc(encoder->base.crtc);
2409 enum dpio_channel ch = vlv_dport_to_channel(dport);
2410 enum pipe pipe = intel_crtc->pipe;
2411 u32 val;
2412
2413 intel_dp_link_down(intel_dp);
2414
2415 mutex_lock(&dev_priv->dpio_lock);
2416
2417 /* Propagate soft reset to data lane reset */
97fd4d5c 2418 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2419 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2420 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2421
97fd4d5c
VS		 2422 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2423 val |= CHV_PCS_REQ_SOFTRESET_EN;
2424 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2425
2426 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2427 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2428 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2429
2430 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2431 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2432 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2433
2434 mutex_unlock(&dev_priv->dpio_lock);
2435}
2436
7b13b58a
VS		 2437static void
2438_intel_dp_set_link_train(struct intel_dp *intel_dp,
2439 uint32_t *DP,
2440 uint8_t dp_train_pat)
2441{
2442 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2443 struct drm_device *dev = intel_dig_port->base.base.dev;
2444 struct drm_i915_private *dev_priv = dev->dev_private;
2445 enum port port = intel_dig_port->port;
2446
2447 if (HAS_DDI(dev)) {
2448 uint32_t temp = I915_READ(DP_TP_CTL(port));
2449
2450 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2451 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2452 else
2453 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2454
2455 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2456 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2457 case DP_TRAINING_PATTERN_DISABLE:
2458 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2459
2460 break;
2461 case DP_TRAINING_PATTERN_1:
2462 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2463 break;
2464 case DP_TRAINING_PATTERN_2:
2465 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2466 break;
2467 case DP_TRAINING_PATTERN_3:
2468 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2469 break;
2470 }
2471 I915_WRITE(DP_TP_CTL(port), temp);
2472
2473 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2474 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2475
2476 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2477 case DP_TRAINING_PATTERN_DISABLE:
2478 *DP |= DP_LINK_TRAIN_OFF_CPT;
2479 break;
2480 case DP_TRAINING_PATTERN_1:
2481 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2482 break;
2483 case DP_TRAINING_PATTERN_2:
2484 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2485 break;
2486 case DP_TRAINING_PATTERN_3:
2487 DRM_ERROR("DP training pattern 3 not supported\n");
2488 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2489 break;
2490 }
2491
2492 } else {
2493 if (IS_CHERRYVIEW(dev))
2494 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2495 else
2496 *DP &= ~DP_LINK_TRAIN_MASK;
2497
2498 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2499 case DP_TRAINING_PATTERN_DISABLE:
2500 *DP |= DP_LINK_TRAIN_OFF;
2501 break;
2502 case DP_TRAINING_PATTERN_1:
2503 *DP |= DP_LINK_TRAIN_PAT_1;
2504 break;
2505 case DP_TRAINING_PATTERN_2:
2506 *DP |= DP_LINK_TRAIN_PAT_2;
2507 break;
2508 case DP_TRAINING_PATTERN_3:
2509 if (IS_CHERRYVIEW(dev)) {
2510 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2511 } else {
2512 DRM_ERROR("DP training pattern 3 not supported\n");
2513 *DP |= DP_LINK_TRAIN_PAT_2;
2514 }
2515 break;
2516 }
2517 }
2518}
2519
2520static void intel_dp_enable_port(struct intel_dp *intel_dp)
2521{
2522 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524
2525 intel_dp->DP |= DP_PORT_EN;
2526
2527 /* enable with pattern 1 (as per spec) */
2528 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2529 DP_TRAINING_PATTERN_1);
2530
2531 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2532 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2533}
2534
e8cb4558 2535static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2536{
e8cb4558
DV		 2537 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2538 struct drm_device *dev = encoder->base.dev;
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2541
0c33d8d7
DV		 2542 if (WARN_ON(dp_reg & DP_PORT_EN))
2543 return;
5d613501 2544
7b13b58a 2545 intel_dp_enable_port(intel_dp);
24f3e092 2546 intel_edp_panel_vdd_on(intel_dp);
4be73780 2547 intel_edp_panel_on(intel_dp);
1e0560e0 2548 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2549 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2550 intel_dp_start_link_train(intel_dp);
33a34e4e 2551 intel_dp_complete_link_train(intel_dp);
3ab9c637 2552 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2553}
89b667f8 2554
ecff4f3b
JN		 2555static void g4x_enable_dp(struct intel_encoder *encoder)
2556{
828f5c6e
JN		 2557 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2558
ecff4f3b 2559 intel_enable_dp(encoder);
4be73780 2560 intel_edp_backlight_on(intel_dp);
ab1f90f9 2561}
89b667f8 2562
ab1f90f9
JN		 2563static void vlv_enable_dp(struct intel_encoder *encoder)
2564{
828f5c6e
JN		 2565 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2566
4be73780 2567 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2568}
2569
ecff4f3b 2570static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2571{
2572 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2573 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2574
8ac33ed3
DV		 2575 intel_dp_prepare(encoder);
2576
d41f1efb
DV		 2577 /* Only ilk+ has port A */
2578 if (dport->port == PORT_A) {
2579 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2580 ironlake_edp_pll_on(intel_dp);
d41f1efb 2581 }
ab1f90f9
JN		 2582}
2583
a4a5d2f8
VS		 2584static void vlv_steal_power_sequencer(struct drm_device *dev,
2585 enum pipe pipe)
2586{
2587 struct drm_i915_private *dev_priv = dev->dev_private;
2588 struct intel_encoder *encoder;
2589
2590 lockdep_assert_held(&dev_priv->pps_mutex);
2591
2592 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2593 base.head) {
2594 struct intel_dp *intel_dp;
773538e8 2595 enum port port;
a4a5d2f8
VS		 2596
2597 if (encoder->type != INTEL_OUTPUT_EDP)
2598 continue;
2599
2600 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2601 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2602
2603 if (intel_dp->pps_pipe != pipe)
2604 continue;
2605
2606 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2607 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2608
2609 /* make sure vdd is off before we steal it */
2610 edp_panel_vdd_off_sync(intel_dp);
2611
2612 intel_dp->pps_pipe = INVALID_PIPE;
2613 }
2614}
2615
2616static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2617{
2618 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2619 struct intel_encoder *encoder = &intel_dig_port->base;
2620 struct drm_device *dev = encoder->base.dev;
2621 struct drm_i915_private *dev_priv = dev->dev_private;
2622 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2623 struct edp_power_seq power_seq;
2624
2625 lockdep_assert_held(&dev_priv->pps_mutex);
2626
2627 if (intel_dp->pps_pipe == crtc->pipe)
2628 return;
2629
2630 /*
2631 * If another power sequencer was being used on this
2632 * port previously make sure to turn off vdd there while
2633 * we still have control of it.
2634 */
2635 if (intel_dp->pps_pipe != INVALID_PIPE)
2636 edp_panel_vdd_off_sync(intel_dp);
2637
2638 /*
2639 * We may be stealing the power
2640 * sequencer from another port.
2641 */
2642 vlv_steal_power_sequencer(dev, crtc->pipe);
2643
2644 /* now it's all ours */
2645 intel_dp->pps_pipe = crtc->pipe;
2646
2647 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2648 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2649
2650 /* init power sequencer on this pipe and port */
2651 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2652 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2653 &power_seq);
2654}
2655
ab1f90f9 2656static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2657{
2bd2ad64 2658 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2659 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2660 struct drm_device *dev = encoder->base.dev;
89b667f8 2661 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2662 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2663 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2664 int pipe = intel_crtc->pipe;
2665 u32 val;
a4fc5ed6 2666
ab1f90f9 2667 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2668
ab3c759a 2669 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2670 val = 0;
2671 if (pipe)
2672 val |= (1<<21);
2673 else
2674 val &= ~(1<<21);
2675 val |= 0x001000c4;
ab3c759a
CML		 2676 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2677 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2678 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2679
ab1f90f9
JN		 2680 mutex_unlock(&dev_priv->dpio_lock);
2681
2cac613b 2682 if (is_edp(intel_dp)) {
773538e8 2683 pps_lock(intel_dp);
a4a5d2f8 2684 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2685 pps_unlock(intel_dp);
2cac613b 2686 }
bf13e81b 2687
ab1f90f9
JN		 2688 intel_enable_dp(encoder);
2689
e4607fcf 2690 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2691}
2692
ecff4f3b 2693static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2694{
2695 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2696 struct drm_device *dev = encoder->base.dev;
2697 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2698 struct intel_crtc *intel_crtc =
2699 to_intel_crtc(encoder->base.crtc);
e4607fcf 2700 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2701 int pipe = intel_crtc->pipe;
89b667f8 2702
8ac33ed3
DV		 2703 intel_dp_prepare(encoder);
2704
89b667f8 2705 /* Program Tx lane resets to default */
0980a60f 2706 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2707 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2708 DPIO_PCS_TX_LANE2_RESET |
2709 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2710 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2711 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2712 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2713 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2714 DPIO_PCS_CLK_SOFT_RESET);
2715
2716 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2717 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2718 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2719 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2720 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2721}
2722
e4a1d846
CML		 2723static void chv_pre_enable_dp(struct intel_encoder *encoder)
2724{
2725 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2726 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2727 struct drm_device *dev = encoder->base.dev;
2728 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2729 struct intel_crtc *intel_crtc =
2730 to_intel_crtc(encoder->base.crtc);
2731 enum dpio_channel ch = vlv_dport_to_channel(dport);
2732 int pipe = intel_crtc->pipe;
2733 int data, i;
949c1d43 2734 u32 val;
e4a1d846 2735
e4a1d846 2736 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2737
570e2a74
VS		 2738 /* allow hardware to manage TX FIFO reset source */
2739 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2740 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2741 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2742
2743 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2744 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2745 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2746
949c1d43 2747 /* Deassert soft data lane reset*/
97fd4d5c 2748 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2749 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2750 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2751
2752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2753 val |= CHV_PCS_REQ_SOFTRESET_EN;
2754 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2755
2756 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2757 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2758 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2759
97fd4d5c 2760 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2761 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2762 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2763
2764 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2765 for (i = 0; i < 4; i++) {
2766 /* Set the latency optimal bit */
2767 data = (i == 1) ? 0x0 : 0x6;
2768 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2769 data << DPIO_FRC_LATENCY_SHFIT);
2770
2771 /* Set the upar bit */
2772 data = (i == 1) ? 0x0 : 0x1;
2773 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2774 data << DPIO_UPAR_SHIFT);
2775 }
2776
2777 /* Data lane stagger programming */
2778 /* FIXME: Fix up value only after power analysis */
2779
2780 mutex_unlock(&dev_priv->dpio_lock);
2781
2782 if (is_edp(intel_dp)) {
773538e8 2783 pps_lock(intel_dp);
a4a5d2f8 2784 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2785 pps_unlock(intel_dp);
e4a1d846
CML		 2786 }
2787
2788 intel_enable_dp(encoder);
2789
2790 vlv_wait_port_ready(dev_priv, dport);
2791}
2792
9197c88b
VS		 2793static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2794{
2795 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2796 struct drm_device *dev = encoder->base.dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 struct intel_crtc *intel_crtc =
2799 to_intel_crtc(encoder->base.crtc);
2800 enum dpio_channel ch = vlv_dport_to_channel(dport);
2801 enum pipe pipe = intel_crtc->pipe;
2802 u32 val;
2803
625695f8
VS		 2804 intel_dp_prepare(encoder);
2805
9197c88b
VS		 2806 mutex_lock(&dev_priv->dpio_lock);
2807
b9e5ac3c
VS		 2808 /* program left/right clock distribution */
2809 if (pipe != PIPE_B) {
2810 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2811 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2812 if (ch == DPIO_CH0)
2813 val |= CHV_BUFLEFTENA1_FORCE;
2814 if (ch == DPIO_CH1)
2815 val |= CHV_BUFRIGHTENA1_FORCE;
2816 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2817 } else {
2818 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2819 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2820 if (ch == DPIO_CH0)
2821 val |= CHV_BUFLEFTENA2_FORCE;
2822 if (ch == DPIO_CH1)
2823 val |= CHV_BUFRIGHTENA2_FORCE;
2824 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2825 }
2826
9197c88b
VS		 2827 /* program clock channel usage */
2828 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2829 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2830 if (pipe != PIPE_B)
2831 val &= ~CHV_PCS_USEDCLKCHANNEL;
2832 else
2833 val |= CHV_PCS_USEDCLKCHANNEL;
2834 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2835
2836 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2837 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2838 if (pipe != PIPE_B)
2839 val &= ~CHV_PCS_USEDCLKCHANNEL;
2840 else
2841 val |= CHV_PCS_USEDCLKCHANNEL;
2842 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2843
2844 /*
2845 * This a a bit weird since generally CL
2846 * matches the pipe, but here we need to
2847 * pick the CL based on the port.
2848 */
2849 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2850 if (pipe != PIPE_B)
2851 val &= ~CHV_CMN_USEDCLKCHANNEL;
2852 else
2853 val |= CHV_CMN_USEDCLKCHANNEL;
2854 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2855
2856 mutex_unlock(&dev_priv->dpio_lock);
2857}
2858
a4fc5ed6 2859/*
df0c237d
JB		 2860 * Native read with retry for link status and receiver capability reads for
2861 * cases where the sink may still be asleep.
9d1a1031
JN		 2862 *
2863 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2864 * supposed to retry 3 times per the spec.
a4fc5ed6 2865 */
9d1a1031
JN		 2866static ssize_t
2867intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2868 void *buffer, size_t size)
a4fc5ed6 2869{
9d1a1031
JN		 2870 ssize_t ret;
2871 int i;
61da5fab 2872
61da5fab 2873 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2874 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2875 if (ret == size)
2876 return ret;
61da5fab
JB		 2877 msleep(1);
2878 }
a4fc5ed6 2879
9d1a1031 2880 return ret;
a4fc5ed6
KP		 2881}
2882
2883/*
2884 * Fetch AUX CH registers 0x202 - 0x207 which contain
2885 * link status information
2886 */
2887static bool
93f62dad 2888intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2889{
9d1a1031
JN		 2890 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2891 DP_LANE0_1_STATUS,
2892 link_status,
2893 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2894}
2895
1100244e 2896/* These are source-specific values. */
a4fc5ed6 2897static uint8_t
1a2eb460 2898intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2899{
30add22d 2900 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2901 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2902
5a9d1f1a
DL		 2903 if (INTEL_INFO(dev)->gen >= 9)
2904 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2905 else if (IS_VALLEYVIEW(dev))
bd60018a 2906 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2907 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2908 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2909 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2910 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2911 else
bd60018a 2912 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2913}
2914
2915static uint8_t
2916intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2917{
30add22d 2918 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2919 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2920
5a9d1f1a
DL		 2921 if (INTEL_INFO(dev)->gen >= 9) {
2922 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2923 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2924 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2926 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2928 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2929 default:
2930 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2931 }
2932 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2933 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2935 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2936 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2937 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2939 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2941 default:
bd60018a 2942 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2943 }
e2fa6fba
P		 2944 } else if (IS_VALLEYVIEW(dev)) {
2945 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2949 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2951 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2953 default:
bd60018a 2954 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2955 }
bc7d38a4 2956 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2957 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2962 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2963 default:
bd60018a 2964 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2965 }
2966 } else {
2967 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2969 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2973 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2975 default:
bd60018a 2976 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2977 }
a4fc5ed6
KP		 2978 }
2979}
2980
e2fa6fba
P		 2981static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2982{
2983 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2984 struct drm_i915_private *dev_priv = dev->dev_private;
2985 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2986 struct intel_crtc *intel_crtc =
2987 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2988 unsigned long demph_reg_value, preemph_reg_value,
2989 uniqtranscale_reg_value;
2990 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2991 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2992 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2993
2994 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2995 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2996 preemph_reg_value = 0x0004000;
2997 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2998 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2999 demph_reg_value = 0x2B405555;
3000 uniqtranscale_reg_value = 0x552AB83A;
3001 break;
bd60018a 3002 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3003 demph_reg_value = 0x2B404040;
3004 uniqtranscale_reg_value = 0x5548B83A;
3005 break;
bd60018a 3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3007 demph_reg_value = 0x2B245555;
3008 uniqtranscale_reg_value = 0x5560B83A;
3009 break;
bd60018a 3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3011 demph_reg_value = 0x2B405555;
3012 uniqtranscale_reg_value = 0x5598DA3A;
3013 break;
3014 default:
3015 return 0;
3016 }
3017 break;
bd60018a 3018 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3019 preemph_reg_value = 0x0002000;
3020 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3022 demph_reg_value = 0x2B404040;
3023 uniqtranscale_reg_value = 0x5552B83A;
3024 break;
bd60018a 3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3026 demph_reg_value = 0x2B404848;
3027 uniqtranscale_reg_value = 0x5580B83A;
3028 break;
bd60018a 3029 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3030 demph_reg_value = 0x2B404040;
3031 uniqtranscale_reg_value = 0x55ADDA3A;
3032 break;
3033 default:
3034 return 0;
3035 }
3036 break;
bd60018a 3037 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3038 preemph_reg_value = 0x0000000;
3039 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3041 demph_reg_value = 0x2B305555;
3042 uniqtranscale_reg_value = 0x5570B83A;
3043 break;
bd60018a 3044 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3045 demph_reg_value = 0x2B2B4040;
3046 uniqtranscale_reg_value = 0x55ADDA3A;
3047 break;
3048 default:
3049 return 0;
3050 }
3051 break;
bd60018a 3052 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3053 preemph_reg_value = 0x0006000;
3054 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3056 demph_reg_value = 0x1B405555;
3057 uniqtranscale_reg_value = 0x55ADDA3A;
3058 break;
3059 default:
3060 return 0;
3061 }
3062 break;
3063 default:
3064 return 0;
3065 }
3066
0980a60f 3067 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3068 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3069 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3070 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3071 uniqtranscale_reg_value);
ab3c759a
CML		 3072 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3073 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3074 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3075 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3076 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3077
3078 return 0;
3079}
3080
e4a1d846
CML		 3081static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3082{
3083 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3086 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3087 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3088 uint8_t train_set = intel_dp->train_set[0];
3089 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3090 enum pipe pipe = intel_crtc->pipe;
3091 int i;
e4a1d846
CML		 3092
3093 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3094 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3095 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3097 deemph_reg_value = 128;
3098 margin_reg_value = 52;
3099 break;
bd60018a 3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3101 deemph_reg_value = 128;
3102 margin_reg_value = 77;
3103 break;
bd60018a 3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3105 deemph_reg_value = 128;
3106 margin_reg_value = 102;
3107 break;
bd60018a 3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3109 deemph_reg_value = 128;
3110 margin_reg_value = 154;
3111 /* FIXME extra to set for 1200 */
3112 break;
3113 default:
3114 return 0;
3115 }
3116 break;
bd60018a 3117 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3118 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3120 deemph_reg_value = 85;
3121 margin_reg_value = 78;
3122 break;
bd60018a 3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3124 deemph_reg_value = 85;
3125 margin_reg_value = 116;
3126 break;
bd60018a 3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3128 deemph_reg_value = 85;
3129 margin_reg_value = 154;
3130 break;
3131 default:
3132 return 0;
3133 }
3134 break;
bd60018a 3135 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3136 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3138 deemph_reg_value = 64;
3139 margin_reg_value = 104;
3140 break;
bd60018a 3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3142 deemph_reg_value = 64;
3143 margin_reg_value = 154;
3144 break;
3145 default:
3146 return 0;
3147 }
3148 break;
bd60018a 3149 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3150 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3151 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3152 deemph_reg_value = 43;
3153 margin_reg_value = 154;
3154 break;
3155 default:
3156 return 0;
3157 }
3158 break;
3159 default:
3160 return 0;
3161 }
3162
3163 mutex_lock(&dev_priv->dpio_lock);
3164
3165 /* Clear calc init */
1966e59e
VS		 3166 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3167 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3168 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3169 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3170 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3171
3172 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3173 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3174 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3175 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3176 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3177
a02ef3c7
VS		 3178 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3179 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3180 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3181 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3182
3183 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3184 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3185 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3186 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3187
e4a1d846 3188 /* Program swing deemph */
f72df8db
VS		 3189 for (i = 0; i < 4; i++) {
3190 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3191 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3192 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3193 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3194 }
e4a1d846
CML		 3195
3196 /* Program swing margin */
f72df8db
VS		 3197 for (i = 0; i < 4; i++) {
3198 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3199 val &= ~DPIO_SWING_MARGIN000_MASK;
3200 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3201 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3202 }
e4a1d846
CML		 3203
3204 /* Disable unique transition scale */
f72df8db
VS		 3205 for (i = 0; i < 4; i++) {
3206 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3207 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3208 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3209 }
e4a1d846
CML		 3210
3211 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3212 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3213 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3214 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3215
3216 /*
3217 * The document said it needs to set bit 27 for ch0 and bit 26
3218 * for ch1. Might be a typo in the doc.
3219 * For now, for this unique transition scale selection, set bit
3220 * 27 for ch0 and ch1.
3221 */
f72df8db
VS		 3222 for (i = 0; i < 4; i++) {
3223 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3224 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3225 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3226 }
e4a1d846 3227
f72df8db
VS		 3228 for (i = 0; i < 4; i++) {
3229 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3230 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3231 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3232 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3233 }
e4a1d846
CML		 3234 }
3235
3236 /* Start swing calculation */
1966e59e
VS		 3237 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3238 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3239 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3240
3241 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3242 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3243 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3244
3245 /* LRC Bypass */
3246 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3247 val |= DPIO_LRC_BYPASS;
3248 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3249
3250 mutex_unlock(&dev_priv->dpio_lock);
3251
3252 return 0;
3253}
3254
a4fc5ed6 3255static void
0301b3ac
JN		 3256intel_get_adjust_train(struct intel_dp *intel_dp,
3257 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3258{
3259 uint8_t v = 0;
3260 uint8_t p = 0;
3261 int lane;
1a2eb460
KP		 3262 uint8_t voltage_max;
3263 uint8_t preemph_max;
a4fc5ed6 3264
33a34e4e 3265 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3266 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3267 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3268
3269 if (this_v > v)
3270 v = this_v;
3271 if (this_p > p)
3272 p = this_p;
3273 }
3274
1a2eb460 3275 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3276 if (v >= voltage_max)
3277 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3278
1a2eb460
KP		 3279 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3280 if (p >= preemph_max)
3281 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3282
3283 for (lane = 0; lane < 4; lane++)
33a34e4e 3284 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3285}
3286
3287static uint32_t
f0a3424e 3288intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3289{
3cf2efb1 3290 uint32_t signal_levels = 0;
a4fc5ed6 3291
3cf2efb1 3292 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3294 default:
3295 signal_levels |= DP_VOLTAGE_0_4;
3296 break;
bd60018a 3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3298 signal_levels |= DP_VOLTAGE_0_6;
3299 break;
bd60018a 3300 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3301 signal_levels |= DP_VOLTAGE_0_8;
3302 break;
bd60018a 3303 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3304 signal_levels |= DP_VOLTAGE_1_2;
3305 break;
3306 }
3cf2efb1 3307 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3308 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3309 default:
3310 signal_levels |= DP_PRE_EMPHASIS_0;
3311 break;
bd60018a 3312 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3313 signal_levels |= DP_PRE_EMPHASIS_3_5;
3314 break;
bd60018a 3315 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3316 signal_levels |= DP_PRE_EMPHASIS_6;
3317 break;
bd60018a 3318 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3319 signal_levels |= DP_PRE_EMPHASIS_9_5;
3320 break;
3321 }
3322 return signal_levels;
3323}
3324
e3421a18
ZW		 3325/* Gen6's DP voltage swing and pre-emphasis control */
3326static uint32_t
3327intel_gen6_edp_signal_levels(uint8_t train_set)
3328{
3c5a62b5
YL		 3329 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3330 DP_TRAIN_PRE_EMPHASIS_MASK);
3331 switch (signal_levels) {
bd60018a
SJ		 3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3334 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3336 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3339 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3340 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3342 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3343 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3344 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3345 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3346 default:
3c5a62b5
YL		 3347 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3348 "0x%x\n", signal_levels);
3349 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3350 }
3351}
3352
1a2eb460
KP		 3353/* Gen7's DP voltage swing and pre-emphasis control */
3354static uint32_t
3355intel_gen7_edp_signal_levels(uint8_t train_set)
3356{
3357 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3358 DP_TRAIN_PRE_EMPHASIS_MASK);
3359 switch (signal_levels) {
bd60018a 3360 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3361 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3362 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3363 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3365 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3366
bd60018a 3367 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3368 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3369 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3370 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3371
bd60018a 3372 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3373 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3374 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3375 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3376
3377 default:
3378 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3379 "0x%x\n", signal_levels);
3380 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3381 }
3382}
3383
d6c0d722
PZ		 3384/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3385static uint32_t
f0a3424e 3386intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3387{
d6c0d722
PZ		 3388 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3389 DP_TRAIN_PRE_EMPHASIS_MASK);
3390 switch (signal_levels) {
bd60018a 3391 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3392 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3394 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3395 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3396 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3398 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3399
bd60018a 3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3401 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3402 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3403 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3404 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3405 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3406
bd60018a 3407 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3408 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3409 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3410 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3411 default:
3412 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3413 "0x%x\n", signal_levels);
c5fe6a06 3414 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3415 }
a4fc5ed6
KP		 3416}
3417
f0a3424e
PZ		 3418/* Properly updates "DP" with the correct signal levels. */
3419static void
3420intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3421{
3422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3423 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3424 struct drm_device *dev = intel_dig_port->base.base.dev;
3425 uint32_t signal_levels, mask;
3426 uint8_t train_set = intel_dp->train_set[0];
3427
5a9d1f1a 3428 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3429 signal_levels = intel_hsw_signal_levels(train_set);
3430 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3431 } else if (IS_CHERRYVIEW(dev)) {
3432 signal_levels = intel_chv_signal_levels(intel_dp);
3433 mask = 0;
e2fa6fba
P		 3434 } else if (IS_VALLEYVIEW(dev)) {
3435 signal_levels = intel_vlv_signal_levels(intel_dp);
3436 mask = 0;
bc7d38a4 3437 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3438 signal_levels = intel_gen7_edp_signal_levels(train_set);
3439 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3440 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3441 signal_levels = intel_gen6_edp_signal_levels(train_set);
3442 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3443 } else {
3444 signal_levels = intel_gen4_signal_levels(train_set);
3445 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3446 }
3447
3448 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3449
3450 *DP = (*DP & ~mask) | signal_levels;
3451}
3452
a4fc5ed6 3453static bool
ea5b213a 3454intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3455 uint32_t *DP,
58e10eb9 3456 uint8_t dp_train_pat)
a4fc5ed6 3457{
174edf1f
PZ		 3458 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3459 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3460 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3461 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3462 int ret, len;
a4fc5ed6 3463
7b13b58a 3464 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3465
70aff66c 3466 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3467 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3468
2cdfe6c8
JN		 3469 buf[0] = dp_train_pat;
3470 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3471 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3472 /* don't write DP_TRAINING_LANEx_SET on disable */
3473 len = 1;
3474 } else {
3475 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3476 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3477 len = intel_dp->lane_count + 1;
47ea7542 3478 }
a4fc5ed6 3479
9d1a1031
JN		 3480 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3481 buf, len);
2cdfe6c8
JN		 3482
3483 return ret == len;
a4fc5ed6
KP		 3484}
3485
70aff66c
JN		 3486static bool
3487intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3488 uint8_t dp_train_pat)
3489{
953d22e8 3490 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3491 intel_dp_set_signal_levels(intel_dp, DP);
3492 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3493}
3494
3495static bool
3496intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3497 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3498{
3499 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3500 struct drm_device *dev = intel_dig_port->base.base.dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 int ret;
3503
3504 intel_get_adjust_train(intel_dp, link_status);
3505 intel_dp_set_signal_levels(intel_dp, DP);
3506
3507 I915_WRITE(intel_dp->output_reg, *DP);
3508 POSTING_READ(intel_dp->output_reg);
3509
9d1a1031
JN		 3510 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3511 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3512
3513 return ret == intel_dp->lane_count;
3514}
3515
3ab9c637
ID		 3516static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3517{
3518 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3519 struct drm_device *dev = intel_dig_port->base.base.dev;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3521 enum port port = intel_dig_port->port;
3522 uint32_t val;
3523
3524 if (!HAS_DDI(dev))
3525 return;
3526
3527 val = I915_READ(DP_TP_CTL(port));
3528 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3529 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3530 I915_WRITE(DP_TP_CTL(port), val);
3531
3532 /*
3533 * On PORT_A we can have only eDP in SST mode. There the only reason
3534 * we need to set idle transmission mode is to work around a HW issue
3535 * where we enable the pipe while not in idle link-training mode.
3536 * In this case there is requirement to wait for a minimum number of
3537 * idle patterns to be sent.
3538 */
3539 if (port == PORT_A)
3540 return;
3541
3542 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3543 1))
3544 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3545}
3546
33a34e4e 3547/* Enable corresponding port and start training pattern 1 */
c19b0669 3548void
33a34e4e 3549intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3550{
da63a9f2 3551 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3552 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3553 int i;
3554 uint8_t voltage;
cdb0e95b 3555 int voltage_tries, loop_tries;
ea5b213a 3556 uint32_t DP = intel_dp->DP;
6aba5b6c 3557 uint8_t link_config[2];
a4fc5ed6 3558
affa9354 3559 if (HAS_DDI(dev))
c19b0669
PZ		 3560 intel_ddi_prepare_link_retrain(encoder);
3561
3cf2efb1 3562 /* Write the link configuration data */
6aba5b6c
JN		 3563 link_config[0] = intel_dp->link_bw;
3564 link_config[1] = intel_dp->lane_count;
3565 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3566 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3567 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3568
3569 link_config[0] = 0;
3570 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3571 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3572
3573 DP |= DP_PORT_EN;
1a2eb460 3574
70aff66c
JN		 3575 /* clock recovery */
3576 if (!intel_dp_reset_link_train(intel_dp, &DP,
3577 DP_TRAINING_PATTERN_1 |
3578 DP_LINK_SCRAMBLING_DISABLE)) {
3579 DRM_ERROR("failed to enable link training\n");
3580 return;
3581 }
3582
a4fc5ed6 3583 voltage = 0xff;
cdb0e95b
KP		 3584 voltage_tries = 0;
3585 loop_tries = 0;
a4fc5ed6 3586 for (;;) {
70aff66c 3587 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3588
a7c9655f 3589 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3590 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3591 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3592 break;
93f62dad 3593 }
a4fc5ed6 3594
01916270 3595 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3596 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3597 break;
3598 }
3599
3600 /* Check to see if we've tried the max voltage */
3601 for (i = 0; i < intel_dp->lane_count; i++)
3602 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3603 break;
3b4f819d 3604 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3605 ++loop_tries;
3606 if (loop_tries == 5) {
3def84b3 3607 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3608 break;
3609 }
70aff66c
JN		 3610 intel_dp_reset_link_train(intel_dp, &DP,
3611 DP_TRAINING_PATTERN_1 |
3612 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3613 voltage_tries = 0;
3614 continue;
3615 }
a4fc5ed6 3616
3cf2efb1 3617 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3618 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3619 ++voltage_tries;
b06fbda3 3620 if (voltage_tries == 5) {
3def84b3 3621 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3622 break;
3623 }
3624 } else
3625 voltage_tries = 0;
3626 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3627
70aff66c
JN		 3628 /* Update training set as requested by target */
3629 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3630 DRM_ERROR("failed to update link training\n");
3631 break;
3632 }
a4fc5ed6
KP		 3633 }
3634
33a34e4e
JB		 3635 intel_dp->DP = DP;
3636}
3637
c19b0669 3638void
33a34e4e
JB		 3639intel_dp_complete_link_train(struct intel_dp *intel_dp)
3640{
33a34e4e 3641 bool channel_eq = false;
37f80975 3642 int tries, cr_tries;
33a34e4e 3643 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3644 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3645
3646 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3647 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3648 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3649
a4fc5ed6 3650 /* channel equalization */
70aff66c 3651 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3652 training_pattern |
70aff66c
JN		 3653 DP_LINK_SCRAMBLING_DISABLE)) {
3654 DRM_ERROR("failed to start channel equalization\n");
3655 return;
3656 }
3657
a4fc5ed6 3658 tries = 0;
37f80975 3659 cr_tries = 0;
a4fc5ed6
KP		 3660 channel_eq = false;
3661 for (;;) {
70aff66c 3662 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3663
37f80975
JB		 3664 if (cr_tries > 5) {
3665 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3666 break;
3667 }
3668
a7c9655f 3669 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3670 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3671 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3672 break;
70aff66c 3673 }
a4fc5ed6 3674
37f80975 3675 /* Make sure clock is still ok */
01916270 3676 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3677 intel_dp_start_link_train(intel_dp);
70aff66c 3678 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3679 training_pattern |
70aff66c 3680 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3681 cr_tries++;
3682 continue;
3683 }
3684
1ffdff13 3685 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3686 channel_eq = true;
3687 break;
3688 }
a4fc5ed6 3689
37f80975
JB		 3690 /* Try 5 times, then try clock recovery if that fails */
3691 if (tries > 5) {
3692 intel_dp_link_down(intel_dp);
3693 intel_dp_start_link_train(intel_dp);
70aff66c 3694 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3695 training_pattern |
70aff66c 3696 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3697 tries = 0;
3698 cr_tries++;
3699 continue;
3700 }
a4fc5ed6 3701
70aff66c
JN		 3702 /* Update training set as requested by target */
3703 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3704 DRM_ERROR("failed to update link training\n");
3705 break;
3706 }
3cf2efb1 3707 ++tries;
869184a6 3708 }
3cf2efb1 3709
3ab9c637
ID		 3710 intel_dp_set_idle_link_train(intel_dp);
3711
3712 intel_dp->DP = DP;
3713
d6c0d722 3714 if (channel_eq)
07f42258 3715 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3716
3ab9c637
ID		 3717}
3718
3719void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3720{
70aff66c 3721 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3722 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3723}
3724
3725static void
ea5b213a 3726intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3727{
da63a9f2 3728 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3729 enum port port = intel_dig_port->port;
da63a9f2 3730 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3731 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3732 struct intel_crtc *intel_crtc =
3733 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3734 uint32_t DP = intel_dp->DP;
a4fc5ed6 3735
bc76e320 3736 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3737 return;
3738
0c33d8d7 3739 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3740 return;
3741
28c97730 3742 DRM_DEBUG_KMS("\n");
32f9d658 3743
bc7d38a4 3744 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3745 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3746 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3747 } else {
aad3d14d
VS		 3748 if (IS_CHERRYVIEW(dev))
3749 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3750 else
3751 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3752 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3753 }
fe255d00 3754 POSTING_READ(intel_dp->output_reg);
5eb08b69 3755
493a7081 3756 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3757 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3758 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3759
5bddd17f
EA		 3760 /* Hardware workaround: leaving our transcoder select
3761 * set to transcoder B while it's off will prevent the
3762 * corresponding HDMI output on transcoder A.
3763 *
3764 * Combine this with another hardware workaround:
3765 * transcoder select bit can only be cleared while the
3766 * port is enabled.
3767 */
3768 DP &= ~DP_PIPEB_SELECT;
3769 I915_WRITE(intel_dp->output_reg, DP);
3770
3771 /* Changes to enable or select take place the vblank
3772 * after being written.
3773 */
ff50afe9
DV		 3774 if (WARN_ON(crtc == NULL)) {
3775 /* We should never try to disable a port without a crtc
3776 * attached. For paranoia keep the code around for a
3777 * bit. */
31acbcc4
CW		 3778 POSTING_READ(intel_dp->output_reg);
3779 msleep(50);
3780 } else
ab527efc 3781 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3782 }
3783
832afda6 3784 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3785 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3786 POSTING_READ(intel_dp->output_reg);
f01eca2e 3787 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3788}
3789
26d61aad
KP		 3790static bool
3791intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3792{
a031d709
RV		 3793 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3794 struct drm_device *dev = dig_port->base.base.dev;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796
9d1a1031
JN		 3797 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3798 sizeof(intel_dp->dpcd)) < 0)
edb39244 3799 return false; /* aux transfer failed */
92fd8fd1 3800
a8e98153 3801 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3802
edb39244
AJ		 3803 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3804 return false; /* DPCD not present */
3805
2293bb5c
SK		 3806 /* Check if the panel supports PSR */
3807 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3808 if (is_edp(intel_dp)) {
9d1a1031
JN		 3809 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3810 intel_dp->psr_dpcd,
3811 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3812 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3813 dev_priv->psr.sink_support = true;
50003939 3814 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3815 }
50003939
JN		 3816 }
3817
06ea66b6
TP		 3818 /* Training Pattern 3 support */
3819 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3820 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3821 intel_dp->use_tps3 = true;
f8d8a672 3822 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3823 } else
3824 intel_dp->use_tps3 = false;
3825
edb39244
AJ		 3826 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3827 DP_DWN_STRM_PORT_PRESENT))
3828 return true; /* native DP sink */
3829
3830 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3831 return true; /* no per-port downstream info */
3832
9d1a1031
JN		 3833 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3834 intel_dp->downstream_ports,
3835 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3836 return false; /* downstream port status fetch failed */
3837
3838 return true;
92fd8fd1
KP		 3839}
3840
0d198328
AJ		 3841static void
3842intel_dp_probe_oui(struct intel_dp *intel_dp)
3843{
3844 u8 buf[3];
3845
3846 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3847 return;
3848
24f3e092 3849 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3850
9d1a1031 3851 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3852 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3853 buf[0], buf[1], buf[2]);
3854
9d1a1031 3855 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3856 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3857 buf[0], buf[1], buf[2]);
351cfc34 3858
1e0560e0 3859 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3860}
3861
0e32b39c
DA		 3862static bool
3863intel_dp_probe_mst(struct intel_dp *intel_dp)
3864{
3865 u8 buf[1];
3866
3867 if (!intel_dp->can_mst)
3868 return false;
3869
3870 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3871 return false;
3872
d337a341 3873 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3874 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3875 if (buf[0] & DP_MST_CAP) {
3876 DRM_DEBUG_KMS("Sink is MST capable\n");
3877 intel_dp->is_mst = true;
3878 } else {
3879 DRM_DEBUG_KMS("Sink is not MST capable\n");
3880 intel_dp->is_mst = false;
3881 }
3882 }
1e0560e0 3883 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3884
3885 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3886 return intel_dp->is_mst;
3887}
3888
d2e216d0
RV		 3889int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3890{
3891 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3892 struct drm_device *dev = intel_dig_port->base.base.dev;
3893 struct intel_crtc *intel_crtc =
3894 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3895 u8 buf;
3896 int test_crc_count;
3897 int attempts = 6;
d2e216d0 3898
ad9dc91b 3899 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3900 return -EIO;
d2e216d0 3901
ad9dc91b 3902 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3903 return -ENOTTY;
3904
1dda5f93
RV		 3905 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3906 return -EIO;
3907
9d1a1031 3908 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3909 buf | DP_TEST_SINK_START) < 0)
bda0381e 3910 return -EIO;
d2e216d0 3911
1dda5f93 3912 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3913 return -EIO;
ad9dc91b 3914 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3915
ad9dc91b 3916 do {
1dda5f93
RV		 3917 if (drm_dp_dpcd_readb(&intel_dp->aux,
3918 DP_TEST_SINK_MISC, &buf) < 0)
3919 return -EIO;
ad9dc91b
RV		 3920 intel_wait_for_vblank(dev, intel_crtc->pipe);
3921 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3922
3923 if (attempts == 0) {
3924 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3925 return -EIO;
3926 }
d2e216d0 3927
9d1a1031 3928 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3929 return -EIO;
d2e216d0 3930
1dda5f93
RV		 3931 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3932 return -EIO;
3933 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3934 buf & ~DP_TEST_SINK_START) < 0)
3935 return -EIO;
ce31d9f4 3936
d2e216d0
RV		 3937 return 0;
3938}
3939
a60f0e38
JB		 3940static bool
3941intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3942{
9d1a1031
JN		 3943 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3944 DP_DEVICE_SERVICE_IRQ_VECTOR,
3945 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3946}
3947
0e32b39c
DA		 3948static bool
3949intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3950{
3951 int ret;
3952
3953 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3954 DP_SINK_COUNT_ESI,
3955 sink_irq_vector, 14);
3956 if (ret != 14)
3957 return false;
3958
3959 return true;
3960}
3961
a60f0e38
JB		 3962static void
3963intel_dp_handle_test_request(struct intel_dp *intel_dp)
3964{
3965 /* NAK by default */
9d1a1031 3966 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3967}
3968
0e32b39c
DA		 3969static int
3970intel_dp_check_mst_status(struct intel_dp *intel_dp)
3971{
3972 bool bret;
3973
3974 if (intel_dp->is_mst) {
3975 u8 esi[16] = { 0 };
3976 int ret = 0;
3977 int retry;
3978 bool handled;
3979 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3980go_again:
3981 if (bret == true) {
3982
3983 /* check link status - esi[10] = 0x200c */
3984 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3985 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3986 intel_dp_start_link_train(intel_dp);
3987 intel_dp_complete_link_train(intel_dp);
3988 intel_dp_stop_link_train(intel_dp);
3989 }
3990
3991 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3992 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3993
3994 if (handled) {
3995 for (retry = 0; retry < 3; retry++) {
3996 int wret;
3997 wret = drm_dp_dpcd_write(&intel_dp->aux,
3998 DP_SINK_COUNT_ESI+1,
3999 &esi[1], 3);
4000 if (wret == 3) {
4001 break;
4002 }
4003 }
4004
4005 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4006 if (bret == true) {
4007 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4008 goto go_again;
4009 }
4010 } else
4011 ret = 0;
4012
4013 return ret;
4014 } else {
4015 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4016 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4017 intel_dp->is_mst = false;
4018 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4019 /* send a hotplug event */
4020 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4021 }
4022 }
4023 return -EINVAL;
4024}
4025
a4fc5ed6
KP		 4026/*
4027 * According to DP spec
4028 * 5.1.2:
4029 * 1. Read DPCD
4030 * 2. Configure link according to Receiver Capabilities
4031 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4032 * 4. Check link status on receipt of hot-plug interrupt
4033 */
00c09d70 4034void
ea5b213a 4035intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4036{
5b215bcf 4037 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4038 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4039 u8 sink_irq_vector;
93f62dad 4040 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4041
5b215bcf
DA		 4042 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4043
da63a9f2 4044 if (!intel_encoder->connectors_active)
d2b996ac 4045 return;
59cd09e1 4046
da63a9f2 4047 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4048 return;
4049
1a125d8a
ID		 4050 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4051 return;
4052
92fd8fd1 4053 /* Try to read receiver status if the link appears to be up */
93f62dad 4054 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4055 return;
4056 }
4057
92fd8fd1 4058 /* Now read the DPCD to see if it's actually running */
26d61aad 4059 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4060 return;
4061 }
4062
a60f0e38
JB		 4063 /* Try to read the source of the interrupt */
4064 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4065 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4066 /* Clear interrupt source */
9d1a1031
JN		 4067 drm_dp_dpcd_writeb(&intel_dp->aux,
4068 DP_DEVICE_SERVICE_IRQ_VECTOR,
4069 sink_irq_vector);
a60f0e38
JB		 4070
4071 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4072 intel_dp_handle_test_request(intel_dp);
4073 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4074 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4075 }
4076
1ffdff13 4077 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4078 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4079 intel_encoder->base.name);
33a34e4e
JB		 4080 intel_dp_start_link_train(intel_dp);
4081 intel_dp_complete_link_train(intel_dp);
3ab9c637 4082 intel_dp_stop_link_train(intel_dp);
33a34e4e 4083 }
a4fc5ed6 4084}
a4fc5ed6 4085
caf9ab24 4086/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4087static enum drm_connector_status
26d61aad 4088intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4089{
caf9ab24 4090 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4091 uint8_t type;
4092
4093 if (!intel_dp_get_dpcd(intel_dp))
4094 return connector_status_disconnected;
4095
4096 /* if there's no downstream port, we're done */
4097 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4098 return connector_status_connected;
caf9ab24
AJ		 4099
4100 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4101 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4102 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4103 uint8_t reg;
9d1a1031
JN		 4104
4105 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4106 &reg, 1) < 0)
caf9ab24 4107 return connector_status_unknown;
9d1a1031 4108
23235177
AJ		 4109 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4110 : connector_status_disconnected;
caf9ab24
AJ		 4111 }
4112
4113 /* If no HPD, poke DDC gently */
0b99836f 4114 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4115 return connector_status_connected;
caf9ab24
AJ		 4116
4117 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4118 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4119 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4120 if (type == DP_DS_PORT_TYPE_VGA ||
4121 type == DP_DS_PORT_TYPE_NON_EDID)
4122 return connector_status_unknown;
4123 } else {
4124 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4125 DP_DWN_STRM_PORT_TYPE_MASK;
4126 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4127 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4128 return connector_status_unknown;
4129 }
caf9ab24
AJ		 4130
4131 /* Anything else is out of spec, warn and ignore */
4132 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4133 return connector_status_disconnected;
71ba9000
AJ		 4134}
4135
d410b56d
CW		 4136static enum drm_connector_status
4137edp_detect(struct intel_dp *intel_dp)
4138{
4139 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4140 enum drm_connector_status status;
4141
4142 status = intel_panel_detect(dev);
4143 if (status == connector_status_unknown)
4144 status = connector_status_connected;
4145
4146 return status;
4147}
4148
5eb08b69 4149static enum drm_connector_status
a9756bb5 4150ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4151{
30add22d 4152 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4155
1b469639
DL		 4156 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4157 return connector_status_disconnected;
4158
26d61aad 4159 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4160}
4161
2a592bec
DA		 4162static int g4x_digital_port_connected(struct drm_device *dev,
4163 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4164{
a4fc5ed6 4165 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4166 uint32_t bit;
5eb08b69 4167
232a6ee9
TP		 4168 if (IS_VALLEYVIEW(dev)) {
4169 switch (intel_dig_port->port) {
4170 case PORT_B:
4171 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4172 break;
4173 case PORT_C:
4174 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4175 break;
4176 case PORT_D:
4177 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4178 break;
4179 default:
2a592bec 4180 return -EINVAL;
232a6ee9
TP		 4181 }
4182 } else {
4183 switch (intel_dig_port->port) {
4184 case PORT_B:
4185 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4186 break;
4187 case PORT_C:
4188 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4189 break;
4190 case PORT_D:
4191 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4192 break;
4193 default:
2a592bec 4194 return -EINVAL;
232a6ee9 4195 }
a4fc5ed6
KP		 4196 }
4197
10f76a38 4198 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4199 return 0;
4200 return 1;
4201}
4202
4203static enum drm_connector_status
4204g4x_dp_detect(struct intel_dp *intel_dp)
4205{
4206 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4207 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4208 int ret;
4209
4210 /* Can't disconnect eDP, but you can close the lid... */
4211 if (is_edp(intel_dp)) {
4212 enum drm_connector_status status;
4213
4214 status = intel_panel_detect(dev);
4215 if (status == connector_status_unknown)
4216 status = connector_status_connected;
4217 return status;
4218 }
4219
4220 ret = g4x_digital_port_connected(dev, intel_dig_port);
4221 if (ret == -EINVAL)
4222 return connector_status_unknown;
4223 else if (ret == 0)
a4fc5ed6
KP		 4224 return connector_status_disconnected;
4225
26d61aad 4226 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4227}
4228
8c241fef 4229static struct edid *
beb60608 4230intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4231{
beb60608 4232 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4233
9cd300e0
JN		 4234 /* use cached edid if we have one */
4235 if (intel_connector->edid) {
9cd300e0
JN		 4236 /* invalid edid */
4237 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4238 return NULL;
4239
55e9edeb 4240 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4241 } else
4242 return drm_get_edid(&intel_connector->base,
4243 &intel_dp->aux.ddc);
4244}
8c241fef 4245
beb60608
CW		 4246static void
4247intel_dp_set_edid(struct intel_dp *intel_dp)
4248{
4249 struct intel_connector *intel_connector = intel_dp->attached_connector;
4250 struct edid *edid;
8c241fef 4251
beb60608
CW		 4252 edid = intel_dp_get_edid(intel_dp);
4253 intel_connector->detect_edid = edid;
4254
4255 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4256 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4257 else
4258 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4259}
4260
beb60608
CW		 4261static void
4262intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4263{
beb60608 4264 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4265
beb60608
CW		 4266 kfree(intel_connector->detect_edid);
4267 intel_connector->detect_edid = NULL;
9cd300e0 4268
beb60608
CW		 4269 intel_dp->has_audio = false;
4270}
d6f24d0f 4271
beb60608
CW		 4272static enum intel_display_power_domain
4273intel_dp_power_get(struct intel_dp *dp)
4274{
4275 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4276 enum intel_display_power_domain power_domain;
4277
4278 power_domain = intel_display_port_power_domain(encoder);
4279 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4280
4281 return power_domain;
4282}
d6f24d0f 4283
beb60608
CW		 4284static void
4285intel_dp_power_put(struct intel_dp *dp,
4286 enum intel_display_power_domain power_domain)
4287{
4288 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4289 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4290}
4291
a9756bb5
ZW		 4292static enum drm_connector_status
4293intel_dp_detect(struct drm_connector *connector, bool force)
4294{
4295 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4297 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4298 struct drm_device *dev = connector->dev;
a9756bb5 4299 enum drm_connector_status status;
671dedd2 4300 enum intel_display_power_domain power_domain;
0e32b39c 4301 bool ret;
a9756bb5 4302
164c8598 4303 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4304 connector->base.id, connector->name);
beb60608 4305 intel_dp_unset_edid(intel_dp);
164c8598 4306
0e32b39c
DA		 4307 if (intel_dp->is_mst) {
4308 /* MST devices are disconnected from a monitor POV */
4309 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4310 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4311 return connector_status_disconnected;
0e32b39c
DA		 4312 }
4313
beb60608 4314 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4315
d410b56d
CW		 4316 /* Can't disconnect eDP, but you can close the lid... */
4317 if (is_edp(intel_dp))
4318 status = edp_detect(intel_dp);
4319 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4320 status = ironlake_dp_detect(intel_dp);
4321 else
4322 status = g4x_dp_detect(intel_dp);
4323 if (status != connector_status_connected)
c8c8fb33 4324 goto out;
a9756bb5 4325
0d198328
AJ		 4326 intel_dp_probe_oui(intel_dp);
4327
0e32b39c
DA		 4328 ret = intel_dp_probe_mst(intel_dp);
4329 if (ret) {
4330 /* if we are in MST mode then this connector
4331 won't appear connected or have anything with EDID on it */
4332 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4333 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4334 status = connector_status_disconnected;
4335 goto out;
4336 }
4337
beb60608 4338 intel_dp_set_edid(intel_dp);
a9756bb5 4339
d63885da
PZ		 4340 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4341 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4342 status = connector_status_connected;
4343
4344out:
beb60608 4345 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4346 return status;
a4fc5ed6
KP		 4347}
4348
beb60608
CW		 4349static void
4350intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4351{
df0e9248 4352 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4353 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4354 enum intel_display_power_domain power_domain;
a4fc5ed6 4355
beb60608
CW		 4356 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4357 connector->base.id, connector->name);
4358 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4359
beb60608
CW		 4360 if (connector->status != connector_status_connected)
4361 return;
671dedd2 4362
beb60608
CW		 4363 power_domain = intel_dp_power_get(intel_dp);
4364
4365 intel_dp_set_edid(intel_dp);
4366
4367 intel_dp_power_put(intel_dp, power_domain);
4368
4369 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4370 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4371}
4372
4373static int intel_dp_get_modes(struct drm_connector *connector)
4374{
4375 struct intel_connector *intel_connector = to_intel_connector(connector);
4376 struct edid *edid;
4377
4378 edid = intel_connector->detect_edid;
4379 if (edid) {
4380 int ret = intel_connector_update_modes(connector, edid);
4381 if (ret)
4382 return ret;
4383 }
32f9d658 4384
f8779fda 4385 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4386 if (is_edp(intel_attached_dp(connector)) &&
4387 intel_connector->panel.fixed_mode) {
f8779fda 4388 struct drm_display_mode *mode;
beb60608
CW		 4389
4390 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4391 intel_connector->panel.fixed_mode);
f8779fda 4392 if (mode) {
32f9d658
ZW		 4393 drm_mode_probed_add(connector, mode);
4394 return 1;
4395 }
4396 }
beb60608 4397
32f9d658 4398 return 0;
a4fc5ed6
KP		 4399}
4400
1aad7ac0
CW		 4401static bool
4402intel_dp_detect_audio(struct drm_connector *connector)
4403{
1aad7ac0 4404 bool has_audio = false;
beb60608 4405 struct edid *edid;
1aad7ac0 4406
beb60608
CW		 4407 edid = to_intel_connector(connector)->detect_edid;
4408 if (edid)
1aad7ac0 4409 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4410
1aad7ac0
CW		 4411 return has_audio;
4412}
4413
f684960e
CW		 4414static int
4415intel_dp_set_property(struct drm_connector *connector,
4416 struct drm_property *property,
4417 uint64_t val)
4418{
e953fd7b 4419 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4420 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4421 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4422 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4423 int ret;
4424
662595df 4425 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4426 if (ret)
4427 return ret;
4428
3f43c48d 4429 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4430 int i = val;
4431 bool has_audio;
4432
4433 if (i == intel_dp->force_audio)
f684960e
CW		 4434 return 0;
4435
1aad7ac0 4436 intel_dp->force_audio = i;
f684960e 4437
c3e5f67b 4438 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4439 has_audio = intel_dp_detect_audio(connector);
4440 else
c3e5f67b 4441 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4442
4443 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4444 return 0;
4445
1aad7ac0 4446 intel_dp->has_audio = has_audio;
f684960e
CW		 4447 goto done;
4448 }
4449
e953fd7b 4450 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4451 bool old_auto = intel_dp->color_range_auto;
4452 uint32_t old_range = intel_dp->color_range;
4453
55bc60db
VS		 4454 switch (val) {
4455 case INTEL_BROADCAST_RGB_AUTO:
4456 intel_dp->color_range_auto = true;
4457 break;
4458 case INTEL_BROADCAST_RGB_FULL:
4459 intel_dp->color_range_auto = false;
4460 intel_dp->color_range = 0;
4461 break;
4462 case INTEL_BROADCAST_RGB_LIMITED:
4463 intel_dp->color_range_auto = false;
4464 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4465 break;
4466 default:
4467 return -EINVAL;
4468 }
ae4edb80
DV		 4469
4470 if (old_auto == intel_dp->color_range_auto &&
4471 old_range == intel_dp->color_range)
4472 return 0;
4473
e953fd7b
CW		 4474 goto done;
4475 }
4476
53b41837
YN		 4477 if (is_edp(intel_dp) &&
4478 property == connector->dev->mode_config.scaling_mode_property) {
4479 if (val == DRM_MODE_SCALE_NONE) {
4480 DRM_DEBUG_KMS("no scaling not supported\n");
4481 return -EINVAL;
4482 }
4483
4484 if (intel_connector->panel.fitting_mode == val) {
4485 /* the eDP scaling property is not changed */
4486 return 0;
4487 }
4488 intel_connector->panel.fitting_mode = val;
4489
4490 goto done;
4491 }
4492
f684960e
CW		 4493 return -EINVAL;
4494
4495done:
c0c36b94
CW		 4496 if (intel_encoder->base.crtc)
4497 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4498
4499 return 0;
4500}
4501
a4fc5ed6 4502static void
73845adf 4503intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4504{
1d508706 4505 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4506
10e972d3 4507 kfree(intel_connector->detect_edid);
beb60608 4508
9cd300e0
JN		 4509 if (!IS_ERR_OR_NULL(intel_connector->edid))
4510 kfree(intel_connector->edid);
4511
acd8db10
PZ		 4512 /* Can't call is_edp() since the encoder may have been destroyed
4513 * already. */
4514 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4515 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4516
a4fc5ed6 4517 drm_connector_cleanup(connector);
55f78c43 4518 kfree(connector);
a4fc5ed6
KP		 4519}
4520
00c09d70 4521void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4522{
da63a9f2
PZ		 4523 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4524 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4525
4f71d0cb 4526 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4527 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4528 drm_encoder_cleanup(encoder);
bd943159
KP		 4529 if (is_edp(intel_dp)) {
4530 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4531 /*
4532 * vdd might still be enabled do to the delayed vdd off.
4533 * Make sure vdd is actually turned off here.
4534 */
773538e8 4535 pps_lock(intel_dp);
4be73780 4536 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4537 pps_unlock(intel_dp);
4538
01527b31
CT		 4539 if (intel_dp->edp_notifier.notifier_call) {
4540 unregister_reboot_notifier(&intel_dp->edp_notifier);
4541 intel_dp->edp_notifier.notifier_call = NULL;
4542 }
bd943159 4543 }
da63a9f2 4544 kfree(intel_dig_port);
24d05927
DV		 4545}
4546
07f9cd0b
ID		 4547static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4548{
4549 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4550
4551 if (!is_edp(intel_dp))
4552 return;
4553
951468f3
VS		 4554 /*
4555 * vdd might still be enabled do to the delayed vdd off.
4556 * Make sure vdd is actually turned off here.
4557 */
773538e8 4558 pps_lock(intel_dp);
07f9cd0b 4559 edp_panel_vdd_off_sync(intel_dp);
773538e8 4560 pps_unlock(intel_dp);
07f9cd0b
ID		 4561}
4562
6d93c0c4
ID		 4563static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4564{
4565 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4566}
4567
a4fc5ed6 4568static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4569 .dpms = intel_connector_dpms,
a4fc5ed6 4570 .detect = intel_dp_detect,
beb60608 4571 .force = intel_dp_force,
a4fc5ed6 4572 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4573 .set_property = intel_dp_set_property,
73845adf 4574 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4575};
4576
4577static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4578 .get_modes = intel_dp_get_modes,
4579 .mode_valid = intel_dp_mode_valid,
df0e9248 4580 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4581};
4582
a4fc5ed6 4583static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4584 .reset = intel_dp_encoder_reset,
24d05927 4585 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4586};
4587
0e32b39c 4588void
21d40d37 4589intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4590{
0e32b39c 4591 return;
c8110e52 4592}
6207937d 4593
13cf5504
DA		 4594bool
4595intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4596{
4597 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4598 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4599 struct drm_device *dev = intel_dig_port->base.base.dev;
4600 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4601 enum intel_display_power_domain power_domain;
4602 bool ret = true;
4603
0e32b39c
DA		 4604 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4605 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4606
26fbb774
VS		 4607 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4608 port_name(intel_dig_port->port),
0e32b39c 4609 long_hpd ? "long" : "short");
13cf5504 4610
1c767b33
ID		 4611 power_domain = intel_display_port_power_domain(intel_encoder);
4612 intel_display_power_get(dev_priv, power_domain);
4613
0e32b39c 4614 if (long_hpd) {
2a592bec
DA		 4615
4616 if (HAS_PCH_SPLIT(dev)) {
4617 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4618 goto mst_fail;
4619 } else {
4620 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4621 goto mst_fail;
4622 }
0e32b39c
DA		 4623
4624 if (!intel_dp_get_dpcd(intel_dp)) {
4625 goto mst_fail;
4626 }
4627
4628 intel_dp_probe_oui(intel_dp);
4629
4630 if (!intel_dp_probe_mst(intel_dp))
4631 goto mst_fail;
4632
4633 } else {
4634 if (intel_dp->is_mst) {
1c767b33 4635 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4636 goto mst_fail;
4637 }
4638
4639 if (!intel_dp->is_mst) {
4640 /*
4641 * we'll check the link status via the normal hot plug path later -
4642 * but for short hpds we should check it now
4643 */
5b215bcf 4644 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4645 intel_dp_check_link_status(intel_dp);
5b215bcf 4646 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4647 }
4648 }
1c767b33
ID		 4649 ret = false;
4650 goto put_power;
0e32b39c
DA		 4651mst_fail:
4652 /* if we were in MST mode, and device is not there get out of MST mode */
4653 if (intel_dp->is_mst) {
4654 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4655 intel_dp->is_mst = false;
4656 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4657 }
1c767b33
ID		 4658put_power:
4659 intel_display_power_put(dev_priv, power_domain);
4660
4661 return ret;
13cf5504
DA		 4662}
4663
e3421a18
ZW		 4664/* Return which DP Port should be selected for Transcoder DP control */
4665int
0206e353 4666intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4667{
4668 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4669 struct intel_encoder *intel_encoder;
4670 struct intel_dp *intel_dp;
e3421a18 4671
fa90ecef
PZ		 4672 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4673 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4674
fa90ecef
PZ		 4675 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4676 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4677 return intel_dp->output_reg;
e3421a18 4678 }
ea5b213a 4679
e3421a18
ZW		 4680 return -1;
4681}
4682
36e83a18 4683/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4684bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4685{
4686 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4687 union child_device_config *p_child;
36e83a18 4688 int i;
5d8a7752
VS		 4689 static const short port_mapping[] = {
4690 [PORT_B] = PORT_IDPB,
4691 [PORT_C] = PORT_IDPC,
4692 [PORT_D] = PORT_IDPD,
4693 };
36e83a18 4694
3b32a35b
VS		 4695 if (port == PORT_A)
4696 return true;
4697
41aa3448 4698 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4699 return false;
4700
41aa3448
RV		 4701 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4702 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4703
5d8a7752 4704 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4705 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4706 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4707 return true;
4708 }
4709 return false;
4710}
4711
0e32b39c 4712void
f684960e
CW		 4713intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4714{
53b41837
YN		 4715 struct intel_connector *intel_connector = to_intel_connector(connector);
4716
3f43c48d 4717 intel_attach_force_audio_property(connector);
e953fd7b 4718 intel_attach_broadcast_rgb_property(connector);
55bc60db 4719 intel_dp->color_range_auto = true;
53b41837
YN		 4720
4721 if (is_edp(intel_dp)) {
4722 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4723 drm_object_attach_property(
4724 &connector->base,
53b41837 4725 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4726 DRM_MODE_SCALE_ASPECT);
4727 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4728 }
f684960e
CW		 4729}
4730
dada1a9f
ID		 4731static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4732{
4733 intel_dp->last_power_cycle = jiffies;
4734 intel_dp->last_power_on = jiffies;
4735 intel_dp->last_backlight_off = jiffies;
4736}
4737
67a54566
DV		 4738static void
4739intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4740 struct intel_dp *intel_dp,
4741 struct edp_power_seq *out)
67a54566
DV		 4742{
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4744 struct edp_power_seq cur, vbt, spec, final;
4745 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4746 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4747
e39b999a
VS		 4748 lockdep_assert_held(&dev_priv->pps_mutex);
4749
453c5420 4750 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4751 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4752 pp_on_reg = PCH_PP_ON_DELAYS;
4753 pp_off_reg = PCH_PP_OFF_DELAYS;
4754 pp_div_reg = PCH_PP_DIVISOR;
4755 } else {
bf13e81b
JN		 4756 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4757
4758 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4759 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4760 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4761 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4762 }
67a54566
DV		 4763
4764 /* Workaround: Need to write PP_CONTROL with the unlock key as
4765 * the very first thing. */
453c5420 4766 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4767 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4768
453c5420
JB		 4769 pp_on = I915_READ(pp_on_reg);
4770 pp_off = I915_READ(pp_off_reg);
4771 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4772
4773 /* Pull timing values out of registers */
4774 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4775 PANEL_POWER_UP_DELAY_SHIFT;
4776
4777 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4778 PANEL_LIGHT_ON_DELAY_SHIFT;
4779
4780 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4781 PANEL_LIGHT_OFF_DELAY_SHIFT;
4782
4783 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4784 PANEL_POWER_DOWN_DELAY_SHIFT;
4785
4786 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4787 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4788
4789 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4790 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4791
41aa3448 4792 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4793
4794 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4795 * our hw here, which are all in 100usec. */
4796 spec.t1_t3 = 210 * 10;
4797 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4798 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4799 spec.t10 = 500 * 10;
4800 /* This one is special and actually in units of 100ms, but zero
4801 * based in the hw (so we need to add 100 ms). But the sw vbt
4802 * table multiplies it with 1000 to make it in units of 100usec,
4803 * too. */
4804 spec.t11_t12 = (510 + 100) * 10;
4805
4806 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4807 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4808
4809 /* Use the max of the register settings and vbt. If both are
4810 * unset, fall back to the spec limits. */
4811#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4812 spec.field : \
4813 max(cur.field, vbt.field))
4814 assign_final(t1_t3);
4815 assign_final(t8);
4816 assign_final(t9);
4817 assign_final(t10);
4818 assign_final(t11_t12);
4819#undef assign_final
4820
4821#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4822 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4823 intel_dp->backlight_on_delay = get_delay(t8);
4824 intel_dp->backlight_off_delay = get_delay(t9);
4825 intel_dp->panel_power_down_delay = get_delay(t10);
4826 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4827#undef get_delay
4828
f30d26e4
JN		 4829 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4830 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4831 intel_dp->panel_power_cycle_delay);
4832
4833 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4834 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4835
4836 if (out)
4837 *out = final;
4838}
4839
4840static void
4841intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4842 struct intel_dp *intel_dp,
4843 struct edp_power_seq *seq)
4844{
4845 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4846 u32 pp_on, pp_off, pp_div, port_sel = 0;
4847 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4848 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4849 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4850
e39b999a 4851 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4852
4853 if (HAS_PCH_SPLIT(dev)) {
4854 pp_on_reg = PCH_PP_ON_DELAYS;
4855 pp_off_reg = PCH_PP_OFF_DELAYS;
4856 pp_div_reg = PCH_PP_DIVISOR;
4857 } else {
bf13e81b
JN		 4858 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4859
4860 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4861 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4862 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4863 }
4864
b2f19d1a
PZ		 4865 /*
4866 * And finally store the new values in the power sequencer. The
4867 * backlight delays are set to 1 because we do manual waits on them. For
4868 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4869 * we'll end up waiting for the backlight off delay twice: once when we
4870 * do the manual sleep, and once when we disable the panel and wait for
4871 * the PP_STATUS bit to become zero.
4872 */
f30d26e4 4873 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4874 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4875 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4876 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4877 /* Compute the divisor for the pp clock, simply match the Bspec
4878 * formula. */
453c5420 4879 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4880 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4881 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4882
4883 /* Haswell doesn't have any port selection bits for the panel
4884 * power sequencer any more. */
bc7d38a4 4885 if (IS_VALLEYVIEW(dev)) {
ad933b56 4886 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4887 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4888 if (port == PORT_A)
a24c144c 4889 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4890 else
a24c144c 4891 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4892 }
4893
453c5420
JB		 4894 pp_on |= port_sel;
4895
4896 I915_WRITE(pp_on_reg, pp_on);
4897 I915_WRITE(pp_off_reg, pp_off);
4898 I915_WRITE(pp_div_reg, pp_div);
67a54566 4899
67a54566 4900 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4901 I915_READ(pp_on_reg),
4902 I915_READ(pp_off_reg),
4903 I915_READ(pp_div_reg));
f684960e
CW		 4904}
4905
439d7ac0
PB		 4906void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4907{
4908 struct drm_i915_private *dev_priv = dev->dev_private;
4909 struct intel_encoder *encoder;
4910 struct intel_dp *intel_dp = NULL;
4911 struct intel_crtc_config *config = NULL;
4912 struct intel_crtc *intel_crtc = NULL;
4913 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4914 u32 reg, val;
4915 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4916
4917 if (refresh_rate <= 0) {
4918 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4919 return;
4920 }
4921
4922 if (intel_connector == NULL) {
4923 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4924 return;
4925 }
4926
1fcc9d1c
DV		 4927 /*
4928 * FIXME: This needs proper synchronization with psr state. But really
4929 * hard to tell without seeing the user of this function of this code.
4930 * Check locking and ordering once that lands.
4931 */
439d7ac0
PB		 4932 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4933 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4934 return;
4935 }
4936
4937 encoder = intel_attached_encoder(&intel_connector->base);
4938 intel_dp = enc_to_intel_dp(&encoder->base);
4939 intel_crtc = encoder->new_crtc;
4940
4941 if (!intel_crtc) {
4942 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4943 return;
4944 }
4945
4946 config = &intel_crtc->config;
4947
4948 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4949 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4950 return;
4951 }
4952
4953 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4954 index = DRRS_LOW_RR;
4955
4956 if (index == intel_dp->drrs_state.refresh_rate_type) {
4957 DRM_DEBUG_KMS(
4958 "DRRS requested for previously set RR...ignoring\n");
4959 return;
4960 }
4961
4962 if (!intel_crtc->active) {
4963 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4964 return;
4965 }
4966
4967 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4968 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4969 val = I915_READ(reg);
4970 if (index > DRRS_HIGH_RR) {
4971 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4972 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4973 } else {
4974 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4975 }
4976 I915_WRITE(reg, val);
4977 }
4978
4979 /*
4980 * mutex taken to ensure that there is no race between differnt
4981 * drrs calls trying to update refresh rate. This scenario may occur
4982 * in future when idleness detection based DRRS in kernel and
4983 * possible calls from user space to set differnt RR are made.
4984 */
4985
4986 mutex_lock(&intel_dp->drrs_state.mutex);
4987
4988 intel_dp->drrs_state.refresh_rate_type = index;
4989
4990 mutex_unlock(&intel_dp->drrs_state.mutex);
4991
4992 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4993}
4994
4f9db5b5
PB		 4995static struct drm_display_mode *
4996intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4997 struct intel_connector *intel_connector,
4998 struct drm_display_mode *fixed_mode)
4999{
5000 struct drm_connector *connector = &intel_connector->base;
5001 struct intel_dp *intel_dp = &intel_dig_port->dp;
5002 struct drm_device *dev = intel_dig_port->base.base.dev;
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 struct drm_display_mode *downclock_mode = NULL;
5005
5006 if (INTEL_INFO(dev)->gen <= 6) {
5007 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5008 return NULL;
5009 }
5010
5011 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5012 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5013 return NULL;
5014 }
5015
5016 downclock_mode = intel_find_panel_downclock
5017 (dev, fixed_mode, connector);
5018
5019 if (!downclock_mode) {
4079b8d1 5020 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 5021 return NULL;
5022 }
5023
439d7ac0
PB		 5024 dev_priv->drrs.connector = intel_connector;
5025
5026 mutex_init(&intel_dp->drrs_state.mutex);
5027
4f9db5b5
PB		 5028 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5029
5030 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5031 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5032 return downclock_mode;
5033}
5034
aba86890
ID		 5035void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5036{
5037 struct drm_device *dev = intel_encoder->base.dev;
5038 struct drm_i915_private *dev_priv = dev->dev_private;
5039 struct intel_dp *intel_dp;
5040 enum intel_display_power_domain power_domain;
5041
5042 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5043 return;
5044
5045 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5046
5047 pps_lock(intel_dp);
5048
aba86890 5049 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5050 goto out;
aba86890
ID		 5051 /*
5052 * The VDD bit needs a power domain reference, so if the bit is
5053 * already enabled when we boot or resume, grab this reference and
5054 * schedule a vdd off, so we don't hold on to the reference
5055 * indefinitely.
5056 */
5057 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5058 power_domain = intel_display_port_power_domain(intel_encoder);
5059 intel_display_power_get(dev_priv, power_domain);
5060
5061 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5062 out:
773538e8 5063 pps_unlock(intel_dp);
aba86890
ID		 5064}
5065
ed92f0b2 5066static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 5067 struct intel_connector *intel_connector,
5068 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 5069{
5070 struct drm_connector *connector = &intel_connector->base;
5071 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5072 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5073 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5074 struct drm_i915_private *dev_priv = dev->dev_private;
5075 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5076 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5077 bool has_dpcd;
5078 struct drm_display_mode *scan;
5079 struct edid *edid;
5080
4f9db5b5
PB		 5081 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5082
ed92f0b2
PZ		 5083 if (!is_edp(intel_dp))
5084 return true;
5085
aba86890 5086 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5087
ed92f0b2 5088 /* Cache DPCD and EDID for edp. */
24f3e092 5089 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 5090 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 5091 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 5092
5093 if (has_dpcd) {
5094 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5095 dev_priv->no_aux_handshake =
5096 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5097 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5098 } else {
5099 /* if this fails, presume the device is a ghost */
5100 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5101 return false;
5102 }
5103
5104 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5105 pps_lock(intel_dp);
0095e6dc 5106 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 5107 pps_unlock(intel_dp);
ed92f0b2 5108
060c8778 5109 mutex_lock(&dev->mode_config.mutex);
0b99836f 5110 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5111 if (edid) {
5112 if (drm_add_edid_modes(connector, edid)) {
5113 drm_mode_connector_update_edid_property(connector,
5114 edid);
5115 drm_edid_to_eld(connector, edid);
5116 } else {
5117 kfree(edid);
5118 edid = ERR_PTR(-EINVAL);
5119 }
5120 } else {
5121 edid = ERR_PTR(-ENOENT);
5122 }
5123 intel_connector->edid = edid;
5124
5125 /* prefer fixed mode from EDID if available */
5126 list_for_each_entry(scan, &connector->probed_modes, head) {
5127 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5128 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5129 downclock_mode = intel_dp_drrs_init(
5130 intel_dig_port,
5131 intel_connector, fixed_mode);
ed92f0b2
PZ		 5132 break;
5133 }
5134 }
5135
5136 /* fallback to VBT if available for eDP */
5137 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5138 fixed_mode = drm_mode_duplicate(dev,
5139 dev_priv->vbt.lfp_lvds_vbt_mode);
5140 if (fixed_mode)
5141 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5142 }
060c8778 5143 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5144
01527b31
CT		 5145 if (IS_VALLEYVIEW(dev)) {
5146 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5147 register_reboot_notifier(&intel_dp->edp_notifier);
5148 }
5149
4f9db5b5 5150 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5151 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5152 intel_panel_setup_backlight(connector);
5153
5154 return true;
5155}
5156
16c25533 5157bool
f0fec3f2
PZ		 5158intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5159 struct intel_connector *intel_connector)
a4fc5ed6 5160{
f0fec3f2
PZ		 5161 struct drm_connector *connector = &intel_connector->base;
5162 struct intel_dp *intel_dp = &intel_dig_port->dp;
5163 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5164 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5165 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5166 enum port port = intel_dig_port->port;
0095e6dc 5167 struct edp_power_seq power_seq = { 0 };
0b99836f 5168 int type;
a4fc5ed6 5169
a4a5d2f8
VS		 5170 intel_dp->pps_pipe = INVALID_PIPE;
5171
ec5b01dd 5172 /* intel_dp vfuncs */
b6b5e383
DL		 5173 if (INTEL_INFO(dev)->gen >= 9)
5174 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5175 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5176 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5177 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5178 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5179 else if (HAS_PCH_SPLIT(dev))
5180 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5181 else
5182 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5183
b9ca5fad
DL		 5184 if (INTEL_INFO(dev)->gen >= 9)
5185 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5186 else
5187 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5188
0767935e
DV		 5189 /* Preserve the current hw state. */
5190 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5191 intel_dp->attached_connector = intel_connector;
3d3dc149 5192
3b32a35b 5193 if (intel_dp_is_edp(dev, port))
b329530c 5194 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5195 else
5196 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5197
f7d24902
ID		 5198 /*
5199 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5200 * for DP the encoder type can be set by the caller to
5201 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5202 */
5203 if (type == DRM_MODE_CONNECTOR_eDP)
5204 intel_encoder->type = INTEL_OUTPUT_EDP;
5205
e7281eab
ID		 5206 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5207 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5208 port_name(port));
5209
b329530c 5210 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5211 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5212
a4fc5ed6
KP		 5213 connector->interlace_allowed = true;
5214 connector->doublescan_allowed = 0;
5215
f0fec3f2 5216 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5217 edp_panel_vdd_work);
a4fc5ed6 5218
df0e9248 5219 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5220 drm_connector_register(connector);
a4fc5ed6 5221
affa9354 5222 if (HAS_DDI(dev))
bcbc889b
PZ		 5223 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5224 else
5225 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5226 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5227
0b99836f 5228 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5229 switch (port) {
5230 case PORT_A:
1d843f9d 5231 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5232 break;
5233 case PORT_B:
1d843f9d 5234 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5235 break;
5236 case PORT_C:
1d843f9d 5237 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5238 break;
5239 case PORT_D:
1d843f9d 5240 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5241 break;
5242 default:
ad1c0b19 5243 BUG();
5eb08b69
ZW		 5244 }
5245
dada1a9f 5246 if (is_edp(intel_dp)) {
773538e8 5247 pps_lock(intel_dp);
a4a5d2f8
VS		 5248 if (IS_VALLEYVIEW(dev)) {
5249 vlv_initial_power_sequencer_setup(intel_dp);
5250 } else {
5251 intel_dp_init_panel_power_timestamps(intel_dp);
5252 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5253 &power_seq);
5254 }
773538e8 5255 pps_unlock(intel_dp);
dada1a9f 5256 }
0095e6dc 5257
9d1a1031 5258 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5259
0e32b39c
DA		 5260 /* init MST on ports that can support it */
5261 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5262 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5263 intel_dp_mst_encoder_init(intel_dig_port,
5264 intel_connector->base.base.id);
0e32b39c
DA		 5265 }
5266 }
5267
0095e6dc 5268 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5269 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5270 if (is_edp(intel_dp)) {
5271 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5272 /*
5273 * vdd might still be enabled do to the delayed vdd off.
5274 * Make sure vdd is actually turned off here.
5275 */
773538e8 5276 pps_lock(intel_dp);
4be73780 5277 edp_panel_vdd_off_sync(intel_dp);
773538e8 5278 pps_unlock(intel_dp);
15b1d171 5279 }
34ea3d38 5280 drm_connector_unregister(connector);
b2f246a8 5281 drm_connector_cleanup(connector);
16c25533 5282 return false;
b2f246a8 5283 }
32f9d658 5284
f684960e
CW		 5285 intel_dp_add_properties(intel_dp, connector);
5286
a4fc5ed6
KP		 5287 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5288 * 0xd. Failure to do so will result in spurious interrupts being
5289 * generated on the port when a cable is not attached.
5290 */
5291 if (IS_G4X(dev) && !IS_GM45(dev)) {
5292 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5293 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5294 }
16c25533
PZ		 5295
5296 return true;
a4fc5ed6 5297}
f0fec3f2
PZ		 5298
5299void
5300intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5301{
13cf5504 5302 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5303 struct intel_digital_port *intel_dig_port;
5304 struct intel_encoder *intel_encoder;
5305 struct drm_encoder *encoder;
5306 struct intel_connector *intel_connector;
5307
b14c5679 5308 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5309 if (!intel_dig_port)
5310 return;
5311
b14c5679 5312 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5313 if (!intel_connector) {
5314 kfree(intel_dig_port);
5315 return;
5316 }
5317
5318 intel_encoder = &intel_dig_port->base;
5319 encoder = &intel_encoder->base;
5320
5321 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5322 DRM_MODE_ENCODER_TMDS);
5323
5bfe2ac0 5324 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5325 intel_encoder->disable = intel_disable_dp;
00c09d70 5326 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5327 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5328 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5329 if (IS_CHERRYVIEW(dev)) {
9197c88b 5330 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5331 intel_encoder->pre_enable = chv_pre_enable_dp;
5332 intel_encoder->enable = vlv_enable_dp;
580d3811 5333 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5334 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5335 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5336 intel_encoder->pre_enable = vlv_pre_enable_dp;
5337 intel_encoder->enable = vlv_enable_dp;
49277c31 5338 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5339 } else {
ecff4f3b
JN		 5340 intel_encoder->pre_enable = g4x_pre_enable_dp;
5341 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5342 if (INTEL_INFO(dev)->gen >= 5)
5343 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5344 }
f0fec3f2 5345
174edf1f 5346 intel_dig_port->port = port;
f0fec3f2
PZ		 5347 intel_dig_port->dp.output_reg = output_reg;
5348
00c09d70 5349 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5350 if (IS_CHERRYVIEW(dev)) {
5351 if (port == PORT_D)
5352 intel_encoder->crtc_mask = 1 << 2;
5353 else
5354 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5355 } else {
5356 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5357 }
bc079e8b 5358 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5359 intel_encoder->hot_plug = intel_dp_hot_plug;
5360
13cf5504
DA		 5361 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5362 dev_priv->hpd_irq_port[port] = intel_dig_port;
5363
15b1d171
PZ		 5364 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5365 drm_encoder_cleanup(encoder);
5366 kfree(intel_dig_port);
b2f246a8 5367 kfree(intel_connector);
15b1d171 5368 }
f0fec3f2 5369}
0e32b39c
DA		 5370
5371void intel_dp_mst_suspend(struct drm_device *dev)
5372{
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 int i;
5375
5376 /* disable MST */
5377 for (i = 0; i < I915_MAX_PORTS; i++) {
5378 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5379 if (!intel_dig_port)
5380 continue;
5381
5382 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5383 if (!intel_dig_port->dp.can_mst)
5384 continue;
5385 if (intel_dig_port->dp.is_mst)
5386 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5387 }
5388 }
5389}
5390
5391void intel_dp_mst_resume(struct drm_device *dev)
5392{
5393 struct drm_i915_private *dev_priv = dev->dev_private;
5394 int i;
5395
5396 for (i = 0; i < I915_MAX_PORTS; i++) {
5397 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5398 if (!intel_dig_port)
5399 continue;
5400 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5401 int ret;
5402
5403 if (!intel_dig_port->dp.can_mst)
5404 continue;
5405
5406 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5407 if (ret != 0) {
5408 intel_dp_check_mst_status(&intel_dig_port->dp);
5409 }
5410 }
5411 }
5412}
Linux 6.x block layer and io_uring tree(s)