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drm/i915: Kill crtc->plane checks from the primary plane update hooks
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
d4eead50 113 break;
a4fc5ed6 114 default:
d4eead50
ID		 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
a4fc5ed6
KP		 117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121}
122
cd9dde44
AJ		 123/*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
a4fc5ed6 140static int
c898261c 141intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 142{
cd9dde44 143 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 144}
145
fe27d53e
DA		 146static int
147intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148{
149 return (max_link_clock * max_lanes * 8) / 10;
150}
151
c19de8eb 152static enum drm_mode_status
a4fc5ed6
KP		 153intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155{
df0e9248 156 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 161
dd06f90e
JN		 162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 164 return MODE_PANEL;
165
dd06f90e 166 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 167 return MODE_PANEL;
03afc4a2
DV		 168
169 target_clock = fixed_mode->clock;
7de56f43
ZY		 170 }
171
36008365
DV		 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
c4867936 179 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
0af78a2b
DV		 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
a4fc5ed6
KP		 187 return MODE_OK;
188}
189
190static uint32_t
191pack_aux(uint8_t *src, int src_bytes)
192{
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201}
202
203static void
204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205{
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211}
212
fb0f8fbf
KP		 213/* hrawclock is 1/4 the FSB frequency */
214static int
215intel_hrawclk(struct drm_device *dev)
216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
9473c8f4
VP		 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
fb0f8fbf
KP		 224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245}
246
bf13e81b
JN		 247static void
248intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251static void
252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256static enum pipe
257vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258{
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282}
283
284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285{
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292}
293
294static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302}
303
4be73780 304static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 305{
30add22d 306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 307 struct drm_i915_private *dev_priv = dev->dev_private;
308
bf13e81b 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 310}
311
4be73780 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 313{
30add22d 314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 315 struct drm_i915_private *dev_priv = dev->dev_private;
316
efbc20ab
PZ		 317 return !dev_priv->pm.suspended &&
318 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 319}
320
9b984dae
KP		 321static void
322intel_dp_check_edp(struct intel_dp *intel_dp)
323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 325 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 326
9b984dae
KP		 327 if (!is_edp(intel_dp))
328 return;
453c5420 329
4be73780 330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 335 }
336}
337
9ee32fea
DV		 338static uint32_t
339intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
340{
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 345 uint32_t status;
346 bool done;
347
ef04f00d 348#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 349 if (has_aux_irq)
b18ac466 350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 351 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 352 else
353 done = wait_for_atomic(C, 10) == 0;
354 if (!done)
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
356 has_aux_irq);
357#undef C
358
359 return status;
360}
361
ec5b01dd 362static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 363{
174edf1f
PZ		 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 366
ec5b01dd
DL		 367 /*
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 370 */
ec5b01dd
DL		 371 return index ? 0 : intel_hrawclk(dev) / 2;
372}
373
374static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
375{
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
378
379 if (index)
380 return 0;
381
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 385 else
b84a1cf8 386 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 387 } else {
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 }
390}
391
392static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
393{
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397
398 if (intel_dig_port->port == PORT_A) {
399 if (index)
400 return 0;
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
bc86625a
CW		 404 switch (index) {
405 case 0: return 63;
406 case 1: return 72;
407 default: return 0;
408 }
ec5b01dd 409 } else {
bc86625a 410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 411 }
b84a1cf8
RV		 412}
413
ec5b01dd
DL		 414static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 return index ? 0 : 100;
417}
418
5ed12a19
DL		 419static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
420 bool has_aux_irq,
421 int send_bytes,
422 uint32_t aux_clock_divider)
423{
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
427
428 if (IS_GEN6(dev))
429 precharge = 3;
430 else
431 precharge = 5;
432
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
435 else
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
437
438 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 439 DP_AUX_CH_CTL_DONE |
5ed12a19 440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 442 timeout |
788d4433 443 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 447}
448
b84a1cf8
RV		 449static int
450intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
453{
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
bc86625a 459 uint32_t aux_clock_divider;
b84a1cf8
RV		 460 int i, ret, recv_bytes;
461 uint32_t status;
5ed12a19 462 int try, clock = 0;
4e6b788c 463 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 464 bool vdd;
465
466 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 467
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
470 * deep sleep states.
471 */
472 pm_qos_update_request(&dev_priv->pm_qos, 0);
473
474 intel_dp_check_edp(intel_dp);
5eb08b69 475
c67a470b
PZ		 476 intel_aux_display_runtime_get(dev_priv);
477
11bee43e
JB		 478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
ef04f00d 480 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
482 break;
483 msleep(1);
484 }
485
486 if (try == 3) {
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
488 I915_READ(ch_ctl));
9ee32fea
DV		 489 ret = -EBUSY;
490 goto out;
4f7f7b7e
CW		 491 }
492
46a5ae9f
PZ		 493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
495 ret = -E2BIG;
496 goto out;
497 }
498
ec5b01dd 499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
501 has_aux_irq,
502 send_bytes,
503 aux_clock_divider);
5ed12a19 504
bc86625a
CW		 505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i = 0; i < send_bytes; i += 4)
509 I915_WRITE(ch_data + i,
510 pack_aux(send + i, send_bytes - i));
511
512 /* Send the command and wait for it to complete */
5ed12a19 513 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 514
515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
516
517 /* Clear done status and any errors */
518 I915_WRITE(ch_ctl,
519 status |
520 DP_AUX_CH_CTL_DONE |
521 DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR);
523
524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
525 DP_AUX_CH_CTL_RECEIVE_ERROR))
526 continue;
527 if (status & DP_AUX_CH_CTL_DONE)
528 break;
529 }
4f7f7b7e 530 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 531 break;
532 }
533
a4fc5ed6 534 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 536 ret = -EBUSY;
537 goto out;
a4fc5ed6
KP		 538 }
539
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
542 */
a5b3da54 543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 545 ret = -EIO;
546 goto out;
a5b3da54 547 }
1ae8c0a5
KP		 548
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
a5b3da54 551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 553 ret = -ETIMEDOUT;
554 goto out;
a4fc5ed6
KP		 555 }
556
557 /* Unload any bytes sent back from the other side */
558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 560 if (recv_bytes > recv_size)
561 recv_bytes = recv_size;
0206e353 562
4f7f7b7e
CW		 563 for (i = 0; i < recv_bytes; i += 4)
564 unpack_aux(I915_READ(ch_data + i),
565 recv + i, recv_bytes - i);
a4fc5ed6 566
9ee32fea
DV		 567 ret = recv_bytes;
568out:
569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 570 intel_aux_display_runtime_put(dev_priv);
9ee32fea 571
884f19e9
JN		 572 if (vdd)
573 edp_panel_vdd_off(intel_dp, false);
574
9ee32fea 575 return ret;
a4fc5ed6
KP		 576}
577
9d1a1031
JN		 578#define HEADER_SIZE 4
579static ssize_t
580intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 581{
9d1a1031
JN		 582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
583 uint8_t txbuf[20], rxbuf[20];
584 size_t txsize, rxsize;
a4fc5ed6 585 int ret;
a4fc5ed6 586
9d1a1031
JN		 587 txbuf[0] = msg->request << 4;
588 txbuf[1] = msg->address >> 8;
589 txbuf[2] = msg->address & 0xff;
590 txbuf[3] = msg->size - 1;
46a5ae9f 591
9d1a1031
JN		 592 switch (msg->request & ~DP_AUX_I2C_MOT) {
593 case DP_AUX_NATIVE_WRITE:
594 case DP_AUX_I2C_WRITE:
595 txsize = HEADER_SIZE + msg->size;
596 rxsize = 1;
f51a44b9 597
9d1a1031
JN		 598 if (WARN_ON(txsize > 20))
599 return -E2BIG;
a4fc5ed6 600
9d1a1031 601 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 602
9d1a1031
JN		 603 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
604 if (ret > 0) {
605 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 606
9d1a1031
JN		 607 /* Return payload size. */
608 ret = msg->size;
609 }
610 break;
46a5ae9f 611
9d1a1031
JN		 612 case DP_AUX_NATIVE_READ:
613 case DP_AUX_I2C_READ:
614 txsize = HEADER_SIZE;
615 rxsize = msg->size + 1;
a4fc5ed6 616
9d1a1031
JN		 617 if (WARN_ON(rxsize > 20))
618 return -E2BIG;
a4fc5ed6 619
9d1a1031
JN		 620 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
621 if (ret > 0) {
622 msg->reply = rxbuf[0] >> 4;
623 /*
624 * Assume happy day, and copy the data. The caller is
625 * expected to check msg->reply before touching it.
626 *
627 * Return payload size.
628 */
629 ret--;
630 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 631 }
9d1a1031
JN		 632 break;
633
634 default:
635 ret = -EINVAL;
636 break;
a4fc5ed6 637 }
f51a44b9 638
9d1a1031 639 return ret;
a4fc5ed6
KP		 640}
641
9d1a1031
JN		 642static void
643intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
644{
645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 646 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
647 enum port port = intel_dig_port->port;
0b99836f 648 const char *name = NULL;
ab2c0672
DA		 649 int ret;
650
33ad6626
JN		 651 switch (port) {
652 case PORT_A:
653 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 654 name = "DPDDC-A";
ab2c0672 655 break;
33ad6626
JN		 656 case PORT_B:
657 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 658 name = "DPDDC-B";
ab2c0672 659 break;
33ad6626
JN		 660 case PORT_C:
661 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 662 name = "DPDDC-C";
ab2c0672 663 break;
33ad6626
JN		 664 case PORT_D:
665 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 666 name = "DPDDC-D";
33ad6626
JN		 667 break;
668 default:
669 BUG();
ab2c0672
DA		 670 }
671
33ad6626
JN		 672 if (!HAS_DDI(dev))
673 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 674
0b99836f 675 intel_dp->aux.name = name;
9d1a1031
JN		 676 intel_dp->aux.dev = dev->dev;
677 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 678
0b99836f
JN		 679 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
680 connector->base.kdev->kobj.name);
8316f337 681
0b99836f
JN		 682 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
683 if (ret < 0) {
684 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
685 name, ret);
686 return;
ab2c0672 687 }
8a5e6aeb 688
0b99836f
JN		 689 ret = sysfs_create_link(&connector->base.kdev->kobj,
690 &intel_dp->aux.ddc.dev.kobj,
691 intel_dp->aux.ddc.dev.kobj.name);
692 if (ret < 0) {
693 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
694 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 695 }
a4fc5ed6
KP		 696}
697
80f65de3
ID		 698static void
699intel_dp_connector_unregister(struct intel_connector *intel_connector)
700{
701 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
702
703 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 704 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 705 intel_connector_unregister(intel_connector);
706}
707
c6bb3538
DV		 708static void
709intel_dp_set_clock(struct intel_encoder *encoder,
710 struct intel_crtc_config *pipe_config, int link_bw)
711{
712 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 713 const struct dp_link_dpll *divisor = NULL;
714 int i, count = 0;
c6bb3538
DV		 715
716 if (IS_G4X(dev)) {
9dd4ffdf
CML		 717 divisor = gen4_dpll;
718 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 719 } else if (IS_HASWELL(dev)) {
720 /* Haswell has special-purpose DP DDI clocks. */
721 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 722 divisor = pch_dpll;
723 count = ARRAY_SIZE(pch_dpll);
c6bb3538 724 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 725 divisor = vlv_dpll;
726 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 727 }
9dd4ffdf
CML		 728
729 if (divisor && count) {
730 for (i = 0; i < count; i++) {
731 if (link_bw == divisor[i].link_bw) {
732 pipe_config->dpll = divisor[i].dpll;
733 pipe_config->clock_set = true;
734 break;
735 }
736 }
c6bb3538
DV		 737 }
738}
739
00c09d70 740bool
5bfe2ac0
DV		 741intel_dp_compute_config(struct intel_encoder *encoder,
742 struct intel_crtc_config *pipe_config)
a4fc5ed6 743{
5bfe2ac0 744 struct drm_device *dev = encoder->base.dev;
36008365 745 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 746 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 747 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 748 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 749 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 750 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 751 int lane_count, clock;
397fe157 752 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 753 /* Conveniently, the link BW constants become indices with a shift...*/
754 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 755 int bpp, mode_rate;
06ea66b6 756 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 757 int link_avail, link_clock;
a4fc5ed6 758
bc7d38a4 759 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 760 pipe_config->has_pch_encoder = true;
761
03afc4a2 762 pipe_config->has_dp_encoder = true;
a4fc5ed6 763
dd06f90e
JN		 764 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
765 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
766 adjusted_mode);
2dd24552
JB		 767 if (!HAS_PCH_SPLIT(dev))
768 intel_gmch_panel_fitting(intel_crtc, pipe_config,
769 intel_connector->panel.fitting_mode);
770 else
b074cec8
JB		 771 intel_pch_panel_fitting(intel_crtc, pipe_config,
772 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 773 }
774
cb1793ce 775 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 776 return false;
777
083f9560
DV		 778 DRM_DEBUG_KMS("DP link computation with max lane count %i "
779 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 780 max_lane_count, bws[max_clock],
781 adjusted_mode->crtc_clock);
083f9560 782
36008365
DV		 783 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
784 * bpc in between. */
3e7ca985 785 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 786 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
787 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 788 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
789 dev_priv->vbt.edp_bpp);
6da7f10d 790 bpp = dev_priv->vbt.edp_bpp;
7984211e 791 }
657445fe 792
36008365 793 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 794 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
795 bpp);
36008365 796
38aecea0
DV		 797 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
798 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 799 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
800 link_avail = intel_dp_max_data_rate(link_clock,
801 lane_count);
802
803 if (mode_rate <= link_avail) {
804 goto found;
805 }
806 }
807 }
808 }
c4867936 809
36008365 810 return false;
3685a8f3 811
36008365 812found:
55bc60db
VS		 813 if (intel_dp->color_range_auto) {
814 /*
815 * See:
816 * CEA-861-E - 5.1 Default Encoding Parameters
817 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
818 */
18316c8c 819 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 820 intel_dp->color_range = DP_COLOR_RANGE_16_235;
821 else
822 intel_dp->color_range = 0;
823 }
824
3685a8f3 825 if (intel_dp->color_range)
50f3b016 826 pipe_config->limited_color_range = true;
a4fc5ed6 827
36008365
DV		 828 intel_dp->link_bw = bws[clock];
829 intel_dp->lane_count = lane_count;
657445fe 830 pipe_config->pipe_bpp = bpp;
ff9a6750 831 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 832
36008365
DV		 833 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
834 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 835 pipe_config->port_clock, bpp);
36008365
DV		 836 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
837 mode_rate, link_avail);
a4fc5ed6 838
03afc4a2 839 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 840 adjusted_mode->crtc_clock,
841 pipe_config->port_clock,
03afc4a2 842 &pipe_config->dp_m_n);
9d1a455b 843
c6bb3538
DV		 844 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
845
03afc4a2 846 return true;
a4fc5ed6
KP		 847}
848
7c62a164 849static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 850{
7c62a164
DV		 851 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
852 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
853 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 854 struct drm_i915_private *dev_priv = dev->dev_private;
855 u32 dpa_ctl;
856
ff9a6750 857 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 858 dpa_ctl = I915_READ(DP_A);
859 dpa_ctl &= ~DP_PLL_FREQ_MASK;
860
ff9a6750 861 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 862 /* For a long time we've carried around a ILK-DevA w/a for the
863 * 160MHz clock. If we're really unlucky, it's still required.
864 */
865 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 866 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 867 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 868 } else {
869 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 870 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 871 }
1ce17038 872
ea9b6006
DV		 873 I915_WRITE(DP_A, dpa_ctl);
874
875 POSTING_READ(DP_A);
876 udelay(500);
877}
878
b934223d 879static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 880{
b934223d 881 struct drm_device *dev = encoder->base.dev;
417e822d 882 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 883 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 884 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 885 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
886 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 887
417e822d 888 /*
1a2eb460 889 * There are four kinds of DP registers:
417e822d
KP		 890 *
891 * IBX PCH
1a2eb460
KP		 892 * SNB CPU
893 * IVB CPU
417e822d
KP		 894 * CPT PCH
895 *
896 * IBX PCH and CPU are the same for almost everything,
897 * except that the CPU DP PLL is configured in this
898 * register
899 *
900 * CPT PCH is quite different, having many bits moved
901 * to the TRANS_DP_CTL register instead. That
902 * configuration happens (oddly) in ironlake_pch_enable
903 */
9c9e7927 904
417e822d
KP		 905 /* Preserve the BIOS-computed detected bit. This is
906 * supposed to be read-only.
907 */
908 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 909
417e822d 910 /* Handle DP bits in common between all three register formats */
417e822d 911 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 912 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 913
e0dac65e
WF		 914 if (intel_dp->has_audio) {
915 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 916 pipe_name(crtc->pipe));
ea5b213a 917 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 918 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 919 }
247d89f6 920
417e822d 921 /* Split out the IBX/CPU vs CPT settings */
32f9d658 922
bc7d38a4 923 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 924 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
925 intel_dp->DP |= DP_SYNC_HS_HIGH;
926 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
927 intel_dp->DP |= DP_SYNC_VS_HIGH;
928 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
929
6aba5b6c 930 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 931 intel_dp->DP |= DP_ENHANCED_FRAMING;
932
7c62a164 933 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 934 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 935 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 936 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 937
938 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
939 intel_dp->DP |= DP_SYNC_HS_HIGH;
940 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
941 intel_dp->DP |= DP_SYNC_VS_HIGH;
942 intel_dp->DP |= DP_LINK_TRAIN_OFF;
943
6aba5b6c 944 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 945 intel_dp->DP |= DP_ENHANCED_FRAMING;
946
7c62a164 947 if (crtc->pipe == 1)
417e822d 948 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 949 } else {
950 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 951 }
ea9b6006 952
bc7d38a4 953 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 954 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 955}
956
ffd6749d
PZ		 957#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
958#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 959
1a5ef5b7
PZ		 960#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
961#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 962
ffd6749d
PZ		 963#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
964#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 965
4be73780 966static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 967 u32 mask,
968 u32 value)
bd943159 969{
30add22d 970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 971 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 972 u32 pp_stat_reg, pp_ctrl_reg;
973
bf13e81b
JN		 974 pp_stat_reg = _pp_stat_reg(intel_dp);
975 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 976
99ea7127 977 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 978 mask, value,
979 I915_READ(pp_stat_reg),
980 I915_READ(pp_ctrl_reg));
32ce697c 981
453c5420 982 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 983 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 984 I915_READ(pp_stat_reg),
985 I915_READ(pp_ctrl_reg));
32ce697c 986 }
54c136d4
CW		 987
988 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 989}
32ce697c 990
4be73780 991static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 992{
993 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 994 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 995}
996
4be73780 997static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 998{
999 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1000 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1001}
1002
4be73780 1003static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1004{
1005 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1006
1007 /* When we disable the VDD override bit last we have to do the manual
1008 * wait. */
1009 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1010 intel_dp->panel_power_cycle_delay);
1011
4be73780 1012 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1013}
1014
4be73780 1015static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1016{
1017 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1018 intel_dp->backlight_on_delay);
1019}
1020
4be73780 1021static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1022{
1023 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1024 intel_dp->backlight_off_delay);
1025}
99ea7127 1026
832dd3c1
KP		 1027/* Read the current pp_control value, unlocking the register if it
1028 * is locked
1029 */
1030
453c5420 1031static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1032{
453c5420
JB		 1033 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1035 u32 control;
832dd3c1 1036
bf13e81b 1037 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1038 control &= ~PANEL_UNLOCK_MASK;
1039 control |= PANEL_UNLOCK_REGS;
1040 return control;
bd943159
KP		 1041}
1042
adddaaf4 1043static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1044{
30add22d 1045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1046 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1047 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1048 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1049 enum intel_display_power_domain power_domain;
5d613501 1050 u32 pp;
453c5420 1051 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1052 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1053
97af61f5 1054 if (!is_edp(intel_dp))
adddaaf4 1055 return false;
bd943159
KP		 1056
1057 intel_dp->want_panel_vdd = true;
99ea7127 1058
4be73780 1059 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1060 return need_to_disable;
b0665d57 1061
4e6e1a54
ID		 1062 power_domain = intel_display_port_power_domain(intel_encoder);
1063 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1064
b0665d57 1065 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1066
4be73780
DV		 1067 if (!edp_have_panel_power(intel_dp))
1068 wait_panel_power_cycle(intel_dp);
99ea7127 1069
453c5420 1070 pp = ironlake_get_pp_control(intel_dp);
5d613501 1071 pp |= EDP_FORCE_VDD;
ebf33b18 1072
bf13e81b
JN		 1073 pp_stat_reg = _pp_stat_reg(intel_dp);
1074 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1075
1076 I915_WRITE(pp_ctrl_reg, pp);
1077 POSTING_READ(pp_ctrl_reg);
1078 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1079 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1080 /*
1081 * If the panel wasn't on, delay before accessing aux channel
1082 */
4be73780 1083 if (!edp_have_panel_power(intel_dp)) {
bd943159 1084 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1085 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1086 }
adddaaf4
JN		 1087
1088 return need_to_disable;
1089}
1090
b80d6c78 1091void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1092{
1093 if (is_edp(intel_dp)) {
1094 bool vdd = _edp_panel_vdd_on(intel_dp);
1095
1096 WARN(!vdd, "eDP VDD already requested on\n");
1097 }
5d613501
JB		 1098}
1099
4be73780 1100static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1101{
30add22d 1102 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1103 struct drm_i915_private *dev_priv = dev->dev_private;
1104 u32 pp;
453c5420 1105 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1106
a0e99e68
DV		 1107 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1108
4be73780 1109 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1110 struct intel_digital_port *intel_dig_port =
1111 dp_to_dig_port(intel_dp);
1112 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1113 enum intel_display_power_domain power_domain;
1114
b0665d57
PZ		 1115 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1116
453c5420 1117 pp = ironlake_get_pp_control(intel_dp);
bd943159 1118 pp &= ~EDP_FORCE_VDD;
bd943159 1119
9f08ef59
PZ		 1120 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1121 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1122
1123 I915_WRITE(pp_ctrl_reg, pp);
1124 POSTING_READ(pp_ctrl_reg);
99ea7127 1125
453c5420
JB		 1126 /* Make sure sequencer is idle before allowing subsequent activity */
1127 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1128 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1129
1130 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1131 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1132
4e6e1a54
ID		 1133 power_domain = intel_display_port_power_domain(intel_encoder);
1134 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1135 }
1136}
5d613501 1137
4be73780 1138static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1139{
1140 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1141 struct intel_dp, panel_vdd_work);
30add22d 1142 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1143
627f7675 1144 mutex_lock(&dev->mode_config.mutex);
4be73780 1145 edp_panel_vdd_off_sync(intel_dp);
627f7675 1146 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1147}
1148
4be73780 1149static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1150{
97af61f5
KP		 1151 if (!is_edp(intel_dp))
1152 return;
5d613501 1153
bd943159 1154 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1155
bd943159
KP		 1156 intel_dp->want_panel_vdd = false;
1157
1158 if (sync) {
4be73780 1159 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1160 } else {
1161 /*
1162 * Queue the timer to fire a long
1163 * time from now (relative to the power down delay)
1164 * to keep the panel power up across a sequence of operations
1165 */
1166 schedule_delayed_work(&intel_dp->panel_vdd_work,
1167 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1168 }
5d613501
JB		 1169}
1170
4be73780 1171void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1172{
30add22d 1173 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1174 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1175 u32 pp;
453c5420 1176 u32 pp_ctrl_reg;
9934c132 1177
97af61f5 1178 if (!is_edp(intel_dp))
bd943159 1179 return;
99ea7127
KP		 1180
1181 DRM_DEBUG_KMS("Turn eDP power on\n");
1182
4be73780 1183 if (edp_have_panel_power(intel_dp)) {
99ea7127 1184 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1185 return;
99ea7127 1186 }
9934c132 1187
4be73780 1188 wait_panel_power_cycle(intel_dp);
37c6c9b0 1189
bf13e81b 1190 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1191 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1192 if (IS_GEN5(dev)) {
1193 /* ILK workaround: disable reset around power sequence */
1194 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1195 I915_WRITE(pp_ctrl_reg, pp);
1196 POSTING_READ(pp_ctrl_reg);
05ce1a49 1197 }
37c6c9b0 1198
1c0ae80a 1199 pp |= POWER_TARGET_ON;
99ea7127
KP		 1200 if (!IS_GEN5(dev))
1201 pp |= PANEL_POWER_RESET;
1202
453c5420
JB		 1203 I915_WRITE(pp_ctrl_reg, pp);
1204 POSTING_READ(pp_ctrl_reg);
9934c132 1205
4be73780 1206 wait_panel_on(intel_dp);
dce56b3c 1207 intel_dp->last_power_on = jiffies;
9934c132 1208
05ce1a49
KP		 1209 if (IS_GEN5(dev)) {
1210 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1211 I915_WRITE(pp_ctrl_reg, pp);
1212 POSTING_READ(pp_ctrl_reg);
05ce1a49 1213 }
9934c132
JB		 1214}
1215
4be73780 1216void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1217{
4e6e1a54
ID		 1218 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1219 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1221 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1222 enum intel_display_power_domain power_domain;
99ea7127 1223 u32 pp;
453c5420 1224 u32 pp_ctrl_reg;
9934c132 1225
97af61f5
KP		 1226 if (!is_edp(intel_dp))
1227 return;
37c6c9b0 1228
99ea7127 1229 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1230
4be73780 1231 edp_wait_backlight_off(intel_dp);
dce56b3c 1232
24f3e092
JN		 1233 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1234
453c5420 1235 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1236 /* We need to switch off panel power _and_ force vdd, for otherwise some
1237 * panels get very unhappy and cease to work. */
b3064154
PJ		 1238 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1239 EDP_BLC_ENABLE);
453c5420 1240
bf13e81b 1241 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1242
849e39f5
PZ		 1243 intel_dp->want_panel_vdd = false;
1244
453c5420
JB		 1245 I915_WRITE(pp_ctrl_reg, pp);
1246 POSTING_READ(pp_ctrl_reg);
9934c132 1247
dce56b3c 1248 intel_dp->last_power_cycle = jiffies;
4be73780 1249 wait_panel_off(intel_dp);
849e39f5
PZ		 1250
1251 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1252 power_domain = intel_display_port_power_domain(intel_encoder);
1253 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1254}
1255
4be73780 1256void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1257{
da63a9f2
PZ		 1258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1259 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 u32 pp;
453c5420 1262 u32 pp_ctrl_reg;
32f9d658 1263
f01eca2e
KP		 1264 if (!is_edp(intel_dp))
1265 return;
1266
28c97730 1267 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1268 /*
1269 * If we enable the backlight right away following a panel power
1270 * on, we may see slight flicker as the panel syncs with the eDP
1271 * link. So delay a bit to make sure the image is solid before
1272 * allowing it to appear.
1273 */
4be73780 1274 wait_backlight_on(intel_dp);
453c5420 1275 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1276 pp |= EDP_BLC_ENABLE;
453c5420 1277
bf13e81b 1278 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1279
1280 I915_WRITE(pp_ctrl_reg, pp);
1281 POSTING_READ(pp_ctrl_reg);
035aa3de 1282
752aa88a 1283 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1284}
1285
4be73780 1286void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1287{
30add22d 1288 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1289 struct drm_i915_private *dev_priv = dev->dev_private;
1290 u32 pp;
453c5420 1291 u32 pp_ctrl_reg;
32f9d658 1292
f01eca2e
KP		 1293 if (!is_edp(intel_dp))
1294 return;
1295
752aa88a 1296 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1297
28c97730 1298 DRM_DEBUG_KMS("\n");
453c5420 1299 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1300 pp &= ~EDP_BLC_ENABLE;
453c5420 1301
bf13e81b 1302 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1303
1304 I915_WRITE(pp_ctrl_reg, pp);
1305 POSTING_READ(pp_ctrl_reg);
dce56b3c 1306 intel_dp->last_backlight_off = jiffies;
32f9d658 1307}
a4fc5ed6 1308
2bd2ad64 1309static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1310{
da63a9f2
PZ		 1311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1312 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1313 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1314 struct drm_i915_private *dev_priv = dev->dev_private;
1315 u32 dpa_ctl;
1316
2bd2ad64
DV		 1317 assert_pipe_disabled(dev_priv,
1318 to_intel_crtc(crtc)->pipe);
1319
d240f20f
JB		 1320 DRM_DEBUG_KMS("\n");
1321 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1322 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1323 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1324
1325 /* We don't adjust intel_dp->DP while tearing down the link, to
1326 * facilitate link retraining (e.g. after hotplug). Hence clear all
1327 * enable bits here to ensure that we don't enable too much. */
1328 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1329 intel_dp->DP |= DP_PLL_ENABLE;
1330 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1331 POSTING_READ(DP_A);
1332 udelay(200);
d240f20f
JB		 1333}
1334
2bd2ad64 1335static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1336{
da63a9f2
PZ		 1337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1338 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1339 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1340 struct drm_i915_private *dev_priv = dev->dev_private;
1341 u32 dpa_ctl;
1342
2bd2ad64
DV		 1343 assert_pipe_disabled(dev_priv,
1344 to_intel_crtc(crtc)->pipe);
1345
d240f20f 1346 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1347 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1348 "dp pll off, should be on\n");
1349 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1350
1351 /* We can't rely on the value tracked for the DP register in
1352 * intel_dp->DP because link_down must not change that (otherwise link
1353 * re-training will fail. */
298b0b39 1354 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1355 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1356 POSTING_READ(DP_A);
d240f20f
JB		 1357 udelay(200);
1358}
1359
c7ad3810 1360/* If the sink supports it, try to set the power state appropriately */
c19b0669 1361void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1362{
1363 int ret, i;
1364
1365 /* Should have a valid DPCD by this point */
1366 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1367 return;
1368
1369 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1370 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1371 DP_SET_POWER_D3);
c7ad3810
JB		 1372 if (ret != 1)
1373 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1374 } else {
1375 /*
1376 * When turning on, we need to retry for 1ms to give the sink
1377 * time to wake up.
1378 */
1379 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1380 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1381 DP_SET_POWER_D0);
c7ad3810
JB		 1382 if (ret == 1)
1383 break;
1384 msleep(1);
1385 }
1386 }
1387}
1388
19d8fe15
DV		 1389static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1390 enum pipe *pipe)
d240f20f 1391{
19d8fe15 1392 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1393 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1394 struct drm_device *dev = encoder->base.dev;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1396 enum intel_display_power_domain power_domain;
1397 u32 tmp;
1398
1399 power_domain = intel_display_port_power_domain(encoder);
1400 if (!intel_display_power_enabled(dev_priv, power_domain))
1401 return false;
1402
1403 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1404
1405 if (!(tmp & DP_PORT_EN))
1406 return false;
1407
bc7d38a4 1408 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1409 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1410 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1411 *pipe = PORT_TO_PIPE(tmp);
1412 } else {
1413 u32 trans_sel;
1414 u32 trans_dp;
1415 int i;
1416
1417 switch (intel_dp->output_reg) {
1418 case PCH_DP_B:
1419 trans_sel = TRANS_DP_PORT_SEL_B;
1420 break;
1421 case PCH_DP_C:
1422 trans_sel = TRANS_DP_PORT_SEL_C;
1423 break;
1424 case PCH_DP_D:
1425 trans_sel = TRANS_DP_PORT_SEL_D;
1426 break;
1427 default:
1428 return true;
1429 }
1430
1431 for_each_pipe(i) {
1432 trans_dp = I915_READ(TRANS_DP_CTL(i));
1433 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1434 *pipe = i;
1435 return true;
1436 }
1437 }
19d8fe15 1438
4a0833ec
DV		 1439 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1440 intel_dp->output_reg);
1441 }
d240f20f 1442
19d8fe15
DV		 1443 return true;
1444}
d240f20f 1445
045ac3b5
JB		 1446static void intel_dp_get_config(struct intel_encoder *encoder,
1447 struct intel_crtc_config *pipe_config)
1448{
1449 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1450 u32 tmp, flags = 0;
63000ef6
XZ		 1451 struct drm_device *dev = encoder->base.dev;
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 enum port port = dp_to_dig_port(intel_dp)->port;
1454 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1455 int dotclock;
045ac3b5 1456
63000ef6
XZ		 1457 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1458 tmp = I915_READ(intel_dp->output_reg);
1459 if (tmp & DP_SYNC_HS_HIGH)
1460 flags |= DRM_MODE_FLAG_PHSYNC;
1461 else
1462 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1463
63000ef6
XZ		 1464 if (tmp & DP_SYNC_VS_HIGH)
1465 flags |= DRM_MODE_FLAG_PVSYNC;
1466 else
1467 flags |= DRM_MODE_FLAG_NVSYNC;
1468 } else {
1469 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1470 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1471 flags |= DRM_MODE_FLAG_PHSYNC;
1472 else
1473 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1474
63000ef6
XZ		 1475 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1476 flags |= DRM_MODE_FLAG_PVSYNC;
1477 else
1478 flags |= DRM_MODE_FLAG_NVSYNC;
1479 }
045ac3b5
JB		 1480
1481 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1482
eb14cb74
VS		 1483 pipe_config->has_dp_encoder = true;
1484
1485 intel_dp_get_m_n(crtc, pipe_config);
1486
18442d08 1487 if (port == PORT_A) {
f1f644dc
JB		 1488 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1489 pipe_config->port_clock = 162000;
1490 else
1491 pipe_config->port_clock = 270000;
1492 }
18442d08
VS		 1493
1494 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1495 &pipe_config->dp_m_n);
1496
1497 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1498 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1499
241bfc38 1500 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1501
c6cd2ee2
JN		 1502 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1503 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1504 /*
1505 * This is a big fat ugly hack.
1506 *
1507 * Some machines in UEFI boot mode provide us a VBT that has 18
1508 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1509 * unknown we fail to light up. Yet the same BIOS boots up with
1510 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1511 * max, not what it tells us to use.
1512 *
1513 * Note: This will still be broken if the eDP panel is not lit
1514 * up by the BIOS, and thus we can't get the mode at module
1515 * load.
1516 */
1517 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1518 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1519 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1520 }
045ac3b5
JB		 1521}
1522
a031d709 1523static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1524{
a031d709
RV		 1525 struct drm_i915_private *dev_priv = dev->dev_private;
1526
1527 return dev_priv->psr.sink_support;
2293bb5c
SK		 1528}
1529
2b28bb1b
RV		 1530static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1531{
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533
18b5992c 1534 if (!HAS_PSR(dev))
2b28bb1b
RV		 1535 return false;
1536
18b5992c 1537 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1538}
1539
1540static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1541 struct edp_vsc_psr *vsc_psr)
1542{
1543 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1544 struct drm_device *dev = dig_port->base.base.dev;
1545 struct drm_i915_private *dev_priv = dev->dev_private;
1546 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1547 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1548 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1549 uint32_t *data = (uint32_t *) vsc_psr;
1550 unsigned int i;
1551
1552 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1553 the video DIP being updated before program video DIP data buffer
1554 registers for DIP being updated. */
1555 I915_WRITE(ctl_reg, 0);
1556 POSTING_READ(ctl_reg);
1557
1558 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1559 if (i < sizeof(struct edp_vsc_psr))
1560 I915_WRITE(data_reg + i, *data++);
1561 else
1562 I915_WRITE(data_reg + i, 0);
1563 }
1564
1565 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1566 POSTING_READ(ctl_reg);
1567}
1568
1569static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1570{
1571 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 struct edp_vsc_psr psr_vsc;
1574
1575 if (intel_dp->psr_setup_done)
1576 return;
1577
1578 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1579 memset(&psr_vsc, 0, sizeof(psr_vsc));
1580 psr_vsc.sdp_header.HB0 = 0;
1581 psr_vsc.sdp_header.HB1 = 0x7;
1582 psr_vsc.sdp_header.HB2 = 0x2;
1583 psr_vsc.sdp_header.HB3 = 0x8;
1584 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1585
1586 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1587 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1588 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1589
1590 intel_dp->psr_setup_done = true;
1591}
1592
1593static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1594{
1595 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1596 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1597 uint32_t aux_clock_divider;
2b28bb1b
RV		 1598 int precharge = 0x3;
1599 int msg_size = 5; /* Header(4) + Message(1) */
1600
ec5b01dd
DL		 1601 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1602
2b28bb1b
RV		 1603 /* Enable PSR in sink */
1604 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1605 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1606 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1607 else
9d1a1031
JN		 1608 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1609 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1610
1611 /* Setup AUX registers */
18b5992c
BW		 1612 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1613 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1614 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1615 DP_AUX_CH_CTL_TIME_OUT_400us |
1616 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1617 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1618 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1619}
1620
1621static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1622{
1623 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 uint32_t max_sleep_time = 0x1f;
1626 uint32_t idle_frames = 1;
1627 uint32_t val = 0x0;
ed8546ac 1628 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1629
1630 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1631 val |= EDP_PSR_LINK_STANDBY;
1632 val |= EDP_PSR_TP2_TP3_TIME_0us;
1633 val |= EDP_PSR_TP1_TIME_0us;
1634 val |= EDP_PSR_SKIP_AUX_EXIT;
1635 } else
1636 val |= EDP_PSR_LINK_DISABLE;
1637
18b5992c 1638 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1639 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1640 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1641 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1642 EDP_PSR_ENABLE);
1643}
1644
3f51e471
RV		 1645static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1646{
1647 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1648 struct drm_device *dev = dig_port->base.base.dev;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 struct drm_crtc *crtc = dig_port->base.base.crtc;
1651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1652 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1653 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1654
a031d709
RV		 1655 dev_priv->psr.source_ok = false;
1656
18b5992c 1657 if (!HAS_PSR(dev)) {
3f51e471 1658 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1659 return false;
1660 }
1661
1662 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1663 (dig_port->port != PORT_A)) {
1664 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1665 return false;
1666 }
1667
d330a953 1668 if (!i915.enable_psr) {
105b7c11 1669 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1670 return false;
1671 }
1672
cd234b0b
CW		 1673 crtc = dig_port->base.base.crtc;
1674 if (crtc == NULL) {
1675 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1676 return false;
1677 }
1678
1679 intel_crtc = to_intel_crtc(crtc);
20ddf665 1680 if (!intel_crtc_active(crtc)) {
3f51e471 1681 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1682 return false;
1683 }
1684
cd234b0b 1685 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1686 if (obj->tiling_mode != I915_TILING_X ||
1687 obj->fence_reg == I915_FENCE_REG_NONE) {
1688 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1689 return false;
1690 }
1691
1692 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1693 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1694 return false;
1695 }
1696
1697 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1698 S3D_ENABLE) {
1699 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1700 return false;
1701 }
1702
ca73b4f0 1703 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1704 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1705 return false;
1706 }
1707
a031d709 1708 dev_priv->psr.source_ok = true;
3f51e471
RV		 1709 return true;
1710}
1711
3d739d92 1712static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1713{
1714 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1715
3f51e471
RV		 1716 if (!intel_edp_psr_match_conditions(intel_dp) ||
1717 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1718 return;
1719
1720 /* Setup PSR once */
1721 intel_edp_psr_setup(intel_dp);
1722
1723 /* Enable PSR on the panel */
1724 intel_edp_psr_enable_sink(intel_dp);
1725
1726 /* Enable PSR on the host */
1727 intel_edp_psr_enable_source(intel_dp);
1728}
1729
3d739d92
RV		 1730void intel_edp_psr_enable(struct intel_dp *intel_dp)
1731{
1732 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1733
1734 if (intel_edp_psr_match_conditions(intel_dp) &&
1735 !intel_edp_is_psr_enabled(dev))
1736 intel_edp_psr_do_enable(intel_dp);
1737}
1738
2b28bb1b
RV		 1739void intel_edp_psr_disable(struct intel_dp *intel_dp)
1740{
1741 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743
1744 if (!intel_edp_is_psr_enabled(dev))
1745 return;
1746
18b5992c
BW		 1747 I915_WRITE(EDP_PSR_CTL(dev),
1748 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1749
1750 /* Wait till PSR is idle */
18b5992c 1751 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1752 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1753 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1754}
1755
3d739d92
RV		 1756void intel_edp_psr_update(struct drm_device *dev)
1757{
1758 struct intel_encoder *encoder;
1759 struct intel_dp *intel_dp = NULL;
1760
1761 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1762 if (encoder->type == INTEL_OUTPUT_EDP) {
1763 intel_dp = enc_to_intel_dp(&encoder->base);
1764
a031d709 1765 if (!is_edp_psr(dev))
3d739d92
RV		 1766 return;
1767
1768 if (!intel_edp_psr_match_conditions(intel_dp))
1769 intel_edp_psr_disable(intel_dp);
1770 else
1771 if (!intel_edp_is_psr_enabled(dev))
1772 intel_edp_psr_do_enable(intel_dp);
1773 }
1774}
1775
e8cb4558 1776static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1777{
e8cb4558 1778 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1779 enum port port = dp_to_dig_port(intel_dp)->port;
1780 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1781
1782 /* Make sure the panel is off before trying to change the mode. But also
1783 * ensure that we have vdd while we switch off the panel. */
24f3e092 1784 intel_edp_panel_vdd_on(intel_dp);
4be73780 1785 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1786 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1787 intel_edp_panel_off(intel_dp);
3739850b
DV		 1788
1789 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1790 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1791 intel_dp_link_down(intel_dp);
d240f20f
JB		 1792}
1793
2bd2ad64 1794static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1795{
2bd2ad64 1796 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1797 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1798 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1799
982a3866 1800 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1801 intel_dp_link_down(intel_dp);
b2634017
JB		 1802 if (!IS_VALLEYVIEW(dev))
1803 ironlake_edp_pll_off(intel_dp);
3739850b 1804 }
2bd2ad64
DV		 1805}
1806
e8cb4558 1807static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1808{
e8cb4558
DV		 1809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1810 struct drm_device *dev = encoder->base.dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1813
0c33d8d7
DV		 1814 if (WARN_ON(dp_reg & DP_PORT_EN))
1815 return;
5d613501 1816
24f3e092 1817 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1818 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1819 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1820 intel_edp_panel_on(intel_dp);
1821 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1822 intel_dp_complete_link_train(intel_dp);
3ab9c637 1823 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1824}
89b667f8 1825
ecff4f3b
JN		 1826static void g4x_enable_dp(struct intel_encoder *encoder)
1827{
828f5c6e
JN		 1828 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1829
ecff4f3b 1830 intel_enable_dp(encoder);
4be73780 1831 intel_edp_backlight_on(intel_dp);
ab1f90f9 1832}
89b667f8 1833
ab1f90f9
JN		 1834static void vlv_enable_dp(struct intel_encoder *encoder)
1835{
828f5c6e
JN		 1836 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1837
4be73780 1838 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1839}
1840
ecff4f3b 1841static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1842{
1843 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1844 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1845
1846 if (dport->port == PORT_A)
1847 ironlake_edp_pll_on(intel_dp);
1848}
1849
1850static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1851{
2bd2ad64 1852 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1853 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1854 struct drm_device *dev = encoder->base.dev;
89b667f8 1855 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1856 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1857 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1858 int pipe = intel_crtc->pipe;
bf13e81b 1859 struct edp_power_seq power_seq;
ab1f90f9 1860 u32 val;
a4fc5ed6 1861
ab1f90f9 1862 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1863
ab3c759a 1864 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1865 val = 0;
1866 if (pipe)
1867 val |= (1<<21);
1868 else
1869 val &= ~(1<<21);
1870 val |= 0x001000c4;
ab3c759a
CML		 1871 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1872 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1873 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1874
ab1f90f9
JN		 1875 mutex_unlock(&dev_priv->dpio_lock);
1876
2cac613b
ID		 1877 if (is_edp(intel_dp)) {
1878 /* init power sequencer on this pipe and port */
1879 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1880 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1881 &power_seq);
1882 }
bf13e81b 1883
ab1f90f9
JN		 1884 intel_enable_dp(encoder);
1885
e4607fcf 1886 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1887}
1888
ecff4f3b 1889static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1890{
1891 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1892 struct drm_device *dev = encoder->base.dev;
1893 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1894 struct intel_crtc *intel_crtc =
1895 to_intel_crtc(encoder->base.crtc);
e4607fcf 1896 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1897 int pipe = intel_crtc->pipe;
89b667f8 1898
89b667f8 1899 /* Program Tx lane resets to default */
0980a60f 1900 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1902 DPIO_PCS_TX_LANE2_RESET |
1903 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1904 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1905 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1906 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1907 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1908 DPIO_PCS_CLK_SOFT_RESET);
1909
1910 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1911 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1912 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1913 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1914 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1915}
1916
1917/*
df0c237d
JB		 1918 * Native read with retry for link status and receiver capability reads for
1919 * cases where the sink may still be asleep.
9d1a1031
JN		 1920 *
1921 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1922 * supposed to retry 3 times per the spec.
a4fc5ed6 1923 */
9d1a1031
JN		 1924static ssize_t
1925intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1926 void *buffer, size_t size)
a4fc5ed6 1927{
9d1a1031
JN		 1928 ssize_t ret;
1929 int i;
61da5fab 1930
61da5fab 1931 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1932 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1933 if (ret == size)
1934 return ret;
61da5fab
JB		 1935 msleep(1);
1936 }
a4fc5ed6 1937
9d1a1031 1938 return ret;
a4fc5ed6
KP		 1939}
1940
1941/*
1942 * Fetch AUX CH registers 0x202 - 0x207 which contain
1943 * link status information
1944 */
1945static bool
93f62dad 1946intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1947{
9d1a1031
JN		 1948 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1949 DP_LANE0_1_STATUS,
1950 link_status,
1951 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 1952}
1953
a4fc5ed6
KP		 1954/*
1955 * These are source-specific values; current Intel hardware supports
1956 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1957 */
a4fc5ed6
KP		 1958
1959static uint8_t
1a2eb460 1960intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1961{
30add22d 1962 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1963 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1964
8f93f4f1 1965 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1966 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1967 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1968 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1969 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1970 return DP_TRAIN_VOLTAGE_SWING_1200;
1971 else
1972 return DP_TRAIN_VOLTAGE_SWING_800;
1973}
1974
1975static uint8_t
1976intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1977{
30add22d 1978 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1979 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1980
8f93f4f1
PZ		 1981 if (IS_BROADWELL(dev)) {
1982 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1983 case DP_TRAIN_VOLTAGE_SWING_400:
1984 case DP_TRAIN_VOLTAGE_SWING_600:
1985 return DP_TRAIN_PRE_EMPHASIS_6;
1986 case DP_TRAIN_VOLTAGE_SWING_800:
1987 return DP_TRAIN_PRE_EMPHASIS_3_5;
1988 case DP_TRAIN_VOLTAGE_SWING_1200:
1989 default:
1990 return DP_TRAIN_PRE_EMPHASIS_0;
1991 }
1992 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 1993 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1994 case DP_TRAIN_VOLTAGE_SWING_400:
1995 return DP_TRAIN_PRE_EMPHASIS_9_5;
1996 case DP_TRAIN_VOLTAGE_SWING_600:
1997 return DP_TRAIN_PRE_EMPHASIS_6;
1998 case DP_TRAIN_VOLTAGE_SWING_800:
1999 return DP_TRAIN_PRE_EMPHASIS_3_5;
2000 case DP_TRAIN_VOLTAGE_SWING_1200:
2001 default:
2002 return DP_TRAIN_PRE_EMPHASIS_0;
2003 }
e2fa6fba
P		 2004 } else if (IS_VALLEYVIEW(dev)) {
2005 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2006 case DP_TRAIN_VOLTAGE_SWING_400:
2007 return DP_TRAIN_PRE_EMPHASIS_9_5;
2008 case DP_TRAIN_VOLTAGE_SWING_600:
2009 return DP_TRAIN_PRE_EMPHASIS_6;
2010 case DP_TRAIN_VOLTAGE_SWING_800:
2011 return DP_TRAIN_PRE_EMPHASIS_3_5;
2012 case DP_TRAIN_VOLTAGE_SWING_1200:
2013 default:
2014 return DP_TRAIN_PRE_EMPHASIS_0;
2015 }
bc7d38a4 2016 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2017 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2018 case DP_TRAIN_VOLTAGE_SWING_400:
2019 return DP_TRAIN_PRE_EMPHASIS_6;
2020 case DP_TRAIN_VOLTAGE_SWING_600:
2021 case DP_TRAIN_VOLTAGE_SWING_800:
2022 return DP_TRAIN_PRE_EMPHASIS_3_5;
2023 default:
2024 return DP_TRAIN_PRE_EMPHASIS_0;
2025 }
2026 } else {
2027 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2028 case DP_TRAIN_VOLTAGE_SWING_400:
2029 return DP_TRAIN_PRE_EMPHASIS_6;
2030 case DP_TRAIN_VOLTAGE_SWING_600:
2031 return DP_TRAIN_PRE_EMPHASIS_6;
2032 case DP_TRAIN_VOLTAGE_SWING_800:
2033 return DP_TRAIN_PRE_EMPHASIS_3_5;
2034 case DP_TRAIN_VOLTAGE_SWING_1200:
2035 default:
2036 return DP_TRAIN_PRE_EMPHASIS_0;
2037 }
a4fc5ed6
KP		 2038 }
2039}
2040
e2fa6fba
P		 2041static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2042{
2043 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2046 struct intel_crtc *intel_crtc =
2047 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2048 unsigned long demph_reg_value, preemph_reg_value,
2049 uniqtranscale_reg_value;
2050 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2051 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2052 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2053
2054 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2055 case DP_TRAIN_PRE_EMPHASIS_0:
2056 preemph_reg_value = 0x0004000;
2057 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2058 case DP_TRAIN_VOLTAGE_SWING_400:
2059 demph_reg_value = 0x2B405555;
2060 uniqtranscale_reg_value = 0x552AB83A;
2061 break;
2062 case DP_TRAIN_VOLTAGE_SWING_600:
2063 demph_reg_value = 0x2B404040;
2064 uniqtranscale_reg_value = 0x5548B83A;
2065 break;
2066 case DP_TRAIN_VOLTAGE_SWING_800:
2067 demph_reg_value = 0x2B245555;
2068 uniqtranscale_reg_value = 0x5560B83A;
2069 break;
2070 case DP_TRAIN_VOLTAGE_SWING_1200:
2071 demph_reg_value = 0x2B405555;
2072 uniqtranscale_reg_value = 0x5598DA3A;
2073 break;
2074 default:
2075 return 0;
2076 }
2077 break;
2078 case DP_TRAIN_PRE_EMPHASIS_3_5:
2079 preemph_reg_value = 0x0002000;
2080 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2081 case DP_TRAIN_VOLTAGE_SWING_400:
2082 demph_reg_value = 0x2B404040;
2083 uniqtranscale_reg_value = 0x5552B83A;
2084 break;
2085 case DP_TRAIN_VOLTAGE_SWING_600:
2086 demph_reg_value = 0x2B404848;
2087 uniqtranscale_reg_value = 0x5580B83A;
2088 break;
2089 case DP_TRAIN_VOLTAGE_SWING_800:
2090 demph_reg_value = 0x2B404040;
2091 uniqtranscale_reg_value = 0x55ADDA3A;
2092 break;
2093 default:
2094 return 0;
2095 }
2096 break;
2097 case DP_TRAIN_PRE_EMPHASIS_6:
2098 preemph_reg_value = 0x0000000;
2099 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2100 case DP_TRAIN_VOLTAGE_SWING_400:
2101 demph_reg_value = 0x2B305555;
2102 uniqtranscale_reg_value = 0x5570B83A;
2103 break;
2104 case DP_TRAIN_VOLTAGE_SWING_600:
2105 demph_reg_value = 0x2B2B4040;
2106 uniqtranscale_reg_value = 0x55ADDA3A;
2107 break;
2108 default:
2109 return 0;
2110 }
2111 break;
2112 case DP_TRAIN_PRE_EMPHASIS_9_5:
2113 preemph_reg_value = 0x0006000;
2114 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2115 case DP_TRAIN_VOLTAGE_SWING_400:
2116 demph_reg_value = 0x1B405555;
2117 uniqtranscale_reg_value = 0x55ADDA3A;
2118 break;
2119 default:
2120 return 0;
2121 }
2122 break;
2123 default:
2124 return 0;
2125 }
2126
0980a60f 2127 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2128 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2129 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2130 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2131 uniqtranscale_reg_value);
ab3c759a
CML		 2132 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2133 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2134 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2135 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2136 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2137
2138 return 0;
2139}
2140
a4fc5ed6 2141static void
0301b3ac
JN		 2142intel_get_adjust_train(struct intel_dp *intel_dp,
2143 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2144{
2145 uint8_t v = 0;
2146 uint8_t p = 0;
2147 int lane;
1a2eb460
KP		 2148 uint8_t voltage_max;
2149 uint8_t preemph_max;
a4fc5ed6 2150
33a34e4e 2151 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2152 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2153 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2154
2155 if (this_v > v)
2156 v = this_v;
2157 if (this_p > p)
2158 p = this_p;
2159 }
2160
1a2eb460 2161 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2162 if (v >= voltage_max)
2163 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2164
1a2eb460
KP		 2165 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2166 if (p >= preemph_max)
2167 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2168
2169 for (lane = 0; lane < 4; lane++)
33a34e4e 2170 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2171}
2172
2173static uint32_t
f0a3424e 2174intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2175{
3cf2efb1 2176 uint32_t signal_levels = 0;
a4fc5ed6 2177
3cf2efb1 2178 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2179 case DP_TRAIN_VOLTAGE_SWING_400:
2180 default:
2181 signal_levels |= DP_VOLTAGE_0_4;
2182 break;
2183 case DP_TRAIN_VOLTAGE_SWING_600:
2184 signal_levels |= DP_VOLTAGE_0_6;
2185 break;
2186 case DP_TRAIN_VOLTAGE_SWING_800:
2187 signal_levels |= DP_VOLTAGE_0_8;
2188 break;
2189 case DP_TRAIN_VOLTAGE_SWING_1200:
2190 signal_levels |= DP_VOLTAGE_1_2;
2191 break;
2192 }
3cf2efb1 2193 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2194 case DP_TRAIN_PRE_EMPHASIS_0:
2195 default:
2196 signal_levels |= DP_PRE_EMPHASIS_0;
2197 break;
2198 case DP_TRAIN_PRE_EMPHASIS_3_5:
2199 signal_levels |= DP_PRE_EMPHASIS_3_5;
2200 break;
2201 case DP_TRAIN_PRE_EMPHASIS_6:
2202 signal_levels |= DP_PRE_EMPHASIS_6;
2203 break;
2204 case DP_TRAIN_PRE_EMPHASIS_9_5:
2205 signal_levels |= DP_PRE_EMPHASIS_9_5;
2206 break;
2207 }
2208 return signal_levels;
2209}
2210
e3421a18
ZW		 2211/* Gen6's DP voltage swing and pre-emphasis control */
2212static uint32_t
2213intel_gen6_edp_signal_levels(uint8_t train_set)
2214{
3c5a62b5
YL		 2215 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2216 DP_TRAIN_PRE_EMPHASIS_MASK);
2217 switch (signal_levels) {
e3421a18 2218 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2219 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2220 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2221 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2222 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2223 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2224 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2225 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2226 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2227 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2228 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2229 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2230 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2231 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2232 default:
3c5a62b5
YL		 2233 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2234 "0x%x\n", signal_levels);
2235 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2236 }
2237}
2238
1a2eb460
KP		 2239/* Gen7's DP voltage swing and pre-emphasis control */
2240static uint32_t
2241intel_gen7_edp_signal_levels(uint8_t train_set)
2242{
2243 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2244 DP_TRAIN_PRE_EMPHASIS_MASK);
2245 switch (signal_levels) {
2246 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2247 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2248 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2249 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2250 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2251 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2252
2253 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2254 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2255 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2256 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2257
2258 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2259 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2260 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2261 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2262
2263 default:
2264 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2265 "0x%x\n", signal_levels);
2266 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2267 }
2268}
2269
d6c0d722
PZ		 2270/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2271static uint32_t
f0a3424e 2272intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2273{
d6c0d722
PZ		 2274 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2275 DP_TRAIN_PRE_EMPHASIS_MASK);
2276 switch (signal_levels) {
2277 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2278 return DDI_BUF_EMP_400MV_0DB_HSW;
2279 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2280 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2281 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2282 return DDI_BUF_EMP_400MV_6DB_HSW;
2283 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2284 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2285
d6c0d722
PZ		 2286 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2287 return DDI_BUF_EMP_600MV_0DB_HSW;
2288 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2289 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2290 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2291 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2292
d6c0d722
PZ		 2293 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2294 return DDI_BUF_EMP_800MV_0DB_HSW;
2295 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2296 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2297 default:
2298 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2299 "0x%x\n", signal_levels);
2300 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2301 }
a4fc5ed6
KP		 2302}
2303
8f93f4f1
PZ		 2304static uint32_t
2305intel_bdw_signal_levels(uint8_t train_set)
2306{
2307 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2308 DP_TRAIN_PRE_EMPHASIS_MASK);
2309 switch (signal_levels) {
2310 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2311 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2312 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2313 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2314 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2315 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2316
2317 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2318 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2319 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2320 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2321 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2322 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2323
2324 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2325 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2326 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2327 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2328
2329 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2330 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2331
2332 default:
2333 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2334 "0x%x\n", signal_levels);
2335 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2336 }
2337}
2338
f0a3424e
PZ		 2339/* Properly updates "DP" with the correct signal levels. */
2340static void
2341intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2342{
2343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2344 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2345 struct drm_device *dev = intel_dig_port->base.base.dev;
2346 uint32_t signal_levels, mask;
2347 uint8_t train_set = intel_dp->train_set[0];
2348
8f93f4f1
PZ		 2349 if (IS_BROADWELL(dev)) {
2350 signal_levels = intel_bdw_signal_levels(train_set);
2351 mask = DDI_BUF_EMP_MASK;
2352 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2353 signal_levels = intel_hsw_signal_levels(train_set);
2354 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2355 } else if (IS_VALLEYVIEW(dev)) {
2356 signal_levels = intel_vlv_signal_levels(intel_dp);
2357 mask = 0;
bc7d38a4 2358 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2359 signal_levels = intel_gen7_edp_signal_levels(train_set);
2360 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2361 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2362 signal_levels = intel_gen6_edp_signal_levels(train_set);
2363 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2364 } else {
2365 signal_levels = intel_gen4_signal_levels(train_set);
2366 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2367 }
2368
2369 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2370
2371 *DP = (*DP & ~mask) | signal_levels;
2372}
2373
a4fc5ed6 2374static bool
ea5b213a 2375intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2376 uint32_t *DP,
58e10eb9 2377 uint8_t dp_train_pat)
a4fc5ed6 2378{
174edf1f
PZ		 2379 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2380 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2381 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2382 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2383 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2384 int ret, len;
a4fc5ed6 2385
22b8bf17 2386 if (HAS_DDI(dev)) {
3ab9c637 2387 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2388
2389 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2390 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2391 else
2392 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2393
2394 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2395 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2396 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2397 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2398
2399 break;
2400 case DP_TRAINING_PATTERN_1:
2401 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2402 break;
2403 case DP_TRAINING_PATTERN_2:
2404 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2405 break;
2406 case DP_TRAINING_PATTERN_3:
2407 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2408 break;
2409 }
174edf1f 2410 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2411
bc7d38a4 2412 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2413 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2414
2415 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2416 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2417 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2418 break;
2419 case DP_TRAINING_PATTERN_1:
70aff66c 2420 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2421 break;
2422 case DP_TRAINING_PATTERN_2:
70aff66c 2423 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2424 break;
2425 case DP_TRAINING_PATTERN_3:
2426 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2427 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2428 break;
2429 }
2430
2431 } else {
70aff66c 2432 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2433
2434 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2435 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2436 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2437 break;
2438 case DP_TRAINING_PATTERN_1:
70aff66c 2439 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2440 break;
2441 case DP_TRAINING_PATTERN_2:
70aff66c 2442 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2443 break;
2444 case DP_TRAINING_PATTERN_3:
2445 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2446 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2447 break;
2448 }
2449 }
2450
70aff66c 2451 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2452 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2453
2cdfe6c8
JN		 2454 buf[0] = dp_train_pat;
2455 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2456 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2457 /* don't write DP_TRAINING_LANEx_SET on disable */
2458 len = 1;
2459 } else {
2460 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2461 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2462 len = intel_dp->lane_count + 1;
47ea7542 2463 }
a4fc5ed6 2464
9d1a1031
JN		 2465 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2466 buf, len);
2cdfe6c8
JN		 2467
2468 return ret == len;
a4fc5ed6
KP		 2469}
2470
70aff66c
JN		 2471static bool
2472intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2473 uint8_t dp_train_pat)
2474{
953d22e8 2475 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2476 intel_dp_set_signal_levels(intel_dp, DP);
2477 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2478}
2479
2480static bool
2481intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2482 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2483{
2484 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2485 struct drm_device *dev = intel_dig_port->base.base.dev;
2486 struct drm_i915_private *dev_priv = dev->dev_private;
2487 int ret;
2488
2489 intel_get_adjust_train(intel_dp, link_status);
2490 intel_dp_set_signal_levels(intel_dp, DP);
2491
2492 I915_WRITE(intel_dp->output_reg, *DP);
2493 POSTING_READ(intel_dp->output_reg);
2494
9d1a1031
JN		 2495 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2496 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2497
2498 return ret == intel_dp->lane_count;
2499}
2500
3ab9c637
ID		 2501static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2502{
2503 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2504 struct drm_device *dev = intel_dig_port->base.base.dev;
2505 struct drm_i915_private *dev_priv = dev->dev_private;
2506 enum port port = intel_dig_port->port;
2507 uint32_t val;
2508
2509 if (!HAS_DDI(dev))
2510 return;
2511
2512 val = I915_READ(DP_TP_CTL(port));
2513 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2514 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2515 I915_WRITE(DP_TP_CTL(port), val);
2516
2517 /*
2518 * On PORT_A we can have only eDP in SST mode. There the only reason
2519 * we need to set idle transmission mode is to work around a HW issue
2520 * where we enable the pipe while not in idle link-training mode.
2521 * In this case there is requirement to wait for a minimum number of
2522 * idle patterns to be sent.
2523 */
2524 if (port == PORT_A)
2525 return;
2526
2527 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2528 1))
2529 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2530}
2531
33a34e4e 2532/* Enable corresponding port and start training pattern 1 */
c19b0669 2533void
33a34e4e 2534intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2535{
da63a9f2 2536 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2537 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2538 int i;
2539 uint8_t voltage;
cdb0e95b 2540 int voltage_tries, loop_tries;
ea5b213a 2541 uint32_t DP = intel_dp->DP;
6aba5b6c 2542 uint8_t link_config[2];
a4fc5ed6 2543
affa9354 2544 if (HAS_DDI(dev))
c19b0669
PZ		 2545 intel_ddi_prepare_link_retrain(encoder);
2546
3cf2efb1 2547 /* Write the link configuration data */
6aba5b6c
JN		 2548 link_config[0] = intel_dp->link_bw;
2549 link_config[1] = intel_dp->lane_count;
2550 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2551 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2552 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2553
2554 link_config[0] = 0;
2555 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2556 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2557
2558 DP |= DP_PORT_EN;
1a2eb460 2559
70aff66c
JN		 2560 /* clock recovery */
2561 if (!intel_dp_reset_link_train(intel_dp, &DP,
2562 DP_TRAINING_PATTERN_1 |
2563 DP_LINK_SCRAMBLING_DISABLE)) {
2564 DRM_ERROR("failed to enable link training\n");
2565 return;
2566 }
2567
a4fc5ed6 2568 voltage = 0xff;
cdb0e95b
KP		 2569 voltage_tries = 0;
2570 loop_tries = 0;
a4fc5ed6 2571 for (;;) {
70aff66c 2572 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2573
a7c9655f 2574 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2575 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2576 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2577 break;
93f62dad 2578 }
a4fc5ed6 2579
01916270 2580 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2581 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2582 break;
2583 }
2584
2585 /* Check to see if we've tried the max voltage */
2586 for (i = 0; i < intel_dp->lane_count; i++)
2587 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2588 break;
3b4f819d 2589 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2590 ++loop_tries;
2591 if (loop_tries == 5) {
3def84b3 2592 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2593 break;
2594 }
70aff66c
JN		 2595 intel_dp_reset_link_train(intel_dp, &DP,
2596 DP_TRAINING_PATTERN_1 |
2597 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2598 voltage_tries = 0;
2599 continue;
2600 }
a4fc5ed6 2601
3cf2efb1 2602 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2603 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2604 ++voltage_tries;
b06fbda3 2605 if (voltage_tries == 5) {
3def84b3 2606 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2607 break;
2608 }
2609 } else
2610 voltage_tries = 0;
2611 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2612
70aff66c
JN		 2613 /* Update training set as requested by target */
2614 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2615 DRM_ERROR("failed to update link training\n");
2616 break;
2617 }
a4fc5ed6
KP		 2618 }
2619
33a34e4e
JB		 2620 intel_dp->DP = DP;
2621}
2622
c19b0669 2623void
33a34e4e
JB		 2624intel_dp_complete_link_train(struct intel_dp *intel_dp)
2625{
33a34e4e 2626 bool channel_eq = false;
37f80975 2627 int tries, cr_tries;
33a34e4e 2628 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2629 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2630
2631 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2632 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2633 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2634
a4fc5ed6 2635 /* channel equalization */
70aff66c 2636 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2637 training_pattern |
70aff66c
JN		 2638 DP_LINK_SCRAMBLING_DISABLE)) {
2639 DRM_ERROR("failed to start channel equalization\n");
2640 return;
2641 }
2642
a4fc5ed6 2643 tries = 0;
37f80975 2644 cr_tries = 0;
a4fc5ed6
KP		 2645 channel_eq = false;
2646 for (;;) {
70aff66c 2647 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2648
37f80975
JB		 2649 if (cr_tries > 5) {
2650 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2651 break;
2652 }
2653
a7c9655f 2654 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2655 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2656 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2657 break;
70aff66c 2658 }
a4fc5ed6 2659
37f80975 2660 /* Make sure clock is still ok */
01916270 2661 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2662 intel_dp_start_link_train(intel_dp);
70aff66c 2663 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2664 training_pattern |
70aff66c 2665 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2666 cr_tries++;
2667 continue;
2668 }
2669
1ffdff13 2670 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2671 channel_eq = true;
2672 break;
2673 }
a4fc5ed6 2674
37f80975
JB		 2675 /* Try 5 times, then try clock recovery if that fails */
2676 if (tries > 5) {
2677 intel_dp_link_down(intel_dp);
2678 intel_dp_start_link_train(intel_dp);
70aff66c 2679 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2680 training_pattern |
70aff66c 2681 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2682 tries = 0;
2683 cr_tries++;
2684 continue;
2685 }
a4fc5ed6 2686
70aff66c
JN		 2687 /* Update training set as requested by target */
2688 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2689 DRM_ERROR("failed to update link training\n");
2690 break;
2691 }
3cf2efb1 2692 ++tries;
869184a6 2693 }
3cf2efb1 2694
3ab9c637
ID		 2695 intel_dp_set_idle_link_train(intel_dp);
2696
2697 intel_dp->DP = DP;
2698
d6c0d722 2699 if (channel_eq)
07f42258 2700 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2701
3ab9c637
ID		 2702}
2703
2704void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2705{
70aff66c 2706 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2707 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2708}
2709
2710static void
ea5b213a 2711intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2712{
da63a9f2 2713 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2714 enum port port = intel_dig_port->port;
da63a9f2 2715 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2716 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2717 struct intel_crtc *intel_crtc =
2718 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2719 uint32_t DP = intel_dp->DP;
a4fc5ed6 2720
c19b0669
PZ		 2721 /*
2722 * DDI code has a strict mode set sequence and we should try to respect
2723 * it, otherwise we might hang the machine in many different ways. So we
2724 * really should be disabling the port only on a complete crtc_disable
2725 * sequence. This function is just called under two conditions on DDI
2726 * code:
2727 * - Link train failed while doing crtc_enable, and on this case we
2728 * really should respect the mode set sequence and wait for a
2729 * crtc_disable.
2730 * - Someone turned the monitor off and intel_dp_check_link_status
2731 * called us. We don't need to disable the whole port on this case, so
2732 * when someone turns the monitor on again,
2733 * intel_ddi_prepare_link_retrain will take care of redoing the link
2734 * train.
2735 */
affa9354 2736 if (HAS_DDI(dev))
c19b0669
PZ		 2737 return;
2738
0c33d8d7 2739 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2740 return;
2741
28c97730 2742 DRM_DEBUG_KMS("\n");
32f9d658 2743
bc7d38a4 2744 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2745 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2746 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2747 } else {
2748 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2749 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2750 }
fe255d00 2751 POSTING_READ(intel_dp->output_reg);
5eb08b69 2752
ab527efc
DV		 2753 /* We don't really know why we're doing this */
2754 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2755
493a7081 2756 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2757 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2758 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2759
5bddd17f
EA		 2760 /* Hardware workaround: leaving our transcoder select
2761 * set to transcoder B while it's off will prevent the
2762 * corresponding HDMI output on transcoder A.
2763 *
2764 * Combine this with another hardware workaround:
2765 * transcoder select bit can only be cleared while the
2766 * port is enabled.
2767 */
2768 DP &= ~DP_PIPEB_SELECT;
2769 I915_WRITE(intel_dp->output_reg, DP);
2770
2771 /* Changes to enable or select take place the vblank
2772 * after being written.
2773 */
ff50afe9
DV		 2774 if (WARN_ON(crtc == NULL)) {
2775 /* We should never try to disable a port without a crtc
2776 * attached. For paranoia keep the code around for a
2777 * bit. */
31acbcc4
CW		 2778 POSTING_READ(intel_dp->output_reg);
2779 msleep(50);
2780 } else
ab527efc 2781 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2782 }
2783
832afda6 2784 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2785 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2786 POSTING_READ(intel_dp->output_reg);
f01eca2e 2787 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2788}
2789
26d61aad
KP		 2790static bool
2791intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2792{
a031d709
RV		 2793 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2794 struct drm_device *dev = dig_port->base.base.dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796
577c7a50
DL		 2797 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2798
9d1a1031
JN		 2799 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2800 sizeof(intel_dp->dpcd)) < 0)
edb39244 2801 return false; /* aux transfer failed */
92fd8fd1 2802
577c7a50
DL		 2803 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2804 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2805 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2806
edb39244
AJ		 2807 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2808 return false; /* DPCD not present */
2809
2293bb5c
SK		 2810 /* Check if the panel supports PSR */
2811 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2812 if (is_edp(intel_dp)) {
9d1a1031
JN		 2813 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2814 intel_dp->psr_dpcd,
2815 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2816 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2817 dev_priv->psr.sink_support = true;
50003939 2818 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2819 }
50003939
JN		 2820 }
2821
06ea66b6
TP		 2822 /* Training Pattern 3 support */
2823 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2824 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2825 intel_dp->use_tps3 = true;
2826 DRM_DEBUG_KMS("Displayport TPS3 supported");
2827 } else
2828 intel_dp->use_tps3 = false;
2829
edb39244
AJ		 2830 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2831 DP_DWN_STRM_PORT_PRESENT))
2832 return true; /* native DP sink */
2833
2834 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2835 return true; /* no per-port downstream info */
2836
9d1a1031
JN		 2837 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2838 intel_dp->downstream_ports,
2839 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2840 return false; /* downstream port status fetch failed */
2841
2842 return true;
92fd8fd1
KP		 2843}
2844
0d198328
AJ		 2845static void
2846intel_dp_probe_oui(struct intel_dp *intel_dp)
2847{
2848 u8 buf[3];
2849
2850 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2851 return;
2852
24f3e092 2853 intel_edp_panel_vdd_on(intel_dp);
351cfc34 2854
9d1a1031 2855 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2856 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2857 buf[0], buf[1], buf[2]);
2858
9d1a1031 2859 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2860 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2861 buf[0], buf[1], buf[2]);
351cfc34 2862
4be73780 2863 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2864}
2865
d2e216d0
RV		 2866int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2867{
2868 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2869 struct drm_device *dev = intel_dig_port->base.base.dev;
2870 struct intel_crtc *intel_crtc =
2871 to_intel_crtc(intel_dig_port->base.base.crtc);
2872 u8 buf[1];
2873
9d1a1031 2874 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2875 return -EAGAIN;
2876
2877 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2878 return -ENOTTY;
2879
9d1a1031
JN		 2880 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2881 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2882 return -EAGAIN;
2883
2884 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2885 intel_wait_for_vblank(dev, intel_crtc->pipe);
2886 intel_wait_for_vblank(dev, intel_crtc->pipe);
2887
9d1a1031 2888 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2889 return -EAGAIN;
2890
9d1a1031 2891 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 2892 return 0;
2893}
2894
a60f0e38
JB		 2895static bool
2896intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2897{
9d1a1031
JN		 2898 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2899 DP_DEVICE_SERVICE_IRQ_VECTOR,
2900 sink_irq_vector, 1) == 1;
a60f0e38
JB		 2901}
2902
2903static void
2904intel_dp_handle_test_request(struct intel_dp *intel_dp)
2905{
2906 /* NAK by default */
9d1a1031 2907 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2908}
2909
a4fc5ed6
KP		 2910/*
2911 * According to DP spec
2912 * 5.1.2:
2913 * 1. Read DPCD
2914 * 2. Configure link according to Receiver Capabilities
2915 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2916 * 4. Check link status on receipt of hot-plug interrupt
2917 */
2918
00c09d70 2919void
ea5b213a 2920intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2921{
da63a9f2 2922 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2923 u8 sink_irq_vector;
93f62dad 2924 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2925
da63a9f2 2926 if (!intel_encoder->connectors_active)
d2b996ac 2927 return;
59cd09e1 2928
da63a9f2 2929 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2930 return;
2931
92fd8fd1 2932 /* Try to read receiver status if the link appears to be up */
93f62dad 2933 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2934 return;
2935 }
2936
92fd8fd1 2937 /* Now read the DPCD to see if it's actually running */
26d61aad 2938 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2939 return;
2940 }
2941
a60f0e38
JB		 2942 /* Try to read the source of the interrupt */
2943 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2944 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2945 /* Clear interrupt source */
9d1a1031
JN		 2946 drm_dp_dpcd_writeb(&intel_dp->aux,
2947 DP_DEVICE_SERVICE_IRQ_VECTOR,
2948 sink_irq_vector);
a60f0e38
JB		 2949
2950 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2951 intel_dp_handle_test_request(intel_dp);
2952 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2953 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2954 }
2955
1ffdff13 2956 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2957 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2958 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2959 intel_dp_start_link_train(intel_dp);
2960 intel_dp_complete_link_train(intel_dp);
3ab9c637 2961 intel_dp_stop_link_train(intel_dp);
33a34e4e 2962 }
a4fc5ed6 2963}
a4fc5ed6 2964
caf9ab24 2965/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2966static enum drm_connector_status
26d61aad 2967intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2968{
caf9ab24 2969 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2970 uint8_t type;
2971
2972 if (!intel_dp_get_dpcd(intel_dp))
2973 return connector_status_disconnected;
2974
2975 /* if there's no downstream port, we're done */
2976 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2977 return connector_status_connected;
caf9ab24
AJ		 2978
2979 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2980 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2981 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2982 uint8_t reg;
9d1a1031
JN		 2983
2984 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
2985 &reg, 1) < 0)
caf9ab24 2986 return connector_status_unknown;
9d1a1031 2987
23235177
AJ		 2988 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2989 : connector_status_disconnected;
caf9ab24
AJ		 2990 }
2991
2992 /* If no HPD, poke DDC gently */
0b99836f 2993 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 2994 return connector_status_connected;
caf9ab24
AJ		 2995
2996 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 2997 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2998 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2999 if (type == DP_DS_PORT_TYPE_VGA ||
3000 type == DP_DS_PORT_TYPE_NON_EDID)
3001 return connector_status_unknown;
3002 } else {
3003 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3004 DP_DWN_STRM_PORT_TYPE_MASK;
3005 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3006 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3007 return connector_status_unknown;
3008 }
caf9ab24
AJ		 3009
3010 /* Anything else is out of spec, warn and ignore */
3011 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3012 return connector_status_disconnected;
71ba9000
AJ		 3013}
3014
5eb08b69 3015static enum drm_connector_status
a9756bb5 3016ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3017{
30add22d 3018 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3021 enum drm_connector_status status;
3022
fe16d949
CW		 3023 /* Can't disconnect eDP, but you can close the lid... */
3024 if (is_edp(intel_dp)) {
30add22d 3025 status = intel_panel_detect(dev);
fe16d949
CW		 3026 if (status == connector_status_unknown)
3027 status = connector_status_connected;
3028 return status;
3029 }
01cb9ea6 3030
1b469639
DL		 3031 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3032 return connector_status_disconnected;
3033
26d61aad 3034 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3035}
3036
a4fc5ed6 3037static enum drm_connector_status
a9756bb5 3038g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3039{
30add22d 3040 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3041 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3042 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3043 uint32_t bit;
5eb08b69 3044
35aad75f
JB		 3045 /* Can't disconnect eDP, but you can close the lid... */
3046 if (is_edp(intel_dp)) {
3047 enum drm_connector_status status;
3048
3049 status = intel_panel_detect(dev);
3050 if (status == connector_status_unknown)
3051 status = connector_status_connected;
3052 return status;
3053 }
3054
232a6ee9
TP		 3055 if (IS_VALLEYVIEW(dev)) {
3056 switch (intel_dig_port->port) {
3057 case PORT_B:
3058 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3059 break;
3060 case PORT_C:
3061 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3062 break;
3063 case PORT_D:
3064 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3065 break;
3066 default:
3067 return connector_status_unknown;
3068 }
3069 } else {
3070 switch (intel_dig_port->port) {
3071 case PORT_B:
3072 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3073 break;
3074 case PORT_C:
3075 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3076 break;
3077 case PORT_D:
3078 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3079 break;
3080 default:
3081 return connector_status_unknown;
3082 }
a4fc5ed6
KP		 3083 }
3084
10f76a38 3085 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3086 return connector_status_disconnected;
3087
26d61aad 3088 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3089}
3090
8c241fef
KP		 3091static struct edid *
3092intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3093{
9cd300e0 3094 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3095
9cd300e0
JN		 3096 /* use cached edid if we have one */
3097 if (intel_connector->edid) {
9cd300e0
JN		 3098 /* invalid edid */
3099 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3100 return NULL;
3101
55e9edeb 3102 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3103 }
8c241fef 3104
9cd300e0 3105 return drm_get_edid(connector, adapter);
8c241fef
KP		 3106}
3107
3108static int
3109intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3110{
9cd300e0 3111 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3112
9cd300e0
JN		 3113 /* use cached edid if we have one */
3114 if (intel_connector->edid) {
3115 /* invalid edid */
3116 if (IS_ERR(intel_connector->edid))
3117 return 0;
3118
3119 return intel_connector_update_modes(connector,
3120 intel_connector->edid);
d6f24d0f
JB		 3121 }
3122
9cd300e0 3123 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3124}
3125
a9756bb5
ZW		 3126static enum drm_connector_status
3127intel_dp_detect(struct drm_connector *connector, bool force)
3128{
3129 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3130 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3131 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3132 struct drm_device *dev = connector->dev;
c8c8fb33 3133 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3134 enum drm_connector_status status;
671dedd2 3135 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3136 struct edid *edid = NULL;
3137
c8c8fb33
PZ		 3138 intel_runtime_pm_get(dev_priv);
3139
671dedd2
ID		 3140 power_domain = intel_display_port_power_domain(intel_encoder);
3141 intel_display_power_get(dev_priv, power_domain);
3142
164c8598
CW		 3143 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3144 connector->base.id, drm_get_connector_name(connector));
3145
a9756bb5
ZW		 3146 intel_dp->has_audio = false;
3147
3148 if (HAS_PCH_SPLIT(dev))
3149 status = ironlake_dp_detect(intel_dp);
3150 else
3151 status = g4x_dp_detect(intel_dp);
1b9be9d0 3152
a9756bb5 3153 if (status != connector_status_connected)
c8c8fb33 3154 goto out;
a9756bb5 3155
0d198328
AJ		 3156 intel_dp_probe_oui(intel_dp);
3157
c3e5f67b
DV		 3158 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3159 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3160 } else {
0b99836f 3161 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3162 if (edid) {
3163 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3164 kfree(edid);
3165 }
a9756bb5
ZW		 3166 }
3167
d63885da
PZ		 3168 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3169 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3170 status = connector_status_connected;
3171
3172out:
671dedd2
ID		 3173 intel_display_power_put(dev_priv, power_domain);
3174
c8c8fb33 3175 intel_runtime_pm_put(dev_priv);
671dedd2 3176
c8c8fb33 3177 return status;
a4fc5ed6
KP		 3178}
3179
3180static int intel_dp_get_modes(struct drm_connector *connector)
3181{
df0e9248 3182 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3183 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3184 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3185 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3186 struct drm_device *dev = connector->dev;
671dedd2
ID		 3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 enum intel_display_power_domain power_domain;
32f9d658 3189 int ret;
a4fc5ed6
KP		 3190
3191 /* We should parse the EDID data and find out if it has an audio sink
3192 */
3193
671dedd2
ID		 3194 power_domain = intel_display_port_power_domain(intel_encoder);
3195 intel_display_power_get(dev_priv, power_domain);
3196
0b99836f 3197 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3198 intel_display_power_put(dev_priv, power_domain);
f8779fda 3199 if (ret)
32f9d658
ZW		 3200 return ret;
3201
f8779fda 3202 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3203 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3204 struct drm_display_mode *mode;
dd06f90e
JN		 3205 mode = drm_mode_duplicate(dev,
3206 intel_connector->panel.fixed_mode);
f8779fda 3207 if (mode) {
32f9d658
ZW		 3208 drm_mode_probed_add(connector, mode);
3209 return 1;
3210 }
3211 }
3212 return 0;
a4fc5ed6
KP		 3213}
3214
1aad7ac0
CW		 3215static bool
3216intel_dp_detect_audio(struct drm_connector *connector)
3217{
3218 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3220 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3221 struct drm_device *dev = connector->dev;
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3223 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3224 struct edid *edid;
3225 bool has_audio = false;
3226
671dedd2
ID		 3227 power_domain = intel_display_port_power_domain(intel_encoder);
3228 intel_display_power_get(dev_priv, power_domain);
3229
0b99836f 3230 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3231 if (edid) {
3232 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3233 kfree(edid);
3234 }
3235
671dedd2
ID		 3236 intel_display_power_put(dev_priv, power_domain);
3237
1aad7ac0
CW		 3238 return has_audio;
3239}
3240
f684960e
CW		 3241static int
3242intel_dp_set_property(struct drm_connector *connector,
3243 struct drm_property *property,
3244 uint64_t val)
3245{
e953fd7b 3246 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3247 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3248 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3249 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3250 int ret;
3251
662595df 3252 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3253 if (ret)
3254 return ret;
3255
3f43c48d 3256 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3257 int i = val;
3258 bool has_audio;
3259
3260 if (i == intel_dp->force_audio)
f684960e
CW		 3261 return 0;
3262
1aad7ac0 3263 intel_dp->force_audio = i;
f684960e 3264
c3e5f67b 3265 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3266 has_audio = intel_dp_detect_audio(connector);
3267 else
c3e5f67b 3268 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3269
3270 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3271 return 0;
3272
1aad7ac0 3273 intel_dp->has_audio = has_audio;
f684960e
CW		 3274 goto done;
3275 }
3276
e953fd7b 3277 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3278 bool old_auto = intel_dp->color_range_auto;
3279 uint32_t old_range = intel_dp->color_range;
3280
55bc60db
VS		 3281 switch (val) {
3282 case INTEL_BROADCAST_RGB_AUTO:
3283 intel_dp->color_range_auto = true;
3284 break;
3285 case INTEL_BROADCAST_RGB_FULL:
3286 intel_dp->color_range_auto = false;
3287 intel_dp->color_range = 0;
3288 break;
3289 case INTEL_BROADCAST_RGB_LIMITED:
3290 intel_dp->color_range_auto = false;
3291 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3292 break;
3293 default:
3294 return -EINVAL;
3295 }
ae4edb80
DV		 3296
3297 if (old_auto == intel_dp->color_range_auto &&
3298 old_range == intel_dp->color_range)
3299 return 0;
3300
e953fd7b
CW		 3301 goto done;
3302 }
3303
53b41837
YN		 3304 if (is_edp(intel_dp) &&
3305 property == connector->dev->mode_config.scaling_mode_property) {
3306 if (val == DRM_MODE_SCALE_NONE) {
3307 DRM_DEBUG_KMS("no scaling not supported\n");
3308 return -EINVAL;
3309 }
3310
3311 if (intel_connector->panel.fitting_mode == val) {
3312 /* the eDP scaling property is not changed */
3313 return 0;
3314 }
3315 intel_connector->panel.fitting_mode = val;
3316
3317 goto done;
3318 }
3319
f684960e
CW		 3320 return -EINVAL;
3321
3322done:
c0c36b94
CW		 3323 if (intel_encoder->base.crtc)
3324 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3325
3326 return 0;
3327}
3328
a4fc5ed6 3329static void
73845adf 3330intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3331{
1d508706 3332 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3333
9cd300e0
JN		 3334 if (!IS_ERR_OR_NULL(intel_connector->edid))
3335 kfree(intel_connector->edid);
3336
acd8db10
PZ		 3337 /* Can't call is_edp() since the encoder may have been destroyed
3338 * already. */
3339 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3340 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3341
a4fc5ed6 3342 drm_connector_cleanup(connector);
55f78c43 3343 kfree(connector);
a4fc5ed6
KP		 3344}
3345
00c09d70 3346void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3347{
da63a9f2
PZ		 3348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3349 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3350 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3351
0b99836f 3352 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3353 drm_encoder_cleanup(encoder);
bd943159
KP		 3354 if (is_edp(intel_dp)) {
3355 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3356 mutex_lock(&dev->mode_config.mutex);
4be73780 3357 edp_panel_vdd_off_sync(intel_dp);
bd173813 3358 mutex_unlock(&dev->mode_config.mutex);
bd943159 3359 }
da63a9f2 3360 kfree(intel_dig_port);
24d05927
DV		 3361}
3362
a4fc5ed6 3363static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3364 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3365 .detect = intel_dp_detect,
3366 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3367 .set_property = intel_dp_set_property,
73845adf 3368 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3369};
3370
3371static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3372 .get_modes = intel_dp_get_modes,
3373 .mode_valid = intel_dp_mode_valid,
df0e9248 3374 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3375};
3376
a4fc5ed6 3377static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3378 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3379};
3380
995b6762 3381static void
21d40d37 3382intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3383{
fa90ecef 3384 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3385
885a5014 3386 intel_dp_check_link_status(intel_dp);
c8110e52 3387}
6207937d 3388
e3421a18
ZW		 3389/* Return which DP Port should be selected for Transcoder DP control */
3390int
0206e353 3391intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3392{
3393 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3394 struct intel_encoder *intel_encoder;
3395 struct intel_dp *intel_dp;
e3421a18 3396
fa90ecef
PZ		 3397 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3398 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3399
fa90ecef
PZ		 3400 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3401 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3402 return intel_dp->output_reg;
e3421a18 3403 }
ea5b213a 3404
e3421a18
ZW		 3405 return -1;
3406}
3407
36e83a18 3408/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3409bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3410{
3411 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3412 union child_device_config *p_child;
36e83a18 3413 int i;
5d8a7752
VS		 3414 static const short port_mapping[] = {
3415 [PORT_B] = PORT_IDPB,
3416 [PORT_C] = PORT_IDPC,
3417 [PORT_D] = PORT_IDPD,
3418 };
36e83a18 3419
3b32a35b
VS		 3420 if (port == PORT_A)
3421 return true;
3422
41aa3448 3423 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3424 return false;
3425
41aa3448
RV		 3426 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3427 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3428
5d8a7752 3429 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3430 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3431 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3432 return true;
3433 }
3434 return false;
3435}
3436
f684960e
CW		 3437static void
3438intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3439{
53b41837
YN		 3440 struct intel_connector *intel_connector = to_intel_connector(connector);
3441
3f43c48d 3442 intel_attach_force_audio_property(connector);
e953fd7b 3443 intel_attach_broadcast_rgb_property(connector);
55bc60db 3444 intel_dp->color_range_auto = true;
53b41837
YN		 3445
3446 if (is_edp(intel_dp)) {
3447 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3448 drm_object_attach_property(
3449 &connector->base,
53b41837 3450 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3451 DRM_MODE_SCALE_ASPECT);
3452 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3453 }
f684960e
CW		 3454}
3455
dada1a9f
ID		 3456static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3457{
3458 intel_dp->last_power_cycle = jiffies;
3459 intel_dp->last_power_on = jiffies;
3460 intel_dp->last_backlight_off = jiffies;
3461}
3462
67a54566
DV		 3463static void
3464intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3465 struct intel_dp *intel_dp,
3466 struct edp_power_seq *out)
67a54566
DV		 3467{
3468 struct drm_i915_private *dev_priv = dev->dev_private;
3469 struct edp_power_seq cur, vbt, spec, final;
3470 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3471 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3472
3473 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3474 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3475 pp_on_reg = PCH_PP_ON_DELAYS;
3476 pp_off_reg = PCH_PP_OFF_DELAYS;
3477 pp_div_reg = PCH_PP_DIVISOR;
3478 } else {
bf13e81b
JN		 3479 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3480
3481 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3482 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3483 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3484 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3485 }
67a54566
DV		 3486
3487 /* Workaround: Need to write PP_CONTROL with the unlock key as
3488 * the very first thing. */
453c5420 3489 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3490 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3491
453c5420
JB		 3492 pp_on = I915_READ(pp_on_reg);
3493 pp_off = I915_READ(pp_off_reg);
3494 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3495
3496 /* Pull timing values out of registers */
3497 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3498 PANEL_POWER_UP_DELAY_SHIFT;
3499
3500 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3501 PANEL_LIGHT_ON_DELAY_SHIFT;
3502
3503 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3504 PANEL_LIGHT_OFF_DELAY_SHIFT;
3505
3506 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3507 PANEL_POWER_DOWN_DELAY_SHIFT;
3508
3509 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3510 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3511
3512 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3513 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3514
41aa3448 3515 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3516
3517 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3518 * our hw here, which are all in 100usec. */
3519 spec.t1_t3 = 210 * 10;
3520 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3521 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3522 spec.t10 = 500 * 10;
3523 /* This one is special and actually in units of 100ms, but zero
3524 * based in the hw (so we need to add 100 ms). But the sw vbt
3525 * table multiplies it with 1000 to make it in units of 100usec,
3526 * too. */
3527 spec.t11_t12 = (510 + 100) * 10;
3528
3529 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3530 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3531
3532 /* Use the max of the register settings and vbt. If both are
3533 * unset, fall back to the spec limits. */
3534#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3535 spec.field : \
3536 max(cur.field, vbt.field))
3537 assign_final(t1_t3);
3538 assign_final(t8);
3539 assign_final(t9);
3540 assign_final(t10);
3541 assign_final(t11_t12);
3542#undef assign_final
3543
3544#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3545 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3546 intel_dp->backlight_on_delay = get_delay(t8);
3547 intel_dp->backlight_off_delay = get_delay(t9);
3548 intel_dp->panel_power_down_delay = get_delay(t10);
3549 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3550#undef get_delay
3551
f30d26e4
JN		 3552 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3553 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3554 intel_dp->panel_power_cycle_delay);
3555
3556 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3557 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3558
3559 if (out)
3560 *out = final;
3561}
3562
3563static void
3564intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3565 struct intel_dp *intel_dp,
3566 struct edp_power_seq *seq)
3567{
3568 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3569 u32 pp_on, pp_off, pp_div, port_sel = 0;
3570 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3571 int pp_on_reg, pp_off_reg, pp_div_reg;
3572
3573 if (HAS_PCH_SPLIT(dev)) {
3574 pp_on_reg = PCH_PP_ON_DELAYS;
3575 pp_off_reg = PCH_PP_OFF_DELAYS;
3576 pp_div_reg = PCH_PP_DIVISOR;
3577 } else {
bf13e81b
JN		 3578 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3579
3580 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3581 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3582 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3583 }
3584
b2f19d1a
PZ		 3585 /*
3586 * And finally store the new values in the power sequencer. The
3587 * backlight delays are set to 1 because we do manual waits on them. For
3588 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3589 * we'll end up waiting for the backlight off delay twice: once when we
3590 * do the manual sleep, and once when we disable the panel and wait for
3591 * the PP_STATUS bit to become zero.
3592 */
f30d26e4 3593 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3594 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3595 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3596 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3597 /* Compute the divisor for the pp clock, simply match the Bspec
3598 * formula. */
453c5420 3599 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3600 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3601 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3602
3603 /* Haswell doesn't have any port selection bits for the panel
3604 * power sequencer any more. */
bc7d38a4 3605 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3606 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3607 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3608 else
3609 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3610 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3611 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3612 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3613 else
a24c144c 3614 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3615 }
3616
453c5420
JB		 3617 pp_on |= port_sel;
3618
3619 I915_WRITE(pp_on_reg, pp_on);
3620 I915_WRITE(pp_off_reg, pp_off);
3621 I915_WRITE(pp_div_reg, pp_div);
67a54566 3622
67a54566 3623 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3624 I915_READ(pp_on_reg),
3625 I915_READ(pp_off_reg),
3626 I915_READ(pp_div_reg));
f684960e
CW		 3627}
3628
ed92f0b2 3629static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3630 struct intel_connector *intel_connector,
3631 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3632{
3633 struct drm_connector *connector = &intel_connector->base;
3634 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3635 struct drm_device *dev = intel_dig_port->base.base.dev;
3636 struct drm_i915_private *dev_priv = dev->dev_private;
3637 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3638 bool has_dpcd;
3639 struct drm_display_mode *scan;
3640 struct edid *edid;
3641
3642 if (!is_edp(intel_dp))
3643 return true;
3644
ed92f0b2 3645 /* Cache DPCD and EDID for edp. */
24f3e092 3646 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 3647 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3648 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3649
3650 if (has_dpcd) {
3651 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3652 dev_priv->no_aux_handshake =
3653 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3654 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3655 } else {
3656 /* if this fails, presume the device is a ghost */
3657 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3658 return false;
3659 }
3660
3661 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3662 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3663
4da98541 3664 mutex_lock(&dev->mode_config.mutex);
0b99836f 3665 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 3666 if (edid) {
3667 if (drm_add_edid_modes(connector, edid)) {
3668 drm_mode_connector_update_edid_property(connector,
3669 edid);
3670 drm_edid_to_eld(connector, edid);
3671 } else {
3672 kfree(edid);
3673 edid = ERR_PTR(-EINVAL);
3674 }
3675 } else {
3676 edid = ERR_PTR(-ENOENT);
3677 }
3678 intel_connector->edid = edid;
3679
3680 /* prefer fixed mode from EDID if available */
3681 list_for_each_entry(scan, &connector->probed_modes, head) {
3682 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3683 fixed_mode = drm_mode_duplicate(dev, scan);
3684 break;
3685 }
3686 }
3687
3688 /* fallback to VBT if available for eDP */
3689 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3690 fixed_mode = drm_mode_duplicate(dev,
3691 dev_priv->vbt.lfp_lvds_vbt_mode);
3692 if (fixed_mode)
3693 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3694 }
4da98541 3695 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 3696
4b6ed685 3697 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3698 intel_panel_setup_backlight(connector);
3699
3700 return true;
3701}
3702
16c25533 3703bool
f0fec3f2
PZ		 3704intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3705 struct intel_connector *intel_connector)
a4fc5ed6 3706{
f0fec3f2
PZ		 3707 struct drm_connector *connector = &intel_connector->base;
3708 struct intel_dp *intel_dp = &intel_dig_port->dp;
3709 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3710 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3711 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3712 enum port port = intel_dig_port->port;
0095e6dc 3713 struct edp_power_seq power_seq = { 0 };
0b99836f 3714 int type;
a4fc5ed6 3715
ec5b01dd
DL		 3716 /* intel_dp vfuncs */
3717 if (IS_VALLEYVIEW(dev))
3718 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3719 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3720 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3721 else if (HAS_PCH_SPLIT(dev))
3722 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3723 else
3724 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3725
153b1100
DL		 3726 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3727
0767935e
DV		 3728 /* Preserve the current hw state. */
3729 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3730 intel_dp->attached_connector = intel_connector;
3d3dc149 3731
3b32a35b 3732 if (intel_dp_is_edp(dev, port))
b329530c 3733 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3734 else
3735 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3736
f7d24902
ID		 3737 /*
3738 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3739 * for DP the encoder type can be set by the caller to
3740 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3741 */
3742 if (type == DRM_MODE_CONNECTOR_eDP)
3743 intel_encoder->type = INTEL_OUTPUT_EDP;
3744
e7281eab
ID		 3745 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3746 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3747 port_name(port));
3748
b329530c 3749 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3750 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3751
a4fc5ed6
KP		 3752 connector->interlace_allowed = true;
3753 connector->doublescan_allowed = 0;
3754
f0fec3f2 3755 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3756 edp_panel_vdd_work);
a4fc5ed6 3757
df0e9248 3758 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3759 drm_sysfs_connector_add(connector);
3760
affa9354 3761 if (HAS_DDI(dev))
bcbc889b
PZ		 3762 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3763 else
3764 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3765 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3766
0b99836f 3767 /* Set up the hotplug pin. */
ab9d7c30
PZ		 3768 switch (port) {
3769 case PORT_A:
1d843f9d 3770 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3771 break;
3772 case PORT_B:
1d843f9d 3773 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3774 break;
3775 case PORT_C:
1d843f9d 3776 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3777 break;
3778 case PORT_D:
1d843f9d 3779 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3780 break;
3781 default:
ad1c0b19 3782 BUG();
5eb08b69
ZW		 3783 }
3784
dada1a9f
ID		 3785 if (is_edp(intel_dp)) {
3786 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3787 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3788 }
0095e6dc 3789
9d1a1031 3790 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 3791
2b28bb1b
RV		 3792 intel_dp->psr_setup_done = false;
3793
0095e6dc 3794 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 3795 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 3796 if (is_edp(intel_dp)) {
3797 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3798 mutex_lock(&dev->mode_config.mutex);
4be73780 3799 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3800 mutex_unlock(&dev->mode_config.mutex);
3801 }
b2f246a8
PZ		 3802 drm_sysfs_connector_remove(connector);
3803 drm_connector_cleanup(connector);
16c25533 3804 return false;
b2f246a8 3805 }
32f9d658 3806
f684960e
CW		 3807 intel_dp_add_properties(intel_dp, connector);
3808
a4fc5ed6
KP		 3809 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3810 * 0xd. Failure to do so will result in spurious interrupts being
3811 * generated on the port when a cable is not attached.
3812 */
3813 if (IS_G4X(dev) && !IS_GM45(dev)) {
3814 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3815 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3816 }
16c25533
PZ		 3817
3818 return true;
a4fc5ed6 3819}
f0fec3f2
PZ		 3820
3821void
3822intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3823{
3824 struct intel_digital_port *intel_dig_port;
3825 struct intel_encoder *intel_encoder;
3826 struct drm_encoder *encoder;
3827 struct intel_connector *intel_connector;
3828
b14c5679 3829 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3830 if (!intel_dig_port)
3831 return;
3832
b14c5679 3833 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3834 if (!intel_connector) {
3835 kfree(intel_dig_port);
3836 return;
3837 }
3838
3839 intel_encoder = &intel_dig_port->base;
3840 encoder = &intel_encoder->base;
3841
3842 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3843 DRM_MODE_ENCODER_TMDS);
3844
5bfe2ac0 3845 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3846 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3847 intel_encoder->disable = intel_disable_dp;
3848 intel_encoder->post_disable = intel_post_disable_dp;
3849 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3850 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3851 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3852 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3853 intel_encoder->pre_enable = vlv_pre_enable_dp;
3854 intel_encoder->enable = vlv_enable_dp;
3855 } else {
ecff4f3b
JN		 3856 intel_encoder->pre_enable = g4x_pre_enable_dp;
3857 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3858 }
f0fec3f2 3859
174edf1f 3860 intel_dig_port->port = port;
f0fec3f2
PZ		 3861 intel_dig_port->dp.output_reg = output_reg;
3862
00c09d70 3863 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 3864 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3865 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 3866 intel_encoder->hot_plug = intel_dp_hot_plug;
3867
15b1d171
PZ		 3868 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3869 drm_encoder_cleanup(encoder);
3870 kfree(intel_dig_port);
b2f246a8 3871 kfree(intel_connector);
15b1d171 3872 }
f0fec3f2 3873}
Linux 6.x block layer and io_uring tree(s)