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drm/i915: Turn on panel power before doing aux transfers
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a
VS		 335 lockdep_assert_held(&dev_priv->pps_mutex);
336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
451 }
452
453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
488}
489
bf13e81b
JN		 490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
5ed12a19
DL		 664static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
665 bool has_aux_irq,
666 int send_bytes,
667 uint32_t aux_clock_divider)
668{
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 struct drm_device *dev = intel_dig_port->base.base.dev;
671 uint32_t precharge, timeout;
672
673 if (IS_GEN6(dev))
674 precharge = 3;
675 else
676 precharge = 5;
677
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
679 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
680 else
681 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
682
683 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 684 DP_AUX_CH_CTL_DONE |
5ed12a19 685 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 686 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 687 timeout |
788d4433 688 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 689 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
690 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 691 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 692}
693
b84a1cf8
RV		 694static int
695intel_dp_aux_ch(struct intel_dp *intel_dp,
696 uint8_t *send, int send_bytes,
697 uint8_t *recv, int recv_size)
698{
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
703 uint32_t ch_data = ch_ctl + 4;
bc86625a 704 uint32_t aux_clock_divider;
b84a1cf8
RV		 705 int i, ret, recv_bytes;
706 uint32_t status;
5ed12a19 707 int try, clock = 0;
4e6b788c 708 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 709 bool vdd;
710
773538e8 711 pps_lock(intel_dp);
e39b999a 712
72c3500a
VS		 713 /*
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
717 * ourselves.
718 */
1e0560e0 719 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 720
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
723 * deep sleep states.
724 */
725 pm_qos_update_request(&dev_priv->pm_qos, 0);
726
727 intel_dp_check_edp(intel_dp);
5eb08b69 728
c67a470b
PZ		 729 intel_aux_display_runtime_get(dev_priv);
730
11bee43e
JB		 731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
ef04f00d 733 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 734 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
735 break;
736 msleep(1);
737 }
738
739 if (try == 3) {
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
741 I915_READ(ch_ctl));
9ee32fea
DV		 742 ret = -EBUSY;
743 goto out;
4f7f7b7e
CW		 744 }
745
46a5ae9f
PZ		 746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
748 ret = -E2BIG;
749 goto out;
750 }
751
ec5b01dd 752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
754 has_aux_irq,
755 send_bytes,
756 aux_clock_divider);
5ed12a19 757
bc86625a
CW		 758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i = 0; i < send_bytes; i += 4)
762 I915_WRITE(ch_data + i,
763 pack_aux(send + i, send_bytes - i));
764
765 /* Send the command and wait for it to complete */
5ed12a19 766 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 767
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
769
770 /* Clear done status and any errors */
771 I915_WRITE(ch_ctl,
772 status |
773 DP_AUX_CH_CTL_DONE |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR);
776
777 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_RECEIVE_ERROR))
779 continue;
780 if (status & DP_AUX_CH_CTL_DONE)
781 break;
782 }
4f7f7b7e 783 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 784 break;
785 }
786
a4fc5ed6 787 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 789 ret = -EBUSY;
790 goto out;
a4fc5ed6
KP		 791 }
792
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
795 */
a5b3da54 796 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 798 ret = -EIO;
799 goto out;
a5b3da54 800 }
1ae8c0a5
KP		 801
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
a5b3da54 804 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 806 ret = -ETIMEDOUT;
807 goto out;
a4fc5ed6
KP		 808 }
809
810 /* Unload any bytes sent back from the other side */
811 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 813 if (recv_bytes > recv_size)
814 recv_bytes = recv_size;
0206e353 815
4f7f7b7e
CW		 816 for (i = 0; i < recv_bytes; i += 4)
817 unpack_aux(I915_READ(ch_data + i),
818 recv + i, recv_bytes - i);
a4fc5ed6 819
9ee32fea
DV		 820 ret = recv_bytes;
821out:
822 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 823 intel_aux_display_runtime_put(dev_priv);
9ee32fea 824
884f19e9
JN		 825 if (vdd)
826 edp_panel_vdd_off(intel_dp, false);
827
773538e8 828 pps_unlock(intel_dp);
e39b999a 829
9ee32fea 830 return ret;
a4fc5ed6
KP		 831}
832
a6c8aff0
JN		 833#define BARE_ADDRESS_SIZE 3
834#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 835static ssize_t
836intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 837{
9d1a1031
JN		 838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
839 uint8_t txbuf[20], rxbuf[20];
840 size_t txsize, rxsize;
a4fc5ed6 841 int ret;
a4fc5ed6 842
9d1a1031
JN		 843 txbuf[0] = msg->request << 4;
844 txbuf[1] = msg->address >> 8;
845 txbuf[2] = msg->address & 0xff;
846 txbuf[3] = msg->size - 1;
46a5ae9f 847
9d1a1031
JN		 848 switch (msg->request & ~DP_AUX_I2C_MOT) {
849 case DP_AUX_NATIVE_WRITE:
850 case DP_AUX_I2C_WRITE:
a6c8aff0 851 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 852 rxsize = 1;
f51a44b9 853
9d1a1031
JN		 854 if (WARN_ON(txsize > 20))
855 return -E2BIG;
a4fc5ed6 856
9d1a1031 857 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 858
9d1a1031
JN		 859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
860 if (ret > 0) {
861 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 862
9d1a1031
JN		 863 /* Return payload size. */
864 ret = msg->size;
865 }
866 break;
46a5ae9f 867
9d1a1031
JN		 868 case DP_AUX_NATIVE_READ:
869 case DP_AUX_I2C_READ:
a6c8aff0 870 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 871 rxsize = msg->size + 1;
a4fc5ed6 872
9d1a1031
JN		 873 if (WARN_ON(rxsize > 20))
874 return -E2BIG;
a4fc5ed6 875
9d1a1031
JN		 876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
877 if (ret > 0) {
878 msg->reply = rxbuf[0] >> 4;
879 /*
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
882 *
883 * Return payload size.
884 */
885 ret--;
886 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 887 }
9d1a1031
JN		 888 break;
889
890 default:
891 ret = -EINVAL;
892 break;
a4fc5ed6 893 }
f51a44b9 894
9d1a1031 895 return ret;
a4fc5ed6
KP		 896}
897
9d1a1031
JN		 898static void
899intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
900{
901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
903 enum port port = intel_dig_port->port;
0b99836f 904 const char *name = NULL;
ab2c0672
DA		 905 int ret;
906
33ad6626
JN		 907 switch (port) {
908 case PORT_A:
909 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 910 name = "DPDDC-A";
ab2c0672 911 break;
33ad6626
JN		 912 case PORT_B:
913 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 914 name = "DPDDC-B";
ab2c0672 915 break;
33ad6626
JN		 916 case PORT_C:
917 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 918 name = "DPDDC-C";
ab2c0672 919 break;
33ad6626
JN		 920 case PORT_D:
921 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 922 name = "DPDDC-D";
33ad6626
JN		 923 break;
924 default:
925 BUG();
ab2c0672
DA		 926 }
927
33ad6626
JN		 928 if (!HAS_DDI(dev))
929 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 930
0b99836f 931 intel_dp->aux.name = name;
9d1a1031
JN		 932 intel_dp->aux.dev = dev->dev;
933 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 934
0b99836f
JN		 935 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
936 connector->base.kdev->kobj.name);
8316f337 937
4f71d0cb 938 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 939 if (ret < 0) {
4f71d0cb 940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 941 name, ret);
942 return;
ab2c0672 943 }
8a5e6aeb 944
0b99836f
JN		 945 ret = sysfs_create_link(&connector->base.kdev->kobj,
946 &intel_dp->aux.ddc.dev.kobj,
947 intel_dp->aux.ddc.dev.kobj.name);
948 if (ret < 0) {
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 950 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 951 }
a4fc5ed6
KP		 952}
953
80f65de3
ID		 954static void
955intel_dp_connector_unregister(struct intel_connector *intel_connector)
956{
957 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
958
0e32b39c
DA		 959 if (!intel_connector->mst_port)
960 sysfs_remove_link(&intel_connector->base.kdev->kobj,
961 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 962 intel_connector_unregister(intel_connector);
963}
964
0e50338c
DV		 965static void
966hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
967{
968 switch (link_bw) {
969 case DP_LINK_BW_1_62:
970 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
971 break;
972 case DP_LINK_BW_2_7:
973 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
974 break;
975 case DP_LINK_BW_5_4:
976 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
977 break;
978 }
979}
980
c6bb3538
DV		 981static void
982intel_dp_set_clock(struct intel_encoder *encoder,
983 struct intel_crtc_config *pipe_config, int link_bw)
984{
985 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 986 const struct dp_link_dpll *divisor = NULL;
987 int i, count = 0;
c6bb3538
DV		 988
989 if (IS_G4X(dev)) {
9dd4ffdf
CML		 990 divisor = gen4_dpll;
991 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 992 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 993 divisor = pch_dpll;
994 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 995 } else if (IS_CHERRYVIEW(dev)) {
996 divisor = chv_dpll;
997 count = ARRAY_SIZE(chv_dpll);
c6bb3538 998 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 999 divisor = vlv_dpll;
1000 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1001 }
9dd4ffdf
CML		 1002
1003 if (divisor && count) {
1004 for (i = 0; i < count; i++) {
1005 if (link_bw == divisor[i].link_bw) {
1006 pipe_config->dpll = divisor[i].dpll;
1007 pipe_config->clock_set = true;
1008 break;
1009 }
1010 }
c6bb3538
DV		 1011 }
1012}
1013
00c09d70 1014bool
5bfe2ac0
DV		 1015intel_dp_compute_config(struct intel_encoder *encoder,
1016 struct intel_crtc_config *pipe_config)
a4fc5ed6 1017{
5bfe2ac0 1018 struct drm_device *dev = encoder->base.dev;
36008365 1019 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1020 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1022 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1023 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1024 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1025 int lane_count, clock;
56071a20 1026 int min_lane_count = 1;
eeb6324d 1027 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1028 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1029 int min_clock = 0;
06ea66b6 1030 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1031 int bpp, mode_rate;
06ea66b6 1032 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1033 int link_avail, link_clock;
a4fc5ed6 1034
bc7d38a4 1035 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1036 pipe_config->has_pch_encoder = true;
1037
03afc4a2 1038 pipe_config->has_dp_encoder = true;
f769cd24 1039 pipe_config->has_drrs = false;
9ed109a7 1040 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1041
dd06f90e
JN		 1042 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1043 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1044 adjusted_mode);
2dd24552
JB		 1045 if (!HAS_PCH_SPLIT(dev))
1046 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1047 intel_connector->panel.fitting_mode);
1048 else
b074cec8
JB		 1049 intel_pch_panel_fitting(intel_crtc, pipe_config,
1050 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1051 }
1052
cb1793ce 1053 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1054 return false;
1055
083f9560
DV		 1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1058 max_lane_count, bws[max_clock],
1059 adjusted_mode->crtc_clock);
083f9560 1060
36008365
DV		 1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
3e7ca985 1063 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1064 if (is_edp(intel_dp)) {
1065 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv->vbt.edp_bpp);
1068 bpp = dev_priv->vbt.edp_bpp;
1069 }
1070
f4cdbc21
JN		 1071 if (IS_BROADWELL(dev)) {
1072 /* Yes, it's an ugly hack. */
1073 min_lane_count = max_lane_count;
1074 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
1075 min_lane_count);
1076 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 1077 min_lane_count = min(dev_priv->vbt.edp_lanes,
1078 max_lane_count);
1079 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
1080 min_lane_count);
1081 }
1082
1083 if (dev_priv->vbt.edp_rate) {
1084 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
1085 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
1086 bws[min_clock]);
1087 }
7984211e 1088 }
657445fe 1089
36008365 1090 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1091 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1092 bpp);
36008365 1093
c6930992
DA		 1094 for (clock = min_clock; clock <= max_clock; clock++) {
1095 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1096 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1097 link_avail = intel_dp_max_data_rate(link_clock,
1098 lane_count);
1099
1100 if (mode_rate <= link_avail) {
1101 goto found;
1102 }
1103 }
1104 }
1105 }
c4867936 1106
36008365 1107 return false;
3685a8f3 1108
36008365 1109found:
55bc60db
VS		 1110 if (intel_dp->color_range_auto) {
1111 /*
1112 * See:
1113 * CEA-861-E - 5.1 Default Encoding Parameters
1114 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1115 */
18316c8c 1116 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1117 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1118 else
1119 intel_dp->color_range = 0;
1120 }
1121
3685a8f3 1122 if (intel_dp->color_range)
50f3b016 1123 pipe_config->limited_color_range = true;
a4fc5ed6 1124
36008365
DV		 1125 intel_dp->link_bw = bws[clock];
1126 intel_dp->lane_count = lane_count;
657445fe 1127 pipe_config->pipe_bpp = bpp;
ff9a6750 1128 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1129
36008365
DV		 1130 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1131 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1132 pipe_config->port_clock, bpp);
36008365
DV		 1133 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1134 mode_rate, link_avail);
a4fc5ed6 1135
03afc4a2 1136 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1137 adjusted_mode->crtc_clock,
1138 pipe_config->port_clock,
03afc4a2 1139 &pipe_config->dp_m_n);
9d1a455b 1140
439d7ac0
PB		 1141 if (intel_connector->panel.downclock_mode != NULL &&
1142 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1143 pipe_config->has_drrs = true;
439d7ac0
PB		 1144 intel_link_compute_m_n(bpp, lane_count,
1145 intel_connector->panel.downclock_mode->clock,
1146 pipe_config->port_clock,
1147 &pipe_config->dp_m2_n2);
1148 }
1149
ea155f32 1150 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1151 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1152 else
1153 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1154
03afc4a2 1155 return true;
a4fc5ed6
KP		 1156}
1157
7c62a164 1158static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1159{
7c62a164
DV		 1160 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1161 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1162 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1163 struct drm_i915_private *dev_priv = dev->dev_private;
1164 u32 dpa_ctl;
1165
ff9a6750 1166 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1167 dpa_ctl = I915_READ(DP_A);
1168 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1169
ff9a6750 1170 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1171 /* For a long time we've carried around a ILK-DevA w/a for the
1172 * 160MHz clock. If we're really unlucky, it's still required.
1173 */
1174 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1175 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1176 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1177 } else {
1178 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1179 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1180 }
1ce17038 1181
ea9b6006
DV		 1182 I915_WRITE(DP_A, dpa_ctl);
1183
1184 POSTING_READ(DP_A);
1185 udelay(500);
1186}
1187
8ac33ed3 1188static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1189{
b934223d 1190 struct drm_device *dev = encoder->base.dev;
417e822d 1191 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1192 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1193 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1194 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1195 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1196
417e822d 1197 /*
1a2eb460 1198 * There are four kinds of DP registers:
417e822d
KP		 1199 *
1200 * IBX PCH
1a2eb460
KP		 1201 * SNB CPU
1202 * IVB CPU
417e822d
KP		 1203 * CPT PCH
1204 *
1205 * IBX PCH and CPU are the same for almost everything,
1206 * except that the CPU DP PLL is configured in this
1207 * register
1208 *
1209 * CPT PCH is quite different, having many bits moved
1210 * to the TRANS_DP_CTL register instead. That
1211 * configuration happens (oddly) in ironlake_pch_enable
1212 */
9c9e7927 1213
417e822d
KP		 1214 /* Preserve the BIOS-computed detected bit. This is
1215 * supposed to be read-only.
1216 */
1217 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1218
417e822d 1219 /* Handle DP bits in common between all three register formats */
417e822d 1220 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1221 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1222
9ed109a7 1223 if (crtc->config.has_audio) {
e0dac65e 1224 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1225 pipe_name(crtc->pipe));
ea5b213a 1226 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1227 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1228 }
247d89f6 1229
417e822d 1230 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1231
bc7d38a4 1232 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1233 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1234 intel_dp->DP |= DP_SYNC_HS_HIGH;
1235 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1236 intel_dp->DP |= DP_SYNC_VS_HIGH;
1237 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1238
6aba5b6c 1239 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1240 intel_dp->DP |= DP_ENHANCED_FRAMING;
1241
7c62a164 1242 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1243 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1244 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1245 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1246
1247 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1248 intel_dp->DP |= DP_SYNC_HS_HIGH;
1249 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1250 intel_dp->DP |= DP_SYNC_VS_HIGH;
1251 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1252
6aba5b6c 1253 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1254 intel_dp->DP |= DP_ENHANCED_FRAMING;
1255
44f37d1f
CML		 1256 if (!IS_CHERRYVIEW(dev)) {
1257 if (crtc->pipe == 1)
1258 intel_dp->DP |= DP_PIPEB_SELECT;
1259 } else {
1260 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1261 }
417e822d
KP		 1262 } else {
1263 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1264 }
a4fc5ed6
KP		 1265}
1266
ffd6749d
PZ		 1267#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1268#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1269
1a5ef5b7
PZ		 1270#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1271#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1272
ffd6749d
PZ		 1273#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1274#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1275
4be73780 1276static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1277 u32 mask,
1278 u32 value)
bd943159 1279{
30add22d 1280 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1281 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1282 u32 pp_stat_reg, pp_ctrl_reg;
1283
e39b999a
VS		 1284 lockdep_assert_held(&dev_priv->pps_mutex);
1285
bf13e81b
JN		 1286 pp_stat_reg = _pp_stat_reg(intel_dp);
1287 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1288
99ea7127 1289 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1290 mask, value,
1291 I915_READ(pp_stat_reg),
1292 I915_READ(pp_ctrl_reg));
32ce697c 1293
453c5420 1294 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1295 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1296 I915_READ(pp_stat_reg),
1297 I915_READ(pp_ctrl_reg));
32ce697c 1298 }
54c136d4
CW		 1299
1300 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1301}
32ce697c 1302
4be73780 1303static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1304{
1305 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1306 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1307}
1308
4be73780 1309static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1310{
1311 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1312 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1313}
1314
4be73780 1315static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1316{
1317 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1318
1319 /* When we disable the VDD override bit last we have to do the manual
1320 * wait. */
1321 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1322 intel_dp->panel_power_cycle_delay);
1323
4be73780 1324 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1325}
1326
4be73780 1327static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1328{
1329 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1330 intel_dp->backlight_on_delay);
1331}
1332
4be73780 1333static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1334{
1335 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1336 intel_dp->backlight_off_delay);
1337}
99ea7127 1338
832dd3c1
KP		 1339/* Read the current pp_control value, unlocking the register if it
1340 * is locked
1341 */
1342
453c5420 1343static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1344{
453c5420
JB		 1345 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 u32 control;
832dd3c1 1348
e39b999a
VS		 1349 lockdep_assert_held(&dev_priv->pps_mutex);
1350
bf13e81b 1351 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1352 control &= ~PANEL_UNLOCK_MASK;
1353 control |= PANEL_UNLOCK_REGS;
1354 return control;
bd943159
KP		 1355}
1356
1e0560e0 1357static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1358{
30add22d 1359 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1360 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1361 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1362 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1363 enum intel_display_power_domain power_domain;
5d613501 1364 u32 pp;
453c5420 1365 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1366 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1367
e39b999a
VS		 1368 lockdep_assert_held(&dev_priv->pps_mutex);
1369
97af61f5 1370 if (!is_edp(intel_dp))
adddaaf4 1371 return false;
bd943159
KP		 1372
1373 intel_dp->want_panel_vdd = true;
99ea7127 1374
4be73780 1375 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1376 return need_to_disable;
b0665d57 1377
4e6e1a54
ID		 1378 power_domain = intel_display_port_power_domain(intel_encoder);
1379 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1380
b0665d57 1381 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1382
4be73780
DV		 1383 if (!edp_have_panel_power(intel_dp))
1384 wait_panel_power_cycle(intel_dp);
99ea7127 1385
453c5420 1386 pp = ironlake_get_pp_control(intel_dp);
5d613501 1387 pp |= EDP_FORCE_VDD;
ebf33b18 1388
bf13e81b
JN		 1389 pp_stat_reg = _pp_stat_reg(intel_dp);
1390 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1391
1392 I915_WRITE(pp_ctrl_reg, pp);
1393 POSTING_READ(pp_ctrl_reg);
1394 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1395 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1396 /*
1397 * If the panel wasn't on, delay before accessing aux channel
1398 */
4be73780 1399 if (!edp_have_panel_power(intel_dp)) {
bd943159 1400 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1401 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1402 }
adddaaf4
JN		 1403
1404 return need_to_disable;
1405}
1406
b80d6c78 1407void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1408{
c695b6b6 1409 bool vdd;
adddaaf4 1410
c695b6b6
VS		 1411 if (!is_edp(intel_dp))
1412 return;
1413
773538e8 1414 pps_lock(intel_dp);
c695b6b6 1415 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1416 pps_unlock(intel_dp);
c695b6b6
VS		 1417
1418 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1419}
1420
4be73780 1421static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1422{
30add22d 1423 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1424 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1425 struct intel_digital_port *intel_dig_port =
1426 dp_to_dig_port(intel_dp);
1427 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1428 enum intel_display_power_domain power_domain;
5d613501 1429 u32 pp;
453c5420 1430 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1431
e39b999a 1432 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1433
15e899a0
VS		 1434 WARN_ON(intel_dp->want_panel_vdd);
1435
1436 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1437 return;
4e6e1a54 1438
be2c9196 1439 DRM_DEBUG_KMS("Turning eDP VDD off\n");
b0665d57 1440
be2c9196
VS		 1441 pp = ironlake_get_pp_control(intel_dp);
1442 pp &= ~EDP_FORCE_VDD;
bd943159 1443
be2c9196
VS		 1444 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1445 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1446
be2c9196
VS		 1447 I915_WRITE(pp_ctrl_reg, pp);
1448 POSTING_READ(pp_ctrl_reg);
99ea7127 1449
be2c9196
VS		 1450 /* Make sure sequencer is idle before allowing subsequent activity */
1451 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1452 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1453
be2c9196
VS		 1454 if ((pp & POWER_TARGET_ON) == 0)
1455 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1456
be2c9196
VS		 1457 power_domain = intel_display_port_power_domain(intel_encoder);
1458 intel_display_power_put(dev_priv, power_domain);
bd943159 1459}
5d613501 1460
4be73780 1461static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1462{
1463 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1464 struct intel_dp, panel_vdd_work);
bd943159 1465
773538e8 1466 pps_lock(intel_dp);
15e899a0
VS		 1467 if (!intel_dp->want_panel_vdd)
1468 edp_panel_vdd_off_sync(intel_dp);
773538e8 1469 pps_unlock(intel_dp);
bd943159
KP		 1470}
1471
aba86890
ID		 1472static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1473{
1474 unsigned long delay;
1475
1476 /*
1477 * Queue the timer to fire a long time from now (relative to the power
1478 * down delay) to keep the panel power up across a sequence of
1479 * operations.
1480 */
1481 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1482 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1483}
1484
4be73780 1485static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1486{
e39b999a
VS		 1487 struct drm_i915_private *dev_priv =
1488 intel_dp_to_dev(intel_dp)->dev_private;
1489
1490 lockdep_assert_held(&dev_priv->pps_mutex);
1491
97af61f5
KP		 1492 if (!is_edp(intel_dp))
1493 return;
5d613501 1494
bd943159 1495 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1496
bd943159
KP		 1497 intel_dp->want_panel_vdd = false;
1498
aba86890 1499 if (sync)
4be73780 1500 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1501 else
1502 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1503}
1504
1e0560e0
VS		 1505static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1506{
e39b999a
VS		 1507 if (!is_edp(intel_dp))
1508 return;
1509
773538e8 1510 pps_lock(intel_dp);
1e0560e0 1511 edp_panel_vdd_off(intel_dp, sync);
773538e8 1512 pps_unlock(intel_dp);
1e0560e0
VS		 1513}
1514
4be73780 1515void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1516{
30add22d 1517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1518 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1519 u32 pp;
453c5420 1520 u32 pp_ctrl_reg;
9934c132 1521
97af61f5 1522 if (!is_edp(intel_dp))
bd943159 1523 return;
99ea7127
KP		 1524
1525 DRM_DEBUG_KMS("Turn eDP power on\n");
1526
773538e8 1527 pps_lock(intel_dp);
e39b999a 1528
4be73780 1529 if (edp_have_panel_power(intel_dp)) {
99ea7127 1530 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1531 goto out;
99ea7127 1532 }
9934c132 1533
4be73780 1534 wait_panel_power_cycle(intel_dp);
37c6c9b0 1535
bf13e81b 1536 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1537 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1538 if (IS_GEN5(dev)) {
1539 /* ILK workaround: disable reset around power sequence */
1540 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1541 I915_WRITE(pp_ctrl_reg, pp);
1542 POSTING_READ(pp_ctrl_reg);
05ce1a49 1543 }
37c6c9b0 1544
1c0ae80a 1545 pp |= POWER_TARGET_ON;
99ea7127
KP		 1546 if (!IS_GEN5(dev))
1547 pp |= PANEL_POWER_RESET;
1548
453c5420
JB		 1549 I915_WRITE(pp_ctrl_reg, pp);
1550 POSTING_READ(pp_ctrl_reg);
9934c132 1551
4be73780 1552 wait_panel_on(intel_dp);
dce56b3c 1553 intel_dp->last_power_on = jiffies;
9934c132 1554
05ce1a49
KP		 1555 if (IS_GEN5(dev)) {
1556 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1557 I915_WRITE(pp_ctrl_reg, pp);
1558 POSTING_READ(pp_ctrl_reg);
05ce1a49 1559 }
e39b999a
VS		 1560
1561 out:
773538e8 1562 pps_unlock(intel_dp);
9934c132
JB		 1563}
1564
4be73780 1565void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1566{
4e6e1a54
ID		 1567 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1568 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1570 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1571 enum intel_display_power_domain power_domain;
99ea7127 1572 u32 pp;
453c5420 1573 u32 pp_ctrl_reg;
9934c132 1574
97af61f5
KP		 1575 if (!is_edp(intel_dp))
1576 return;
37c6c9b0 1577
99ea7127 1578 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1579
773538e8 1580 pps_lock(intel_dp);
e39b999a 1581
24f3e092
JN		 1582 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1583
453c5420 1584 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1585 /* We need to switch off panel power _and_ force vdd, for otherwise some
1586 * panels get very unhappy and cease to work. */
b3064154
PJ		 1587 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1588 EDP_BLC_ENABLE);
453c5420 1589
bf13e81b 1590 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1591
849e39f5
PZ		 1592 intel_dp->want_panel_vdd = false;
1593
453c5420
JB		 1594 I915_WRITE(pp_ctrl_reg, pp);
1595 POSTING_READ(pp_ctrl_reg);
9934c132 1596
dce56b3c 1597 intel_dp->last_power_cycle = jiffies;
4be73780 1598 wait_panel_off(intel_dp);
849e39f5
PZ		 1599
1600 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1601 power_domain = intel_display_port_power_domain(intel_encoder);
1602 intel_display_power_put(dev_priv, power_domain);
e39b999a 1603
773538e8 1604 pps_unlock(intel_dp);
9934c132
JB		 1605}
1606
1250d107
JN		 1607/* Enable backlight in the panel power control. */
1608static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1609{
da63a9f2
PZ		 1610 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1611 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 u32 pp;
453c5420 1614 u32 pp_ctrl_reg;
32f9d658 1615
01cb9ea6
JB		 1616 /*
1617 * If we enable the backlight right away following a panel power
1618 * on, we may see slight flicker as the panel syncs with the eDP
1619 * link. So delay a bit to make sure the image is solid before
1620 * allowing it to appear.
1621 */
4be73780 1622 wait_backlight_on(intel_dp);
e39b999a 1623
773538e8 1624 pps_lock(intel_dp);
e39b999a 1625
453c5420 1626 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1627 pp |= EDP_BLC_ENABLE;
453c5420 1628
bf13e81b 1629 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1630
1631 I915_WRITE(pp_ctrl_reg, pp);
1632 POSTING_READ(pp_ctrl_reg);
e39b999a 1633
773538e8 1634 pps_unlock(intel_dp);
32f9d658
ZW		 1635}
1636
1250d107
JN		 1637/* Enable backlight PWM and backlight PP control. */
1638void intel_edp_backlight_on(struct intel_dp *intel_dp)
1639{
1640 if (!is_edp(intel_dp))
1641 return;
1642
1643 DRM_DEBUG_KMS("\n");
1644
1645 intel_panel_enable_backlight(intel_dp->attached_connector);
1646 _intel_edp_backlight_on(intel_dp);
1647}
1648
1649/* Disable backlight in the panel power control. */
1650static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1651{
30add22d 1652 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 u32 pp;
453c5420 1655 u32 pp_ctrl_reg;
32f9d658 1656
e39b999a
VS		 1657 if (!is_edp(intel_dp))
1658 return;
1659
773538e8 1660 pps_lock(intel_dp);
e39b999a 1661
453c5420 1662 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1663 pp &= ~EDP_BLC_ENABLE;
453c5420 1664
bf13e81b 1665 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1666
1667 I915_WRITE(pp_ctrl_reg, pp);
1668 POSTING_READ(pp_ctrl_reg);
f7d2323c 1669
773538e8 1670 pps_unlock(intel_dp);
e39b999a
VS		 1671
1672 intel_dp->last_backlight_off = jiffies;
f7d2323c 1673 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1674}
1675
1676/* Disable backlight PP control and backlight PWM. */
1677void intel_edp_backlight_off(struct intel_dp *intel_dp)
1678{
1679 if (!is_edp(intel_dp))
1680 return;
1681
1682 DRM_DEBUG_KMS("\n");
f7d2323c 1683
1250d107 1684 _intel_edp_backlight_off(intel_dp);
f7d2323c 1685 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1686}
a4fc5ed6 1687
73580fb7
JN		 1688/*
1689 * Hook for controlling the panel power control backlight through the bl_power
1690 * sysfs attribute. Take care to handle multiple calls.
1691 */
1692static void intel_edp_backlight_power(struct intel_connector *connector,
1693 bool enable)
1694{
1695 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1696 bool is_enabled;
1697
773538e8 1698 pps_lock(intel_dp);
e39b999a 1699 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1700 pps_unlock(intel_dp);
73580fb7
JN		 1701
1702 if (is_enabled == enable)
1703 return;
1704
23ba9373
JN		 1705 DRM_DEBUG_KMS("panel power control backlight %s\n",
1706 enable ? "enable" : "disable");
73580fb7
JN		 1707
1708 if (enable)
1709 _intel_edp_backlight_on(intel_dp);
1710 else
1711 _intel_edp_backlight_off(intel_dp);
1712}
1713
2bd2ad64 1714static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1715{
da63a9f2
PZ		 1716 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1717 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1718 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720 u32 dpa_ctl;
1721
2bd2ad64
DV		 1722 assert_pipe_disabled(dev_priv,
1723 to_intel_crtc(crtc)->pipe);
1724
d240f20f
JB		 1725 DRM_DEBUG_KMS("\n");
1726 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1727 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1728 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1729
1730 /* We don't adjust intel_dp->DP while tearing down the link, to
1731 * facilitate link retraining (e.g. after hotplug). Hence clear all
1732 * enable bits here to ensure that we don't enable too much. */
1733 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1734 intel_dp->DP |= DP_PLL_ENABLE;
1735 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1736 POSTING_READ(DP_A);
1737 udelay(200);
d240f20f
JB		 1738}
1739
2bd2ad64 1740static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1741{
da63a9f2
PZ		 1742 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1743 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1744 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1745 struct drm_i915_private *dev_priv = dev->dev_private;
1746 u32 dpa_ctl;
1747
2bd2ad64
DV		 1748 assert_pipe_disabled(dev_priv,
1749 to_intel_crtc(crtc)->pipe);
1750
d240f20f 1751 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1752 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1753 "dp pll off, should be on\n");
1754 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1755
1756 /* We can't rely on the value tracked for the DP register in
1757 * intel_dp->DP because link_down must not change that (otherwise link
1758 * re-training will fail. */
298b0b39 1759 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1760 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1761 POSTING_READ(DP_A);
d240f20f
JB		 1762 udelay(200);
1763}
1764
c7ad3810 1765/* If the sink supports it, try to set the power state appropriately */
c19b0669 1766void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1767{
1768 int ret, i;
1769
1770 /* Should have a valid DPCD by this point */
1771 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1772 return;
1773
1774 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1775 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1776 DP_SET_POWER_D3);
c7ad3810
JB		 1777 } else {
1778 /*
1779 * When turning on, we need to retry for 1ms to give the sink
1780 * time to wake up.
1781 */
1782 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1783 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1784 DP_SET_POWER_D0);
c7ad3810
JB		 1785 if (ret == 1)
1786 break;
1787 msleep(1);
1788 }
1789 }
f9cac721
JN		 1790
1791 if (ret != 1)
1792 DRM_DEBUG_KMS("failed to %s sink power state\n",
1793 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1794}
1795
19d8fe15
DV		 1796static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1797 enum pipe *pipe)
d240f20f 1798{
19d8fe15 1799 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1800 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1801 struct drm_device *dev = encoder->base.dev;
1802 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1803 enum intel_display_power_domain power_domain;
1804 u32 tmp;
1805
1806 power_domain = intel_display_port_power_domain(encoder);
1807 if (!intel_display_power_enabled(dev_priv, power_domain))
1808 return false;
1809
1810 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1811
1812 if (!(tmp & DP_PORT_EN))
1813 return false;
1814
bc7d38a4 1815 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1816 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1817 } else if (IS_CHERRYVIEW(dev)) {
1818 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1819 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1820 *pipe = PORT_TO_PIPE(tmp);
1821 } else {
1822 u32 trans_sel;
1823 u32 trans_dp;
1824 int i;
1825
1826 switch (intel_dp->output_reg) {
1827 case PCH_DP_B:
1828 trans_sel = TRANS_DP_PORT_SEL_B;
1829 break;
1830 case PCH_DP_C:
1831 trans_sel = TRANS_DP_PORT_SEL_C;
1832 break;
1833 case PCH_DP_D:
1834 trans_sel = TRANS_DP_PORT_SEL_D;
1835 break;
1836 default:
1837 return true;
1838 }
1839
055e393f 1840 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1841 trans_dp = I915_READ(TRANS_DP_CTL(i));
1842 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1843 *pipe = i;
1844 return true;
1845 }
1846 }
19d8fe15 1847
4a0833ec
DV		 1848 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1849 intel_dp->output_reg);
1850 }
d240f20f 1851
19d8fe15
DV		 1852 return true;
1853}
d240f20f 1854
045ac3b5
JB		 1855static void intel_dp_get_config(struct intel_encoder *encoder,
1856 struct intel_crtc_config *pipe_config)
1857{
1858 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1859 u32 tmp, flags = 0;
63000ef6
XZ		 1860 struct drm_device *dev = encoder->base.dev;
1861 struct drm_i915_private *dev_priv = dev->dev_private;
1862 enum port port = dp_to_dig_port(intel_dp)->port;
1863 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1864 int dotclock;
045ac3b5 1865
9ed109a7
DV		 1866 tmp = I915_READ(intel_dp->output_reg);
1867 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1868 pipe_config->has_audio = true;
1869
63000ef6 1870 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1871 if (tmp & DP_SYNC_HS_HIGH)
1872 flags |= DRM_MODE_FLAG_PHSYNC;
1873 else
1874 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1875
63000ef6
XZ		 1876 if (tmp & DP_SYNC_VS_HIGH)
1877 flags |= DRM_MODE_FLAG_PVSYNC;
1878 else
1879 flags |= DRM_MODE_FLAG_NVSYNC;
1880 } else {
1881 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1882 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1883 flags |= DRM_MODE_FLAG_PHSYNC;
1884 else
1885 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1886
63000ef6
XZ		 1887 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1888 flags |= DRM_MODE_FLAG_PVSYNC;
1889 else
1890 flags |= DRM_MODE_FLAG_NVSYNC;
1891 }
045ac3b5
JB		 1892
1893 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1894
eb14cb74
VS		 1895 pipe_config->has_dp_encoder = true;
1896
1897 intel_dp_get_m_n(crtc, pipe_config);
1898
18442d08 1899 if (port == PORT_A) {
f1f644dc
JB		 1900 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1901 pipe_config->port_clock = 162000;
1902 else
1903 pipe_config->port_clock = 270000;
1904 }
18442d08
VS		 1905
1906 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1907 &pipe_config->dp_m_n);
1908
1909 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1910 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1911
241bfc38 1912 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1913
c6cd2ee2
JN		 1914 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1915 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1916 /*
1917 * This is a big fat ugly hack.
1918 *
1919 * Some machines in UEFI boot mode provide us a VBT that has 18
1920 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1921 * unknown we fail to light up. Yet the same BIOS boots up with
1922 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1923 * max, not what it tells us to use.
1924 *
1925 * Note: This will still be broken if the eDP panel is not lit
1926 * up by the BIOS, and thus we can't get the mode at module
1927 * load.
1928 */
1929 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1930 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1931 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1932 }
045ac3b5
JB		 1933}
1934
34eb7579 1935static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1936{
34eb7579 1937 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1938}
1939
2b28bb1b
RV		 1940static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1941{
1942 struct drm_i915_private *dev_priv = dev->dev_private;
1943
18b5992c 1944 if (!HAS_PSR(dev))
2b28bb1b
RV		 1945 return false;
1946
18b5992c 1947 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1948}
1949
1950static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1951 struct edp_vsc_psr *vsc_psr)
1952{
1953 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1954 struct drm_device *dev = dig_port->base.base.dev;
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1957 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1958 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1959 uint32_t *data = (uint32_t *) vsc_psr;
1960 unsigned int i;
1961
1962 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1963 the video DIP being updated before program video DIP data buffer
1964 registers for DIP being updated. */
1965 I915_WRITE(ctl_reg, 0);
1966 POSTING_READ(ctl_reg);
1967
1968 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1969 if (i < sizeof(struct edp_vsc_psr))
1970 I915_WRITE(data_reg + i, *data++);
1971 else
1972 I915_WRITE(data_reg + i, 0);
1973 }
1974
1975 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1976 POSTING_READ(ctl_reg);
1977}
1978
1979static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1980{
1981 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct edp_vsc_psr psr_vsc;
1984
2b28bb1b
RV		 1985 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1986 memset(&psr_vsc, 0, sizeof(psr_vsc));
1987 psr_vsc.sdp_header.HB0 = 0;
1988 psr_vsc.sdp_header.HB1 = 0x7;
1989 psr_vsc.sdp_header.HB2 = 0x2;
1990 psr_vsc.sdp_header.HB3 = 0x8;
1991 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1992
1993 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1994 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1995 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1996}
1997
1998static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1999{
0e0ae652
RV		 2000 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2001 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2002 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2003 uint32_t aux_clock_divider;
2b28bb1b
RV		 2004 int precharge = 0x3;
2005 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 2006 bool only_standby = false;
2b28bb1b 2007
ec5b01dd
DL		 2008 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2009
0e0ae652
RV		 2010 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2011 only_standby = true;
2012
2b28bb1b 2013 /* Enable PSR in sink */
0e0ae652 2014 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2015 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2016 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2017 else
9d1a1031
JN		 2018 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2019 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2020
2021 /* Setup AUX registers */
18b5992c
BW		 2022 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2023 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2024 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 2025 DP_AUX_CH_CTL_TIME_OUT_400us |
2026 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2027 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2028 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2029}
2030
2031static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2032{
0e0ae652
RV		 2033 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2034 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2035 struct drm_i915_private *dev_priv = dev->dev_private;
2036 uint32_t max_sleep_time = 0x1f;
2037 uint32_t idle_frames = 1;
2038 uint32_t val = 0x0;
ed8546ac 2039 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2040 bool only_standby = false;
2041
2042 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2043 only_standby = true;
2b28bb1b 2044
0e0ae652 2045 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2046 val |= EDP_PSR_LINK_STANDBY;
2047 val |= EDP_PSR_TP2_TP3_TIME_0us;
2048 val |= EDP_PSR_TP1_TIME_0us;
2049 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2050 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2051 } else
2052 val |= EDP_PSR_LINK_DISABLE;
2053
18b5992c 2054 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2055 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2056 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2057 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2058 EDP_PSR_ENABLE);
2059}
2060
3f51e471
RV		 2061static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2062{
2063 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2064 struct drm_device *dev = dig_port->base.base.dev;
2065 struct drm_i915_private *dev_priv = dev->dev_private;
2066 struct drm_crtc *crtc = dig_port->base.base.crtc;
2067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2068
f0355c4a 2069 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2070 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2071 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2072
a031d709
RV		 2073 dev_priv->psr.source_ok = false;
2074
9ca15301 2075 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2076 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2077 return false;
2078 }
2079
d330a953 2080 if (!i915.enable_psr) {
105b7c11 2081 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2082 return false;
2083 }
2084
4c8c7000
RV		 2085 /* Below limitations aren't valid for Broadwell */
2086 if (IS_BROADWELL(dev))
2087 goto out;
2088
3f51e471
RV		 2089 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2090 S3D_ENABLE) {
2091 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2092 return false;
2093 }
2094
ca73b4f0 2095 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2096 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2097 return false;
2098 }
2099
4c8c7000 2100 out:
a031d709 2101 dev_priv->psr.source_ok = true;
3f51e471
RV		 2102 return true;
2103}
2104
3d739d92 2105static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2106{
7c8f8a70
RV		 2107 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2108 struct drm_device *dev = intel_dig_port->base.base.dev;
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2110
3638379c
DV		 2111 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2112 WARN_ON(dev_priv->psr.active);
f0355c4a 2113 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2114
2b28bb1b
RV		 2115 /* Enable PSR on the panel */
2116 intel_edp_psr_enable_sink(intel_dp);
2117
2118 /* Enable PSR on the host */
2119 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2120
7c8f8a70 2121 dev_priv->psr.active = true;
2b28bb1b
RV		 2122}
2123
3d739d92
RV		 2124void intel_edp_psr_enable(struct intel_dp *intel_dp)
2125{
2126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2127 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2128
4704c573
RV		 2129 if (!HAS_PSR(dev)) {
2130 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2131 return;
2132 }
2133
34eb7579
RV		 2134 if (!is_edp_psr(intel_dp)) {
2135 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2136 return;
2137 }
2138
f0355c4a 2139 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2140 if (dev_priv->psr.enabled) {
2141 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 2142 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 2143 return;
2144 }
2145
9ca15301
DV		 2146 dev_priv->psr.busy_frontbuffer_bits = 0;
2147
16487254
RV		 2148 /* Setup PSR once */
2149 intel_edp_psr_setup(intel_dp);
2150
7c8f8a70 2151 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 2152 dev_priv->psr.enabled = intel_dp;
f0355c4a 2153 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2154}
2155
2b28bb1b
RV		 2156void intel_edp_psr_disable(struct intel_dp *intel_dp)
2157{
2158 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2159 struct drm_i915_private *dev_priv = dev->dev_private;
2160
f0355c4a
DV		 2161 mutex_lock(&dev_priv->psr.lock);
2162 if (!dev_priv->psr.enabled) {
2163 mutex_unlock(&dev_priv->psr.lock);
2164 return;
2165 }
2166
3638379c
DV		 2167 if (dev_priv->psr.active) {
2168 I915_WRITE(EDP_PSR_CTL(dev),
2169 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2170
2171 /* Wait till PSR is idle */
2172 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2173 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2174 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2175
3638379c
DV		 2176 dev_priv->psr.active = false;
2177 } else {
2178 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2179 }
7c8f8a70 2180
2807cf69 2181 dev_priv->psr.enabled = NULL;
f0355c4a 2182 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2183
2184 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2185}
2186
f02a326e 2187static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2188{
2189 struct drm_i915_private *dev_priv =
2190 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2191 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2192
f0355c4a
DV		 2193 mutex_lock(&dev_priv->psr.lock);
2194 intel_dp = dev_priv->psr.enabled;
2195
2807cf69 2196 if (!intel_dp)
f0355c4a 2197 goto unlock;
2807cf69 2198
9ca15301
DV		 2199 /*
2200 * The delayed work can race with an invalidate hence we need to
2201 * recheck. Since psr_flush first clears this and then reschedules we
2202 * won't ever miss a flush when bailing out here.
2203 */
2204 if (dev_priv->psr.busy_frontbuffer_bits)
2205 goto unlock;
2206
2207 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2208unlock:
2209 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2210}
2211
9ca15301 2212static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2213{
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215
3638379c
DV		 2216 if (dev_priv->psr.active) {
2217 u32 val = I915_READ(EDP_PSR_CTL(dev));
2218
2219 WARN_ON(!(val & EDP_PSR_ENABLE));
2220
2221 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2222
2223 dev_priv->psr.active = false;
2224 }
7c8f8a70 2225
9ca15301
DV		 2226}
2227
2228void intel_edp_psr_invalidate(struct drm_device *dev,
2229 unsigned frontbuffer_bits)
2230{
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 struct drm_crtc *crtc;
2233 enum pipe pipe;
2234
9ca15301
DV		 2235 mutex_lock(&dev_priv->psr.lock);
2236 if (!dev_priv->psr.enabled) {
2237 mutex_unlock(&dev_priv->psr.lock);
2238 return;
2239 }
2240
2241 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2242 pipe = to_intel_crtc(crtc)->pipe;
2243
2244 intel_edp_psr_do_exit(dev);
2245
2246 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2247
2248 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2249 mutex_unlock(&dev_priv->psr.lock);
2250}
2251
2252void intel_edp_psr_flush(struct drm_device *dev,
2253 unsigned frontbuffer_bits)
2254{
2255 struct drm_i915_private *dev_priv = dev->dev_private;
2256 struct drm_crtc *crtc;
2257 enum pipe pipe;
2258
9ca15301
DV		 2259 mutex_lock(&dev_priv->psr.lock);
2260 if (!dev_priv->psr.enabled) {
2261 mutex_unlock(&dev_priv->psr.lock);
2262 return;
2263 }
2264
2265 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2266 pipe = to_intel_crtc(crtc)->pipe;
2267 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2268
2269 /*
2270 * On Haswell sprite plane updates don't result in a psr invalidating
2271 * signal in the hardware. Which means we need to manually fake this in
2272 * software for all flushes, not just when we've seen a preceding
2273 * invalidation through frontbuffer rendering.
2274 */
2275 if (IS_HASWELL(dev) &&
2276 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2277 intel_edp_psr_do_exit(dev);
2278
2279 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2280 schedule_delayed_work(&dev_priv->psr.work,
2281 msecs_to_jiffies(100));
f0355c4a 2282 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2283}
2284
2285void intel_edp_psr_init(struct drm_device *dev)
2286{
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288
7c8f8a70 2289 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2290 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2291}
2292
e8cb4558 2293static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2294{
e8cb4558 2295 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2296 enum port port = dp_to_dig_port(intel_dp)->port;
2297 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2298
2299 /* Make sure the panel is off before trying to change the mode. But also
2300 * ensure that we have vdd while we switch off the panel. */
24f3e092 2301 intel_edp_panel_vdd_on(intel_dp);
4be73780 2302 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2303 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2304 intel_edp_panel_off(intel_dp);
3739850b
DV		 2305
2306 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2307 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2308 intel_dp_link_down(intel_dp);
d240f20f
JB		 2309}
2310
49277c31 2311static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2312{
2bd2ad64 2313 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2314 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2315
49277c31
VS		 2316 if (port != PORT_A)
2317 return;
2318
2319 intel_dp_link_down(intel_dp);
2320 ironlake_edp_pll_off(intel_dp);
2321}
2322
2323static void vlv_post_disable_dp(struct intel_encoder *encoder)
2324{
2325 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2326
2327 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2328}
2329
580d3811
VS		 2330static void chv_post_disable_dp(struct intel_encoder *encoder)
2331{
2332 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2333 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2334 struct drm_device *dev = encoder->base.dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct intel_crtc *intel_crtc =
2337 to_intel_crtc(encoder->base.crtc);
2338 enum dpio_channel ch = vlv_dport_to_channel(dport);
2339 enum pipe pipe = intel_crtc->pipe;
2340 u32 val;
2341
2342 intel_dp_link_down(intel_dp);
2343
2344 mutex_lock(&dev_priv->dpio_lock);
2345
2346 /* Propagate soft reset to data lane reset */
97fd4d5c 2347 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2348 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2349 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2350
97fd4d5c
VS		 2351 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2352 val |= CHV_PCS_REQ_SOFTRESET_EN;
2353 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2354
2355 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2356 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2357 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2358
2359 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2360 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2361 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2362
2363 mutex_unlock(&dev_priv->dpio_lock);
2364}
2365
e8cb4558 2366static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2367{
e8cb4558
DV		 2368 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2369 struct drm_device *dev = encoder->base.dev;
2370 struct drm_i915_private *dev_priv = dev->dev_private;
2371 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2372
0c33d8d7
DV		 2373 if (WARN_ON(dp_reg & DP_PORT_EN))
2374 return;
5d613501 2375
24f3e092 2376 intel_edp_panel_vdd_on(intel_dp);
4be73780 2377 intel_edp_panel_on(intel_dp);
1e0560e0 2378 intel_edp_panel_vdd_off(intel_dp, true);
43072a45
VS		 2379 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2380 intel_dp_start_link_train(intel_dp);
33a34e4e 2381 intel_dp_complete_link_train(intel_dp);
3ab9c637 2382 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2383}
89b667f8 2384
ecff4f3b
JN		 2385static void g4x_enable_dp(struct intel_encoder *encoder)
2386{
828f5c6e
JN		 2387 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2388
ecff4f3b 2389 intel_enable_dp(encoder);
4be73780 2390 intel_edp_backlight_on(intel_dp);
ab1f90f9 2391}
89b667f8 2392
ab1f90f9
JN		 2393static void vlv_enable_dp(struct intel_encoder *encoder)
2394{
828f5c6e
JN		 2395 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2396
4be73780 2397 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2398}
2399
ecff4f3b 2400static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2401{
2402 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2403 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2404
8ac33ed3
DV		 2405 intel_dp_prepare(encoder);
2406
d41f1efb
DV		 2407 /* Only ilk+ has port A */
2408 if (dport->port == PORT_A) {
2409 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2410 ironlake_edp_pll_on(intel_dp);
d41f1efb 2411 }
ab1f90f9
JN		 2412}
2413
a4a5d2f8
VS		 2414static void vlv_steal_power_sequencer(struct drm_device *dev,
2415 enum pipe pipe)
2416{
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 struct intel_encoder *encoder;
2419
2420 lockdep_assert_held(&dev_priv->pps_mutex);
2421
2422 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2423 base.head) {
2424 struct intel_dp *intel_dp;
773538e8 2425 enum port port;
a4a5d2f8
VS		 2426
2427 if (encoder->type != INTEL_OUTPUT_EDP)
2428 continue;
2429
2430 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2431 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2432
2433 if (intel_dp->pps_pipe != pipe)
2434 continue;
2435
2436 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2437 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2438
2439 /* make sure vdd is off before we steal it */
2440 edp_panel_vdd_off_sync(intel_dp);
2441
2442 intel_dp->pps_pipe = INVALID_PIPE;
2443 }
2444}
2445
2446static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2447{
2448 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2449 struct intel_encoder *encoder = &intel_dig_port->base;
2450 struct drm_device *dev = encoder->base.dev;
2451 struct drm_i915_private *dev_priv = dev->dev_private;
2452 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2453 struct edp_power_seq power_seq;
2454
2455 lockdep_assert_held(&dev_priv->pps_mutex);
2456
2457 if (intel_dp->pps_pipe == crtc->pipe)
2458 return;
2459
2460 /*
2461 * If another power sequencer was being used on this
2462 * port previously make sure to turn off vdd there while
2463 * we still have control of it.
2464 */
2465 if (intel_dp->pps_pipe != INVALID_PIPE)
2466 edp_panel_vdd_off_sync(intel_dp);
2467
2468 /*
2469 * We may be stealing the power
2470 * sequencer from another port.
2471 */
2472 vlv_steal_power_sequencer(dev, crtc->pipe);
2473
2474 /* now it's all ours */
2475 intel_dp->pps_pipe = crtc->pipe;
2476
2477 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2478 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2479
2480 /* init power sequencer on this pipe and port */
2481 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2482 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2483 &power_seq);
2484}
2485
ab1f90f9 2486static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2487{
2bd2ad64 2488 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2489 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2490 struct drm_device *dev = encoder->base.dev;
89b667f8 2491 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2492 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2493 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2494 int pipe = intel_crtc->pipe;
2495 u32 val;
a4fc5ed6 2496
ab1f90f9 2497 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2498
ab3c759a 2499 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2500 val = 0;
2501 if (pipe)
2502 val |= (1<<21);
2503 else
2504 val &= ~(1<<21);
2505 val |= 0x001000c4;
ab3c759a
CML		 2506 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2507 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2508 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2509
ab1f90f9
JN		 2510 mutex_unlock(&dev_priv->dpio_lock);
2511
2cac613b 2512 if (is_edp(intel_dp)) {
773538e8 2513 pps_lock(intel_dp);
a4a5d2f8 2514 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2515 pps_unlock(intel_dp);
2cac613b 2516 }
bf13e81b 2517
ab1f90f9
JN		 2518 intel_enable_dp(encoder);
2519
e4607fcf 2520 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2521}
2522
ecff4f3b 2523static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2524{
2525 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2526 struct drm_device *dev = encoder->base.dev;
2527 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2528 struct intel_crtc *intel_crtc =
2529 to_intel_crtc(encoder->base.crtc);
e4607fcf 2530 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2531 int pipe = intel_crtc->pipe;
89b667f8 2532
8ac33ed3
DV		 2533 intel_dp_prepare(encoder);
2534
89b667f8 2535 /* Program Tx lane resets to default */
0980a60f 2536 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2537 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2538 DPIO_PCS_TX_LANE2_RESET |
2539 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2540 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2541 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2542 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2543 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2544 DPIO_PCS_CLK_SOFT_RESET);
2545
2546 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2547 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2548 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2549 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2550 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2551}
2552
e4a1d846
CML		 2553static void chv_pre_enable_dp(struct intel_encoder *encoder)
2554{
2555 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2556 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2557 struct drm_device *dev = encoder->base.dev;
2558 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2559 struct intel_crtc *intel_crtc =
2560 to_intel_crtc(encoder->base.crtc);
2561 enum dpio_channel ch = vlv_dport_to_channel(dport);
2562 int pipe = intel_crtc->pipe;
2563 int data, i;
949c1d43 2564 u32 val;
e4a1d846 2565
e4a1d846 2566 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2567
2568 /* Deassert soft data lane reset*/
97fd4d5c 2569 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2570 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2571 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2572
2573 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2574 val |= CHV_PCS_REQ_SOFTRESET_EN;
2575 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2576
2577 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2578 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2579 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2580
97fd4d5c 2581 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2582 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2583 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2584
2585 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2586 for (i = 0; i < 4; i++) {
2587 /* Set the latency optimal bit */
2588 data = (i == 1) ? 0x0 : 0x6;
2589 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2590 data << DPIO_FRC_LATENCY_SHFIT);
2591
2592 /* Set the upar bit */
2593 data = (i == 1) ? 0x0 : 0x1;
2594 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2595 data << DPIO_UPAR_SHIFT);
2596 }
2597
2598 /* Data lane stagger programming */
2599 /* FIXME: Fix up value only after power analysis */
2600
2601 mutex_unlock(&dev_priv->dpio_lock);
2602
2603 if (is_edp(intel_dp)) {
773538e8 2604 pps_lock(intel_dp);
a4a5d2f8 2605 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2606 pps_unlock(intel_dp);
e4a1d846
CML		 2607 }
2608
2609 intel_enable_dp(encoder);
2610
2611 vlv_wait_port_ready(dev_priv, dport);
2612}
2613
9197c88b
VS		 2614static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2615{
2616 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2617 struct drm_device *dev = encoder->base.dev;
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619 struct intel_crtc *intel_crtc =
2620 to_intel_crtc(encoder->base.crtc);
2621 enum dpio_channel ch = vlv_dport_to_channel(dport);
2622 enum pipe pipe = intel_crtc->pipe;
2623 u32 val;
2624
625695f8
VS		 2625 intel_dp_prepare(encoder);
2626
9197c88b
VS		 2627 mutex_lock(&dev_priv->dpio_lock);
2628
b9e5ac3c
VS		 2629 /* program left/right clock distribution */
2630 if (pipe != PIPE_B) {
2631 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2632 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2633 if (ch == DPIO_CH0)
2634 val |= CHV_BUFLEFTENA1_FORCE;
2635 if (ch == DPIO_CH1)
2636 val |= CHV_BUFRIGHTENA1_FORCE;
2637 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2638 } else {
2639 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2640 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2641 if (ch == DPIO_CH0)
2642 val |= CHV_BUFLEFTENA2_FORCE;
2643 if (ch == DPIO_CH1)
2644 val |= CHV_BUFRIGHTENA2_FORCE;
2645 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2646 }
2647
9197c88b
VS		 2648 /* program clock channel usage */
2649 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2650 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2651 if (pipe != PIPE_B)
2652 val &= ~CHV_PCS_USEDCLKCHANNEL;
2653 else
2654 val |= CHV_PCS_USEDCLKCHANNEL;
2655 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2656
2657 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2658 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2659 if (pipe != PIPE_B)
2660 val &= ~CHV_PCS_USEDCLKCHANNEL;
2661 else
2662 val |= CHV_PCS_USEDCLKCHANNEL;
2663 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2664
2665 /*
2666 * This a a bit weird since generally CL
2667 * matches the pipe, but here we need to
2668 * pick the CL based on the port.
2669 */
2670 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2671 if (pipe != PIPE_B)
2672 val &= ~CHV_CMN_USEDCLKCHANNEL;
2673 else
2674 val |= CHV_CMN_USEDCLKCHANNEL;
2675 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2676
2677 mutex_unlock(&dev_priv->dpio_lock);
2678}
2679
a4fc5ed6 2680/*
df0c237d
JB		 2681 * Native read with retry for link status and receiver capability reads for
2682 * cases where the sink may still be asleep.
9d1a1031
JN		 2683 *
2684 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2685 * supposed to retry 3 times per the spec.
a4fc5ed6 2686 */
9d1a1031
JN		 2687static ssize_t
2688intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2689 void *buffer, size_t size)
a4fc5ed6 2690{
9d1a1031
JN		 2691 ssize_t ret;
2692 int i;
61da5fab 2693
61da5fab 2694 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2695 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2696 if (ret == size)
2697 return ret;
61da5fab
JB		 2698 msleep(1);
2699 }
a4fc5ed6 2700
9d1a1031 2701 return ret;
a4fc5ed6
KP		 2702}
2703
2704/*
2705 * Fetch AUX CH registers 0x202 - 0x207 which contain
2706 * link status information
2707 */
2708static bool
93f62dad 2709intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2710{
9d1a1031
JN		 2711 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2712 DP_LANE0_1_STATUS,
2713 link_status,
2714 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2715}
2716
1100244e 2717/* These are source-specific values. */
a4fc5ed6 2718static uint8_t
1a2eb460 2719intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2720{
30add22d 2721 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2722 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2723
9576c27f 2724 if (IS_VALLEYVIEW(dev))
bd60018a 2725 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2726 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2727 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2728 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2729 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2730 else
bd60018a 2731 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2732}
2733
2734static uint8_t
2735intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2736{
30add22d 2737 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2738 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2739
9576c27f 2740 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2741 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2742 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2743 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2744 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2745 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2746 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2747 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2748 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2749 default:
bd60018a 2750 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2751 }
e2fa6fba
P		 2752 } else if (IS_VALLEYVIEW(dev)) {
2753 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2754 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2755 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2756 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2757 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2758 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2759 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2760 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2761 default:
bd60018a 2762 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2763 }
bc7d38a4 2764 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2765 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2766 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2767 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2768 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2769 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2770 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2771 default:
bd60018a 2772 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2773 }
2774 } else {
2775 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2776 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2777 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2778 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2779 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2780 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2781 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2782 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2783 default:
bd60018a 2784 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2785 }
a4fc5ed6
KP		 2786 }
2787}
2788
e2fa6fba
P		 2789static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2790{
2791 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2794 struct intel_crtc *intel_crtc =
2795 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2796 unsigned long demph_reg_value, preemph_reg_value,
2797 uniqtranscale_reg_value;
2798 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2799 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2800 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2801
2802 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2803 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2804 preemph_reg_value = 0x0004000;
2805 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2806 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2807 demph_reg_value = 0x2B405555;
2808 uniqtranscale_reg_value = 0x552AB83A;
2809 break;
bd60018a 2810 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2811 demph_reg_value = 0x2B404040;
2812 uniqtranscale_reg_value = 0x5548B83A;
2813 break;
bd60018a 2814 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2815 demph_reg_value = 0x2B245555;
2816 uniqtranscale_reg_value = 0x5560B83A;
2817 break;
bd60018a 2818 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2819 demph_reg_value = 0x2B405555;
2820 uniqtranscale_reg_value = 0x5598DA3A;
2821 break;
2822 default:
2823 return 0;
2824 }
2825 break;
bd60018a 2826 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2827 preemph_reg_value = 0x0002000;
2828 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2829 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2830 demph_reg_value = 0x2B404040;
2831 uniqtranscale_reg_value = 0x5552B83A;
2832 break;
bd60018a 2833 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2834 demph_reg_value = 0x2B404848;
2835 uniqtranscale_reg_value = 0x5580B83A;
2836 break;
bd60018a 2837 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2838 demph_reg_value = 0x2B404040;
2839 uniqtranscale_reg_value = 0x55ADDA3A;
2840 break;
2841 default:
2842 return 0;
2843 }
2844 break;
bd60018a 2845 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2846 preemph_reg_value = 0x0000000;
2847 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2848 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2849 demph_reg_value = 0x2B305555;
2850 uniqtranscale_reg_value = 0x5570B83A;
2851 break;
bd60018a 2852 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2853 demph_reg_value = 0x2B2B4040;
2854 uniqtranscale_reg_value = 0x55ADDA3A;
2855 break;
2856 default:
2857 return 0;
2858 }
2859 break;
bd60018a 2860 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2861 preemph_reg_value = 0x0006000;
2862 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2863 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2864 demph_reg_value = 0x1B405555;
2865 uniqtranscale_reg_value = 0x55ADDA3A;
2866 break;
2867 default:
2868 return 0;
2869 }
2870 break;
2871 default:
2872 return 0;
2873 }
2874
0980a60f 2875 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2876 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2877 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2878 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2879 uniqtranscale_reg_value);
ab3c759a
CML		 2880 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2881 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2882 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2883 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2884 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2885
2886 return 0;
2887}
2888
e4a1d846
CML		 2889static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2890{
2891 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2894 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2895 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2896 uint8_t train_set = intel_dp->train_set[0];
2897 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2898 enum pipe pipe = intel_crtc->pipe;
2899 int i;
e4a1d846
CML		 2900
2901 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2902 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2903 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2904 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2905 deemph_reg_value = 128;
2906 margin_reg_value = 52;
2907 break;
bd60018a 2908 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2909 deemph_reg_value = 128;
2910 margin_reg_value = 77;
2911 break;
bd60018a 2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2913 deemph_reg_value = 128;
2914 margin_reg_value = 102;
2915 break;
bd60018a 2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2917 deemph_reg_value = 128;
2918 margin_reg_value = 154;
2919 /* FIXME extra to set for 1200 */
2920 break;
2921 default:
2922 return 0;
2923 }
2924 break;
bd60018a 2925 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2926 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2928 deemph_reg_value = 85;
2929 margin_reg_value = 78;
2930 break;
bd60018a 2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2932 deemph_reg_value = 85;
2933 margin_reg_value = 116;
2934 break;
bd60018a 2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2936 deemph_reg_value = 85;
2937 margin_reg_value = 154;
2938 break;
2939 default:
2940 return 0;
2941 }
2942 break;
bd60018a 2943 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2944 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2946 deemph_reg_value = 64;
2947 margin_reg_value = 104;
2948 break;
bd60018a 2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2950 deemph_reg_value = 64;
2951 margin_reg_value = 154;
2952 break;
2953 default:
2954 return 0;
2955 }
2956 break;
bd60018a 2957 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2958 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2960 deemph_reg_value = 43;
2961 margin_reg_value = 154;
2962 break;
2963 default:
2964 return 0;
2965 }
2966 break;
2967 default:
2968 return 0;
2969 }
2970
2971 mutex_lock(&dev_priv->dpio_lock);
2972
2973 /* Clear calc init */
1966e59e
VS		 2974 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2975 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2976 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2977
2978 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2979 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2980 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2981
2982 /* Program swing deemph */
f72df8db
VS		 2983 for (i = 0; i < 4; i++) {
2984 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2985 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2986 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2987 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2988 }
e4a1d846
CML		 2989
2990 /* Program swing margin */
f72df8db
VS		 2991 for (i = 0; i < 4; i++) {
2992 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2993 val &= ~DPIO_SWING_MARGIN000_MASK;
2994 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2995 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2996 }
e4a1d846
CML		 2997
2998 /* Disable unique transition scale */
f72df8db
VS		 2999 for (i = 0; i < 4; i++) {
3000 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3001 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3002 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3003 }
e4a1d846
CML		 3004
3005 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3006 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3007 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3008 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3009
3010 /*
3011 * The document said it needs to set bit 27 for ch0 and bit 26
3012 * for ch1. Might be a typo in the doc.
3013 * For now, for this unique transition scale selection, set bit
3014 * 27 for ch0 and ch1.
3015 */
f72df8db
VS		 3016 for (i = 0; i < 4; i++) {
3017 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3018 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3019 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3020 }
e4a1d846 3021
f72df8db
VS		 3022 for (i = 0; i < 4; i++) {
3023 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3024 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3025 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3026 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3027 }
e4a1d846
CML		 3028 }
3029
3030 /* Start swing calculation */
1966e59e
VS		 3031 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3032 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3033 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3034
3035 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3036 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3037 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3038
3039 /* LRC Bypass */
3040 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3041 val |= DPIO_LRC_BYPASS;
3042 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3043
3044 mutex_unlock(&dev_priv->dpio_lock);
3045
3046 return 0;
3047}
3048
a4fc5ed6 3049static void
0301b3ac
JN		 3050intel_get_adjust_train(struct intel_dp *intel_dp,
3051 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3052{
3053 uint8_t v = 0;
3054 uint8_t p = 0;
3055 int lane;
1a2eb460
KP		 3056 uint8_t voltage_max;
3057 uint8_t preemph_max;
a4fc5ed6 3058
33a34e4e 3059 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3060 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3061 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3062
3063 if (this_v > v)
3064 v = this_v;
3065 if (this_p > p)
3066 p = this_p;
3067 }
3068
1a2eb460 3069 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3070 if (v >= voltage_max)
3071 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3072
1a2eb460
KP		 3073 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3074 if (p >= preemph_max)
3075 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3076
3077 for (lane = 0; lane < 4; lane++)
33a34e4e 3078 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3079}
3080
3081static uint32_t
f0a3424e 3082intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3083{
3cf2efb1 3084 uint32_t signal_levels = 0;
a4fc5ed6 3085
3cf2efb1 3086 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3088 default:
3089 signal_levels |= DP_VOLTAGE_0_4;
3090 break;
bd60018a 3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3092 signal_levels |= DP_VOLTAGE_0_6;
3093 break;
bd60018a 3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3095 signal_levels |= DP_VOLTAGE_0_8;
3096 break;
bd60018a 3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3098 signal_levels |= DP_VOLTAGE_1_2;
3099 break;
3100 }
3cf2efb1 3101 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3102 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3103 default:
3104 signal_levels |= DP_PRE_EMPHASIS_0;
3105 break;
bd60018a 3106 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3107 signal_levels |= DP_PRE_EMPHASIS_3_5;
3108 break;
bd60018a 3109 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3110 signal_levels |= DP_PRE_EMPHASIS_6;
3111 break;
bd60018a 3112 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3113 signal_levels |= DP_PRE_EMPHASIS_9_5;
3114 break;
3115 }
3116 return signal_levels;
3117}
3118
e3421a18
ZW		 3119/* Gen6's DP voltage swing and pre-emphasis control */
3120static uint32_t
3121intel_gen6_edp_signal_levels(uint8_t train_set)
3122{
3c5a62b5
YL		 3123 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3124 DP_TRAIN_PRE_EMPHASIS_MASK);
3125 switch (signal_levels) {
bd60018a
SJ		 3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3128 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3130 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3131 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3133 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3136 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3137 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3139 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3140 default:
3c5a62b5
YL		 3141 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3142 "0x%x\n", signal_levels);
3143 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3144 }
3145}
3146
1a2eb460
KP		 3147/* Gen7's DP voltage swing and pre-emphasis control */
3148static uint32_t
3149intel_gen7_edp_signal_levels(uint8_t train_set)
3150{
3151 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3152 DP_TRAIN_PRE_EMPHASIS_MASK);
3153 switch (signal_levels) {
bd60018a 3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3155 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3157 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3159 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3160
bd60018a 3161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3162 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3164 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3165
bd60018a 3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3167 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3169 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3170
3171 default:
3172 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3173 "0x%x\n", signal_levels);
3174 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3175 }
3176}
3177
d6c0d722
PZ		 3178/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3179static uint32_t
f0a3424e 3180intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3181{
d6c0d722
PZ		 3182 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3183 DP_TRAIN_PRE_EMPHASIS_MASK);
3184 switch (signal_levels) {
bd60018a 3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3186 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3188 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3190 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3192 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3193
bd60018a 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3195 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3197 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3199 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3200
bd60018a 3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3202 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3204 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3205 default:
3206 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3207 "0x%x\n", signal_levels);
c5fe6a06 3208 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3209 }
a4fc5ed6
KP		 3210}
3211
f0a3424e
PZ		 3212/* Properly updates "DP" with the correct signal levels. */
3213static void
3214intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3215{
3216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3217 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3218 struct drm_device *dev = intel_dig_port->base.base.dev;
3219 uint32_t signal_levels, mask;
3220 uint8_t train_set = intel_dp->train_set[0];
3221
9576c27f 3222 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 3223 signal_levels = intel_hsw_signal_levels(train_set);
3224 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3225 } else if (IS_CHERRYVIEW(dev)) {
3226 signal_levels = intel_chv_signal_levels(intel_dp);
3227 mask = 0;
e2fa6fba
P		 3228 } else if (IS_VALLEYVIEW(dev)) {
3229 signal_levels = intel_vlv_signal_levels(intel_dp);
3230 mask = 0;
bc7d38a4 3231 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3232 signal_levels = intel_gen7_edp_signal_levels(train_set);
3233 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3234 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3235 signal_levels = intel_gen6_edp_signal_levels(train_set);
3236 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3237 } else {
3238 signal_levels = intel_gen4_signal_levels(train_set);
3239 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3240 }
3241
3242 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3243
3244 *DP = (*DP & ~mask) | signal_levels;
3245}
3246
a4fc5ed6 3247static bool
ea5b213a 3248intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3249 uint32_t *DP,
58e10eb9 3250 uint8_t dp_train_pat)
a4fc5ed6 3251{
174edf1f
PZ		 3252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3253 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3254 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3255 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 3256 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3257 int ret, len;
a4fc5ed6 3258
22b8bf17 3259 if (HAS_DDI(dev)) {
3ab9c637 3260 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 3261
3262 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3263 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3264 else
3265 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3266
3267 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3268 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3269 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 3270 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3271
3272 break;
3273 case DP_TRAINING_PATTERN_1:
3274 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3275 break;
3276 case DP_TRAINING_PATTERN_2:
3277 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3278 break;
3279 case DP_TRAINING_PATTERN_3:
3280 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3281 break;
3282 }
174edf1f 3283 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 3284
bc7d38a4 3285 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 3286 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 3287
3288 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3289 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3290 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 3291 break;
3292 case DP_TRAINING_PATTERN_1:
70aff66c 3293 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 3294 break;
3295 case DP_TRAINING_PATTERN_2:
70aff66c 3296 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3297 break;
3298 case DP_TRAINING_PATTERN_3:
3299 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 3300 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3301 break;
3302 }
3303
3304 } else {
aad3d14d
VS		 3305 if (IS_CHERRYVIEW(dev))
3306 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3307 else
3308 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 3309
3310 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3311 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3312 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 3313 break;
3314 case DP_TRAINING_PATTERN_1:
70aff66c 3315 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 3316 break;
3317 case DP_TRAINING_PATTERN_2:
70aff66c 3318 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 3319 break;
3320 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 3321 if (IS_CHERRYVIEW(dev)) {
3322 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3323 } else {
3324 DRM_ERROR("DP training pattern 3 not supported\n");
3325 *DP |= DP_LINK_TRAIN_PAT_2;
3326 }
47ea7542
PZ		 3327 break;
3328 }
3329 }
3330
70aff66c 3331 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3332 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3333
2cdfe6c8
JN		 3334 buf[0] = dp_train_pat;
3335 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3336 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3337 /* don't write DP_TRAINING_LANEx_SET on disable */
3338 len = 1;
3339 } else {
3340 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3341 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3342 len = intel_dp->lane_count + 1;
47ea7542 3343 }
a4fc5ed6 3344
9d1a1031
JN		 3345 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3346 buf, len);
2cdfe6c8
JN		 3347
3348 return ret == len;
a4fc5ed6
KP		 3349}
3350
70aff66c
JN		 3351static bool
3352intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3353 uint8_t dp_train_pat)
3354{
953d22e8 3355 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3356 intel_dp_set_signal_levels(intel_dp, DP);
3357 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3358}
3359
3360static bool
3361intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3362 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3363{
3364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3365 struct drm_device *dev = intel_dig_port->base.base.dev;
3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367 int ret;
3368
3369 intel_get_adjust_train(intel_dp, link_status);
3370 intel_dp_set_signal_levels(intel_dp, DP);
3371
3372 I915_WRITE(intel_dp->output_reg, *DP);
3373 POSTING_READ(intel_dp->output_reg);
3374
9d1a1031
JN		 3375 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3376 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3377
3378 return ret == intel_dp->lane_count;
3379}
3380
3ab9c637
ID		 3381static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3382{
3383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3384 struct drm_device *dev = intel_dig_port->base.base.dev;
3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386 enum port port = intel_dig_port->port;
3387 uint32_t val;
3388
3389 if (!HAS_DDI(dev))
3390 return;
3391
3392 val = I915_READ(DP_TP_CTL(port));
3393 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3394 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3395 I915_WRITE(DP_TP_CTL(port), val);
3396
3397 /*
3398 * On PORT_A we can have only eDP in SST mode. There the only reason
3399 * we need to set idle transmission mode is to work around a HW issue
3400 * where we enable the pipe while not in idle link-training mode.
3401 * In this case there is requirement to wait for a minimum number of
3402 * idle patterns to be sent.
3403 */
3404 if (port == PORT_A)
3405 return;
3406
3407 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3408 1))
3409 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3410}
3411
33a34e4e 3412/* Enable corresponding port and start training pattern 1 */
c19b0669 3413void
33a34e4e 3414intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3415{
da63a9f2 3416 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3417 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3418 int i;
3419 uint8_t voltage;
cdb0e95b 3420 int voltage_tries, loop_tries;
ea5b213a 3421 uint32_t DP = intel_dp->DP;
6aba5b6c 3422 uint8_t link_config[2];
a4fc5ed6 3423
affa9354 3424 if (HAS_DDI(dev))
c19b0669
PZ		 3425 intel_ddi_prepare_link_retrain(encoder);
3426
3cf2efb1 3427 /* Write the link configuration data */
6aba5b6c
JN		 3428 link_config[0] = intel_dp->link_bw;
3429 link_config[1] = intel_dp->lane_count;
3430 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3431 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3432 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3433
3434 link_config[0] = 0;
3435 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3436 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3437
3438 DP |= DP_PORT_EN;
1a2eb460 3439
70aff66c
JN		 3440 /* clock recovery */
3441 if (!intel_dp_reset_link_train(intel_dp, &DP,
3442 DP_TRAINING_PATTERN_1 |
3443 DP_LINK_SCRAMBLING_DISABLE)) {
3444 DRM_ERROR("failed to enable link training\n");
3445 return;
3446 }
3447
a4fc5ed6 3448 voltage = 0xff;
cdb0e95b
KP		 3449 voltage_tries = 0;
3450 loop_tries = 0;
a4fc5ed6 3451 for (;;) {
70aff66c 3452 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3453
a7c9655f 3454 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3455 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3456 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3457 break;
93f62dad 3458 }
a4fc5ed6 3459
01916270 3460 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3461 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3462 break;
3463 }
3464
3465 /* Check to see if we've tried the max voltage */
3466 for (i = 0; i < intel_dp->lane_count; i++)
3467 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3468 break;
3b4f819d 3469 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3470 ++loop_tries;
3471 if (loop_tries == 5) {
3def84b3 3472 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3473 break;
3474 }
70aff66c
JN		 3475 intel_dp_reset_link_train(intel_dp, &DP,
3476 DP_TRAINING_PATTERN_1 |
3477 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3478 voltage_tries = 0;
3479 continue;
3480 }
a4fc5ed6 3481
3cf2efb1 3482 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3483 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3484 ++voltage_tries;
b06fbda3 3485 if (voltage_tries == 5) {
3def84b3 3486 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3487 break;
3488 }
3489 } else
3490 voltage_tries = 0;
3491 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3492
70aff66c
JN		 3493 /* Update training set as requested by target */
3494 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3495 DRM_ERROR("failed to update link training\n");
3496 break;
3497 }
a4fc5ed6
KP		 3498 }
3499
33a34e4e
JB		 3500 intel_dp->DP = DP;
3501}
3502
c19b0669 3503void
33a34e4e
JB		 3504intel_dp_complete_link_train(struct intel_dp *intel_dp)
3505{
33a34e4e 3506 bool channel_eq = false;
37f80975 3507 int tries, cr_tries;
33a34e4e 3508 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3509 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3510
3511 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3512 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3513 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3514
a4fc5ed6 3515 /* channel equalization */
70aff66c 3516 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3517 training_pattern |
70aff66c
JN		 3518 DP_LINK_SCRAMBLING_DISABLE)) {
3519 DRM_ERROR("failed to start channel equalization\n");
3520 return;
3521 }
3522
a4fc5ed6 3523 tries = 0;
37f80975 3524 cr_tries = 0;
a4fc5ed6
KP		 3525 channel_eq = false;
3526 for (;;) {
70aff66c 3527 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3528
37f80975
JB		 3529 if (cr_tries > 5) {
3530 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3531 break;
3532 }
3533
a7c9655f 3534 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3535 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3536 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3537 break;
70aff66c 3538 }
a4fc5ed6 3539
37f80975 3540 /* Make sure clock is still ok */
01916270 3541 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3542 intel_dp_start_link_train(intel_dp);
70aff66c 3543 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3544 training_pattern |
70aff66c 3545 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3546 cr_tries++;
3547 continue;
3548 }
3549
1ffdff13 3550 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3551 channel_eq = true;
3552 break;
3553 }
a4fc5ed6 3554
37f80975
JB		 3555 /* Try 5 times, then try clock recovery if that fails */
3556 if (tries > 5) {
3557 intel_dp_link_down(intel_dp);
3558 intel_dp_start_link_train(intel_dp);
70aff66c 3559 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3560 training_pattern |
70aff66c 3561 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3562 tries = 0;
3563 cr_tries++;
3564 continue;
3565 }
a4fc5ed6 3566
70aff66c
JN		 3567 /* Update training set as requested by target */
3568 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3569 DRM_ERROR("failed to update link training\n");
3570 break;
3571 }
3cf2efb1 3572 ++tries;
869184a6 3573 }
3cf2efb1 3574
3ab9c637
ID		 3575 intel_dp_set_idle_link_train(intel_dp);
3576
3577 intel_dp->DP = DP;
3578
d6c0d722 3579 if (channel_eq)
07f42258 3580 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3581
3ab9c637
ID		 3582}
3583
3584void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3585{
70aff66c 3586 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3587 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3588}
3589
3590static void
ea5b213a 3591intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3592{
da63a9f2 3593 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3594 enum port port = intel_dig_port->port;
da63a9f2 3595 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3596 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3597 struct intel_crtc *intel_crtc =
3598 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3599 uint32_t DP = intel_dp->DP;
a4fc5ed6 3600
bc76e320 3601 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3602 return;
3603
0c33d8d7 3604 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3605 return;
3606
28c97730 3607 DRM_DEBUG_KMS("\n");
32f9d658 3608
bc7d38a4 3609 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3610 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3611 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3612 } else {
aad3d14d
VS		 3613 if (IS_CHERRYVIEW(dev))
3614 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3615 else
3616 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3617 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3618 }
fe255d00 3619 POSTING_READ(intel_dp->output_reg);
5eb08b69 3620
493a7081 3621 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3622 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3623 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3624
5bddd17f
EA		 3625 /* Hardware workaround: leaving our transcoder select
3626 * set to transcoder B while it's off will prevent the
3627 * corresponding HDMI output on transcoder A.
3628 *
3629 * Combine this with another hardware workaround:
3630 * transcoder select bit can only be cleared while the
3631 * port is enabled.
3632 */
3633 DP &= ~DP_PIPEB_SELECT;
3634 I915_WRITE(intel_dp->output_reg, DP);
3635
3636 /* Changes to enable or select take place the vblank
3637 * after being written.
3638 */
ff50afe9
DV		 3639 if (WARN_ON(crtc == NULL)) {
3640 /* We should never try to disable a port without a crtc
3641 * attached. For paranoia keep the code around for a
3642 * bit. */
31acbcc4
CW		 3643 POSTING_READ(intel_dp->output_reg);
3644 msleep(50);
3645 } else
ab527efc 3646 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3647 }
3648
832afda6 3649 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3650 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3651 POSTING_READ(intel_dp->output_reg);
f01eca2e 3652 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3653}
3654
26d61aad
KP		 3655static bool
3656intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3657{
a031d709
RV		 3658 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3659 struct drm_device *dev = dig_port->base.base.dev;
3660 struct drm_i915_private *dev_priv = dev->dev_private;
3661
9d1a1031
JN		 3662 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3663 sizeof(intel_dp->dpcd)) < 0)
edb39244 3664 return false; /* aux transfer failed */
92fd8fd1 3665
a8e98153 3666 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3667
edb39244
AJ		 3668 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3669 return false; /* DPCD not present */
3670
2293bb5c
SK		 3671 /* Check if the panel supports PSR */
3672 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3673 if (is_edp(intel_dp)) {
9d1a1031
JN		 3674 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3675 intel_dp->psr_dpcd,
3676 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3677 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3678 dev_priv->psr.sink_support = true;
50003939 3679 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3680 }
50003939
JN		 3681 }
3682
06ea66b6
TP		 3683 /* Training Pattern 3 support */
3684 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3685 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3686 intel_dp->use_tps3 = true;
3687 DRM_DEBUG_KMS("Displayport TPS3 supported");
3688 } else
3689 intel_dp->use_tps3 = false;
3690
edb39244
AJ		 3691 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3692 DP_DWN_STRM_PORT_PRESENT))
3693 return true; /* native DP sink */
3694
3695 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3696 return true; /* no per-port downstream info */
3697
9d1a1031
JN		 3698 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3699 intel_dp->downstream_ports,
3700 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3701 return false; /* downstream port status fetch failed */
3702
3703 return true;
92fd8fd1
KP		 3704}
3705
0d198328
AJ		 3706static void
3707intel_dp_probe_oui(struct intel_dp *intel_dp)
3708{
3709 u8 buf[3];
3710
3711 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3712 return;
3713
24f3e092 3714 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3715
9d1a1031 3716 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3717 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3718 buf[0], buf[1], buf[2]);
3719
9d1a1031 3720 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3721 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3722 buf[0], buf[1], buf[2]);
351cfc34 3723
1e0560e0 3724 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3725}
3726
0e32b39c
DA		 3727static bool
3728intel_dp_probe_mst(struct intel_dp *intel_dp)
3729{
3730 u8 buf[1];
3731
3732 if (!intel_dp->can_mst)
3733 return false;
3734
3735 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3736 return false;
3737
d337a341 3738 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3739 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3740 if (buf[0] & DP_MST_CAP) {
3741 DRM_DEBUG_KMS("Sink is MST capable\n");
3742 intel_dp->is_mst = true;
3743 } else {
3744 DRM_DEBUG_KMS("Sink is not MST capable\n");
3745 intel_dp->is_mst = false;
3746 }
3747 }
1e0560e0 3748 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3749
3750 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3751 return intel_dp->is_mst;
3752}
3753
d2e216d0
RV		 3754int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3755{
3756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3757 struct drm_device *dev = intel_dig_port->base.base.dev;
3758 struct intel_crtc *intel_crtc =
3759 to_intel_crtc(intel_dig_port->base.base.crtc);
3760 u8 buf[1];
3761
9d1a1031 3762 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3763 return -EAGAIN;
3764
3765 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3766 return -ENOTTY;
3767
9d1a1031
JN		 3768 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3769 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3770 return -EAGAIN;
3771
3772 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3773 intel_wait_for_vblank(dev, intel_crtc->pipe);
3774 intel_wait_for_vblank(dev, intel_crtc->pipe);
3775
9d1a1031 3776 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3777 return -EAGAIN;
3778
9d1a1031 3779 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3780 return 0;
3781}
3782
a60f0e38
JB		 3783static bool
3784intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3785{
9d1a1031
JN		 3786 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3787 DP_DEVICE_SERVICE_IRQ_VECTOR,
3788 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3789}
3790
0e32b39c
DA		 3791static bool
3792intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3793{
3794 int ret;
3795
3796 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3797 DP_SINK_COUNT_ESI,
3798 sink_irq_vector, 14);
3799 if (ret != 14)
3800 return false;
3801
3802 return true;
3803}
3804
a60f0e38
JB		 3805static void
3806intel_dp_handle_test_request(struct intel_dp *intel_dp)
3807{
3808 /* NAK by default */
9d1a1031 3809 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3810}
3811
0e32b39c
DA		 3812static int
3813intel_dp_check_mst_status(struct intel_dp *intel_dp)
3814{
3815 bool bret;
3816
3817 if (intel_dp->is_mst) {
3818 u8 esi[16] = { 0 };
3819 int ret = 0;
3820 int retry;
3821 bool handled;
3822 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3823go_again:
3824 if (bret == true) {
3825
3826 /* check link status - esi[10] = 0x200c */
3827 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3828 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3829 intel_dp_start_link_train(intel_dp);
3830 intel_dp_complete_link_train(intel_dp);
3831 intel_dp_stop_link_train(intel_dp);
3832 }
3833
3834 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3835 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3836
3837 if (handled) {
3838 for (retry = 0; retry < 3; retry++) {
3839 int wret;
3840 wret = drm_dp_dpcd_write(&intel_dp->aux,
3841 DP_SINK_COUNT_ESI+1,
3842 &esi[1], 3);
3843 if (wret == 3) {
3844 break;
3845 }
3846 }
3847
3848 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3849 if (bret == true) {
3850 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3851 goto go_again;
3852 }
3853 } else
3854 ret = 0;
3855
3856 return ret;
3857 } else {
3858 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3859 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3860 intel_dp->is_mst = false;
3861 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3862 /* send a hotplug event */
3863 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3864 }
3865 }
3866 return -EINVAL;
3867}
3868
a4fc5ed6
KP		 3869/*
3870 * According to DP spec
3871 * 5.1.2:
3872 * 1. Read DPCD
3873 * 2. Configure link according to Receiver Capabilities
3874 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3875 * 4. Check link status on receipt of hot-plug interrupt
3876 */
00c09d70 3877void
ea5b213a 3878intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3879{
5b215bcf 3880 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3881 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3882 u8 sink_irq_vector;
93f62dad 3883 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3884
5b215bcf
DA		 3885 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3886
da63a9f2 3887 if (!intel_encoder->connectors_active)
d2b996ac 3888 return;
59cd09e1 3889
da63a9f2 3890 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3891 return;
3892
1a125d8a
ID		 3893 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3894 return;
3895
92fd8fd1 3896 /* Try to read receiver status if the link appears to be up */
93f62dad 3897 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3898 return;
3899 }
3900
92fd8fd1 3901 /* Now read the DPCD to see if it's actually running */
26d61aad 3902 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3903 return;
3904 }
3905
a60f0e38
JB		 3906 /* Try to read the source of the interrupt */
3907 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3908 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3909 /* Clear interrupt source */
9d1a1031
JN		 3910 drm_dp_dpcd_writeb(&intel_dp->aux,
3911 DP_DEVICE_SERVICE_IRQ_VECTOR,
3912 sink_irq_vector);
a60f0e38
JB		 3913
3914 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3915 intel_dp_handle_test_request(intel_dp);
3916 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3917 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3918 }
3919
1ffdff13 3920 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3921 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3922 intel_encoder->base.name);
33a34e4e
JB		 3923 intel_dp_start_link_train(intel_dp);
3924 intel_dp_complete_link_train(intel_dp);
3ab9c637 3925 intel_dp_stop_link_train(intel_dp);
33a34e4e 3926 }
a4fc5ed6 3927}
a4fc5ed6 3928
caf9ab24 3929/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3930static enum drm_connector_status
26d61aad 3931intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3932{
caf9ab24 3933 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3934 uint8_t type;
3935
3936 if (!intel_dp_get_dpcd(intel_dp))
3937 return connector_status_disconnected;
3938
3939 /* if there's no downstream port, we're done */
3940 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3941 return connector_status_connected;
caf9ab24
AJ		 3942
3943 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3944 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3945 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3946 uint8_t reg;
9d1a1031
JN		 3947
3948 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3949 &reg, 1) < 0)
caf9ab24 3950 return connector_status_unknown;
9d1a1031 3951
23235177
AJ		 3952 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3953 : connector_status_disconnected;
caf9ab24
AJ		 3954 }
3955
3956 /* If no HPD, poke DDC gently */
0b99836f 3957 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3958 return connector_status_connected;
caf9ab24
AJ		 3959
3960 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3961 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3962 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3963 if (type == DP_DS_PORT_TYPE_VGA ||
3964 type == DP_DS_PORT_TYPE_NON_EDID)
3965 return connector_status_unknown;
3966 } else {
3967 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3968 DP_DWN_STRM_PORT_TYPE_MASK;
3969 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3970 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3971 return connector_status_unknown;
3972 }
caf9ab24
AJ		 3973
3974 /* Anything else is out of spec, warn and ignore */
3975 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3976 return connector_status_disconnected;
71ba9000
AJ		 3977}
3978
d410b56d
CW		 3979static enum drm_connector_status
3980edp_detect(struct intel_dp *intel_dp)
3981{
3982 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3983 enum drm_connector_status status;
3984
3985 status = intel_panel_detect(dev);
3986 if (status == connector_status_unknown)
3987 status = connector_status_connected;
3988
3989 return status;
3990}
3991
5eb08b69 3992static enum drm_connector_status
a9756bb5 3993ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3994{
30add22d 3995 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3996 struct drm_i915_private *dev_priv = dev->dev_private;
3997 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3998
1b469639
DL		 3999 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4000 return connector_status_disconnected;
4001
26d61aad 4002 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4003}
4004
a4fc5ed6 4005static enum drm_connector_status
a9756bb5 4006g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 4007{
30add22d 4008 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 4009 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 4010 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 4011 uint32_t bit;
5eb08b69 4012
232a6ee9
TP		 4013 if (IS_VALLEYVIEW(dev)) {
4014 switch (intel_dig_port->port) {
4015 case PORT_B:
4016 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4017 break;
4018 case PORT_C:
4019 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4020 break;
4021 case PORT_D:
4022 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4023 break;
4024 default:
4025 return connector_status_unknown;
4026 }
4027 } else {
4028 switch (intel_dig_port->port) {
4029 case PORT_B:
4030 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4031 break;
4032 case PORT_C:
4033 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4034 break;
4035 case PORT_D:
4036 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4037 break;
4038 default:
4039 return connector_status_unknown;
4040 }
a4fc5ed6
KP		 4041 }
4042
10f76a38 4043 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 4044 return connector_status_disconnected;
4045
26d61aad 4046 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4047}
4048
8c241fef 4049static struct edid *
beb60608 4050intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4051{
beb60608 4052 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4053
9cd300e0
JN		 4054 /* use cached edid if we have one */
4055 if (intel_connector->edid) {
9cd300e0
JN		 4056 /* invalid edid */
4057 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4058 return NULL;
4059
55e9edeb 4060 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4061 } else
4062 return drm_get_edid(&intel_connector->base,
4063 &intel_dp->aux.ddc);
4064}
8c241fef 4065
beb60608
CW		 4066static void
4067intel_dp_set_edid(struct intel_dp *intel_dp)
4068{
4069 struct intel_connector *intel_connector = intel_dp->attached_connector;
4070 struct edid *edid;
4071
4072 edid = intel_dp_get_edid(intel_dp);
4073 intel_connector->detect_edid = edid;
4074
4075 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4076 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4077 else
4078 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4079}
4080
beb60608
CW		 4081static void
4082intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4083{
beb60608 4084 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4085
beb60608
CW		 4086 kfree(intel_connector->detect_edid);
4087 intel_connector->detect_edid = NULL;
9cd300e0 4088
beb60608
CW		 4089 intel_dp->has_audio = false;
4090}
d6f24d0f 4091
beb60608
CW		 4092static enum intel_display_power_domain
4093intel_dp_power_get(struct intel_dp *dp)
4094{
4095 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4096 enum intel_display_power_domain power_domain;
4097
4098 power_domain = intel_display_port_power_domain(encoder);
4099 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4100
4101 return power_domain;
4102}
4103
4104static void
4105intel_dp_power_put(struct intel_dp *dp,
4106 enum intel_display_power_domain power_domain)
4107{
4108 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4109 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4110}
4111
a9756bb5
ZW		 4112static enum drm_connector_status
4113intel_dp_detect(struct drm_connector *connector, bool force)
4114{
4115 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4117 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4118 struct drm_device *dev = connector->dev;
a9756bb5 4119 enum drm_connector_status status;
671dedd2 4120 enum intel_display_power_domain power_domain;
0e32b39c 4121 bool ret;
a9756bb5 4122
164c8598 4123 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4124 connector->base.id, connector->name);
beb60608 4125 intel_dp_unset_edid(intel_dp);
164c8598 4126
0e32b39c
DA		 4127 if (intel_dp->is_mst) {
4128 /* MST devices are disconnected from a monitor POV */
4129 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4130 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4131 return connector_status_disconnected;
0e32b39c
DA		 4132 }
4133
beb60608 4134 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4135
d410b56d
CW		 4136 /* Can't disconnect eDP, but you can close the lid... */
4137 if (is_edp(intel_dp))
4138 status = edp_detect(intel_dp);
4139 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4140 status = ironlake_dp_detect(intel_dp);
4141 else
4142 status = g4x_dp_detect(intel_dp);
4143 if (status != connector_status_connected)
c8c8fb33 4144 goto out;
a9756bb5 4145
0d198328
AJ		 4146 intel_dp_probe_oui(intel_dp);
4147
0e32b39c
DA		 4148 ret = intel_dp_probe_mst(intel_dp);
4149 if (ret) {
4150 /* if we are in MST mode then this connector
4151 won't appear connected or have anything with EDID on it */
4152 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4153 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4154 status = connector_status_disconnected;
4155 goto out;
4156 }
4157
beb60608 4158 intel_dp_set_edid(intel_dp);
a9756bb5 4159
d63885da
PZ		 4160 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4161 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4162 status = connector_status_connected;
4163
4164out:
beb60608 4165 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4166 return status;
a4fc5ed6
KP		 4167}
4168
beb60608
CW		 4169static void
4170intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4171{
df0e9248 4172 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4173 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4174 enum intel_display_power_domain power_domain;
a4fc5ed6 4175
beb60608
CW		 4176 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4177 connector->base.id, connector->name);
4178 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4179
beb60608
CW		 4180 if (connector->status != connector_status_connected)
4181 return;
671dedd2 4182
beb60608
CW		 4183 power_domain = intel_dp_power_get(intel_dp);
4184
4185 intel_dp_set_edid(intel_dp);
4186
4187 intel_dp_power_put(intel_dp, power_domain);
4188
4189 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4190 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4191}
4192
4193static int intel_dp_get_modes(struct drm_connector *connector)
4194{
4195 struct intel_connector *intel_connector = to_intel_connector(connector);
4196 struct edid *edid;
4197
4198 edid = intel_connector->detect_edid;
4199 if (edid) {
4200 int ret = intel_connector_update_modes(connector, edid);
4201 if (ret)
4202 return ret;
4203 }
32f9d658 4204
f8779fda 4205 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4206 if (is_edp(intel_attached_dp(connector)) &&
4207 intel_connector->panel.fixed_mode) {
f8779fda 4208 struct drm_display_mode *mode;
beb60608
CW		 4209
4210 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4211 intel_connector->panel.fixed_mode);
f8779fda 4212 if (mode) {
32f9d658
ZW		 4213 drm_mode_probed_add(connector, mode);
4214 return 1;
4215 }
4216 }
beb60608 4217
32f9d658 4218 return 0;
a4fc5ed6
KP		 4219}
4220
1aad7ac0
CW		 4221static bool
4222intel_dp_detect_audio(struct drm_connector *connector)
4223{
1aad7ac0 4224 bool has_audio = false;
beb60608 4225 struct edid *edid;
1aad7ac0 4226
beb60608
CW		 4227 edid = to_intel_connector(connector)->detect_edid;
4228 if (edid)
1aad7ac0 4229 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4230
1aad7ac0
CW		 4231 return has_audio;
4232}
4233
f684960e
CW		 4234static int
4235intel_dp_set_property(struct drm_connector *connector,
4236 struct drm_property *property,
4237 uint64_t val)
4238{
e953fd7b 4239 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4240 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4241 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4242 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4243 int ret;
4244
662595df 4245 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4246 if (ret)
4247 return ret;
4248
3f43c48d 4249 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4250 int i = val;
4251 bool has_audio;
4252
4253 if (i == intel_dp->force_audio)
f684960e
CW		 4254 return 0;
4255
1aad7ac0 4256 intel_dp->force_audio = i;
f684960e 4257
c3e5f67b 4258 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4259 has_audio = intel_dp_detect_audio(connector);
4260 else
c3e5f67b 4261 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4262
4263 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4264 return 0;
4265
1aad7ac0 4266 intel_dp->has_audio = has_audio;
f684960e
CW		 4267 goto done;
4268 }
4269
e953fd7b 4270 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4271 bool old_auto = intel_dp->color_range_auto;
4272 uint32_t old_range = intel_dp->color_range;
4273
55bc60db
VS		 4274 switch (val) {
4275 case INTEL_BROADCAST_RGB_AUTO:
4276 intel_dp->color_range_auto = true;
4277 break;
4278 case INTEL_BROADCAST_RGB_FULL:
4279 intel_dp->color_range_auto = false;
4280 intel_dp->color_range = 0;
4281 break;
4282 case INTEL_BROADCAST_RGB_LIMITED:
4283 intel_dp->color_range_auto = false;
4284 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4285 break;
4286 default:
4287 return -EINVAL;
4288 }
ae4edb80
DV		 4289
4290 if (old_auto == intel_dp->color_range_auto &&
4291 old_range == intel_dp->color_range)
4292 return 0;
4293
e953fd7b
CW		 4294 goto done;
4295 }
4296
53b41837
YN		 4297 if (is_edp(intel_dp) &&
4298 property == connector->dev->mode_config.scaling_mode_property) {
4299 if (val == DRM_MODE_SCALE_NONE) {
4300 DRM_DEBUG_KMS("no scaling not supported\n");
4301 return -EINVAL;
4302 }
4303
4304 if (intel_connector->panel.fitting_mode == val) {
4305 /* the eDP scaling property is not changed */
4306 return 0;
4307 }
4308 intel_connector->panel.fitting_mode = val;
4309
4310 goto done;
4311 }
4312
f684960e
CW		 4313 return -EINVAL;
4314
4315done:
c0c36b94
CW		 4316 if (intel_encoder->base.crtc)
4317 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4318
4319 return 0;
4320}
4321
a4fc5ed6 4322static void
73845adf 4323intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4324{
1d508706 4325 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4326
beb60608
CW		 4327 intel_dp_unset_edid(intel_attached_dp(connector));
4328
9cd300e0
JN		 4329 if (!IS_ERR_OR_NULL(intel_connector->edid))
4330 kfree(intel_connector->edid);
4331
acd8db10
PZ		 4332 /* Can't call is_edp() since the encoder may have been destroyed
4333 * already. */
4334 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4335 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4336
a4fc5ed6 4337 drm_connector_cleanup(connector);
55f78c43 4338 kfree(connector);
a4fc5ed6
KP		 4339}
4340
00c09d70 4341void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4342{
da63a9f2
PZ		 4343 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4344 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4345
4f71d0cb 4346 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4347 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4348 drm_encoder_cleanup(encoder);
bd943159
KP		 4349 if (is_edp(intel_dp)) {
4350 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4351 pps_lock(intel_dp);
4be73780 4352 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4353 pps_unlock(intel_dp);
4354
01527b31
CT		 4355 if (intel_dp->edp_notifier.notifier_call) {
4356 unregister_reboot_notifier(&intel_dp->edp_notifier);
4357 intel_dp->edp_notifier.notifier_call = NULL;
4358 }
bd943159 4359 }
da63a9f2 4360 kfree(intel_dig_port);
24d05927
DV		 4361}
4362
07f9cd0b
ID		 4363static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4364{
4365 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4366
4367 if (!is_edp(intel_dp))
4368 return;
4369
773538e8 4370 pps_lock(intel_dp);
07f9cd0b 4371 edp_panel_vdd_off_sync(intel_dp);
773538e8 4372 pps_unlock(intel_dp);
07f9cd0b
ID		 4373}
4374
6d93c0c4
ID		 4375static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4376{
4377 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4378}
4379
a4fc5ed6 4380static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4381 .dpms = intel_connector_dpms,
a4fc5ed6 4382 .detect = intel_dp_detect,
beb60608 4383 .force = intel_dp_force,
a4fc5ed6 4384 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4385 .set_property = intel_dp_set_property,
73845adf 4386 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4387};
4388
4389static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4390 .get_modes = intel_dp_get_modes,
4391 .mode_valid = intel_dp_mode_valid,
df0e9248 4392 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4393};
4394
a4fc5ed6 4395static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4396 .reset = intel_dp_encoder_reset,
24d05927 4397 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4398};
4399
0e32b39c 4400void
21d40d37 4401intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4402{
0e32b39c 4403 return;
c8110e52 4404}
6207937d 4405
13cf5504
DA		 4406bool
4407intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4408{
4409 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4410 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4411 struct drm_device *dev = intel_dig_port->base.base.dev;
4412 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4413 enum intel_display_power_domain power_domain;
4414 bool ret = true;
4415
0e32b39c
DA		 4416 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4417 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4418
26fbb774
VS		 4419 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4420 port_name(intel_dig_port->port),
0e32b39c 4421 long_hpd ? "long" : "short");
13cf5504 4422
1c767b33
ID		 4423 power_domain = intel_display_port_power_domain(intel_encoder);
4424 intel_display_power_get(dev_priv, power_domain);
4425
0e32b39c
DA		 4426 if (long_hpd) {
4427 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4428 goto mst_fail;
4429
4430 if (!intel_dp_get_dpcd(intel_dp)) {
4431 goto mst_fail;
4432 }
4433
4434 intel_dp_probe_oui(intel_dp);
4435
4436 if (!intel_dp_probe_mst(intel_dp))
4437 goto mst_fail;
4438
4439 } else {
4440 if (intel_dp->is_mst) {
1c767b33 4441 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4442 goto mst_fail;
4443 }
4444
4445 if (!intel_dp->is_mst) {
4446 /*
4447 * we'll check the link status via the normal hot plug path later -
4448 * but for short hpds we should check it now
4449 */
5b215bcf 4450 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4451 intel_dp_check_link_status(intel_dp);
5b215bcf 4452 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4453 }
4454 }
1c767b33
ID		 4455 ret = false;
4456 goto put_power;
0e32b39c
DA		 4457mst_fail:
4458 /* if we were in MST mode, and device is not there get out of MST mode */
4459 if (intel_dp->is_mst) {
4460 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4461 intel_dp->is_mst = false;
4462 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4463 }
1c767b33
ID		 4464put_power:
4465 intel_display_power_put(dev_priv, power_domain);
4466
4467 return ret;
13cf5504
DA		 4468}
4469
e3421a18
ZW		 4470/* Return which DP Port should be selected for Transcoder DP control */
4471int
0206e353 4472intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4473{
4474 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4475 struct intel_encoder *intel_encoder;
4476 struct intel_dp *intel_dp;
e3421a18 4477
fa90ecef
PZ		 4478 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4479 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4480
fa90ecef
PZ		 4481 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4482 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4483 return intel_dp->output_reg;
e3421a18 4484 }
ea5b213a 4485
e3421a18
ZW		 4486 return -1;
4487}
4488
36e83a18 4489/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4490bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4491{
4492 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4493 union child_device_config *p_child;
36e83a18 4494 int i;
5d8a7752
VS		 4495 static const short port_mapping[] = {
4496 [PORT_B] = PORT_IDPB,
4497 [PORT_C] = PORT_IDPC,
4498 [PORT_D] = PORT_IDPD,
4499 };
36e83a18 4500
3b32a35b
VS		 4501 if (port == PORT_A)
4502 return true;
4503
41aa3448 4504 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4505 return false;
4506
41aa3448
RV		 4507 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4508 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4509
5d8a7752 4510 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4511 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4512 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4513 return true;
4514 }
4515 return false;
4516}
4517
0e32b39c 4518void
f684960e
CW		 4519intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4520{
53b41837
YN		 4521 struct intel_connector *intel_connector = to_intel_connector(connector);
4522
3f43c48d 4523 intel_attach_force_audio_property(connector);
e953fd7b 4524 intel_attach_broadcast_rgb_property(connector);
55bc60db 4525 intel_dp->color_range_auto = true;
53b41837
YN		 4526
4527 if (is_edp(intel_dp)) {
4528 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4529 drm_object_attach_property(
4530 &connector->base,
53b41837 4531 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4532 DRM_MODE_SCALE_ASPECT);
4533 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4534 }
f684960e
CW		 4535}
4536
dada1a9f
ID		 4537static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4538{
4539 intel_dp->last_power_cycle = jiffies;
4540 intel_dp->last_power_on = jiffies;
4541 intel_dp->last_backlight_off = jiffies;
4542}
4543
67a54566
DV		 4544static void
4545intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4546 struct intel_dp *intel_dp,
4547 struct edp_power_seq *out)
67a54566
DV		 4548{
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550 struct edp_power_seq cur, vbt, spec, final;
4551 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4552 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4553
e39b999a
VS		 4554 lockdep_assert_held(&dev_priv->pps_mutex);
4555
453c5420 4556 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4557 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4558 pp_on_reg = PCH_PP_ON_DELAYS;
4559 pp_off_reg = PCH_PP_OFF_DELAYS;
4560 pp_div_reg = PCH_PP_DIVISOR;
4561 } else {
bf13e81b
JN		 4562 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4563
4564 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4565 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4566 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4567 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4568 }
67a54566
DV		 4569
4570 /* Workaround: Need to write PP_CONTROL with the unlock key as
4571 * the very first thing. */
453c5420 4572 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4573 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4574
453c5420
JB		 4575 pp_on = I915_READ(pp_on_reg);
4576 pp_off = I915_READ(pp_off_reg);
4577 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4578
4579 /* Pull timing values out of registers */
4580 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4581 PANEL_POWER_UP_DELAY_SHIFT;
4582
4583 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4584 PANEL_LIGHT_ON_DELAY_SHIFT;
4585
4586 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4587 PANEL_LIGHT_OFF_DELAY_SHIFT;
4588
4589 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4590 PANEL_POWER_DOWN_DELAY_SHIFT;
4591
4592 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4593 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4594
4595 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4596 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4597
41aa3448 4598 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4599
4600 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4601 * our hw here, which are all in 100usec. */
4602 spec.t1_t3 = 210 * 10;
4603 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4604 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4605 spec.t10 = 500 * 10;
4606 /* This one is special and actually in units of 100ms, but zero
4607 * based in the hw (so we need to add 100 ms). But the sw vbt
4608 * table multiplies it with 1000 to make it in units of 100usec,
4609 * too. */
4610 spec.t11_t12 = (510 + 100) * 10;
4611
4612 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4613 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4614
4615 /* Use the max of the register settings and vbt. If both are
4616 * unset, fall back to the spec limits. */
4617#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4618 spec.field : \
4619 max(cur.field, vbt.field))
4620 assign_final(t1_t3);
4621 assign_final(t8);
4622 assign_final(t9);
4623 assign_final(t10);
4624 assign_final(t11_t12);
4625#undef assign_final
4626
4627#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4628 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4629 intel_dp->backlight_on_delay = get_delay(t8);
4630 intel_dp->backlight_off_delay = get_delay(t9);
4631 intel_dp->panel_power_down_delay = get_delay(t10);
4632 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4633#undef get_delay
4634
f30d26e4
JN		 4635 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4636 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4637 intel_dp->panel_power_cycle_delay);
4638
4639 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4640 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4641
4642 if (out)
4643 *out = final;
4644}
4645
4646static void
4647intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4648 struct intel_dp *intel_dp,
4649 struct edp_power_seq *seq)
4650{
4651 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4652 u32 pp_on, pp_off, pp_div, port_sel = 0;
4653 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4654 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4655 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4656
e39b999a
VS		 4657 lockdep_assert_held(&dev_priv->pps_mutex);
4658
453c5420
JB		 4659 if (HAS_PCH_SPLIT(dev)) {
4660 pp_on_reg = PCH_PP_ON_DELAYS;
4661 pp_off_reg = PCH_PP_OFF_DELAYS;
4662 pp_div_reg = PCH_PP_DIVISOR;
4663 } else {
bf13e81b
JN		 4664 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4665
4666 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4667 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4668 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4669 }
4670
b2f19d1a
PZ		 4671 /*
4672 * And finally store the new values in the power sequencer. The
4673 * backlight delays are set to 1 because we do manual waits on them. For
4674 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4675 * we'll end up waiting for the backlight off delay twice: once when we
4676 * do the manual sleep, and once when we disable the panel and wait for
4677 * the PP_STATUS bit to become zero.
4678 */
f30d26e4 4679 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4680 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4681 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4682 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4683 /* Compute the divisor for the pp clock, simply match the Bspec
4684 * formula. */
453c5420 4685 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4686 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4687 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4688
4689 /* Haswell doesn't have any port selection bits for the panel
4690 * power sequencer any more. */
bc7d38a4 4691 if (IS_VALLEYVIEW(dev)) {
ad933b56 4692 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4693 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4694 if (port == PORT_A)
a24c144c 4695 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4696 else
a24c144c 4697 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4698 }
4699
453c5420
JB		 4700 pp_on |= port_sel;
4701
4702 I915_WRITE(pp_on_reg, pp_on);
4703 I915_WRITE(pp_off_reg, pp_off);
4704 I915_WRITE(pp_div_reg, pp_div);
67a54566 4705
67a54566 4706 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4707 I915_READ(pp_on_reg),
4708 I915_READ(pp_off_reg),
4709 I915_READ(pp_div_reg));
f684960e
CW		 4710}
4711
439d7ac0
PB		 4712void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4713{
4714 struct drm_i915_private *dev_priv = dev->dev_private;
4715 struct intel_encoder *encoder;
4716 struct intel_dp *intel_dp = NULL;
4717 struct intel_crtc_config *config = NULL;
4718 struct intel_crtc *intel_crtc = NULL;
4719 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4720 u32 reg, val;
4721 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4722
4723 if (refresh_rate <= 0) {
4724 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4725 return;
4726 }
4727
4728 if (intel_connector == NULL) {
4729 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4730 return;
4731 }
4732
1fcc9d1c
DV		 4733 /*
4734 * FIXME: This needs proper synchronization with psr state. But really
4735 * hard to tell without seeing the user of this function of this code.
4736 * Check locking and ordering once that lands.
4737 */
439d7ac0
PB		 4738 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4739 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4740 return;
4741 }
4742
4743 encoder = intel_attached_encoder(&intel_connector->base);
4744 intel_dp = enc_to_intel_dp(&encoder->base);
4745 intel_crtc = encoder->new_crtc;
4746
4747 if (!intel_crtc) {
4748 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4749 return;
4750 }
4751
4752 config = &intel_crtc->config;
4753
4754 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4755 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4756 return;
4757 }
4758
4759 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4760 index = DRRS_LOW_RR;
4761
4762 if (index == intel_dp->drrs_state.refresh_rate_type) {
4763 DRM_DEBUG_KMS(
4764 "DRRS requested for previously set RR...ignoring\n");
4765 return;
4766 }
4767
4768 if (!intel_crtc->active) {
4769 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4770 return;
4771 }
4772
4773 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4774 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4775 val = I915_READ(reg);
4776 if (index > DRRS_HIGH_RR) {
4777 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4778 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4779 } else {
4780 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4781 }
4782 I915_WRITE(reg, val);
4783 }
4784
4785 /*
4786 * mutex taken to ensure that there is no race between differnt
4787 * drrs calls trying to update refresh rate. This scenario may occur
4788 * in future when idleness detection based DRRS in kernel and
4789 * possible calls from user space to set differnt RR are made.
4790 */
4791
4792 mutex_lock(&intel_dp->drrs_state.mutex);
4793
4794 intel_dp->drrs_state.refresh_rate_type = index;
4795
4796 mutex_unlock(&intel_dp->drrs_state.mutex);
4797
4798 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4799}
4800
4f9db5b5
PB		 4801static struct drm_display_mode *
4802intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4803 struct intel_connector *intel_connector,
4804 struct drm_display_mode *fixed_mode)
4805{
4806 struct drm_connector *connector = &intel_connector->base;
4807 struct intel_dp *intel_dp = &intel_dig_port->dp;
4808 struct drm_device *dev = intel_dig_port->base.base.dev;
4809 struct drm_i915_private *dev_priv = dev->dev_private;
4810 struct drm_display_mode *downclock_mode = NULL;
4811
4812 if (INTEL_INFO(dev)->gen <= 6) {
4813 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4814 return NULL;
4815 }
4816
4817 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4818 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4819 return NULL;
4820 }
4821
4822 downclock_mode = intel_find_panel_downclock
4823 (dev, fixed_mode, connector);
4824
4825 if (!downclock_mode) {
4079b8d1 4826 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4827 return NULL;
4828 }
4829
439d7ac0
PB		 4830 dev_priv->drrs.connector = intel_connector;
4831
4832 mutex_init(&intel_dp->drrs_state.mutex);
4833
4f9db5b5
PB		 4834 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4835
4836 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4837 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4838 return downclock_mode;
4839}
4840
aba86890
ID		 4841void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4842{
4843 struct drm_device *dev = intel_encoder->base.dev;
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845 struct intel_dp *intel_dp;
4846 enum intel_display_power_domain power_domain;
4847
4848 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4849 return;
4850
4851 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 4852
4853 pps_lock(intel_dp);
4854
aba86890 4855 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4856 goto out;
aba86890
ID		 4857 /*
4858 * The VDD bit needs a power domain reference, so if the bit is
4859 * already enabled when we boot or resume, grab this reference and
4860 * schedule a vdd off, so we don't hold on to the reference
4861 * indefinitely.
4862 */
4863 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4864 power_domain = intel_display_port_power_domain(intel_encoder);
4865 intel_display_power_get(dev_priv, power_domain);
4866
4867 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 4868 out:
773538e8 4869 pps_unlock(intel_dp);
aba86890
ID		 4870}
4871
ed92f0b2 4872static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4873 struct intel_connector *intel_connector,
4874 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4875{
4876 struct drm_connector *connector = &intel_connector->base;
4877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4878 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4879 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4882 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4883 bool has_dpcd;
4884 struct drm_display_mode *scan;
4885 struct edid *edid;
4886
4f9db5b5
PB		 4887 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4888
ed92f0b2
PZ		 4889 if (!is_edp(intel_dp))
4890 return true;
4891
aba86890 4892 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4893
ed92f0b2 4894 /* Cache DPCD and EDID for edp. */
24f3e092 4895 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4896 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4897 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4898
4899 if (has_dpcd) {
4900 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4901 dev_priv->no_aux_handshake =
4902 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4903 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4904 } else {
4905 /* if this fails, presume the device is a ghost */
4906 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4907 return false;
4908 }
4909
4910 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4911 pps_lock(intel_dp);
0095e6dc 4912 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 4913 pps_unlock(intel_dp);
ed92f0b2 4914
060c8778 4915 mutex_lock(&dev->mode_config.mutex);
0b99836f 4916 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4917 if (edid) {
4918 if (drm_add_edid_modes(connector, edid)) {
4919 drm_mode_connector_update_edid_property(connector,
4920 edid);
4921 drm_edid_to_eld(connector, edid);
4922 } else {
4923 kfree(edid);
4924 edid = ERR_PTR(-EINVAL);
4925 }
4926 } else {
4927 edid = ERR_PTR(-ENOENT);
4928 }
4929 intel_connector->edid = edid;
4930
4931 /* prefer fixed mode from EDID if available */
4932 list_for_each_entry(scan, &connector->probed_modes, head) {
4933 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4934 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4935 downclock_mode = intel_dp_drrs_init(
4936 intel_dig_port,
4937 intel_connector, fixed_mode);
ed92f0b2
PZ		 4938 break;
4939 }
4940 }
4941
4942 /* fallback to VBT if available for eDP */
4943 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4944 fixed_mode = drm_mode_duplicate(dev,
4945 dev_priv->vbt.lfp_lvds_vbt_mode);
4946 if (fixed_mode)
4947 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4948 }
060c8778 4949 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4950
01527b31
CT		 4951 if (IS_VALLEYVIEW(dev)) {
4952 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4953 register_reboot_notifier(&intel_dp->edp_notifier);
4954 }
4955
4f9db5b5 4956 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4957 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 4958 intel_panel_setup_backlight(connector);
4959
4960 return true;
4961}
4962
16c25533 4963bool
f0fec3f2
PZ		 4964intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4965 struct intel_connector *intel_connector)
a4fc5ed6 4966{
f0fec3f2
PZ		 4967 struct drm_connector *connector = &intel_connector->base;
4968 struct intel_dp *intel_dp = &intel_dig_port->dp;
4969 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4970 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4971 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4972 enum port port = intel_dig_port->port;
0095e6dc 4973 struct edp_power_seq power_seq = { 0 };
0b99836f 4974 int type;
a4fc5ed6 4975
a4a5d2f8
VS		 4976 intel_dp->pps_pipe = INVALID_PIPE;
4977
ec5b01dd
DL		 4978 /* intel_dp vfuncs */
4979 if (IS_VALLEYVIEW(dev))
4980 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4981 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4982 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4983 else if (HAS_PCH_SPLIT(dev))
4984 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4985 else
4986 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4987
153b1100
DL		 4988 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4989
0767935e
DV		 4990 /* Preserve the current hw state. */
4991 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4992 intel_dp->attached_connector = intel_connector;
3d3dc149 4993
3b32a35b 4994 if (intel_dp_is_edp(dev, port))
b329530c 4995 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4996 else
4997 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4998
f7d24902
ID		 4999 /*
5000 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5001 * for DP the encoder type can be set by the caller to
5002 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5003 */
5004 if (type == DRM_MODE_CONNECTOR_eDP)
5005 intel_encoder->type = INTEL_OUTPUT_EDP;
5006
e7281eab
ID		 5007 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5008 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5009 port_name(port));
5010
b329530c 5011 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5012 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5013
a4fc5ed6
KP		 5014 connector->interlace_allowed = true;
5015 connector->doublescan_allowed = 0;
5016
f0fec3f2 5017 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5018 edp_panel_vdd_work);
a4fc5ed6 5019
df0e9248 5020 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5021 drm_connector_register(connector);
a4fc5ed6 5022
affa9354 5023 if (HAS_DDI(dev))
bcbc889b
PZ		 5024 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5025 else
5026 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5027 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5028
0b99836f 5029 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5030 switch (port) {
5031 case PORT_A:
1d843f9d 5032 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5033 break;
5034 case PORT_B:
1d843f9d 5035 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5036 break;
5037 case PORT_C:
1d843f9d 5038 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5039 break;
5040 case PORT_D:
1d843f9d 5041 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5042 break;
5043 default:
ad1c0b19 5044 BUG();
5eb08b69
ZW		 5045 }
5046
dada1a9f 5047 if (is_edp(intel_dp)) {
773538e8 5048 pps_lock(intel_dp);
a4a5d2f8
VS		 5049 if (IS_VALLEYVIEW(dev)) {
5050 vlv_initial_power_sequencer_setup(intel_dp);
5051 } else {
5052 intel_dp_init_panel_power_timestamps(intel_dp);
5053 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5054 &power_seq);
5055 }
773538e8 5056 pps_unlock(intel_dp);
dada1a9f 5057 }
0095e6dc 5058
9d1a1031 5059 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5060
0e32b39c
DA		 5061 /* init MST on ports that can support it */
5062 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5063 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5064 intel_dp_mst_encoder_init(intel_dig_port,
5065 intel_connector->base.base.id);
0e32b39c
DA		 5066 }
5067 }
5068
0095e6dc 5069 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5070 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5071 if (is_edp(intel_dp)) {
5072 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 5073 pps_lock(intel_dp);
4be73780 5074 edp_panel_vdd_off_sync(intel_dp);
773538e8 5075 pps_unlock(intel_dp);
15b1d171 5076 }
34ea3d38 5077 drm_connector_unregister(connector);
b2f246a8 5078 drm_connector_cleanup(connector);
16c25533 5079 return false;
b2f246a8 5080 }
32f9d658 5081
f684960e
CW		 5082 intel_dp_add_properties(intel_dp, connector);
5083
a4fc5ed6
KP		 5084 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5085 * 0xd. Failure to do so will result in spurious interrupts being
5086 * generated on the port when a cable is not attached.
5087 */
5088 if (IS_G4X(dev) && !IS_GM45(dev)) {
5089 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5090 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5091 }
16c25533
PZ		 5092
5093 return true;
a4fc5ed6 5094}
f0fec3f2
PZ		 5095
5096void
5097intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5098{
13cf5504 5099 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5100 struct intel_digital_port *intel_dig_port;
5101 struct intel_encoder *intel_encoder;
5102 struct drm_encoder *encoder;
5103 struct intel_connector *intel_connector;
5104
b14c5679 5105 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5106 if (!intel_dig_port)
5107 return;
5108
b14c5679 5109 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5110 if (!intel_connector) {
5111 kfree(intel_dig_port);
5112 return;
5113 }
5114
5115 intel_encoder = &intel_dig_port->base;
5116 encoder = &intel_encoder->base;
5117
5118 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5119 DRM_MODE_ENCODER_TMDS);
5120
5bfe2ac0 5121 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5122 intel_encoder->disable = intel_disable_dp;
00c09d70 5123 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5124 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5125 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5126 if (IS_CHERRYVIEW(dev)) {
9197c88b 5127 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5128 intel_encoder->pre_enable = chv_pre_enable_dp;
5129 intel_encoder->enable = vlv_enable_dp;
580d3811 5130 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5131 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5132 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5133 intel_encoder->pre_enable = vlv_pre_enable_dp;
5134 intel_encoder->enable = vlv_enable_dp;
49277c31 5135 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5136 } else {
ecff4f3b
JN		 5137 intel_encoder->pre_enable = g4x_pre_enable_dp;
5138 intel_encoder->enable = g4x_enable_dp;
49277c31 5139 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 5140 }
f0fec3f2 5141
174edf1f 5142 intel_dig_port->port = port;
f0fec3f2
PZ		 5143 intel_dig_port->dp.output_reg = output_reg;
5144
00c09d70 5145 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5146 if (IS_CHERRYVIEW(dev)) {
5147 if (port == PORT_D)
5148 intel_encoder->crtc_mask = 1 << 2;
5149 else
5150 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5151 } else {
5152 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5153 }
bc079e8b 5154 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5155 intel_encoder->hot_plug = intel_dp_hot_plug;
5156
13cf5504
DA		 5157 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5158 dev_priv->hpd_irq_port[port] = intel_dig_port;
5159
15b1d171
PZ		 5160 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5161 drm_encoder_cleanup(encoder);
5162 kfree(intel_dig_port);
b2f246a8 5163 kfree(intel_connector);
15b1d171 5164 }
f0fec3f2 5165}
0e32b39c
DA		 5166
5167void intel_dp_mst_suspend(struct drm_device *dev)
5168{
5169 struct drm_i915_private *dev_priv = dev->dev_private;
5170 int i;
5171
5172 /* disable MST */
5173 for (i = 0; i < I915_MAX_PORTS; i++) {
5174 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5175 if (!intel_dig_port)
5176 continue;
5177
5178 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5179 if (!intel_dig_port->dp.can_mst)
5180 continue;
5181 if (intel_dig_port->dp.is_mst)
5182 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5183 }
5184 }
5185}
5186
5187void intel_dp_mst_resume(struct drm_device *dev)
5188{
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 int i;
5191
5192 for (i = 0; i < I915_MAX_PORTS; i++) {
5193 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5194 if (!intel_dig_port)
5195 continue;
5196 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5197 int ret;
5198
5199 if (!intel_dig_port->dp.can_mst)
5200 continue;
5201
5202 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5203 if (ret != 0) {
5204 intel_dp_check_mst_status(&intel_dig_port->dp);
5205 }
5206 }
5207 }
5208}
Linux 6.x block layer and io_uring tree(s)