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drm/i915: clean up the cpu edp pll special case
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
d6f24d0f 35#include "drm_edid.h"
a4fc5ed6
KP		 36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
a4fc5ed6
KP		 39
40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
cfcb0fc9
JB		 43/**
44 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
45 * @intel_dp: DP struct
46 *
47 * If a CPU or PCH DP output is attached to an eDP panel, this function
48 * will return true, and false otherwise.
49 */
50static bool is_edp(struct intel_dp *intel_dp)
51{
52 return intel_dp->base.type == INTEL_OUTPUT_EDP;
53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
ea5b213a
CW		 79static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
80{
4ef69c7a 81 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 82}
a4fc5ed6 83
df0e9248
CW		 84static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
85{
86 return container_of(intel_attached_encoder(connector),
87 struct intel_dp, base);
88}
89
814948ad
JB		 90/**
91 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
92 * @encoder: DRM encoder
93 *
94 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
95 * by intel_display.c.
96 */
97bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
98{
99 struct intel_dp *intel_dp;
100
101 if (!encoder)
102 return false;
103
104 intel_dp = enc_to_intel_dp(encoder);
105
106 return is_pch_edp(intel_dp);
107}
108
33a34e4e
JB		 109static void intel_dp_start_link_train(struct intel_dp *intel_dp);
110static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 112
32f9d658 113void
0206e353 114intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 115 int *lane_num, int *link_bw)
32f9d658 116{
ea5b213a 117 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 118
ea5b213a
CW		 119 *lane_num = intel_dp->lane_count;
120 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 121 *link_bw = 162000;
ea5b213a 122 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 123 *link_bw = 270000;
124}
125
94bf2ced
DV		 126int
127intel_edp_target_clock(struct intel_encoder *intel_encoder,
128 struct drm_display_mode *mode)
129{
130 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
131
132 if (intel_dp->panel_fixed_mode)
133 return intel_dp->panel_fixed_mode->clock;
134 else
135 return mode->clock;
136}
137
a4fc5ed6 138static int
ea5b213a 139intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 140{
9a10f401
KP		 141 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
142 switch (max_lane_count) {
143 case 1: case 2: case 4:
144 break;
145 default:
146 max_lane_count = 4;
a4fc5ed6
KP		 147 }
148 return max_lane_count;
149}
150
151static int
ea5b213a 152intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 153{
7183dc29 154 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 155
156 switch (max_link_bw) {
157 case DP_LINK_BW_1_62:
158 case DP_LINK_BW_2_7:
159 break;
160 default:
161 max_link_bw = DP_LINK_BW_1_62;
162 break;
163 }
164 return max_link_bw;
165}
166
167static int
168intel_dp_link_clock(uint8_t link_bw)
169{
170 if (link_bw == DP_LINK_BW_2_7)
171 return 270000;
172 else
173 return 162000;
174}
175
cd9dde44
AJ		 176/*
177 * The units on the numbers in the next two are... bizarre. Examples will
178 * make it clearer; this one parallels an example in the eDP spec.
179 *
180 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
181 *
182 * 270000 * 1 * 8 / 10 == 216000
183 *
184 * The actual data capacity of that configuration is 2.16Gbit/s, so the
185 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
186 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
187 * 119000. At 18bpp that's 2142000 kilobits per second.
188 *
189 * Thus the strange-looking division by 10 in intel_dp_link_required, to
190 * get the result in decakilobits instead of kilobits.
191 */
192
a4fc5ed6 193static int
c898261c 194intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 195{
cd9dde44 196 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 197}
198
fe27d53e
DA		 199static int
200intel_dp_max_data_rate(int max_link_clock, int max_lanes)
201{
202 return (max_link_clock * max_lanes * 8) / 10;
203}
204
c4867936
DV		 205static bool
206intel_dp_adjust_dithering(struct intel_dp *intel_dp,
207 struct drm_display_mode *mode,
cb1793ce 208 bool adjust_mode)
c4867936
DV		 209{
210 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
211 int max_lanes = intel_dp_max_lane_count(intel_dp);
212 int max_rate, mode_rate;
213
214 mode_rate = intel_dp_link_required(mode->clock, 24);
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216
217 if (mode_rate > max_rate) {
218 mode_rate = intel_dp_link_required(mode->clock, 18);
219 if (mode_rate > max_rate)
220 return false;
221
cb1793ce
DV		 222 if (adjust_mode)
223 mode->private_flags
c4867936
DV		 224 |= INTEL_MODE_DP_FORCE_6BPC;
225
226 return true;
227 }
228
229 return true;
230}
231
a4fc5ed6
KP		 232static int
233intel_dp_mode_valid(struct drm_connector *connector,
234 struct drm_display_mode *mode)
235{
df0e9248 236 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 237
d15456de
KP		 238 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
239 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 240 return MODE_PANEL;
241
d15456de 242 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 243 return MODE_PANEL;
244 }
245
cb1793ce 246 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 247 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 248
249 if (mode->clock < 10000)
250 return MODE_CLOCK_LOW;
251
0af78a2b
DV		 252 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
253 return MODE_H_ILLEGAL;
254
a4fc5ed6
KP		 255 return MODE_OK;
256}
257
258static uint32_t
259pack_aux(uint8_t *src, int src_bytes)
260{
261 int i;
262 uint32_t v = 0;
263
264 if (src_bytes > 4)
265 src_bytes = 4;
266 for (i = 0; i < src_bytes; i++)
267 v |= ((uint32_t) src[i]) << ((3-i) * 8);
268 return v;
269}
270
271static void
272unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
273{
274 int i;
275 if (dst_bytes > 4)
276 dst_bytes = 4;
277 for (i = 0; i < dst_bytes; i++)
278 dst[i] = src >> ((3-i) * 8);
279}
280
fb0f8fbf
KP		 281/* hrawclock is 1/4 the FSB frequency */
282static int
283intel_hrawclk(struct drm_device *dev)
284{
285 struct drm_i915_private *dev_priv = dev->dev_private;
286 uint32_t clkcfg;
287
288 clkcfg = I915_READ(CLKCFG);
289 switch (clkcfg & CLKCFG_FSB_MASK) {
290 case CLKCFG_FSB_400:
291 return 100;
292 case CLKCFG_FSB_533:
293 return 133;
294 case CLKCFG_FSB_667:
295 return 166;
296 case CLKCFG_FSB_800:
297 return 200;
298 case CLKCFG_FSB_1067:
299 return 266;
300 case CLKCFG_FSB_1333:
301 return 333;
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600:
304 case CLKCFG_FSB_1600_ALT:
305 return 400;
306 default:
307 return 133;
308 }
309}
310
ebf33b18
KP		 311static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
312{
313 struct drm_device *dev = intel_dp->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
317}
318
319static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
325}
326
9b984dae
KP		 327static void
328intel_dp_check_edp(struct intel_dp *intel_dp)
329{
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 332
9b984dae
KP		 333 if (!is_edp(intel_dp))
334 return;
ebf33b18 335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 338 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 339 I915_READ(PCH_PP_CONTROL));
340 }
341}
342
a4fc5ed6 343static int
ea5b213a 344intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 345 uint8_t *send, int send_bytes,
346 uint8_t *recv, int recv_size)
347{
ea5b213a 348 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 349 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 350 struct drm_i915_private *dev_priv = dev->dev_private;
351 uint32_t ch_ctl = output_reg + 0x10;
352 uint32_t ch_data = ch_ctl + 4;
353 int i;
354 int recv_bytes;
a4fc5ed6 355 uint32_t status;
fb0f8fbf 356 uint32_t aux_clock_divider;
6b4e0a93 357 int try, precharge;
a4fc5ed6 358
9b984dae 359 intel_dp_check_edp(intel_dp);
a4fc5ed6 360 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 361 * and would like to run at 2MHz. So, take the
362 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 363 *
364 * Note that PCH attached eDP panels should use a 125MHz input
365 * clock divider.
a4fc5ed6 366 */
1c95822a 367 if (is_cpu_edp(intel_dp)) {
1a2eb460
KP		 368 if (IS_GEN6(dev) || IS_GEN7(dev))
369 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 370 else
371 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
372 } else if (HAS_PCH_SPLIT(dev))
6919132e 373 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 374 else
375 aux_clock_divider = intel_hrawclk(dev) / 2;
376
6b4e0a93
DV		 377 if (IS_GEN6(dev))
378 precharge = 3;
379 else
380 precharge = 5;
381
11bee43e
JB		 382 /* Try to wait for any previous AUX channel activity */
383 for (try = 0; try < 3; try++) {
384 status = I915_READ(ch_ctl);
385 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
386 break;
387 msleep(1);
388 }
389
390 if (try == 3) {
391 WARN(1, "dp_aux_ch not started status 0x%08x\n",
392 I915_READ(ch_ctl));
4f7f7b7e
CW		 393 return -EBUSY;
394 }
395
fb0f8fbf
KP		 396 /* Must try at least 3 times according to DP spec */
397 for (try = 0; try < 5; try++) {
398 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 399 for (i = 0; i < send_bytes; i += 4)
400 I915_WRITE(ch_data + i,
401 pack_aux(send + i, send_bytes - i));
0206e353 402
fb0f8fbf 403 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 404 I915_WRITE(ch_ctl,
405 DP_AUX_CH_CTL_SEND_BUSY |
406 DP_AUX_CH_CTL_TIME_OUT_400us |
407 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
408 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
409 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
410 DP_AUX_CH_CTL_DONE |
411 DP_AUX_CH_CTL_TIME_OUT_ERROR |
412 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 413 for (;;) {
fb0f8fbf
KP		 414 status = I915_READ(ch_ctl);
415 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
416 break;
4f7f7b7e 417 udelay(100);
fb0f8fbf 418 }
0206e353 419
fb0f8fbf 420 /* Clear done status and any errors */
4f7f7b7e
CW		 421 I915_WRITE(ch_ctl,
422 status |
423 DP_AUX_CH_CTL_DONE |
424 DP_AUX_CH_CTL_TIME_OUT_ERROR |
425 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 426
427 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
428 DP_AUX_CH_CTL_RECEIVE_ERROR))
429 continue;
4f7f7b7e 430 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 431 break;
432 }
433
a4fc5ed6 434 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 435 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 436 return -EBUSY;
a4fc5ed6
KP		 437 }
438
439 /* Check for timeout or receive error.
440 * Timeouts occur when the sink is not connected
441 */
a5b3da54 442 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 443 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 444 return -EIO;
445 }
1ae8c0a5
KP		 446
447 /* Timeouts occur when the device isn't connected, so they're
448 * "normal" -- don't fill the kernel log with these */
a5b3da54 449 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 450 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 451 return -ETIMEDOUT;
a4fc5ed6
KP		 452 }
453
454 /* Unload any bytes sent back from the other side */
455 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
456 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 457 if (recv_bytes > recv_size)
458 recv_bytes = recv_size;
0206e353 459
4f7f7b7e
CW		 460 for (i = 0; i < recv_bytes; i += 4)
461 unpack_aux(I915_READ(ch_data + i),
462 recv + i, recv_bytes - i);
a4fc5ed6
KP		 463
464 return recv_bytes;
465}
466
467/* Write data to the aux channel in native mode */
468static int
ea5b213a 469intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 470 uint16_t address, uint8_t *send, int send_bytes)
471{
472 int ret;
473 uint8_t msg[20];
474 int msg_bytes;
475 uint8_t ack;
476
9b984dae 477 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 478 if (send_bytes > 16)
479 return -1;
480 msg[0] = AUX_NATIVE_WRITE << 4;
481 msg[1] = address >> 8;
eebc863e 482 msg[2] = address & 0xff;
a4fc5ed6
KP		 483 msg[3] = send_bytes - 1;
484 memcpy(&msg[4], send, send_bytes);
485 msg_bytes = send_bytes + 4;
486 for (;;) {
ea5b213a 487 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 488 if (ret < 0)
489 return ret;
490 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
491 break;
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
493 udelay(100);
494 else
a5b3da54 495 return -EIO;
a4fc5ed6
KP		 496 }
497 return send_bytes;
498}
499
500/* Write a single byte to the aux channel in native mode */
501static int
ea5b213a 502intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 503 uint16_t address, uint8_t byte)
504{
ea5b213a 505 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 506}
507
508/* read bytes from a native aux channel */
509static int
ea5b213a 510intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 511 uint16_t address, uint8_t *recv, int recv_bytes)
512{
513 uint8_t msg[4];
514 int msg_bytes;
515 uint8_t reply[20];
516 int reply_bytes;
517 uint8_t ack;
518 int ret;
519
9b984dae 520 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 521 msg[0] = AUX_NATIVE_READ << 4;
522 msg[1] = address >> 8;
523 msg[2] = address & 0xff;
524 msg[3] = recv_bytes - 1;
525
526 msg_bytes = 4;
527 reply_bytes = recv_bytes + 1;
528
529 for (;;) {
ea5b213a 530 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 531 reply, reply_bytes);
a5b3da54
KP		 532 if (ret == 0)
533 return -EPROTO;
534 if (ret < 0)
a4fc5ed6
KP		 535 return ret;
536 ack = reply[0];
537 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
538 memcpy(recv, reply + 1, ret - 1);
539 return ret - 1;
540 }
541 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
542 udelay(100);
543 else
a5b3da54 544 return -EIO;
a4fc5ed6
KP		 545 }
546}
547
548static int
ab2c0672
DA		 549intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
550 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 551{
ab2c0672 552 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 553 struct intel_dp *intel_dp = container_of(adapter,
554 struct intel_dp,
555 adapter);
ab2c0672
DA		 556 uint16_t address = algo_data->address;
557 uint8_t msg[5];
558 uint8_t reply[2];
8316f337 559 unsigned retry;
ab2c0672
DA		 560 int msg_bytes;
561 int reply_bytes;
562 int ret;
563
9b984dae 564 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 565 /* Set up the command byte */
566 if (mode & MODE_I2C_READ)
567 msg[0] = AUX_I2C_READ << 4;
568 else
569 msg[0] = AUX_I2C_WRITE << 4;
570
571 if (!(mode & MODE_I2C_STOP))
572 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 573
ab2c0672
DA		 574 msg[1] = address >> 8;
575 msg[2] = address;
576
577 switch (mode) {
578 case MODE_I2C_WRITE:
579 msg[3] = 0;
580 msg[4] = write_byte;
581 msg_bytes = 5;
582 reply_bytes = 1;
583 break;
584 case MODE_I2C_READ:
585 msg[3] = 0;
586 msg_bytes = 4;
587 reply_bytes = 2;
588 break;
589 default:
590 msg_bytes = 3;
591 reply_bytes = 1;
592 break;
593 }
594
8316f337
DF		 595 for (retry = 0; retry < 5; retry++) {
596 ret = intel_dp_aux_ch(intel_dp,
597 msg, msg_bytes,
598 reply, reply_bytes);
ab2c0672 599 if (ret < 0) {
3ff99164 600 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 601 return ret;
602 }
8316f337
DF		 603
604 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
605 case AUX_NATIVE_REPLY_ACK:
606 /* I2C-over-AUX Reply field is only valid
607 * when paired with AUX ACK.
608 */
609 break;
610 case AUX_NATIVE_REPLY_NACK:
611 DRM_DEBUG_KMS("aux_ch native nack\n");
612 return -EREMOTEIO;
613 case AUX_NATIVE_REPLY_DEFER:
614 udelay(100);
615 continue;
616 default:
617 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
618 reply[0]);
619 return -EREMOTEIO;
620 }
621
ab2c0672
DA		 622 switch (reply[0] & AUX_I2C_REPLY_MASK) {
623 case AUX_I2C_REPLY_ACK:
624 if (mode == MODE_I2C_READ) {
625 *read_byte = reply[1];
626 }
627 return reply_bytes - 1;
628 case AUX_I2C_REPLY_NACK:
8316f337 629 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 630 return -EREMOTEIO;
631 case AUX_I2C_REPLY_DEFER:
8316f337 632 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 633 udelay(100);
634 break;
635 default:
8316f337 636 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 637 return -EREMOTEIO;
638 }
639 }
8316f337
DF		 640
641 DRM_ERROR("too many retries, giving up\n");
642 return -EREMOTEIO;
a4fc5ed6
KP		 643}
644
0b5c541b 645static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 646static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 647
a4fc5ed6 648static int
ea5b213a 649intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 650 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 651{
0b5c541b
KP		 652 int ret;
653
d54e9d28 654 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 655 intel_dp->algo.running = false;
656 intel_dp->algo.address = 0;
657 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
658
0206e353 659 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 660 intel_dp->adapter.owner = THIS_MODULE;
661 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 662 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 663 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
664 intel_dp->adapter.algo_data = &intel_dp->algo;
665 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
666
0b5c541b
KP		 667 ironlake_edp_panel_vdd_on(intel_dp);
668 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 669 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 670 return ret;
a4fc5ed6
KP		 671}
672
673static bool
e811f5ae
LP		 674intel_dp_mode_fixup(struct drm_encoder *encoder,
675 const struct drm_display_mode *mode,
a4fc5ed6
KP		 676 struct drm_display_mode *adjusted_mode)
677{
0d3a1bee 678 struct drm_device *dev = encoder->dev;
ea5b213a 679 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 680 int lane_count, clock;
ea5b213a
CW		 681 int max_lane_count = intel_dp_max_lane_count(intel_dp);
682 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 683 int bpp, mode_rate;
a4fc5ed6
KP		 684 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
685
d15456de
KP		 686 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
687 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 688 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
689 mode, adjusted_mode);
0d3a1bee
ZY		 690 }
691
cb1793ce 692 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 693 return false;
694
083f9560
DV		 695 DRM_DEBUG_KMS("DP link computation with max lane count %i "
696 "max bw %02x pixel clock %iKHz\n",
71244653 697 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 698
cb1793ce 699 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 700 return false;
701
702 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 703 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 704
2514bc51
JB		 705 for (clock = 0; clock <= max_clock; clock++) {
706 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 707 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 708
083f9560 709 if (mode_rate <= link_avail) {
ea5b213a
CW		 710 intel_dp->link_bw = bws[clock];
711 intel_dp->lane_count = lane_count;
712 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 713 DRM_DEBUG_KMS("DP link bw %02x lane "
714 "count %d clock %d bpp %d\n",
ea5b213a 715 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 716 adjusted_mode->clock, bpp);
717 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
718 mode_rate, link_avail);
a4fc5ed6
KP		 719 return true;
720 }
721 }
722 }
fe27d53e 723
a4fc5ed6
KP		 724 return false;
725}
726
727struct intel_dp_m_n {
728 uint32_t tu;
729 uint32_t gmch_m;
730 uint32_t gmch_n;
731 uint32_t link_m;
732 uint32_t link_n;
733};
734
735static void
736intel_reduce_ratio(uint32_t *num, uint32_t *den)
737{
738 while (*num > 0xffffff || *den > 0xffffff) {
739 *num >>= 1;
740 *den >>= 1;
741 }
742}
743
744static void
36e83a18 745intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 746 int nlanes,
747 int pixel_clock,
748 int link_clock,
749 struct intel_dp_m_n *m_n)
750{
751 m_n->tu = 64;
36e83a18 752 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 753 m_n->gmch_n = link_clock * nlanes;
754 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
755 m_n->link_m = pixel_clock;
756 m_n->link_n = link_clock;
757 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
758}
759
760void
761intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
762 struct drm_display_mode *adjusted_mode)
763{
764 struct drm_device *dev = crtc->dev;
6c2b7c12 765 struct intel_encoder *encoder;
a4fc5ed6
KP		 766 struct drm_i915_private *dev_priv = dev->dev_private;
767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 768 int lane_count = 4;
a4fc5ed6 769 struct intel_dp_m_n m_n;
9db4a9c7 770 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 771
772 /*
21d40d37 773 * Find the lane count in the intel_encoder private
a4fc5ed6 774 */
6c2b7c12
DV		 775 for_each_encoder_on_crtc(dev, crtc, encoder) {
776 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 777
9a10f401
KP		 778 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
779 intel_dp->base.type == INTEL_OUTPUT_EDP)
780 {
ea5b213a 781 lane_count = intel_dp->lane_count;
51190667 782 break;
a4fc5ed6
KP		 783 }
784 }
785
786 /*
787 * Compute the GMCH and Link ratios. The '3' here is
788 * the number of bytes_per_pixel post-LUT, which we always
789 * set up for 8-bits of R/G/B, or 3 bytes total.
790 */
858fa035 791 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 792 mode->clock, adjusted_mode->clock, &m_n);
793
c619eed4 794 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 795 I915_WRITE(TRANSDATA_M1(pipe),
796 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
797 m_n.gmch_m);
798 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
799 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
800 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 801 } else {
9db4a9c7
JB		 802 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
803 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
804 m_n.gmch_m);
805 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
806 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
807 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 808 }
809}
810
811static void
812intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
813 struct drm_display_mode *adjusted_mode)
814{
e3421a18 815 struct drm_device *dev = encoder->dev;
417e822d 816 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 817 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 818 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
820
417e822d 821 /*
1a2eb460 822 * There are four kinds of DP registers:
417e822d
KP		 823 *
824 * IBX PCH
1a2eb460
KP		 825 * SNB CPU
826 * IVB CPU
417e822d
KP		 827 * CPT PCH
828 *
829 * IBX PCH and CPU are the same for almost everything,
830 * except that the CPU DP PLL is configured in this
831 * register
832 *
833 * CPT PCH is quite different, having many bits moved
834 * to the TRANS_DP_CTL register instead. That
835 * configuration happens (oddly) in ironlake_pch_enable
836 */
9c9e7927 837
417e822d
KP		 838 /* Preserve the BIOS-computed detected bit. This is
839 * supposed to be read-only.
840 */
841 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 842
417e822d 843 /* Handle DP bits in common between all three register formats */
417e822d 844 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 845
ea5b213a 846 switch (intel_dp->lane_count) {
a4fc5ed6 847 case 1:
ea5b213a 848 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 849 break;
850 case 2:
ea5b213a 851 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 852 break;
853 case 4:
ea5b213a 854 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 855 break;
856 }
e0dac65e
WF		 857 if (intel_dp->has_audio) {
858 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
859 pipe_name(intel_crtc->pipe));
ea5b213a 860 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 861 intel_write_eld(encoder, adjusted_mode);
862 }
ea5b213a
CW		 863 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
864 intel_dp->link_configuration[0] = intel_dp->link_bw;
865 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 866 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 867 /*
9962c925 868 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 869 */
7183dc29
JB		 870 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
871 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 872 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 873 }
874
417e822d 875 /* Split out the IBX/CPU vs CPT settings */
32f9d658 876
1a2eb460
KP		 877 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
878 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
879 intel_dp->DP |= DP_SYNC_HS_HIGH;
880 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
881 intel_dp->DP |= DP_SYNC_VS_HIGH;
882 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
883
884 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
885 intel_dp->DP |= DP_ENHANCED_FRAMING;
886
887 intel_dp->DP |= intel_crtc->pipe << 29;
888
889 /* don't miss out required setting for eDP */
890 intel_dp->DP |= DP_PLL_ENABLE;
891 if (adjusted_mode->clock < 200000)
892 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
893 else
894 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
895 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 896 intel_dp->DP |= intel_dp->color_range;
897
898 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
899 intel_dp->DP |= DP_SYNC_HS_HIGH;
900 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
901 intel_dp->DP |= DP_SYNC_VS_HIGH;
902 intel_dp->DP |= DP_LINK_TRAIN_OFF;
903
904 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
905 intel_dp->DP |= DP_ENHANCED_FRAMING;
906
907 if (intel_crtc->pipe == 1)
908 intel_dp->DP |= DP_PIPEB_SELECT;
909
910 if (is_cpu_edp(intel_dp)) {
911 /* don't miss out required setting for eDP */
912 intel_dp->DP |= DP_PLL_ENABLE;
913 if (adjusted_mode->clock < 200000)
914 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
915 else
916 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
917 }
918 } else {
919 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 920 }
a4fc5ed6
KP		 921}
922
99ea7127
KP		 923#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
924#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
925
926#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
927#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
928
929#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
930#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
931
932static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
933 u32 mask,
934 u32 value)
bd943159 935{
99ea7127
KP		 936 struct drm_device *dev = intel_dp->base.base.dev;
937 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 938
99ea7127
KP		 939 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
940 mask, value,
941 I915_READ(PCH_PP_STATUS),
942 I915_READ(PCH_PP_CONTROL));
32ce697c 943
99ea7127
KP		 944 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
945 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
946 I915_READ(PCH_PP_STATUS),
947 I915_READ(PCH_PP_CONTROL));
32ce697c 948 }
99ea7127 949}
32ce697c 950
99ea7127
KP		 951static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
952{
953 DRM_DEBUG_KMS("Wait for panel power on\n");
954 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 955}
956
99ea7127
KP		 957static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
958{
959 DRM_DEBUG_KMS("Wait for panel power off time\n");
960 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
961}
962
963static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
964{
965 DRM_DEBUG_KMS("Wait for panel power cycle\n");
966 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
967}
968
969
832dd3c1
KP		 970/* Read the current pp_control value, unlocking the register if it
971 * is locked
972 */
973
974static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
975{
976 u32 control = I915_READ(PCH_PP_CONTROL);
977
978 control &= ~PANEL_UNLOCK_MASK;
979 control |= PANEL_UNLOCK_REGS;
980 return control;
bd943159
KP		 981}
982
5d613501
JB		 983static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
984{
985 struct drm_device *dev = intel_dp->base.base.dev;
986 struct drm_i915_private *dev_priv = dev->dev_private;
987 u32 pp;
988
97af61f5
KP		 989 if (!is_edp(intel_dp))
990 return;
f01eca2e 991 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 992
bd943159
KP		 993 WARN(intel_dp->want_panel_vdd,
994 "eDP VDD already requested on\n");
995
996 intel_dp->want_panel_vdd = true;
99ea7127 997
bd943159
KP		 998 if (ironlake_edp_have_panel_vdd(intel_dp)) {
999 DRM_DEBUG_KMS("eDP VDD already on\n");
1000 return;
1001 }
1002
99ea7127
KP		 1003 if (!ironlake_edp_have_panel_power(intel_dp))
1004 ironlake_wait_panel_power_cycle(intel_dp);
1005
832dd3c1 1006 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1007 pp |= EDP_FORCE_VDD;
1008 I915_WRITE(PCH_PP_CONTROL, pp);
1009 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1010 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1011 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1012
1013 /*
1014 * If the panel wasn't on, delay before accessing aux channel
1015 */
1016 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1017 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1018 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1019 }
5d613501
JB		 1020}
1021
bd943159 1022static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1023{
1024 struct drm_device *dev = intel_dp->base.base.dev;
1025 struct drm_i915_private *dev_priv = dev->dev_private;
1026 u32 pp;
1027
bd943159 1028 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1029 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1030 pp &= ~EDP_FORCE_VDD;
1031 I915_WRITE(PCH_PP_CONTROL, pp);
1032 POSTING_READ(PCH_PP_CONTROL);
1033
1034 /* Make sure sequencer is idle before allowing subsequent activity */
1035 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1036 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1037
1038 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1039 }
1040}
5d613501 1041
bd943159
KP		 1042static void ironlake_panel_vdd_work(struct work_struct *__work)
1043{
1044 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1045 struct intel_dp, panel_vdd_work);
1046 struct drm_device *dev = intel_dp->base.base.dev;
1047
627f7675 1048 mutex_lock(&dev->mode_config.mutex);
bd943159 1049 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1050 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1051}
1052
1053static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1054{
97af61f5
KP		 1055 if (!is_edp(intel_dp))
1056 return;
5d613501 1057
bd943159
KP		 1058 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1059 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1060
bd943159
KP		 1061 intel_dp->want_panel_vdd = false;
1062
1063 if (sync) {
1064 ironlake_panel_vdd_off_sync(intel_dp);
1065 } else {
1066 /*
1067 * Queue the timer to fire a long
1068 * time from now (relative to the power down delay)
1069 * to keep the panel power up across a sequence of operations
1070 */
1071 schedule_delayed_work(&intel_dp->panel_vdd_work,
1072 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1073 }
5d613501
JB		 1074}
1075
86a3073e 1076static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1077{
01cb9ea6 1078 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1079 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1080 u32 pp;
9934c132 1081
97af61f5 1082 if (!is_edp(intel_dp))
bd943159 1083 return;
99ea7127
KP		 1084
1085 DRM_DEBUG_KMS("Turn eDP power on\n");
1086
1087 if (ironlake_edp_have_panel_power(intel_dp)) {
1088 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1089 return;
99ea7127 1090 }
9934c132 1091
99ea7127 1092 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1093
99ea7127 1094 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1095 if (IS_GEN5(dev)) {
1096 /* ILK workaround: disable reset around power sequence */
1097 pp &= ~PANEL_POWER_RESET;
1098 I915_WRITE(PCH_PP_CONTROL, pp);
1099 POSTING_READ(PCH_PP_CONTROL);
1100 }
37c6c9b0 1101
1c0ae80a 1102 pp |= POWER_TARGET_ON;
99ea7127
KP		 1103 if (!IS_GEN5(dev))
1104 pp |= PANEL_POWER_RESET;
1105
9934c132 1106 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1107 POSTING_READ(PCH_PP_CONTROL);
9934c132 1108
99ea7127 1109 ironlake_wait_panel_on(intel_dp);
9934c132 1110
05ce1a49
KP		 1111 if (IS_GEN5(dev)) {
1112 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1113 I915_WRITE(PCH_PP_CONTROL, pp);
1114 POSTING_READ(PCH_PP_CONTROL);
1115 }
9934c132
JB		 1116}
1117
99ea7127 1118static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1119{
99ea7127 1120 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1121 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1122 u32 pp;
9934c132 1123
97af61f5
KP		 1124 if (!is_edp(intel_dp))
1125 return;
37c6c9b0 1126
99ea7127 1127 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1128
6cb49835 1129 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1130
99ea7127 1131 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1132 /* We need to switch off panel power _and_ force vdd, for otherwise some
1133 * panels get very unhappy and cease to work. */
1134 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1135 I915_WRITE(PCH_PP_CONTROL, pp);
1136 POSTING_READ(PCH_PP_CONTROL);
9934c132 1137
35a38556
DV		 1138 intel_dp->want_panel_vdd = false;
1139
99ea7127 1140 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1141}
1142
86a3073e 1143static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1144{
f01eca2e 1145 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1146 struct drm_i915_private *dev_priv = dev->dev_private;
1147 u32 pp;
1148
f01eca2e
KP		 1149 if (!is_edp(intel_dp))
1150 return;
1151
28c97730 1152 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1153 /*
1154 * If we enable the backlight right away following a panel power
1155 * on, we may see slight flicker as the panel syncs with the eDP
1156 * link. So delay a bit to make sure the image is solid before
1157 * allowing it to appear.
1158 */
f01eca2e 1159 msleep(intel_dp->backlight_on_delay);
832dd3c1 1160 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1161 pp |= EDP_BLC_ENABLE;
1162 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1163 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1164}
1165
86a3073e 1166static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1167{
f01eca2e 1168 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1169 struct drm_i915_private *dev_priv = dev->dev_private;
1170 u32 pp;
1171
f01eca2e
KP		 1172 if (!is_edp(intel_dp))
1173 return;
1174
28c97730 1175 DRM_DEBUG_KMS("\n");
832dd3c1 1176 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1177 pp &= ~EDP_BLC_ENABLE;
1178 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1179 POSTING_READ(PCH_PP_CONTROL);
1180 msleep(intel_dp->backlight_off_delay);
32f9d658 1181}
a4fc5ed6 1182
2bd2ad64 1183static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1184{
2bd2ad64
DV		 1185 struct drm_device *dev = intel_dp->base.base.dev;
1186 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1187 struct drm_i915_private *dev_priv = dev->dev_private;
1188 u32 dpa_ctl;
1189
2bd2ad64
DV		 1190 assert_pipe_disabled(dev_priv,
1191 to_intel_crtc(crtc)->pipe);
1192
d240f20f
JB		 1193 DRM_DEBUG_KMS("\n");
1194 dpa_ctl = I915_READ(DP_A);
298b0b39 1195 dpa_ctl |= DP_PLL_ENABLE;
d240f20f 1196 I915_WRITE(DP_A, dpa_ctl);
298b0b39
JB		 1197 POSTING_READ(DP_A);
1198 udelay(200);
d240f20f
JB		 1199}
1200
2bd2ad64 1201static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1202{
2bd2ad64
DV		 1203 struct drm_device *dev = intel_dp->base.base.dev;
1204 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 u32 dpa_ctl;
1207
2bd2ad64
DV		 1208 assert_pipe_disabled(dev_priv,
1209 to_intel_crtc(crtc)->pipe);
1210
d240f20f 1211 dpa_ctl = I915_READ(DP_A);
298b0b39 1212 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1213 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1214 POSTING_READ(DP_A);
d240f20f
JB		 1215 udelay(200);
1216}
1217
c7ad3810
JB		 1218/* If the sink supports it, try to set the power state appropriately */
1219static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1220{
1221 int ret, i;
1222
1223 /* Should have a valid DPCD by this point */
1224 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1225 return;
1226
1227 if (mode != DRM_MODE_DPMS_ON) {
1228 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1229 DP_SET_POWER_D3);
1230 if (ret != 1)
1231 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1232 } else {
1233 /*
1234 * When turning on, we need to retry for 1ms to give the sink
1235 * time to wake up.
1236 */
1237 for (i = 0; i < 3; i++) {
1238 ret = intel_dp_aux_native_write_1(intel_dp,
1239 DP_SET_POWER,
1240 DP_SET_POWER_D0);
1241 if (ret == 1)
1242 break;
1243 msleep(1);
1244 }
1245 }
1246}
1247
19d8fe15
DV		 1248static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1249 enum pipe *pipe)
d240f20f 1250{
19d8fe15
DV		 1251 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1252 struct drm_device *dev = encoder->base.dev;
1253 struct drm_i915_private *dev_priv = dev->dev_private;
1254 u32 tmp = I915_READ(intel_dp->output_reg);
1255
1256 if (!(tmp & DP_PORT_EN))
1257 return false;
1258
1259 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1260 *pipe = PORT_TO_PIPE_CPT(tmp);
1261 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1262 *pipe = PORT_TO_PIPE(tmp);
1263 } else {
1264 u32 trans_sel;
1265 u32 trans_dp;
1266 int i;
1267
1268 switch (intel_dp->output_reg) {
1269 case PCH_DP_B:
1270 trans_sel = TRANS_DP_PORT_SEL_B;
1271 break;
1272 case PCH_DP_C:
1273 trans_sel = TRANS_DP_PORT_SEL_C;
1274 break;
1275 case PCH_DP_D:
1276 trans_sel = TRANS_DP_PORT_SEL_D;
1277 break;
1278 default:
1279 return true;
1280 }
1281
1282 for_each_pipe(i) {
1283 trans_dp = I915_READ(TRANS_DP_CTL(i));
1284 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1285 *pipe = i;
1286 return true;
1287 }
1288 }
1289 }
1290
1291 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1292
19d8fe15
DV		 1293 return true;
1294}
1295
e8cb4558 1296static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1297{
e8cb4558 1298 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1299
1300 /* Make sure the panel is off before trying to change the mode. But also
1301 * ensure that we have vdd while we switch off the panel. */
1302 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1303 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1304 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1305 ironlake_edp_panel_off(intel_dp);
21264c63 1306 intel_dp_link_down(intel_dp);
d240f20f
JB		 1307}
1308
2bd2ad64
DV		 1309static void intel_post_disable_dp(struct intel_encoder *encoder)
1310{
1311 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1312
1313 if (is_cpu_edp(intel_dp))
1314 ironlake_edp_pll_off(intel_dp);
1315}
1316
e8cb4558 1317static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1318{
e8cb4558
DV		 1319 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1320 struct drm_device *dev = encoder->base.dev;
1321 struct drm_i915_private *dev_priv = dev->dev_private;
1322 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1323
97af61f5 1324 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1325 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
e8cb4558
DV		 1326 if (!(dp_reg & DP_PORT_EN)) {
1327 intel_dp_start_link_train(intel_dp);
1328 ironlake_edp_panel_on(intel_dp);
1329 ironlake_edp_panel_vdd_off(intel_dp, true);
1330 intel_dp_complete_link_train(intel_dp);
1331 } else
1332 ironlake_edp_panel_vdd_off(intel_dp, false);
f01eca2e 1333 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1334}
1335
2bd2ad64 1336static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1337{
2bd2ad64 1338 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1339
2bd2ad64
DV		 1340 if (is_cpu_edp(intel_dp))
1341 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1342}
1343
1344/*
df0c237d
JB		 1345 * Native read with retry for link status and receiver capability reads for
1346 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1347 */
1348static bool
df0c237d
JB		 1349intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1350 uint8_t *recv, int recv_bytes)
a4fc5ed6 1351{
61da5fab
JB		 1352 int ret, i;
1353
df0c237d
JB		 1354 /*
1355 * Sinks are *supposed* to come up within 1ms from an off state,
1356 * but we're also supposed to retry 3 times per the spec.
1357 */
61da5fab 1358 for (i = 0; i < 3; i++) {
df0c237d
JB		 1359 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1360 recv_bytes);
1361 if (ret == recv_bytes)
61da5fab
JB		 1362 return true;
1363 msleep(1);
1364 }
a4fc5ed6 1365
61da5fab 1366 return false;
a4fc5ed6
KP		 1367}
1368
1369/*
1370 * Fetch AUX CH registers 0x202 - 0x207 which contain
1371 * link status information
1372 */
1373static bool
93f62dad 1374intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1375{
df0c237d
JB		 1376 return intel_dp_aux_native_read_retry(intel_dp,
1377 DP_LANE0_1_STATUS,
93f62dad 1378 link_status,
df0c237d 1379 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1380}
1381
1382static uint8_t
1383intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1384 int r)
1385{
1386 return link_status[r - DP_LANE0_1_STATUS];
1387}
1388
a4fc5ed6 1389static uint8_t
93f62dad 1390intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1391 int lane)
1392{
a4fc5ed6
KP		 1393 int s = ((lane & 1) ?
1394 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1395 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1396 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1397
1398 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1399}
1400
1401static uint8_t
93f62dad 1402intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1403 int lane)
1404{
a4fc5ed6
KP		 1405 int s = ((lane & 1) ?
1406 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1407 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1408 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1409
1410 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1411}
1412
1413
1414#if 0
1415static char *voltage_names[] = {
1416 "0.4V", "0.6V", "0.8V", "1.2V"
1417};
1418static char *pre_emph_names[] = {
1419 "0dB", "3.5dB", "6dB", "9.5dB"
1420};
1421static char *link_train_names[] = {
1422 "pattern 1", "pattern 2", "idle", "off"
1423};
1424#endif
1425
1426/*
1427 * These are source-specific values; current Intel hardware supports
1428 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1429 */
a4fc5ed6
KP		 1430
1431static uint8_t
1a2eb460 1432intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1433{
1a2eb460
KP		 1434 struct drm_device *dev = intel_dp->base.base.dev;
1435
1436 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1437 return DP_TRAIN_VOLTAGE_SWING_800;
1438 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1439 return DP_TRAIN_VOLTAGE_SWING_1200;
1440 else
1441 return DP_TRAIN_VOLTAGE_SWING_800;
1442}
1443
1444static uint8_t
1445intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1446{
1447 struct drm_device *dev = intel_dp->base.base.dev;
1448
1449 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1450 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1451 case DP_TRAIN_VOLTAGE_SWING_400:
1452 return DP_TRAIN_PRE_EMPHASIS_6;
1453 case DP_TRAIN_VOLTAGE_SWING_600:
1454 case DP_TRAIN_VOLTAGE_SWING_800:
1455 return DP_TRAIN_PRE_EMPHASIS_3_5;
1456 default:
1457 return DP_TRAIN_PRE_EMPHASIS_0;
1458 }
1459 } else {
1460 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1461 case DP_TRAIN_VOLTAGE_SWING_400:
1462 return DP_TRAIN_PRE_EMPHASIS_6;
1463 case DP_TRAIN_VOLTAGE_SWING_600:
1464 return DP_TRAIN_PRE_EMPHASIS_6;
1465 case DP_TRAIN_VOLTAGE_SWING_800:
1466 return DP_TRAIN_PRE_EMPHASIS_3_5;
1467 case DP_TRAIN_VOLTAGE_SWING_1200:
1468 default:
1469 return DP_TRAIN_PRE_EMPHASIS_0;
1470 }
a4fc5ed6
KP		 1471 }
1472}
1473
1474static void
93f62dad 1475intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1476{
1477 uint8_t v = 0;
1478 uint8_t p = 0;
1479 int lane;
93f62dad 1480 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1481 uint8_t voltage_max;
1482 uint8_t preemph_max;
a4fc5ed6 1483
33a34e4e 1484 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1485 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1486 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1487
1488 if (this_v > v)
1489 v = this_v;
1490 if (this_p > p)
1491 p = this_p;
1492 }
1493
1a2eb460 1494 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1495 if (v >= voltage_max)
1496 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1497
1a2eb460
KP		 1498 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1499 if (p >= preemph_max)
1500 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1501
1502 for (lane = 0; lane < 4; lane++)
33a34e4e 1503 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1504}
1505
1506static uint32_t
93f62dad 1507intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1508{
3cf2efb1 1509 uint32_t signal_levels = 0;
a4fc5ed6 1510
3cf2efb1 1511 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1512 case DP_TRAIN_VOLTAGE_SWING_400:
1513 default:
1514 signal_levels |= DP_VOLTAGE_0_4;
1515 break;
1516 case DP_TRAIN_VOLTAGE_SWING_600:
1517 signal_levels |= DP_VOLTAGE_0_6;
1518 break;
1519 case DP_TRAIN_VOLTAGE_SWING_800:
1520 signal_levels |= DP_VOLTAGE_0_8;
1521 break;
1522 case DP_TRAIN_VOLTAGE_SWING_1200:
1523 signal_levels |= DP_VOLTAGE_1_2;
1524 break;
1525 }
3cf2efb1 1526 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1527 case DP_TRAIN_PRE_EMPHASIS_0:
1528 default:
1529 signal_levels |= DP_PRE_EMPHASIS_0;
1530 break;
1531 case DP_TRAIN_PRE_EMPHASIS_3_5:
1532 signal_levels |= DP_PRE_EMPHASIS_3_5;
1533 break;
1534 case DP_TRAIN_PRE_EMPHASIS_6:
1535 signal_levels |= DP_PRE_EMPHASIS_6;
1536 break;
1537 case DP_TRAIN_PRE_EMPHASIS_9_5:
1538 signal_levels |= DP_PRE_EMPHASIS_9_5;
1539 break;
1540 }
1541 return signal_levels;
1542}
1543
e3421a18
ZW		 1544/* Gen6's DP voltage swing and pre-emphasis control */
1545static uint32_t
1546intel_gen6_edp_signal_levels(uint8_t train_set)
1547{
3c5a62b5
YL		 1548 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1549 DP_TRAIN_PRE_EMPHASIS_MASK);
1550 switch (signal_levels) {
e3421a18 1551 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1552 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1553 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1554 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1555 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1556 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1557 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1558 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1559 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1560 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1561 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1562 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1563 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1564 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1565 default:
3c5a62b5
YL		 1566 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1567 "0x%x\n", signal_levels);
1568 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1569 }
1570}
1571
1a2eb460
KP		 1572/* Gen7's DP voltage swing and pre-emphasis control */
1573static uint32_t
1574intel_gen7_edp_signal_levels(uint8_t train_set)
1575{
1576 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1577 DP_TRAIN_PRE_EMPHASIS_MASK);
1578 switch (signal_levels) {
1579 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1580 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1581 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1582 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1583 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1584 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1585
1586 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1587 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1588 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1589 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1590
1591 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1592 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1593 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1594 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1595
1596 default:
1597 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1598 "0x%x\n", signal_levels);
1599 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1600 }
1601}
1602
a4fc5ed6
KP		 1603static uint8_t
1604intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1605 int lane)
1606{
a4fc5ed6 1607 int s = (lane & 1) * 4;
93f62dad 1608 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1609
1610 return (l >> s) & 0xf;
1611}
1612
1613/* Check for clock recovery is done on all channels */
1614static bool
1615intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1616{
1617 int lane;
1618 uint8_t lane_status;
1619
1620 for (lane = 0; lane < lane_count; lane++) {
1621 lane_status = intel_get_lane_status(link_status, lane);
1622 if ((lane_status & DP_LANE_CR_DONE) == 0)
1623 return false;
1624 }
1625 return true;
1626}
1627
1628/* Check to see if channel eq is done on all channels */
1629#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1630 DP_LANE_CHANNEL_EQ_DONE|\
1631 DP_LANE_SYMBOL_LOCKED)
1632static bool
93f62dad 1633intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1634{
1635 uint8_t lane_align;
1636 uint8_t lane_status;
1637 int lane;
1638
93f62dad 1639 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1640 DP_LANE_ALIGN_STATUS_UPDATED);
1641 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1642 return false;
33a34e4e 1643 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1644 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1645 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1646 return false;
1647 }
1648 return true;
1649}
1650
1651static bool
ea5b213a 1652intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1653 uint32_t dp_reg_value,
58e10eb9 1654 uint8_t dp_train_pat)
a4fc5ed6 1655{
4ef69c7a 1656 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1657 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1658 int ret;
1659
47ea7542
PZ		 1660 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1661 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1662
1663 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1664 case DP_TRAINING_PATTERN_DISABLE:
1665 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1666 break;
1667 case DP_TRAINING_PATTERN_1:
1668 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1669 break;
1670 case DP_TRAINING_PATTERN_2:
1671 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1672 break;
1673 case DP_TRAINING_PATTERN_3:
1674 DRM_ERROR("DP training pattern 3 not supported\n");
1675 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1676 break;
1677 }
1678
1679 } else {
1680 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1681
1682 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1683 case DP_TRAINING_PATTERN_DISABLE:
1684 dp_reg_value |= DP_LINK_TRAIN_OFF;
1685 break;
1686 case DP_TRAINING_PATTERN_1:
1687 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1688 break;
1689 case DP_TRAINING_PATTERN_2:
1690 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1691 break;
1692 case DP_TRAINING_PATTERN_3:
1693 DRM_ERROR("DP training pattern 3 not supported\n");
1694 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1695 break;
1696 }
1697 }
1698
ea5b213a
CW		 1699 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1700 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1701
ea5b213a 1702 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1703 DP_TRAINING_PATTERN_SET,
1704 dp_train_pat);
1705
47ea7542
PZ		 1706 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1707 DP_TRAINING_PATTERN_DISABLE) {
1708 ret = intel_dp_aux_native_write(intel_dp,
1709 DP_TRAINING_LANE0_SET,
1710 intel_dp->train_set,
1711 intel_dp->lane_count);
1712 if (ret != intel_dp->lane_count)
1713 return false;
1714 }
a4fc5ed6
KP		 1715
1716 return true;
1717}
1718
33a34e4e 1719/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1720static void
33a34e4e 1721intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1722{
4ef69c7a 1723 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 1724 int i;
1725 uint8_t voltage;
1726 bool clock_recovery = false;
cdb0e95b 1727 int voltage_tries, loop_tries;
ea5b213a 1728 uint32_t DP = intel_dp->DP;
a4fc5ed6 1729
3cf2efb1
CW		 1730 /* Write the link configuration data */
1731 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1732 intel_dp->link_configuration,
1733 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1734
1735 DP |= DP_PORT_EN;
1a2eb460 1736
33a34e4e 1737 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1738 voltage = 0xff;
cdb0e95b
KP		 1739 voltage_tries = 0;
1740 loop_tries = 0;
a4fc5ed6
KP		 1741 clock_recovery = false;
1742 for (;;) {
33a34e4e 1743 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1744 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1745 uint32_t signal_levels;
417e822d 1746
1a2eb460
KP		 1747
1748 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1749 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1750 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1751 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1752 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1753 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1754 } else {
93f62dad
KP		 1755 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1756 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1757 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1758 }
a4fc5ed6 1759
47ea7542 1760 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1761 DP_TRAINING_PATTERN_1 |
1762 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1763 break;
a4fc5ed6
KP		 1764 /* Set training pattern 1 */
1765
3cf2efb1 1766 udelay(100);
93f62dad
KP		 1767 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1768 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1769 break;
93f62dad 1770 }
a4fc5ed6 1771
93f62dad
KP		 1772 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1773 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1774 clock_recovery = true;
1775 break;
1776 }
1777
1778 /* Check to see if we've tried the max voltage */
1779 for (i = 0; i < intel_dp->lane_count; i++)
1780 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1781 break;
0d710688 1782 if (i == intel_dp->lane_count && voltage_tries == 5) {
cdb0e95b
KP		 1783 ++loop_tries;
1784 if (loop_tries == 5) {
1785 DRM_DEBUG_KMS("too many full retries, give up\n");
1786 break;
1787 }
1788 memset(intel_dp->train_set, 0, 4);
1789 voltage_tries = 0;
1790 continue;
1791 }
a4fc5ed6 1792
3cf2efb1
CW		 1793 /* Check to see if we've tried the same voltage 5 times */
1794 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1795 ++voltage_tries;
1796 if (voltage_tries == 5) {
1797 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1798 break;
cdb0e95b 1799 }
3cf2efb1 1800 } else
cdb0e95b 1801 voltage_tries = 0;
3cf2efb1 1802 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1803
3cf2efb1 1804 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1805 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1806 }
1807
33a34e4e
JB		 1808 intel_dp->DP = DP;
1809}
1810
1811static void
1812intel_dp_complete_link_train(struct intel_dp *intel_dp)
1813{
4ef69c7a 1814 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1815 bool channel_eq = false;
37f80975 1816 int tries, cr_tries;
33a34e4e
JB		 1817 uint32_t DP = intel_dp->DP;
1818
a4fc5ed6
KP		 1819 /* channel equalization */
1820 tries = 0;
37f80975 1821 cr_tries = 0;
a4fc5ed6
KP		 1822 channel_eq = false;
1823 for (;;) {
33a34e4e 1824 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1825 uint32_t signal_levels;
93f62dad 1826 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1827
37f80975
JB		 1828 if (cr_tries > 5) {
1829 DRM_ERROR("failed to train DP, aborting\n");
1830 intel_dp_link_down(intel_dp);
1831 break;
1832 }
1833
1a2eb460
KP		 1834 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1835 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1836 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1837 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1838 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1839 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1840 } else {
93f62dad 1841 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1842 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1843 }
1844
a4fc5ed6 1845 /* channel eq pattern */
47ea7542 1846 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1847 DP_TRAINING_PATTERN_2 |
1848 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1849 break;
1850
3cf2efb1 1851 udelay(400);
93f62dad 1852 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1853 break;
a4fc5ed6 1854
37f80975 1855 /* Make sure clock is still ok */
93f62dad 1856 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1857 intel_dp_start_link_train(intel_dp);
1858 cr_tries++;
1859 continue;
1860 }
1861
93f62dad 1862 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1863 channel_eq = true;
1864 break;
1865 }
a4fc5ed6 1866
37f80975
JB		 1867 /* Try 5 times, then try clock recovery if that fails */
1868 if (tries > 5) {
1869 intel_dp_link_down(intel_dp);
1870 intel_dp_start_link_train(intel_dp);
1871 tries = 0;
1872 cr_tries++;
1873 continue;
1874 }
a4fc5ed6 1875
3cf2efb1 1876 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1877 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1878 ++tries;
869184a6 1879 }
3cf2efb1 1880
47ea7542 1881 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1882}
1883
1884static void
ea5b213a 1885intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1886{
4ef69c7a 1887 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1888 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1889 uint32_t DP = intel_dp->DP;
a4fc5ed6 1890
1b39d6f3
CW		 1891 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1892 return;
1893
28c97730 1894 DRM_DEBUG_KMS("\n");
32f9d658 1895
cfcb0fc9 1896 if (is_edp(intel_dp)) {
32f9d658 1897 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1898 I915_WRITE(intel_dp->output_reg, DP);
1899 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1900 udelay(100);
1901 }
1902
1a2eb460 1903 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1904 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1905 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1906 } else {
1907 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1908 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1909 }
fe255d00 1910 POSTING_READ(intel_dp->output_reg);
5eb08b69 1911
fe255d00 1912 msleep(17);
5eb08b69 1913
417e822d 1914 if (is_edp(intel_dp)) {
1a2eb460 1915 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
417e822d
KP		 1916 DP |= DP_LINK_TRAIN_OFF_CPT;
1917 else
1918 DP |= DP_LINK_TRAIN_OFF;
1919 }
5bddd17f 1920
493a7081 1921 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1922 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1923 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1924
5bddd17f
EA		 1925 /* Hardware workaround: leaving our transcoder select
1926 * set to transcoder B while it's off will prevent the
1927 * corresponding HDMI output on transcoder A.
1928 *
1929 * Combine this with another hardware workaround:
1930 * transcoder select bit can only be cleared while the
1931 * port is enabled.
1932 */
1933 DP &= ~DP_PIPEB_SELECT;
1934 I915_WRITE(intel_dp->output_reg, DP);
1935
1936 /* Changes to enable or select take place the vblank
1937 * after being written.
1938 */
31acbcc4
CW		 1939 if (crtc == NULL) {
1940 /* We can arrive here never having been attached
1941 * to a CRTC, for instance, due to inheriting
1942 * random state from the BIOS.
1943 *
1944 * If the pipe is not running, play safe and
1945 * wait for the clocks to stabilise before
1946 * continuing.
1947 */
1948 POSTING_READ(intel_dp->output_reg);
1949 msleep(50);
1950 } else
1951 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1952 }
1953
832afda6 1954 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1955 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1956 POSTING_READ(intel_dp->output_reg);
f01eca2e 1957 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1958}
1959
26d61aad
KP		 1960static bool
1961intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1962{
92fd8fd1 1963 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
0206e353 1964 sizeof(intel_dp->dpcd)) &&
92fd8fd1 1965 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
26d61aad 1966 return true;
92fd8fd1
KP		 1967 }
1968
26d61aad 1969 return false;
92fd8fd1
KP		 1970}
1971
0d198328
AJ		 1972static void
1973intel_dp_probe_oui(struct intel_dp *intel_dp)
1974{
1975 u8 buf[3];
1976
1977 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1978 return;
1979
351cfc34
DV		 1980 ironlake_edp_panel_vdd_on(intel_dp);
1981
0d198328
AJ		 1982 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1983 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1984 buf[0], buf[1], buf[2]);
1985
1986 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1987 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1988 buf[0], buf[1], buf[2]);
351cfc34
DV		 1989
1990 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 1991}
1992
a60f0e38
JB		 1993static bool
1994intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1995{
1996 int ret;
1997
1998 ret = intel_dp_aux_native_read_retry(intel_dp,
1999 DP_DEVICE_SERVICE_IRQ_VECTOR,
2000 sink_irq_vector, 1);
2001 if (!ret)
2002 return false;
2003
2004 return true;
2005}
2006
2007static void
2008intel_dp_handle_test_request(struct intel_dp *intel_dp)
2009{
2010 /* NAK by default */
2011 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2012}
2013
a4fc5ed6
KP		 2014/*
2015 * According to DP spec
2016 * 5.1.2:
2017 * 1. Read DPCD
2018 * 2. Configure link according to Receiver Capabilities
2019 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2020 * 4. Check link status on receipt of hot-plug interrupt
2021 */
2022
2023static void
ea5b213a 2024intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2025{
a60f0e38 2026 u8 sink_irq_vector;
93f62dad 2027 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2028
24e804ba 2029 if (!intel_dp->base.connectors_active)
d2b996ac 2030 return;
59cd09e1 2031
24e804ba 2032 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2033 return;
2034
92fd8fd1 2035 /* Try to read receiver status if the link appears to be up */
93f62dad 2036 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2037 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2038 return;
2039 }
2040
92fd8fd1 2041 /* Now read the DPCD to see if it's actually running */
26d61aad 2042 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2043 intel_dp_link_down(intel_dp);
2044 return;
2045 }
2046
a60f0e38
JB		 2047 /* Try to read the source of the interrupt */
2048 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2049 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2050 /* Clear interrupt source */
2051 intel_dp_aux_native_write_1(intel_dp,
2052 DP_DEVICE_SERVICE_IRQ_VECTOR,
2053 sink_irq_vector);
2054
2055 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2056 intel_dp_handle_test_request(intel_dp);
2057 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2058 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2059 }
2060
93f62dad 2061 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2062 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2063 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2064 intel_dp_start_link_train(intel_dp);
2065 intel_dp_complete_link_train(intel_dp);
2066 }
a4fc5ed6 2067}
a4fc5ed6 2068
71ba9000 2069static enum drm_connector_status
26d61aad 2070intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2071{
26d61aad
KP		 2072 if (intel_dp_get_dpcd(intel_dp))
2073 return connector_status_connected;
2074 return connector_status_disconnected;
71ba9000
AJ		 2075}
2076
5eb08b69 2077static enum drm_connector_status
a9756bb5 2078ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2079{
5eb08b69
ZW		 2080 enum drm_connector_status status;
2081
fe16d949
CW		 2082 /* Can't disconnect eDP, but you can close the lid... */
2083 if (is_edp(intel_dp)) {
2084 status = intel_panel_detect(intel_dp->base.base.dev);
2085 if (status == connector_status_unknown)
2086 status = connector_status_connected;
2087 return status;
2088 }
01cb9ea6 2089
26d61aad 2090 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2091}
2092
a4fc5ed6 2093static enum drm_connector_status
a9756bb5 2094g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2095{
4ef69c7a 2096 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2097 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2098 uint32_t bit;
5eb08b69 2099
ea5b213a 2100 switch (intel_dp->output_reg) {
a4fc5ed6 2101 case DP_B:
10f76a38 2102 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2103 break;
2104 case DP_C:
10f76a38 2105 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2106 break;
2107 case DP_D:
10f76a38 2108 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2109 break;
2110 default:
2111 return connector_status_unknown;
2112 }
2113
10f76a38 2114 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2115 return connector_status_disconnected;
2116
26d61aad 2117 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2118}
2119
8c241fef
KP		 2120static struct edid *
2121intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2122{
2123 struct intel_dp *intel_dp = intel_attached_dp(connector);
2124 struct edid *edid;
d6f24d0f
JB		 2125 int size;
2126
2127 if (is_edp(intel_dp)) {
2128 if (!intel_dp->edid)
2129 return NULL;
2130
2131 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2132 edid = kmalloc(size, GFP_KERNEL);
2133 if (!edid)
2134 return NULL;
2135
2136 memcpy(edid, intel_dp->edid, size);
2137 return edid;
2138 }
8c241fef 2139
8c241fef 2140 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2141 return edid;
2142}
2143
2144static int
2145intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2146{
2147 struct intel_dp *intel_dp = intel_attached_dp(connector);
2148 int ret;
2149
d6f24d0f
JB		 2150 if (is_edp(intel_dp)) {
2151 drm_mode_connector_update_edid_property(connector,
2152 intel_dp->edid);
2153 ret = drm_add_edid_modes(connector, intel_dp->edid);
2154 drm_edid_to_eld(connector,
2155 intel_dp->edid);
d6f24d0f
JB		 2156 return intel_dp->edid_mode_count;
2157 }
2158
8c241fef 2159 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2160 return ret;
2161}
2162
2163
a9756bb5
ZW		 2164/**
2165 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2166 *
2167 * \return true if DP port is connected.
2168 * \return false if DP port is disconnected.
2169 */
2170static enum drm_connector_status
2171intel_dp_detect(struct drm_connector *connector, bool force)
2172{
2173 struct intel_dp *intel_dp = intel_attached_dp(connector);
2174 struct drm_device *dev = intel_dp->base.base.dev;
2175 enum drm_connector_status status;
2176 struct edid *edid = NULL;
2177
2178 intel_dp->has_audio = false;
2179
2180 if (HAS_PCH_SPLIT(dev))
2181 status = ironlake_dp_detect(intel_dp);
2182 else
2183 status = g4x_dp_detect(intel_dp);
1b9be9d0 2184
ac66ae83
AJ		 2185 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2186 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2187 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2188 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2189
a9756bb5
ZW		 2190 if (status != connector_status_connected)
2191 return status;
2192
0d198328
AJ		 2193 intel_dp_probe_oui(intel_dp);
2194
c3e5f67b
DV		 2195 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2196 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2197 } else {
8c241fef 2198 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2199 if (edid) {
2200 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2201 kfree(edid);
2202 }
a9756bb5
ZW		 2203 }
2204
2205 return connector_status_connected;
a4fc5ed6
KP		 2206}
2207
2208static int intel_dp_get_modes(struct drm_connector *connector)
2209{
df0e9248 2210 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2211 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 int ret;
a4fc5ed6
KP		 2214
2215 /* We should parse the EDID data and find out if it has an audio sink
2216 */
2217
8c241fef 2218 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2219 if (ret) {
d15456de 2220 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2221 struct drm_display_mode *newmode;
2222 list_for_each_entry(newmode, &connector->probed_modes,
2223 head) {
d15456de
KP		 2224 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2225 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2226 drm_mode_duplicate(dev, newmode);
2227 break;
2228 }
2229 }
2230 }
32f9d658 2231 return ret;
b9efc480 2232 }
32f9d658
ZW		 2233
2234 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2235 if (is_edp(intel_dp)) {
47f0eb22 2236 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2237 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2238 intel_dp->panel_fixed_mode =
47f0eb22 2239 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2240 if (intel_dp->panel_fixed_mode) {
2241 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2242 DRM_MODE_TYPE_PREFERRED;
2243 }
2244 }
d15456de 2245 if (intel_dp->panel_fixed_mode) {
32f9d658 2246 struct drm_display_mode *mode;
d15456de 2247 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2248 drm_mode_probed_add(connector, mode);
2249 return 1;
2250 }
2251 }
2252 return 0;
a4fc5ed6
KP		 2253}
2254
1aad7ac0
CW		 2255static bool
2256intel_dp_detect_audio(struct drm_connector *connector)
2257{
2258 struct intel_dp *intel_dp = intel_attached_dp(connector);
2259 struct edid *edid;
2260 bool has_audio = false;
2261
8c241fef 2262 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2263 if (edid) {
2264 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2265 kfree(edid);
2266 }
2267
2268 return has_audio;
2269}
2270
f684960e
CW		 2271static int
2272intel_dp_set_property(struct drm_connector *connector,
2273 struct drm_property *property,
2274 uint64_t val)
2275{
e953fd7b 2276 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2277 struct intel_dp *intel_dp = intel_attached_dp(connector);
2278 int ret;
2279
2280 ret = drm_connector_property_set_value(connector, property, val);
2281 if (ret)
2282 return ret;
2283
3f43c48d 2284 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2285 int i = val;
2286 bool has_audio;
2287
2288 if (i == intel_dp->force_audio)
f684960e
CW		 2289 return 0;
2290
1aad7ac0 2291 intel_dp->force_audio = i;
f684960e 2292
c3e5f67b 2293 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2294 has_audio = intel_dp_detect_audio(connector);
2295 else
c3e5f67b 2296 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2297
2298 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2299 return 0;
2300
1aad7ac0 2301 intel_dp->has_audio = has_audio;
f684960e
CW		 2302 goto done;
2303 }
2304
e953fd7b
CW		 2305 if (property == dev_priv->broadcast_rgb_property) {
2306 if (val == !!intel_dp->color_range)
2307 return 0;
2308
2309 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2310 goto done;
2311 }
2312
f684960e
CW		 2313 return -EINVAL;
2314
2315done:
2316 if (intel_dp->base.base.crtc) {
2317 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2318 intel_set_mode(crtc, &crtc->mode,
2319 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2320 }
2321
2322 return 0;
2323}
2324
a4fc5ed6 2325static void
0206e353 2326intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2327{
aaa6fd2a
MG		 2328 struct drm_device *dev = connector->dev;
2329
2330 if (intel_dpd_is_edp(dev))
2331 intel_panel_destroy_backlight(dev);
2332
a4fc5ed6
KP		 2333 drm_sysfs_connector_remove(connector);
2334 drm_connector_cleanup(connector);
55f78c43 2335 kfree(connector);
a4fc5ed6
KP		 2336}
2337
24d05927
DV		 2338static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2339{
2340 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2341
2342 i2c_del_adapter(&intel_dp->adapter);
2343 drm_encoder_cleanup(encoder);
bd943159 2344 if (is_edp(intel_dp)) {
d6f24d0f 2345 kfree(intel_dp->edid);
bd943159
KP		 2346 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2347 ironlake_panel_vdd_off_sync(intel_dp);
2348 }
24d05927
DV		 2349 kfree(intel_dp);
2350}
2351
a4fc5ed6 2352static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2353 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2354 .mode_set = intel_dp_mode_set,
1f703855 2355 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2356};
2357
2358static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2359 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2360 .detect = intel_dp_detect,
2361 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2362 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2363 .destroy = intel_dp_destroy,
2364};
2365
2366static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2367 .get_modes = intel_dp_get_modes,
2368 .mode_valid = intel_dp_mode_valid,
df0e9248 2369 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2370};
2371
a4fc5ed6 2372static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2373 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2374};
2375
995b6762 2376static void
21d40d37 2377intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2378{
ea5b213a 2379 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2380
885a5014 2381 intel_dp_check_link_status(intel_dp);
c8110e52 2382}
6207937d 2383
e3421a18
ZW		 2384/* Return which DP Port should be selected for Transcoder DP control */
2385int
0206e353 2386intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2387{
2388 struct drm_device *dev = crtc->dev;
6c2b7c12 2389 struct intel_encoder *encoder;
e3421a18 2390
6c2b7c12
DV		 2391 for_each_encoder_on_crtc(dev, crtc, encoder) {
2392 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2393
417e822d
KP		 2394 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2395 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2396 return intel_dp->output_reg;
e3421a18 2397 }
ea5b213a 2398
e3421a18
ZW		 2399 return -1;
2400}
2401
36e83a18 2402/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2403bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2404{
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 struct child_device_config *p_child;
2407 int i;
2408
2409 if (!dev_priv->child_dev_num)
2410 return false;
2411
2412 for (i = 0; i < dev_priv->child_dev_num; i++) {
2413 p_child = dev_priv->child_dev + i;
2414
2415 if (p_child->dvo_port == PORT_IDPD &&
2416 p_child->device_type == DEVICE_TYPE_eDP)
2417 return true;
2418 }
2419 return false;
2420}
2421
f684960e
CW		 2422static void
2423intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2424{
3f43c48d 2425 intel_attach_force_audio_property(connector);
e953fd7b 2426 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2427}
2428
a4fc5ed6 2429void
ab9d7c30 2430intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2431{
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 struct drm_connector *connector;
ea5b213a 2434 struct intel_dp *intel_dp;
21d40d37 2435 struct intel_encoder *intel_encoder;
55f78c43 2436 struct intel_connector *intel_connector;
5eb08b69 2437 const char *name = NULL;
b329530c 2438 int type;
a4fc5ed6 2439
ea5b213a
CW		 2440 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2441 if (!intel_dp)
a4fc5ed6
KP		 2442 return;
2443
3d3dc149 2444 intel_dp->output_reg = output_reg;
ab9d7c30 2445 intel_dp->port = port;
3d3dc149 2446
55f78c43
ZW		 2447 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2448 if (!intel_connector) {
ea5b213a 2449 kfree(intel_dp);
55f78c43
ZW		 2450 return;
2451 }
ea5b213a 2452 intel_encoder = &intel_dp->base;
55f78c43 2453
ea5b213a 2454 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2455 if (intel_dpd_is_edp(dev))
ea5b213a 2456 intel_dp->is_pch_edp = true;
b329530c 2457
cfcb0fc9 2458 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2459 type = DRM_MODE_CONNECTOR_eDP;
2460 intel_encoder->type = INTEL_OUTPUT_EDP;
2461 } else {
2462 type = DRM_MODE_CONNECTOR_DisplayPort;
2463 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2464 }
2465
55f78c43 2466 connector = &intel_connector->base;
b329530c 2467 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2468 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2469
eb1f8e4f
DA		 2470 connector->polled = DRM_CONNECTOR_POLL_HPD;
2471
66a9278e 2472 intel_encoder->cloneable = false;
f8aed700 2473
66a9278e
DV		 2474 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2475 ironlake_panel_vdd_work);
6251ec0a 2476
27f8227b 2477 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2478
a4fc5ed6
KP		 2479 connector->interlace_allowed = true;
2480 connector->doublescan_allowed = 0;
2481
4ef69c7a 2482 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2483 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2484 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2485
df0e9248 2486 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2487 drm_sysfs_connector_add(connector);
2488
e8cb4558 2489 intel_encoder->enable = intel_enable_dp;
2bd2ad64 2490 intel_encoder->pre_enable = intel_pre_enable_dp;
e8cb4558 2491 intel_encoder->disable = intel_disable_dp;
2bd2ad64 2492 intel_encoder->post_disable = intel_post_disable_dp;
19d8fe15
DV		 2493 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2494 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2495
a4fc5ed6 2496 /* Set up the DDC bus. */
ab9d7c30
PZ		 2497 switch (port) {
2498 case PORT_A:
2499 name = "DPDDC-A";
2500 break;
2501 case PORT_B:
2502 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2503 name = "DPDDC-B";
2504 break;
2505 case PORT_C:
2506 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2507 name = "DPDDC-C";
2508 break;
2509 case PORT_D:
2510 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2511 name = "DPDDC-D";
2512 break;
2513 default:
2514 WARN(1, "Invalid port %c\n", port_name(port));
2515 break;
5eb08b69
ZW		 2516 }
2517
d6f24d0f
JB		 2518 intel_dp_i2c_init(intel_dp, intel_connector, name);
2519
89667383
JB		 2520 /* Cache some DPCD data in the eDP case */
2521 if (is_edp(intel_dp)) {
59f3e272 2522 bool ret;
f01eca2e
KP		 2523 struct edp_power_seq cur, vbt;
2524 u32 pp_on, pp_off, pp_div;
d6f24d0f 2525 struct edid *edid;
5d613501
JB		 2526
2527 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2528 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2529 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2530
bfa3384a
JB		 2531 if (!pp_on || !pp_off || !pp_div) {
2532 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2533 intel_dp_encoder_destroy(&intel_dp->base.base);
2534 intel_dp_destroy(&intel_connector->base);
2535 return;
2536 }
2537
f01eca2e
KP		 2538 /* Pull timing values out of registers */
2539 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2540 PANEL_POWER_UP_DELAY_SHIFT;
2541
2542 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2543 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2544
f01eca2e
KP		 2545 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2546 PANEL_LIGHT_OFF_DELAY_SHIFT;
2547
2548 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2549 PANEL_POWER_DOWN_DELAY_SHIFT;
2550
2551 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2552 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2553
2554 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2555 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2556
2557 vbt = dev_priv->edp.pps;
2558
2559 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2560 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2561
2562#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2563
2564 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2565 intel_dp->backlight_on_delay = get_delay(t8);
2566 intel_dp->backlight_off_delay = get_delay(t9);
2567 intel_dp->panel_power_down_delay = get_delay(t10);
2568 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2569
2570 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2571 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2572 intel_dp->panel_power_cycle_delay);
2573
2574 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2575 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5d613501
JB		 2576
2577 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2578 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2579 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2580
59f3e272 2581 if (ret) {
7183dc29
JB		 2582 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2583 dev_priv->no_aux_handshake =
2584 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2585 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2586 } else {
3d3dc149 2587 /* if this fails, presume the device is a ghost */
48898b03 2588 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2589 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2590 intel_dp_destroy(&intel_connector->base);
3d3dc149 2591 return;
89667383 2592 }
89667383 2593
d6f24d0f
JB		 2594 ironlake_edp_panel_vdd_on(intel_dp);
2595 edid = drm_get_edid(connector, &intel_dp->adapter);
2596 if (edid) {
2597 drm_mode_connector_update_edid_property(connector,
2598 edid);
2599 intel_dp->edid_mode_count =
2600 drm_add_edid_modes(connector, edid);
2601 drm_edid_to_eld(connector, edid);
2602 intel_dp->edid = edid;
2603 }
2604 ironlake_edp_panel_vdd_off(intel_dp, false);
2605 }
552fb0b7 2606
21d40d37 2607 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2608
4d926461 2609 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2610 dev_priv->int_edp_connector = connector;
2611 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2612 }
2613
f684960e
CW		 2614 intel_dp_add_properties(intel_dp, connector);
2615
a4fc5ed6
KP		 2616 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2617 * 0xd. Failure to do so will result in spurious interrupts being
2618 * generated on the port when a cable is not attached.
2619 */
2620 if (IS_G4X(dev) && !IS_GM45(dev)) {
2621 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2622 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2623 }
2624}
Linux 6.x block layer and io_uring tree(s)