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drm/i915: add port field to intel_digital_port
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d
PZ		 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
30add22d
PZ		 84}
85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
32f9d658 112void
0206e353 113intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 114 int *lane_num, int *link_bw)
32f9d658 115{
fa90ecef 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
32f9d658 117
ea5b213a 118 *lane_num = intel_dp->lane_count;
3b5c662e 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
fa90ecef 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
dd06f90e 127 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 128
dd06f90e
JN		 129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 131 else
132 return mode->clock;
133}
134
a4fc5ed6 135static int
ea5b213a 136intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 137{
7183dc29 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
151static int
152intel_dp_link_clock(uint8_t link_bw)
153{
154 if (link_bw == DP_LINK_BW_2_7)
155 return 270000;
156 else
157 return 162000;
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c4867936
DV		 189static bool
190intel_dp_adjust_dithering(struct intel_dp *intel_dp,
191 struct drm_display_mode *mode,
cb1793ce 192 bool adjust_mode)
c4867936
DV		 193{
194 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
397fe157 195 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 196 int max_rate, mode_rate;
197
198 mode_rate = intel_dp_link_required(mode->clock, 24);
199 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
200
201 if (mode_rate > max_rate) {
202 mode_rate = intel_dp_link_required(mode->clock, 18);
203 if (mode_rate > max_rate)
204 return false;
205
cb1793ce
DV		 206 if (adjust_mode)
207 mode->private_flags
c4867936
DV		 208 |= INTEL_MODE_DP_FORCE_6BPC;
209
210 return true;
211 }
212
213 return true;
214}
215
a4fc5ed6
KP		 216static int
217intel_dp_mode_valid(struct drm_connector *connector,
218 struct drm_display_mode *mode)
219{
df0e9248 220 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 221 struct intel_connector *intel_connector = to_intel_connector(connector);
222 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 223
dd06f90e
JN		 224 if (is_edp(intel_dp) && fixed_mode) {
225 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 226 return MODE_PANEL;
227
dd06f90e 228 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 229 return MODE_PANEL;
230 }
231
cb1793ce 232 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 233 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 234
235 if (mode->clock < 10000)
236 return MODE_CLOCK_LOW;
237
0af78a2b
DV		 238 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
239 return MODE_H_ILLEGAL;
240
a4fc5ed6
KP		 241 return MODE_OK;
242}
243
244static uint32_t
245pack_aux(uint8_t *src, int src_bytes)
246{
247 int i;
248 uint32_t v = 0;
249
250 if (src_bytes > 4)
251 src_bytes = 4;
252 for (i = 0; i < src_bytes; i++)
253 v |= ((uint32_t) src[i]) << ((3-i) * 8);
254 return v;
255}
256
257static void
258unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
259{
260 int i;
261 if (dst_bytes > 4)
262 dst_bytes = 4;
263 for (i = 0; i < dst_bytes; i++)
264 dst[i] = src >> ((3-i) * 8);
265}
266
fb0f8fbf
KP		 267/* hrawclock is 1/4 the FSB frequency */
268static int
269intel_hrawclk(struct drm_device *dev)
270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 uint32_t clkcfg;
273
9473c8f4
VP		 274 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
275 if (IS_VALLEYVIEW(dev))
276 return 200;
277
fb0f8fbf
KP		 278 clkcfg = I915_READ(CLKCFG);
279 switch (clkcfg & CLKCFG_FSB_MASK) {
280 case CLKCFG_FSB_400:
281 return 100;
282 case CLKCFG_FSB_533:
283 return 133;
284 case CLKCFG_FSB_667:
285 return 166;
286 case CLKCFG_FSB_800:
287 return 200;
288 case CLKCFG_FSB_1067:
289 return 266;
290 case CLKCFG_FSB_1333:
291 return 333;
292 /* these two are just a guess; one of them might be right */
293 case CLKCFG_FSB_1600:
294 case CLKCFG_FSB_1600_ALT:
295 return 400;
296 default:
297 return 133;
298 }
299}
300
ebf33b18
KP		 301static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
302{
30add22d 303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
307}
308
309static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
310{
30add22d 311 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
315}
316
9b984dae
KP		 317static void
318intel_dp_check_edp(struct intel_dp *intel_dp)
319{
30add22d 320 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 321 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 322
9b984dae
KP		 323 if (!is_edp(intel_dp))
324 return;
ebf33b18 325 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 326 WARN(1, "eDP powered off while attempting aux channel communication.\n");
327 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 328 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 329 I915_READ(PCH_PP_CONTROL));
330 }
331}
332
a4fc5ed6 333static int
ea5b213a 334intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 335 uint8_t *send, int send_bytes,
336 uint8_t *recv, int recv_size)
337{
ea5b213a 338 uint32_t output_reg = intel_dp->output_reg;
174edf1f
PZ		 339 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
340 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6
KP		 341 struct drm_i915_private *dev_priv = dev->dev_private;
342 uint32_t ch_ctl = output_reg + 0x10;
343 uint32_t ch_data = ch_ctl + 4;
344 int i;
345 int recv_bytes;
a4fc5ed6 346 uint32_t status;
fb0f8fbf 347 uint32_t aux_clock_divider;
6b4e0a93 348 int try, precharge;
a4fc5ed6 349
750eb99e 350 if (IS_HASWELL(dev)) {
174edf1f 351 switch (intel_dig_port->port) {
750eb99e
PZ		 352 case PORT_A:
353 ch_ctl = DPA_AUX_CH_CTL;
354 ch_data = DPA_AUX_CH_DATA1;
355 break;
356 case PORT_B:
357 ch_ctl = PCH_DPB_AUX_CH_CTL;
358 ch_data = PCH_DPB_AUX_CH_DATA1;
359 break;
360 case PORT_C:
361 ch_ctl = PCH_DPC_AUX_CH_CTL;
362 ch_data = PCH_DPC_AUX_CH_DATA1;
363 break;
364 case PORT_D:
365 ch_ctl = PCH_DPD_AUX_CH_CTL;
366 ch_data = PCH_DPD_AUX_CH_DATA1;
367 break;
368 default:
369 BUG();
370 }
371 }
372
9b984dae 373 intel_dp_check_edp(intel_dp);
a4fc5ed6 374 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 375 * and would like to run at 2MHz. So, take the
376 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 377 *
378 * Note that PCH attached eDP panels should use a 125MHz input
379 * clock divider.
a4fc5ed6 380 */
1c95822a 381 if (is_cpu_edp(intel_dp)) {
b8fc2f6a
PZ		 382 if (IS_HASWELL(dev))
383 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
384 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 385 aux_clock_divider = 100;
386 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 387 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 388 else
389 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
390 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 391 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 392 else
393 aux_clock_divider = intel_hrawclk(dev) / 2;
394
6b4e0a93
DV		 395 if (IS_GEN6(dev))
396 precharge = 3;
397 else
398 precharge = 5;
399
11bee43e
JB		 400 /* Try to wait for any previous AUX channel activity */
401 for (try = 0; try < 3; try++) {
402 status = I915_READ(ch_ctl);
403 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
404 break;
405 msleep(1);
406 }
407
408 if (try == 3) {
409 WARN(1, "dp_aux_ch not started status 0x%08x\n",
410 I915_READ(ch_ctl));
4f7f7b7e
CW		 411 return -EBUSY;
412 }
413
fb0f8fbf
KP		 414 /* Must try at least 3 times according to DP spec */
415 for (try = 0; try < 5; try++) {
416 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 417 for (i = 0; i < send_bytes; i += 4)
418 I915_WRITE(ch_data + i,
419 pack_aux(send + i, send_bytes - i));
0206e353 420
fb0f8fbf 421 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 422 I915_WRITE(ch_ctl,
423 DP_AUX_CH_CTL_SEND_BUSY |
424 DP_AUX_CH_CTL_TIME_OUT_400us |
425 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
426 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
427 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
428 DP_AUX_CH_CTL_DONE |
429 DP_AUX_CH_CTL_TIME_OUT_ERROR |
430 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 431 for (;;) {
fb0f8fbf
KP		 432 status = I915_READ(ch_ctl);
433 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
434 break;
4f7f7b7e 435 udelay(100);
fb0f8fbf 436 }
0206e353 437
fb0f8fbf 438 /* Clear done status and any errors */
4f7f7b7e
CW		 439 I915_WRITE(ch_ctl,
440 status |
441 DP_AUX_CH_CTL_DONE |
442 DP_AUX_CH_CTL_TIME_OUT_ERROR |
443 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 444
445 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
446 DP_AUX_CH_CTL_RECEIVE_ERROR))
447 continue;
4f7f7b7e 448 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 449 break;
450 }
451
a4fc5ed6 452 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 453 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 454 return -EBUSY;
a4fc5ed6
KP		 455 }
456
457 /* Check for timeout or receive error.
458 * Timeouts occur when the sink is not connected
459 */
a5b3da54 460 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 461 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 462 return -EIO;
463 }
1ae8c0a5
KP		 464
465 /* Timeouts occur when the device isn't connected, so they're
466 * "normal" -- don't fill the kernel log with these */
a5b3da54 467 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 468 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 469 return -ETIMEDOUT;
a4fc5ed6
KP		 470 }
471
472 /* Unload any bytes sent back from the other side */
473 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
474 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 475 if (recv_bytes > recv_size)
476 recv_bytes = recv_size;
0206e353 477
4f7f7b7e
CW		 478 for (i = 0; i < recv_bytes; i += 4)
479 unpack_aux(I915_READ(ch_data + i),
480 recv + i, recv_bytes - i);
a4fc5ed6
KP		 481
482 return recv_bytes;
483}
484
485/* Write data to the aux channel in native mode */
486static int
ea5b213a 487intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 488 uint16_t address, uint8_t *send, int send_bytes)
489{
490 int ret;
491 uint8_t msg[20];
492 int msg_bytes;
493 uint8_t ack;
494
9b984dae 495 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 496 if (send_bytes > 16)
497 return -1;
498 msg[0] = AUX_NATIVE_WRITE << 4;
499 msg[1] = address >> 8;
eebc863e 500 msg[2] = address & 0xff;
a4fc5ed6
KP		 501 msg[3] = send_bytes - 1;
502 memcpy(&msg[4], send, send_bytes);
503 msg_bytes = send_bytes + 4;
504 for (;;) {
ea5b213a 505 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 506 if (ret < 0)
507 return ret;
508 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
509 break;
510 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
511 udelay(100);
512 else
a5b3da54 513 return -EIO;
a4fc5ed6
KP		 514 }
515 return send_bytes;
516}
517
518/* Write a single byte to the aux channel in native mode */
519static int
ea5b213a 520intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 521 uint16_t address, uint8_t byte)
522{
ea5b213a 523 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 524}
525
526/* read bytes from a native aux channel */
527static int
ea5b213a 528intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 529 uint16_t address, uint8_t *recv, int recv_bytes)
530{
531 uint8_t msg[4];
532 int msg_bytes;
533 uint8_t reply[20];
534 int reply_bytes;
535 uint8_t ack;
536 int ret;
537
9b984dae 538 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 539 msg[0] = AUX_NATIVE_READ << 4;
540 msg[1] = address >> 8;
541 msg[2] = address & 0xff;
542 msg[3] = recv_bytes - 1;
543
544 msg_bytes = 4;
545 reply_bytes = recv_bytes + 1;
546
547 for (;;) {
ea5b213a 548 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 549 reply, reply_bytes);
a5b3da54
KP		 550 if (ret == 0)
551 return -EPROTO;
552 if (ret < 0)
a4fc5ed6
KP		 553 return ret;
554 ack = reply[0];
555 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
556 memcpy(recv, reply + 1, ret - 1);
557 return ret - 1;
558 }
559 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
560 udelay(100);
561 else
a5b3da54 562 return -EIO;
a4fc5ed6
KP		 563 }
564}
565
566static int
ab2c0672
DA		 567intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
568 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 569{
ab2c0672 570 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 571 struct intel_dp *intel_dp = container_of(adapter,
572 struct intel_dp,
573 adapter);
ab2c0672
DA		 574 uint16_t address = algo_data->address;
575 uint8_t msg[5];
576 uint8_t reply[2];
8316f337 577 unsigned retry;
ab2c0672
DA		 578 int msg_bytes;
579 int reply_bytes;
580 int ret;
581
9b984dae 582 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 583 /* Set up the command byte */
584 if (mode & MODE_I2C_READ)
585 msg[0] = AUX_I2C_READ << 4;
586 else
587 msg[0] = AUX_I2C_WRITE << 4;
588
589 if (!(mode & MODE_I2C_STOP))
590 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 591
ab2c0672
DA		 592 msg[1] = address >> 8;
593 msg[2] = address;
594
595 switch (mode) {
596 case MODE_I2C_WRITE:
597 msg[3] = 0;
598 msg[4] = write_byte;
599 msg_bytes = 5;
600 reply_bytes = 1;
601 break;
602 case MODE_I2C_READ:
603 msg[3] = 0;
604 msg_bytes = 4;
605 reply_bytes = 2;
606 break;
607 default:
608 msg_bytes = 3;
609 reply_bytes = 1;
610 break;
611 }
612
8316f337
DF		 613 for (retry = 0; retry < 5; retry++) {
614 ret = intel_dp_aux_ch(intel_dp,
615 msg, msg_bytes,
616 reply, reply_bytes);
ab2c0672 617 if (ret < 0) {
3ff99164 618 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 619 return ret;
620 }
8316f337
DF		 621
622 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
623 case AUX_NATIVE_REPLY_ACK:
624 /* I2C-over-AUX Reply field is only valid
625 * when paired with AUX ACK.
626 */
627 break;
628 case AUX_NATIVE_REPLY_NACK:
629 DRM_DEBUG_KMS("aux_ch native nack\n");
630 return -EREMOTEIO;
631 case AUX_NATIVE_REPLY_DEFER:
632 udelay(100);
633 continue;
634 default:
635 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
636 reply[0]);
637 return -EREMOTEIO;
638 }
639
ab2c0672
DA		 640 switch (reply[0] & AUX_I2C_REPLY_MASK) {
641 case AUX_I2C_REPLY_ACK:
642 if (mode == MODE_I2C_READ) {
643 *read_byte = reply[1];
644 }
645 return reply_bytes - 1;
646 case AUX_I2C_REPLY_NACK:
8316f337 647 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 648 return -EREMOTEIO;
649 case AUX_I2C_REPLY_DEFER:
8316f337 650 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 651 udelay(100);
652 break;
653 default:
8316f337 654 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 655 return -EREMOTEIO;
656 }
657 }
8316f337
DF		 658
659 DRM_ERROR("too many retries, giving up\n");
660 return -EREMOTEIO;
a4fc5ed6
KP		 661}
662
663static int
ea5b213a 664intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 665 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 666{
0b5c541b
KP		 667 int ret;
668
d54e9d28 669 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 670 intel_dp->algo.running = false;
671 intel_dp->algo.address = 0;
672 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
673
0206e353 674 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 675 intel_dp->adapter.owner = THIS_MODULE;
676 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 677 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 678 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
679 intel_dp->adapter.algo_data = &intel_dp->algo;
680 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
681
0b5c541b
KP		 682 ironlake_edp_panel_vdd_on(intel_dp);
683 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 684 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 685 return ret;
a4fc5ed6
KP		 686}
687
688static bool
e811f5ae
LP		 689intel_dp_mode_fixup(struct drm_encoder *encoder,
690 const struct drm_display_mode *mode,
a4fc5ed6
KP		 691 struct drm_display_mode *adjusted_mode)
692{
0d3a1bee 693 struct drm_device *dev = encoder->dev;
ea5b213a 694 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 695 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 696 int lane_count, clock;
397fe157 697 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 698 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 699 int bpp, mode_rate;
a4fc5ed6
KP		 700 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
701
dd06f90e
JN		 702 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
703 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
704 adjusted_mode);
53b41837
YN		 705 intel_pch_panel_fitting(dev,
706 intel_connector->panel.fitting_mode,
1d8e1c75 707 mode, adjusted_mode);
0d3a1bee
ZY		 708 }
709
cb1793ce 710 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 711 return false;
712
083f9560
DV		 713 DRM_DEBUG_KMS("DP link computation with max lane count %i "
714 "max bw %02x pixel clock %iKHz\n",
71244653 715 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 716
cb1793ce 717 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 718 return false;
719
720 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 721 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 722
2514bc51
JB		 723 for (clock = 0; clock <= max_clock; clock++) {
724 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 725 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 726
083f9560 727 if (mode_rate <= link_avail) {
ea5b213a
CW		 728 intel_dp->link_bw = bws[clock];
729 intel_dp->lane_count = lane_count;
730 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 731 DRM_DEBUG_KMS("DP link bw %02x lane "
732 "count %d clock %d bpp %d\n",
ea5b213a 733 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 734 adjusted_mode->clock, bpp);
735 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
736 mode_rate, link_avail);
a4fc5ed6
KP		 737 return true;
738 }
739 }
740 }
fe27d53e 741
a4fc5ed6
KP		 742 return false;
743}
744
745struct intel_dp_m_n {
746 uint32_t tu;
747 uint32_t gmch_m;
748 uint32_t gmch_n;
749 uint32_t link_m;
750 uint32_t link_n;
751};
752
753static void
754intel_reduce_ratio(uint32_t *num, uint32_t *den)
755{
756 while (*num > 0xffffff || *den > 0xffffff) {
757 *num >>= 1;
758 *den >>= 1;
759 }
760}
761
762static void
36e83a18 763intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 764 int nlanes,
765 int pixel_clock,
766 int link_clock,
767 struct intel_dp_m_n *m_n)
768{
769 m_n->tu = 64;
36e83a18 770 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 771 m_n->gmch_n = link_clock * nlanes;
772 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
773 m_n->link_m = pixel_clock;
774 m_n->link_n = link_clock;
775 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
776}
777
778void
779intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
780 struct drm_display_mode *adjusted_mode)
781{
782 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 783 struct intel_encoder *intel_encoder;
784 struct intel_dp *intel_dp;
a4fc5ed6
KP		 785 struct drm_i915_private *dev_priv = dev->dev_private;
786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 787 int lane_count = 4;
a4fc5ed6 788 struct intel_dp_m_n m_n;
9db4a9c7 789 int pipe = intel_crtc->pipe;
afe2fcf5 790 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 791
792 /*
21d40d37 793 * Find the lane count in the intel_encoder private
a4fc5ed6 794 */
fa90ecef
PZ		 795 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
796 intel_dp = enc_to_intel_dp(&intel_encoder->base);
a4fc5ed6 797
fa90ecef
PZ		 798 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
799 intel_encoder->type == INTEL_OUTPUT_EDP)
9a10f401 800 {
ea5b213a 801 lane_count = intel_dp->lane_count;
51190667 802 break;
a4fc5ed6
KP		 803 }
804 }
805
806 /*
807 * Compute the GMCH and Link ratios. The '3' here is
808 * the number of bytes_per_pixel post-LUT, which we always
809 * set up for 8-bits of R/G/B, or 3 bytes total.
810 */
858fa035 811 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 812 mode->clock, adjusted_mode->clock, &m_n);
813
1eb8dfec 814 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 815 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
816 TU_SIZE(m_n.tu) | m_n.gmch_m);
817 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
818 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
819 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 820 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 821 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 822 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
823 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
824 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 825 } else if (IS_VALLEYVIEW(dev)) {
826 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
827 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
828 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
829 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 830 } else {
9db4a9c7 831 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 832 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 833 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
834 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
835 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 836 }
837}
838
247d89f6
PZ		 839void intel_dp_init_link_config(struct intel_dp *intel_dp)
840{
841 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
842 intel_dp->link_configuration[0] = intel_dp->link_bw;
843 intel_dp->link_configuration[1] = intel_dp->lane_count;
844 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
845 /*
846 * Check for DPCD version > 1.1 and enhanced framing support
847 */
848 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
849 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
850 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
851 }
852}
853
a4fc5ed6
KP		 854static void
855intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
856 struct drm_display_mode *adjusted_mode)
857{
e3421a18 858 struct drm_device *dev = encoder->dev;
417e822d 859 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 860 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 861 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863
417e822d 864 /*
1a2eb460 865 * There are four kinds of DP registers:
417e822d
KP		 866 *
867 * IBX PCH
1a2eb460
KP		 868 * SNB CPU
869 * IVB CPU
417e822d
KP		 870 * CPT PCH
871 *
872 * IBX PCH and CPU are the same for almost everything,
873 * except that the CPU DP PLL is configured in this
874 * register
875 *
876 * CPT PCH is quite different, having many bits moved
877 * to the TRANS_DP_CTL register instead. That
878 * configuration happens (oddly) in ironlake_pch_enable
879 */
9c9e7927 880
417e822d
KP		 881 /* Preserve the BIOS-computed detected bit. This is
882 * supposed to be read-only.
883 */
884 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 885
417e822d 886 /* Handle DP bits in common between all three register formats */
417e822d 887 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 888
ea5b213a 889 switch (intel_dp->lane_count) {
a4fc5ed6 890 case 1:
ea5b213a 891 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 892 break;
893 case 2:
ea5b213a 894 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 895 break;
896 case 4:
ea5b213a 897 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 898 break;
899 }
e0dac65e
WF		 900 if (intel_dp->has_audio) {
901 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
902 pipe_name(intel_crtc->pipe));
ea5b213a 903 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 904 intel_write_eld(encoder, adjusted_mode);
905 }
247d89f6
PZ		 906
907 intel_dp_init_link_config(intel_dp);
a4fc5ed6 908
417e822d 909 /* Split out the IBX/CPU vs CPT settings */
32f9d658 910
19c03924 911 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 912 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
913 intel_dp->DP |= DP_SYNC_HS_HIGH;
914 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
915 intel_dp->DP |= DP_SYNC_VS_HIGH;
916 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
917
918 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
919 intel_dp->DP |= DP_ENHANCED_FRAMING;
920
921 intel_dp->DP |= intel_crtc->pipe << 29;
922
923 /* don't miss out required setting for eDP */
1a2eb460
KP		 924 if (adjusted_mode->clock < 200000)
925 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
926 else
927 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
928 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 929 intel_dp->DP |= intel_dp->color_range;
930
931 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
932 intel_dp->DP |= DP_SYNC_HS_HIGH;
933 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
934 intel_dp->DP |= DP_SYNC_VS_HIGH;
935 intel_dp->DP |= DP_LINK_TRAIN_OFF;
936
937 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
938 intel_dp->DP |= DP_ENHANCED_FRAMING;
939
940 if (intel_crtc->pipe == 1)
941 intel_dp->DP |= DP_PIPEB_SELECT;
942
943 if (is_cpu_edp(intel_dp)) {
944 /* don't miss out required setting for eDP */
417e822d
KP		 945 if (adjusted_mode->clock < 200000)
946 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
947 else
948 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
949 }
950 } else {
951 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 952 }
a4fc5ed6
KP		 953}
954
99ea7127
KP		 955#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
956#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
957
958#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
959#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
960
961#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
962#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
963
964static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
965 u32 mask,
966 u32 value)
bd943159 967{
30add22d 968 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 969 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 970
99ea7127
KP		 971 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
972 mask, value,
973 I915_READ(PCH_PP_STATUS),
974 I915_READ(PCH_PP_CONTROL));
32ce697c 975
99ea7127
KP		 976 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
977 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
978 I915_READ(PCH_PP_STATUS),
979 I915_READ(PCH_PP_CONTROL));
32ce697c 980 }
99ea7127 981}
32ce697c 982
99ea7127
KP		 983static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
984{
985 DRM_DEBUG_KMS("Wait for panel power on\n");
986 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 987}
988
99ea7127
KP		 989static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
990{
991 DRM_DEBUG_KMS("Wait for panel power off time\n");
992 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
993}
994
995static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
996{
997 DRM_DEBUG_KMS("Wait for panel power cycle\n");
998 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
999}
1000
1001
832dd3c1
KP		 1002/* Read the current pp_control value, unlocking the register if it
1003 * is locked
1004 */
1005
1006static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1007{
1008 u32 control = I915_READ(PCH_PP_CONTROL);
1009
1010 control &= ~PANEL_UNLOCK_MASK;
1011 control |= PANEL_UNLOCK_REGS;
1012 return control;
bd943159
KP		 1013}
1014
82a4d9c0 1015void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1016{
30add22d 1017 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 pp;
1020
97af61f5
KP		 1021 if (!is_edp(intel_dp))
1022 return;
f01eca2e 1023 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1024
bd943159
KP		 1025 WARN(intel_dp->want_panel_vdd,
1026 "eDP VDD already requested on\n");
1027
1028 intel_dp->want_panel_vdd = true;
99ea7127 1029
bd943159
KP		 1030 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1031 DRM_DEBUG_KMS("eDP VDD already on\n");
1032 return;
1033 }
1034
99ea7127
KP		 1035 if (!ironlake_edp_have_panel_power(intel_dp))
1036 ironlake_wait_panel_power_cycle(intel_dp);
1037
832dd3c1 1038 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1039 pp |= EDP_FORCE_VDD;
1040 I915_WRITE(PCH_PP_CONTROL, pp);
1041 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1042 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1043 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1044
1045 /*
1046 * If the panel wasn't on, delay before accessing aux channel
1047 */
1048 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1049 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1050 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1051 }
5d613501
JB		 1052}
1053
bd943159 1054static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1055{
30add22d 1056 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1057 struct drm_i915_private *dev_priv = dev->dev_private;
1058 u32 pp;
1059
bd943159 1060 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1061 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1062 pp &= ~EDP_FORCE_VDD;
1063 I915_WRITE(PCH_PP_CONTROL, pp);
1064 POSTING_READ(PCH_PP_CONTROL);
1065
1066 /* Make sure sequencer is idle before allowing subsequent activity */
1067 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1068 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1069
1070 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1071 }
1072}
5d613501 1073
bd943159
KP		 1074static void ironlake_panel_vdd_work(struct work_struct *__work)
1075{
1076 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1077 struct intel_dp, panel_vdd_work);
30add22d 1078 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1079
627f7675 1080 mutex_lock(&dev->mode_config.mutex);
bd943159 1081 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1082 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1083}
1084
82a4d9c0 1085void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1086{
97af61f5
KP		 1087 if (!is_edp(intel_dp))
1088 return;
5d613501 1089
bd943159
KP		 1090 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1091 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1092
bd943159
KP		 1093 intel_dp->want_panel_vdd = false;
1094
1095 if (sync) {
1096 ironlake_panel_vdd_off_sync(intel_dp);
1097 } else {
1098 /*
1099 * Queue the timer to fire a long
1100 * time from now (relative to the power down delay)
1101 * to keep the panel power up across a sequence of operations
1102 */
1103 schedule_delayed_work(&intel_dp->panel_vdd_work,
1104 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1105 }
5d613501
JB		 1106}
1107
82a4d9c0 1108void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1109{
30add22d 1110 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1111 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1112 u32 pp;
9934c132 1113
97af61f5 1114 if (!is_edp(intel_dp))
bd943159 1115 return;
99ea7127
KP		 1116
1117 DRM_DEBUG_KMS("Turn eDP power on\n");
1118
1119 if (ironlake_edp_have_panel_power(intel_dp)) {
1120 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1121 return;
99ea7127 1122 }
9934c132 1123
99ea7127 1124 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1125
99ea7127 1126 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1127 if (IS_GEN5(dev)) {
1128 /* ILK workaround: disable reset around power sequence */
1129 pp &= ~PANEL_POWER_RESET;
1130 I915_WRITE(PCH_PP_CONTROL, pp);
1131 POSTING_READ(PCH_PP_CONTROL);
1132 }
37c6c9b0 1133
1c0ae80a 1134 pp |= POWER_TARGET_ON;
99ea7127
KP		 1135 if (!IS_GEN5(dev))
1136 pp |= PANEL_POWER_RESET;
1137
9934c132 1138 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1139 POSTING_READ(PCH_PP_CONTROL);
9934c132 1140
99ea7127 1141 ironlake_wait_panel_on(intel_dp);
9934c132 1142
05ce1a49
KP		 1143 if (IS_GEN5(dev)) {
1144 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1145 I915_WRITE(PCH_PP_CONTROL, pp);
1146 POSTING_READ(PCH_PP_CONTROL);
1147 }
9934c132
JB		 1148}
1149
82a4d9c0 1150void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1151{
30add22d 1152 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1153 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1154 u32 pp;
9934c132 1155
97af61f5
KP		 1156 if (!is_edp(intel_dp))
1157 return;
37c6c9b0 1158
99ea7127 1159 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1160
6cb49835 1161 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1162
99ea7127 1163 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1164 /* We need to switch off panel power _and_ force vdd, for otherwise some
1165 * panels get very unhappy and cease to work. */
1166 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1167 I915_WRITE(PCH_PP_CONTROL, pp);
1168 POSTING_READ(PCH_PP_CONTROL);
9934c132 1169
35a38556
DV		 1170 intel_dp->want_panel_vdd = false;
1171
99ea7127 1172 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1173}
1174
d6c50ff8 1175void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1176{
da63a9f2
PZ		 1177 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1178 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1179 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1180 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658
ZW		 1181 u32 pp;
1182
f01eca2e
KP		 1183 if (!is_edp(intel_dp))
1184 return;
1185
28c97730 1186 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1187 /*
1188 * If we enable the backlight right away following a panel power
1189 * on, we may see slight flicker as the panel syncs with the eDP
1190 * link. So delay a bit to make sure the image is solid before
1191 * allowing it to appear.
1192 */
f01eca2e 1193 msleep(intel_dp->backlight_on_delay);
832dd3c1 1194 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1195 pp |= EDP_BLC_ENABLE;
1196 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1197 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1198
1199 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1200}
1201
d6c50ff8 1202void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1203{
30add22d 1204 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 u32 pp;
1207
f01eca2e
KP		 1208 if (!is_edp(intel_dp))
1209 return;
1210
035aa3de
DV		 1211 intel_panel_disable_backlight(dev);
1212
28c97730 1213 DRM_DEBUG_KMS("\n");
832dd3c1 1214 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1215 pp &= ~EDP_BLC_ENABLE;
1216 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1217 POSTING_READ(PCH_PP_CONTROL);
1218 msleep(intel_dp->backlight_off_delay);
32f9d658 1219}
a4fc5ed6 1220
2bd2ad64 1221static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1222{
da63a9f2
PZ		 1223 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1224 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1225 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1226 struct drm_i915_private *dev_priv = dev->dev_private;
1227 u32 dpa_ctl;
1228
2bd2ad64
DV		 1229 assert_pipe_disabled(dev_priv,
1230 to_intel_crtc(crtc)->pipe);
1231
d240f20f
JB		 1232 DRM_DEBUG_KMS("\n");
1233 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1234 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1235 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1236
1237 /* We don't adjust intel_dp->DP while tearing down the link, to
1238 * facilitate link retraining (e.g. after hotplug). Hence clear all
1239 * enable bits here to ensure that we don't enable too much. */
1240 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1241 intel_dp->DP |= DP_PLL_ENABLE;
1242 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1243 POSTING_READ(DP_A);
1244 udelay(200);
d240f20f
JB		 1245}
1246
2bd2ad64 1247static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1248{
da63a9f2
PZ		 1249 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1250 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1251 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1252 struct drm_i915_private *dev_priv = dev->dev_private;
1253 u32 dpa_ctl;
1254
2bd2ad64
DV		 1255 assert_pipe_disabled(dev_priv,
1256 to_intel_crtc(crtc)->pipe);
1257
d240f20f 1258 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1259 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1260 "dp pll off, should be on\n");
1261 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1262
1263 /* We can't rely on the value tracked for the DP register in
1264 * intel_dp->DP because link_down must not change that (otherwise link
1265 * re-training will fail. */
298b0b39 1266 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1267 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1268 POSTING_READ(DP_A);
d240f20f
JB		 1269 udelay(200);
1270}
1271
c7ad3810 1272/* If the sink supports it, try to set the power state appropriately */
c19b0669 1273void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1274{
1275 int ret, i;
1276
1277 /* Should have a valid DPCD by this point */
1278 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1279 return;
1280
1281 if (mode != DRM_MODE_DPMS_ON) {
1282 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1283 DP_SET_POWER_D3);
1284 if (ret != 1)
1285 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1286 } else {
1287 /*
1288 * When turning on, we need to retry for 1ms to give the sink
1289 * time to wake up.
1290 */
1291 for (i = 0; i < 3; i++) {
1292 ret = intel_dp_aux_native_write_1(intel_dp,
1293 DP_SET_POWER,
1294 DP_SET_POWER_D0);
1295 if (ret == 1)
1296 break;
1297 msleep(1);
1298 }
1299 }
1300}
1301
19d8fe15
DV		 1302static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1303 enum pipe *pipe)
d240f20f 1304{
19d8fe15
DV		 1305 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1306 struct drm_device *dev = encoder->base.dev;
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 u32 tmp = I915_READ(intel_dp->output_reg);
1309
1310 if (!(tmp & DP_PORT_EN))
1311 return false;
1312
1313 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1314 *pipe = PORT_TO_PIPE_CPT(tmp);
1315 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1316 *pipe = PORT_TO_PIPE(tmp);
1317 } else {
1318 u32 trans_sel;
1319 u32 trans_dp;
1320 int i;
1321
1322 switch (intel_dp->output_reg) {
1323 case PCH_DP_B:
1324 trans_sel = TRANS_DP_PORT_SEL_B;
1325 break;
1326 case PCH_DP_C:
1327 trans_sel = TRANS_DP_PORT_SEL_C;
1328 break;
1329 case PCH_DP_D:
1330 trans_sel = TRANS_DP_PORT_SEL_D;
1331 break;
1332 default:
1333 return true;
1334 }
1335
1336 for_each_pipe(i) {
1337 trans_dp = I915_READ(TRANS_DP_CTL(i));
1338 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1339 *pipe = i;
1340 return true;
1341 }
1342 }
19d8fe15 1343
4a0833ec
DV		 1344 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1345 intel_dp->output_reg);
1346 }
d240f20f 1347
19d8fe15
DV		 1348 return true;
1349}
1350
e8cb4558 1351static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1352{
e8cb4558 1353 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1354
1355 /* Make sure the panel is off before trying to change the mode. But also
1356 * ensure that we have vdd while we switch off the panel. */
1357 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1358 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1359 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1360 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1361
1362 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1363 if (!is_cpu_edp(intel_dp))
1364 intel_dp_link_down(intel_dp);
d240f20f
JB		 1365}
1366
2bd2ad64
DV		 1367static void intel_post_disable_dp(struct intel_encoder *encoder)
1368{
1369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1370
3739850b
DV		 1371 if (is_cpu_edp(intel_dp)) {
1372 intel_dp_link_down(intel_dp);
2bd2ad64 1373 ironlake_edp_pll_off(intel_dp);
3739850b 1374 }
2bd2ad64
DV		 1375}
1376
e8cb4558 1377static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1378{
e8cb4558
DV		 1379 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1380 struct drm_device *dev = encoder->base.dev;
1381 struct drm_i915_private *dev_priv = dev->dev_private;
1382 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1383
0c33d8d7
DV		 1384 if (WARN_ON(dp_reg & DP_PORT_EN))
1385 return;
1386
97af61f5 1387 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1388 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1389 intel_dp_start_link_train(intel_dp);
1390 ironlake_edp_panel_on(intel_dp);
1391 ironlake_edp_panel_vdd_off(intel_dp, true);
1392 intel_dp_complete_link_train(intel_dp);
f01eca2e 1393 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1394}
1395
2bd2ad64 1396static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1397{
2bd2ad64 1398 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1399
2bd2ad64
DV		 1400 if (is_cpu_edp(intel_dp))
1401 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1402}
1403
1404/*
df0c237d
JB		 1405 * Native read with retry for link status and receiver capability reads for
1406 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1407 */
1408static bool
df0c237d
JB		 1409intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1410 uint8_t *recv, int recv_bytes)
a4fc5ed6 1411{
61da5fab
JB		 1412 int ret, i;
1413
df0c237d
JB		 1414 /*
1415 * Sinks are *supposed* to come up within 1ms from an off state,
1416 * but we're also supposed to retry 3 times per the spec.
1417 */
61da5fab 1418 for (i = 0; i < 3; i++) {
df0c237d
JB		 1419 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1420 recv_bytes);
1421 if (ret == recv_bytes)
61da5fab
JB		 1422 return true;
1423 msleep(1);
1424 }
a4fc5ed6 1425
61da5fab 1426 return false;
a4fc5ed6
KP		 1427}
1428
1429/*
1430 * Fetch AUX CH registers 0x202 - 0x207 which contain
1431 * link status information
1432 */
1433static bool
93f62dad 1434intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1435{
df0c237d
JB		 1436 return intel_dp_aux_native_read_retry(intel_dp,
1437 DP_LANE0_1_STATUS,
93f62dad 1438 link_status,
df0c237d 1439 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1440}
1441
a4fc5ed6
KP		 1442#if 0
1443static char *voltage_names[] = {
1444 "0.4V", "0.6V", "0.8V", "1.2V"
1445};
1446static char *pre_emph_names[] = {
1447 "0dB", "3.5dB", "6dB", "9.5dB"
1448};
1449static char *link_train_names[] = {
1450 "pattern 1", "pattern 2", "idle", "off"
1451};
1452#endif
1453
1454/*
1455 * These are source-specific values; current Intel hardware supports
1456 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1457 */
a4fc5ed6
KP		 1458
1459static uint8_t
1a2eb460 1460intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1461{
30add22d 1462 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1463
1464 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1465 return DP_TRAIN_VOLTAGE_SWING_800;
1466 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1467 return DP_TRAIN_VOLTAGE_SWING_1200;
1468 else
1469 return DP_TRAIN_VOLTAGE_SWING_800;
1470}
1471
1472static uint8_t
1473intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1474{
30add22d 1475 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1476
d6c0d722
PZ		 1477 if (IS_HASWELL(dev)) {
1478 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1479 case DP_TRAIN_VOLTAGE_SWING_400:
1480 return DP_TRAIN_PRE_EMPHASIS_9_5;
1481 case DP_TRAIN_VOLTAGE_SWING_600:
1482 return DP_TRAIN_PRE_EMPHASIS_6;
1483 case DP_TRAIN_VOLTAGE_SWING_800:
1484 return DP_TRAIN_PRE_EMPHASIS_3_5;
1485 case DP_TRAIN_VOLTAGE_SWING_1200:
1486 default:
1487 return DP_TRAIN_PRE_EMPHASIS_0;
1488 }
1489 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1490 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1491 case DP_TRAIN_VOLTAGE_SWING_400:
1492 return DP_TRAIN_PRE_EMPHASIS_6;
1493 case DP_TRAIN_VOLTAGE_SWING_600:
1494 case DP_TRAIN_VOLTAGE_SWING_800:
1495 return DP_TRAIN_PRE_EMPHASIS_3_5;
1496 default:
1497 return DP_TRAIN_PRE_EMPHASIS_0;
1498 }
1499 } else {
1500 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1501 case DP_TRAIN_VOLTAGE_SWING_400:
1502 return DP_TRAIN_PRE_EMPHASIS_6;
1503 case DP_TRAIN_VOLTAGE_SWING_600:
1504 return DP_TRAIN_PRE_EMPHASIS_6;
1505 case DP_TRAIN_VOLTAGE_SWING_800:
1506 return DP_TRAIN_PRE_EMPHASIS_3_5;
1507 case DP_TRAIN_VOLTAGE_SWING_1200:
1508 default:
1509 return DP_TRAIN_PRE_EMPHASIS_0;
1510 }
a4fc5ed6
KP		 1511 }
1512}
1513
1514static void
93f62dad 1515intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1516{
1517 uint8_t v = 0;
1518 uint8_t p = 0;
1519 int lane;
1a2eb460
KP		 1520 uint8_t voltage_max;
1521 uint8_t preemph_max;
a4fc5ed6 1522
33a34e4e 1523 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1524 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1525 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1526
1527 if (this_v > v)
1528 v = this_v;
1529 if (this_p > p)
1530 p = this_p;
1531 }
1532
1a2eb460 1533 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1534 if (v >= voltage_max)
1535 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1536
1a2eb460
KP		 1537 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1538 if (p >= preemph_max)
1539 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1540
1541 for (lane = 0; lane < 4; lane++)
33a34e4e 1542 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1543}
1544
1545static uint32_t
93f62dad 1546intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1547{
3cf2efb1 1548 uint32_t signal_levels = 0;
a4fc5ed6 1549
3cf2efb1 1550 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1551 case DP_TRAIN_VOLTAGE_SWING_400:
1552 default:
1553 signal_levels |= DP_VOLTAGE_0_4;
1554 break;
1555 case DP_TRAIN_VOLTAGE_SWING_600:
1556 signal_levels |= DP_VOLTAGE_0_6;
1557 break;
1558 case DP_TRAIN_VOLTAGE_SWING_800:
1559 signal_levels |= DP_VOLTAGE_0_8;
1560 break;
1561 case DP_TRAIN_VOLTAGE_SWING_1200:
1562 signal_levels |= DP_VOLTAGE_1_2;
1563 break;
1564 }
3cf2efb1 1565 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1566 case DP_TRAIN_PRE_EMPHASIS_0:
1567 default:
1568 signal_levels |= DP_PRE_EMPHASIS_0;
1569 break;
1570 case DP_TRAIN_PRE_EMPHASIS_3_5:
1571 signal_levels |= DP_PRE_EMPHASIS_3_5;
1572 break;
1573 case DP_TRAIN_PRE_EMPHASIS_6:
1574 signal_levels |= DP_PRE_EMPHASIS_6;
1575 break;
1576 case DP_TRAIN_PRE_EMPHASIS_9_5:
1577 signal_levels |= DP_PRE_EMPHASIS_9_5;
1578 break;
1579 }
1580 return signal_levels;
1581}
1582
e3421a18
ZW		 1583/* Gen6's DP voltage swing and pre-emphasis control */
1584static uint32_t
1585intel_gen6_edp_signal_levels(uint8_t train_set)
1586{
3c5a62b5
YL		 1587 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1588 DP_TRAIN_PRE_EMPHASIS_MASK);
1589 switch (signal_levels) {
e3421a18 1590 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1591 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1592 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1593 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1594 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1595 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1596 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1597 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1598 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1599 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1600 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1601 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1602 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1603 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1604 default:
3c5a62b5
YL		 1605 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1606 "0x%x\n", signal_levels);
1607 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1608 }
1609}
1610
1a2eb460
KP		 1611/* Gen7's DP voltage swing and pre-emphasis control */
1612static uint32_t
1613intel_gen7_edp_signal_levels(uint8_t train_set)
1614{
1615 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1616 DP_TRAIN_PRE_EMPHASIS_MASK);
1617 switch (signal_levels) {
1618 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1619 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1620 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1621 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1622 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1623 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1624
1625 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1626 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1627 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1628 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1629
1630 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1631 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1632 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1633 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1634
1635 default:
1636 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1637 "0x%x\n", signal_levels);
1638 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1639 }
1640}
1641
d6c0d722
PZ		 1642/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1643static uint32_t
1644intel_dp_signal_levels_hsw(uint8_t train_set)
1645{
1646 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1647 DP_TRAIN_PRE_EMPHASIS_MASK);
1648 switch (signal_levels) {
1649 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1650 return DDI_BUF_EMP_400MV_0DB_HSW;
1651 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1652 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1653 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1654 return DDI_BUF_EMP_400MV_6DB_HSW;
1655 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1656 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1657
1658 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1659 return DDI_BUF_EMP_600MV_0DB_HSW;
1660 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1661 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1662 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1663 return DDI_BUF_EMP_600MV_6DB_HSW;
1664
1665 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1666 return DDI_BUF_EMP_800MV_0DB_HSW;
1667 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1668 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1669 default:
1670 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1671 "0x%x\n", signal_levels);
1672 return DDI_BUF_EMP_400MV_0DB_HSW;
1673 }
1674}
1675
a4fc5ed6 1676static bool
ea5b213a 1677intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1678 uint32_t dp_reg_value,
58e10eb9 1679 uint8_t dp_train_pat)
a4fc5ed6 1680{
174edf1f
PZ		 1681 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1682 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1683 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1684 enum port port = intel_dig_port->port;
a4fc5ed6 1685 int ret;
d6c0d722 1686 uint32_t temp;
a4fc5ed6 1687
d6c0d722 1688 if (IS_HASWELL(dev)) {
174edf1f 1689 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1690
1691 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1692 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1693 else
1694 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1695
1696 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1697 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1698 case DP_TRAINING_PATTERN_DISABLE:
1699 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
174edf1f 1700 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 1701
174edf1f 1702 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
d6c0d722
PZ		 1703 DP_TP_STATUS_IDLE_DONE), 1))
1704 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1705
1706 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1707 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1708
1709 break;
1710 case DP_TRAINING_PATTERN_1:
1711 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1712 break;
1713 case DP_TRAINING_PATTERN_2:
1714 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1715 break;
1716 case DP_TRAINING_PATTERN_3:
1717 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1718 break;
1719 }
174edf1f 1720 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1721
1722 } else if (HAS_PCH_CPT(dev) &&
1723 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1724 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1725
1726 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1727 case DP_TRAINING_PATTERN_DISABLE:
1728 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1729 break;
1730 case DP_TRAINING_PATTERN_1:
1731 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1732 break;
1733 case DP_TRAINING_PATTERN_2:
1734 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1735 break;
1736 case DP_TRAINING_PATTERN_3:
1737 DRM_ERROR("DP training pattern 3 not supported\n");
1738 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1739 break;
1740 }
1741
1742 } else {
1743 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1744
1745 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1746 case DP_TRAINING_PATTERN_DISABLE:
1747 dp_reg_value |= DP_LINK_TRAIN_OFF;
1748 break;
1749 case DP_TRAINING_PATTERN_1:
1750 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1751 break;
1752 case DP_TRAINING_PATTERN_2:
1753 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1754 break;
1755 case DP_TRAINING_PATTERN_3:
1756 DRM_ERROR("DP training pattern 3 not supported\n");
1757 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1758 break;
1759 }
1760 }
1761
ea5b213a
CW		 1762 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1763 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1764
ea5b213a 1765 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1766 DP_TRAINING_PATTERN_SET,
1767 dp_train_pat);
1768
47ea7542
PZ		 1769 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1770 DP_TRAINING_PATTERN_DISABLE) {
1771 ret = intel_dp_aux_native_write(intel_dp,
1772 DP_TRAINING_LANE0_SET,
1773 intel_dp->train_set,
1774 intel_dp->lane_count);
1775 if (ret != intel_dp->lane_count)
1776 return false;
1777 }
a4fc5ed6
KP		 1778
1779 return true;
1780}
1781
33a34e4e 1782/* Enable corresponding port and start training pattern 1 */
c19b0669 1783void
33a34e4e 1784intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1785{
da63a9f2 1786 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1787 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1788 int i;
1789 uint8_t voltage;
1790 bool clock_recovery = false;
cdb0e95b 1791 int voltage_tries, loop_tries;
ea5b213a 1792 uint32_t DP = intel_dp->DP;
a4fc5ed6 1793
c19b0669
PZ		 1794 if (IS_HASWELL(dev))
1795 intel_ddi_prepare_link_retrain(encoder);
1796
3cf2efb1
CW		 1797 /* Write the link configuration data */
1798 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1799 intel_dp->link_configuration,
1800 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1801
1802 DP |= DP_PORT_EN;
1a2eb460 1803
33a34e4e 1804 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1805 voltage = 0xff;
cdb0e95b
KP		 1806 voltage_tries = 0;
1807 loop_tries = 0;
a4fc5ed6
KP		 1808 clock_recovery = false;
1809 for (;;) {
33a34e4e 1810 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1811 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1812 uint32_t signal_levels;
417e822d 1813
d6c0d722
PZ		 1814 if (IS_HASWELL(dev)) {
1815 signal_levels = intel_dp_signal_levels_hsw(
1816 intel_dp->train_set[0]);
1817 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1818 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1819 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1820 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1821 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1822 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1823 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1824 } else {
93f62dad 1825 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1826 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1827 }
d6c0d722
PZ		 1828 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1829 signal_levels);
a4fc5ed6 1830
a7c9655f 1831 /* Set training pattern 1 */
47ea7542 1832 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1833 DP_TRAINING_PATTERN_1 |
1834 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1835 break;
a4fc5ed6 1836
a7c9655f 1837 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1838 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1839 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1840 break;
93f62dad 1841 }
a4fc5ed6 1842
01916270 1843 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1844 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1845 clock_recovery = true;
1846 break;
1847 }
1848
1849 /* Check to see if we've tried the max voltage */
1850 for (i = 0; i < intel_dp->lane_count; i++)
1851 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1852 break;
0d710688 1853 if (i == intel_dp->lane_count && voltage_tries == 5) {
24773670 1854 if (++loop_tries == 5) {
cdb0e95b
KP		 1855 DRM_DEBUG_KMS("too many full retries, give up\n");
1856 break;
1857 }
1858 memset(intel_dp->train_set, 0, 4);
1859 voltage_tries = 0;
1860 continue;
1861 }
a4fc5ed6 1862
3cf2efb1 1863 /* Check to see if we've tried the same voltage 5 times */
24773670
CW		 1864 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1865 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
cdb0e95b 1866 voltage_tries = 0;
24773670
CW		 1867 } else
1868 ++voltage_tries;
a4fc5ed6 1869
3cf2efb1 1870 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1871 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1872 }
1873
33a34e4e
JB		 1874 intel_dp->DP = DP;
1875}
1876
c19b0669 1877void
33a34e4e
JB		 1878intel_dp_complete_link_train(struct intel_dp *intel_dp)
1879{
30add22d 1880 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33a34e4e 1881 bool channel_eq = false;
37f80975 1882 int tries, cr_tries;
33a34e4e
JB		 1883 uint32_t DP = intel_dp->DP;
1884
a4fc5ed6
KP		 1885 /* channel equalization */
1886 tries = 0;
37f80975 1887 cr_tries = 0;
a4fc5ed6
KP		 1888 channel_eq = false;
1889 for (;;) {
33a34e4e 1890 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1891 uint32_t signal_levels;
93f62dad 1892 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1893
37f80975
JB		 1894 if (cr_tries > 5) {
1895 DRM_ERROR("failed to train DP, aborting\n");
1896 intel_dp_link_down(intel_dp);
1897 break;
1898 }
1899
d6c0d722
PZ		 1900 if (IS_HASWELL(dev)) {
1901 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1902 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1903 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1904 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1905 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1906 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1907 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1908 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1909 } else {
93f62dad 1910 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1911 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1912 }
1913
a4fc5ed6 1914 /* channel eq pattern */
47ea7542 1915 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1916 DP_TRAINING_PATTERN_2 |
1917 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1918 break;
1919
a7c9655f 1920 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1921 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1922 break;
a4fc5ed6 1923
37f80975 1924 /* Make sure clock is still ok */
01916270 1925 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1926 intel_dp_start_link_train(intel_dp);
1927 cr_tries++;
1928 continue;
1929 }
1930
1ffdff13 1931 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1932 channel_eq = true;
1933 break;
1934 }
a4fc5ed6 1935
37f80975
JB		 1936 /* Try 5 times, then try clock recovery if that fails */
1937 if (tries > 5) {
1938 intel_dp_link_down(intel_dp);
1939 intel_dp_start_link_train(intel_dp);
1940 tries = 0;
1941 cr_tries++;
1942 continue;
1943 }
a4fc5ed6 1944
3cf2efb1 1945 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1946 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1947 ++tries;
869184a6 1948 }
3cf2efb1 1949
d6c0d722
PZ		 1950 if (channel_eq)
1951 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1952
47ea7542 1953 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1954}
1955
1956static void
ea5b213a 1957intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1958{
da63a9f2
PZ		 1959 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1960 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1961 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1962 uint32_t DP = intel_dp->DP;
a4fc5ed6 1963
c19b0669
PZ		 1964 /*
1965 * DDI code has a strict mode set sequence and we should try to respect
1966 * it, otherwise we might hang the machine in many different ways. So we
1967 * really should be disabling the port only on a complete crtc_disable
1968 * sequence. This function is just called under two conditions on DDI
1969 * code:
1970 * - Link train failed while doing crtc_enable, and on this case we
1971 * really should respect the mode set sequence and wait for a
1972 * crtc_disable.
1973 * - Someone turned the monitor off and intel_dp_check_link_status
1974 * called us. We don't need to disable the whole port on this case, so
1975 * when someone turns the monitor on again,
1976 * intel_ddi_prepare_link_retrain will take care of redoing the link
1977 * train.
1978 */
1979 if (IS_HASWELL(dev))
1980 return;
1981
0c33d8d7 1982 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 1983 return;
1984
28c97730 1985 DRM_DEBUG_KMS("\n");
32f9d658 1986
1a2eb460 1987 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1988 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1989 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1990 } else {
1991 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1992 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1993 }
fe255d00 1994 POSTING_READ(intel_dp->output_reg);
5eb08b69 1995
fe255d00 1996 msleep(17);
5eb08b69 1997
493a7081 1998 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1999 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2000 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2001
5bddd17f
EA		 2002 /* Hardware workaround: leaving our transcoder select
2003 * set to transcoder B while it's off will prevent the
2004 * corresponding HDMI output on transcoder A.
2005 *
2006 * Combine this with another hardware workaround:
2007 * transcoder select bit can only be cleared while the
2008 * port is enabled.
2009 */
2010 DP &= ~DP_PIPEB_SELECT;
2011 I915_WRITE(intel_dp->output_reg, DP);
2012
2013 /* Changes to enable or select take place the vblank
2014 * after being written.
2015 */
31acbcc4
CW		 2016 if (crtc == NULL) {
2017 /* We can arrive here never having been attached
2018 * to a CRTC, for instance, due to inheriting
2019 * random state from the BIOS.
2020 *
2021 * If the pipe is not running, play safe and
2022 * wait for the clocks to stabilise before
2023 * continuing.
2024 */
2025 POSTING_READ(intel_dp->output_reg);
2026 msleep(50);
2027 } else
2028 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2029 }
2030
832afda6 2031 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2032 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2033 POSTING_READ(intel_dp->output_reg);
f01eca2e 2034 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2035}
2036
26d61aad
KP		 2037static bool
2038intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2039{
92fd8fd1 2040 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 2041 sizeof(intel_dp->dpcd)) == 0)
2042 return false; /* aux transfer failed */
92fd8fd1 2043
b091cd92
AJ		 2044 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2045 return false; /* DPCD not present */
2046
2047 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2048 DP_DWN_STRM_PORT_PRESENT))
2049 return true; /* native DP sink */
2050
2051 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2052 return true; /* no per-port downstream info */
2053
2054 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2055 intel_dp->downstream_ports,
2056 DP_MAX_DOWNSTREAM_PORTS) == 0)
2057 return false; /* downstream port status fetch failed */
2058
2059 return true;
92fd8fd1
KP		 2060}
2061
0d198328
AJ		 2062static void
2063intel_dp_probe_oui(struct intel_dp *intel_dp)
2064{
2065 u8 buf[3];
2066
2067 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2068 return;
2069
351cfc34
DV		 2070 ironlake_edp_panel_vdd_on(intel_dp);
2071
0d198328
AJ		 2072 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2073 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2074 buf[0], buf[1], buf[2]);
2075
2076 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2077 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2078 buf[0], buf[1], buf[2]);
351cfc34
DV		 2079
2080 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2081}
2082
a60f0e38
JB		 2083static bool
2084intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2085{
2086 int ret;
2087
2088 ret = intel_dp_aux_native_read_retry(intel_dp,
2089 DP_DEVICE_SERVICE_IRQ_VECTOR,
2090 sink_irq_vector, 1);
2091 if (!ret)
2092 return false;
2093
2094 return true;
2095}
2096
2097static void
2098intel_dp_handle_test_request(struct intel_dp *intel_dp)
2099{
2100 /* NAK by default */
9324cf7f 2101 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2102}
2103
a4fc5ed6
KP		 2104/*
2105 * According to DP spec
2106 * 5.1.2:
2107 * 1. Read DPCD
2108 * 2. Configure link according to Receiver Capabilities
2109 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2110 * 4. Check link status on receipt of hot-plug interrupt
2111 */
2112
2113static void
ea5b213a 2114intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2115{
da63a9f2 2116 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2117 u8 sink_irq_vector;
93f62dad 2118 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2119
da63a9f2 2120 if (!intel_encoder->connectors_active)
d2b996ac 2121 return;
59cd09e1 2122
da63a9f2 2123 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2124 return;
2125
92fd8fd1 2126 /* Try to read receiver status if the link appears to be up */
93f62dad 2127 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2128 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2129 return;
2130 }
2131
92fd8fd1 2132 /* Now read the DPCD to see if it's actually running */
26d61aad 2133 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2134 intel_dp_link_down(intel_dp);
2135 return;
2136 }
2137
a60f0e38
JB		 2138 /* Try to read the source of the interrupt */
2139 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2140 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2141 /* Clear interrupt source */
2142 intel_dp_aux_native_write_1(intel_dp,
2143 DP_DEVICE_SERVICE_IRQ_VECTOR,
2144 sink_irq_vector);
2145
2146 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2147 intel_dp_handle_test_request(intel_dp);
2148 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2149 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2150 }
2151
1ffdff13 2152 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2153 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2154 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2155 intel_dp_start_link_train(intel_dp);
2156 intel_dp_complete_link_train(intel_dp);
2157 }
a4fc5ed6 2158}
a4fc5ed6 2159
07d3dc18 2160/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2161static enum drm_connector_status
26d61aad 2162intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2163{
07d3dc18
AJ		 2164 uint8_t *dpcd = intel_dp->dpcd;
2165 bool hpd;
2166 uint8_t type;
2167
2168 if (!intel_dp_get_dpcd(intel_dp))
2169 return connector_status_disconnected;
2170
2171 /* if there's no downstream port, we're done */
2172 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2173 return connector_status_connected;
2174
2175 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2176 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2177 if (hpd) {
da131a46 2178 uint8_t reg;
07d3dc18 2179 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2180 &reg, 1))
07d3dc18 2181 return connector_status_unknown;
da131a46
AJ		 2182 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2183 : connector_status_disconnected;
07d3dc18
AJ		 2184 }
2185
2186 /* If no HPD, poke DDC gently */
2187 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2188 return connector_status_connected;
07d3dc18
AJ		 2189
2190 /* Well we tried, say unknown for unreliable port types */
2191 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2192 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2193 return connector_status_unknown;
2194
2195 /* Anything else is out of spec, warn and ignore */
2196 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2197 return connector_status_disconnected;
71ba9000
AJ		 2198}
2199
5eb08b69 2200static enum drm_connector_status
a9756bb5 2201ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2202{
30add22d 2203 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5eb08b69
ZW		 2204 enum drm_connector_status status;
2205
fe16d949
CW		 2206 /* Can't disconnect eDP, but you can close the lid... */
2207 if (is_edp(intel_dp)) {
30add22d 2208 status = intel_panel_detect(dev);
fe16d949
CW		 2209 if (status == connector_status_unknown)
2210 status = connector_status_connected;
2211 return status;
2212 }
01cb9ea6 2213
26d61aad 2214 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2215}
2216
a4fc5ed6 2217static enum drm_connector_status
a9756bb5 2218g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2219{
30add22d 2220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2221 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2222 uint32_t bit;
5eb08b69 2223
ea5b213a 2224 switch (intel_dp->output_reg) {
a4fc5ed6 2225 case DP_B:
10f76a38 2226 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2227 break;
2228 case DP_C:
10f76a38 2229 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2230 break;
2231 case DP_D:
10f76a38 2232 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2233 break;
2234 default:
2235 return connector_status_unknown;
2236 }
2237
10f76a38 2238 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2239 return connector_status_disconnected;
2240
26d61aad 2241 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2242}
2243
8c241fef
KP		 2244static struct edid *
2245intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2246{
9cd300e0 2247 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2248
9cd300e0
JN		 2249 /* use cached edid if we have one */
2250 if (intel_connector->edid) {
2251 struct edid *edid;
2252 int size;
2253
2254 /* invalid edid */
2255 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2256 return NULL;
2257
9cd300e0 2258 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2259 edid = kmalloc(size, GFP_KERNEL);
2260 if (!edid)
2261 return NULL;
2262
9cd300e0 2263 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2264 return edid;
2265 }
8c241fef 2266
9cd300e0 2267 return drm_get_edid(connector, adapter);
8c241fef
KP		 2268}
2269
2270static int
2271intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2272{
9cd300e0 2273 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2274
9cd300e0
JN		 2275 /* use cached edid if we have one */
2276 if (intel_connector->edid) {
2277 /* invalid edid */
2278 if (IS_ERR(intel_connector->edid))
2279 return 0;
2280
2281 return intel_connector_update_modes(connector,
2282 intel_connector->edid);
d6f24d0f
JB		 2283 }
2284
9cd300e0 2285 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2286}
2287
2288
a9756bb5
ZW		 2289/**
2290 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2291 *
2292 * \return true if DP port is connected.
2293 * \return false if DP port is disconnected.
2294 */
2295static enum drm_connector_status
2296intel_dp_detect(struct drm_connector *connector, bool force)
2297{
2298 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2299 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2300 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2301 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2302 enum drm_connector_status status;
2303 struct edid *edid = NULL;
898076ed 2304 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
a9756bb5
ZW		 2305
2306 intel_dp->has_audio = false;
2307
2308 if (HAS_PCH_SPLIT(dev))
2309 status = ironlake_dp_detect(intel_dp);
2310 else
2311 status = g4x_dp_detect(intel_dp);
1b9be9d0 2312
898076ed
JN		 2313 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2314 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2315 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
1b9be9d0 2316
a9756bb5
ZW		 2317 if (status != connector_status_connected)
2318 return status;
2319
0d198328
AJ		 2320 intel_dp_probe_oui(intel_dp);
2321
c3e5f67b
DV		 2322 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2323 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2324 } else {
8c241fef 2325 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2326 if (edid) {
2327 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2328 kfree(edid);
2329 }
a9756bb5
ZW		 2330 }
2331
d63885da
PZ		 2332 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2333 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2334 return connector_status_connected;
a4fc5ed6
KP		 2335}
2336
2337static int intel_dp_get_modes(struct drm_connector *connector)
2338{
df0e9248 2339 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2340 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2341 struct drm_device *dev = connector->dev;
32f9d658 2342 int ret;
a4fc5ed6
KP		 2343
2344 /* We should parse the EDID data and find out if it has an audio sink
2345 */
2346
8c241fef 2347 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2348 if (ret)
32f9d658
ZW		 2349 return ret;
2350
f8779fda 2351 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2352 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2353 struct drm_display_mode *mode;
dd06f90e
JN		 2354 mode = drm_mode_duplicate(dev,
2355 intel_connector->panel.fixed_mode);
f8779fda 2356 if (mode) {
32f9d658
ZW		 2357 drm_mode_probed_add(connector, mode);
2358 return 1;
2359 }
2360 }
2361 return 0;
a4fc5ed6
KP		 2362}
2363
1aad7ac0
CW		 2364static bool
2365intel_dp_detect_audio(struct drm_connector *connector)
2366{
2367 struct intel_dp *intel_dp = intel_attached_dp(connector);
2368 struct edid *edid;
2369 bool has_audio = false;
2370
8c241fef 2371 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2372 if (edid) {
2373 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2374 kfree(edid);
2375 }
2376
2377 return has_audio;
2378}
2379
f684960e
CW		 2380static int
2381intel_dp_set_property(struct drm_connector *connector,
2382 struct drm_property *property,
2383 uint64_t val)
2384{
e953fd7b 2385 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2386 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2387 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2388 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2389 int ret;
2390
2391 ret = drm_connector_property_set_value(connector, property, val);
2392 if (ret)
2393 return ret;
2394
3f43c48d 2395 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2396 int i = val;
2397 bool has_audio;
2398
2399 if (i == intel_dp->force_audio)
f684960e
CW		 2400 return 0;
2401
1aad7ac0 2402 intel_dp->force_audio = i;
f684960e 2403
c3e5f67b 2404 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2405 has_audio = intel_dp_detect_audio(connector);
2406 else
c3e5f67b 2407 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2408
2409 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2410 return 0;
2411
1aad7ac0 2412 intel_dp->has_audio = has_audio;
f684960e
CW		 2413 goto done;
2414 }
2415
e953fd7b
CW		 2416 if (property == dev_priv->broadcast_rgb_property) {
2417 if (val == !!intel_dp->color_range)
2418 return 0;
2419
2420 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2421 goto done;
2422 }
2423
53b41837
YN		 2424 if (is_edp(intel_dp) &&
2425 property == connector->dev->mode_config.scaling_mode_property) {
2426 if (val == DRM_MODE_SCALE_NONE) {
2427 DRM_DEBUG_KMS("no scaling not supported\n");
2428 return -EINVAL;
2429 }
2430
2431 if (intel_connector->panel.fitting_mode == val) {
2432 /* the eDP scaling property is not changed */
2433 return 0;
2434 }
2435 intel_connector->panel.fitting_mode = val;
2436
2437 goto done;
2438 }
2439
f684960e
CW		 2440 return -EINVAL;
2441
2442done:
da63a9f2
PZ		 2443 if (intel_encoder->base.crtc) {
2444 struct drm_crtc *crtc = intel_encoder->base.crtc;
a6778b3c
DV		 2445 intel_set_mode(crtc, &crtc->mode,
2446 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2447 }
2448
2449 return 0;
2450}
2451
a4fc5ed6 2452static void
0206e353 2453intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2454{
aaa6fd2a 2455 struct drm_device *dev = connector->dev;
be3cd5e3 2456 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2457 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2458
9cd300e0
JN		 2459 if (!IS_ERR_OR_NULL(intel_connector->edid))
2460 kfree(intel_connector->edid);
2461
1d508706 2462 if (is_edp(intel_dp)) {
aaa6fd2a 2463 intel_panel_destroy_backlight(dev);
1d508706
JN		 2464 intel_panel_fini(&intel_connector->panel);
2465 }
aaa6fd2a 2466
a4fc5ed6
KP		 2467 drm_sysfs_connector_remove(connector);
2468 drm_connector_cleanup(connector);
55f78c43 2469 kfree(connector);
a4fc5ed6
KP		 2470}
2471
24d05927
DV		 2472static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2473{
da63a9f2
PZ		 2474 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2475 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2476
2477 i2c_del_adapter(&intel_dp->adapter);
2478 drm_encoder_cleanup(encoder);
bd943159
KP		 2479 if (is_edp(intel_dp)) {
2480 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2481 ironlake_panel_vdd_off_sync(intel_dp);
2482 }
da63a9f2 2483 kfree(intel_dig_port);
24d05927
DV		 2484}
2485
a4fc5ed6 2486static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2487 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2488 .mode_set = intel_dp_mode_set,
1f703855 2489 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2490};
2491
a7902ac5
PZ		 2492static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2493 .mode_fixup = intel_dp_mode_fixup,
2494 .mode_set = intel_ddi_mode_set,
2495 .disable = intel_encoder_noop,
2496};
2497
a4fc5ed6 2498static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2499 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2500 .detect = intel_dp_detect,
2501 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2502 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2503 .destroy = intel_dp_destroy,
2504};
2505
2506static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2507 .get_modes = intel_dp_get_modes,
2508 .mode_valid = intel_dp_mode_valid,
df0e9248 2509 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2510};
2511
a4fc5ed6 2512static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2513 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2514};
2515
995b6762 2516static void
21d40d37 2517intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2518{
fa90ecef 2519 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2520
885a5014 2521 intel_dp_check_link_status(intel_dp);
c8110e52 2522}
6207937d 2523
e3421a18
ZW		 2524/* Return which DP Port should be selected for Transcoder DP control */
2525int
0206e353 2526intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2527{
2528 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2529 struct intel_encoder *intel_encoder;
2530 struct intel_dp *intel_dp;
e3421a18 2531
fa90ecef
PZ		 2532 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2533 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2534
fa90ecef
PZ		 2535 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2536 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2537 return intel_dp->output_reg;
e3421a18 2538 }
ea5b213a 2539
e3421a18
ZW		 2540 return -1;
2541}
2542
36e83a18 2543/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2544bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2545{
2546 struct drm_i915_private *dev_priv = dev->dev_private;
2547 struct child_device_config *p_child;
2548 int i;
2549
2550 if (!dev_priv->child_dev_num)
2551 return false;
2552
2553 for (i = 0; i < dev_priv->child_dev_num; i++) {
2554 p_child = dev_priv->child_dev + i;
2555
2556 if (p_child->dvo_port == PORT_IDPD &&
2557 p_child->device_type == DEVICE_TYPE_eDP)
2558 return true;
2559 }
2560 return false;
2561}
2562
f684960e
CW		 2563static void
2564intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2565{
53b41837
YN		 2566 struct intel_connector *intel_connector = to_intel_connector(connector);
2567
3f43c48d 2568 intel_attach_force_audio_property(connector);
e953fd7b 2569 intel_attach_broadcast_rgb_property(connector);
53b41837
YN		 2570
2571 if (is_edp(intel_dp)) {
2572 drm_mode_create_scaling_mode_property(connector->dev);
2573 drm_connector_attach_property(
2574 connector,
2575 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2576 DRM_MODE_SCALE_ASPECT);
2577 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2578 }
f684960e
CW		 2579}
2580
67a54566
DV		 2581static void
2582intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2583 struct intel_dp *intel_dp)
2584{
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct edp_power_seq cur, vbt, spec, final;
2587 u32 pp_on, pp_off, pp_div, pp;
2588
2589 /* Workaround: Need to write PP_CONTROL with the unlock key as
2590 * the very first thing. */
2591 pp = ironlake_get_pp_control(dev_priv);
2592 I915_WRITE(PCH_PP_CONTROL, pp);
2593
2594 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2595 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2596 pp_div = I915_READ(PCH_PP_DIVISOR);
2597
2598 /* Pull timing values out of registers */
2599 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2600 PANEL_POWER_UP_DELAY_SHIFT;
2601
2602 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2603 PANEL_LIGHT_ON_DELAY_SHIFT;
2604
2605 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2606 PANEL_LIGHT_OFF_DELAY_SHIFT;
2607
2608 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2609 PANEL_POWER_DOWN_DELAY_SHIFT;
2610
2611 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2612 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2613
2614 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2615 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2616
2617 vbt = dev_priv->edp.pps;
2618
2619 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2620 * our hw here, which are all in 100usec. */
2621 spec.t1_t3 = 210 * 10;
2622 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2623 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2624 spec.t10 = 500 * 10;
2625 /* This one is special and actually in units of 100ms, but zero
2626 * based in the hw (so we need to add 100 ms). But the sw vbt
2627 * table multiplies it with 1000 to make it in units of 100usec,
2628 * too. */
2629 spec.t11_t12 = (510 + 100) * 10;
2630
2631 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2632 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2633
2634 /* Use the max of the register settings and vbt. If both are
2635 * unset, fall back to the spec limits. */
2636#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2637 spec.field : \
2638 max(cur.field, vbt.field))
2639 assign_final(t1_t3);
2640 assign_final(t8);
2641 assign_final(t9);
2642 assign_final(t10);
2643 assign_final(t11_t12);
2644#undef assign_final
2645
2646#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2647 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2648 intel_dp->backlight_on_delay = get_delay(t8);
2649 intel_dp->backlight_off_delay = get_delay(t9);
2650 intel_dp->panel_power_down_delay = get_delay(t10);
2651 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2652#undef get_delay
2653
2654 /* And finally store the new values in the power sequencer. */
2655 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2656 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2657 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2658 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2659 /* Compute the divisor for the pp clock, simply match the Bspec
2660 * formula. */
2661 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2662 << PP_REFERENCE_DIVIDER_SHIFT;
2663 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2664 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2665
2666 /* Haswell doesn't have any port selection bits for the panel
2667 * power sequencer any more. */
2668 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2669 if (is_cpu_edp(intel_dp))
2670 pp_on |= PANEL_POWER_PORT_DP_A;
2671 else
2672 pp_on |= PANEL_POWER_PORT_DP_D;
2673 }
2674
2675 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2676 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2677 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2678
2679
2680 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2681 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2682 intel_dp->panel_power_cycle_delay);
2683
2684 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2685 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2686
2687 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2688 I915_READ(PCH_PP_ON_DELAYS),
2689 I915_READ(PCH_PP_OFF_DELAYS),
2690 I915_READ(PCH_PP_DIVISOR));
2691}
2692
f0fec3f2
PZ		 2693static void
2694intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2695 struct intel_connector *intel_connector)
a4fc5ed6 2696{
f0fec3f2
PZ		 2697 struct drm_connector *connector = &intel_connector->base;
2698 struct intel_dp *intel_dp = &intel_dig_port->dp;
2699 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2700 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2701 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2702 struct drm_display_mode *fixed_mode = NULL;
174edf1f 2703 enum port port = intel_dig_port->port;
5eb08b69 2704 const char *name = NULL;
b329530c 2705 int type;
a4fc5ed6 2706
0767935e
DV		 2707 /* Preserve the current hw state. */
2708 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2709 intel_dp->attached_connector = intel_connector;
55f78c43 2710
f0fec3f2 2711 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2712 if (intel_dpd_is_edp(dev))
ea5b213a 2713 intel_dp->is_pch_edp = true;
b329530c 2714
19c03924
GB		 2715 /*
2716 * FIXME : We need to initialize built-in panels before external panels.
2717 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2718 */
f0fec3f2 2719 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2720 type = DRM_MODE_CONNECTOR_eDP;
2721 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2722 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2723 type = DRM_MODE_CONNECTOR_eDP;
2724 intel_encoder->type = INTEL_OUTPUT_EDP;
2725 } else {
2726 type = DRM_MODE_CONNECTOR_DisplayPort;
2727 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2728 }
2729
b329530c 2730 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2731 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2732
eb1f8e4f 2733 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2734 connector->interlace_allowed = true;
2735 connector->doublescan_allowed = 0;
2736
f0fec3f2
PZ		 2737 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2738 ironlake_panel_vdd_work);
a4fc5ed6 2739
df0e9248 2740 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2741 drm_sysfs_connector_add(connector);
2742
19d8fe15 2743 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2744
a4fc5ed6 2745 /* Set up the DDC bus. */
ab9d7c30
PZ		 2746 switch (port) {
2747 case PORT_A:
2748 name = "DPDDC-A";
2749 break;
2750 case PORT_B:
2751 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2752 name = "DPDDC-B";
2753 break;
2754 case PORT_C:
2755 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2756 name = "DPDDC-C";
2757 break;
2758 case PORT_D:
2759 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2760 name = "DPDDC-D";
2761 break;
2762 default:
2763 WARN(1, "Invalid port %c\n", port_name(port));
2764 break;
5eb08b69
ZW		 2765 }
2766
67a54566
DV		 2767 if (is_edp(intel_dp))
2768 intel_dp_init_panel_power_sequencer(dev, intel_dp);
c1f05264
DA		 2769
2770 intel_dp_i2c_init(intel_dp, intel_connector, name);
2771
67a54566 2772 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2773 if (is_edp(intel_dp)) {
2774 bool ret;
f8779fda 2775 struct drm_display_mode *scan;
c1f05264 2776 struct edid *edid;
5d613501
JB		 2777
2778 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2779 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2780 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2781
59f3e272 2782 if (ret) {
7183dc29
JB		 2783 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2784 dev_priv->no_aux_handshake =
2785 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2786 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2787 } else {
3d3dc149 2788 /* if this fails, presume the device is a ghost */
48898b03 2789 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2790 intel_dp_encoder_destroy(&intel_encoder->base);
2791 intel_dp_destroy(connector);
3d3dc149 2792 return;
89667383 2793 }
89667383 2794
d6f24d0f
JB		 2795 ironlake_edp_panel_vdd_on(intel_dp);
2796 edid = drm_get_edid(connector, &intel_dp->adapter);
2797 if (edid) {
9cd300e0
JN		 2798 if (drm_add_edid_modes(connector, edid)) {
2799 drm_mode_connector_update_edid_property(connector, edid);
2800 drm_edid_to_eld(connector, edid);
2801 } else {
2802 kfree(edid);
2803 edid = ERR_PTR(-EINVAL);
2804 }
2805 } else {
2806 edid = ERR_PTR(-ENOENT);
d6f24d0f 2807 }
9cd300e0 2808 intel_connector->edid = edid;
f8779fda
JN		 2809
2810 /* prefer fixed mode from EDID if available */
2811 list_for_each_entry(scan, &connector->probed_modes, head) {
2812 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2813 fixed_mode = drm_mode_duplicate(dev, scan);
2814 break;
2815 }
2816 }
2817
2818 /* fallback to VBT if available for eDP */
2819 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2820 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2821 if (fixed_mode)
2822 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2823 }
f8779fda 2824
d6f24d0f
JB		 2825 ironlake_edp_panel_vdd_off(intel_dp, false);
2826 }
552fb0b7 2827
1d508706 2828 if (is_edp(intel_dp)) {
dd06f90e 2829 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2830 intel_panel_setup_backlight(connector);
1d508706 2831 }
32f9d658 2832
f684960e
CW		 2833 intel_dp_add_properties(intel_dp, connector);
2834
a4fc5ed6
KP		 2835 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2836 * 0xd. Failure to do so will result in spurious interrupts being
2837 * generated on the port when a cable is not attached.
2838 */
2839 if (IS_G4X(dev) && !IS_GM45(dev)) {
2840 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2841 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2842 }
2843}
f0fec3f2
PZ		 2844
2845void
2846intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2847{
2848 struct intel_digital_port *intel_dig_port;
2849 struct intel_encoder *intel_encoder;
2850 struct drm_encoder *encoder;
2851 struct intel_connector *intel_connector;
2852
2853 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2854 if (!intel_dig_port)
2855 return;
2856
2857 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2858 if (!intel_connector) {
2859 kfree(intel_dig_port);
2860 return;
2861 }
2862
2863 intel_encoder = &intel_dig_port->base;
2864 encoder = &intel_encoder->base;
2865
2866 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2867 DRM_MODE_ENCODER_TMDS);
2868
2869 if (IS_HASWELL(dev)) {
2870 drm_encoder_helper_add(&intel_encoder->base,
2871 &intel_dp_helper_funcs_hsw);
2872
2873 intel_encoder->enable = intel_enable_ddi;
2874 intel_encoder->pre_enable = intel_ddi_pre_enable;
2875 intel_encoder->disable = intel_disable_ddi;
2876 intel_encoder->post_disable = intel_ddi_post_disable;
2877 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2878 } else {
2879 drm_encoder_helper_add(&intel_encoder->base,
2880 &intel_dp_helper_funcs);
2881
2882 intel_encoder->enable = intel_enable_dp;
2883 intel_encoder->pre_enable = intel_pre_enable_dp;
2884 intel_encoder->disable = intel_disable_dp;
2885 intel_encoder->post_disable = intel_post_disable_dp;
2886 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2887 }
2888
174edf1f 2889 intel_dig_port->port = port;
f0fec3f2
PZ		 2890 intel_dig_port->dp.output_reg = output_reg;
2891
2892 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2893 intel_encoder->cloneable = false;
2894 intel_encoder->hot_plug = intel_dp_hot_plug;
2895
2896 intel_dp_init_connector(intel_dig_port, intel_connector);
2897}
Linux 6.x block layer and io_uring tree(s)