projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: quirk invert brightness for Acer Aspire 5336
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
4be73780
DV		 94static void edp_panel_vdd_on(struct intel_dp *intel_dp);
95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
d4eead50 113 break;
a4fc5ed6 114 default:
d4eead50
ID		 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
a4fc5ed6
KP		 117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121}
122
cd9dde44
AJ		 123/*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
a4fc5ed6 140static int
c898261c 141intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 142{
cd9dde44 143 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 144}
145
fe27d53e
DA		 146static int
147intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148{
149 return (max_link_clock * max_lanes * 8) / 10;
150}
151
c19de8eb 152static enum drm_mode_status
a4fc5ed6
KP		 153intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155{
df0e9248 156 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 161
dd06f90e
JN		 162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 164 return MODE_PANEL;
165
dd06f90e 166 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 167 return MODE_PANEL;
03afc4a2
DV		 168
169 target_clock = fixed_mode->clock;
7de56f43
ZY		 170 }
171
36008365
DV		 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
c4867936 179 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
0af78a2b
DV		 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
a4fc5ed6
KP		 187 return MODE_OK;
188}
189
190static uint32_t
191pack_aux(uint8_t *src, int src_bytes)
192{
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201}
202
203static void
204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205{
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211}
212
fb0f8fbf
KP		 213/* hrawclock is 1/4 the FSB frequency */
214static int
215intel_hrawclk(struct drm_device *dev)
216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
9473c8f4
VP		 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
fb0f8fbf
KP		 224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245}
246
bf13e81b
JN		 247static void
248intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251static void
252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256static enum pipe
257vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258{
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282}
283
284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285{
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292}
293
294static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302}
303
4be73780 304static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 305{
30add22d 306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 307 struct drm_i915_private *dev_priv = dev->dev_private;
308
bf13e81b 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 310}
311
4be73780 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 313{
30add22d 314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 315 struct drm_i915_private *dev_priv = dev->dev_private;
316
bf13e81b 317 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 318}
319
9b984dae
KP		 320static void
321intel_dp_check_edp(struct intel_dp *intel_dp)
322{
30add22d 323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 324 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 325
9b984dae
KP		 326 if (!is_edp(intel_dp))
327 return;
453c5420 328
4be73780 329 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 330 WARN(1, "eDP powered off while attempting aux channel communication.\n");
331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 332 I915_READ(_pp_stat_reg(intel_dp)),
333 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 334 }
335}
336
9ee32fea
DV		 337static uint32_t
338intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
339{
340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
341 struct drm_device *dev = intel_dig_port->base.base.dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 343 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 344 uint32_t status;
345 bool done;
346
ef04f00d 347#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 348 if (has_aux_irq)
b18ac466 349 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 350 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 351 else
352 done = wait_for_atomic(C, 10) == 0;
353 if (!done)
354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
355 has_aux_irq);
356#undef C
357
358 return status;
359}
360
bc86625a
CW		 361static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
362 int index)
a4fc5ed6 363{
174edf1f
PZ		 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 366 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 367
a4fc5ed6 368 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 369 * and would like to run at 2MHz. So, take the
370 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 371 *
372 * Note that PCH attached eDP panels should use a 125MHz input
373 * clock divider.
a4fc5ed6 374 */
a62d0834 375 if (IS_VALLEYVIEW(dev)) {
bc86625a 376 return index ? 0 : 100;
a62d0834 377 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 378 if (index)
379 return 0;
affa9354 380 if (HAS_DDI(dev))
bc86625a 381 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 382 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 383 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 384 else
b84a1cf8 385 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 386 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
387 /* Workaround for non-ULT HSW */
bc86625a
CW		 388 switch (index) {
389 case 0: return 63;
390 case 1: return 72;
391 default: return 0;
392 }
2c55c336 393 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 394 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 395 } else {
bc86625a 396 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 397 }
b84a1cf8
RV		 398}
399
400static int
401intel_dp_aux_ch(struct intel_dp *intel_dp,
402 uint8_t *send, int send_bytes,
403 uint8_t *recv, int recv_size)
404{
405 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
406 struct drm_device *dev = intel_dig_port->base.base.dev;
407 struct drm_i915_private *dev_priv = dev->dev_private;
408 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
409 uint32_t ch_data = ch_ctl + 4;
bc86625a 410 uint32_t aux_clock_divider;
b84a1cf8
RV		 411 int i, ret, recv_bytes;
412 uint32_t status;
bc86625a 413 int try, precharge, clock = 0;
4aeebd74 414 bool has_aux_irq = true;
a81a507d 415 uint32_t timeout;
b84a1cf8
RV		 416
417 /* dp aux is extremely sensitive to irq latency, hence request the
418 * lowest possible wakeup latency and so prevent the cpu from going into
419 * deep sleep states.
420 */
421 pm_qos_update_request(&dev_priv->pm_qos, 0);
422
423 intel_dp_check_edp(intel_dp);
5eb08b69 424
6b4e0a93
DV		 425 if (IS_GEN6(dev))
426 precharge = 3;
427 else
428 precharge = 5;
429
a81a507d
BW		 430 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
431 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
432 else
433 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
434
c67a470b
PZ		 435 intel_aux_display_runtime_get(dev_priv);
436
11bee43e
JB		 437 /* Try to wait for any previous AUX channel activity */
438 for (try = 0; try < 3; try++) {
ef04f00d 439 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 440 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
441 break;
442 msleep(1);
443 }
444
445 if (try == 3) {
446 WARN(1, "dp_aux_ch not started status 0x%08x\n",
447 I915_READ(ch_ctl));
9ee32fea
DV		 448 ret = -EBUSY;
449 goto out;
4f7f7b7e
CW		 450 }
451
46a5ae9f
PZ		 452 /* Only 5 data registers! */
453 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
454 ret = -E2BIG;
455 goto out;
456 }
457
bc86625a
CW		 458 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
459 /* Must try at least 3 times according to DP spec */
460 for (try = 0; try < 5; try++) {
461 /* Load the send data into the aux channel data registers */
462 for (i = 0; i < send_bytes; i += 4)
463 I915_WRITE(ch_data + i,
464 pack_aux(send + i, send_bytes - i));
465
466 /* Send the command and wait for it to complete */
467 I915_WRITE(ch_ctl,
468 DP_AUX_CH_CTL_SEND_BUSY |
469 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
a81a507d 470 timeout |
bc86625a
CW		 471 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
472 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
473 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
474 DP_AUX_CH_CTL_DONE |
475 DP_AUX_CH_CTL_TIME_OUT_ERROR |
476 DP_AUX_CH_CTL_RECEIVE_ERROR);
477
478 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
479
480 /* Clear done status and any errors */
481 I915_WRITE(ch_ctl,
482 status |
483 DP_AUX_CH_CTL_DONE |
484 DP_AUX_CH_CTL_TIME_OUT_ERROR |
485 DP_AUX_CH_CTL_RECEIVE_ERROR);
486
487 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
488 DP_AUX_CH_CTL_RECEIVE_ERROR))
489 continue;
490 if (status & DP_AUX_CH_CTL_DONE)
491 break;
492 }
4f7f7b7e 493 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 494 break;
495 }
496
a4fc5ed6 497 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 498 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 499 ret = -EBUSY;
500 goto out;
a4fc5ed6
KP		 501 }
502
503 /* Check for timeout or receive error.
504 * Timeouts occur when the sink is not connected
505 */
a5b3da54 506 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 507 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 508 ret = -EIO;
509 goto out;
a5b3da54 510 }
1ae8c0a5
KP		 511
512 /* Timeouts occur when the device isn't connected, so they're
513 * "normal" -- don't fill the kernel log with these */
a5b3da54 514 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 515 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 516 ret = -ETIMEDOUT;
517 goto out;
a4fc5ed6
KP		 518 }
519
520 /* Unload any bytes sent back from the other side */
521 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
522 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 523 if (recv_bytes > recv_size)
524 recv_bytes = recv_size;
0206e353 525
4f7f7b7e
CW		 526 for (i = 0; i < recv_bytes; i += 4)
527 unpack_aux(I915_READ(ch_data + i),
528 recv + i, recv_bytes - i);
a4fc5ed6 529
9ee32fea
DV		 530 ret = recv_bytes;
531out:
532 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 533 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 534
535 return ret;
a4fc5ed6
KP		 536}
537
538/* Write data to the aux channel in native mode */
539static int
ea5b213a 540intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 541 uint16_t address, uint8_t *send, int send_bytes)
542{
543 int ret;
544 uint8_t msg[20];
545 int msg_bytes;
546 uint8_t ack;
547
46a5ae9f
PZ		 548 if (WARN_ON(send_bytes > 16))
549 return -E2BIG;
550
9b984dae 551 intel_dp_check_edp(intel_dp);
6b27f7f0 552 msg[0] = DP_AUX_NATIVE_WRITE << 4;
a4fc5ed6 553 msg[1] = address >> 8;
eebc863e 554 msg[2] = address & 0xff;
a4fc5ed6
KP		 555 msg[3] = send_bytes - 1;
556 memcpy(&msg[4], send, send_bytes);
557 msg_bytes = send_bytes + 4;
558 for (;;) {
ea5b213a 559 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 560 if (ret < 0)
561 return ret;
6b27f7f0
TR		 562 ack >>= 4;
563 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
a4fc5ed6 564 break;
6b27f7f0 565 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 566 udelay(100);
567 else
a5b3da54 568 return -EIO;
a4fc5ed6
KP		 569 }
570 return send_bytes;
571}
572
573/* Write a single byte to the aux channel in native mode */
574static int
ea5b213a 575intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 576 uint16_t address, uint8_t byte)
577{
ea5b213a 578 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 579}
580
581/* read bytes from a native aux channel */
582static int
ea5b213a 583intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 584 uint16_t address, uint8_t *recv, int recv_bytes)
585{
586 uint8_t msg[4];
587 int msg_bytes;
588 uint8_t reply[20];
589 int reply_bytes;
590 uint8_t ack;
591 int ret;
592
46a5ae9f
PZ		 593 if (WARN_ON(recv_bytes > 19))
594 return -E2BIG;
595
9b984dae 596 intel_dp_check_edp(intel_dp);
6b27f7f0 597 msg[0] = DP_AUX_NATIVE_READ << 4;
a4fc5ed6
KP		 598 msg[1] = address >> 8;
599 msg[2] = address & 0xff;
600 msg[3] = recv_bytes - 1;
601
602 msg_bytes = 4;
603 reply_bytes = recv_bytes + 1;
604
605 for (;;) {
ea5b213a 606 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 607 reply, reply_bytes);
a5b3da54
KP		 608 if (ret == 0)
609 return -EPROTO;
610 if (ret < 0)
a4fc5ed6 611 return ret;
6b27f7f0
TR		 612 ack = reply[0] >> 4;
613 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
a4fc5ed6
KP		 614 memcpy(recv, reply + 1, ret - 1);
615 return ret - 1;
616 }
6b27f7f0 617 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 618 udelay(100);
619 else
a5b3da54 620 return -EIO;
a4fc5ed6
KP		 621 }
622}
623
624static int
ab2c0672
DA		 625intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
626 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 627{
ab2c0672 628 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 629 struct intel_dp *intel_dp = container_of(adapter,
630 struct intel_dp,
631 adapter);
ab2c0672
DA		 632 uint16_t address = algo_data->address;
633 uint8_t msg[5];
634 uint8_t reply[2];
8316f337 635 unsigned retry;
ab2c0672
DA		 636 int msg_bytes;
637 int reply_bytes;
638 int ret;
639
4be73780 640 edp_panel_vdd_on(intel_dp);
9b984dae 641 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 642 /* Set up the command byte */
643 if (mode & MODE_I2C_READ)
6b27f7f0 644 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 645 else
6b27f7f0 646 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 647
648 if (!(mode & MODE_I2C_STOP))
6b27f7f0 649 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 650
ab2c0672
DA		 651 msg[1] = address >> 8;
652 msg[2] = address;
653
654 switch (mode) {
655 case MODE_I2C_WRITE:
656 msg[3] = 0;
657 msg[4] = write_byte;
658 msg_bytes = 5;
659 reply_bytes = 1;
660 break;
661 case MODE_I2C_READ:
662 msg[3] = 0;
663 msg_bytes = 4;
664 reply_bytes = 2;
665 break;
666 default:
667 msg_bytes = 3;
668 reply_bytes = 1;
669 break;
670 }
671
58c67ce9
JN		 672 /*
673 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
674 * required to retry at least seven times upon receiving AUX_DEFER
675 * before giving up the AUX transaction.
676 */
677 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 678 ret = intel_dp_aux_ch(intel_dp,
679 msg, msg_bytes,
680 reply, reply_bytes);
ab2c0672 681 if (ret < 0) {
3ff99164 682 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 683 goto out;
ab2c0672 684 }
8316f337 685
6b27f7f0
TR		 686 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
687 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 688 /* I2C-over-AUX Reply field is only valid
689 * when paired with AUX ACK.
690 */
691 break;
6b27f7f0 692 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 693 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 694 ret = -EREMOTEIO;
695 goto out;
6b27f7f0 696 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 697 /*
698 * For now, just give more slack to branch devices. We
699 * could check the DPCD for I2C bit rate capabilities,
700 * and if available, adjust the interval. We could also
701 * be more careful with DP-to-Legacy adapters where a
702 * long legacy cable may force very low I2C bit rates.
703 */
704 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
705 DP_DWN_STRM_PORT_PRESENT)
706 usleep_range(500, 600);
707 else
708 usleep_range(300, 400);
8316f337
DF		 709 continue;
710 default:
711 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
712 reply[0]);
8a5e6aeb
PZ		 713 ret = -EREMOTEIO;
714 goto out;
8316f337
DF		 715 }
716
6b27f7f0
TR		 717 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
718 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 719 if (mode == MODE_I2C_READ) {
720 *read_byte = reply[1];
721 }
8a5e6aeb
PZ		 722 ret = reply_bytes - 1;
723 goto out;
6b27f7f0 724 case DP_AUX_I2C_REPLY_NACK:
8316f337 725 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 726 ret = -EREMOTEIO;
727 goto out;
6b27f7f0 728 case DP_AUX_I2C_REPLY_DEFER:
8316f337 729 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 730 udelay(100);
731 break;
732 default:
8316f337 733 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 734 ret = -EREMOTEIO;
735 goto out;
ab2c0672
DA		 736 }
737 }
8316f337
DF		 738
739 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 740 ret = -EREMOTEIO;
741
742out:
4be73780 743 edp_panel_vdd_off(intel_dp, false);
8a5e6aeb 744 return ret;
a4fc5ed6
KP		 745}
746
747static int
ea5b213a 748intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 749 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 750{
0b5c541b
KP		 751 int ret;
752
d54e9d28 753 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 754 intel_dp->algo.running = false;
755 intel_dp->algo.address = 0;
756 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
757
0206e353 758 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 759 intel_dp->adapter.owner = THIS_MODULE;
760 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 761 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 762 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
763 intel_dp->adapter.algo_data = &intel_dp->algo;
5bdebb18 764 intel_dp->adapter.dev.parent = intel_connector->base.kdev;
ea5b213a 765
0b5c541b 766 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
0b5c541b 767 return ret;
a4fc5ed6
KP		 768}
769
c6bb3538
DV		 770static void
771intel_dp_set_clock(struct intel_encoder *encoder,
772 struct intel_crtc_config *pipe_config, int link_bw)
773{
774 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 775 const struct dp_link_dpll *divisor = NULL;
776 int i, count = 0;
c6bb3538
DV		 777
778 if (IS_G4X(dev)) {
9dd4ffdf
CML		 779 divisor = gen4_dpll;
780 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 781 } else if (IS_HASWELL(dev)) {
782 /* Haswell has special-purpose DP DDI clocks. */
783 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 784 divisor = pch_dpll;
785 count = ARRAY_SIZE(pch_dpll);
c6bb3538 786 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 787 divisor = vlv_dpll;
788 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 789 }
9dd4ffdf
CML		 790
791 if (divisor && count) {
792 for (i = 0; i < count; i++) {
793 if (link_bw == divisor[i].link_bw) {
794 pipe_config->dpll = divisor[i].dpll;
795 pipe_config->clock_set = true;
796 break;
797 }
798 }
c6bb3538
DV		 799 }
800}
801
00c09d70 802bool
5bfe2ac0
DV		 803intel_dp_compute_config(struct intel_encoder *encoder,
804 struct intel_crtc_config *pipe_config)
a4fc5ed6 805{
5bfe2ac0 806 struct drm_device *dev = encoder->base.dev;
36008365 807 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 808 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 810 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 811 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 812 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 813 int lane_count, clock;
397fe157 814 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 815 /* Conveniently, the link BW constants become indices with a shift...*/
816 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 817 int bpp, mode_rate;
06ea66b6 818 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 819 int link_avail, link_clock;
a4fc5ed6 820
bc7d38a4 821 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 822 pipe_config->has_pch_encoder = true;
823
03afc4a2 824 pipe_config->has_dp_encoder = true;
a4fc5ed6 825
dd06f90e
JN		 826 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
827 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
828 adjusted_mode);
2dd24552
JB		 829 if (!HAS_PCH_SPLIT(dev))
830 intel_gmch_panel_fitting(intel_crtc, pipe_config,
831 intel_connector->panel.fitting_mode);
832 else
b074cec8
JB		 833 intel_pch_panel_fitting(intel_crtc, pipe_config,
834 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 835 }
836
cb1793ce 837 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 838 return false;
839
083f9560
DV		 840 DRM_DEBUG_KMS("DP link computation with max lane count %i "
841 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 842 max_lane_count, bws[max_clock],
843 adjusted_mode->crtc_clock);
083f9560 844
36008365
DV		 845 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
846 * bpc in between. */
3e7ca985 847 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 848 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
849 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 850 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
851 dev_priv->vbt.edp_bpp);
6da7f10d 852 bpp = dev_priv->vbt.edp_bpp;
7984211e 853 }
657445fe 854
36008365 855 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 856 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
857 bpp);
36008365
DV		 858
859 for (clock = 0; clock <= max_clock; clock++) {
860 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
861 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
862 link_avail = intel_dp_max_data_rate(link_clock,
863 lane_count);
864
865 if (mode_rate <= link_avail) {
866 goto found;
867 }
868 }
869 }
870 }
c4867936 871
36008365 872 return false;
3685a8f3 873
36008365 874found:
55bc60db
VS		 875 if (intel_dp->color_range_auto) {
876 /*
877 * See:
878 * CEA-861-E - 5.1 Default Encoding Parameters
879 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
880 */
18316c8c 881 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 882 intel_dp->color_range = DP_COLOR_RANGE_16_235;
883 else
884 intel_dp->color_range = 0;
885 }
886
3685a8f3 887 if (intel_dp->color_range)
50f3b016 888 pipe_config->limited_color_range = true;
a4fc5ed6 889
36008365
DV		 890 intel_dp->link_bw = bws[clock];
891 intel_dp->lane_count = lane_count;
657445fe 892 pipe_config->pipe_bpp = bpp;
ff9a6750 893 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 894
36008365
DV		 895 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
896 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 897 pipe_config->port_clock, bpp);
36008365
DV		 898 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
899 mode_rate, link_avail);
a4fc5ed6 900
03afc4a2 901 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 902 adjusted_mode->crtc_clock,
903 pipe_config->port_clock,
03afc4a2 904 &pipe_config->dp_m_n);
9d1a455b 905
c6bb3538
DV		 906 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
907
03afc4a2 908 return true;
a4fc5ed6
KP		 909}
910
7c62a164 911static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 912{
7c62a164
DV		 913 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
914 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
915 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 916 struct drm_i915_private *dev_priv = dev->dev_private;
917 u32 dpa_ctl;
918
ff9a6750 919 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 920 dpa_ctl = I915_READ(DP_A);
921 dpa_ctl &= ~DP_PLL_FREQ_MASK;
922
ff9a6750 923 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 924 /* For a long time we've carried around a ILK-DevA w/a for the
925 * 160MHz clock. If we're really unlucky, it's still required.
926 */
927 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 928 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 929 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 930 } else {
931 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 932 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 933 }
1ce17038 934
ea9b6006
DV		 935 I915_WRITE(DP_A, dpa_ctl);
936
937 POSTING_READ(DP_A);
938 udelay(500);
939}
940
b934223d 941static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 942{
b934223d 943 struct drm_device *dev = encoder->base.dev;
417e822d 944 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 945 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 946 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 947 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
948 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 949
417e822d 950 /*
1a2eb460 951 * There are four kinds of DP registers:
417e822d
KP		 952 *
953 * IBX PCH
1a2eb460
KP		 954 * SNB CPU
955 * IVB CPU
417e822d
KP		 956 * CPT PCH
957 *
958 * IBX PCH and CPU are the same for almost everything,
959 * except that the CPU DP PLL is configured in this
960 * register
961 *
962 * CPT PCH is quite different, having many bits moved
963 * to the TRANS_DP_CTL register instead. That
964 * configuration happens (oddly) in ironlake_pch_enable
965 */
9c9e7927 966
417e822d
KP		 967 /* Preserve the BIOS-computed detected bit. This is
968 * supposed to be read-only.
969 */
970 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 971
417e822d 972 /* Handle DP bits in common between all three register formats */
417e822d 973 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 974 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 975
e0dac65e
WF		 976 if (intel_dp->has_audio) {
977 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 978 pipe_name(crtc->pipe));
ea5b213a 979 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 980 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 981 }
247d89f6 982
417e822d 983 /* Split out the IBX/CPU vs CPT settings */
32f9d658 984
bc7d38a4 985 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 986 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
987 intel_dp->DP |= DP_SYNC_HS_HIGH;
988 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
989 intel_dp->DP |= DP_SYNC_VS_HIGH;
990 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
991
6aba5b6c 992 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 993 intel_dp->DP |= DP_ENHANCED_FRAMING;
994
7c62a164 995 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 996 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 997 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 998 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 999
1000 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1001 intel_dp->DP |= DP_SYNC_HS_HIGH;
1002 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1003 intel_dp->DP |= DP_SYNC_VS_HIGH;
1004 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1005
6aba5b6c 1006 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1007 intel_dp->DP |= DP_ENHANCED_FRAMING;
1008
7c62a164 1009 if (crtc->pipe == 1)
417e822d 1010 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1011 } else {
1012 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1013 }
ea9b6006 1014
bc7d38a4 1015 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1016 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1017}
1018
ffd6749d
PZ		 1019#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1020#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1021
1a5ef5b7
PZ		 1022#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1023#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1024
ffd6749d
PZ		 1025#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1026#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1027
4be73780 1028static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1029 u32 mask,
1030 u32 value)
bd943159 1031{
30add22d 1032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1033 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1034 u32 pp_stat_reg, pp_ctrl_reg;
1035
bf13e81b
JN		 1036 pp_stat_reg = _pp_stat_reg(intel_dp);
1037 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1038
99ea7127 1039 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1040 mask, value,
1041 I915_READ(pp_stat_reg),
1042 I915_READ(pp_ctrl_reg));
32ce697c 1043
453c5420 1044 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1045 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1046 I915_READ(pp_stat_reg),
1047 I915_READ(pp_ctrl_reg));
32ce697c 1048 }
54c136d4
CW		 1049
1050 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1051}
32ce697c 1052
4be73780 1053static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1054{
1055 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1056 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1057}
1058
4be73780 1059static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1060{
1061 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1062 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1063}
1064
4be73780 1065static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1066{
1067 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1068
1069 /* When we disable the VDD override bit last we have to do the manual
1070 * wait. */
1071 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1072 intel_dp->panel_power_cycle_delay);
1073
4be73780 1074 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1075}
1076
4be73780 1077static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1078{
1079 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1080 intel_dp->backlight_on_delay);
1081}
1082
4be73780 1083static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1084{
1085 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1086 intel_dp->backlight_off_delay);
1087}
99ea7127 1088
832dd3c1
KP		 1089/* Read the current pp_control value, unlocking the register if it
1090 * is locked
1091 */
1092
453c5420 1093static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1094{
453c5420
JB		 1095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 u32 control;
832dd3c1 1098
bf13e81b 1099 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1100 control &= ~PANEL_UNLOCK_MASK;
1101 control |= PANEL_UNLOCK_REGS;
1102 return control;
bd943159
KP		 1103}
1104
4be73780 1105static void edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1106{
30add22d 1107 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1108 struct drm_i915_private *dev_priv = dev->dev_private;
1109 u32 pp;
453c5420 1110 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1111
97af61f5
KP		 1112 if (!is_edp(intel_dp))
1113 return;
5d613501 1114
bd943159
KP		 1115 WARN(intel_dp->want_panel_vdd,
1116 "eDP VDD already requested on\n");
1117
1118 intel_dp->want_panel_vdd = true;
99ea7127 1119
4be73780 1120 if (edp_have_panel_vdd(intel_dp))
bd943159 1121 return;
b0665d57 1122
e9cb81a2
PZ		 1123 intel_runtime_pm_get(dev_priv);
1124
b0665d57 1125 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1126
4be73780
DV		 1127 if (!edp_have_panel_power(intel_dp))
1128 wait_panel_power_cycle(intel_dp);
99ea7127 1129
453c5420 1130 pp = ironlake_get_pp_control(intel_dp);
5d613501 1131 pp |= EDP_FORCE_VDD;
ebf33b18 1132
bf13e81b
JN		 1133 pp_stat_reg = _pp_stat_reg(intel_dp);
1134 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1135
1136 I915_WRITE(pp_ctrl_reg, pp);
1137 POSTING_READ(pp_ctrl_reg);
1138 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1139 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1140 /*
1141 * If the panel wasn't on, delay before accessing aux channel
1142 */
4be73780 1143 if (!edp_have_panel_power(intel_dp)) {
bd943159 1144 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1145 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1146 }
5d613501
JB		 1147}
1148
4be73780 1149static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1150{
30add22d 1151 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 u32 pp;
453c5420 1154 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1155
a0e99e68
DV		 1156 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1157
4be73780 1158 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1159 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1160
453c5420 1161 pp = ironlake_get_pp_control(intel_dp);
bd943159 1162 pp &= ~EDP_FORCE_VDD;
bd943159 1163
9f08ef59
PZ		 1164 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1165 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1166
1167 I915_WRITE(pp_ctrl_reg, pp);
1168 POSTING_READ(pp_ctrl_reg);
99ea7127 1169
453c5420
JB		 1170 /* Make sure sequencer is idle before allowing subsequent activity */
1171 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1172 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1173
1174 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1175 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1176
1177 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1178 }
1179}
5d613501 1180
4be73780 1181static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1182{
1183 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1184 struct intel_dp, panel_vdd_work);
30add22d 1185 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1186
627f7675 1187 mutex_lock(&dev->mode_config.mutex);
4be73780 1188 edp_panel_vdd_off_sync(intel_dp);
627f7675 1189 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1190}
1191
4be73780 1192static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1193{
97af61f5
KP		 1194 if (!is_edp(intel_dp))
1195 return;
5d613501 1196
bd943159 1197 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1198
bd943159
KP		 1199 intel_dp->want_panel_vdd = false;
1200
1201 if (sync) {
4be73780 1202 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1203 } else {
1204 /*
1205 * Queue the timer to fire a long
1206 * time from now (relative to the power down delay)
1207 * to keep the panel power up across a sequence of operations
1208 */
1209 schedule_delayed_work(&intel_dp->panel_vdd_work,
1210 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1211 }
5d613501
JB		 1212}
1213
4be73780 1214void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1215{
30add22d 1216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1217 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1218 u32 pp;
453c5420 1219 u32 pp_ctrl_reg;
9934c132 1220
97af61f5 1221 if (!is_edp(intel_dp))
bd943159 1222 return;
99ea7127
KP		 1223
1224 DRM_DEBUG_KMS("Turn eDP power on\n");
1225
4be73780 1226 if (edp_have_panel_power(intel_dp)) {
99ea7127 1227 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1228 return;
99ea7127 1229 }
9934c132 1230
4be73780 1231 wait_panel_power_cycle(intel_dp);
37c6c9b0 1232
bf13e81b 1233 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1234 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1235 if (IS_GEN5(dev)) {
1236 /* ILK workaround: disable reset around power sequence */
1237 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1238 I915_WRITE(pp_ctrl_reg, pp);
1239 POSTING_READ(pp_ctrl_reg);
05ce1a49 1240 }
37c6c9b0 1241
1c0ae80a 1242 pp |= POWER_TARGET_ON;
99ea7127
KP		 1243 if (!IS_GEN5(dev))
1244 pp |= PANEL_POWER_RESET;
1245
453c5420
JB		 1246 I915_WRITE(pp_ctrl_reg, pp);
1247 POSTING_READ(pp_ctrl_reg);
9934c132 1248
4be73780 1249 wait_panel_on(intel_dp);
dce56b3c 1250 intel_dp->last_power_on = jiffies;
9934c132 1251
05ce1a49
KP		 1252 if (IS_GEN5(dev)) {
1253 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1254 I915_WRITE(pp_ctrl_reg, pp);
1255 POSTING_READ(pp_ctrl_reg);
05ce1a49 1256 }
9934c132
JB		 1257}
1258
4be73780 1259void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1260{
30add22d 1261 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1262 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1263 u32 pp;
453c5420 1264 u32 pp_ctrl_reg;
9934c132 1265
97af61f5
KP		 1266 if (!is_edp(intel_dp))
1267 return;
37c6c9b0 1268
99ea7127 1269 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1270
4be73780 1271 edp_wait_backlight_off(intel_dp);
dce56b3c 1272
453c5420 1273 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1274 /* We need to switch off panel power _and_ force vdd, for otherwise some
1275 * panels get very unhappy and cease to work. */
dff392db 1276 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1277
bf13e81b 1278 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1279
1280 I915_WRITE(pp_ctrl_reg, pp);
1281 POSTING_READ(pp_ctrl_reg);
9934c132 1282
dce56b3c 1283 intel_dp->last_power_cycle = jiffies;
4be73780 1284 wait_panel_off(intel_dp);
9934c132
JB		 1285}
1286
4be73780 1287void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1288{
da63a9f2
PZ		 1289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1290 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1291 struct drm_i915_private *dev_priv = dev->dev_private;
1292 u32 pp;
453c5420 1293 u32 pp_ctrl_reg;
32f9d658 1294
f01eca2e
KP		 1295 if (!is_edp(intel_dp))
1296 return;
1297
28c97730 1298 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1299 /*
1300 * If we enable the backlight right away following a panel power
1301 * on, we may see slight flicker as the panel syncs with the eDP
1302 * link. So delay a bit to make sure the image is solid before
1303 * allowing it to appear.
1304 */
4be73780 1305 wait_backlight_on(intel_dp);
453c5420 1306 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1307 pp |= EDP_BLC_ENABLE;
453c5420 1308
bf13e81b 1309 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1310
1311 I915_WRITE(pp_ctrl_reg, pp);
1312 POSTING_READ(pp_ctrl_reg);
035aa3de 1313
752aa88a 1314 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1315}
1316
4be73780 1317void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1318{
30add22d 1319 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321 u32 pp;
453c5420 1322 u32 pp_ctrl_reg;
32f9d658 1323
f01eca2e
KP		 1324 if (!is_edp(intel_dp))
1325 return;
1326
752aa88a 1327 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1328
28c97730 1329 DRM_DEBUG_KMS("\n");
453c5420 1330 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1331 pp &= ~EDP_BLC_ENABLE;
453c5420 1332
bf13e81b 1333 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1334
1335 I915_WRITE(pp_ctrl_reg, pp);
1336 POSTING_READ(pp_ctrl_reg);
dce56b3c 1337 intel_dp->last_backlight_off = jiffies;
32f9d658 1338}
a4fc5ed6 1339
2bd2ad64 1340static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1341{
da63a9f2
PZ		 1342 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1343 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1344 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 u32 dpa_ctl;
1347
2bd2ad64
DV		 1348 assert_pipe_disabled(dev_priv,
1349 to_intel_crtc(crtc)->pipe);
1350
d240f20f
JB		 1351 DRM_DEBUG_KMS("\n");
1352 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1353 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1354 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1355
1356 /* We don't adjust intel_dp->DP while tearing down the link, to
1357 * facilitate link retraining (e.g. after hotplug). Hence clear all
1358 * enable bits here to ensure that we don't enable too much. */
1359 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1360 intel_dp->DP |= DP_PLL_ENABLE;
1361 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1362 POSTING_READ(DP_A);
1363 udelay(200);
d240f20f
JB		 1364}
1365
2bd2ad64 1366static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1367{
da63a9f2
PZ		 1368 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1369 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1370 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 u32 dpa_ctl;
1373
2bd2ad64
DV		 1374 assert_pipe_disabled(dev_priv,
1375 to_intel_crtc(crtc)->pipe);
1376
d240f20f 1377 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1378 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1379 "dp pll off, should be on\n");
1380 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1381
1382 /* We can't rely on the value tracked for the DP register in
1383 * intel_dp->DP because link_down must not change that (otherwise link
1384 * re-training will fail. */
298b0b39 1385 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1386 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1387 POSTING_READ(DP_A);
d240f20f
JB		 1388 udelay(200);
1389}
1390
c7ad3810 1391/* If the sink supports it, try to set the power state appropriately */
c19b0669 1392void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1393{
1394 int ret, i;
1395
1396 /* Should have a valid DPCD by this point */
1397 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1398 return;
1399
1400 if (mode != DRM_MODE_DPMS_ON) {
1401 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1402 DP_SET_POWER_D3);
1403 if (ret != 1)
1404 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1405 } else {
1406 /*
1407 * When turning on, we need to retry for 1ms to give the sink
1408 * time to wake up.
1409 */
1410 for (i = 0; i < 3; i++) {
1411 ret = intel_dp_aux_native_write_1(intel_dp,
1412 DP_SET_POWER,
1413 DP_SET_POWER_D0);
1414 if (ret == 1)
1415 break;
1416 msleep(1);
1417 }
1418 }
1419}
1420
19d8fe15
DV		 1421static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1422 enum pipe *pipe)
d240f20f 1423{
19d8fe15 1424 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1425 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1426 struct drm_device *dev = encoder->base.dev;
1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 u32 tmp = I915_READ(intel_dp->output_reg);
1429
1430 if (!(tmp & DP_PORT_EN))
1431 return false;
1432
bc7d38a4 1433 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1434 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1435 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1436 *pipe = PORT_TO_PIPE(tmp);
1437 } else {
1438 u32 trans_sel;
1439 u32 trans_dp;
1440 int i;
1441
1442 switch (intel_dp->output_reg) {
1443 case PCH_DP_B:
1444 trans_sel = TRANS_DP_PORT_SEL_B;
1445 break;
1446 case PCH_DP_C:
1447 trans_sel = TRANS_DP_PORT_SEL_C;
1448 break;
1449 case PCH_DP_D:
1450 trans_sel = TRANS_DP_PORT_SEL_D;
1451 break;
1452 default:
1453 return true;
1454 }
1455
1456 for_each_pipe(i) {
1457 trans_dp = I915_READ(TRANS_DP_CTL(i));
1458 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1459 *pipe = i;
1460 return true;
1461 }
1462 }
19d8fe15 1463
4a0833ec
DV		 1464 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1465 intel_dp->output_reg);
1466 }
d240f20f 1467
19d8fe15
DV		 1468 return true;
1469}
d240f20f 1470
045ac3b5
JB		 1471static void intel_dp_get_config(struct intel_encoder *encoder,
1472 struct intel_crtc_config *pipe_config)
1473{
1474 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1475 u32 tmp, flags = 0;
63000ef6
XZ		 1476 struct drm_device *dev = encoder->base.dev;
1477 struct drm_i915_private *dev_priv = dev->dev_private;
1478 enum port port = dp_to_dig_port(intel_dp)->port;
1479 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1480 int dotclock;
045ac3b5 1481
63000ef6
XZ		 1482 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1483 tmp = I915_READ(intel_dp->output_reg);
1484 if (tmp & DP_SYNC_HS_HIGH)
1485 flags |= DRM_MODE_FLAG_PHSYNC;
1486 else
1487 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1488
63000ef6
XZ		 1489 if (tmp & DP_SYNC_VS_HIGH)
1490 flags |= DRM_MODE_FLAG_PVSYNC;
1491 else
1492 flags |= DRM_MODE_FLAG_NVSYNC;
1493 } else {
1494 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1495 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1496 flags |= DRM_MODE_FLAG_PHSYNC;
1497 else
1498 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1499
63000ef6
XZ		 1500 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1501 flags |= DRM_MODE_FLAG_PVSYNC;
1502 else
1503 flags |= DRM_MODE_FLAG_NVSYNC;
1504 }
045ac3b5
JB		 1505
1506 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1507
eb14cb74
VS		 1508 pipe_config->has_dp_encoder = true;
1509
1510 intel_dp_get_m_n(crtc, pipe_config);
1511
18442d08 1512 if (port == PORT_A) {
f1f644dc
JB		 1513 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1514 pipe_config->port_clock = 162000;
1515 else
1516 pipe_config->port_clock = 270000;
1517 }
18442d08
VS		 1518
1519 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1520 &pipe_config->dp_m_n);
1521
1522 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1523 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1524
241bfc38 1525 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1526
c6cd2ee2
JN		 1527 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1528 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1529 /*
1530 * This is a big fat ugly hack.
1531 *
1532 * Some machines in UEFI boot mode provide us a VBT that has 18
1533 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1534 * unknown we fail to light up. Yet the same BIOS boots up with
1535 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1536 * max, not what it tells us to use.
1537 *
1538 * Note: This will still be broken if the eDP panel is not lit
1539 * up by the BIOS, and thus we can't get the mode at module
1540 * load.
1541 */
1542 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1543 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1544 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1545 }
045ac3b5
JB		 1546}
1547
a031d709 1548static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1549{
a031d709
RV		 1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551
1552 return dev_priv->psr.sink_support;
2293bb5c
SK		 1553}
1554
2b28bb1b
RV		 1555static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1556{
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558
18b5992c 1559 if (!HAS_PSR(dev))
2b28bb1b
RV		 1560 return false;
1561
18b5992c 1562 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1563}
1564
1565static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1566 struct edp_vsc_psr *vsc_psr)
1567{
1568 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1569 struct drm_device *dev = dig_port->base.base.dev;
1570 struct drm_i915_private *dev_priv = dev->dev_private;
1571 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1572 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1573 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1574 uint32_t *data = (uint32_t *) vsc_psr;
1575 unsigned int i;
1576
1577 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1578 the video DIP being updated before program video DIP data buffer
1579 registers for DIP being updated. */
1580 I915_WRITE(ctl_reg, 0);
1581 POSTING_READ(ctl_reg);
1582
1583 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1584 if (i < sizeof(struct edp_vsc_psr))
1585 I915_WRITE(data_reg + i, *data++);
1586 else
1587 I915_WRITE(data_reg + i, 0);
1588 }
1589
1590 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1591 POSTING_READ(ctl_reg);
1592}
1593
1594static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1595{
1596 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 struct edp_vsc_psr psr_vsc;
1599
1600 if (intel_dp->psr_setup_done)
1601 return;
1602
1603 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1604 memset(&psr_vsc, 0, sizeof(psr_vsc));
1605 psr_vsc.sdp_header.HB0 = 0;
1606 psr_vsc.sdp_header.HB1 = 0x7;
1607 psr_vsc.sdp_header.HB2 = 0x2;
1608 psr_vsc.sdp_header.HB3 = 0x8;
1609 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1610
1611 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1612 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1613 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1614
1615 intel_dp->psr_setup_done = true;
1616}
1617
1618static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1619{
1620 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1621 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1622 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1623 int precharge = 0x3;
1624 int msg_size = 5; /* Header(4) + Message(1) */
1625
1626 /* Enable PSR in sink */
1627 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1628 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1629 DP_PSR_ENABLE &
1630 ~DP_PSR_MAIN_LINK_ACTIVE);
1631 else
1632 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1633 DP_PSR_ENABLE |
1634 DP_PSR_MAIN_LINK_ACTIVE);
1635
1636 /* Setup AUX registers */
18b5992c
BW		 1637 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1638 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1639 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1640 DP_AUX_CH_CTL_TIME_OUT_400us |
1641 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1642 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1643 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1644}
1645
1646static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1647{
1648 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 uint32_t max_sleep_time = 0x1f;
1651 uint32_t idle_frames = 1;
1652 uint32_t val = 0x0;
ed8546ac 1653 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1654
1655 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1656 val |= EDP_PSR_LINK_STANDBY;
1657 val |= EDP_PSR_TP2_TP3_TIME_0us;
1658 val |= EDP_PSR_TP1_TIME_0us;
1659 val |= EDP_PSR_SKIP_AUX_EXIT;
1660 } else
1661 val |= EDP_PSR_LINK_DISABLE;
1662
18b5992c 1663 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1664 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1665 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1666 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1667 EDP_PSR_ENABLE);
1668}
1669
3f51e471
RV		 1670static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1671{
1672 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1673 struct drm_device *dev = dig_port->base.base.dev;
1674 struct drm_i915_private *dev_priv = dev->dev_private;
1675 struct drm_crtc *crtc = dig_port->base.base.crtc;
1676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1677 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1678 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1679
a031d709
RV		 1680 dev_priv->psr.source_ok = false;
1681
18b5992c 1682 if (!HAS_PSR(dev)) {
3f51e471 1683 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1684 return false;
1685 }
1686
1687 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1688 (dig_port->port != PORT_A)) {
1689 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1690 return false;
1691 }
1692
105b7c11
RV		 1693 if (!i915_enable_psr) {
1694 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1695 return false;
1696 }
1697
cd234b0b
CW		 1698 crtc = dig_port->base.base.crtc;
1699 if (crtc == NULL) {
1700 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1701 return false;
1702 }
1703
1704 intel_crtc = to_intel_crtc(crtc);
20ddf665 1705 if (!intel_crtc_active(crtc)) {
3f51e471 1706 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1707 return false;
1708 }
1709
cd234b0b 1710 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1711 if (obj->tiling_mode != I915_TILING_X ||
1712 obj->fence_reg == I915_FENCE_REG_NONE) {
1713 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1714 return false;
1715 }
1716
1717 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1718 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1719 return false;
1720 }
1721
1722 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1723 S3D_ENABLE) {
1724 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1725 return false;
1726 }
1727
ca73b4f0 1728 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1729 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1730 return false;
1731 }
1732
a031d709 1733 dev_priv->psr.source_ok = true;
3f51e471
RV		 1734 return true;
1735}
1736
3d739d92 1737static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1738{
1739 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1740
3f51e471
RV		 1741 if (!intel_edp_psr_match_conditions(intel_dp) ||
1742 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1743 return;
1744
1745 /* Setup PSR once */
1746 intel_edp_psr_setup(intel_dp);
1747
1748 /* Enable PSR on the panel */
1749 intel_edp_psr_enable_sink(intel_dp);
1750
1751 /* Enable PSR on the host */
1752 intel_edp_psr_enable_source(intel_dp);
1753}
1754
3d739d92
RV		 1755void intel_edp_psr_enable(struct intel_dp *intel_dp)
1756{
1757 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1758
1759 if (intel_edp_psr_match_conditions(intel_dp) &&
1760 !intel_edp_is_psr_enabled(dev))
1761 intel_edp_psr_do_enable(intel_dp);
1762}
1763
2b28bb1b
RV		 1764void intel_edp_psr_disable(struct intel_dp *intel_dp)
1765{
1766 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768
1769 if (!intel_edp_is_psr_enabled(dev))
1770 return;
1771
18b5992c
BW		 1772 I915_WRITE(EDP_PSR_CTL(dev),
1773 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1774
1775 /* Wait till PSR is idle */
18b5992c 1776 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1777 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1778 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1779}
1780
3d739d92
RV		 1781void intel_edp_psr_update(struct drm_device *dev)
1782{
1783 struct intel_encoder *encoder;
1784 struct intel_dp *intel_dp = NULL;
1785
1786 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1787 if (encoder->type == INTEL_OUTPUT_EDP) {
1788 intel_dp = enc_to_intel_dp(&encoder->base);
1789
a031d709 1790 if (!is_edp_psr(dev))
3d739d92
RV		 1791 return;
1792
1793 if (!intel_edp_psr_match_conditions(intel_dp))
1794 intel_edp_psr_disable(intel_dp);
1795 else
1796 if (!intel_edp_is_psr_enabled(dev))
1797 intel_edp_psr_do_enable(intel_dp);
1798 }
1799}
1800
e8cb4558 1801static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1802{
e8cb4558 1803 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1804 enum port port = dp_to_dig_port(intel_dp)->port;
1805 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1806
1807 /* Make sure the panel is off before trying to change the mode. But also
1808 * ensure that we have vdd while we switch off the panel. */
4be73780 1809 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1810 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1811 intel_edp_panel_off(intel_dp);
3739850b
DV		 1812
1813 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1814 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1815 intel_dp_link_down(intel_dp);
d240f20f
JB		 1816}
1817
2bd2ad64 1818static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1819{
2bd2ad64 1820 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1821 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1822 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1823
982a3866 1824 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1825 intel_dp_link_down(intel_dp);
b2634017
JB		 1826 if (!IS_VALLEYVIEW(dev))
1827 ironlake_edp_pll_off(intel_dp);
3739850b 1828 }
2bd2ad64
DV		 1829}
1830
e8cb4558 1831static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1832{
e8cb4558
DV		 1833 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1834 struct drm_device *dev = encoder->base.dev;
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1837
0c33d8d7
DV		 1838 if (WARN_ON(dp_reg & DP_PORT_EN))
1839 return;
5d613501 1840
4be73780 1841 edp_panel_vdd_on(intel_dp);
f01eca2e 1842 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1843 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1844 intel_edp_panel_on(intel_dp);
1845 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1846 intel_dp_complete_link_train(intel_dp);
3ab9c637 1847 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1848}
89b667f8 1849
ecff4f3b
JN		 1850static void g4x_enable_dp(struct intel_encoder *encoder)
1851{
828f5c6e
JN		 1852 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1853
ecff4f3b 1854 intel_enable_dp(encoder);
4be73780 1855 intel_edp_backlight_on(intel_dp);
ab1f90f9 1856}
89b667f8 1857
ab1f90f9
JN		 1858static void vlv_enable_dp(struct intel_encoder *encoder)
1859{
828f5c6e
JN		 1860 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1861
4be73780 1862 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1863}
1864
ecff4f3b 1865static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1866{
1867 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1868 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1869
1870 if (dport->port == PORT_A)
1871 ironlake_edp_pll_on(intel_dp);
1872}
1873
1874static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1875{
2bd2ad64 1876 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1877 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1878 struct drm_device *dev = encoder->base.dev;
89b667f8 1879 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1880 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1881 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1882 int pipe = intel_crtc->pipe;
bf13e81b 1883 struct edp_power_seq power_seq;
ab1f90f9 1884 u32 val;
a4fc5ed6 1885
ab1f90f9 1886 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1887
ab3c759a 1888 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1889 val = 0;
1890 if (pipe)
1891 val |= (1<<21);
1892 else
1893 val &= ~(1<<21);
1894 val |= 0x001000c4;
ab3c759a
CML		 1895 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1896 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1897 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1898
ab1f90f9
JN		 1899 mutex_unlock(&dev_priv->dpio_lock);
1900
bf13e81b
JN		 1901 /* init power sequencer on this pipe and port */
1902 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1903 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1904 &power_seq);
1905
ab1f90f9
JN		 1906 intel_enable_dp(encoder);
1907
e4607fcf 1908 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1909}
1910
ecff4f3b 1911static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1912{
1913 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1914 struct drm_device *dev = encoder->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1916 struct intel_crtc *intel_crtc =
1917 to_intel_crtc(encoder->base.crtc);
e4607fcf 1918 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1919 int pipe = intel_crtc->pipe;
89b667f8 1920
89b667f8 1921 /* Program Tx lane resets to default */
0980a60f 1922 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1923 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1924 DPIO_PCS_TX_LANE2_RESET |
1925 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1926 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1927 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1928 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1929 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1930 DPIO_PCS_CLK_SOFT_RESET);
1931
1932 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1933 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1934 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1935 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1936 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1937}
1938
1939/*
df0c237d
JB		 1940 * Native read with retry for link status and receiver capability reads for
1941 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1942 */
1943static bool
df0c237d
JB		 1944intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1945 uint8_t *recv, int recv_bytes)
a4fc5ed6 1946{
61da5fab
JB		 1947 int ret, i;
1948
df0c237d
JB		 1949 /*
1950 * Sinks are *supposed* to come up within 1ms from an off state,
1951 * but we're also supposed to retry 3 times per the spec.
1952 */
61da5fab 1953 for (i = 0; i < 3; i++) {
df0c237d
JB		 1954 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1955 recv_bytes);
1956 if (ret == recv_bytes)
61da5fab
JB		 1957 return true;
1958 msleep(1);
1959 }
a4fc5ed6 1960
61da5fab 1961 return false;
a4fc5ed6
KP		 1962}
1963
1964/*
1965 * Fetch AUX CH registers 0x202 - 0x207 which contain
1966 * link status information
1967 */
1968static bool
93f62dad 1969intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1970{
df0c237d
JB		 1971 return intel_dp_aux_native_read_retry(intel_dp,
1972 DP_LANE0_1_STATUS,
93f62dad 1973 link_status,
df0c237d 1974 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1975}
1976
a4fc5ed6
KP		 1977/*
1978 * These are source-specific values; current Intel hardware supports
1979 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1980 */
a4fc5ed6
KP		 1981
1982static uint8_t
1a2eb460 1983intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1984{
30add22d 1985 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1986 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1987
8f93f4f1 1988 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1989 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1990 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1991 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1992 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1993 return DP_TRAIN_VOLTAGE_SWING_1200;
1994 else
1995 return DP_TRAIN_VOLTAGE_SWING_800;
1996}
1997
1998static uint8_t
1999intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2000{
30add22d 2001 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2002 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2003
8f93f4f1
PZ		 2004 if (IS_BROADWELL(dev)) {
2005 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2006 case DP_TRAIN_VOLTAGE_SWING_400:
2007 case DP_TRAIN_VOLTAGE_SWING_600:
2008 return DP_TRAIN_PRE_EMPHASIS_6;
2009 case DP_TRAIN_VOLTAGE_SWING_800:
2010 return DP_TRAIN_PRE_EMPHASIS_3_5;
2011 case DP_TRAIN_VOLTAGE_SWING_1200:
2012 default:
2013 return DP_TRAIN_PRE_EMPHASIS_0;
2014 }
2015 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2016 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2017 case DP_TRAIN_VOLTAGE_SWING_400:
2018 return DP_TRAIN_PRE_EMPHASIS_9_5;
2019 case DP_TRAIN_VOLTAGE_SWING_600:
2020 return DP_TRAIN_PRE_EMPHASIS_6;
2021 case DP_TRAIN_VOLTAGE_SWING_800:
2022 return DP_TRAIN_PRE_EMPHASIS_3_5;
2023 case DP_TRAIN_VOLTAGE_SWING_1200:
2024 default:
2025 return DP_TRAIN_PRE_EMPHASIS_0;
2026 }
e2fa6fba
P		 2027 } else if (IS_VALLEYVIEW(dev)) {
2028 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2029 case DP_TRAIN_VOLTAGE_SWING_400:
2030 return DP_TRAIN_PRE_EMPHASIS_9_5;
2031 case DP_TRAIN_VOLTAGE_SWING_600:
2032 return DP_TRAIN_PRE_EMPHASIS_6;
2033 case DP_TRAIN_VOLTAGE_SWING_800:
2034 return DP_TRAIN_PRE_EMPHASIS_3_5;
2035 case DP_TRAIN_VOLTAGE_SWING_1200:
2036 default:
2037 return DP_TRAIN_PRE_EMPHASIS_0;
2038 }
bc7d38a4 2039 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2040 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2041 case DP_TRAIN_VOLTAGE_SWING_400:
2042 return DP_TRAIN_PRE_EMPHASIS_6;
2043 case DP_TRAIN_VOLTAGE_SWING_600:
2044 case DP_TRAIN_VOLTAGE_SWING_800:
2045 return DP_TRAIN_PRE_EMPHASIS_3_5;
2046 default:
2047 return DP_TRAIN_PRE_EMPHASIS_0;
2048 }
2049 } else {
2050 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2051 case DP_TRAIN_VOLTAGE_SWING_400:
2052 return DP_TRAIN_PRE_EMPHASIS_6;
2053 case DP_TRAIN_VOLTAGE_SWING_600:
2054 return DP_TRAIN_PRE_EMPHASIS_6;
2055 case DP_TRAIN_VOLTAGE_SWING_800:
2056 return DP_TRAIN_PRE_EMPHASIS_3_5;
2057 case DP_TRAIN_VOLTAGE_SWING_1200:
2058 default:
2059 return DP_TRAIN_PRE_EMPHASIS_0;
2060 }
a4fc5ed6
KP		 2061 }
2062}
2063
e2fa6fba
P		 2064static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2065{
2066 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2069 struct intel_crtc *intel_crtc =
2070 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2071 unsigned long demph_reg_value, preemph_reg_value,
2072 uniqtranscale_reg_value;
2073 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2074 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2075 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2076
2077 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2078 case DP_TRAIN_PRE_EMPHASIS_0:
2079 preemph_reg_value = 0x0004000;
2080 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2081 case DP_TRAIN_VOLTAGE_SWING_400:
2082 demph_reg_value = 0x2B405555;
2083 uniqtranscale_reg_value = 0x552AB83A;
2084 break;
2085 case DP_TRAIN_VOLTAGE_SWING_600:
2086 demph_reg_value = 0x2B404040;
2087 uniqtranscale_reg_value = 0x5548B83A;
2088 break;
2089 case DP_TRAIN_VOLTAGE_SWING_800:
2090 demph_reg_value = 0x2B245555;
2091 uniqtranscale_reg_value = 0x5560B83A;
2092 break;
2093 case DP_TRAIN_VOLTAGE_SWING_1200:
2094 demph_reg_value = 0x2B405555;
2095 uniqtranscale_reg_value = 0x5598DA3A;
2096 break;
2097 default:
2098 return 0;
2099 }
2100 break;
2101 case DP_TRAIN_PRE_EMPHASIS_3_5:
2102 preemph_reg_value = 0x0002000;
2103 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2104 case DP_TRAIN_VOLTAGE_SWING_400:
2105 demph_reg_value = 0x2B404040;
2106 uniqtranscale_reg_value = 0x5552B83A;
2107 break;
2108 case DP_TRAIN_VOLTAGE_SWING_600:
2109 demph_reg_value = 0x2B404848;
2110 uniqtranscale_reg_value = 0x5580B83A;
2111 break;
2112 case DP_TRAIN_VOLTAGE_SWING_800:
2113 demph_reg_value = 0x2B404040;
2114 uniqtranscale_reg_value = 0x55ADDA3A;
2115 break;
2116 default:
2117 return 0;
2118 }
2119 break;
2120 case DP_TRAIN_PRE_EMPHASIS_6:
2121 preemph_reg_value = 0x0000000;
2122 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2123 case DP_TRAIN_VOLTAGE_SWING_400:
2124 demph_reg_value = 0x2B305555;
2125 uniqtranscale_reg_value = 0x5570B83A;
2126 break;
2127 case DP_TRAIN_VOLTAGE_SWING_600:
2128 demph_reg_value = 0x2B2B4040;
2129 uniqtranscale_reg_value = 0x55ADDA3A;
2130 break;
2131 default:
2132 return 0;
2133 }
2134 break;
2135 case DP_TRAIN_PRE_EMPHASIS_9_5:
2136 preemph_reg_value = 0x0006000;
2137 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2138 case DP_TRAIN_VOLTAGE_SWING_400:
2139 demph_reg_value = 0x1B405555;
2140 uniqtranscale_reg_value = 0x55ADDA3A;
2141 break;
2142 default:
2143 return 0;
2144 }
2145 break;
2146 default:
2147 return 0;
2148 }
2149
0980a60f 2150 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2151 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2152 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2153 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2154 uniqtranscale_reg_value);
ab3c759a
CML		 2155 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2156 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2157 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2158 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2159 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2160
2161 return 0;
2162}
2163
a4fc5ed6 2164static void
0301b3ac
JN		 2165intel_get_adjust_train(struct intel_dp *intel_dp,
2166 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2167{
2168 uint8_t v = 0;
2169 uint8_t p = 0;
2170 int lane;
1a2eb460
KP		 2171 uint8_t voltage_max;
2172 uint8_t preemph_max;
a4fc5ed6 2173
33a34e4e 2174 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2175 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2176 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2177
2178 if (this_v > v)
2179 v = this_v;
2180 if (this_p > p)
2181 p = this_p;
2182 }
2183
1a2eb460 2184 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2185 if (v >= voltage_max)
2186 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2187
1a2eb460
KP		 2188 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2189 if (p >= preemph_max)
2190 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2191
2192 for (lane = 0; lane < 4; lane++)
33a34e4e 2193 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2194}
2195
2196static uint32_t
f0a3424e 2197intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2198{
3cf2efb1 2199 uint32_t signal_levels = 0;
a4fc5ed6 2200
3cf2efb1 2201 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2202 case DP_TRAIN_VOLTAGE_SWING_400:
2203 default:
2204 signal_levels |= DP_VOLTAGE_0_4;
2205 break;
2206 case DP_TRAIN_VOLTAGE_SWING_600:
2207 signal_levels |= DP_VOLTAGE_0_6;
2208 break;
2209 case DP_TRAIN_VOLTAGE_SWING_800:
2210 signal_levels |= DP_VOLTAGE_0_8;
2211 break;
2212 case DP_TRAIN_VOLTAGE_SWING_1200:
2213 signal_levels |= DP_VOLTAGE_1_2;
2214 break;
2215 }
3cf2efb1 2216 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2217 case DP_TRAIN_PRE_EMPHASIS_0:
2218 default:
2219 signal_levels |= DP_PRE_EMPHASIS_0;
2220 break;
2221 case DP_TRAIN_PRE_EMPHASIS_3_5:
2222 signal_levels |= DP_PRE_EMPHASIS_3_5;
2223 break;
2224 case DP_TRAIN_PRE_EMPHASIS_6:
2225 signal_levels |= DP_PRE_EMPHASIS_6;
2226 break;
2227 case DP_TRAIN_PRE_EMPHASIS_9_5:
2228 signal_levels |= DP_PRE_EMPHASIS_9_5;
2229 break;
2230 }
2231 return signal_levels;
2232}
2233
e3421a18
ZW		 2234/* Gen6's DP voltage swing and pre-emphasis control */
2235static uint32_t
2236intel_gen6_edp_signal_levels(uint8_t train_set)
2237{
3c5a62b5
YL		 2238 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2239 DP_TRAIN_PRE_EMPHASIS_MASK);
2240 switch (signal_levels) {
e3421a18 2241 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2242 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2243 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2244 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2245 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2246 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2247 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2248 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2249 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2250 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2251 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2252 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2253 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2254 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2255 default:
3c5a62b5
YL		 2256 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2257 "0x%x\n", signal_levels);
2258 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2259 }
2260}
2261
1a2eb460
KP		 2262/* Gen7's DP voltage swing and pre-emphasis control */
2263static uint32_t
2264intel_gen7_edp_signal_levels(uint8_t train_set)
2265{
2266 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2267 DP_TRAIN_PRE_EMPHASIS_MASK);
2268 switch (signal_levels) {
2269 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2270 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2271 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2272 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2273 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2274 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2275
2276 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2277 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2278 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2279 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2280
2281 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2282 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2283 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2284 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2285
2286 default:
2287 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2288 "0x%x\n", signal_levels);
2289 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2290 }
2291}
2292
d6c0d722
PZ		 2293/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2294static uint32_t
f0a3424e 2295intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2296{
d6c0d722
PZ		 2297 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2298 DP_TRAIN_PRE_EMPHASIS_MASK);
2299 switch (signal_levels) {
2300 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2301 return DDI_BUF_EMP_400MV_0DB_HSW;
2302 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2303 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2305 return DDI_BUF_EMP_400MV_6DB_HSW;
2306 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2307 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2308
d6c0d722
PZ		 2309 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2310 return DDI_BUF_EMP_600MV_0DB_HSW;
2311 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2312 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2313 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2314 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2315
d6c0d722
PZ		 2316 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2317 return DDI_BUF_EMP_800MV_0DB_HSW;
2318 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2319 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2320 default:
2321 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2322 "0x%x\n", signal_levels);
2323 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2324 }
a4fc5ed6
KP		 2325}
2326
8f93f4f1
PZ		 2327static uint32_t
2328intel_bdw_signal_levels(uint8_t train_set)
2329{
2330 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2331 DP_TRAIN_PRE_EMPHASIS_MASK);
2332 switch (signal_levels) {
2333 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2334 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2335 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2336 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2337 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2338 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2339
2340 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2341 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2342 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2343 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2344 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2345 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2346
2347 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2348 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2349 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2350 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2351
2352 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2353 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2354
2355 default:
2356 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2357 "0x%x\n", signal_levels);
2358 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2359 }
2360}
2361
f0a3424e
PZ		 2362/* Properly updates "DP" with the correct signal levels. */
2363static void
2364intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2365{
2366 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2367 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2368 struct drm_device *dev = intel_dig_port->base.base.dev;
2369 uint32_t signal_levels, mask;
2370 uint8_t train_set = intel_dp->train_set[0];
2371
8f93f4f1
PZ		 2372 if (IS_BROADWELL(dev)) {
2373 signal_levels = intel_bdw_signal_levels(train_set);
2374 mask = DDI_BUF_EMP_MASK;
2375 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2376 signal_levels = intel_hsw_signal_levels(train_set);
2377 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2378 } else if (IS_VALLEYVIEW(dev)) {
2379 signal_levels = intel_vlv_signal_levels(intel_dp);
2380 mask = 0;
bc7d38a4 2381 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2382 signal_levels = intel_gen7_edp_signal_levels(train_set);
2383 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2384 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2385 signal_levels = intel_gen6_edp_signal_levels(train_set);
2386 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2387 } else {
2388 signal_levels = intel_gen4_signal_levels(train_set);
2389 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2390 }
2391
2392 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2393
2394 *DP = (*DP & ~mask) | signal_levels;
2395}
2396
a4fc5ed6 2397static bool
ea5b213a 2398intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2399 uint32_t *DP,
58e10eb9 2400 uint8_t dp_train_pat)
a4fc5ed6 2401{
174edf1f
PZ		 2402 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2403 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2404 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2405 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2406 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2407 int ret, len;
a4fc5ed6 2408
22b8bf17 2409 if (HAS_DDI(dev)) {
3ab9c637 2410 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2411
2412 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2413 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2414 else
2415 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2416
2417 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2418 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2419 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2420 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2421
2422 break;
2423 case DP_TRAINING_PATTERN_1:
2424 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2425 break;
2426 case DP_TRAINING_PATTERN_2:
2427 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2428 break;
2429 case DP_TRAINING_PATTERN_3:
2430 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2431 break;
2432 }
174edf1f 2433 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2434
bc7d38a4 2435 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2436 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2437
2438 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2439 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2440 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2441 break;
2442 case DP_TRAINING_PATTERN_1:
70aff66c 2443 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2444 break;
2445 case DP_TRAINING_PATTERN_2:
70aff66c 2446 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2447 break;
2448 case DP_TRAINING_PATTERN_3:
2449 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2450 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2451 break;
2452 }
2453
2454 } else {
70aff66c 2455 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2456
2457 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2458 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2459 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2460 break;
2461 case DP_TRAINING_PATTERN_1:
70aff66c 2462 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2463 break;
2464 case DP_TRAINING_PATTERN_2:
70aff66c 2465 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2466 break;
2467 case DP_TRAINING_PATTERN_3:
2468 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2469 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2470 break;
2471 }
2472 }
2473
70aff66c 2474 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2475 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2476
2cdfe6c8
JN		 2477 buf[0] = dp_train_pat;
2478 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2479 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2480 /* don't write DP_TRAINING_LANEx_SET on disable */
2481 len = 1;
2482 } else {
2483 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2484 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2485 len = intel_dp->lane_count + 1;
47ea7542 2486 }
a4fc5ed6 2487
2cdfe6c8
JN		 2488 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2489 buf, len);
2490
2491 return ret == len;
a4fc5ed6
KP		 2492}
2493
70aff66c
JN		 2494static bool
2495intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2496 uint8_t dp_train_pat)
2497{
953d22e8 2498 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2499 intel_dp_set_signal_levels(intel_dp, DP);
2500 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2501}
2502
2503static bool
2504intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2505 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2506{
2507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2508 struct drm_device *dev = intel_dig_port->base.base.dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 int ret;
2511
2512 intel_get_adjust_train(intel_dp, link_status);
2513 intel_dp_set_signal_levels(intel_dp, DP);
2514
2515 I915_WRITE(intel_dp->output_reg, *DP);
2516 POSTING_READ(intel_dp->output_reg);
2517
2518 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2519 intel_dp->train_set,
2520 intel_dp->lane_count);
2521
2522 return ret == intel_dp->lane_count;
2523}
2524
3ab9c637
ID		 2525static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2526{
2527 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2528 struct drm_device *dev = intel_dig_port->base.base.dev;
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 enum port port = intel_dig_port->port;
2531 uint32_t val;
2532
2533 if (!HAS_DDI(dev))
2534 return;
2535
2536 val = I915_READ(DP_TP_CTL(port));
2537 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2538 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2539 I915_WRITE(DP_TP_CTL(port), val);
2540
2541 /*
2542 * On PORT_A we can have only eDP in SST mode. There the only reason
2543 * we need to set idle transmission mode is to work around a HW issue
2544 * where we enable the pipe while not in idle link-training mode.
2545 * In this case there is requirement to wait for a minimum number of
2546 * idle patterns to be sent.
2547 */
2548 if (port == PORT_A)
2549 return;
2550
2551 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2552 1))
2553 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2554}
2555
33a34e4e 2556/* Enable corresponding port and start training pattern 1 */
c19b0669 2557void
33a34e4e 2558intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2559{
da63a9f2 2560 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2561 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2562 int i;
2563 uint8_t voltage;
cdb0e95b 2564 int voltage_tries, loop_tries;
ea5b213a 2565 uint32_t DP = intel_dp->DP;
6aba5b6c 2566 uint8_t link_config[2];
a4fc5ed6 2567
affa9354 2568 if (HAS_DDI(dev))
c19b0669
PZ		 2569 intel_ddi_prepare_link_retrain(encoder);
2570
3cf2efb1 2571 /* Write the link configuration data */
6aba5b6c
JN		 2572 link_config[0] = intel_dp->link_bw;
2573 link_config[1] = intel_dp->lane_count;
2574 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2575 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2576 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2577
2578 link_config[0] = 0;
2579 link_config[1] = DP_SET_ANSI_8B10B;
2580 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2581
2582 DP |= DP_PORT_EN;
1a2eb460 2583
70aff66c
JN		 2584 /* clock recovery */
2585 if (!intel_dp_reset_link_train(intel_dp, &DP,
2586 DP_TRAINING_PATTERN_1 |
2587 DP_LINK_SCRAMBLING_DISABLE)) {
2588 DRM_ERROR("failed to enable link training\n");
2589 return;
2590 }
2591
a4fc5ed6 2592 voltage = 0xff;
cdb0e95b
KP		 2593 voltage_tries = 0;
2594 loop_tries = 0;
a4fc5ed6 2595 for (;;) {
70aff66c 2596 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2597
a7c9655f 2598 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2599 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2600 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2601 break;
93f62dad 2602 }
a4fc5ed6 2603
01916270 2604 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2605 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2606 break;
2607 }
2608
2609 /* Check to see if we've tried the max voltage */
2610 for (i = 0; i < intel_dp->lane_count; i++)
2611 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2612 break;
3b4f819d 2613 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2614 ++loop_tries;
2615 if (loop_tries == 5) {
3def84b3 2616 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2617 break;
2618 }
70aff66c
JN		 2619 intel_dp_reset_link_train(intel_dp, &DP,
2620 DP_TRAINING_PATTERN_1 |
2621 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2622 voltage_tries = 0;
2623 continue;
2624 }
a4fc5ed6 2625
3cf2efb1 2626 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2627 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2628 ++voltage_tries;
b06fbda3 2629 if (voltage_tries == 5) {
3def84b3 2630 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2631 break;
2632 }
2633 } else
2634 voltage_tries = 0;
2635 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2636
70aff66c
JN		 2637 /* Update training set as requested by target */
2638 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2639 DRM_ERROR("failed to update link training\n");
2640 break;
2641 }
a4fc5ed6
KP		 2642 }
2643
33a34e4e
JB		 2644 intel_dp->DP = DP;
2645}
2646
c19b0669 2647void
33a34e4e
JB		 2648intel_dp_complete_link_train(struct intel_dp *intel_dp)
2649{
33a34e4e 2650 bool channel_eq = false;
37f80975 2651 int tries, cr_tries;
33a34e4e 2652 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2653 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2654
2655 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2656 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2657 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2658
a4fc5ed6 2659 /* channel equalization */
70aff66c 2660 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2661 training_pattern |
70aff66c
JN		 2662 DP_LINK_SCRAMBLING_DISABLE)) {
2663 DRM_ERROR("failed to start channel equalization\n");
2664 return;
2665 }
2666
a4fc5ed6 2667 tries = 0;
37f80975 2668 cr_tries = 0;
a4fc5ed6
KP		 2669 channel_eq = false;
2670 for (;;) {
70aff66c 2671 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2672
37f80975
JB		 2673 if (cr_tries > 5) {
2674 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2675 break;
2676 }
2677
a7c9655f 2678 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2679 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2680 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2681 break;
70aff66c 2682 }
a4fc5ed6 2683
37f80975 2684 /* Make sure clock is still ok */
01916270 2685 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2686 intel_dp_start_link_train(intel_dp);
70aff66c 2687 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2688 training_pattern |
70aff66c 2689 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2690 cr_tries++;
2691 continue;
2692 }
2693
1ffdff13 2694 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2695 channel_eq = true;
2696 break;
2697 }
a4fc5ed6 2698
37f80975
JB		 2699 /* Try 5 times, then try clock recovery if that fails */
2700 if (tries > 5) {
2701 intel_dp_link_down(intel_dp);
2702 intel_dp_start_link_train(intel_dp);
70aff66c 2703 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2704 training_pattern |
70aff66c 2705 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2706 tries = 0;
2707 cr_tries++;
2708 continue;
2709 }
a4fc5ed6 2710
70aff66c
JN		 2711 /* Update training set as requested by target */
2712 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2713 DRM_ERROR("failed to update link training\n");
2714 break;
2715 }
3cf2efb1 2716 ++tries;
869184a6 2717 }
3cf2efb1 2718
3ab9c637
ID		 2719 intel_dp_set_idle_link_train(intel_dp);
2720
2721 intel_dp->DP = DP;
2722
d6c0d722 2723 if (channel_eq)
07f42258 2724 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2725
3ab9c637
ID		 2726}
2727
2728void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2729{
70aff66c 2730 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2731 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2732}
2733
2734static void
ea5b213a 2735intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2736{
da63a9f2 2737 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2738 enum port port = intel_dig_port->port;
da63a9f2 2739 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2740 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2741 struct intel_crtc *intel_crtc =
2742 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2743 uint32_t DP = intel_dp->DP;
a4fc5ed6 2744
c19b0669
PZ		 2745 /*
2746 * DDI code has a strict mode set sequence and we should try to respect
2747 * it, otherwise we might hang the machine in many different ways. So we
2748 * really should be disabling the port only on a complete crtc_disable
2749 * sequence. This function is just called under two conditions on DDI
2750 * code:
2751 * - Link train failed while doing crtc_enable, and on this case we
2752 * really should respect the mode set sequence and wait for a
2753 * crtc_disable.
2754 * - Someone turned the monitor off and intel_dp_check_link_status
2755 * called us. We don't need to disable the whole port on this case, so
2756 * when someone turns the monitor on again,
2757 * intel_ddi_prepare_link_retrain will take care of redoing the link
2758 * train.
2759 */
affa9354 2760 if (HAS_DDI(dev))
c19b0669
PZ		 2761 return;
2762
0c33d8d7 2763 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2764 return;
2765
28c97730 2766 DRM_DEBUG_KMS("\n");
32f9d658 2767
bc7d38a4 2768 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2769 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2770 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2771 } else {
2772 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2773 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2774 }
fe255d00 2775 POSTING_READ(intel_dp->output_reg);
5eb08b69 2776
ab527efc
DV		 2777 /* We don't really know why we're doing this */
2778 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2779
493a7081 2780 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2781 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2782 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2783
5bddd17f
EA		 2784 /* Hardware workaround: leaving our transcoder select
2785 * set to transcoder B while it's off will prevent the
2786 * corresponding HDMI output on transcoder A.
2787 *
2788 * Combine this with another hardware workaround:
2789 * transcoder select bit can only be cleared while the
2790 * port is enabled.
2791 */
2792 DP &= ~DP_PIPEB_SELECT;
2793 I915_WRITE(intel_dp->output_reg, DP);
2794
2795 /* Changes to enable or select take place the vblank
2796 * after being written.
2797 */
ff50afe9
DV		 2798 if (WARN_ON(crtc == NULL)) {
2799 /* We should never try to disable a port without a crtc
2800 * attached. For paranoia keep the code around for a
2801 * bit. */
31acbcc4
CW		 2802 POSTING_READ(intel_dp->output_reg);
2803 msleep(50);
2804 } else
ab527efc 2805 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2806 }
2807
832afda6 2808 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2809 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2810 POSTING_READ(intel_dp->output_reg);
f01eca2e 2811 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2812}
2813
26d61aad
KP		 2814static bool
2815intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2816{
a031d709
RV		 2817 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2818 struct drm_device *dev = dig_port->base.base.dev;
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820
577c7a50
DL		 2821 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2822
92fd8fd1 2823 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2824 sizeof(intel_dp->dpcd)) == 0)
2825 return false; /* aux transfer failed */
92fd8fd1 2826
577c7a50
DL		 2827 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2828 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2829 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2830
edb39244
AJ		 2831 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2832 return false; /* DPCD not present */
2833
2293bb5c
SK		 2834 /* Check if the panel supports PSR */
2835 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2836 if (is_edp(intel_dp)) {
2837 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2838 intel_dp->psr_dpcd,
2839 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2840 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2841 dev_priv->psr.sink_support = true;
50003939 2842 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2843 }
50003939
JN		 2844 }
2845
06ea66b6
TP		 2846 /* Training Pattern 3 support */
2847 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2848 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2849 intel_dp->use_tps3 = true;
2850 DRM_DEBUG_KMS("Displayport TPS3 supported");
2851 } else
2852 intel_dp->use_tps3 = false;
2853
edb39244
AJ		 2854 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2855 DP_DWN_STRM_PORT_PRESENT))
2856 return true; /* native DP sink */
2857
2858 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2859 return true; /* no per-port downstream info */
2860
2861 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2862 intel_dp->downstream_ports,
2863 DP_MAX_DOWNSTREAM_PORTS) == 0)
2864 return false; /* downstream port status fetch failed */
2865
2866 return true;
92fd8fd1
KP		 2867}
2868
0d198328
AJ		 2869static void
2870intel_dp_probe_oui(struct intel_dp *intel_dp)
2871{
2872 u8 buf[3];
2873
2874 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2875 return;
2876
4be73780 2877 edp_panel_vdd_on(intel_dp);
351cfc34 2878
0d198328
AJ		 2879 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2880 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2881 buf[0], buf[1], buf[2]);
2882
2883 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2884 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2885 buf[0], buf[1], buf[2]);
351cfc34 2886
4be73780 2887 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2888}
2889
a60f0e38
JB		 2890static bool
2891intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2892{
2893 int ret;
2894
2895 ret = intel_dp_aux_native_read_retry(intel_dp,
2896 DP_DEVICE_SERVICE_IRQ_VECTOR,
2897 sink_irq_vector, 1);
2898 if (!ret)
2899 return false;
2900
2901 return true;
2902}
2903
2904static void
2905intel_dp_handle_test_request(struct intel_dp *intel_dp)
2906{
2907 /* NAK by default */
9324cf7f 2908 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2909}
2910
a4fc5ed6
KP		 2911/*
2912 * According to DP spec
2913 * 5.1.2:
2914 * 1. Read DPCD
2915 * 2. Configure link according to Receiver Capabilities
2916 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2917 * 4. Check link status on receipt of hot-plug interrupt
2918 */
2919
00c09d70 2920void
ea5b213a 2921intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2922{
da63a9f2 2923 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2924 u8 sink_irq_vector;
93f62dad 2925 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2926
da63a9f2 2927 if (!intel_encoder->connectors_active)
d2b996ac 2928 return;
59cd09e1 2929
da63a9f2 2930 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2931 return;
2932
92fd8fd1 2933 /* Try to read receiver status if the link appears to be up */
93f62dad 2934 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2935 return;
2936 }
2937
92fd8fd1 2938 /* Now read the DPCD to see if it's actually running */
26d61aad 2939 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2940 return;
2941 }
2942
a60f0e38
JB		 2943 /* Try to read the source of the interrupt */
2944 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2945 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2946 /* Clear interrupt source */
2947 intel_dp_aux_native_write_1(intel_dp,
2948 DP_DEVICE_SERVICE_IRQ_VECTOR,
2949 sink_irq_vector);
2950
2951 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2952 intel_dp_handle_test_request(intel_dp);
2953 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2954 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2955 }
2956
1ffdff13 2957 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2958 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2959 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2960 intel_dp_start_link_train(intel_dp);
2961 intel_dp_complete_link_train(intel_dp);
3ab9c637 2962 intel_dp_stop_link_train(intel_dp);
33a34e4e 2963 }
a4fc5ed6 2964}
a4fc5ed6 2965
caf9ab24 2966/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2967static enum drm_connector_status
26d61aad 2968intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2969{
caf9ab24 2970 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2971 uint8_t type;
2972
2973 if (!intel_dp_get_dpcd(intel_dp))
2974 return connector_status_disconnected;
2975
2976 /* if there's no downstream port, we're done */
2977 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2978 return connector_status_connected;
caf9ab24
AJ		 2979
2980 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2981 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2982 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2983 uint8_t reg;
caf9ab24 2984 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2985 &reg, 1))
caf9ab24 2986 return connector_status_unknown;
23235177
AJ		 2987 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2988 : connector_status_disconnected;
caf9ab24
AJ		 2989 }
2990
2991 /* If no HPD, poke DDC gently */
2992 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2993 return connector_status_connected;
caf9ab24
AJ		 2994
2995 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 2996 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2997 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2998 if (type == DP_DS_PORT_TYPE_VGA ||
2999 type == DP_DS_PORT_TYPE_NON_EDID)
3000 return connector_status_unknown;
3001 } else {
3002 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3003 DP_DWN_STRM_PORT_TYPE_MASK;
3004 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3005 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3006 return connector_status_unknown;
3007 }
caf9ab24
AJ		 3008
3009 /* Anything else is out of spec, warn and ignore */
3010 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3011 return connector_status_disconnected;
71ba9000
AJ		 3012}
3013
5eb08b69 3014static enum drm_connector_status
a9756bb5 3015ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3016{
30add22d 3017 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3018 struct drm_i915_private *dev_priv = dev->dev_private;
3019 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3020 enum drm_connector_status status;
3021
fe16d949
CW		 3022 /* Can't disconnect eDP, but you can close the lid... */
3023 if (is_edp(intel_dp)) {
30add22d 3024 status = intel_panel_detect(dev);
fe16d949
CW		 3025 if (status == connector_status_unknown)
3026 status = connector_status_connected;
3027 return status;
3028 }
01cb9ea6 3029
1b469639
DL		 3030 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3031 return connector_status_disconnected;
3032
26d61aad 3033 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3034}
3035
a4fc5ed6 3036static enum drm_connector_status
a9756bb5 3037g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3038{
30add22d 3039 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3040 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3041 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3042 uint32_t bit;
5eb08b69 3043
35aad75f
JB		 3044 /* Can't disconnect eDP, but you can close the lid... */
3045 if (is_edp(intel_dp)) {
3046 enum drm_connector_status status;
3047
3048 status = intel_panel_detect(dev);
3049 if (status == connector_status_unknown)
3050 status = connector_status_connected;
3051 return status;
3052 }
3053
232a6ee9
TP		 3054 if (IS_VALLEYVIEW(dev)) {
3055 switch (intel_dig_port->port) {
3056 case PORT_B:
3057 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3058 break;
3059 case PORT_C:
3060 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3061 break;
3062 case PORT_D:
3063 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3064 break;
3065 default:
3066 return connector_status_unknown;
3067 }
3068 } else {
3069 switch (intel_dig_port->port) {
3070 case PORT_B:
3071 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3072 break;
3073 case PORT_C:
3074 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3075 break;
3076 case PORT_D:
3077 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3078 break;
3079 default:
3080 return connector_status_unknown;
3081 }
a4fc5ed6
KP		 3082 }
3083
10f76a38 3084 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3085 return connector_status_disconnected;
3086
26d61aad 3087 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3088}
3089
8c241fef
KP		 3090static struct edid *
3091intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3092{
9cd300e0 3093 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3094
9cd300e0
JN		 3095 /* use cached edid if we have one */
3096 if (intel_connector->edid) {
9cd300e0
JN		 3097 /* invalid edid */
3098 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3099 return NULL;
3100
55e9edeb 3101 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3102 }
8c241fef 3103
9cd300e0 3104 return drm_get_edid(connector, adapter);
8c241fef
KP		 3105}
3106
3107static int
3108intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3109{
9cd300e0 3110 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3111
9cd300e0
JN		 3112 /* use cached edid if we have one */
3113 if (intel_connector->edid) {
3114 /* invalid edid */
3115 if (IS_ERR(intel_connector->edid))
3116 return 0;
3117
3118 return intel_connector_update_modes(connector,
3119 intel_connector->edid);
d6f24d0f
JB		 3120 }
3121
9cd300e0 3122 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3123}
3124
a9756bb5
ZW		 3125static enum drm_connector_status
3126intel_dp_detect(struct drm_connector *connector, bool force)
3127{
3128 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3129 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3130 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3131 struct drm_device *dev = connector->dev;
c8c8fb33 3132 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5
ZW		 3133 enum drm_connector_status status;
3134 struct edid *edid = NULL;
3135
c8c8fb33
PZ		 3136 intel_runtime_pm_get(dev_priv);
3137
164c8598
CW		 3138 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3139 connector->base.id, drm_get_connector_name(connector));
3140
a9756bb5
ZW		 3141 intel_dp->has_audio = false;
3142
3143 if (HAS_PCH_SPLIT(dev))
3144 status = ironlake_dp_detect(intel_dp);
3145 else
3146 status = g4x_dp_detect(intel_dp);
1b9be9d0 3147
a9756bb5 3148 if (status != connector_status_connected)
c8c8fb33 3149 goto out;
a9756bb5 3150
0d198328
AJ		 3151 intel_dp_probe_oui(intel_dp);
3152
c3e5f67b
DV		 3153 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3154 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3155 } else {
8c241fef 3156 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3157 if (edid) {
3158 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3159 kfree(edid);
3160 }
a9756bb5
ZW		 3161 }
3162
d63885da
PZ		 3163 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3164 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3165 status = connector_status_connected;
3166
3167out:
3168 intel_runtime_pm_put(dev_priv);
3169 return status;
a4fc5ed6
KP		 3170}
3171
3172static int intel_dp_get_modes(struct drm_connector *connector)
3173{
df0e9248 3174 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 3175 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3176 struct drm_device *dev = connector->dev;
32f9d658 3177 int ret;
a4fc5ed6
KP		 3178
3179 /* We should parse the EDID data and find out if it has an audio sink
3180 */
3181
8c241fef 3182 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 3183 if (ret)
32f9d658
ZW		 3184 return ret;
3185
f8779fda 3186 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3187 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3188 struct drm_display_mode *mode;
dd06f90e
JN		 3189 mode = drm_mode_duplicate(dev,
3190 intel_connector->panel.fixed_mode);
f8779fda 3191 if (mode) {
32f9d658
ZW		 3192 drm_mode_probed_add(connector, mode);
3193 return 1;
3194 }
3195 }
3196 return 0;
a4fc5ed6
KP		 3197}
3198
1aad7ac0
CW		 3199static bool
3200intel_dp_detect_audio(struct drm_connector *connector)
3201{
3202 struct intel_dp *intel_dp = intel_attached_dp(connector);
3203 struct edid *edid;
3204 bool has_audio = false;
3205
8c241fef 3206 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3207 if (edid) {
3208 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3209 kfree(edid);
3210 }
3211
3212 return has_audio;
3213}
3214
f684960e
CW		 3215static int
3216intel_dp_set_property(struct drm_connector *connector,
3217 struct drm_property *property,
3218 uint64_t val)
3219{
e953fd7b 3220 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3221 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3222 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3223 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3224 int ret;
3225
662595df 3226 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3227 if (ret)
3228 return ret;
3229
3f43c48d 3230 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3231 int i = val;
3232 bool has_audio;
3233
3234 if (i == intel_dp->force_audio)
f684960e
CW		 3235 return 0;
3236
1aad7ac0 3237 intel_dp->force_audio = i;
f684960e 3238
c3e5f67b 3239 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3240 has_audio = intel_dp_detect_audio(connector);
3241 else
c3e5f67b 3242 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3243
3244 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3245 return 0;
3246
1aad7ac0 3247 intel_dp->has_audio = has_audio;
f684960e
CW		 3248 goto done;
3249 }
3250
e953fd7b 3251 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3252 bool old_auto = intel_dp->color_range_auto;
3253 uint32_t old_range = intel_dp->color_range;
3254
55bc60db
VS		 3255 switch (val) {
3256 case INTEL_BROADCAST_RGB_AUTO:
3257 intel_dp->color_range_auto = true;
3258 break;
3259 case INTEL_BROADCAST_RGB_FULL:
3260 intel_dp->color_range_auto = false;
3261 intel_dp->color_range = 0;
3262 break;
3263 case INTEL_BROADCAST_RGB_LIMITED:
3264 intel_dp->color_range_auto = false;
3265 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3266 break;
3267 default:
3268 return -EINVAL;
3269 }
ae4edb80
DV		 3270
3271 if (old_auto == intel_dp->color_range_auto &&
3272 old_range == intel_dp->color_range)
3273 return 0;
3274
e953fd7b
CW		 3275 goto done;
3276 }
3277
53b41837
YN		 3278 if (is_edp(intel_dp) &&
3279 property == connector->dev->mode_config.scaling_mode_property) {
3280 if (val == DRM_MODE_SCALE_NONE) {
3281 DRM_DEBUG_KMS("no scaling not supported\n");
3282 return -EINVAL;
3283 }
3284
3285 if (intel_connector->panel.fitting_mode == val) {
3286 /* the eDP scaling property is not changed */
3287 return 0;
3288 }
3289 intel_connector->panel.fitting_mode = val;
3290
3291 goto done;
3292 }
3293
f684960e
CW		 3294 return -EINVAL;
3295
3296done:
c0c36b94
CW		 3297 if (intel_encoder->base.crtc)
3298 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3299
3300 return 0;
3301}
3302
a4fc5ed6 3303static void
73845adf 3304intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3305{
1d508706 3306 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3307
9cd300e0
JN		 3308 if (!IS_ERR_OR_NULL(intel_connector->edid))
3309 kfree(intel_connector->edid);
3310
acd8db10
PZ		 3311 /* Can't call is_edp() since the encoder may have been destroyed
3312 * already. */
3313 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3314 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3315
a4fc5ed6 3316 drm_connector_cleanup(connector);
55f78c43 3317 kfree(connector);
a4fc5ed6
KP		 3318}
3319
00c09d70 3320void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3321{
da63a9f2
PZ		 3322 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3323 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3325
3326 i2c_del_adapter(&intel_dp->adapter);
3327 drm_encoder_cleanup(encoder);
bd943159
KP		 3328 if (is_edp(intel_dp)) {
3329 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3330 mutex_lock(&dev->mode_config.mutex);
4be73780 3331 edp_panel_vdd_off_sync(intel_dp);
bd173813 3332 mutex_unlock(&dev->mode_config.mutex);
bd943159 3333 }
da63a9f2 3334 kfree(intel_dig_port);
24d05927
DV		 3335}
3336
a4fc5ed6 3337static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3338 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3339 .detect = intel_dp_detect,
3340 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3341 .set_property = intel_dp_set_property,
73845adf 3342 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3343};
3344
3345static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3346 .get_modes = intel_dp_get_modes,
3347 .mode_valid = intel_dp_mode_valid,
df0e9248 3348 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3349};
3350
a4fc5ed6 3351static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3352 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3353};
3354
995b6762 3355static void
21d40d37 3356intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3357{
fa90ecef 3358 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3359
885a5014 3360 intel_dp_check_link_status(intel_dp);
c8110e52 3361}
6207937d 3362
e3421a18
ZW		 3363/* Return which DP Port should be selected for Transcoder DP control */
3364int
0206e353 3365intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3366{
3367 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3368 struct intel_encoder *intel_encoder;
3369 struct intel_dp *intel_dp;
e3421a18 3370
fa90ecef
PZ		 3371 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3372 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3373
fa90ecef
PZ		 3374 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3375 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3376 return intel_dp->output_reg;
e3421a18 3377 }
ea5b213a 3378
e3421a18
ZW		 3379 return -1;
3380}
3381
36e83a18 3382/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3383bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3384{
3385 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3386 union child_device_config *p_child;
36e83a18 3387 int i;
5d8a7752
VS		 3388 static const short port_mapping[] = {
3389 [PORT_B] = PORT_IDPB,
3390 [PORT_C] = PORT_IDPC,
3391 [PORT_D] = PORT_IDPD,
3392 };
36e83a18 3393
3b32a35b
VS		 3394 if (port == PORT_A)
3395 return true;
3396
41aa3448 3397 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3398 return false;
3399
41aa3448
RV		 3400 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3401 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3402
5d8a7752 3403 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3404 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3405 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3406 return true;
3407 }
3408 return false;
3409}
3410
f684960e
CW		 3411static void
3412intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3413{
53b41837
YN		 3414 struct intel_connector *intel_connector = to_intel_connector(connector);
3415
3f43c48d 3416 intel_attach_force_audio_property(connector);
e953fd7b 3417 intel_attach_broadcast_rgb_property(connector);
55bc60db 3418 intel_dp->color_range_auto = true;
53b41837
YN		 3419
3420 if (is_edp(intel_dp)) {
3421 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3422 drm_object_attach_property(
3423 &connector->base,
53b41837 3424 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3425 DRM_MODE_SCALE_ASPECT);
3426 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3427 }
f684960e
CW		 3428}
3429
67a54566
DV		 3430static void
3431intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3432 struct intel_dp *intel_dp,
3433 struct edp_power_seq *out)
67a54566
DV		 3434{
3435 struct drm_i915_private *dev_priv = dev->dev_private;
3436 struct edp_power_seq cur, vbt, spec, final;
3437 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3438 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3439
3440 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3441 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3442 pp_on_reg = PCH_PP_ON_DELAYS;
3443 pp_off_reg = PCH_PP_OFF_DELAYS;
3444 pp_div_reg = PCH_PP_DIVISOR;
3445 } else {
bf13e81b
JN		 3446 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3447
3448 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3449 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3450 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3451 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3452 }
67a54566
DV		 3453
3454 /* Workaround: Need to write PP_CONTROL with the unlock key as
3455 * the very first thing. */
453c5420 3456 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3457 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3458
453c5420
JB		 3459 pp_on = I915_READ(pp_on_reg);
3460 pp_off = I915_READ(pp_off_reg);
3461 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3462
3463 /* Pull timing values out of registers */
3464 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3465 PANEL_POWER_UP_DELAY_SHIFT;
3466
3467 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3468 PANEL_LIGHT_ON_DELAY_SHIFT;
3469
3470 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3471 PANEL_LIGHT_OFF_DELAY_SHIFT;
3472
3473 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3474 PANEL_POWER_DOWN_DELAY_SHIFT;
3475
3476 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3477 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3478
3479 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3480 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3481
41aa3448 3482 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3483
3484 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3485 * our hw here, which are all in 100usec. */
3486 spec.t1_t3 = 210 * 10;
3487 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3488 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3489 spec.t10 = 500 * 10;
3490 /* This one is special and actually in units of 100ms, but zero
3491 * based in the hw (so we need to add 100 ms). But the sw vbt
3492 * table multiplies it with 1000 to make it in units of 100usec,
3493 * too. */
3494 spec.t11_t12 = (510 + 100) * 10;
3495
3496 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3497 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3498
3499 /* Use the max of the register settings and vbt. If both are
3500 * unset, fall back to the spec limits. */
3501#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3502 spec.field : \
3503 max(cur.field, vbt.field))
3504 assign_final(t1_t3);
3505 assign_final(t8);
3506 assign_final(t9);
3507 assign_final(t10);
3508 assign_final(t11_t12);
3509#undef assign_final
3510
3511#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3512 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3513 intel_dp->backlight_on_delay = get_delay(t8);
3514 intel_dp->backlight_off_delay = get_delay(t9);
3515 intel_dp->panel_power_down_delay = get_delay(t10);
3516 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3517#undef get_delay
3518
f30d26e4
JN		 3519 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3520 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3521 intel_dp->panel_power_cycle_delay);
3522
3523 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3524 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3525
3526 if (out)
3527 *out = final;
3528}
3529
3530static void
3531intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3532 struct intel_dp *intel_dp,
3533 struct edp_power_seq *seq)
3534{
3535 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3536 u32 pp_on, pp_off, pp_div, port_sel = 0;
3537 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3538 int pp_on_reg, pp_off_reg, pp_div_reg;
3539
3540 if (HAS_PCH_SPLIT(dev)) {
3541 pp_on_reg = PCH_PP_ON_DELAYS;
3542 pp_off_reg = PCH_PP_OFF_DELAYS;
3543 pp_div_reg = PCH_PP_DIVISOR;
3544 } else {
bf13e81b
JN		 3545 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3546
3547 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3548 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3549 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3550 }
3551
b2f19d1a
PZ		 3552 /*
3553 * And finally store the new values in the power sequencer. The
3554 * backlight delays are set to 1 because we do manual waits on them. For
3555 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3556 * we'll end up waiting for the backlight off delay twice: once when we
3557 * do the manual sleep, and once when we disable the panel and wait for
3558 * the PP_STATUS bit to become zero.
3559 */
f30d26e4 3560 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3561 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3562 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3563 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3564 /* Compute the divisor for the pp clock, simply match the Bspec
3565 * formula. */
453c5420 3566 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3567 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3568 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3569
3570 /* Haswell doesn't have any port selection bits for the panel
3571 * power sequencer any more. */
bc7d38a4 3572 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3573 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3574 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3575 else
3576 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3577 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3578 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3579 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3580 else
a24c144c 3581 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3582 }
3583
453c5420
JB		 3584 pp_on |= port_sel;
3585
3586 I915_WRITE(pp_on_reg, pp_on);
3587 I915_WRITE(pp_off_reg, pp_off);
3588 I915_WRITE(pp_div_reg, pp_div);
67a54566 3589
67a54566 3590 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3591 I915_READ(pp_on_reg),
3592 I915_READ(pp_off_reg),
3593 I915_READ(pp_div_reg));
f684960e
CW		 3594}
3595
ed92f0b2 3596static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3597 struct intel_connector *intel_connector,
3598 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3599{
3600 struct drm_connector *connector = &intel_connector->base;
3601 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3602 struct drm_device *dev = intel_dig_port->base.base.dev;
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3605 bool has_dpcd;
3606 struct drm_display_mode *scan;
3607 struct edid *edid;
3608
3609 if (!is_edp(intel_dp))
3610 return true;
3611
ed92f0b2 3612 /* Cache DPCD and EDID for edp. */
4be73780 3613 edp_panel_vdd_on(intel_dp);
ed92f0b2 3614 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3615 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3616
3617 if (has_dpcd) {
3618 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3619 dev_priv->no_aux_handshake =
3620 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3621 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3622 } else {
3623 /* if this fails, presume the device is a ghost */
3624 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3625 return false;
3626 }
3627
3628 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3629 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3630
ed92f0b2
PZ		 3631 edid = drm_get_edid(connector, &intel_dp->adapter);
3632 if (edid) {
3633 if (drm_add_edid_modes(connector, edid)) {
3634 drm_mode_connector_update_edid_property(connector,
3635 edid);
3636 drm_edid_to_eld(connector, edid);
3637 } else {
3638 kfree(edid);
3639 edid = ERR_PTR(-EINVAL);
3640 }
3641 } else {
3642 edid = ERR_PTR(-ENOENT);
3643 }
3644 intel_connector->edid = edid;
3645
3646 /* prefer fixed mode from EDID if available */
3647 list_for_each_entry(scan, &connector->probed_modes, head) {
3648 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3649 fixed_mode = drm_mode_duplicate(dev, scan);
3650 break;
3651 }
3652 }
3653
3654 /* fallback to VBT if available for eDP */
3655 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3656 fixed_mode = drm_mode_duplicate(dev,
3657 dev_priv->vbt.lfp_lvds_vbt_mode);
3658 if (fixed_mode)
3659 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3660 }
3661
ed92f0b2
PZ		 3662 intel_panel_init(&intel_connector->panel, fixed_mode);
3663 intel_panel_setup_backlight(connector);
3664
3665 return true;
3666}
3667
16c25533 3668bool
f0fec3f2
PZ		 3669intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3670 struct intel_connector *intel_connector)
a4fc5ed6 3671{
f0fec3f2
PZ		 3672 struct drm_connector *connector = &intel_connector->base;
3673 struct intel_dp *intel_dp = &intel_dig_port->dp;
3674 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3675 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3676 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3677 enum port port = intel_dig_port->port;
0095e6dc 3678 struct edp_power_seq power_seq = { 0 };
5eb08b69 3679 const char *name = NULL;
b2a14755 3680 int type, error;
a4fc5ed6 3681
0767935e
DV		 3682 /* Preserve the current hw state. */
3683 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3684 intel_dp->attached_connector = intel_connector;
3d3dc149 3685
3b32a35b 3686 if (intel_dp_is_edp(dev, port))
b329530c 3687 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3688 else
3689 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3690
f7d24902
ID		 3691 /*
3692 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3693 * for DP the encoder type can be set by the caller to
3694 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3695 */
3696 if (type == DRM_MODE_CONNECTOR_eDP)
3697 intel_encoder->type = INTEL_OUTPUT_EDP;
3698
e7281eab
ID		 3699 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3700 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3701 port_name(port));
3702
b329530c 3703 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3704 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3705
a4fc5ed6
KP		 3706 connector->interlace_allowed = true;
3707 connector->doublescan_allowed = 0;
3708
f0fec3f2 3709 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3710 edp_panel_vdd_work);
a4fc5ed6 3711
df0e9248 3712 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3713 drm_sysfs_connector_add(connector);
3714
affa9354 3715 if (HAS_DDI(dev))
bcbc889b
PZ		 3716 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3717 else
3718 intel_connector->get_hw_state = intel_connector_get_hw_state;
3719
9ed35ab1
PZ		 3720 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3721 if (HAS_DDI(dev)) {
3722 switch (intel_dig_port->port) {
3723 case PORT_A:
3724 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3725 break;
3726 case PORT_B:
3727 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3728 break;
3729 case PORT_C:
3730 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3731 break;
3732 case PORT_D:
3733 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3734 break;
3735 default:
3736 BUG();
3737 }
3738 }
e8cb4558 3739
a4fc5ed6 3740 /* Set up the DDC bus. */
ab9d7c30
PZ		 3741 switch (port) {
3742 case PORT_A:
1d843f9d 3743 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3744 name = "DPDDC-A";
3745 break;
3746 case PORT_B:
1d843f9d 3747 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3748 name = "DPDDC-B";
3749 break;
3750 case PORT_C:
1d843f9d 3751 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3752 name = "DPDDC-C";
3753 break;
3754 case PORT_D:
1d843f9d 3755 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3756 name = "DPDDC-D";
3757 break;
3758 default:
ad1c0b19 3759 BUG();
5eb08b69
ZW		 3760 }
3761
0095e6dc
PZ		 3762 if (is_edp(intel_dp))
3763 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3764
b2a14755
PZ		 3765 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3766 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3767 error, port_name(port));
c1f05264 3768
2b28bb1b
RV		 3769 intel_dp->psr_setup_done = false;
3770
0095e6dc 3771 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
15b1d171
PZ		 3772 i2c_del_adapter(&intel_dp->adapter);
3773 if (is_edp(intel_dp)) {
3774 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3775 mutex_lock(&dev->mode_config.mutex);
4be73780 3776 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3777 mutex_unlock(&dev->mode_config.mutex);
3778 }
b2f246a8
PZ		 3779 drm_sysfs_connector_remove(connector);
3780 drm_connector_cleanup(connector);
16c25533 3781 return false;
b2f246a8 3782 }
32f9d658 3783
f684960e
CW		 3784 intel_dp_add_properties(intel_dp, connector);
3785
a4fc5ed6
KP		 3786 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3787 * 0xd. Failure to do so will result in spurious interrupts being
3788 * generated on the port when a cable is not attached.
3789 */
3790 if (IS_G4X(dev) && !IS_GM45(dev)) {
3791 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3792 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3793 }
16c25533
PZ		 3794
3795 return true;
a4fc5ed6 3796}
f0fec3f2
PZ		 3797
3798void
3799intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3800{
3801 struct intel_digital_port *intel_dig_port;
3802 struct intel_encoder *intel_encoder;
3803 struct drm_encoder *encoder;
3804 struct intel_connector *intel_connector;
3805
b14c5679 3806 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3807 if (!intel_dig_port)
3808 return;
3809
b14c5679 3810 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3811 if (!intel_connector) {
3812 kfree(intel_dig_port);
3813 return;
3814 }
3815
3816 intel_encoder = &intel_dig_port->base;
3817 encoder = &intel_encoder->base;
3818
3819 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3820 DRM_MODE_ENCODER_TMDS);
3821
5bfe2ac0 3822 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3823 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3824 intel_encoder->disable = intel_disable_dp;
3825 intel_encoder->post_disable = intel_post_disable_dp;
3826 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3827 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3828 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3829 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3830 intel_encoder->pre_enable = vlv_pre_enable_dp;
3831 intel_encoder->enable = vlv_enable_dp;
3832 } else {
ecff4f3b
JN		 3833 intel_encoder->pre_enable = g4x_pre_enable_dp;
3834 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3835 }
f0fec3f2 3836
174edf1f 3837 intel_dig_port->port = port;
f0fec3f2
PZ		 3838 intel_dig_port->dp.output_reg = output_reg;
3839
00c09d70 3840 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3841 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3842 intel_encoder->cloneable = false;
3843 intel_encoder->hot_plug = intel_dp_hot_plug;
3844
15b1d171
PZ		 3845 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3846 drm_encoder_cleanup(encoder);
3847 kfree(intel_dig_port);
b2f246a8 3848 kfree(intel_connector);
15b1d171 3849 }
f0fec3f2 3850}
Linux 6.x block layer and io_uring tree(s)