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drm/i915: Allow parsing of variable size child device entries from VBT
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
f8896f5d 131/* Skylake H, S, and Skylake Y with 0.95V VccIO */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
150 { 0x00002016, 0x0000009D, 0x0 },
151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
155};
156
157/* Skylake Y with 0.85V VccIO */
158static const struct ddi_buf_trans skl_y_085v_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
168};
169
170/*
171 * Skylake H and S, and Skylake Y with 0.95V VccIO
172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d
DW		 204/*
205 * Skylake Y with 0.95V VccIO
206 * eDP 1.4 low vswing translation parameters
207 */
208static const struct ddi_buf_trans skl_y_085v_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
f8896f5d 221/* Skylake H, S and U, and Skylake Y with 0.95V VccIO */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
236/* Skylake Y with 0.85V VccIO */
237static const struct ddi_buf_trans skl_y_085v_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost */
248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
259/* BSpec does not define separate vswing/pre-emphasis values for eDP.
260 * Using DP values for eDP as well.
261 */
262static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
263 /* Idx NT mV diff db */
fe4c63c8
ID		 264 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
265 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
266 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
267 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
268 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
269 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
270 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
271 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
272 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 273 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 274};
275
276/* BSpec has 2 recommended values - entries 0 and 8.
277 * Using the entry with higher vswing.
278 */
279static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
280 /* Idx NT mV diff db */
fe4c63c8
ID		 281 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
282 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
283 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
284 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
285 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
286 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
287 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
288 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
289 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 290 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
291};
292
f8896f5d
DW		 293static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
294 enum port port, int type);
295
a1e6ad66
ID		 296static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
297 struct intel_digital_port **dig_port,
298 enum port *port)
fc914639 299{
0bdee30e 300 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 301 int type = intel_encoder->type;
302
0e32b39c 303 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 304 *dig_port = enc_to_mst(encoder)->primary;
305 *port = (*dig_port)->port;
0e32b39c 306 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 307 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 308 *dig_port = enc_to_dig_port(encoder);
309 *port = (*dig_port)->port;
fc914639 310 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 311 *dig_port = NULL;
312 *port = PORT_E;
fc914639
PZ		 313 } else {
314 DRM_ERROR("Invalid DDI encoder type %d\n", type);
315 BUG();
316 }
317}
318
a1e6ad66
ID		 319enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
320{
321 struct intel_digital_port *dig_port;
322 enum port port;
323
324 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
325
326 return port;
327}
328
ce3b7e9b
DL		 329static bool
330intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
331{
332 return intel_dig_port->hdmi.hdmi_reg;
333}
334
f8896f5d
DW		 335static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
336 int *n_entries)
337{
338 struct drm_i915_private *dev_priv = dev->dev_private;
339 const struct ddi_buf_trans *ddi_translations;
340 static int is_095v = -1;
341
342 if (is_095v == -1) {
343 u32 spr1 = I915_READ(UAIMI_SPR1);
344
345 is_095v = spr1 & SKL_VCCIO_MASK;
346 }
347
348 if (IS_SKL_ULX(dev) && !is_095v) {
349 ddi_translations = skl_y_085v_ddi_translations_dp;
350 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
351 } else if (IS_SKL_ULT(dev)) {
352 ddi_translations = skl_u_ddi_translations_dp;
353 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
354 } else {
355 ddi_translations = skl_ddi_translations_dp;
356 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
357 }
358
359 return ddi_translations;
360}
361
362static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
363 int *n_entries)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 const struct ddi_buf_trans *ddi_translations;
367 static int is_095v = -1;
368
369 if (is_095v == -1) {
370 u32 spr1 = I915_READ(UAIMI_SPR1);
371
372 is_095v = spr1 & SKL_VCCIO_MASK;
373 }
374
375 if (IS_SKL_ULX(dev) && !is_095v) {
376 if (dev_priv->edp_low_vswing) {
377 ddi_translations = skl_y_085v_ddi_translations_edp;
378 *n_entries =
379 ARRAY_SIZE(skl_y_085v_ddi_translations_edp);
380 } else {
381 ddi_translations = skl_y_085v_ddi_translations_dp;
382 *n_entries =
383 ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
384 }
385 } else if (IS_SKL_ULT(dev)) {
386 if (dev_priv->edp_low_vswing) {
387 ddi_translations = skl_u_ddi_translations_edp;
388 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
389 } else {
390 ddi_translations = skl_u_ddi_translations_dp;
391 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
392 }
393 } else {
394 if (dev_priv->edp_low_vswing) {
395 ddi_translations = skl_ddi_translations_edp;
396 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
397 } else {
398 ddi_translations = skl_ddi_translations_dp;
399 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
400 }
401 }
402
403 return ddi_translations;
404}
405
406static const struct ddi_buf_trans *
407skl_get_buf_trans_hdmi(struct drm_device *dev,
408 int *n_entries)
409{
410 struct drm_i915_private *dev_priv = dev->dev_private;
411 const struct ddi_buf_trans *ddi_translations;
412 static int is_095v = -1;
413
414 if (is_095v == -1) {
415 u32 spr1 = I915_READ(UAIMI_SPR1);
416
417 is_095v = spr1 & SKL_VCCIO_MASK;
418 }
419
420 if (IS_SKL_ULX(dev) && !is_095v) {
421 ddi_translations = skl_y_085v_ddi_translations_hdmi;
422 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_hdmi);
423 } else {
424 ddi_translations = skl_ddi_translations_hdmi;
425 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
426 }
427
428 return ddi_translations;
429}
430
e58623cb
AR		 431/*
432 * Starting with Haswell, DDI port buffers must be programmed with correct
433 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 434 * but the HDMI/DVI fields are shared among those. So we program the DDI
435 * in either FDI or DP modes only, as HDMI connections will work with both
436 * of those
437 */
faa0cdbe
ID		 438static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
439 bool supports_hdmi)
45244b87
ED		 440{
441 struct drm_i915_private *dev_priv = dev->dev_private;
442 u32 reg;
75067dde 443 u32 iboost_bit = 0;
7ff44670 444 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 445 size;
6acab15a 446 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 447 const struct ddi_buf_trans *ddi_translations_fdi;
448 const struct ddi_buf_trans *ddi_translations_dp;
449 const struct ddi_buf_trans *ddi_translations_edp;
450 const struct ddi_buf_trans *ddi_translations_hdmi;
451 const struct ddi_buf_trans *ddi_translations;
e58623cb 452
96fb9f9b 453 if (IS_BROXTON(dev)) {
faa0cdbe 454 if (!supports_hdmi)
96fb9f9b
VK		 455 return;
456
457 /* Vswing programming for HDMI */
458 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
459 INTEL_OUTPUT_HDMI);
460 return;
461 } else if (IS_SKYLAKE(dev)) {
c30400fc 462 ddi_translations_fdi = NULL;
f8896f5d
DW		 463 ddi_translations_dp =
464 skl_get_buf_trans_dp(dev, &n_dp_entries);
465 ddi_translations_edp =
466 skl_get_buf_trans_edp(dev, &n_edp_entries);
467 ddi_translations_hdmi =
468 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
469 hdmi_default_entry = 8;
75067dde
AK		 470 /* If we're boosting the current, set bit 31 of trans1 */
471 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
472 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
473 iboost_bit = 1<<31;
7f88e3af 474 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 475 ddi_translations_fdi = bdw_ddi_translations_fdi;
476 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 477 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 478 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 479 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
480 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 481 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 482 hdmi_default_entry = 7;
e58623cb
AR		 483 } else if (IS_HASWELL(dev)) {
484 ddi_translations_fdi = hsw_ddi_translations_fdi;
485 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 486 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 487 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 488 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 489 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 490 hdmi_default_entry = 6;
e58623cb
AR		 491 } else {
492 WARN(1, "ddi translation table missing\n");
300644c7 493 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 494 ddi_translations_fdi = bdw_ddi_translations_fdi;
495 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 496 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 497 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
498 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 499 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 500 hdmi_default_entry = 7;
e58623cb
AR		 501 }
502
300644c7
PZ		 503 switch (port) {
504 case PORT_A:
505 ddi_translations = ddi_translations_edp;
7ad14a29 506 size = n_edp_entries;
300644c7
PZ		 507 break;
508 case PORT_B:
509 case PORT_C:
300644c7 510 ddi_translations = ddi_translations_dp;
7ad14a29 511 size = n_dp_entries;
300644c7 512 break;
77d8d009 513 case PORT_D:
7ad14a29 514 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 515 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 516 size = n_edp_entries;
517 } else {
77d8d009 518 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 519 size = n_dp_entries;
520 }
77d8d009 521 break;
300644c7 522 case PORT_E:
7f88e3af
DL		 523 if (ddi_translations_fdi)
524 ddi_translations = ddi_translations_fdi;
525 else
526 ddi_translations = ddi_translations_dp;
7ad14a29 527 size = n_dp_entries;
300644c7
PZ		 528 break;
529 default:
530 BUG();
531 }
45244b87 532
7ad14a29 533 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
75067dde 534 I915_WRITE(reg, ddi_translations[i].trans1 | iboost_bit);
10122051
JN		 535 reg += 4;
536 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 537 reg += 4;
538 }
ce4dd49e 539
faa0cdbe 540 if (!supports_hdmi)
ce3b7e9b
DL		 541 return;
542
ce4dd49e
DL		 543 /* Choose a good default if VBT is badly populated */
544 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
545 hdmi_level >= n_hdmi_entries)
7ff44670 546 hdmi_level = hdmi_default_entry;
ce4dd49e 547
6acab15a 548 /* Entry 9 is for HDMI: */
75067dde 549 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
10122051
JN		 550 reg += 4;
551 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
552 reg += 4;
45244b87
ED		 553}
554
555/* Program DDI buffers translations for DP. By default, program ports A-D in DP
556 * mode and port E for FDI.
557 */
558void intel_prepare_ddi(struct drm_device *dev)
559{
faa0cdbe 560 struct intel_encoder *intel_encoder;
b403745c 561 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 562
0d536cb4
PZ		 563 if (!HAS_DDI(dev))
564 return;
45244b87 565
faa0cdbe
ID		 566 for_each_intel_encoder(dev, intel_encoder) {
567 struct intel_digital_port *intel_dig_port;
568 enum port port;
569 bool supports_hdmi;
570
571 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
572
573 if (visited[port])
b403745c
DL		 574 continue;
575
faa0cdbe
ID		 576 supports_hdmi = intel_dig_port &&
577 intel_dig_port_supports_hdmi(intel_dig_port);
578
579 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
580 visited[port] = true;
b403745c 581 }
45244b87 582}
c82e4d26 583
248138b5
PZ		 584static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
585 enum port port)
586{
587 uint32_t reg = DDI_BUF_CTL(port);
588 int i;
589
3449ca85 590 for (i = 0; i < 16; i++) {
248138b5
PZ		 591 udelay(1);
592 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
593 return;
594 }
595 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
596}
c82e4d26
ED		 597
598/* Starting with Haswell, different DDI ports can work in FDI mode for
599 * connection to the PCH-located connectors. For this, it is necessary to train
600 * both the DDI port and PCH receiver for the desired DDI buffer settings.
601 *
602 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
603 * please note that when FDI mode is active on DDI E, it shares 2 lines with
604 * DDI A (which is used for eDP)
605 */
606
607void hsw_fdi_link_train(struct drm_crtc *crtc)
608{
609 struct drm_device *dev = crtc->dev;
610 struct drm_i915_private *dev_priv = dev->dev_private;
611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 612 u32 temp, i, rx_ctl_val;
c82e4d26 613
04945641
PZ		 614 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
615 * mode set "sequence for CRT port" document:
616 * - TP1 to TP2 time with the default value
617 * - FDI delay to 90h
8693a824
DL		 618 *
619 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 620 */
621 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
622 FDI_RX_PWRDN_LANE0_VAL(2) |
623 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
624
625 /* Enable the PCH Receiver FDI PLL */
3e68320e 626 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 627 FDI_RX_PLL_ENABLE |
6e3c9717 628 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 629 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
630 POSTING_READ(_FDI_RXA_CTL);
631 udelay(220);
632
633 /* Switch from Rawclk to PCDclk */
634 rx_ctl_val |= FDI_PCDCLK;
635 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
636
637 /* Configure Port Clock Select */
6e3c9717
ACO		 638 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
639 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 640
641 /* Start the training iterating through available voltages and emphasis,
642 * testing each value twice. */
10122051 643 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 644 /* Configure DP_TP_CTL with auto-training */
645 I915_WRITE(DP_TP_CTL(PORT_E),
646 DP_TP_CTL_FDI_AUTOTRAIN |
647 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
648 DP_TP_CTL_LINK_TRAIN_PAT1 |
649 DP_TP_CTL_ENABLE);
650
876a8cdf
DL		 651 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
652 * DDI E does not support port reversal, the functionality is
653 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
654 * port reversal bit */
c82e4d26 655 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 656 DDI_BUF_CTL_ENABLE |
6e3c9717 657 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 658 DDI_BUF_TRANS_SELECT(i / 2));
04945641 659 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 660
661 udelay(600);
662
04945641
PZ		 663 /* Program PCH FDI Receiver TU */
664 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
665
666 /* Enable PCH FDI Receiver with auto-training */
667 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
668 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
669 POSTING_READ(_FDI_RXA_CTL);
670
671 /* Wait for FDI receiver lane calibration */
672 udelay(30);
673
674 /* Unset FDI_RX_MISC pwrdn lanes */
675 temp = I915_READ(_FDI_RXA_MISC);
676 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
677 I915_WRITE(_FDI_RXA_MISC, temp);
678 POSTING_READ(_FDI_RXA_MISC);
679
680 /* Wait for FDI auto training time */
681 udelay(5);
c82e4d26
ED		 682
683 temp = I915_READ(DP_TP_STATUS(PORT_E));
684 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 685 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 686
687 /* Enable normal pixel sending for FDI */
688 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 689 DP_TP_CTL_FDI_AUTOTRAIN |
690 DP_TP_CTL_LINK_TRAIN_NORMAL |
691 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
692 DP_TP_CTL_ENABLE);
c82e4d26 693
04945641 694 return;
c82e4d26 695 }
04945641 696
248138b5
PZ		 697 temp = I915_READ(DDI_BUF_CTL(PORT_E));
698 temp &= ~DDI_BUF_CTL_ENABLE;
699 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
700 POSTING_READ(DDI_BUF_CTL(PORT_E));
701
04945641 702 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 703 temp = I915_READ(DP_TP_CTL(PORT_E));
704 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
705 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
706 I915_WRITE(DP_TP_CTL(PORT_E), temp);
707 POSTING_READ(DP_TP_CTL(PORT_E));
708
709 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 710
711 rx_ctl_val &= ~FDI_RX_ENABLE;
712 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 713 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 714
715 /* Reset FDI_RX_MISC pwrdn lanes */
716 temp = I915_READ(_FDI_RXA_MISC);
717 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
718 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
719 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 720 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 721 }
722
04945641 723 DRM_ERROR("FDI link training failed!\n");
c82e4d26 724}
0e72a5b5 725
44905a27
DA		 726void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
727{
728 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
729 struct intel_digital_port *intel_dig_port =
730 enc_to_dig_port(&encoder->base);
731
732 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 733 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 734 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
735
736}
737
8d9ddbcb
PZ		 738static struct intel_encoder *
739intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
740{
741 struct drm_device *dev = crtc->dev;
742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
743 struct intel_encoder *intel_encoder, *ret = NULL;
744 int num_encoders = 0;
745
746 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
747 ret = intel_encoder;
748 num_encoders++;
749 }
750
751 if (num_encoders != 1)
84f44ce7
VS		 752 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
753 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 754
755 BUG_ON(ret == NULL);
756 return ret;
757}
758
bcddf610 759struct intel_encoder *
3165c074 760intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 761{
3165c074
ACO		 762 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
763 struct intel_encoder *ret = NULL;
764 struct drm_atomic_state *state;
da3ced29
ACO		 765 struct drm_connector *connector;
766 struct drm_connector_state *connector_state;
d0737e1d 767 int num_encoders = 0;
3165c074 768 int i;
d0737e1d 769
3165c074
ACO		 770 state = crtc_state->base.state;
771
da3ced29
ACO		 772 for_each_connector_in_state(state, connector, connector_state, i) {
773 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 774 continue;
775
da3ced29 776 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 777 num_encoders++;
d0737e1d
ACO		 778 }
779
780 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
781 pipe_name(crtc->pipe));
782
783 BUG_ON(ret == NULL);
784 return ret;
785}
786
1c0b85c5 787#define LC_FREQ 2700
27893390 788#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 789
790#define P_MIN 2
791#define P_MAX 64
792#define P_INC 2
793
794/* Constraints for PLL good behavior */
795#define REF_MIN 48
796#define REF_MAX 400
797#define VCO_MIN 2400
798#define VCO_MAX 4800
799
27893390
DL		 800#define abs_diff(a, b) ({ \
801 typeof(a) __a = (a); \
802 typeof(b) __b = (b); \
803 (void) (&__a == &__b); \
804 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 805
63582983 806struct hsw_wrpll_rnp {
1c0b85c5
DL		 807 unsigned p, n2, r2;
808};
809
63582983 810static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 811{
1c0b85c5
DL		 812 unsigned budget;
813
814 switch (clock) {
815 case 25175000:
816 case 25200000:
817 case 27000000:
818 case 27027000:
819 case 37762500:
820 case 37800000:
821 case 40500000:
822 case 40541000:
823 case 54000000:
824 case 54054000:
825 case 59341000:
826 case 59400000:
827 case 72000000:
828 case 74176000:
829 case 74250000:
830 case 81000000:
831 case 81081000:
832 case 89012000:
833 case 89100000:
834 case 108000000:
835 case 108108000:
836 case 111264000:
837 case 111375000:
838 case 148352000:
839 case 148500000:
840 case 162000000:
841 case 162162000:
842 case 222525000:
843 case 222750000:
844 case 296703000:
845 case 297000000:
846 budget = 0;
847 break;
848 case 233500000:
849 case 245250000:
850 case 247750000:
851 case 253250000:
852 case 298000000:
853 budget = 1500;
854 break;
855 case 169128000:
856 case 169500000:
857 case 179500000:
858 case 202000000:
859 budget = 2000;
860 break;
861 case 256250000:
862 case 262500000:
863 case 270000000:
864 case 272500000:
865 case 273750000:
866 case 280750000:
867 case 281250000:
868 case 286000000:
869 case 291750000:
870 budget = 4000;
871 break;
872 case 267250000:
873 case 268500000:
874 budget = 5000;
875 break;
876 default:
877 budget = 1000;
878 break;
879 }
6441ab5f 880
1c0b85c5
DL		 881 return budget;
882}
883
63582983
DL		 884static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
885 unsigned r2, unsigned n2, unsigned p,
886 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 887{
888 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 889
1c0b85c5
DL		 890 /* No best (r,n,p) yet */
891 if (best->p == 0) {
892 best->p = p;
893 best->n2 = n2;
894 best->r2 = r2;
895 return;
896 }
6441ab5f 897
1c0b85c5
DL		 898 /*
899 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
900 * freq2k.
901 *
902 * delta = 1e6 *
903 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
904 * freq2k;
905 *
906 * and we would like delta <= budget.
907 *
908 * If the discrepancy is above the PPM-based budget, always prefer to
909 * improve upon the previous solution. However, if you're within the
910 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
911 */
912 a = freq2k * budget * p * r2;
913 b = freq2k * budget * best->p * best->r2;
27893390
DL		 914 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
915 diff_best = abs_diff(freq2k * best->p * best->r2,
916 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 917 c = 1000000 * diff;
918 d = 1000000 * diff_best;
919
920 if (a < c && b < d) {
921 /* If both are above the budget, pick the closer */
922 if (best->p * best->r2 * diff < p * r2 * diff_best) {
923 best->p = p;
924 best->n2 = n2;
925 best->r2 = r2;
926 }
927 } else if (a >= c && b < d) {
928 /* If A is below the threshold but B is above it? Update. */
929 best->p = p;
930 best->n2 = n2;
931 best->r2 = r2;
932 } else if (a >= c && b >= d) {
933 /* Both are below the limit, so pick the higher n2/(r2*r2) */
934 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
935 best->p = p;
936 best->n2 = n2;
937 best->r2 = r2;
938 }
939 }
940 /* Otherwise a < c && b >= d, do nothing */
941}
942
63582983 943static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 944{
945 int refclk = LC_FREQ;
946 int n, p, r;
947 u32 wrpll;
948
949 wrpll = I915_READ(reg);
114fe488
DV		 950 switch (wrpll & WRPLL_PLL_REF_MASK) {
951 case WRPLL_PLL_SSC:
952 case WRPLL_PLL_NON_SSC:
11578553
JB		 953 /*
954 * We could calculate spread here, but our checking
955 * code only cares about 5% accuracy, and spread is a max of
956 * 0.5% downspread.
957 */
958 refclk = 135;
959 break;
114fe488 960 case WRPLL_PLL_LCPLL:
11578553
JB		 961 refclk = LC_FREQ;
962 break;
963 default:
964 WARN(1, "bad wrpll refclk\n");
965 return 0;
966 }
967
968 r = wrpll & WRPLL_DIVIDER_REF_MASK;
969 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
970 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
971
20f0ec16
JB		 972 /* Convert to KHz, p & r have a fixed point portion */
973 return (refclk * n * 100) / (p * r);
11578553
JB		 974}
975
540e732c
S		 976static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
977 uint32_t dpll)
978{
979 uint32_t cfgcr1_reg, cfgcr2_reg;
980 uint32_t cfgcr1_val, cfgcr2_val;
981 uint32_t p0, p1, p2, dco_freq;
982
983 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
984 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
985
986 cfgcr1_val = I915_READ(cfgcr1_reg);
987 cfgcr2_val = I915_READ(cfgcr2_reg);
988
989 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
990 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
991
992 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
993 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
994 else
995 p1 = 1;
996
997
998 switch (p0) {
999 case DPLL_CFGCR2_PDIV_1:
1000 p0 = 1;
1001 break;
1002 case DPLL_CFGCR2_PDIV_2:
1003 p0 = 2;
1004 break;
1005 case DPLL_CFGCR2_PDIV_3:
1006 p0 = 3;
1007 break;
1008 case DPLL_CFGCR2_PDIV_7:
1009 p0 = 7;
1010 break;
1011 }
1012
1013 switch (p2) {
1014 case DPLL_CFGCR2_KDIV_5:
1015 p2 = 5;
1016 break;
1017 case DPLL_CFGCR2_KDIV_2:
1018 p2 = 2;
1019 break;
1020 case DPLL_CFGCR2_KDIV_3:
1021 p2 = 3;
1022 break;
1023 case DPLL_CFGCR2_KDIV_1:
1024 p2 = 1;
1025 break;
1026 }
1027
1028 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1029
1030 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1031 1000) / 0x8000;
1032
1033 return dco_freq / (p0 * p1 * p2 * 5);
1034}
1035
398a017e
VS		 1036static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1037{
1038 int dotclock;
1039
1040 if (pipe_config->has_pch_encoder)
1041 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1042 &pipe_config->fdi_m_n);
1043 else if (pipe_config->has_dp_encoder)
1044 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1045 &pipe_config->dp_m_n);
1046 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1047 dotclock = pipe_config->port_clock * 2 / 3;
1048 else
1049 dotclock = pipe_config->port_clock;
1050
1051 if (pipe_config->pixel_multiplier)
1052 dotclock /= pipe_config->pixel_multiplier;
1053
1054 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1055}
540e732c
S		 1056
1057static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1058 struct intel_crtc_state *pipe_config)
540e732c
S		 1059{
1060 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1061 int link_clock = 0;
1062 uint32_t dpll_ctl1, dpll;
1063
134ffa44 1064 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1065
1066 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1067
1068 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1069 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1070 } else {
71cd8423
DL		 1071 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1072 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1073
1074 switch (link_clock) {
71cd8423 1075 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1076 link_clock = 81000;
1077 break;
71cd8423 1078 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1079 link_clock = 108000;
1080 break;
71cd8423 1081 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1082 link_clock = 135000;
1083 break;
71cd8423 1084 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1085 link_clock = 162000;
1086 break;
71cd8423 1087 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1088 link_clock = 216000;
1089 break;
71cd8423 1090 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1091 link_clock = 270000;
1092 break;
1093 default:
1094 WARN(1, "Unsupported link rate\n");
1095 break;
1096 }
1097 link_clock *= 2;
1098 }
1099
1100 pipe_config->port_clock = link_clock;
1101
398a017e 1102 ddi_dotclock_get(pipe_config);
540e732c
S		 1103}
1104
3d51278a 1105static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1106 struct intel_crtc_state *pipe_config)
11578553
JB		 1107{
1108 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1109 int link_clock = 0;
1110 u32 val, pll;
1111
26804afd 1112 val = pipe_config->ddi_pll_sel;
11578553
JB		 1113 switch (val & PORT_CLK_SEL_MASK) {
1114 case PORT_CLK_SEL_LCPLL_810:
1115 link_clock = 81000;
1116 break;
1117 case PORT_CLK_SEL_LCPLL_1350:
1118 link_clock = 135000;
1119 break;
1120 case PORT_CLK_SEL_LCPLL_2700:
1121 link_clock = 270000;
1122 break;
1123 case PORT_CLK_SEL_WRPLL1:
63582983 1124 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 1125 break;
1126 case PORT_CLK_SEL_WRPLL2:
63582983 1127 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 1128 break;
1129 case PORT_CLK_SEL_SPLL:
1130 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1131 if (pll == SPLL_PLL_FREQ_810MHz)
1132 link_clock = 81000;
1133 else if (pll == SPLL_PLL_FREQ_1350MHz)
1134 link_clock = 135000;
1135 else if (pll == SPLL_PLL_FREQ_2700MHz)
1136 link_clock = 270000;
1137 else {
1138 WARN(1, "bad spll freq\n");
1139 return;
1140 }
1141 break;
1142 default:
1143 WARN(1, "bad port clock sel\n");
1144 return;
1145 }
1146
1147 pipe_config->port_clock = link_clock * 2;
1148
398a017e 1149 ddi_dotclock_get(pipe_config);
11578553
JB		 1150}
1151
977bb38d
S		 1152static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1153 enum intel_dpll_id dpll)
1154{
aa610dcb
ID		 1155 struct intel_shared_dpll *pll;
1156 struct intel_dpll_hw_state *state;
1157 intel_clock_t clock;
1158
1159 /* For DDI ports we always use a shared PLL. */
1160 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1161 return 0;
1162
1163 pll = &dev_priv->shared_dplls[dpll];
1164 state = &pll->config.hw_state;
1165
1166 clock.m1 = 2;
1167 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1168 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1169 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1170 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1171 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1172 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1173
1174 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1175}
1176
1177static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1178 struct intel_crtc_state *pipe_config)
1179{
1180 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1181 enum port port = intel_ddi_get_encoder_port(encoder);
1182 uint32_t dpll = port;
1183
398a017e 1184 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1185
398a017e 1186 ddi_dotclock_get(pipe_config);
977bb38d
S		 1187}
1188
3d51278a 1189void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1190 struct intel_crtc_state *pipe_config)
3d51278a 1191{
22606a18
DL		 1192 struct drm_device *dev = encoder->base.dev;
1193
1194 if (INTEL_INFO(dev)->gen <= 8)
1195 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1196 else if (IS_SKYLAKE(dev))
22606a18 1197 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1198 else if (IS_BROXTON(dev))
1199 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1200}
1201
1c0b85c5 1202static void
d664c0ce
DL		 1203hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1204 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1205{
1206 uint64_t freq2k;
1207 unsigned p, n2, r2;
63582983 1208 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1209 unsigned budget;
1210
1211 freq2k = clock / 100;
1212
63582983 1213 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1214
1215 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1216 * and directly pass the LC PLL to it. */
1217 if (freq2k == 5400000) {
1218 *n2_out = 2;
1219 *p_out = 1;
1220 *r2_out = 2;
1221 return;
1222 }
1223
1224 /*
1225 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1226 * the WR PLL.
1227 *
1228 * We want R so that REF_MIN <= Ref <= REF_MAX.
1229 * Injecting R2 = 2 * R gives:
1230 * REF_MAX * r2 > LC_FREQ * 2 and
1231 * REF_MIN * r2 < LC_FREQ * 2
1232 *
1233 * Which means the desired boundaries for r2 are:
1234 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1235 *
1236 */
1237 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1238 r2 <= LC_FREQ * 2 / REF_MIN;
1239 r2++) {
1240
1241 /*
1242 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1243 *
1244 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1245 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1246 * VCO_MAX * r2 > n2 * LC_FREQ and
1247 * VCO_MIN * r2 < n2 * LC_FREQ)
1248 *
1249 * Which means the desired boundaries for n2 are:
1250 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1251 */
1252 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1253 n2 <= VCO_MAX * r2 / LC_FREQ;
1254 n2++) {
1255
1256 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1257 hsw_wrpll_update_rnp(freq2k, budget,
1258 r2, n2, p, &best);
1c0b85c5
DL		 1259 }
1260 }
6441ab5f 1261
1c0b85c5
DL		 1262 *n2_out = best.n2;
1263 *p_out = best.p;
1264 *r2_out = best.r2;
6441ab5f
PZ		 1265}
1266
0220ab6e 1267static bool
d664c0ce 1268hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1269 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1270 struct intel_encoder *intel_encoder,
1271 int clock)
6441ab5f 1272{
d664c0ce 1273 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1274 struct intel_shared_dpll *pll;
716c2e55 1275 uint32_t val;
1c0b85c5 1276 unsigned p, n2, r2;
6441ab5f 1277
d664c0ce 1278 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1279
114fe488 1280 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1281 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1282 WRPLL_DIVIDER_POST(p);
1283
dd3cd74a
ACO		 1284 memset(&crtc_state->dpll_hw_state, 0,
1285 sizeof(crtc_state->dpll_hw_state));
1286
190f68c5 1287 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1288
190f68c5 1289 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1290 if (pll == NULL) {
1291 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1292 pipe_name(intel_crtc->pipe));
1293 return false;
0694001b 1294 }
d452c5b6 1295
190f68c5 1296 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1297 }
1298
6441ab5f
PZ		 1299 return true;
1300}
1301
dc253813
DL		 1302struct skl_wrpll_context {
1303 uint64_t min_deviation; /* current minimal deviation */
1304 uint64_t central_freq; /* chosen central freq */
1305 uint64_t dco_freq; /* chosen dco freq */
1306 unsigned int p; /* chosen divider */
1307};
1308
1309static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1310{
1311 memset(ctx, 0, sizeof(*ctx));
1312
1313 ctx->min_deviation = U64_MAX;
1314}
1315
1316/* DCO freq must be within +1%/-6% of the DCO central freq */
1317#define SKL_DCO_MAX_PDEVIATION 100
1318#define SKL_DCO_MAX_NDEVIATION 600
1319
1320static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1321 uint64_t central_freq,
1322 uint64_t dco_freq,
1323 unsigned int divider)
1324{
1325 uint64_t deviation;
1326
1327 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1328 central_freq);
1329
1330 /* positive deviation */
1331 if (dco_freq >= central_freq) {
1332 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1333 deviation < ctx->min_deviation) {
1334 ctx->min_deviation = deviation;
1335 ctx->central_freq = central_freq;
1336 ctx->dco_freq = dco_freq;
1337 ctx->p = divider;
1338 }
1339 /* negative deviation */
1340 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1341 deviation < ctx->min_deviation) {
1342 ctx->min_deviation = deviation;
1343 ctx->central_freq = central_freq;
1344 ctx->dco_freq = dco_freq;
1345 ctx->p = divider;
1346 }
dc253813
DL		 1347}
1348
1349static void skl_wrpll_get_multipliers(unsigned int p,
1350 unsigned int *p0 /* out */,
1351 unsigned int *p1 /* out */,
1352 unsigned int *p2 /* out */)
1353{
1354 /* even dividers */
1355 if (p % 2 == 0) {
1356 unsigned int half = p / 2;
1357
1358 if (half == 1 || half == 2 || half == 3 || half == 5) {
1359 *p0 = 2;
1360 *p1 = 1;
1361 *p2 = half;
1362 } else if (half % 2 == 0) {
1363 *p0 = 2;
1364 *p1 = half / 2;
1365 *p2 = 2;
1366 } else if (half % 3 == 0) {
1367 *p0 = 3;
1368 *p1 = half / 3;
1369 *p2 = 2;
1370 } else if (half % 7 == 0) {
1371 *p0 = 7;
1372 *p1 = half / 7;
1373 *p2 = 2;
1374 }
1375 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1376 *p0 = 3;
1377 *p1 = 1;
1378 *p2 = p / 3;
1379 } else if (p == 5 || p == 7) {
1380 *p0 = p;
1381 *p1 = 1;
1382 *p2 = 1;
1383 } else if (p == 15) {
1384 *p0 = 3;
1385 *p1 = 1;
1386 *p2 = 5;
1387 } else if (p == 21) {
1388 *p0 = 7;
1389 *p1 = 1;
1390 *p2 = 3;
1391 } else if (p == 35) {
1392 *p0 = 7;
1393 *p1 = 1;
1394 *p2 = 5;
1395 }
1396}
1397
82d35437
S		 1398struct skl_wrpll_params {
1399 uint32_t dco_fraction;
1400 uint32_t dco_integer;
1401 uint32_t qdiv_ratio;
1402 uint32_t qdiv_mode;
1403 uint32_t kdiv;
1404 uint32_t pdiv;
1405 uint32_t central_freq;
1406};
1407
76516fbc
DL		 1408static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1409 uint64_t afe_clock,
1410 uint64_t central_freq,
1411 uint32_t p0, uint32_t p1, uint32_t p2)
1412{
1413 uint64_t dco_freq;
1414
76516fbc
DL		 1415 switch (central_freq) {
1416 case 9600000000ULL:
1417 params->central_freq = 0;
1418 break;
1419 case 9000000000ULL:
1420 params->central_freq = 1;
1421 break;
1422 case 8400000000ULL:
1423 params->central_freq = 3;
1424 }
1425
1426 switch (p0) {
1427 case 1:
1428 params->pdiv = 0;
1429 break;
1430 case 2:
1431 params->pdiv = 1;
1432 break;
1433 case 3:
1434 params->pdiv = 2;
1435 break;
1436 case 7:
1437 params->pdiv = 4;
1438 break;
1439 default:
1440 WARN(1, "Incorrect PDiv\n");
1441 }
1442
1443 switch (p2) {
1444 case 5:
1445 params->kdiv = 0;
1446 break;
1447 case 2:
1448 params->kdiv = 1;
1449 break;
1450 case 3:
1451 params->kdiv = 2;
1452 break;
1453 case 1:
1454 params->kdiv = 3;
1455 break;
1456 default:
1457 WARN(1, "Incorrect KDiv\n");
1458 }
1459
1460 params->qdiv_ratio = p1;
1461 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1462
1463 dco_freq = p0 * p1 * p2 * afe_clock;
1464
1465 /*
1466 * Intermediate values are in Hz.
1467 * Divide by MHz to match bsepc
1468 */
30a7862d 1469 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1470 params->dco_fraction =
30a7862d
DL		 1471 div_u64((div_u64(dco_freq, 24) -
1472 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1473}
1474
318bd821 1475static bool
82d35437
S		 1476skl_ddi_calculate_wrpll(int clock /* in Hz */,
1477 struct skl_wrpll_params *wrpll_params)
1478{
1479 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1480 uint64_t dco_central_freq[3] = {8400000000ULL,
1481 9000000000ULL,
1482 9600000000ULL};
dc253813
DL		 1483 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1484 24, 28, 30, 32, 36, 40, 42, 44,
1485 48, 52, 54, 56, 60, 64, 66, 68,
1486 70, 72, 76, 78, 80, 84, 88, 90,
1487 92, 96, 98 };
1488 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1489 static const struct {
1490 const int *list;
1491 int n_dividers;
1492 } dividers[] = {
1493 { even_dividers, ARRAY_SIZE(even_dividers) },
1494 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1495 };
1496 struct skl_wrpll_context ctx;
1497 unsigned int dco, d, i;
1498 unsigned int p0, p1, p2;
1499
1500 skl_wrpll_context_init(&ctx);
1501
1502 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1503 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1504 for (i = 0; i < dividers[d].n_dividers; i++) {
1505 unsigned int p = dividers[d].list[i];
1506 uint64_t dco_freq = p * afe_clock;
1507
1508 skl_wrpll_try_divider(&ctx,
1509 dco_central_freq[dco],
1510 dco_freq,
1511 p);
e7ad9878
DL		 1512 /*
1513 * Skip the remaining dividers if we're sure to
1514 * have found the definitive divider, we can't
1515 * improve a 0 deviation.
1516 */
1517 if (ctx.min_deviation == 0)
1518 goto skip_remaining_dividers;
82d35437
S		 1519 }
1520 }
267db663 1521
e7ad9878 1522skip_remaining_dividers:
267db663
DL		 1523 /*
1524 * If a solution is found with an even divider, prefer
1525 * this one.
1526 */
1527 if (d == 0 && ctx.p)
1528 break;
82d35437
S		 1529 }
1530
dc253813
DL		 1531 if (!ctx.p) {
1532 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1533 return false;
dc253813 1534 }
82d35437 1535
dc253813
DL		 1536 /*
1537 * gcc incorrectly analyses that these can be used without being
1538 * initialized. To be fair, it's hard to guess.
1539 */
1540 p0 = p1 = p2 = 0;
1541 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1542 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1543 p0, p1, p2);
318bd821
DL		 1544
1545 return true;
82d35437
S		 1546}
1547
82d35437
S		 1548static bool
1549skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1550 struct intel_crtc_state *crtc_state,
82d35437
S		 1551 struct intel_encoder *intel_encoder,
1552 int clock)
1553{
1554 struct intel_shared_dpll *pll;
1555 uint32_t ctrl1, cfgcr1, cfgcr2;
1556
1557 /*
1558 * See comment in intel_dpll_hw_state to understand why we always use 0
1559 * as the DPLL id in this function.
1560 */
1561
1562 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1563
1564 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1565 struct skl_wrpll_params wrpll_params = { 0, };
1566
1567 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1568
318bd821
DL		 1569 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1570 return false;
82d35437
S		 1571
1572 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1573 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1574 wrpll_params.dco_integer;
1575
1576 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1577 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1578 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1579 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1580 wrpll_params.central_freq;
1581 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1582 struct drm_encoder *encoder = &intel_encoder->base;
1583 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1584
1585 switch (intel_dp->link_bw) {
1586 case DP_LINK_BW_1_62:
71cd8423 1587 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437
S		 1588 break;
1589 case DP_LINK_BW_2_7:
71cd8423 1590 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437
S		 1591 break;
1592 case DP_LINK_BW_5_4:
71cd8423 1593 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1594 break;
1595 }
1596
1597 cfgcr1 = cfgcr2 = 0;
1598 } else /* eDP */
1599 return true;
1600
dd3cd74a
ACO		 1601 memset(&crtc_state->dpll_hw_state, 0,
1602 sizeof(crtc_state->dpll_hw_state));
1603
190f68c5
ACO		 1604 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1605 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1606 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1607
190f68c5 1608 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1609 if (pll == NULL) {
1610 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1611 pipe_name(intel_crtc->pipe));
1612 return false;
1613 }
1614
1615 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1616 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1617
1618 return true;
1619}
0220ab6e 1620
d683f3bc
S		 1621/* bxt clock parameters */
1622struct bxt_clk_div {
64987fc5 1623 int clock;
d683f3bc
S		 1624 uint32_t p1;
1625 uint32_t p2;
1626 uint32_t m2_int;
1627 uint32_t m2_frac;
1628 bool m2_frac_en;
1629 uint32_t n;
d683f3bc
S		 1630};
1631
1632/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1633static const struct bxt_clk_div bxt_dp_clk_val[] = {
1634 {162000, 4, 2, 32, 1677722, 1, 1},
1635 {270000, 4, 1, 27, 0, 0, 1},
1636 {540000, 2, 1, 27, 0, 0, 1},
1637 {216000, 3, 2, 32, 1677722, 1, 1},
1638 {243000, 4, 1, 24, 1258291, 1, 1},
1639 {324000, 4, 1, 32, 1677722, 1, 1},
1640 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1641};
1642
1643static bool
1644bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1645 struct intel_crtc_state *crtc_state,
1646 struct intel_encoder *intel_encoder,
1647 int clock)
1648{
1649 struct intel_shared_dpll *pll;
1650 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1651 int vco = 0;
1652 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1653 uint32_t lanestagger;
d683f3bc
S		 1654
1655 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1656 intel_clock_t best_clock;
1657
1658 /* Calculate HDMI div */
1659 /*
1660 * FIXME: tie the following calculation into
1661 * i9xx_crtc_compute_clock
1662 */
1663 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1664 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1665 clock, pipe_name(intel_crtc->pipe));
1666 return false;
1667 }
1668
1669 clk_div.p1 = best_clock.p1;
1670 clk_div.p2 = best_clock.p2;
1671 WARN_ON(best_clock.m1 != 2);
1672 clk_div.n = best_clock.n;
1673 clk_div.m2_int = best_clock.m2 >> 22;
1674 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1675 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1676
b6dc71f3 1677 vco = best_clock.vco;
d683f3bc
S		 1678 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1679 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1680 int i;
d683f3bc 1681
64987fc5
SJ		 1682 clk_div = bxt_dp_clk_val[0];
1683 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1684 if (bxt_dp_clk_val[i].clock == clock) {
1685 clk_div = bxt_dp_clk_val[i];
1686 break;
1687 }
d683f3bc 1688 }
b6dc71f3
VK		 1689 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1690 }
1691
e6292556 1692 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1693 prop_coef = 4;
1694 int_coef = 9;
1695 gain_ctl = 3;
1696 targ_cnt = 8;
1697 } else if ((vco > 5400000 && vco < 6200000) ||
1698 (vco >= 4800000 && vco < 5400000)) {
1699 prop_coef = 5;
1700 int_coef = 11;
1701 gain_ctl = 3;
1702 targ_cnt = 9;
b6dc71f3
VK		 1703 } else if (vco == 5400000) {
1704 prop_coef = 3;
1705 int_coef = 8;
1706 gain_ctl = 1;
1707 targ_cnt = 9;
1708 } else {
1709 DRM_ERROR("Invalid VCO\n");
1710 return false;
d683f3bc
S		 1711 }
1712
dd3cd74a
ACO		 1713 memset(&crtc_state->dpll_hw_state, 0,
1714 sizeof(crtc_state->dpll_hw_state));
1715
e0681e38
VK		 1716 if (clock > 270000)
1717 lanestagger = 0x18;
1718 else if (clock > 135000)
1719 lanestagger = 0x0d;
1720 else if (clock > 67000)
1721 lanestagger = 0x07;
1722 else if (clock > 33000)
1723 lanestagger = 0x04;
1724 else
1725 lanestagger = 0x02;
1726
d683f3bc
S		 1727 crtc_state->dpll_hw_state.ebb0 =
1728 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1729 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1730 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1731 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1732
1733 if (clk_div.m2_frac_en)
1734 crtc_state->dpll_hw_state.pll3 =
1735 PORT_PLL_M2_FRAC_ENABLE;
1736
1737 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1738 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1739 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1740 PORT_PLL_GAIN_CTL(gain_ctl);
1741
1742 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1743
05712c15
ID		 1744 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1745
e6292556
VK		 1746 crtc_state->dpll_hw_state.pll10 =
1747 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1748 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1749
05712c15
ID		 1750 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1751
d683f3bc 1752 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1753 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1754
1755 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1756 if (pll == NULL) {
1757 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1758 pipe_name(intel_crtc->pipe));
1759 return false;
1760 }
1761
1762 /* shared DPLL id 0 is DPLL A */
1763 crtc_state->ddi_pll_sel = pll->id;
1764
1765 return true;
1766}
1767
0220ab6e
DL		 1768/*
1769 * Tries to find a *shared* PLL for the CRTC and store it in
1770 * intel_crtc->ddi_pll_sel.
1771 *
1772 * For private DPLLs, compute_config() should do the selection for us. This
1773 * function should be folded into compute_config() eventually.
1774 */
190f68c5
ACO		 1775bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1776 struct intel_crtc_state *crtc_state)
0220ab6e 1777{
82d35437 1778 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1779 struct intel_encoder *intel_encoder =
3165c074 1780 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1781 int clock = crtc_state->port_clock;
0220ab6e 1782
82d35437 1783 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1784 return skl_ddi_pll_select(intel_crtc, crtc_state,
1785 intel_encoder, clock);
d683f3bc
S		 1786 else if (IS_BROXTON(dev))
1787 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1788 intel_encoder, clock);
82d35437 1789 else
190f68c5
ACO		 1790 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1791 intel_encoder, clock);
0220ab6e
DL		 1792}
1793
dae84799
PZ		 1794void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1795{
1796 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1798 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1799 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1800 int type = intel_encoder->type;
1801 uint32_t temp;
1802
0e32b39c 1803 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1804 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1805 switch (intel_crtc->config->pipe_bpp) {
dae84799 1806 case 18:
c9809791 1807 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1808 break;
1809 case 24:
c9809791 1810 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1811 break;
1812 case 30:
c9809791 1813 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1814 break;
1815 case 36:
c9809791 1816 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1817 break;
1818 default:
4e53c2e0 1819 BUG();
dae84799 1820 }
c9809791 1821 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1822 }
1823}
1824
0e32b39c
DA		 1825void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1826{
1827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1828 struct drm_device *dev = crtc->dev;
1829 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1830 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1831 uint32_t temp;
1832 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1833 if (state == true)
1834 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1835 else
1836 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1837 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1838}
1839
8228c251 1840void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1841{
1842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1843 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1844 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1845 struct drm_device *dev = crtc->dev;
1846 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1847 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1848 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1849 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1850 int type = intel_encoder->type;
8d9ddbcb
PZ		 1851 uint32_t temp;
1852
ad80a810
PZ		 1853 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1854 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1855 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1856
6e3c9717 1857 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1858 case 18:
ad80a810 1859 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1860 break;
1861 case 24:
ad80a810 1862 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1863 break;
1864 case 30:
ad80a810 1865 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1866 break;
1867 case 36:
ad80a810 1868 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1869 break;
1870 default:
4e53c2e0 1871 BUG();
dfcef252 1872 }
72662e10 1873
6e3c9717 1874 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1875 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1876 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1877 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1878
e6f0bfc4
PZ		 1879 if (cpu_transcoder == TRANSCODER_EDP) {
1880 switch (pipe) {
1881 case PIPE_A:
c7670b10
PZ		 1882 /* On Haswell, can only use the always-on power well for
1883 * eDP when not using the panel fitter, and when not
1884 * using motion blur mitigation (which we don't
1885 * support). */
fabf6e51 1886 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1887 (intel_crtc->config->pch_pfit.enabled ||
1888 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1889 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1890 else
1891 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1892 break;
1893 case PIPE_B:
1894 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1895 break;
1896 case PIPE_C:
1897 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1898 break;
1899 default:
1900 BUG();
1901 break;
1902 }
1903 }
1904
7739c33b 1905 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1906 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1907 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1908 else
ad80a810 1909 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1910
7739c33b 1911 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1912 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1913 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1914
1915 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1916 type == INTEL_OUTPUT_EDP) {
1917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1918
0e32b39c
DA		 1919 if (intel_dp->is_mst) {
1920 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1921 } else
1922 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1923
1924 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1925 } else if (type == INTEL_OUTPUT_DP_MST) {
1926 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1927
1928 if (intel_dp->is_mst) {
1929 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1930 } else
1931 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1932
17aa6be9 1933 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1934 } else {
84f44ce7
VS		 1935 WARN(1, "Invalid encoder type %d for pipe %c\n",
1936 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1937 }
1938
ad80a810 1939 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1940}
72662e10 1941
ad80a810
PZ		 1942void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1943 enum transcoder cpu_transcoder)
8d9ddbcb 1944{
ad80a810 1945 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1946 uint32_t val = I915_READ(reg);
1947
0e32b39c 1948 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1949 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1950 I915_WRITE(reg, val);
72662e10
ED		 1951}
1952
bcbc889b
PZ		 1953bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1954{
1955 struct drm_device *dev = intel_connector->base.dev;
1956 struct drm_i915_private *dev_priv = dev->dev_private;
1957 struct intel_encoder *intel_encoder = intel_connector->encoder;
1958 int type = intel_connector->base.connector_type;
1959 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1960 enum pipe pipe = 0;
1961 enum transcoder cpu_transcoder;
882244a3 1962 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1963 uint32_t tmp;
1964
882244a3 1965 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1966 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1967 return false;
1968
bcbc889b
PZ		 1969 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1970 return false;
1971
1972 if (port == PORT_A)
1973 cpu_transcoder = TRANSCODER_EDP;
1974 else
1a240d4d 1975 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1976
1977 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1978
1979 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1980 case TRANS_DDI_MODE_SELECT_HDMI:
1981 case TRANS_DDI_MODE_SELECT_DVI:
1982 return (type == DRM_MODE_CONNECTOR_HDMIA);
1983
1984 case TRANS_DDI_MODE_SELECT_DP_SST:
1985 if (type == DRM_MODE_CONNECTOR_eDP)
1986 return true;
bcbc889b 1987 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1988 case TRANS_DDI_MODE_SELECT_DP_MST:
1989 /* if the transcoder is in MST state then
1990 * connector isn't connected */
1991 return false;
bcbc889b
PZ		 1992
1993 case TRANS_DDI_MODE_SELECT_FDI:
1994 return (type == DRM_MODE_CONNECTOR_VGA);
1995
1996 default:
1997 return false;
1998 }
1999}
2000
85234cdc
DV		 2001bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2002 enum pipe *pipe)
2003{
2004 struct drm_device *dev = encoder->base.dev;
2005 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 2006 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 2007 enum intel_display_power_domain power_domain;
85234cdc
DV		 2008 u32 tmp;
2009 int i;
2010
6d129bea 2011 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2012 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2013 return false;
2014
fe43d3f5 2015 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 2016
2017 if (!(tmp & DDI_BUF_CTL_ENABLE))
2018 return false;
2019
ad80a810
PZ		 2020 if (port == PORT_A) {
2021 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2022
ad80a810
PZ		 2023 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2024 case TRANS_DDI_EDP_INPUT_A_ON:
2025 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2026 *pipe = PIPE_A;
2027 break;
2028 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2029 *pipe = PIPE_B;
2030 break;
2031 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2032 *pipe = PIPE_C;
2033 break;
2034 }
2035
2036 return true;
2037 } else {
2038 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2039 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2040
2041 if ((tmp & TRANS_DDI_PORT_MASK)
2042 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2043 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2044 return false;
2045
ad80a810
PZ		 2046 *pipe = i;
2047 return true;
2048 }
85234cdc
DV		 2049 }
2050 }
2051
84f44ce7 2052 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2053
22f9fe50 2054 return false;
85234cdc
DV		 2055}
2056
fc914639
PZ		 2057void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2058{
2059 struct drm_crtc *crtc = &intel_crtc->base;
2060 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2061 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2062 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2063 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2064
bb523fc0
PZ		 2065 if (cpu_transcoder != TRANSCODER_EDP)
2066 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2067 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2068}
2069
2070void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2071{
2072 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2073 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2074
bb523fc0
PZ		 2075 if (cpu_transcoder != TRANSCODER_EDP)
2076 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2077 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2078}
2079
f8896f5d
DW		 2080static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2081 enum port port, int type)
2082{
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 const struct ddi_buf_trans *ddi_translations;
2085 uint8_t iboost;
75067dde 2086 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2087 int n_entries;
2088 u32 reg;
2089
75067dde
AK		 2090 /* VBT may override standard boost values */
2091 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2092 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2093
f8896f5d 2094 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2095 if (dp_iboost) {
2096 iboost = dp_iboost;
2097 } else {
2098 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2099 iboost = ddi_translations[port].i_boost;
2100 }
f8896f5d 2101 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2102 if (dp_iboost) {
2103 iboost = dp_iboost;
2104 } else {
2105 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2106 iboost = ddi_translations[port].i_boost;
2107 }
f8896f5d 2108 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2109 if (hdmi_iboost) {
2110 iboost = hdmi_iboost;
2111 } else {
2112 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2113 iboost = ddi_translations[port].i_boost;
2114 }
f8896f5d
DW		 2115 } else {
2116 return;
2117 }
2118
2119 /* Make sure that the requested I_boost is valid */
2120 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2121 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2122 return;
2123 }
2124
2125 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2126 reg &= ~BALANCE_LEG_MASK(port);
2127 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2128
2129 if (iboost)
2130 reg |= iboost << BALANCE_LEG_SHIFT(port);
2131 else
2132 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2133
2134 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2135}
2136
2137static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2138 enum port port, int type)
96fb9f9b
VK		 2139{
2140 struct drm_i915_private *dev_priv = dev->dev_private;
2141 const struct bxt_ddi_buf_trans *ddi_translations;
2142 u32 n_entries, i;
2143 uint32_t val;
2144
2145 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2146 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2147 ddi_translations = bxt_ddi_translations_dp;
2148 } else if (type == INTEL_OUTPUT_HDMI) {
2149 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2150 ddi_translations = bxt_ddi_translations_hdmi;
2151 } else {
2152 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2153 type);
2154 return;
2155 }
2156
2157 /* Check if default value has to be used */
2158 if (level >= n_entries ||
2159 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2160 for (i = 0; i < n_entries; i++) {
2161 if (ddi_translations[i].default_index) {
2162 level = i;
2163 break;
2164 }
2165 }
2166 }
2167
2168 /*
2169 * While we write to the group register to program all lanes at once we
2170 * can read only lane registers and we pick lanes 0/1 for that.
2171 */
2172 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2173 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2174 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2175
2176 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2177 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2178 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2179 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2180 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2181
2182 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2183 val &= ~UNIQE_TRANGE_EN_METHOD;
2184 if (ddi_translations[level].enable)
2185 val |= UNIQE_TRANGE_EN_METHOD;
2186 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2187
2188 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2189 val &= ~DE_EMPHASIS;
2190 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2191 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2192
2193 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2194 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2195 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2196}
2197
f8896f5d
DW		 2198static uint32_t translate_signal_level(int signal_levels)
2199{
2200 uint32_t level;
2201
2202 switch (signal_levels) {
2203 default:
2204 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2205 signal_levels);
2206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2207 level = 0;
2208 break;
2209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2210 level = 1;
2211 break;
2212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2213 level = 2;
2214 break;
2215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2216 level = 3;
2217 break;
2218
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2220 level = 4;
2221 break;
2222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2223 level = 5;
2224 break;
2225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2226 level = 6;
2227 break;
2228
2229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2230 level = 7;
2231 break;
2232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2233 level = 8;
2234 break;
2235
2236 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2237 level = 9;
2238 break;
2239 }
2240
2241 return level;
2242}
2243
2244uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2245{
2246 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2247 struct drm_device *dev = dport->base.base.dev;
2248 struct intel_encoder *encoder = &dport->base;
2249 uint8_t train_set = intel_dp->train_set[0];
2250 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2251 DP_TRAIN_PRE_EMPHASIS_MASK);
2252 enum port port = dport->port;
2253 uint32_t level;
2254
2255 level = translate_signal_level(signal_levels);
2256
2257 if (IS_SKYLAKE(dev))
2258 skl_ddi_set_iboost(dev, level, port, encoder->type);
2259 else if (IS_BROXTON(dev))
2260 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2261
2262 return DDI_BUF_TRANS_SELECT(level);
2263}
2264
00c09d70 2265static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 2266{
c19b0669 2267 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2268 struct drm_device *dev = encoder->dev;
2269 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 2270 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 2271 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2272 int type = intel_encoder->type;
96fb9f9b 2273 int hdmi_level;
6441ab5f 2274
82a4d9c0
PZ		 2275 if (type == INTEL_OUTPUT_EDP) {
2276 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 2277 intel_edp_panel_on(intel_dp);
82a4d9c0 2278 }
6441ab5f 2279
efa80add 2280 if (IS_SKYLAKE(dev)) {
6e3c9717 2281 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 2282 uint32_t val;
2283
5416d871
DL		 2284 /*
2285 * DPLL0 is used for eDP and is the only "private" DPLL (as
2286 * opposed to shared) on SKL
2287 */
2288 if (type == INTEL_OUTPUT_EDP) {
2289 WARN_ON(dpll != SKL_DPLL0);
2290
2291 val = I915_READ(DPLL_CTRL1);
2292
2293 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2294 DPLL_CTRL1_SSC(dpll) |
71cd8423 2295 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 2296 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2297
2298 I915_WRITE(DPLL_CTRL1, val);
2299 POSTING_READ(DPLL_CTRL1);
2300 }
2301
2302 /* DDI -> PLL mapping */
efa80add
S		 2303 val = I915_READ(DPLL_CTRL2);
2304
2305 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2306 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2307 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2308 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2309
2310 I915_WRITE(DPLL_CTRL2, val);
5416d871 2311
1ab23380 2312 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 2313 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2314 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 2315 }
c19b0669 2316
82a4d9c0 2317 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2318 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2319
44905a27 2320 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2321
2322 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2323 intel_dp_start_link_train(intel_dp);
2324 intel_dp_complete_link_train(intel_dp);
23f08d83 2325 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2326 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2327 } else if (type == INTEL_OUTPUT_HDMI) {
2328 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2329
96fb9f9b
VK		 2330 if (IS_BROXTON(dev)) {
2331 hdmi_level = dev_priv->vbt.
2332 ddi_port_info[port].hdmi_level_shift;
2333 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2334 INTEL_OUTPUT_HDMI);
2335 }
30cf6db8 2336 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2337 crtc->config->has_hdmi_sink,
2338 &crtc->config->base.adjusted_mode);
c19b0669 2339 }
6441ab5f
PZ		 2340}
2341
00c09d70 2342static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2343{
2344 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2345 struct drm_device *dev = encoder->dev;
2346 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2347 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2348 int type = intel_encoder->type;
2886e93f 2349 uint32_t val;
a836bdf9 2350 bool wait = false;
2886e93f
PZ		 2351
2352 val = I915_READ(DDI_BUF_CTL(port));
2353 if (val & DDI_BUF_CTL_ENABLE) {
2354 val &= ~DDI_BUF_CTL_ENABLE;
2355 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2356 wait = true;
2886e93f 2357 }
6441ab5f 2358
a836bdf9
PZ		 2359 val = I915_READ(DP_TP_CTL(port));
2360 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2361 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2362 I915_WRITE(DP_TP_CTL(port), val);
2363
2364 if (wait)
2365 intel_wait_ddi_buf_idle(dev_priv, port);
2366
76bb80ed 2367 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2368 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2369 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2370 intel_edp_panel_vdd_on(intel_dp);
4be73780 2371 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2372 }
2373
efa80add
S		 2374 if (IS_SKYLAKE(dev))
2375 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2376 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2377 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2378 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2379}
2380
00c09d70 2381static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2382{
6547fef8 2383 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2384 struct drm_crtc *crtc = encoder->crtc;
2385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2386 struct drm_device *dev = encoder->dev;
72662e10 2387 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2388 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2389 int type = intel_encoder->type;
72662e10 2390
6547fef8 2391 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2392 struct intel_digital_port *intel_dig_port =
2393 enc_to_dig_port(encoder);
2394
6547fef8
PZ		 2395 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2396 * are ignored so nothing special needs to be done besides
2397 * enabling the port.
2398 */
876a8cdf 2399 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2400 intel_dig_port->saved_port_bits |
2401 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2402 } else if (type == INTEL_OUTPUT_EDP) {
2403 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2404
23f08d83 2405 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2406 intel_dp_stop_link_train(intel_dp);
2407
4be73780 2408 intel_edp_backlight_on(intel_dp);
0bc12bcb 2409 intel_psr_enable(intel_dp);
c395578e 2410 intel_edp_drrs_enable(intel_dp);
6547fef8 2411 }
7b9f35a6 2412
6e3c9717 2413 if (intel_crtc->config->has_audio) {
d45a0bf5 2414 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2415 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2416 }
5ab432ef
DV		 2417}
2418
00c09d70 2419static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2420{
d6c50ff8 2421 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2422 struct drm_crtc *crtc = encoder->crtc;
2423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2424 int type = intel_encoder->type;
7b9f35a6
WX		 2425 struct drm_device *dev = encoder->dev;
2426 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2427
6e3c9717 2428 if (intel_crtc->config->has_audio) {
69bfe1a9 2429 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2430 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2431 }
2831d842 2432
d6c50ff8
PZ		 2433 if (type == INTEL_OUTPUT_EDP) {
2434 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2435
c395578e 2436 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2437 intel_psr_disable(intel_dp);
4be73780 2438 intel_edp_backlight_off(intel_dp);
d6c50ff8 2439 }
72662e10 2440}
79f689aa 2441
e0b01be4
DV		 2442static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2443 struct intel_shared_dpll *pll)
2444{
3e369b76 2445 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2446 POSTING_READ(WRPLL_CTL(pll->id));
2447 udelay(20);
2448}
2449
12030431
DV		 2450static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2451 struct intel_shared_dpll *pll)
2452{
2453 uint32_t val;
2454
2455 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2456 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2457 POSTING_READ(WRPLL_CTL(pll->id));
2458}
2459
d452c5b6
DV		 2460static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2461 struct intel_shared_dpll *pll,
2462 struct intel_dpll_hw_state *hw_state)
2463{
2464 uint32_t val;
2465
f458ebbc 2466 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2467 return false;
2468
2469 val = I915_READ(WRPLL_CTL(pll->id));
2470 hw_state->wrpll = val;
2471
2472 return val & WRPLL_PLL_ENABLE;
2473}
2474
ca1381b5 2475static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2476 "WRPLL 1",
2477 "WRPLL 2",
2478};
2479
143b307c 2480static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2481{
9cd86933
DV		 2482 int i;
2483
716c2e55 2484 dev_priv->num_shared_dpll = 2;
9cd86933 2485
716c2e55 2486 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2487 dev_priv->shared_dplls[i].id = i;
2488 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2489 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2490 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2491 dev_priv->shared_dplls[i].get_hw_state =
2492 hsw_ddi_pll_get_hw_state;
9cd86933 2493 }
143b307c
DL		 2494}
2495
d1a2dc78
S		 2496static const char * const skl_ddi_pll_names[] = {
2497 "DPLL 1",
2498 "DPLL 2",
2499 "DPLL 3",
2500};
2501
2502struct skl_dpll_regs {
2503 u32 ctl, cfgcr1, cfgcr2;
2504};
2505
2506/* this array is indexed by the *shared* pll id */
2507static const struct skl_dpll_regs skl_dpll_regs[3] = {
2508 {
2509 /* DPLL 1 */
2510 .ctl = LCPLL2_CTL,
2511 .cfgcr1 = DPLL1_CFGCR1,
2512 .cfgcr2 = DPLL1_CFGCR2,
2513 },
2514 {
2515 /* DPLL 2 */
2516 .ctl = WRPLL_CTL1,
2517 .cfgcr1 = DPLL2_CFGCR1,
2518 .cfgcr2 = DPLL2_CFGCR2,
2519 },
2520 {
2521 /* DPLL 3 */
2522 .ctl = WRPLL_CTL2,
2523 .cfgcr1 = DPLL3_CFGCR1,
2524 .cfgcr2 = DPLL3_CFGCR2,
2525 },
2526};
2527
2528static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2529 struct intel_shared_dpll *pll)
2530{
2531 uint32_t val;
2532 unsigned int dpll;
2533 const struct skl_dpll_regs *regs = skl_dpll_regs;
2534
2535 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2536 dpll = pll->id + 1;
2537
2538 val = I915_READ(DPLL_CTRL1);
2539
2540 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2541 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2542 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2543
2544 I915_WRITE(DPLL_CTRL1, val);
2545 POSTING_READ(DPLL_CTRL1);
2546
2547 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2548 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2549 POSTING_READ(regs[pll->id].cfgcr1);
2550 POSTING_READ(regs[pll->id].cfgcr2);
2551
2552 /* the enable bit is always bit 31 */
2553 I915_WRITE(regs[pll->id].ctl,
2554 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2555
2556 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2557 DRM_ERROR("DPLL %d not locked\n", dpll);
2558}
2559
2560static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2561 struct intel_shared_dpll *pll)
2562{
2563 const struct skl_dpll_regs *regs = skl_dpll_regs;
2564
2565 /* the enable bit is always bit 31 */
2566 I915_WRITE(regs[pll->id].ctl,
2567 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2568 POSTING_READ(regs[pll->id].ctl);
2569}
2570
2571static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2572 struct intel_shared_dpll *pll,
2573 struct intel_dpll_hw_state *hw_state)
2574{
2575 uint32_t val;
2576 unsigned int dpll;
2577 const struct skl_dpll_regs *regs = skl_dpll_regs;
2578
2579 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2580 return false;
2581
2582 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2583 dpll = pll->id + 1;
2584
2585 val = I915_READ(regs[pll->id].ctl);
2586 if (!(val & LCPLL_PLL_ENABLE))
2587 return false;
2588
2589 val = I915_READ(DPLL_CTRL1);
2590 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2591
2592 /* avoid reading back stale values if HDMI mode is not enabled */
2593 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2594 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2595 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2596 }
2597
2598 return true;
2599}
2600
2601static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2602{
2603 int i;
2604
2605 dev_priv->num_shared_dpll = 3;
2606
2607 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2608 dev_priv->shared_dplls[i].id = i;
2609 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2610 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2611 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2612 dev_priv->shared_dplls[i].get_hw_state =
2613 skl_ddi_pll_get_hw_state;
2614 }
2615}
2616
5c6706e5
VK		 2617static void broxton_phy_init(struct drm_i915_private *dev_priv,
2618 enum dpio_phy phy)
2619{
2620 enum port port;
2621 uint32_t val;
2622
2623 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2624 val |= GT_DISPLAY_POWER_ON(phy);
2625 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2626
2627 /* Considering 10ms timeout until BSpec is updated */
2628 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2629 DRM_ERROR("timeout during PHY%d power on\n", phy);
2630
2631 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2632 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2633 int lane;
2634
2635 for (lane = 0; lane < 4; lane++) {
2636 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2637 /*
2638 * Note that on CHV this flag is called UPAR, but has
2639 * the same function.
2640 */
2641 val &= ~LATENCY_OPTIM;
2642 if (lane != 1)
2643 val |= LATENCY_OPTIM;
2644
2645 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2646 }
2647 }
2648
2649 /* Program PLL Rcomp code offset */
2650 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2651 val &= ~IREF0RC_OFFSET_MASK;
2652 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2653 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2654
2655 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2656 val &= ~IREF1RC_OFFSET_MASK;
2657 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2658 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2659
2660 /* Program power gating */
2661 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2662 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2663 SUS_CLK_CONFIG;
2664 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2665
2666 if (phy == DPIO_PHY0) {
2667 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2668 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2669 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2670 }
2671
2672 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2673 val &= ~OCL2_LDOFUSE_PWR_DIS;
2674 /*
2675 * On PHY1 disable power on the second channel, since no port is
2676 * connected there. On PHY0 both channels have a port, so leave it
2677 * enabled.
2678 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2679 * power down the second channel on PHY0 as well.
2680 */
2681 if (phy == DPIO_PHY1)
2682 val |= OCL2_LDOFUSE_PWR_DIS;
2683 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2684
2685 if (phy == DPIO_PHY0) {
2686 uint32_t grc_code;
2687 /*
2688 * PHY0 isn't connected to an RCOMP resistor so copy over
2689 * the corresponding calibrated value from PHY1, and disable
2690 * the automatic calibration on PHY0.
2691 */
2692 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2693 10))
2694 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2695
2696 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2697 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2698 grc_code = val << GRC_CODE_FAST_SHIFT |
2699 val << GRC_CODE_SLOW_SHIFT |
2700 val;
2701 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2702
2703 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2704 val |= GRC_DIS | GRC_RDY_OVRD;
2705 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2706 }
2707
2708 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2709 val |= COMMON_RESET_DIS;
2710 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2711}
2712
2713void broxton_ddi_phy_init(struct drm_device *dev)
2714{
2715 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2716 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2717 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2718}
2719
2720static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2721 enum dpio_phy phy)
2722{
2723 uint32_t val;
2724
2725 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2726 val &= ~COMMON_RESET_DIS;
2727 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2728}
2729
2730void broxton_ddi_phy_uninit(struct drm_device *dev)
2731{
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733
2734 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2735 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2736
2737 /* FIXME: do this in broxton_phy_uninit per phy */
2738 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2739}
2740
dfb82408
S		 2741static const char * const bxt_ddi_pll_names[] = {
2742 "PORT PLL A",
2743 "PORT PLL B",
2744 "PORT PLL C",
2745};
2746
2747static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2748 struct intel_shared_dpll *pll)
2749{
2750 uint32_t temp;
2751 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2752
2753 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2754 temp &= ~PORT_PLL_REF_SEL;
2755 /* Non-SSC reference */
2756 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2757
2758 /* Disable 10 bit clock */
2759 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2760 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2761 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2762
2763 /* Write P1 & P2 */
2764 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2765 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2766 temp |= pll->config.hw_state.ebb0;
2767 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2768
2769 /* Write M2 integer */
2770 temp = I915_READ(BXT_PORT_PLL(port, 0));
2771 temp &= ~PORT_PLL_M2_MASK;
2772 temp |= pll->config.hw_state.pll0;
2773 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2774
2775 /* Write N */
2776 temp = I915_READ(BXT_PORT_PLL(port, 1));
2777 temp &= ~PORT_PLL_N_MASK;
2778 temp |= pll->config.hw_state.pll1;
2779 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2780
2781 /* Write M2 fraction */
2782 temp = I915_READ(BXT_PORT_PLL(port, 2));
2783 temp &= ~PORT_PLL_M2_FRAC_MASK;
2784 temp |= pll->config.hw_state.pll2;
2785 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2786
2787 /* Write M2 fraction enable */
2788 temp = I915_READ(BXT_PORT_PLL(port, 3));
2789 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2790 temp |= pll->config.hw_state.pll3;
2791 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2792
2793 /* Write coeff */
2794 temp = I915_READ(BXT_PORT_PLL(port, 6));
2795 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2796 temp &= ~PORT_PLL_INT_COEFF_MASK;
2797 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2798 temp |= pll->config.hw_state.pll6;
2799 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2800
2801 /* Write calibration val */
2802 temp = I915_READ(BXT_PORT_PLL(port, 8));
2803 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2804 temp |= pll->config.hw_state.pll8;
2805 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2806
b6dc71f3
VK		 2807 temp = I915_READ(BXT_PORT_PLL(port, 9));
2808 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2809 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2810 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2811
2812 temp = I915_READ(BXT_PORT_PLL(port, 10));
2813 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2814 temp &= ~PORT_PLL_DCO_AMP_MASK;
2815 temp |= pll->config.hw_state.pll10;
2816 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2817
2818 /* Recalibrate with new settings */
2819 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2820 temp |= PORT_PLL_RECALIBRATE;
2821 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2822 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2823 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2824 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2825
2826 /* Enable PLL */
2827 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2828 temp |= PORT_PLL_ENABLE;
2829 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2830 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2831
2832 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2833 PORT_PLL_LOCK), 200))
2834 DRM_ERROR("PLL %d not locked\n", port);
2835
2836 /*
2837 * While we write to the group register to program all lanes at once we
2838 * can read only lane registers and we pick lanes 0/1 for that.
2839 */
2840 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2841 temp &= ~LANE_STAGGER_MASK;
2842 temp &= ~LANESTAGGER_STRAP_OVRD;
2843 temp |= pll->config.hw_state.pcsdw12;
2844 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2845}
2846
2847static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2848 struct intel_shared_dpll *pll)
2849{
2850 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2851 uint32_t temp;
2852
2853 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2854 temp &= ~PORT_PLL_ENABLE;
2855 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2856 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2857}
2858
2859static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2860 struct intel_shared_dpll *pll,
2861 struct intel_dpll_hw_state *hw_state)
2862{
2863 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2864 uint32_t val;
2865
2866 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2867 return false;
2868
2869 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2870 if (!(val & PORT_PLL_ENABLE))
2871 return false;
2872
2873 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2874 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2875
05712c15
ID		 2876 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2877 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2878
dfb82408 2879 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2880 hw_state->pll0 &= PORT_PLL_M2_MASK;
2881
dfb82408 2882 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2883 hw_state->pll1 &= PORT_PLL_N_MASK;
2884
dfb82408 2885 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2886 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2887
dfb82408 2888 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2889 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2890
dfb82408 2891 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2892 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2893 PORT_PLL_INT_COEFF_MASK |
2894 PORT_PLL_GAIN_CTL_MASK;
2895
dfb82408 2896 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2897 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2898
05712c15
ID		 2899 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2900 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2901
b6dc71f3 2902 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2903 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2904 PORT_PLL_DCO_AMP_MASK;
2905
dfb82408
S		 2906 /*
2907 * While we write to the group register to program all lanes at once we
2908 * can read only lane registers. We configure all lanes the same way, so
2909 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2910 */
2911 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2912 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2913 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2914 hw_state->pcsdw12,
2915 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2916 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408
S		 2917
2918 return true;
2919}
2920
2921static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2922{
2923 int i;
2924
2925 dev_priv->num_shared_dpll = 3;
2926
2927 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2928 dev_priv->shared_dplls[i].id = i;
2929 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2930 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2931 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2932 dev_priv->shared_dplls[i].get_hw_state =
2933 bxt_ddi_pll_get_hw_state;
2934 }
2935}
2936
143b307c
DL		 2937void intel_ddi_pll_init(struct drm_device *dev)
2938{
2939 struct drm_i915_private *dev_priv = dev->dev_private;
2940 uint32_t val = I915_READ(LCPLL_CTL);
2941
d1a2dc78
S		 2942 if (IS_SKYLAKE(dev))
2943 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2944 else if (IS_BROXTON(dev))
2945 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2946 else
2947 hsw_shared_dplls_init(dev_priv);
79f689aa 2948
121643c2 2949 if (IS_SKYLAKE(dev)) {
d9062ae5
DL		 2950 int cdclk_freq;
2951
2952 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2953 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2954 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2955 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2956 else
2957 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2958 } else if (IS_BROXTON(dev)) {
2959 broxton_init_cdclk(dev);
5c6706e5 2960 broxton_ddi_phy_init(dev);
121643c2
S		 2961 } else {
2962 /*
2963 * The LCPLL register should be turned on by the BIOS. For now
2964 * let's just check its state and print errors in case
2965 * something is wrong. Don't even try to turn it on.
2966 */
2967
2968 if (val & LCPLL_CD_SOURCE_FCLK)
2969 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2970
121643c2
S		 2971 if (val & LCPLL_PLL_DISABLE)
2972 DRM_ERROR("LCPLL is disabled\n");
2973 }
79f689aa 2974}
c19b0669
PZ		 2975
2976void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2977{
174edf1f
PZ		 2978 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2979 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2980 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2981 enum port port = intel_dig_port->port;
c19b0669 2982 uint32_t val;
f3e227df 2983 bool wait = false;
c19b0669
PZ		 2984
2985 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2986 val = I915_READ(DDI_BUF_CTL(port));
2987 if (val & DDI_BUF_CTL_ENABLE) {
2988 val &= ~DDI_BUF_CTL_ENABLE;
2989 I915_WRITE(DDI_BUF_CTL(port), val);
2990 wait = true;
2991 }
2992
2993 val = I915_READ(DP_TP_CTL(port));
2994 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2995 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2996 I915_WRITE(DP_TP_CTL(port), val);
2997 POSTING_READ(DP_TP_CTL(port));
2998
2999 if (wait)
3000 intel_wait_ddi_buf_idle(dev_priv, port);
3001 }
3002
0e32b39c 3003 val = DP_TP_CTL_ENABLE |
c19b0669 3004 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 3005 if (intel_dp->is_mst)
3006 val |= DP_TP_CTL_MODE_MST;
3007 else {
3008 val |= DP_TP_CTL_MODE_SST;
3009 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3010 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3011 }
c19b0669
PZ		 3012 I915_WRITE(DP_TP_CTL(port), val);
3013 POSTING_READ(DP_TP_CTL(port));
3014
3015 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3016 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3017 POSTING_READ(DDI_BUF_CTL(port));
3018
3019 udelay(600);
3020}
00c09d70 3021
1ad960f2
PZ		 3022void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3023{
3024 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3025 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3026 uint32_t val;
3027
3028 intel_ddi_post_disable(intel_encoder);
3029
3030 val = I915_READ(_FDI_RXA_CTL);
3031 val &= ~FDI_RX_ENABLE;
3032 I915_WRITE(_FDI_RXA_CTL, val);
3033
3034 val = I915_READ(_FDI_RXA_MISC);
3035 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3036 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3037 I915_WRITE(_FDI_RXA_MISC, val);
3038
3039 val = I915_READ(_FDI_RXA_CTL);
3040 val &= ~FDI_PCDCLK;
3041 I915_WRITE(_FDI_RXA_CTL, val);
3042
3043 val = I915_READ(_FDI_RXA_CTL);
3044 val &= ~FDI_RX_PLL_ENABLE;
3045 I915_WRITE(_FDI_RXA_CTL, val);
3046}
3047
6801c18c 3048void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3049 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3050{
3051 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3052 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3053 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3054 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3055 u32 temp, flags = 0;
3056
3057 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3058 if (temp & TRANS_DDI_PHSYNC)
3059 flags |= DRM_MODE_FLAG_PHSYNC;
3060 else
3061 flags |= DRM_MODE_FLAG_NHSYNC;
3062 if (temp & TRANS_DDI_PVSYNC)
3063 flags |= DRM_MODE_FLAG_PVSYNC;
3064 else
3065 flags |= DRM_MODE_FLAG_NVSYNC;
3066
2d112de7 3067 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3068
3069 switch (temp & TRANS_DDI_BPC_MASK) {
3070 case TRANS_DDI_BPC_6:
3071 pipe_config->pipe_bpp = 18;
3072 break;
3073 case TRANS_DDI_BPC_8:
3074 pipe_config->pipe_bpp = 24;
3075 break;
3076 case TRANS_DDI_BPC_10:
3077 pipe_config->pipe_bpp = 30;
3078 break;
3079 case TRANS_DDI_BPC_12:
3080 pipe_config->pipe_bpp = 36;
3081 break;
3082 default:
3083 break;
3084 }
eb14cb74
VS		 3085
3086 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3087 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3088 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3089 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3090
3091 if (intel_hdmi->infoframe_enabled(&encoder->base))
3092 pipe_config->has_infoframe = true;
cbc572a9 3093 break;
eb14cb74
VS		 3094 case TRANS_DDI_MODE_SELECT_DVI:
3095 case TRANS_DDI_MODE_SELECT_FDI:
3096 break;
3097 case TRANS_DDI_MODE_SELECT_DP_SST:
3098 case TRANS_DDI_MODE_SELECT_DP_MST:
3099 pipe_config->has_dp_encoder = true;
3100 intel_dp_get_m_n(intel_crtc, pipe_config);
3101 break;
3102 default:
3103 break;
3104 }
10214420 3105
f458ebbc 3106 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 3107 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 3108 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 3109 pipe_config->has_audio = true;
3110 }
9ed109a7 3111
10214420
DV		 3112 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3113 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3114 /*
3115 * This is a big fat ugly hack.
3116 *
3117 * Some machines in UEFI boot mode provide us a VBT that has 18
3118 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3119 * unknown we fail to light up. Yet the same BIOS boots up with
3120 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3121 * max, not what it tells us to use.
3122 *
3123 * Note: This will still be broken if the eDP panel is not lit
3124 * up by the BIOS, and thus we can't get the mode at module
3125 * load.
3126 */
3127 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3128 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3129 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3130 }
11578553 3131
22606a18 3132 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3133}
3134
00c09d70
PZ		 3135static void intel_ddi_destroy(struct drm_encoder *encoder)
3136{
3137 /* HDMI has nothing special to destroy, so we can go with this. */
3138 intel_dp_encoder_destroy(encoder);
3139}
3140
5bfe2ac0 3141static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3142 struct intel_crtc_state *pipe_config)
00c09d70 3143{
5bfe2ac0 3144 int type = encoder->type;
eccb140b 3145 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3146
5bfe2ac0 3147 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3148
eccb140b
DV		 3149 if (port == PORT_A)
3150 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3151
00c09d70 3152 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3153 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3154 else
5bfe2ac0 3155 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3156}
3157
3158static const struct drm_encoder_funcs intel_ddi_funcs = {
3159 .destroy = intel_ddi_destroy,
3160};
3161
4a28ae58
PZ		 3162static struct intel_connector *
3163intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3164{
3165 struct intel_connector *connector;
3166 enum port port = intel_dig_port->port;
3167
9bdbd0b9 3168 connector = intel_connector_alloc();
4a28ae58
PZ		 3169 if (!connector)
3170 return NULL;
3171
3172 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3173 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3174 kfree(connector);
3175 return NULL;
3176 }
3177
3178 return connector;
3179}
3180
3181static struct intel_connector *
3182intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3183{
3184 struct intel_connector *connector;
3185 enum port port = intel_dig_port->port;
3186
9bdbd0b9 3187 connector = intel_connector_alloc();
4a28ae58
PZ		 3188 if (!connector)
3189 return NULL;
3190
3191 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3192 intel_hdmi_init_connector(intel_dig_port, connector);
3193
3194 return connector;
3195}
3196
00c09d70
PZ		 3197void intel_ddi_init(struct drm_device *dev, enum port port)
3198{
876a8cdf 3199 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3200 struct intel_digital_port *intel_dig_port;
3201 struct intel_encoder *intel_encoder;
3202 struct drm_encoder *encoder;
311a2094
PZ		 3203 bool init_hdmi, init_dp;
3204
3205 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3206 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3207 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3208 if (!init_dp && !init_hdmi) {
500ea70d 3209 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3210 port_name(port));
500ea70d 3211 return;
311a2094 3212 }
00c09d70 3213
b14c5679 3214 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3215 if (!intel_dig_port)
3216 return;
3217
00c09d70
PZ		 3218 intel_encoder = &intel_dig_port->base;
3219 encoder = &intel_encoder->base;
3220
3221 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3222 DRM_MODE_ENCODER_TMDS);
00c09d70 3223
5bfe2ac0 3224 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3225 intel_encoder->enable = intel_enable_ddi;
3226 intel_encoder->pre_enable = intel_ddi_pre_enable;
3227 intel_encoder->disable = intel_disable_ddi;
3228 intel_encoder->post_disable = intel_ddi_post_disable;
3229 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3230 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3231
3232 intel_dig_port->port = port;
bcf53de4
SM		 3233 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3234 (DDI_BUF_PORT_REVERSAL |
3235 DDI_A_4_LANES);
00c09d70
PZ		 3236
3237 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3238 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3239 intel_encoder->cloneable = 0;
00c09d70 3240
f68d697e
CW		 3241 if (init_dp) {
3242 if (!intel_ddi_init_dp_connector(intel_dig_port))
3243 goto err;
13cf5504 3244
f68d697e 3245 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 3246 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3247 }
21a8e6a4 3248
311a2094
PZ		 3249 /* In theory we don't need the encoder->type check, but leave it just in
3250 * case we have some really bad VBTs... */
f68d697e
CW		 3251 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3252 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3253 goto err;
21a8e6a4 3254 }
f68d697e
CW		 3255
3256 return;
3257
3258err:
3259 drm_encoder_cleanup(encoder);
3260 kfree(intel_dig_port);
00c09d70 3261}
Linux 6.x block layer and io_uring tree(s)