projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Configure eDP PLL freq from ironlake_edp_pll_on()
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d
DW		 147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
5f8b2531
RV		 149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */
150 { 0x0000201B, 0x0000009D, 0x0 },
f8896f5d
DW		 151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
5f8b2531 162 { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */
f8896f5d
DW		 163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
5f8b2531 247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
f8896f5d 248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
f8896f5d
DW		 304static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
305 enum port port, int type);
306
a1e6ad66
ID		 307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
fc914639 310{
0bdee30e 311 struct drm_encoder *encoder = &intel_encoder->base;
fc914639 312
8cd21b7f
JN		 313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
a1e6ad66
ID		 315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
8cd21b7f
JN		 317 break;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
a1e6ad66
ID		 322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
8cd21b7f
JN		 324 break;
325 case INTEL_OUTPUT_ANALOG:
a1e6ad66
ID		 326 *dig_port = NULL;
327 *port = PORT_E;
8cd21b7f
JN		 328 break;
329 default:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 break;
fc914639
PZ		 332 }
333}
334
a1e6ad66
ID		 335enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336{
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343}
344
ce3b7e9b
DL		 345static bool
346intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
347{
348 return intel_dig_port->hdmi.hdmi_reg;
349}
350
f8896f5d
DW		 351static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
352 int *n_entries)
353{
f8896f5d 354 const struct ddi_buf_trans *ddi_translations;
f8896f5d 355
5f8b2531
RV		 356 if (IS_SKL_ULX(dev)) {
357 ddi_translations = skl_y_ddi_translations_dp;
358 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
f8896f5d
DW		 359 } else if (IS_SKL_ULT(dev)) {
360 ddi_translations = skl_u_ddi_translations_dp;
361 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
362 } else {
363 ddi_translations = skl_ddi_translations_dp;
364 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
365 }
366
367 return ddi_translations;
368}
369
370static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
371 int *n_entries)
372{
373 struct drm_i915_private *dev_priv = dev->dev_private;
374 const struct ddi_buf_trans *ddi_translations;
f8896f5d 375
5f8b2531 376 if (IS_SKL_ULX(dev)) {
f8896f5d 377 if (dev_priv->edp_low_vswing) {
5f8b2531
RV		 378 ddi_translations = skl_y_ddi_translations_edp;
379 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
f8896f5d 380 } else {
5f8b2531
RV		 381 ddi_translations = skl_y_ddi_translations_dp;
382 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
f8896f5d
DW		 383 }
384 } else if (IS_SKL_ULT(dev)) {
385 if (dev_priv->edp_low_vswing) {
386 ddi_translations = skl_u_ddi_translations_edp;
387 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
388 } else {
389 ddi_translations = skl_u_ddi_translations_dp;
390 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
391 }
392 } else {
393 if (dev_priv->edp_low_vswing) {
394 ddi_translations = skl_ddi_translations_edp;
395 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
396 } else {
397 ddi_translations = skl_ddi_translations_dp;
398 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
399 }
400 }
401
402 return ddi_translations;
403}
404
405static const struct ddi_buf_trans *
406skl_get_buf_trans_hdmi(struct drm_device *dev,
407 int *n_entries)
408{
f8896f5d 409 const struct ddi_buf_trans *ddi_translations;
f8896f5d 410
5f8b2531
RV		 411 if (IS_SKL_ULX(dev)) {
412 ddi_translations = skl_y_ddi_translations_hdmi;
413 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
f8896f5d
DW		 414 } else {
415 ddi_translations = skl_ddi_translations_hdmi;
416 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
417 }
418
419 return ddi_translations;
420}
421
e58623cb
AR		 422/*
423 * Starting with Haswell, DDI port buffers must be programmed with correct
424 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 425 * but the HDMI/DVI fields are shared among those. So we program the DDI
426 * in either FDI or DP modes only, as HDMI connections will work with both
427 * of those
428 */
faa0cdbe
ID		 429static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
430 bool supports_hdmi)
45244b87
ED		 431{
432 struct drm_i915_private *dev_priv = dev->dev_private;
75067dde 433 u32 iboost_bit = 0;
7ff44670 434 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 435 size;
6acab15a 436 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 437 const struct ddi_buf_trans *ddi_translations_fdi;
438 const struct ddi_buf_trans *ddi_translations_dp;
439 const struct ddi_buf_trans *ddi_translations_edp;
440 const struct ddi_buf_trans *ddi_translations_hdmi;
441 const struct ddi_buf_trans *ddi_translations;
e58623cb 442
96fb9f9b 443 if (IS_BROXTON(dev)) {
faa0cdbe 444 if (!supports_hdmi)
96fb9f9b
VK		 445 return;
446
447 /* Vswing programming for HDMI */
448 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
449 INTEL_OUTPUT_HDMI);
450 return;
ef11bdb3 451 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c30400fc 452 ddi_translations_fdi = NULL;
f8896f5d
DW		 453 ddi_translations_dp =
454 skl_get_buf_trans_dp(dev, &n_dp_entries);
455 ddi_translations_edp =
456 skl_get_buf_trans_edp(dev, &n_edp_entries);
457 ddi_translations_hdmi =
458 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
459 hdmi_default_entry = 8;
75067dde
AK		 460 /* If we're boosting the current, set bit 31 of trans1 */
461 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
462 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
463 iboost_bit = 1<<31;
7f88e3af 464 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 465 ddi_translations_fdi = bdw_ddi_translations_fdi;
466 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 467 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 468 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 469 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
470 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 471 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 472 hdmi_default_entry = 7;
e58623cb
AR		 473 } else if (IS_HASWELL(dev)) {
474 ddi_translations_fdi = hsw_ddi_translations_fdi;
475 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 476 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 477 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 478 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 479 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 480 hdmi_default_entry = 6;
e58623cb
AR		 481 } else {
482 WARN(1, "ddi translation table missing\n");
300644c7 483 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 484 ddi_translations_fdi = bdw_ddi_translations_fdi;
485 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 486 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 487 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
488 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 489 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 490 hdmi_default_entry = 7;
e58623cb
AR		 491 }
492
300644c7
PZ		 493 switch (port) {
494 case PORT_A:
495 ddi_translations = ddi_translations_edp;
7ad14a29 496 size = n_edp_entries;
300644c7
PZ		 497 break;
498 case PORT_B:
499 case PORT_C:
300644c7 500 ddi_translations = ddi_translations_dp;
7ad14a29 501 size = n_dp_entries;
300644c7 502 break;
77d8d009 503 case PORT_D:
7ad14a29 504 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 505 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 506 size = n_edp_entries;
507 } else {
77d8d009 508 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 509 size = n_dp_entries;
510 }
77d8d009 511 break;
300644c7 512 case PORT_E:
7f88e3af
DL		 513 if (ddi_translations_fdi)
514 ddi_translations = ddi_translations_fdi;
515 else
516 ddi_translations = ddi_translations_dp;
7ad14a29 517 size = n_dp_entries;
300644c7
PZ		 518 break;
519 default:
520 BUG();
521 }
45244b87 522
9712e688
VS		 523 for (i = 0; i < size; i++) {
524 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
525 ddi_translations[i].trans1 | iboost_bit);
526 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
527 ddi_translations[i].trans2);
45244b87 528 }
ce4dd49e 529
faa0cdbe 530 if (!supports_hdmi)
ce3b7e9b
DL		 531 return;
532
ce4dd49e
DL		 533 /* Choose a good default if VBT is badly populated */
534 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
535 hdmi_level >= n_hdmi_entries)
7ff44670 536 hdmi_level = hdmi_default_entry;
ce4dd49e 537
6acab15a 538 /* Entry 9 is for HDMI: */
9712e688
VS		 539 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
540 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
541 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
542 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 543}
544
545/* Program DDI buffers translations for DP. By default, program ports A-D in DP
546 * mode and port E for FDI.
547 */
548void intel_prepare_ddi(struct drm_device *dev)
549{
faa0cdbe 550 struct intel_encoder *intel_encoder;
b403745c 551 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 552
0d536cb4
PZ		 553 if (!HAS_DDI(dev))
554 return;
45244b87 555
faa0cdbe
ID		 556 for_each_intel_encoder(dev, intel_encoder) {
557 struct intel_digital_port *intel_dig_port;
558 enum port port;
559 bool supports_hdmi;
560
7d4aefd0
SS		 561 if (intel_encoder->type == INTEL_OUTPUT_DSI)
562 continue;
faa0cdbe 563
7d4aefd0 564 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
faa0cdbe 565 if (visited[port])
b403745c
DL		 566 continue;
567
faa0cdbe
ID		 568 supports_hdmi = intel_dig_port &&
569 intel_dig_port_supports_hdmi(intel_dig_port);
570
571 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
572 visited[port] = true;
b403745c 573 }
45244b87 574}
c82e4d26 575
248138b5
PZ		 576static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
577 enum port port)
578{
579 uint32_t reg = DDI_BUF_CTL(port);
580 int i;
581
3449ca85 582 for (i = 0; i < 16; i++) {
248138b5
PZ		 583 udelay(1);
584 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
585 return;
586 }
587 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
588}
c82e4d26
ED		 589
590/* Starting with Haswell, different DDI ports can work in FDI mode for
591 * connection to the PCH-located connectors. For this, it is necessary to train
592 * both the DDI port and PCH receiver for the desired DDI buffer settings.
593 *
594 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
595 * please note that when FDI mode is active on DDI E, it shares 2 lines with
596 * DDI A (which is used for eDP)
597 */
598
599void hsw_fdi_link_train(struct drm_crtc *crtc)
600{
601 struct drm_device *dev = crtc->dev;
602 struct drm_i915_private *dev_priv = dev->dev_private;
603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 604 u32 temp, i, rx_ctl_val;
c82e4d26 605
04945641
PZ		 606 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
607 * mode set "sequence for CRT port" document:
608 * - TP1 to TP2 time with the default value
609 * - FDI delay to 90h
8693a824
DL		 610 *
611 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 612 */
eede3b53 613 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 614 FDI_RX_PWRDN_LANE0_VAL(2) |
615 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
616
617 /* Enable the PCH Receiver FDI PLL */
3e68320e 618 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 619 FDI_RX_PLL_ENABLE |
6e3c9717 620 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
eede3b53
VS		 621 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
622 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 623 udelay(220);
624
625 /* Switch from Rawclk to PCDclk */
626 rx_ctl_val |= FDI_PCDCLK;
eede3b53 627 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 628
629 /* Configure Port Clock Select */
6e3c9717
ACO		 630 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
631 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 632
633 /* Start the training iterating through available voltages and emphasis,
634 * testing each value twice. */
10122051 635 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 636 /* Configure DP_TP_CTL with auto-training */
637 I915_WRITE(DP_TP_CTL(PORT_E),
638 DP_TP_CTL_FDI_AUTOTRAIN |
639 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
640 DP_TP_CTL_LINK_TRAIN_PAT1 |
641 DP_TP_CTL_ENABLE);
642
876a8cdf
DL		 643 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
644 * DDI E does not support port reversal, the functionality is
645 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
646 * port reversal bit */
c82e4d26 647 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 648 DDI_BUF_CTL_ENABLE |
6e3c9717 649 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 650 DDI_BUF_TRANS_SELECT(i / 2));
04945641 651 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 652
653 udelay(600);
654
04945641 655 /* Program PCH FDI Receiver TU */
eede3b53 656 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 657
658 /* Enable PCH FDI Receiver with auto-training */
659 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 660 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
661 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 662
663 /* Wait for FDI receiver lane calibration */
664 udelay(30);
665
666 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 667 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 668 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 669 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
670 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 671
672 /* Wait for FDI auto training time */
673 udelay(5);
c82e4d26
ED		 674
675 temp = I915_READ(DP_TP_STATUS(PORT_E));
676 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 677 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 678
679 /* Enable normal pixel sending for FDI */
680 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 681 DP_TP_CTL_FDI_AUTOTRAIN |
682 DP_TP_CTL_LINK_TRAIN_NORMAL |
683 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
684 DP_TP_CTL_ENABLE);
c82e4d26 685
04945641 686 return;
c82e4d26 687 }
04945641 688
248138b5
PZ		 689 temp = I915_READ(DDI_BUF_CTL(PORT_E));
690 temp &= ~DDI_BUF_CTL_ENABLE;
691 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
692 POSTING_READ(DDI_BUF_CTL(PORT_E));
693
04945641 694 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 695 temp = I915_READ(DP_TP_CTL(PORT_E));
696 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
697 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
698 I915_WRITE(DP_TP_CTL(PORT_E), temp);
699 POSTING_READ(DP_TP_CTL(PORT_E));
700
701 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 702
703 rx_ctl_val &= ~FDI_RX_ENABLE;
eede3b53
VS		 704 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
705 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 706
707 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 708 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 709 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
710 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 711 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
712 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 713 }
714
04945641 715 DRM_ERROR("FDI link training failed!\n");
c82e4d26 716}
0e72a5b5 717
44905a27
DA		 718void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
719{
720 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
721 struct intel_digital_port *intel_dig_port =
722 enc_to_dig_port(&encoder->base);
723
724 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 725 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 726 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 727}
728
8d9ddbcb
PZ		 729static struct intel_encoder *
730intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
731{
732 struct drm_device *dev = crtc->dev;
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734 struct intel_encoder *intel_encoder, *ret = NULL;
735 int num_encoders = 0;
736
737 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
738 ret = intel_encoder;
739 num_encoders++;
740 }
741
742 if (num_encoders != 1)
84f44ce7
VS		 743 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
744 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 745
746 BUG_ON(ret == NULL);
747 return ret;
748}
749
bcddf610 750struct intel_encoder *
3165c074 751intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 752{
3165c074
ACO		 753 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
754 struct intel_encoder *ret = NULL;
755 struct drm_atomic_state *state;
da3ced29
ACO		 756 struct drm_connector *connector;
757 struct drm_connector_state *connector_state;
d0737e1d 758 int num_encoders = 0;
3165c074 759 int i;
d0737e1d 760
3165c074
ACO		 761 state = crtc_state->base.state;
762
da3ced29
ACO		 763 for_each_connector_in_state(state, connector, connector_state, i) {
764 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 765 continue;
766
da3ced29 767 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 768 num_encoders++;
d0737e1d
ACO		 769 }
770
771 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
772 pipe_name(crtc->pipe));
773
774 BUG_ON(ret == NULL);
775 return ret;
776}
777
1c0b85c5 778#define LC_FREQ 2700
27893390 779#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 780
781#define P_MIN 2
782#define P_MAX 64
783#define P_INC 2
784
785/* Constraints for PLL good behavior */
786#define REF_MIN 48
787#define REF_MAX 400
788#define VCO_MIN 2400
789#define VCO_MAX 4800
790
27893390
DL		 791#define abs_diff(a, b) ({ \
792 typeof(a) __a = (a); \
793 typeof(b) __b = (b); \
794 (void) (&__a == &__b); \
795 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 796
63582983 797struct hsw_wrpll_rnp {
1c0b85c5
DL		 798 unsigned p, n2, r2;
799};
800
63582983 801static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 802{
1c0b85c5
DL		 803 unsigned budget;
804
805 switch (clock) {
806 case 25175000:
807 case 25200000:
808 case 27000000:
809 case 27027000:
810 case 37762500:
811 case 37800000:
812 case 40500000:
813 case 40541000:
814 case 54000000:
815 case 54054000:
816 case 59341000:
817 case 59400000:
818 case 72000000:
819 case 74176000:
820 case 74250000:
821 case 81000000:
822 case 81081000:
823 case 89012000:
824 case 89100000:
825 case 108000000:
826 case 108108000:
827 case 111264000:
828 case 111375000:
829 case 148352000:
830 case 148500000:
831 case 162000000:
832 case 162162000:
833 case 222525000:
834 case 222750000:
835 case 296703000:
836 case 297000000:
837 budget = 0;
838 break;
839 case 233500000:
840 case 245250000:
841 case 247750000:
842 case 253250000:
843 case 298000000:
844 budget = 1500;
845 break;
846 case 169128000:
847 case 169500000:
848 case 179500000:
849 case 202000000:
850 budget = 2000;
851 break;
852 case 256250000:
853 case 262500000:
854 case 270000000:
855 case 272500000:
856 case 273750000:
857 case 280750000:
858 case 281250000:
859 case 286000000:
860 case 291750000:
861 budget = 4000;
862 break;
863 case 267250000:
864 case 268500000:
865 budget = 5000;
866 break;
867 default:
868 budget = 1000;
869 break;
870 }
6441ab5f 871
1c0b85c5
DL		 872 return budget;
873}
874
63582983
DL		 875static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
876 unsigned r2, unsigned n2, unsigned p,
877 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 878{
879 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 880
1c0b85c5
DL		 881 /* No best (r,n,p) yet */
882 if (best->p == 0) {
883 best->p = p;
884 best->n2 = n2;
885 best->r2 = r2;
886 return;
887 }
6441ab5f 888
1c0b85c5
DL		 889 /*
890 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
891 * freq2k.
892 *
893 * delta = 1e6 *
894 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
895 * freq2k;
896 *
897 * and we would like delta <= budget.
898 *
899 * If the discrepancy is above the PPM-based budget, always prefer to
900 * improve upon the previous solution. However, if you're within the
901 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
902 */
903 a = freq2k * budget * p * r2;
904 b = freq2k * budget * best->p * best->r2;
27893390
DL		 905 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
906 diff_best = abs_diff(freq2k * best->p * best->r2,
907 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 908 c = 1000000 * diff;
909 d = 1000000 * diff_best;
910
911 if (a < c && b < d) {
912 /* If both are above the budget, pick the closer */
913 if (best->p * best->r2 * diff < p * r2 * diff_best) {
914 best->p = p;
915 best->n2 = n2;
916 best->r2 = r2;
917 }
918 } else if (a >= c && b < d) {
919 /* If A is below the threshold but B is above it? Update. */
920 best->p = p;
921 best->n2 = n2;
922 best->r2 = r2;
923 } else if (a >= c && b >= d) {
924 /* Both are below the limit, so pick the higher n2/(r2*r2) */
925 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
926 best->p = p;
927 best->n2 = n2;
928 best->r2 = r2;
929 }
930 }
931 /* Otherwise a < c && b >= d, do nothing */
932}
933
63582983 934static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 935{
936 int refclk = LC_FREQ;
937 int n, p, r;
938 u32 wrpll;
939
940 wrpll = I915_READ(reg);
114fe488
DV		 941 switch (wrpll & WRPLL_PLL_REF_MASK) {
942 case WRPLL_PLL_SSC:
943 case WRPLL_PLL_NON_SSC:
11578553
JB		 944 /*
945 * We could calculate spread here, but our checking
946 * code only cares about 5% accuracy, and spread is a max of
947 * 0.5% downspread.
948 */
949 refclk = 135;
950 break;
114fe488 951 case WRPLL_PLL_LCPLL:
11578553
JB		 952 refclk = LC_FREQ;
953 break;
954 default:
955 WARN(1, "bad wrpll refclk\n");
956 return 0;
957 }
958
959 r = wrpll & WRPLL_DIVIDER_REF_MASK;
960 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
961 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
962
20f0ec16
JB		 963 /* Convert to KHz, p & r have a fixed point portion */
964 return (refclk * n * 100) / (p * r);
11578553
JB		 965}
966
540e732c
S		 967static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
968 uint32_t dpll)
969{
970 uint32_t cfgcr1_reg, cfgcr2_reg;
971 uint32_t cfgcr1_val, cfgcr2_val;
972 uint32_t p0, p1, p2, dco_freq;
973
923c1241
VS		 974 cfgcr1_reg = DPLL_CFGCR1(dpll);
975 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 976
977 cfgcr1_val = I915_READ(cfgcr1_reg);
978 cfgcr2_val = I915_READ(cfgcr2_reg);
979
980 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
981 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
982
983 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
984 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
985 else
986 p1 = 1;
987
988
989 switch (p0) {
990 case DPLL_CFGCR2_PDIV_1:
991 p0 = 1;
992 break;
993 case DPLL_CFGCR2_PDIV_2:
994 p0 = 2;
995 break;
996 case DPLL_CFGCR2_PDIV_3:
997 p0 = 3;
998 break;
999 case DPLL_CFGCR2_PDIV_7:
1000 p0 = 7;
1001 break;
1002 }
1003
1004 switch (p2) {
1005 case DPLL_CFGCR2_KDIV_5:
1006 p2 = 5;
1007 break;
1008 case DPLL_CFGCR2_KDIV_2:
1009 p2 = 2;
1010 break;
1011 case DPLL_CFGCR2_KDIV_3:
1012 p2 = 3;
1013 break;
1014 case DPLL_CFGCR2_KDIV_1:
1015 p2 = 1;
1016 break;
1017 }
1018
1019 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1020
1021 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1022 1000) / 0x8000;
1023
1024 return dco_freq / (p0 * p1 * p2 * 5);
1025}
1026
398a017e
VS		 1027static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1028{
1029 int dotclock;
1030
1031 if (pipe_config->has_pch_encoder)
1032 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1033 &pipe_config->fdi_m_n);
1034 else if (pipe_config->has_dp_encoder)
1035 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1036 &pipe_config->dp_m_n);
1037 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1038 dotclock = pipe_config->port_clock * 2 / 3;
1039 else
1040 dotclock = pipe_config->port_clock;
1041
1042 if (pipe_config->pixel_multiplier)
1043 dotclock /= pipe_config->pixel_multiplier;
1044
1045 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1046}
540e732c
S		 1047
1048static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1049 struct intel_crtc_state *pipe_config)
540e732c
S		 1050{
1051 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1052 int link_clock = 0;
1053 uint32_t dpll_ctl1, dpll;
1054
134ffa44 1055 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1056
1057 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1058
1059 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1060 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1061 } else {
71cd8423
DL		 1062 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1063 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1064
1065 switch (link_clock) {
71cd8423 1066 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1067 link_clock = 81000;
1068 break;
71cd8423 1069 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1070 link_clock = 108000;
1071 break;
71cd8423 1072 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1073 link_clock = 135000;
1074 break;
71cd8423 1075 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1076 link_clock = 162000;
1077 break;
71cd8423 1078 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1079 link_clock = 216000;
1080 break;
71cd8423 1081 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1082 link_clock = 270000;
1083 break;
1084 default:
1085 WARN(1, "Unsupported link rate\n");
1086 break;
1087 }
1088 link_clock *= 2;
1089 }
1090
1091 pipe_config->port_clock = link_clock;
1092
398a017e 1093 ddi_dotclock_get(pipe_config);
540e732c
S		 1094}
1095
3d51278a 1096static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1097 struct intel_crtc_state *pipe_config)
11578553
JB		 1098{
1099 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1100 int link_clock = 0;
1101 u32 val, pll;
1102
26804afd 1103 val = pipe_config->ddi_pll_sel;
11578553
JB		 1104 switch (val & PORT_CLK_SEL_MASK) {
1105 case PORT_CLK_SEL_LCPLL_810:
1106 link_clock = 81000;
1107 break;
1108 case PORT_CLK_SEL_LCPLL_1350:
1109 link_clock = 135000;
1110 break;
1111 case PORT_CLK_SEL_LCPLL_2700:
1112 link_clock = 270000;
1113 break;
1114 case PORT_CLK_SEL_WRPLL1:
01403de3 1115 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1116 break;
1117 case PORT_CLK_SEL_WRPLL2:
01403de3 1118 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1119 break;
1120 case PORT_CLK_SEL_SPLL:
1121 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1122 if (pll == SPLL_PLL_FREQ_810MHz)
1123 link_clock = 81000;
1124 else if (pll == SPLL_PLL_FREQ_1350MHz)
1125 link_clock = 135000;
1126 else if (pll == SPLL_PLL_FREQ_2700MHz)
1127 link_clock = 270000;
1128 else {
1129 WARN(1, "bad spll freq\n");
1130 return;
1131 }
1132 break;
1133 default:
1134 WARN(1, "bad port clock sel\n");
1135 return;
1136 }
1137
1138 pipe_config->port_clock = link_clock * 2;
1139
398a017e 1140 ddi_dotclock_get(pipe_config);
11578553
JB		 1141}
1142
977bb38d
S		 1143static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1144 enum intel_dpll_id dpll)
1145{
aa610dcb
ID		 1146 struct intel_shared_dpll *pll;
1147 struct intel_dpll_hw_state *state;
1148 intel_clock_t clock;
1149
1150 /* For DDI ports we always use a shared PLL. */
1151 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1152 return 0;
1153
1154 pll = &dev_priv->shared_dplls[dpll];
1155 state = &pll->config.hw_state;
1156
1157 clock.m1 = 2;
1158 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1159 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1160 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1161 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1162 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1163 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1164
1165 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1166}
1167
1168static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1169 struct intel_crtc_state *pipe_config)
1170{
1171 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1172 enum port port = intel_ddi_get_encoder_port(encoder);
1173 uint32_t dpll = port;
1174
398a017e 1175 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1176
398a017e 1177 ddi_dotclock_get(pipe_config);
977bb38d
S		 1178}
1179
3d51278a 1180void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1181 struct intel_crtc_state *pipe_config)
3d51278a 1182{
22606a18
DL		 1183 struct drm_device *dev = encoder->base.dev;
1184
1185 if (INTEL_INFO(dev)->gen <= 8)
1186 hsw_ddi_clock_get(encoder, pipe_config);
ef11bdb3 1187 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
22606a18 1188 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1189 else if (IS_BROXTON(dev))
1190 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1191}
1192
1c0b85c5 1193static void
d664c0ce
DL		 1194hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1195 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1196{
1197 uint64_t freq2k;
1198 unsigned p, n2, r2;
63582983 1199 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1200 unsigned budget;
1201
1202 freq2k = clock / 100;
1203
63582983 1204 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1205
1206 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1207 * and directly pass the LC PLL to it. */
1208 if (freq2k == 5400000) {
1209 *n2_out = 2;
1210 *p_out = 1;
1211 *r2_out = 2;
1212 return;
1213 }
1214
1215 /*
1216 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1217 * the WR PLL.
1218 *
1219 * We want R so that REF_MIN <= Ref <= REF_MAX.
1220 * Injecting R2 = 2 * R gives:
1221 * REF_MAX * r2 > LC_FREQ * 2 and
1222 * REF_MIN * r2 < LC_FREQ * 2
1223 *
1224 * Which means the desired boundaries for r2 are:
1225 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1226 *
1227 */
1228 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1229 r2 <= LC_FREQ * 2 / REF_MIN;
1230 r2++) {
1231
1232 /*
1233 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1234 *
1235 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1236 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1237 * VCO_MAX * r2 > n2 * LC_FREQ and
1238 * VCO_MIN * r2 < n2 * LC_FREQ)
1239 *
1240 * Which means the desired boundaries for n2 are:
1241 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1242 */
1243 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1244 n2 <= VCO_MAX * r2 / LC_FREQ;
1245 n2++) {
1246
1247 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1248 hsw_wrpll_update_rnp(freq2k, budget,
1249 r2, n2, p, &best);
1c0b85c5
DL		 1250 }
1251 }
6441ab5f 1252
1c0b85c5
DL		 1253 *n2_out = best.n2;
1254 *p_out = best.p;
1255 *r2_out = best.r2;
6441ab5f
PZ		 1256}
1257
0220ab6e 1258static bool
d664c0ce 1259hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1260 struct intel_crtc_state *crtc_state,
96f3f1f9 1261 struct intel_encoder *intel_encoder)
6441ab5f 1262{
96f3f1f9
VS		 1263 int clock = crtc_state->port_clock;
1264
d664c0ce 1265 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1266 struct intel_shared_dpll *pll;
716c2e55 1267 uint32_t val;
1c0b85c5 1268 unsigned p, n2, r2;
6441ab5f 1269
d664c0ce 1270 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1271
114fe488 1272 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1273 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1274 WRPLL_DIVIDER_POST(p);
1275
dd3cd74a
ACO		 1276 memset(&crtc_state->dpll_hw_state, 0,
1277 sizeof(crtc_state->dpll_hw_state));
1278
190f68c5 1279 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1280
190f68c5 1281 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1282 if (pll == NULL) {
1283 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1284 pipe_name(intel_crtc->pipe));
1285 return false;
0694001b 1286 }
d452c5b6 1287
190f68c5 1288 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1289 }
1290
6441ab5f
PZ		 1291 return true;
1292}
1293
dc253813
DL		 1294struct skl_wrpll_context {
1295 uint64_t min_deviation; /* current minimal deviation */
1296 uint64_t central_freq; /* chosen central freq */
1297 uint64_t dco_freq; /* chosen dco freq */
1298 unsigned int p; /* chosen divider */
1299};
1300
1301static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1302{
1303 memset(ctx, 0, sizeof(*ctx));
1304
1305 ctx->min_deviation = U64_MAX;
1306}
1307
1308/* DCO freq must be within +1%/-6% of the DCO central freq */
1309#define SKL_DCO_MAX_PDEVIATION 100
1310#define SKL_DCO_MAX_NDEVIATION 600
1311
1312static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1313 uint64_t central_freq,
1314 uint64_t dco_freq,
1315 unsigned int divider)
1316{
1317 uint64_t deviation;
1318
1319 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1320 central_freq);
1321
1322 /* positive deviation */
1323 if (dco_freq >= central_freq) {
1324 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1325 deviation < ctx->min_deviation) {
1326 ctx->min_deviation = deviation;
1327 ctx->central_freq = central_freq;
1328 ctx->dco_freq = dco_freq;
1329 ctx->p = divider;
1330 }
1331 /* negative deviation */
1332 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1333 deviation < ctx->min_deviation) {
1334 ctx->min_deviation = deviation;
1335 ctx->central_freq = central_freq;
1336 ctx->dco_freq = dco_freq;
1337 ctx->p = divider;
1338 }
dc253813
DL		 1339}
1340
1341static void skl_wrpll_get_multipliers(unsigned int p,
1342 unsigned int *p0 /* out */,
1343 unsigned int *p1 /* out */,
1344 unsigned int *p2 /* out */)
1345{
1346 /* even dividers */
1347 if (p % 2 == 0) {
1348 unsigned int half = p / 2;
1349
1350 if (half == 1 || half == 2 || half == 3 || half == 5) {
1351 *p0 = 2;
1352 *p1 = 1;
1353 *p2 = half;
1354 } else if (half % 2 == 0) {
1355 *p0 = 2;
1356 *p1 = half / 2;
1357 *p2 = 2;
1358 } else if (half % 3 == 0) {
1359 *p0 = 3;
1360 *p1 = half / 3;
1361 *p2 = 2;
1362 } else if (half % 7 == 0) {
1363 *p0 = 7;
1364 *p1 = half / 7;
1365 *p2 = 2;
1366 }
1367 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1368 *p0 = 3;
1369 *p1 = 1;
1370 *p2 = p / 3;
1371 } else if (p == 5 || p == 7) {
1372 *p0 = p;
1373 *p1 = 1;
1374 *p2 = 1;
1375 } else if (p == 15) {
1376 *p0 = 3;
1377 *p1 = 1;
1378 *p2 = 5;
1379 } else if (p == 21) {
1380 *p0 = 7;
1381 *p1 = 1;
1382 *p2 = 3;
1383 } else if (p == 35) {
1384 *p0 = 7;
1385 *p1 = 1;
1386 *p2 = 5;
1387 }
1388}
1389
82d35437
S		 1390struct skl_wrpll_params {
1391 uint32_t dco_fraction;
1392 uint32_t dco_integer;
1393 uint32_t qdiv_ratio;
1394 uint32_t qdiv_mode;
1395 uint32_t kdiv;
1396 uint32_t pdiv;
1397 uint32_t central_freq;
1398};
1399
76516fbc
DL		 1400static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1401 uint64_t afe_clock,
1402 uint64_t central_freq,
1403 uint32_t p0, uint32_t p1, uint32_t p2)
1404{
1405 uint64_t dco_freq;
1406
76516fbc
DL		 1407 switch (central_freq) {
1408 case 9600000000ULL:
1409 params->central_freq = 0;
1410 break;
1411 case 9000000000ULL:
1412 params->central_freq = 1;
1413 break;
1414 case 8400000000ULL:
1415 params->central_freq = 3;
1416 }
1417
1418 switch (p0) {
1419 case 1:
1420 params->pdiv = 0;
1421 break;
1422 case 2:
1423 params->pdiv = 1;
1424 break;
1425 case 3:
1426 params->pdiv = 2;
1427 break;
1428 case 7:
1429 params->pdiv = 4;
1430 break;
1431 default:
1432 WARN(1, "Incorrect PDiv\n");
1433 }
1434
1435 switch (p2) {
1436 case 5:
1437 params->kdiv = 0;
1438 break;
1439 case 2:
1440 params->kdiv = 1;
1441 break;
1442 case 3:
1443 params->kdiv = 2;
1444 break;
1445 case 1:
1446 params->kdiv = 3;
1447 break;
1448 default:
1449 WARN(1, "Incorrect KDiv\n");
1450 }
1451
1452 params->qdiv_ratio = p1;
1453 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1454
1455 dco_freq = p0 * p1 * p2 * afe_clock;
1456
1457 /*
1458 * Intermediate values are in Hz.
1459 * Divide by MHz to match bsepc
1460 */
30a7862d 1461 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1462 params->dco_fraction =
30a7862d
DL		 1463 div_u64((div_u64(dco_freq, 24) -
1464 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1465}
1466
318bd821 1467static bool
82d35437
S		 1468skl_ddi_calculate_wrpll(int clock /* in Hz */,
1469 struct skl_wrpll_params *wrpll_params)
1470{
1471 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1472 uint64_t dco_central_freq[3] = {8400000000ULL,
1473 9000000000ULL,
1474 9600000000ULL};
dc253813
DL		 1475 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1476 24, 28, 30, 32, 36, 40, 42, 44,
1477 48, 52, 54, 56, 60, 64, 66, 68,
1478 70, 72, 76, 78, 80, 84, 88, 90,
1479 92, 96, 98 };
1480 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1481 static const struct {
1482 const int *list;
1483 int n_dividers;
1484 } dividers[] = {
1485 { even_dividers, ARRAY_SIZE(even_dividers) },
1486 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1487 };
1488 struct skl_wrpll_context ctx;
1489 unsigned int dco, d, i;
1490 unsigned int p0, p1, p2;
1491
1492 skl_wrpll_context_init(&ctx);
1493
1494 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1495 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1496 for (i = 0; i < dividers[d].n_dividers; i++) {
1497 unsigned int p = dividers[d].list[i];
1498 uint64_t dco_freq = p * afe_clock;
1499
1500 skl_wrpll_try_divider(&ctx,
1501 dco_central_freq[dco],
1502 dco_freq,
1503 p);
e7ad9878
DL		 1504 /*
1505 * Skip the remaining dividers if we're sure to
1506 * have found the definitive divider, we can't
1507 * improve a 0 deviation.
1508 */
1509 if (ctx.min_deviation == 0)
1510 goto skip_remaining_dividers;
82d35437
S		 1511 }
1512 }
267db663 1513
e7ad9878 1514skip_remaining_dividers:
267db663
DL		 1515 /*
1516 * If a solution is found with an even divider, prefer
1517 * this one.
1518 */
1519 if (d == 0 && ctx.p)
1520 break;
82d35437
S		 1521 }
1522
dc253813
DL		 1523 if (!ctx.p) {
1524 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1525 return false;
dc253813 1526 }
82d35437 1527
dc253813
DL		 1528 /*
1529 * gcc incorrectly analyses that these can be used without being
1530 * initialized. To be fair, it's hard to guess.
1531 */
1532 p0 = p1 = p2 = 0;
1533 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1534 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1535 p0, p1, p2);
318bd821
DL		 1536
1537 return true;
82d35437
S		 1538}
1539
82d35437
S		 1540static bool
1541skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1542 struct intel_crtc_state *crtc_state,
96f3f1f9 1543 struct intel_encoder *intel_encoder)
82d35437
S		 1544{
1545 struct intel_shared_dpll *pll;
1546 uint32_t ctrl1, cfgcr1, cfgcr2;
96f3f1f9 1547 int clock = crtc_state->port_clock;
82d35437
S		 1548
1549 /*
1550 * See comment in intel_dpll_hw_state to understand why we always use 0
1551 * as the DPLL id in this function.
1552 */
1553
1554 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1555
1556 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1557 struct skl_wrpll_params wrpll_params = { 0, };
1558
1559 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1560
318bd821
DL		 1561 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1562 return false;
82d35437
S		 1563
1564 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1565 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1566 wrpll_params.dco_integer;
1567
1568 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1569 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1570 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1571 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1572 wrpll_params.central_freq;
1573 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
840b32b7
VS		 1574 switch (crtc_state->port_clock / 2) {
1575 case 81000:
71cd8423 1576 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437 1577 break;
840b32b7 1578 case 135000:
71cd8423 1579 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437 1580 break;
840b32b7 1581 case 270000:
71cd8423 1582 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1583 break;
1584 }
1585
1586 cfgcr1 = cfgcr2 = 0;
1587 } else /* eDP */
1588 return true;
1589
dd3cd74a
ACO		 1590 memset(&crtc_state->dpll_hw_state, 0,
1591 sizeof(crtc_state->dpll_hw_state));
1592
190f68c5
ACO		 1593 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1594 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1595 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1596
190f68c5 1597 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1598 if (pll == NULL) {
1599 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1600 pipe_name(intel_crtc->pipe));
1601 return false;
1602 }
1603
1604 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1605 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1606
1607 return true;
1608}
0220ab6e 1609
d683f3bc
S		 1610/* bxt clock parameters */
1611struct bxt_clk_div {
64987fc5 1612 int clock;
d683f3bc
S		 1613 uint32_t p1;
1614 uint32_t p2;
1615 uint32_t m2_int;
1616 uint32_t m2_frac;
1617 bool m2_frac_en;
1618 uint32_t n;
d683f3bc
S		 1619};
1620
1621/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1622static const struct bxt_clk_div bxt_dp_clk_val[] = {
1623 {162000, 4, 2, 32, 1677722, 1, 1},
1624 {270000, 4, 1, 27, 0, 0, 1},
1625 {540000, 2, 1, 27, 0, 0, 1},
1626 {216000, 3, 2, 32, 1677722, 1, 1},
1627 {243000, 4, 1, 24, 1258291, 1, 1},
1628 {324000, 4, 1, 32, 1677722, 1, 1},
1629 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1630};
1631
1632static bool
1633bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1634 struct intel_crtc_state *crtc_state,
96f3f1f9 1635 struct intel_encoder *intel_encoder)
d683f3bc
S		 1636{
1637 struct intel_shared_dpll *pll;
1638 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1639 int vco = 0;
1640 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1641 uint32_t lanestagger;
96f3f1f9 1642 int clock = crtc_state->port_clock;
d683f3bc
S		 1643
1644 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1645 intel_clock_t best_clock;
1646
1647 /* Calculate HDMI div */
1648 /*
1649 * FIXME: tie the following calculation into
1650 * i9xx_crtc_compute_clock
1651 */
1652 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1653 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1654 clock, pipe_name(intel_crtc->pipe));
1655 return false;
1656 }
1657
1658 clk_div.p1 = best_clock.p1;
1659 clk_div.p2 = best_clock.p2;
1660 WARN_ON(best_clock.m1 != 2);
1661 clk_div.n = best_clock.n;
1662 clk_div.m2_int = best_clock.m2 >> 22;
1663 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1664 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1665
b6dc71f3 1666 vco = best_clock.vco;
d683f3bc
S		 1667 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1668 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1669 int i;
d683f3bc 1670
64987fc5
SJ		 1671 clk_div = bxt_dp_clk_val[0];
1672 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1673 if (bxt_dp_clk_val[i].clock == clock) {
1674 clk_div = bxt_dp_clk_val[i];
1675 break;
1676 }
d683f3bc 1677 }
b6dc71f3
VK		 1678 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1679 }
1680
e6292556 1681 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1682 prop_coef = 4;
1683 int_coef = 9;
1684 gain_ctl = 3;
1685 targ_cnt = 8;
1686 } else if ((vco > 5400000 && vco < 6200000) ||
1687 (vco >= 4800000 && vco < 5400000)) {
1688 prop_coef = 5;
1689 int_coef = 11;
1690 gain_ctl = 3;
1691 targ_cnt = 9;
b6dc71f3
VK		 1692 } else if (vco == 5400000) {
1693 prop_coef = 3;
1694 int_coef = 8;
1695 gain_ctl = 1;
1696 targ_cnt = 9;
1697 } else {
1698 DRM_ERROR("Invalid VCO\n");
1699 return false;
d683f3bc
S		 1700 }
1701
dd3cd74a
ACO		 1702 memset(&crtc_state->dpll_hw_state, 0,
1703 sizeof(crtc_state->dpll_hw_state));
1704
e0681e38
VK		 1705 if (clock > 270000)
1706 lanestagger = 0x18;
1707 else if (clock > 135000)
1708 lanestagger = 0x0d;
1709 else if (clock > 67000)
1710 lanestagger = 0x07;
1711 else if (clock > 33000)
1712 lanestagger = 0x04;
1713 else
1714 lanestagger = 0x02;
1715
d683f3bc
S		 1716 crtc_state->dpll_hw_state.ebb0 =
1717 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1718 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1719 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1720 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1721
1722 if (clk_div.m2_frac_en)
1723 crtc_state->dpll_hw_state.pll3 =
1724 PORT_PLL_M2_FRAC_ENABLE;
1725
1726 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1727 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1728 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1729 PORT_PLL_GAIN_CTL(gain_ctl);
1730
1731 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1732
05712c15
ID		 1733 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1734
e6292556
VK		 1735 crtc_state->dpll_hw_state.pll10 =
1736 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1737 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1738
05712c15
ID		 1739 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1740
d683f3bc 1741 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1742 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1743
1744 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1745 if (pll == NULL) {
1746 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1747 pipe_name(intel_crtc->pipe));
1748 return false;
1749 }
1750
1751 /* shared DPLL id 0 is DPLL A */
1752 crtc_state->ddi_pll_sel = pll->id;
1753
1754 return true;
1755}
1756
0220ab6e
DL		 1757/*
1758 * Tries to find a *shared* PLL for the CRTC and store it in
1759 * intel_crtc->ddi_pll_sel.
1760 *
1761 * For private DPLLs, compute_config() should do the selection for us. This
1762 * function should be folded into compute_config() eventually.
1763 */
190f68c5
ACO		 1764bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1765 struct intel_crtc_state *crtc_state)
0220ab6e 1766{
82d35437 1767 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1768 struct intel_encoder *intel_encoder =
3165c074 1769 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1770
ef11bdb3 1771 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
190f68c5 1772 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1773 intel_encoder);
d683f3bc
S		 1774 else if (IS_BROXTON(dev))
1775 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1776 intel_encoder);
82d35437 1777 else
190f68c5 1778 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1779 intel_encoder);
0220ab6e
DL		 1780}
1781
dae84799
PZ		 1782void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1783{
1784 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1786 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1787 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1788 int type = intel_encoder->type;
1789 uint32_t temp;
1790
0e32b39c 1791 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1792 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1793 switch (intel_crtc->config->pipe_bpp) {
dae84799 1794 case 18:
c9809791 1795 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1796 break;
1797 case 24:
c9809791 1798 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1799 break;
1800 case 30:
c9809791 1801 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1802 break;
1803 case 36:
c9809791 1804 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1805 break;
1806 default:
4e53c2e0 1807 BUG();
dae84799 1808 }
c9809791 1809 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1810 }
1811}
1812
0e32b39c
DA		 1813void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1814{
1815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1816 struct drm_device *dev = crtc->dev;
1817 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1818 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1819 uint32_t temp;
1820 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1821 if (state == true)
1822 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1823 else
1824 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1825 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1826}
1827
8228c251 1828void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1829{
1830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1831 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1832 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1833 struct drm_device *dev = crtc->dev;
1834 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1835 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1836 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1837 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1838 int type = intel_encoder->type;
8d9ddbcb
PZ		 1839 uint32_t temp;
1840
ad80a810
PZ		 1841 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1842 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1843 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1844
6e3c9717 1845 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1846 case 18:
ad80a810 1847 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1848 break;
1849 case 24:
ad80a810 1850 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1851 break;
1852 case 30:
ad80a810 1853 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1854 break;
1855 case 36:
ad80a810 1856 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1857 break;
1858 default:
4e53c2e0 1859 BUG();
dfcef252 1860 }
72662e10 1861
6e3c9717 1862 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1863 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1864 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1865 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1866
e6f0bfc4
PZ		 1867 if (cpu_transcoder == TRANSCODER_EDP) {
1868 switch (pipe) {
1869 case PIPE_A:
c7670b10
PZ		 1870 /* On Haswell, can only use the always-on power well for
1871 * eDP when not using the panel fitter, and when not
1872 * using motion blur mitigation (which we don't
1873 * support). */
fabf6e51 1874 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1875 (intel_crtc->config->pch_pfit.enabled ||
1876 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1877 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1878 else
1879 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1880 break;
1881 case PIPE_B:
1882 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1883 break;
1884 case PIPE_C:
1885 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1886 break;
1887 default:
1888 BUG();
1889 break;
1890 }
1891 }
1892
7739c33b 1893 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1894 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1895 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1896 else
ad80a810 1897 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1898
7739c33b 1899 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1900 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1901 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1902
1903 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1904 type == INTEL_OUTPUT_EDP) {
1905 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1906
0e32b39c
DA		 1907 if (intel_dp->is_mst) {
1908 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1909 } else
1910 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1911
90a6b7b0 1912 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1913 } else if (type == INTEL_OUTPUT_DP_MST) {
1914 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1915
1916 if (intel_dp->is_mst) {
1917 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1918 } else
1919 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1920
90a6b7b0 1921 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1922 } else {
84f44ce7
VS		 1923 WARN(1, "Invalid encoder type %d for pipe %c\n",
1924 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1925 }
1926
ad80a810 1927 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1928}
72662e10 1929
ad80a810
PZ		 1930void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1931 enum transcoder cpu_transcoder)
8d9ddbcb 1932{
ad80a810 1933 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1934 uint32_t val = I915_READ(reg);
1935
0e32b39c 1936 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1937 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1938 I915_WRITE(reg, val);
72662e10
ED		 1939}
1940
bcbc889b
PZ		 1941bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1942{
1943 struct drm_device *dev = intel_connector->base.dev;
1944 struct drm_i915_private *dev_priv = dev->dev_private;
1945 struct intel_encoder *intel_encoder = intel_connector->encoder;
1946 int type = intel_connector->base.connector_type;
1947 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1948 enum pipe pipe = 0;
1949 enum transcoder cpu_transcoder;
882244a3 1950 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1951 uint32_t tmp;
1952
882244a3 1953 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1954 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1955 return false;
1956
bcbc889b
PZ		 1957 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1958 return false;
1959
1960 if (port == PORT_A)
1961 cpu_transcoder = TRANSCODER_EDP;
1962 else
1a240d4d 1963 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1964
1965 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1966
1967 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1968 case TRANS_DDI_MODE_SELECT_HDMI:
1969 case TRANS_DDI_MODE_SELECT_DVI:
1970 return (type == DRM_MODE_CONNECTOR_HDMIA);
1971
1972 case TRANS_DDI_MODE_SELECT_DP_SST:
1973 if (type == DRM_MODE_CONNECTOR_eDP)
1974 return true;
bcbc889b 1975 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1976 case TRANS_DDI_MODE_SELECT_DP_MST:
1977 /* if the transcoder is in MST state then
1978 * connector isn't connected */
1979 return false;
bcbc889b
PZ		 1980
1981 case TRANS_DDI_MODE_SELECT_FDI:
1982 return (type == DRM_MODE_CONNECTOR_VGA);
1983
1984 default:
1985 return false;
1986 }
1987}
1988
85234cdc
DV		 1989bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1990 enum pipe *pipe)
1991{
1992 struct drm_device *dev = encoder->base.dev;
1993 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1994 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1995 enum intel_display_power_domain power_domain;
85234cdc
DV		 1996 u32 tmp;
1997 int i;
1998
6d129bea 1999 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2000 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2001 return false;
2002
fe43d3f5 2003 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 2004
2005 if (!(tmp & DDI_BUF_CTL_ENABLE))
2006 return false;
2007
ad80a810
PZ		 2008 if (port == PORT_A) {
2009 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2010
ad80a810
PZ		 2011 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2012 case TRANS_DDI_EDP_INPUT_A_ON:
2013 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2014 *pipe = PIPE_A;
2015 break;
2016 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2017 *pipe = PIPE_B;
2018 break;
2019 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2020 *pipe = PIPE_C;
2021 break;
2022 }
2023
2024 return true;
2025 } else {
2026 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2027 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2028
2029 if ((tmp & TRANS_DDI_PORT_MASK)
2030 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2031 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2032 return false;
2033
ad80a810
PZ		 2034 *pipe = i;
2035 return true;
2036 }
85234cdc
DV		 2037 }
2038 }
2039
84f44ce7 2040 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2041
22f9fe50 2042 return false;
85234cdc
DV		 2043}
2044
fc914639
PZ		 2045void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2046{
2047 struct drm_crtc *crtc = &intel_crtc->base;
7d4aefd0
SS		 2048 struct drm_device *dev = crtc->dev;
2049 struct drm_i915_private *dev_priv = dev->dev_private;
fc914639
PZ		 2050 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2051 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2052 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2053
bb523fc0
PZ		 2054 if (cpu_transcoder != TRANSCODER_EDP)
2055 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2056 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2057}
2058
2059void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2060{
2061 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2062 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2063
bb523fc0
PZ		 2064 if (cpu_transcoder != TRANSCODER_EDP)
2065 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2066 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2067}
2068
f8896f5d
DW		 2069static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2070 enum port port, int type)
2071{
2072 struct drm_i915_private *dev_priv = dev->dev_private;
2073 const struct ddi_buf_trans *ddi_translations;
2074 uint8_t iboost;
75067dde 2075 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2076 int n_entries;
2077 u32 reg;
2078
75067dde
AK		 2079 /* VBT may override standard boost values */
2080 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2081 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2082
f8896f5d 2083 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2084 if (dp_iboost) {
2085 iboost = dp_iboost;
2086 } else {
2087 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2088 iboost = ddi_translations[port].i_boost;
2089 }
f8896f5d 2090 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2091 if (dp_iboost) {
2092 iboost = dp_iboost;
2093 } else {
2094 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2095 iboost = ddi_translations[port].i_boost;
2096 }
f8896f5d 2097 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2098 if (hdmi_iboost) {
2099 iboost = hdmi_iboost;
2100 } else {
2101 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2102 iboost = ddi_translations[port].i_boost;
2103 }
f8896f5d
DW		 2104 } else {
2105 return;
2106 }
2107
2108 /* Make sure that the requested I_boost is valid */
2109 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2110 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2111 return;
2112 }
2113
2114 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2115 reg &= ~BALANCE_LEG_MASK(port);
2116 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2117
2118 if (iboost)
2119 reg |= iboost << BALANCE_LEG_SHIFT(port);
2120 else
2121 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2122
2123 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2124}
2125
2126static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2127 enum port port, int type)
96fb9f9b
VK		 2128{
2129 struct drm_i915_private *dev_priv = dev->dev_private;
2130 const struct bxt_ddi_buf_trans *ddi_translations;
2131 u32 n_entries, i;
2132 uint32_t val;
2133
d9d7000d
SJ		 2134 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2135 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2136 ddi_translations = bxt_ddi_translations_edp;
2137 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2138 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 2139 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2140 ddi_translations = bxt_ddi_translations_dp;
2141 } else if (type == INTEL_OUTPUT_HDMI) {
2142 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2143 ddi_translations = bxt_ddi_translations_hdmi;
2144 } else {
2145 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2146 type);
2147 return;
2148 }
2149
2150 /* Check if default value has to be used */
2151 if (level >= n_entries ||
2152 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2153 for (i = 0; i < n_entries; i++) {
2154 if (ddi_translations[i].default_index) {
2155 level = i;
2156 break;
2157 }
2158 }
2159 }
2160
2161 /*
2162 * While we write to the group register to program all lanes at once we
2163 * can read only lane registers and we pick lanes 0/1 for that.
2164 */
2165 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2166 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2167 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2168
2169 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2170 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2171 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2172 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2173 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2174
2175 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
9c58a049 2176 val &= ~SCALE_DCOMP_METHOD;
96fb9f9b 2177 if (ddi_translations[level].enable)
9c58a049
SJ		 2178 val |= SCALE_DCOMP_METHOD;
2179
2180 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2181 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2182
96fb9f9b
VK		 2183 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2184
2185 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2186 val &= ~DE_EMPHASIS;
2187 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2188 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2189
2190 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2191 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2192 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2193}
2194
f8896f5d
DW		 2195static uint32_t translate_signal_level(int signal_levels)
2196{
2197 uint32_t level;
2198
2199 switch (signal_levels) {
2200 default:
2201 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2202 signal_levels);
2203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2204 level = 0;
2205 break;
2206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2207 level = 1;
2208 break;
2209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2210 level = 2;
2211 break;
2212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2213 level = 3;
2214 break;
2215
2216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2217 level = 4;
2218 break;
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2220 level = 5;
2221 break;
2222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2223 level = 6;
2224 break;
2225
2226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2227 level = 7;
2228 break;
2229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2230 level = 8;
2231 break;
2232
2233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2234 level = 9;
2235 break;
2236 }
2237
2238 return level;
2239}
2240
2241uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2242{
2243 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2244 struct drm_device *dev = dport->base.base.dev;
2245 struct intel_encoder *encoder = &dport->base;
2246 uint8_t train_set = intel_dp->train_set[0];
2247 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2248 DP_TRAIN_PRE_EMPHASIS_MASK);
2249 enum port port = dport->port;
2250 uint32_t level;
2251
2252 level = translate_signal_level(signal_levels);
2253
ef11bdb3 2254 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
f8896f5d
DW		 2255 skl_ddi_set_iboost(dev, level, port, encoder->type);
2256 else if (IS_BROXTON(dev))
2257 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2258
2259 return DDI_BUF_TRANS_SELECT(level);
2260}
2261
00c09d70 2262static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 2263{
c19b0669 2264 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2265 struct drm_device *dev = encoder->dev;
2266 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 2267 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 2268 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2269 int type = intel_encoder->type;
96fb9f9b 2270 int hdmi_level;
6441ab5f 2271
82a4d9c0
PZ		 2272 if (type == INTEL_OUTPUT_EDP) {
2273 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 2274 intel_edp_panel_on(intel_dp);
82a4d9c0 2275 }
6441ab5f 2276
ef11bdb3 2277 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
6e3c9717 2278 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 2279 uint32_t val;
2280
5416d871
DL		 2281 /*
2282 * DPLL0 is used for eDP and is the only "private" DPLL (as
2283 * opposed to shared) on SKL
2284 */
2285 if (type == INTEL_OUTPUT_EDP) {
2286 WARN_ON(dpll != SKL_DPLL0);
2287
2288 val = I915_READ(DPLL_CTRL1);
2289
2290 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2291 DPLL_CTRL1_SSC(dpll) |
71cd8423 2292 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 2293 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2294
2295 I915_WRITE(DPLL_CTRL1, val);
2296 POSTING_READ(DPLL_CTRL1);
2297 }
2298
2299 /* DDI -> PLL mapping */
efa80add
S		 2300 val = I915_READ(DPLL_CTRL2);
2301
2302 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2303 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2304 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2305 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2306
2307 I915_WRITE(DPLL_CTRL2, val);
5416d871 2308
1ab23380 2309 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 2310 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2311 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 2312 }
c19b0669 2313
82a4d9c0 2314 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2315 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2316
901c2daf
VS		 2317 intel_dp_set_link_params(intel_dp, crtc->config);
2318
44905a27 2319 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2320
2321 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2322 intel_dp_start_link_train(intel_dp);
23f08d83 2323 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2324 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2325 } else if (type == INTEL_OUTPUT_HDMI) {
2326 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2327
96fb9f9b
VK		 2328 if (IS_BROXTON(dev)) {
2329 hdmi_level = dev_priv->vbt.
2330 ddi_port_info[port].hdmi_level_shift;
2331 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2332 INTEL_OUTPUT_HDMI);
2333 }
30cf6db8 2334 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2335 crtc->config->has_hdmi_sink,
2336 &crtc->config->base.adjusted_mode);
c19b0669 2337 }
6441ab5f
PZ		 2338}
2339
00c09d70 2340static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2341{
2342 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2343 struct drm_device *dev = encoder->dev;
2344 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2345 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2346 int type = intel_encoder->type;
2886e93f 2347 uint32_t val;
a836bdf9 2348 bool wait = false;
2886e93f
PZ		 2349
2350 val = I915_READ(DDI_BUF_CTL(port));
2351 if (val & DDI_BUF_CTL_ENABLE) {
2352 val &= ~DDI_BUF_CTL_ENABLE;
2353 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2354 wait = true;
2886e93f 2355 }
6441ab5f 2356
a836bdf9
PZ		 2357 val = I915_READ(DP_TP_CTL(port));
2358 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2359 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2360 I915_WRITE(DP_TP_CTL(port), val);
2361
2362 if (wait)
2363 intel_wait_ddi_buf_idle(dev_priv, port);
2364
76bb80ed 2365 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2366 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2367 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2368 intel_edp_panel_vdd_on(intel_dp);
4be73780 2369 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2370 }
2371
ef11bdb3 2372 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
efa80add
S		 2373 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2374 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2375 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2376 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2377}
2378
00c09d70 2379static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2380{
6547fef8 2381 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2382 struct drm_crtc *crtc = encoder->crtc;
2383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2384 struct drm_device *dev = encoder->dev;
72662e10 2385 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2386 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2387 int type = intel_encoder->type;
72662e10 2388
6547fef8 2389 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2390 struct intel_digital_port *intel_dig_port =
2391 enc_to_dig_port(encoder);
2392
6547fef8
PZ		 2393 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2394 * are ignored so nothing special needs to be done besides
2395 * enabling the port.
2396 */
876a8cdf 2397 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2398 intel_dig_port->saved_port_bits |
2399 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2400 } else if (type == INTEL_OUTPUT_EDP) {
2401 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2402
23f08d83 2403 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2404 intel_dp_stop_link_train(intel_dp);
2405
4be73780 2406 intel_edp_backlight_on(intel_dp);
0bc12bcb 2407 intel_psr_enable(intel_dp);
c395578e 2408 intel_edp_drrs_enable(intel_dp);
6547fef8 2409 }
7b9f35a6 2410
6e3c9717 2411 if (intel_crtc->config->has_audio) {
d45a0bf5 2412 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2413 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2414 }
5ab432ef
DV		 2415}
2416
00c09d70 2417static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2418{
d6c50ff8 2419 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2420 struct drm_crtc *crtc = encoder->crtc;
2421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2422 int type = intel_encoder->type;
7b9f35a6
WX		 2423 struct drm_device *dev = encoder->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2425
6e3c9717 2426 if (intel_crtc->config->has_audio) {
69bfe1a9 2427 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2428 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2429 }
2831d842 2430
d6c50ff8
PZ		 2431 if (type == INTEL_OUTPUT_EDP) {
2432 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2433
c395578e 2434 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2435 intel_psr_disable(intel_dp);
4be73780 2436 intel_edp_backlight_off(intel_dp);
d6c50ff8 2437 }
72662e10 2438}
79f689aa 2439
e0b01be4
DV		 2440static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2441 struct intel_shared_dpll *pll)
2442{
3e369b76 2443 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2444 POSTING_READ(WRPLL_CTL(pll->id));
2445 udelay(20);
2446}
2447
12030431
DV		 2448static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2449 struct intel_shared_dpll *pll)
2450{
2451 uint32_t val;
2452
2453 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2454 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2455 POSTING_READ(WRPLL_CTL(pll->id));
2456}
2457
d452c5b6
DV		 2458static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2459 struct intel_shared_dpll *pll,
2460 struct intel_dpll_hw_state *hw_state)
2461{
2462 uint32_t val;
2463
f458ebbc 2464 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2465 return false;
2466
2467 val = I915_READ(WRPLL_CTL(pll->id));
2468 hw_state->wrpll = val;
2469
2470 return val & WRPLL_PLL_ENABLE;
2471}
2472
ca1381b5 2473static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2474 "WRPLL 1",
2475 "WRPLL 2",
2476};
2477
143b307c 2478static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2479{
9cd86933
DV		 2480 int i;
2481
716c2e55 2482 dev_priv->num_shared_dpll = 2;
9cd86933 2483
716c2e55 2484 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2485 dev_priv->shared_dplls[i].id = i;
2486 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2487 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2488 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2489 dev_priv->shared_dplls[i].get_hw_state =
2490 hsw_ddi_pll_get_hw_state;
9cd86933 2491 }
143b307c
DL		 2492}
2493
d1a2dc78
S		 2494static const char * const skl_ddi_pll_names[] = {
2495 "DPLL 1",
2496 "DPLL 2",
2497 "DPLL 3",
2498};
2499
2500struct skl_dpll_regs {
2501 u32 ctl, cfgcr1, cfgcr2;
2502};
2503
2504/* this array is indexed by the *shared* pll id */
2505static const struct skl_dpll_regs skl_dpll_regs[3] = {
2506 {
2507 /* DPLL 1 */
2508 .ctl = LCPLL2_CTL,
923c1241
VS		 2509 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2510 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
d1a2dc78
S		 2511 },
2512 {
2513 /* DPLL 2 */
01403de3 2514 .ctl = WRPLL_CTL(0),
923c1241
VS		 2515 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2516 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
d1a2dc78
S		 2517 },
2518 {
2519 /* DPLL 3 */
01403de3 2520 .ctl = WRPLL_CTL(1),
923c1241
VS		 2521 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2522 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
d1a2dc78
S		 2523 },
2524};
2525
2526static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2527 struct intel_shared_dpll *pll)
2528{
2529 uint32_t val;
2530 unsigned int dpll;
2531 const struct skl_dpll_regs *regs = skl_dpll_regs;
2532
2533 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2534 dpll = pll->id + 1;
2535
2536 val = I915_READ(DPLL_CTRL1);
2537
2538 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2539 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2540 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2541
2542 I915_WRITE(DPLL_CTRL1, val);
2543 POSTING_READ(DPLL_CTRL1);
2544
2545 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2546 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2547 POSTING_READ(regs[pll->id].cfgcr1);
2548 POSTING_READ(regs[pll->id].cfgcr2);
2549
2550 /* the enable bit is always bit 31 */
2551 I915_WRITE(regs[pll->id].ctl,
2552 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2553
2554 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2555 DRM_ERROR("DPLL %d not locked\n", dpll);
2556}
2557
2558static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2559 struct intel_shared_dpll *pll)
2560{
2561 const struct skl_dpll_regs *regs = skl_dpll_regs;
2562
2563 /* the enable bit is always bit 31 */
2564 I915_WRITE(regs[pll->id].ctl,
2565 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2566 POSTING_READ(regs[pll->id].ctl);
2567}
2568
2569static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2570 struct intel_shared_dpll *pll,
2571 struct intel_dpll_hw_state *hw_state)
2572{
2573 uint32_t val;
2574 unsigned int dpll;
2575 const struct skl_dpll_regs *regs = skl_dpll_regs;
2576
2577 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2578 return false;
2579
2580 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2581 dpll = pll->id + 1;
2582
2583 val = I915_READ(regs[pll->id].ctl);
2584 if (!(val & LCPLL_PLL_ENABLE))
2585 return false;
2586
2587 val = I915_READ(DPLL_CTRL1);
2588 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2589
2590 /* avoid reading back stale values if HDMI mode is not enabled */
2591 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2592 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2593 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2594 }
2595
2596 return true;
2597}
2598
2599static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2600{
2601 int i;
2602
2603 dev_priv->num_shared_dpll = 3;
2604
2605 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2606 dev_priv->shared_dplls[i].id = i;
2607 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2608 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2609 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2610 dev_priv->shared_dplls[i].get_hw_state =
2611 skl_ddi_pll_get_hw_state;
2612 }
2613}
2614
5c6706e5
VK		 2615static void broxton_phy_init(struct drm_i915_private *dev_priv,
2616 enum dpio_phy phy)
2617{
2618 enum port port;
2619 uint32_t val;
2620
2621 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2622 val |= GT_DISPLAY_POWER_ON(phy);
2623 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2624
2625 /* Considering 10ms timeout until BSpec is updated */
2626 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2627 DRM_ERROR("timeout during PHY%d power on\n", phy);
2628
2629 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2630 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2631 int lane;
2632
2633 for (lane = 0; lane < 4; lane++) {
2634 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2635 /*
2636 * Note that on CHV this flag is called UPAR, but has
2637 * the same function.
2638 */
2639 val &= ~LATENCY_OPTIM;
2640 if (lane != 1)
2641 val |= LATENCY_OPTIM;
2642
2643 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2644 }
2645 }
2646
2647 /* Program PLL Rcomp code offset */
2648 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2649 val &= ~IREF0RC_OFFSET_MASK;
2650 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2651 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2652
2653 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2654 val &= ~IREF1RC_OFFSET_MASK;
2655 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2656 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2657
2658 /* Program power gating */
2659 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2660 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2661 SUS_CLK_CONFIG;
2662 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2663
2664 if (phy == DPIO_PHY0) {
2665 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2666 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2667 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2668 }
2669
2670 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2671 val &= ~OCL2_LDOFUSE_PWR_DIS;
2672 /*
2673 * On PHY1 disable power on the second channel, since no port is
2674 * connected there. On PHY0 both channels have a port, so leave it
2675 * enabled.
2676 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2677 * power down the second channel on PHY0 as well.
2678 */
2679 if (phy == DPIO_PHY1)
2680 val |= OCL2_LDOFUSE_PWR_DIS;
2681 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2682
2683 if (phy == DPIO_PHY0) {
2684 uint32_t grc_code;
2685 /*
2686 * PHY0 isn't connected to an RCOMP resistor so copy over
2687 * the corresponding calibrated value from PHY1, and disable
2688 * the automatic calibration on PHY0.
2689 */
2690 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2691 10))
2692 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2693
2694 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2695 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2696 grc_code = val << GRC_CODE_FAST_SHIFT |
2697 val << GRC_CODE_SLOW_SHIFT |
2698 val;
2699 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2700
2701 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2702 val |= GRC_DIS | GRC_RDY_OVRD;
2703 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2704 }
2705
2706 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2707 val |= COMMON_RESET_DIS;
2708 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2709}
2710
2711void broxton_ddi_phy_init(struct drm_device *dev)
2712{
2713 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2714 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2715 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2716}
2717
2718static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2719 enum dpio_phy phy)
2720{
2721 uint32_t val;
2722
2723 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2724 val &= ~COMMON_RESET_DIS;
2725 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2726}
2727
2728void broxton_ddi_phy_uninit(struct drm_device *dev)
2729{
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731
2732 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2733 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2734
2735 /* FIXME: do this in broxton_phy_uninit per phy */
2736 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2737}
2738
dfb82408
S		 2739static const char * const bxt_ddi_pll_names[] = {
2740 "PORT PLL A",
2741 "PORT PLL B",
2742 "PORT PLL C",
2743};
2744
2745static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2746 struct intel_shared_dpll *pll)
2747{
2748 uint32_t temp;
2749 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2750
2751 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2752 temp &= ~PORT_PLL_REF_SEL;
2753 /* Non-SSC reference */
2754 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2755
2756 /* Disable 10 bit clock */
2757 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2758 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2759 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2760
2761 /* Write P1 & P2 */
2762 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2763 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2764 temp |= pll->config.hw_state.ebb0;
2765 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2766
2767 /* Write M2 integer */
2768 temp = I915_READ(BXT_PORT_PLL(port, 0));
2769 temp &= ~PORT_PLL_M2_MASK;
2770 temp |= pll->config.hw_state.pll0;
2771 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2772
2773 /* Write N */
2774 temp = I915_READ(BXT_PORT_PLL(port, 1));
2775 temp &= ~PORT_PLL_N_MASK;
2776 temp |= pll->config.hw_state.pll1;
2777 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2778
2779 /* Write M2 fraction */
2780 temp = I915_READ(BXT_PORT_PLL(port, 2));
2781 temp &= ~PORT_PLL_M2_FRAC_MASK;
2782 temp |= pll->config.hw_state.pll2;
2783 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2784
2785 /* Write M2 fraction enable */
2786 temp = I915_READ(BXT_PORT_PLL(port, 3));
2787 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2788 temp |= pll->config.hw_state.pll3;
2789 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2790
2791 /* Write coeff */
2792 temp = I915_READ(BXT_PORT_PLL(port, 6));
2793 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2794 temp &= ~PORT_PLL_INT_COEFF_MASK;
2795 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2796 temp |= pll->config.hw_state.pll6;
2797 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2798
2799 /* Write calibration val */
2800 temp = I915_READ(BXT_PORT_PLL(port, 8));
2801 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2802 temp |= pll->config.hw_state.pll8;
2803 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2804
b6dc71f3
VK		 2805 temp = I915_READ(BXT_PORT_PLL(port, 9));
2806 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2807 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2808 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2809
2810 temp = I915_READ(BXT_PORT_PLL(port, 10));
2811 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2812 temp &= ~PORT_PLL_DCO_AMP_MASK;
2813 temp |= pll->config.hw_state.pll10;
2814 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2815
2816 /* Recalibrate with new settings */
2817 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2818 temp |= PORT_PLL_RECALIBRATE;
2819 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2820 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2821 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2822 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2823
2824 /* Enable PLL */
2825 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2826 temp |= PORT_PLL_ENABLE;
2827 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2828 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2829
2830 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2831 PORT_PLL_LOCK), 200))
2832 DRM_ERROR("PLL %d not locked\n", port);
2833
2834 /*
2835 * While we write to the group register to program all lanes at once we
2836 * can read only lane registers and we pick lanes 0/1 for that.
2837 */
2838 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2839 temp &= ~LANE_STAGGER_MASK;
2840 temp &= ~LANESTAGGER_STRAP_OVRD;
2841 temp |= pll->config.hw_state.pcsdw12;
2842 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2843}
2844
2845static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2846 struct intel_shared_dpll *pll)
2847{
2848 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2849 uint32_t temp;
2850
2851 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2852 temp &= ~PORT_PLL_ENABLE;
2853 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2854 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2855}
2856
2857static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2858 struct intel_shared_dpll *pll,
2859 struct intel_dpll_hw_state *hw_state)
2860{
2861 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2862 uint32_t val;
2863
2864 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2865 return false;
2866
2867 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2868 if (!(val & PORT_PLL_ENABLE))
2869 return false;
2870
2871 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2872 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2873
05712c15
ID		 2874 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2875 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2876
dfb82408 2877 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2878 hw_state->pll0 &= PORT_PLL_M2_MASK;
2879
dfb82408 2880 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2881 hw_state->pll1 &= PORT_PLL_N_MASK;
2882
dfb82408 2883 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2884 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2885
dfb82408 2886 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2887 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2888
dfb82408 2889 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2890 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2891 PORT_PLL_INT_COEFF_MASK |
2892 PORT_PLL_GAIN_CTL_MASK;
2893
dfb82408 2894 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2895 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2896
05712c15
ID		 2897 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2898 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2899
b6dc71f3 2900 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2901 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2902 PORT_PLL_DCO_AMP_MASK;
2903
dfb82408
S		 2904 /*
2905 * While we write to the group register to program all lanes at once we
2906 * can read only lane registers. We configure all lanes the same way, so
2907 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2908 */
2909 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
b5dada82 2910 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
dfb82408
S		 2911 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2912 hw_state->pcsdw12,
2913 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2914 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408
S		 2915
2916 return true;
2917}
2918
2919static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2920{
2921 int i;
2922
2923 dev_priv->num_shared_dpll = 3;
2924
2925 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2926 dev_priv->shared_dplls[i].id = i;
2927 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2928 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2929 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2930 dev_priv->shared_dplls[i].get_hw_state =
2931 bxt_ddi_pll_get_hw_state;
2932 }
2933}
2934
143b307c
DL		 2935void intel_ddi_pll_init(struct drm_device *dev)
2936{
2937 struct drm_i915_private *dev_priv = dev->dev_private;
2938 uint32_t val = I915_READ(LCPLL_CTL);
2939
ef11bdb3 2940 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
d1a2dc78 2941 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2942 else if (IS_BROXTON(dev))
2943 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2944 else
2945 hsw_shared_dplls_init(dev_priv);
79f689aa 2946
ef11bdb3 2947 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
d9062ae5
DL		 2948 int cdclk_freq;
2949
2950 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2951 dev_priv->skl_boot_cdclk = cdclk_freq;
c73666f3
SK		 2952 if (skl_sanitize_cdclk(dev_priv))
2953 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
5d96d8af
DL		 2954 else
2955 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2956 } else if (IS_BROXTON(dev)) {
2957 broxton_init_cdclk(dev);
5c6706e5 2958 broxton_ddi_phy_init(dev);
121643c2
S		 2959 } else {
2960 /*
2961 * The LCPLL register should be turned on by the BIOS. For now
2962 * let's just check its state and print errors in case
2963 * something is wrong. Don't even try to turn it on.
2964 */
2965
2966 if (val & LCPLL_CD_SOURCE_FCLK)
2967 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2968
121643c2
S		 2969 if (val & LCPLL_PLL_DISABLE)
2970 DRM_ERROR("LCPLL is disabled\n");
2971 }
79f689aa 2972}
c19b0669 2973
ad64217b 2974void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2975{
ad64217b
ACO		 2976 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2977 struct drm_i915_private *dev_priv =
2978 to_i915(intel_dig_port->base.base.dev);
174edf1f 2979 enum port port = intel_dig_port->port;
c19b0669 2980 uint32_t val;
f3e227df 2981 bool wait = false;
c19b0669
PZ		 2982
2983 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2984 val = I915_READ(DDI_BUF_CTL(port));
2985 if (val & DDI_BUF_CTL_ENABLE) {
2986 val &= ~DDI_BUF_CTL_ENABLE;
2987 I915_WRITE(DDI_BUF_CTL(port), val);
2988 wait = true;
2989 }
2990
2991 val = I915_READ(DP_TP_CTL(port));
2992 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2993 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2994 I915_WRITE(DP_TP_CTL(port), val);
2995 POSTING_READ(DP_TP_CTL(port));
2996
2997 if (wait)
2998 intel_wait_ddi_buf_idle(dev_priv, port);
2999 }
3000
0e32b39c 3001 val = DP_TP_CTL_ENABLE |
c19b0669 3002 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 3003 if (intel_dp->is_mst)
3004 val |= DP_TP_CTL_MODE_MST;
3005 else {
3006 val |= DP_TP_CTL_MODE_SST;
3007 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3008 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3009 }
c19b0669
PZ		 3010 I915_WRITE(DP_TP_CTL(port), val);
3011 POSTING_READ(DP_TP_CTL(port));
3012
3013 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3014 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3015 POSTING_READ(DDI_BUF_CTL(port));
3016
3017 udelay(600);
3018}
00c09d70 3019
1ad960f2
PZ		 3020void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3021{
3022 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3023 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3024 uint32_t val;
3025
3026 intel_ddi_post_disable(intel_encoder);
3027
eede3b53 3028 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3029 val &= ~FDI_RX_ENABLE;
eede3b53 3030 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 3031
eede3b53 3032 val = I915_READ(FDI_RX_MISC(PIPE_A));
1ad960f2
PZ		 3033 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3034 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53 3035 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1ad960f2 3036
eede3b53 3037 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3038 val &= ~FDI_PCDCLK;
eede3b53 3039 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 3040
eede3b53 3041 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3042 val &= ~FDI_RX_PLL_ENABLE;
eede3b53 3043 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2
PZ		 3044}
3045
6801c18c 3046void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3047 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3048{
3049 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3050 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3051 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3052 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3053 u32 temp, flags = 0;
3054
3055 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3056 if (temp & TRANS_DDI_PHSYNC)
3057 flags |= DRM_MODE_FLAG_PHSYNC;
3058 else
3059 flags |= DRM_MODE_FLAG_NHSYNC;
3060 if (temp & TRANS_DDI_PVSYNC)
3061 flags |= DRM_MODE_FLAG_PVSYNC;
3062 else
3063 flags |= DRM_MODE_FLAG_NVSYNC;
3064
2d112de7 3065 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3066
3067 switch (temp & TRANS_DDI_BPC_MASK) {
3068 case TRANS_DDI_BPC_6:
3069 pipe_config->pipe_bpp = 18;
3070 break;
3071 case TRANS_DDI_BPC_8:
3072 pipe_config->pipe_bpp = 24;
3073 break;
3074 case TRANS_DDI_BPC_10:
3075 pipe_config->pipe_bpp = 30;
3076 break;
3077 case TRANS_DDI_BPC_12:
3078 pipe_config->pipe_bpp = 36;
3079 break;
3080 default:
3081 break;
3082 }
eb14cb74
VS		 3083
3084 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3085 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3086 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3087 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3088
3089 if (intel_hdmi->infoframe_enabled(&encoder->base))
3090 pipe_config->has_infoframe = true;
cbc572a9 3091 break;
eb14cb74
VS		 3092 case TRANS_DDI_MODE_SELECT_DVI:
3093 case TRANS_DDI_MODE_SELECT_FDI:
3094 break;
3095 case TRANS_DDI_MODE_SELECT_DP_SST:
3096 case TRANS_DDI_MODE_SELECT_DP_MST:
3097 pipe_config->has_dp_encoder = true;
90a6b7b0
VS		 3098 pipe_config->lane_count =
3099 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3100 intel_dp_get_m_n(intel_crtc, pipe_config);
3101 break;
3102 default:
3103 break;
3104 }
10214420 3105
f458ebbc 3106 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 3107 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 3108 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 3109 pipe_config->has_audio = true;
3110 }
9ed109a7 3111
10214420
DV		 3112 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3113 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3114 /*
3115 * This is a big fat ugly hack.
3116 *
3117 * Some machines in UEFI boot mode provide us a VBT that has 18
3118 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3119 * unknown we fail to light up. Yet the same BIOS boots up with
3120 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3121 * max, not what it tells us to use.
3122 *
3123 * Note: This will still be broken if the eDP panel is not lit
3124 * up by the BIOS, and thus we can't get the mode at module
3125 * load.
3126 */
3127 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3128 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3129 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3130 }
11578553 3131
22606a18 3132 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3133}
3134
00c09d70
PZ		 3135static void intel_ddi_destroy(struct drm_encoder *encoder)
3136{
3137 /* HDMI has nothing special to destroy, so we can go with this. */
3138 intel_dp_encoder_destroy(encoder);
3139}
3140
5bfe2ac0 3141static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3142 struct intel_crtc_state *pipe_config)
00c09d70 3143{
5bfe2ac0 3144 int type = encoder->type;
eccb140b 3145 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3146
5bfe2ac0 3147 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3148
eccb140b
DV		 3149 if (port == PORT_A)
3150 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3151
00c09d70 3152 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3153 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3154 else
5bfe2ac0 3155 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3156}
3157
3158static const struct drm_encoder_funcs intel_ddi_funcs = {
3159 .destroy = intel_ddi_destroy,
3160};
3161
4a28ae58
PZ		 3162static struct intel_connector *
3163intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3164{
3165 struct intel_connector *connector;
3166 enum port port = intel_dig_port->port;
3167
9bdbd0b9 3168 connector = intel_connector_alloc();
4a28ae58
PZ		 3169 if (!connector)
3170 return NULL;
3171
3172 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3173 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3174 kfree(connector);
3175 return NULL;
3176 }
3177
3178 return connector;
3179}
3180
3181static struct intel_connector *
3182intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3183{
3184 struct intel_connector *connector;
3185 enum port port = intel_dig_port->port;
3186
9bdbd0b9 3187 connector = intel_connector_alloc();
4a28ae58
PZ		 3188 if (!connector)
3189 return NULL;
3190
3191 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3192 intel_hdmi_init_connector(intel_dig_port, connector);
3193
3194 return connector;
3195}
3196
00c09d70
PZ		 3197void intel_ddi_init(struct drm_device *dev, enum port port)
3198{
876a8cdf 3199 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3200 struct intel_digital_port *intel_dig_port;
3201 struct intel_encoder *intel_encoder;
3202 struct drm_encoder *encoder;
311a2094
PZ		 3203 bool init_hdmi, init_dp;
3204
3205 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3206 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3207 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3208 if (!init_dp && !init_hdmi) {
500ea70d 3209 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3210 port_name(port));
500ea70d 3211 return;
311a2094 3212 }
00c09d70 3213
b14c5679 3214 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3215 if (!intel_dig_port)
3216 return;
3217
00c09d70
PZ		 3218 intel_encoder = &intel_dig_port->base;
3219 encoder = &intel_encoder->base;
3220
3221 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3222 DRM_MODE_ENCODER_TMDS);
00c09d70 3223
5bfe2ac0 3224 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3225 intel_encoder->enable = intel_enable_ddi;
3226 intel_encoder->pre_enable = intel_ddi_pre_enable;
3227 intel_encoder->disable = intel_disable_ddi;
3228 intel_encoder->post_disable = intel_ddi_post_disable;
3229 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3230 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3231
3232 intel_dig_port->port = port;
bcf53de4
SM		 3233 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3234 (DDI_BUF_PORT_REVERSAL |
3235 DDI_A_4_LANES);
00c09d70 3236
6c566dc9
MR		 3237 /*
3238 * Bspec says that DDI_A_4_LANES is the only supported configuration
3239 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
3240 * wasn't lit up at boot. Force this bit on in our internal
3241 * configuration so that we use the proper lane count for our
3242 * calculations.
3243 */
3244 if (IS_BROXTON(dev) && port == PORT_A) {
3245 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
3246 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3247 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
3248 }
3249 }
3250
00c09d70 3251 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3252 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3253 intel_encoder->cloneable = 0;
00c09d70 3254
f68d697e
CW		 3255 if (init_dp) {
3256 if (!intel_ddi_init_dp_connector(intel_dig_port))
3257 goto err;
13cf5504 3258
f68d697e 3259 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 3260 /*
3261 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3262 * interrupts to check the external panel connection.
3263 */
e87a005d 3264 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
cf1d5883
SJ		 3265 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3266 else
3267 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3268 }
21a8e6a4 3269
311a2094
PZ		 3270 /* In theory we don't need the encoder->type check, but leave it just in
3271 * case we have some really bad VBTs... */
f68d697e
CW		 3272 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3273 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3274 goto err;
21a8e6a4 3275 }
f68d697e
CW		 3276
3277 return;
3278
3279err:
3280 drm_encoder_cleanup(encoder);
3281 kfree(intel_dig_port);
00c09d70 3282}
Linux 6.x block layer and io_uring tree(s)