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drm/i915/lvds: Remove ->mode_set callback
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
31/* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45244b87
ED		 45};
46
47static const u32 hsw_ddi_translations_fdi[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */
49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000,
52 0x00FFFFFF, 0x000F000A,
53 0x00D75FFF, 0x00160004,
54 0x00C30FFF, 0x001E0000,
55 0x00FFFFFF, 0x00060006,
56 0x00D75FFF, 0x001E0000,
6acab15a
PZ		 57};
58
59static const u32 hsw_ddi_translations_hdmi[] = {
60 /* Idx NT mV diff T mV diff db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
45244b87
ED		 73};
74
300644c7 75static const u32 bdw_ddi_translations_edp[] = {
e1b22732 76 0x00FFFFFF, 0x00000012, /* eDP parameters */
300644c7
PZ		 77 0x00EBAFFF, 0x00020011,
78 0x00C71FFF, 0x0006000F,
79 0x00FFFFFF, 0x00020011,
80 0x00DB6FFF, 0x0005000F,
81 0x00BEEFFF, 0x000A000C,
82 0x00FFFFFF, 0x0005000F,
83 0x00DB6FFF, 0x000A000C,
84 0x00FFFFFF, 0x000A000C,
85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
86};
87
e58623cb
AR		 88static const u32 bdw_ddi_translations_dp[] = {
89 0x00FFFFFF, 0x0007000E, /* DP parameters */
90 0x00D75FFF, 0x000E000A,
91 0x00BEFFFF, 0x00140006,
92 0x00FFFFFF, 0x000E000A,
93 0x00D75FFF, 0x00180004,
94 0x80CB2FFF, 0x001B0002,
95 0x00F7DFFF, 0x00180004,
96 0x80D75FFF, 0x001B0002,
97 0x80FFFFFF, 0x001B0002,
98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
99};
100
101static const u32 bdw_ddi_translations_fdi[] = {
102 0x00FFFFFF, 0x0001000E, /* FDI parameters */
103 0x00D75FFF, 0x0004000A,
104 0x00C30FFF, 0x00070006,
105 0x00AAAFFF, 0x000C0000,
106 0x00FFFFFF, 0x0004000A,
107 0x00D75FFF, 0x00090004,
108 0x00C30FFF, 0x000C0000,
109 0x00FFFFFF, 0x00070006,
110 0x00D75FFF, 0x000C0000,
111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
112};
113
20f4dbe4 114enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
fc914639 115{
0bdee30e 116 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 117 int type = intel_encoder->type;
118
174edf1f 119 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 120 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 121 struct intel_digital_port *intel_dig_port =
122 enc_to_dig_port(encoder);
123 return intel_dig_port->port;
0bdee30e 124
fc914639
PZ		 125 } else if (type == INTEL_OUTPUT_ANALOG) {
126 return PORT_E;
0bdee30e 127
fc914639
PZ		 128 } else {
129 DRM_ERROR("Invalid DDI encoder type %d\n", type);
130 BUG();
131 }
132}
133
e58623cb
AR		 134/*
135 * Starting with Haswell, DDI port buffers must be programmed with correct
136 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 137 * but the HDMI/DVI fields are shared among those. So we program the DDI
138 * in either FDI or DP modes only, as HDMI connections will work with both
139 * of those
140 */
ad8d270c 141static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
45244b87
ED		 142{
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 u32 reg;
145 int i;
6acab15a 146 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
e58623cb
AR		 147 const u32 *ddi_translations_fdi;
148 const u32 *ddi_translations_dp;
300644c7 149 const u32 *ddi_translations_edp;
e58623cb
AR		 150 const u32 *ddi_translations;
151
152 if (IS_BROADWELL(dev)) {
153 ddi_translations_fdi = bdw_ddi_translations_fdi;
154 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 155 ddi_translations_edp = bdw_ddi_translations_edp;
e58623cb
AR		 156 } else if (IS_HASWELL(dev)) {
157 ddi_translations_fdi = hsw_ddi_translations_fdi;
158 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 159 ddi_translations_edp = hsw_ddi_translations_dp;
e58623cb
AR		 160 } else {
161 WARN(1, "ddi translation table missing\n");
300644c7 162 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 163 ddi_translations_fdi = bdw_ddi_translations_fdi;
164 ddi_translations_dp = bdw_ddi_translations_dp;
165 }
166
300644c7
PZ		 167 switch (port) {
168 case PORT_A:
169 ddi_translations = ddi_translations_edp;
170 break;
171 case PORT_B:
172 case PORT_C:
300644c7
PZ		 173 ddi_translations = ddi_translations_dp;
174 break;
77d8d009 175 case PORT_D:
5d8a7752 176 if (intel_dp_is_edp(dev, PORT_D))
77d8d009
PZ		 177 ddi_translations = ddi_translations_edp;
178 else
179 ddi_translations = ddi_translations_dp;
180 break;
300644c7
PZ		 181 case PORT_E:
182 ddi_translations = ddi_translations_fdi;
183 break;
184 default:
185 BUG();
186 }
45244b87 187
f72d19f0
PZ		 188 for (i = 0, reg = DDI_BUF_TRANS(port);
189 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
45244b87
ED		 190 I915_WRITE(reg, ddi_translations[i]);
191 reg += 4;
192 }
6acab15a
PZ		 193 /* Entry 9 is for HDMI: */
194 for (i = 0; i < 2; i++) {
195 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
196 reg += 4;
197 }
45244b87
ED		 198}
199
200/* Program DDI buffers translations for DP. By default, program ports A-D in DP
201 * mode and port E for FDI.
202 */
203void intel_prepare_ddi(struct drm_device *dev)
204{
205 int port;
206
0d536cb4
PZ		 207 if (!HAS_DDI(dev))
208 return;
45244b87 209
ad8d270c
PZ		 210 for (port = PORT_A; port <= PORT_E; port++)
211 intel_prepare_ddi_buffers(dev, port);
45244b87 212}
c82e4d26
ED		 213
214static const long hsw_ddi_buf_ctl_values[] = {
215 DDI_BUF_EMP_400MV_0DB_HSW,
216 DDI_BUF_EMP_400MV_3_5DB_HSW,
217 DDI_BUF_EMP_400MV_6DB_HSW,
218 DDI_BUF_EMP_400MV_9_5DB_HSW,
219 DDI_BUF_EMP_600MV_0DB_HSW,
220 DDI_BUF_EMP_600MV_3_5DB_HSW,
221 DDI_BUF_EMP_600MV_6DB_HSW,
222 DDI_BUF_EMP_800MV_0DB_HSW,
223 DDI_BUF_EMP_800MV_3_5DB_HSW
224};
225
248138b5
PZ		 226static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
227 enum port port)
228{
229 uint32_t reg = DDI_BUF_CTL(port);
230 int i;
231
232 for (i = 0; i < 8; i++) {
233 udelay(1);
234 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
235 return;
236 }
237 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
238}
c82e4d26
ED		 239
240/* Starting with Haswell, different DDI ports can work in FDI mode for
241 * connection to the PCH-located connectors. For this, it is necessary to train
242 * both the DDI port and PCH receiver for the desired DDI buffer settings.
243 *
244 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
245 * please note that when FDI mode is active on DDI E, it shares 2 lines with
246 * DDI A (which is used for eDP)
247 */
248
249void hsw_fdi_link_train(struct drm_crtc *crtc)
250{
251 struct drm_device *dev = crtc->dev;
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 254 u32 temp, i, rx_ctl_val;
c82e4d26 255
04945641
PZ		 256 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
257 * mode set "sequence for CRT port" document:
258 * - TP1 to TP2 time with the default value
259 * - FDI delay to 90h
8693a824
DL		 260 *
261 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 262 */
263 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
264 FDI_RX_PWRDN_LANE0_VAL(2) |
265 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
266
267 /* Enable the PCH Receiver FDI PLL */
3e68320e 268 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 269 FDI_RX_PLL_ENABLE |
627eb5a3 270 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
04945641
PZ		 271 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
272 POSTING_READ(_FDI_RXA_CTL);
273 udelay(220);
274
275 /* Switch from Rawclk to PCDclk */
276 rx_ctl_val |= FDI_PCDCLK;
277 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
278
279 /* Configure Port Clock Select */
280 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
281
282 /* Start the training iterating through available voltages and emphasis,
283 * testing each value twice. */
284 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
c82e4d26
ED		 285 /* Configure DP_TP_CTL with auto-training */
286 I915_WRITE(DP_TP_CTL(PORT_E),
287 DP_TP_CTL_FDI_AUTOTRAIN |
288 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
289 DP_TP_CTL_LINK_TRAIN_PAT1 |
290 DP_TP_CTL_ENABLE);
291
876a8cdf
DL		 292 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
293 * DDI E does not support port reversal, the functionality is
294 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
295 * port reversal bit */
c82e4d26 296 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 297 DDI_BUF_CTL_ENABLE |
33d29b14 298 ((intel_crtc->config.fdi_lanes - 1) << 1) |
04945641
PZ		 299 hsw_ddi_buf_ctl_values[i / 2]);
300 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 301
302 udelay(600);
303
04945641
PZ		 304 /* Program PCH FDI Receiver TU */
305 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
306
307 /* Enable PCH FDI Receiver with auto-training */
308 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
309 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
310 POSTING_READ(_FDI_RXA_CTL);
311
312 /* Wait for FDI receiver lane calibration */
313 udelay(30);
314
315 /* Unset FDI_RX_MISC pwrdn lanes */
316 temp = I915_READ(_FDI_RXA_MISC);
317 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
318 I915_WRITE(_FDI_RXA_MISC, temp);
319 POSTING_READ(_FDI_RXA_MISC);
320
321 /* Wait for FDI auto training time */
322 udelay(5);
c82e4d26
ED		 323
324 temp = I915_READ(DP_TP_STATUS(PORT_E));
325 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 326 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 327
328 /* Enable normal pixel sending for FDI */
329 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 330 DP_TP_CTL_FDI_AUTOTRAIN |
331 DP_TP_CTL_LINK_TRAIN_NORMAL |
332 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
333 DP_TP_CTL_ENABLE);
c82e4d26 334
04945641 335 return;
c82e4d26 336 }
04945641 337
248138b5
PZ		 338 temp = I915_READ(DDI_BUF_CTL(PORT_E));
339 temp &= ~DDI_BUF_CTL_ENABLE;
340 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
341 POSTING_READ(DDI_BUF_CTL(PORT_E));
342
04945641 343 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 344 temp = I915_READ(DP_TP_CTL(PORT_E));
345 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
346 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
347 I915_WRITE(DP_TP_CTL(PORT_E), temp);
348 POSTING_READ(DP_TP_CTL(PORT_E));
349
350 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 351
352 rx_ctl_val &= ~FDI_RX_ENABLE;
353 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 354 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 355
356 /* Reset FDI_RX_MISC pwrdn lanes */
357 temp = I915_READ(_FDI_RXA_MISC);
358 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
359 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
360 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 361 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 362 }
363
04945641 364 DRM_ERROR("FDI link training failed!\n");
c82e4d26 365}
0e72a5b5 366
c7d8be30 367static void intel_ddi_mode_set(struct intel_encoder *encoder)
72662e10 368{
c7d8be30
DV		 369 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
370 int port = intel_ddi_get_encoder_port(encoder);
371 int pipe = crtc->pipe;
372 int type = encoder->type;
373 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
72662e10 374
bf98a726 375 DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
247d89f6 376 port_name(port), pipe_name(pipe));
72662e10 377
9ed109a7
DV		 378 if (crtc->config.has_audio) {
379 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
380 pipe_name(crtc->pipe));
381
382 /* write eld */
383 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
384 intel_write_eld(&encoder->base, adjusted_mode);
385 }
386
247d89f6 387 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c7d8be30 388 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
876a8cdf 389 struct intel_digital_port *intel_dig_port =
c7d8be30 390 enc_to_dig_port(&encoder->base);
4f07854d 391
bcf53de4 392 intel_dp->DP = intel_dig_port->saved_port_bits |
876a8cdf 393 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
17aa6be9 394 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
247d89f6 395 } else if (type == INTEL_OUTPUT_HDMI) {
c7d8be30 396 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
247d89f6 397
6897b4b5
DV		 398 intel_hdmi->set_infoframes(&encoder->base,
399 crtc->config.has_hdmi_sink,
400 adjusted_mode);
247d89f6 401 }
8d9ddbcb
PZ		 402}
403
404static struct intel_encoder *
405intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
406{
407 struct drm_device *dev = crtc->dev;
408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
409 struct intel_encoder *intel_encoder, *ret = NULL;
410 int num_encoders = 0;
411
412 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
413 ret = intel_encoder;
414 num_encoders++;
415 }
416
417 if (num_encoders != 1)
84f44ce7
VS		 418 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
419 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 420
421 BUG_ON(ret == NULL);
422 return ret;
423}
424
6441ab5f
PZ		 425void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
426{
427 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
428 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
430 uint32_t val;
431
432 switch (intel_crtc->ddi_pll_sel) {
433 case PORT_CLK_SEL_SPLL:
434 plls->spll_refcount--;
435 if (plls->spll_refcount == 0) {
436 DRM_DEBUG_KMS("Disabling SPLL\n");
437 val = I915_READ(SPLL_CTL);
438 WARN_ON(!(val & SPLL_PLL_ENABLE));
439 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
440 POSTING_READ(SPLL_CTL);
441 }
442 break;
443 case PORT_CLK_SEL_WRPLL1:
444 plls->wrpll1_refcount--;
445 if (plls->wrpll1_refcount == 0) {
446 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
447 val = I915_READ(WRPLL_CTL1);
448 WARN_ON(!(val & WRPLL_PLL_ENABLE));
449 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
450 POSTING_READ(WRPLL_CTL1);
451 }
452 break;
453 case PORT_CLK_SEL_WRPLL2:
454 plls->wrpll2_refcount--;
455 if (plls->wrpll2_refcount == 0) {
456 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
457 val = I915_READ(WRPLL_CTL2);
458 WARN_ON(!(val & WRPLL_PLL_ENABLE));
459 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
460 POSTING_READ(WRPLL_CTL2);
461 }
462 break;
463 }
464
465 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
466 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
467 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
468
469 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
470}
471
1c0b85c5
DL		 472#define LC_FREQ 2700
473#define LC_FREQ_2K (LC_FREQ * 2000)
474
475#define P_MIN 2
476#define P_MAX 64
477#define P_INC 2
478
479/* Constraints for PLL good behavior */
480#define REF_MIN 48
481#define REF_MAX 400
482#define VCO_MIN 2400
483#define VCO_MAX 4800
484
485#define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
486
487struct wrpll_rnp {
488 unsigned p, n2, r2;
489};
490
491static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 492{
1c0b85c5
DL		 493 unsigned budget;
494
495 switch (clock) {
496 case 25175000:
497 case 25200000:
498 case 27000000:
499 case 27027000:
500 case 37762500:
501 case 37800000:
502 case 40500000:
503 case 40541000:
504 case 54000000:
505 case 54054000:
506 case 59341000:
507 case 59400000:
508 case 72000000:
509 case 74176000:
510 case 74250000:
511 case 81000000:
512 case 81081000:
513 case 89012000:
514 case 89100000:
515 case 108000000:
516 case 108108000:
517 case 111264000:
518 case 111375000:
519 case 148352000:
520 case 148500000:
521 case 162000000:
522 case 162162000:
523 case 222525000:
524 case 222750000:
525 case 296703000:
526 case 297000000:
527 budget = 0;
528 break;
529 case 233500000:
530 case 245250000:
531 case 247750000:
532 case 253250000:
533 case 298000000:
534 budget = 1500;
535 break;
536 case 169128000:
537 case 169500000:
538 case 179500000:
539 case 202000000:
540 budget = 2000;
541 break;
542 case 256250000:
543 case 262500000:
544 case 270000000:
545 case 272500000:
546 case 273750000:
547 case 280750000:
548 case 281250000:
549 case 286000000:
550 case 291750000:
551 budget = 4000;
552 break;
553 case 267250000:
554 case 268500000:
555 budget = 5000;
556 break;
557 default:
558 budget = 1000;
559 break;
560 }
6441ab5f 561
1c0b85c5
DL		 562 return budget;
563}
564
565static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
566 unsigned r2, unsigned n2, unsigned p,
567 struct wrpll_rnp *best)
568{
569 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 570
1c0b85c5
DL		 571 /* No best (r,n,p) yet */
572 if (best->p == 0) {
573 best->p = p;
574 best->n2 = n2;
575 best->r2 = r2;
576 return;
577 }
6441ab5f 578
1c0b85c5
DL		 579 /*
580 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
581 * freq2k.
582 *
583 * delta = 1e6 *
584 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
585 * freq2k;
586 *
587 * and we would like delta <= budget.
588 *
589 * If the discrepancy is above the PPM-based budget, always prefer to
590 * improve upon the previous solution. However, if you're within the
591 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
592 */
593 a = freq2k * budget * p * r2;
594 b = freq2k * budget * best->p * best->r2;
595 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
596 diff_best = ABS_DIFF((freq2k * best->p * best->r2),
597 (LC_FREQ_2K * best->n2));
598 c = 1000000 * diff;
599 d = 1000000 * diff_best;
600
601 if (a < c && b < d) {
602 /* If both are above the budget, pick the closer */
603 if (best->p * best->r2 * diff < p * r2 * diff_best) {
604 best->p = p;
605 best->n2 = n2;
606 best->r2 = r2;
607 }
608 } else if (a >= c && b < d) {
609 /* If A is below the threshold but B is above it? Update. */
610 best->p = p;
611 best->n2 = n2;
612 best->r2 = r2;
613 } else if (a >= c && b >= d) {
614 /* Both are below the limit, so pick the higher n2/(r2*r2) */
615 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
616 best->p = p;
617 best->n2 = n2;
618 best->r2 = r2;
619 }
620 }
621 /* Otherwise a < c && b >= d, do nothing */
622}
623
11578553
JB		 624static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
625 int reg)
626{
627 int refclk = LC_FREQ;
628 int n, p, r;
629 u32 wrpll;
630
631 wrpll = I915_READ(reg);
632 switch (wrpll & SPLL_PLL_REF_MASK) {
633 case SPLL_PLL_SSC:
634 case SPLL_PLL_NON_SSC:
635 /*
636 * We could calculate spread here, but our checking
637 * code only cares about 5% accuracy, and spread is a max of
638 * 0.5% downspread.
639 */
640 refclk = 135;
641 break;
642 case SPLL_PLL_LCPLL:
643 refclk = LC_FREQ;
644 break;
645 default:
646 WARN(1, "bad wrpll refclk\n");
647 return 0;
648 }
649
650 r = wrpll & WRPLL_DIVIDER_REF_MASK;
651 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
652 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
653
20f0ec16
JB		 654 /* Convert to KHz, p & r have a fixed point portion */
655 return (refclk * n * 100) / (p * r);
11578553
JB		 656}
657
658static void intel_ddi_clock_get(struct intel_encoder *encoder,
659 struct intel_crtc_config *pipe_config)
660{
661 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
662 enum port port = intel_ddi_get_encoder_port(encoder);
663 int link_clock = 0;
664 u32 val, pll;
665
666 val = I915_READ(PORT_CLK_SEL(port));
667 switch (val & PORT_CLK_SEL_MASK) {
668 case PORT_CLK_SEL_LCPLL_810:
669 link_clock = 81000;
670 break;
671 case PORT_CLK_SEL_LCPLL_1350:
672 link_clock = 135000;
673 break;
674 case PORT_CLK_SEL_LCPLL_2700:
675 link_clock = 270000;
676 break;
677 case PORT_CLK_SEL_WRPLL1:
678 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
679 break;
680 case PORT_CLK_SEL_WRPLL2:
681 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
682 break;
683 case PORT_CLK_SEL_SPLL:
684 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
685 if (pll == SPLL_PLL_FREQ_810MHz)
686 link_clock = 81000;
687 else if (pll == SPLL_PLL_FREQ_1350MHz)
688 link_clock = 135000;
689 else if (pll == SPLL_PLL_FREQ_2700MHz)
690 link_clock = 270000;
691 else {
692 WARN(1, "bad spll freq\n");
693 return;
694 }
695 break;
696 default:
697 WARN(1, "bad port clock sel\n");
698 return;
699 }
700
701 pipe_config->port_clock = link_clock * 2;
702
703 if (pipe_config->has_pch_encoder)
704 pipe_config->adjusted_mode.crtc_clock =
705 intel_dotclock_calculate(pipe_config->port_clock,
706 &pipe_config->fdi_m_n);
707 else if (pipe_config->has_dp_encoder)
708 pipe_config->adjusted_mode.crtc_clock =
709 intel_dotclock_calculate(pipe_config->port_clock,
710 &pipe_config->dp_m_n);
711 else
712 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
713}
714
1c0b85c5
DL		 715static void
716intel_ddi_calculate_wrpll(int clock /* in Hz */,
717 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
718{
719 uint64_t freq2k;
720 unsigned p, n2, r2;
721 struct wrpll_rnp best = { 0, 0, 0 };
722 unsigned budget;
723
724 freq2k = clock / 100;
725
726 budget = wrpll_get_budget_for_freq(clock);
727
728 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
729 * and directly pass the LC PLL to it. */
730 if (freq2k == 5400000) {
731 *n2_out = 2;
732 *p_out = 1;
733 *r2_out = 2;
734 return;
735 }
736
737 /*
738 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
739 * the WR PLL.
740 *
741 * We want R so that REF_MIN <= Ref <= REF_MAX.
742 * Injecting R2 = 2 * R gives:
743 * REF_MAX * r2 > LC_FREQ * 2 and
744 * REF_MIN * r2 < LC_FREQ * 2
745 *
746 * Which means the desired boundaries for r2 are:
747 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
748 *
749 */
750 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
751 r2 <= LC_FREQ * 2 / REF_MIN;
752 r2++) {
753
754 /*
755 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
756 *
757 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
758 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
759 * VCO_MAX * r2 > n2 * LC_FREQ and
760 * VCO_MIN * r2 < n2 * LC_FREQ)
761 *
762 * Which means the desired boundaries for n2 are:
763 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
764 */
765 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
766 n2 <= VCO_MAX * r2 / LC_FREQ;
767 n2++) {
768
769 for (p = P_MIN; p <= P_MAX; p += P_INC)
770 wrpll_update_rnp(freq2k, budget,
771 r2, n2, p, &best);
772 }
773 }
6441ab5f 774
1c0b85c5
DL		 775 *n2_out = best.n2;
776 *p_out = best.p;
777 *r2_out = best.r2;
6441ab5f
PZ		 778}
779
566b734a
PZ		 780/*
781 * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
782 * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
783 * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
784 * enable the PLL.
785 */
786bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
6441ab5f 787{
566b734a 788 struct drm_crtc *crtc = &intel_crtc->base;
6441ab5f 789 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
068759bd 790 struct drm_encoder *encoder = &intel_encoder->base;
6441ab5f
PZ		 791 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
792 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
793 int type = intel_encoder->type;
794 enum pipe pipe = intel_crtc->pipe;
ff9a6750 795 int clock = intel_crtc->config.port_clock;
6441ab5f 796
6441ab5f
PZ		 797 intel_ddi_put_crtc_pll(crtc);
798
068759bd
PZ		 799 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
800 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
801
802 switch (intel_dp->link_bw) {
803 case DP_LINK_BW_1_62:
804 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
805 break;
806 case DP_LINK_BW_2_7:
807 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
808 break;
809 case DP_LINK_BW_5_4:
810 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
811 break;
812 default:
813 DRM_ERROR("Link bandwidth %d unsupported\n",
814 intel_dp->link_bw);
815 return false;
816 }
817
068759bd 818 } else if (type == INTEL_OUTPUT_HDMI) {
566b734a 819 uint32_t reg, val;
1c0b85c5 820 unsigned p, n2, r2;
6441ab5f 821
0694001b
PZ		 822 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
823
824 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
825 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
826 WRPLL_DIVIDER_POST(p);
827
828 if (val == I915_READ(WRPLL_CTL1)) {
829 DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
830 pipe_name(pipe));
831 reg = WRPLL_CTL1;
832 } else if (val == I915_READ(WRPLL_CTL2)) {
833 DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
834 pipe_name(pipe));
835 reg = WRPLL_CTL2;
836 } else if (plls->wrpll1_refcount == 0) {
6441ab5f
PZ		 837 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
838 pipe_name(pipe));
6441ab5f 839 reg = WRPLL_CTL1;
6441ab5f
PZ		 840 } else if (plls->wrpll2_refcount == 0) {
841 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
842 pipe_name(pipe));
6441ab5f 843 reg = WRPLL_CTL2;
6441ab5f
PZ		 844 } else {
845 DRM_ERROR("No WRPLLs available!\n");
846 return false;
847 }
848
566b734a
PZ		 849 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
850 clock, p, n2, r2);
851
0694001b
PZ		 852 if (reg == WRPLL_CTL1) {
853 plls->wrpll1_refcount++;
854 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
855 } else {
856 plls->wrpll2_refcount++;
857 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
858 }
6441ab5f
PZ		 859
860 } else if (type == INTEL_OUTPUT_ANALOG) {
861 if (plls->spll_refcount == 0) {
862 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
863 pipe_name(pipe));
864 plls->spll_refcount++;
6441ab5f 865 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
00037c2e
DL		 866 } else {
867 DRM_ERROR("SPLL already in use\n");
868 return false;
6441ab5f
PZ		 869 }
870
6441ab5f
PZ		 871 } else {
872 WARN(1, "Invalid DDI encoder type %d\n", type);
873 return false;
874 }
875
6441ab5f
PZ		 876 return true;
877}
878
566b734a
PZ		 879/*
880 * To be called after intel_ddi_pll_select(). That one selects the PLL to be
881 * used, this one actually enables the PLL.
882 */
883void intel_ddi_pll_enable(struct intel_crtc *crtc)
884{
885 struct drm_device *dev = crtc->base.dev;
886 struct drm_i915_private *dev_priv = dev->dev_private;
887 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
888 int clock = crtc->config.port_clock;
889 uint32_t reg, cur_val, new_val;
890 int refcount;
891 const char *pll_name;
892 uint32_t enable_bit = (1 << 31);
893 unsigned int p, n2, r2;
894
895 BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
896 BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
897
898 switch (crtc->ddi_pll_sel) {
899 case PORT_CLK_SEL_LCPLL_2700:
900 case PORT_CLK_SEL_LCPLL_1350:
901 case PORT_CLK_SEL_LCPLL_810:
902 /*
903 * LCPLL should always be enabled at this point of the mode set
904 * sequence, so nothing to do.
905 */
906 return;
907
908 case PORT_CLK_SEL_SPLL:
909 pll_name = "SPLL";
910 reg = SPLL_CTL;
911 refcount = plls->spll_refcount;
912 new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
913 SPLL_PLL_SSC;
914 break;
915
916 case PORT_CLK_SEL_WRPLL1:
917 case PORT_CLK_SEL_WRPLL2:
918 if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
919 pll_name = "WRPLL1";
920 reg = WRPLL_CTL1;
921 refcount = plls->wrpll1_refcount;
922 } else {
923 pll_name = "WRPLL2";
924 reg = WRPLL_CTL2;
925 refcount = plls->wrpll2_refcount;
926 }
927
928 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
929
930 new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
931 WRPLL_DIVIDER_REFERENCE(r2) |
932 WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
933
934 break;
935
936 case PORT_CLK_SEL_NONE:
937 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
938 return;
939 default:
940 WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel);
941 return;
942 }
943
944 cur_val = I915_READ(reg);
945
946 WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
947 if (refcount == 1) {
948 WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
949 I915_WRITE(reg, new_val);
950 POSTING_READ(reg);
951 udelay(20);
952 } else {
953 WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
954 }
955}
956
dae84799
PZ		 957void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
958{
959 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
961 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3b117c8f 962 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
dae84799
PZ		 963 int type = intel_encoder->type;
964 uint32_t temp;
965
966 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
967
c9809791 968 temp = TRANS_MSA_SYNC_CLK;
965e0c48 969 switch (intel_crtc->config.pipe_bpp) {
dae84799 970 case 18:
c9809791 971 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 972 break;
973 case 24:
c9809791 974 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 975 break;
976 case 30:
c9809791 977 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 978 break;
979 case 36:
c9809791 980 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 981 break;
982 default:
4e53c2e0 983 BUG();
dae84799 984 }
c9809791 985 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 986 }
987}
988
8228c251 989void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 990{
991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
992 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 993 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 994 struct drm_device *dev = crtc->dev;
995 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 996 enum pipe pipe = intel_crtc->pipe;
3b117c8f 997 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
174edf1f 998 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 999 int type = intel_encoder->type;
8d9ddbcb
PZ		 1000 uint32_t temp;
1001
ad80a810
PZ		 1002 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1003 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1004 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1005
965e0c48 1006 switch (intel_crtc->config.pipe_bpp) {
dfcef252 1007 case 18:
ad80a810 1008 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1009 break;
1010 case 24:
ad80a810 1011 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1012 break;
1013 case 30:
ad80a810 1014 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1015 break;
1016 case 36:
ad80a810 1017 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1018 break;
1019 default:
4e53c2e0 1020 BUG();
dfcef252 1021 }
72662e10 1022
a666283e 1023 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1024 temp |= TRANS_DDI_PVSYNC;
a666283e 1025 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1026 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1027
e6f0bfc4
PZ		 1028 if (cpu_transcoder == TRANSCODER_EDP) {
1029 switch (pipe) {
1030 case PIPE_A:
c7670b10
PZ		 1031 /* On Haswell, can only use the always-on power well for
1032 * eDP when not using the panel fitter, and when not
1033 * using motion blur mitigation (which we don't
1034 * support). */
1035 if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
d6dd9eb1
DV		 1036 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1037 else
1038 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1039 break;
1040 case PIPE_B:
1041 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1042 break;
1043 case PIPE_C:
1044 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1045 break;
1046 default:
1047 BUG();
1048 break;
1049 }
1050 }
1051
7739c33b 1052 if (type == INTEL_OUTPUT_HDMI) {
6897b4b5 1053 if (intel_crtc->config.has_hdmi_sink)
ad80a810 1054 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1055 else
ad80a810 1056 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1057
7739c33b 1058 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1059 temp |= TRANS_DDI_MODE_SELECT_FDI;
33d29b14 1060 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
7739c33b
PZ		 1061
1062 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1063 type == INTEL_OUTPUT_EDP) {
1064 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1065
ad80a810 1066 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1067
17aa6be9 1068 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1069 } else {
84f44ce7
VS		 1070 WARN(1, "Invalid encoder type %d for pipe %c\n",
1071 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1072 }
1073
ad80a810 1074 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1075}
72662e10 1076
ad80a810
PZ		 1077void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1078 enum transcoder cpu_transcoder)
8d9ddbcb 1079{
ad80a810 1080 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1081 uint32_t val = I915_READ(reg);
1082
ad80a810
PZ		 1083 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1084 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1085 I915_WRITE(reg, val);
72662e10
ED		 1086}
1087
bcbc889b
PZ		 1088bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1089{
1090 struct drm_device *dev = intel_connector->base.dev;
1091 struct drm_i915_private *dev_priv = dev->dev_private;
1092 struct intel_encoder *intel_encoder = intel_connector->encoder;
1093 int type = intel_connector->base.connector_type;
1094 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1095 enum pipe pipe = 0;
1096 enum transcoder cpu_transcoder;
882244a3 1097 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1098 uint32_t tmp;
1099
882244a3
PZ		 1100 power_domain = intel_display_port_power_domain(intel_encoder);
1101 if (!intel_display_power_enabled(dev_priv, power_domain))
1102 return false;
1103
bcbc889b
PZ		 1104 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1105 return false;
1106
1107 if (port == PORT_A)
1108 cpu_transcoder = TRANSCODER_EDP;
1109 else
1a240d4d 1110 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1111
1112 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1113
1114 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1115 case TRANS_DDI_MODE_SELECT_HDMI:
1116 case TRANS_DDI_MODE_SELECT_DVI:
1117 return (type == DRM_MODE_CONNECTOR_HDMIA);
1118
1119 case TRANS_DDI_MODE_SELECT_DP_SST:
1120 if (type == DRM_MODE_CONNECTOR_eDP)
1121 return true;
1122 case TRANS_DDI_MODE_SELECT_DP_MST:
1123 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1124
1125 case TRANS_DDI_MODE_SELECT_FDI:
1126 return (type == DRM_MODE_CONNECTOR_VGA);
1127
1128 default:
1129 return false;
1130 }
1131}
1132
85234cdc
DV		 1133bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1134 enum pipe *pipe)
1135{
1136 struct drm_device *dev = encoder->base.dev;
1137 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1138 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1139 enum intel_display_power_domain power_domain;
85234cdc
DV		 1140 u32 tmp;
1141 int i;
1142
6d129bea
ID		 1143 power_domain = intel_display_port_power_domain(encoder);
1144 if (!intel_display_power_enabled(dev_priv, power_domain))
1145 return false;
1146
fe43d3f5 1147 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1148
1149 if (!(tmp & DDI_BUF_CTL_ENABLE))
1150 return false;
1151
ad80a810
PZ		 1152 if (port == PORT_A) {
1153 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1154
ad80a810
PZ		 1155 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1156 case TRANS_DDI_EDP_INPUT_A_ON:
1157 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1158 *pipe = PIPE_A;
1159 break;
1160 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1161 *pipe = PIPE_B;
1162 break;
1163 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1164 *pipe = PIPE_C;
1165 break;
1166 }
1167
1168 return true;
1169 } else {
1170 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1171 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1172
1173 if ((tmp & TRANS_DDI_PORT_MASK)
1174 == TRANS_DDI_SELECT_PORT(port)) {
1175 *pipe = i;
1176 return true;
1177 }
85234cdc
DV		 1178 }
1179 }
1180
84f44ce7 1181 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1182
22f9fe50 1183 return false;
85234cdc
DV		 1184}
1185
6441ab5f
PZ		 1186static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1187 enum pipe pipe)
1188{
1189 uint32_t temp, ret;
a42f704b 1190 enum port port = I915_MAX_PORTS;
ad80a810
PZ		 1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
6441ab5f
PZ		 1193 int i;
1194
ad80a810
PZ		 1195 if (cpu_transcoder == TRANSCODER_EDP) {
1196 port = PORT_A;
1197 } else {
1198 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1199 temp &= TRANS_DDI_PORT_MASK;
1200
1201 for (i = PORT_B; i <= PORT_E; i++)
1202 if (temp == TRANS_DDI_SELECT_PORT(i))
1203 port = i;
1204 }
6441ab5f 1205
a42f704b
DL		 1206 if (port == I915_MAX_PORTS) {
1207 WARN(1, "Pipe %c enabled on an unknown port\n",
1208 pipe_name(pipe));
1209 ret = PORT_CLK_SEL_NONE;
1210 } else {
1211 ret = I915_READ(PORT_CLK_SEL(port));
1212 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1213 "0x%08x\n", pipe_name(pipe), port_name(port),
1214 ret);
1215 }
6441ab5f
PZ		 1216
1217 return ret;
1218}
1219
1220void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1221{
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 enum pipe pipe;
1224 struct intel_crtc *intel_crtc;
1225
0882dae9
PZ		 1226 dev_priv->ddi_plls.spll_refcount = 0;
1227 dev_priv->ddi_plls.wrpll1_refcount = 0;
1228 dev_priv->ddi_plls.wrpll2_refcount = 0;
1229
6441ab5f
PZ		 1230 for_each_pipe(pipe) {
1231 intel_crtc =
1232 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1233
0882dae9
PZ		 1234 if (!intel_crtc->active) {
1235 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
6441ab5f 1236 continue;
0882dae9 1237 }
6441ab5f
PZ		 1238
1239 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1240 pipe);
1241
1242 switch (intel_crtc->ddi_pll_sel) {
1243 case PORT_CLK_SEL_SPLL:
1244 dev_priv->ddi_plls.spll_refcount++;
1245 break;
1246 case PORT_CLK_SEL_WRPLL1:
1247 dev_priv->ddi_plls.wrpll1_refcount++;
1248 break;
1249 case PORT_CLK_SEL_WRPLL2:
1250 dev_priv->ddi_plls.wrpll2_refcount++;
1251 break;
1252 }
1253 }
1254}
1255
fc914639
PZ		 1256void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1257{
1258 struct drm_crtc *crtc = &intel_crtc->base;
1259 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1260 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1261 enum port port = intel_ddi_get_encoder_port(intel_encoder);
3b117c8f 1262 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1263
bb523fc0
PZ		 1264 if (cpu_transcoder != TRANSCODER_EDP)
1265 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1266 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1267}
1268
1269void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1270{
1271 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3b117c8f 1272 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1273
bb523fc0
PZ		 1274 if (cpu_transcoder != TRANSCODER_EDP)
1275 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1276 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1277}
1278
00c09d70 1279static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1280{
c19b0669
PZ		 1281 struct drm_encoder *encoder = &intel_encoder->base;
1282 struct drm_crtc *crtc = encoder->crtc;
1283 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
6441ab5f
PZ		 1284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1285 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1286 int type = intel_encoder->type;
6441ab5f 1287
82a4d9c0
PZ		 1288 if (type == INTEL_OUTPUT_EDP) {
1289 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1290 intel_edp_panel_on(intel_dp);
82a4d9c0 1291 }
6441ab5f 1292
82a4d9c0 1293 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
6441ab5f 1294 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
c19b0669 1295
82a4d9c0 1296 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669
PZ		 1297 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1298
1299 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1300 intel_dp_start_link_train(intel_dp);
1301 intel_dp_complete_link_train(intel_dp);
3ab9c637
ID		 1302 if (port != PORT_A)
1303 intel_dp_stop_link_train(intel_dp);
c19b0669 1304 }
6441ab5f
PZ		 1305}
1306
00c09d70 1307static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1308{
1309 struct drm_encoder *encoder = &intel_encoder->base;
1310 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1311 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1312 int type = intel_encoder->type;
2886e93f 1313 uint32_t val;
a836bdf9 1314 bool wait = false;
2886e93f
PZ		 1315
1316 val = I915_READ(DDI_BUF_CTL(port));
1317 if (val & DDI_BUF_CTL_ENABLE) {
1318 val &= ~DDI_BUF_CTL_ENABLE;
1319 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1320 wait = true;
2886e93f 1321 }
6441ab5f 1322
a836bdf9
PZ		 1323 val = I915_READ(DP_TP_CTL(port));
1324 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1325 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1326 I915_WRITE(DP_TP_CTL(port), val);
1327
1328 if (wait)
1329 intel_wait_ddi_buf_idle(dev_priv, port);
1330
76bb80ed 1331 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1332 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1333 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1334 intel_edp_panel_vdd_on(intel_dp);
4be73780 1335 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1336 }
1337
6441ab5f
PZ		 1338 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1339}
1340
00c09d70 1341static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1342{
6547fef8 1343 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1344 struct drm_crtc *crtc = encoder->crtc;
1345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1346 int pipe = intel_crtc->pipe;
6547fef8 1347 struct drm_device *dev = encoder->dev;
72662e10 1348 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1349 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1350 int type = intel_encoder->type;
7b9f35a6 1351 uint32_t tmp;
72662e10 1352
6547fef8 1353 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1354 struct intel_digital_port *intel_dig_port =
1355 enc_to_dig_port(encoder);
1356
6547fef8
PZ		 1357 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1358 * are ignored so nothing special needs to be done besides
1359 * enabling the port.
1360 */
876a8cdf 1361 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1362 intel_dig_port->saved_port_bits |
1363 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1364 } else if (type == INTEL_OUTPUT_EDP) {
1365 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1366
3ab9c637
ID		 1367 if (port == PORT_A)
1368 intel_dp_stop_link_train(intel_dp);
1369
4be73780 1370 intel_edp_backlight_on(intel_dp);
4906557e 1371 intel_edp_psr_enable(intel_dp);
6547fef8 1372 }
7b9f35a6 1373
9ed109a7 1374 if (intel_crtc->config.has_audio) {
7b9f35a6
WX		 1375 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1376 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1377 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1378 }
5ab432ef
DV		 1379}
1380
00c09d70 1381static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1382{
d6c50ff8 1383 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1384 struct drm_crtc *crtc = encoder->crtc;
1385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1386 int pipe = intel_crtc->pipe;
d6c50ff8 1387 int type = intel_encoder->type;
7b9f35a6
WX		 1388 struct drm_device *dev = encoder->dev;
1389 struct drm_i915_private *dev_priv = dev->dev_private;
1390 uint32_t tmp;
d6c50ff8 1391
acfa75b0
DV		 1392 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1393 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1394 (pipe * 4));
1395 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
2831d842 1396
d6c50ff8
PZ		 1397 if (type == INTEL_OUTPUT_EDP) {
1398 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1399
4906557e 1400 intel_edp_psr_disable(intel_dp);
4be73780 1401 intel_edp_backlight_off(intel_dp);
d6c50ff8 1402 }
72662e10 1403}
79f689aa 1404
b8fc2f6a 1405int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa 1406{
e39bf98a 1407 struct drm_device *dev = dev_priv->dev;
a4006641 1408 uint32_t lcpll = I915_READ(LCPLL_CTL);
e39bf98a 1409 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
a4006641 1410
e39bf98a 1411 if (lcpll & LCPLL_CD_SOURCE_FCLK) {
a4006641 1412 return 800000;
e3589908 1413 } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
b2b877ff 1414 return 450000;
e39bf98a 1415 } else if (freq == LCPLL_CLK_FREQ_450) {
b2b877ff 1416 return 450000;
e39bf98a
PZ		 1417 } else if (IS_HASWELL(dev)) {
1418 if (IS_ULT(dev))
1419 return 337500;
1420 else
1421 return 540000;
1422 } else {
1423 if (freq == LCPLL_CLK_FREQ_54O_BDW)
1424 return 540000;
1425 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1426 return 337500;
1427 else
1428 return 675000;
1429 }
79f689aa
PZ		 1430}
1431
1432void intel_ddi_pll_init(struct drm_device *dev)
1433{
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1435 uint32_t val = I915_READ(LCPLL_CTL);
1436
1437 /* The LCPLL register should be turned on by the BIOS. For now let's
1438 * just check its state and print errors in case something is wrong.
1439 * Don't even try to turn it on.
1440 */
1441
b2b877ff 1442 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
79f689aa
PZ		 1443 intel_ddi_get_cdclk_freq(dev_priv));
1444
1445 if (val & LCPLL_CD_SOURCE_FCLK)
1446 DRM_ERROR("CDCLK source is not LCPLL\n");
1447
1448 if (val & LCPLL_PLL_DISABLE)
1449 DRM_ERROR("LCPLL is disabled\n");
1450}
c19b0669
PZ		 1451
1452void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1453{
174edf1f
PZ		 1454 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1455 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1456 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1457 enum port port = intel_dig_port->port;
c19b0669 1458 uint32_t val;
f3e227df 1459 bool wait = false;
c19b0669
PZ		 1460
1461 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1462 val = I915_READ(DDI_BUF_CTL(port));
1463 if (val & DDI_BUF_CTL_ENABLE) {
1464 val &= ~DDI_BUF_CTL_ENABLE;
1465 I915_WRITE(DDI_BUF_CTL(port), val);
1466 wait = true;
1467 }
1468
1469 val = I915_READ(DP_TP_CTL(port));
1470 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1471 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1472 I915_WRITE(DP_TP_CTL(port), val);
1473 POSTING_READ(DP_TP_CTL(port));
1474
1475 if (wait)
1476 intel_wait_ddi_buf_idle(dev_priv, port);
1477 }
1478
1479 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1480 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
6aba5b6c 1481 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
c19b0669
PZ		 1482 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1483 I915_WRITE(DP_TP_CTL(port), val);
1484 POSTING_READ(DP_TP_CTL(port));
1485
1486 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1487 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1488 POSTING_READ(DDI_BUF_CTL(port));
1489
1490 udelay(600);
1491}
00c09d70 1492
1ad960f2
PZ		 1493void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1494{
1495 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1496 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1497 uint32_t val;
1498
1499 intel_ddi_post_disable(intel_encoder);
1500
1501 val = I915_READ(_FDI_RXA_CTL);
1502 val &= ~FDI_RX_ENABLE;
1503 I915_WRITE(_FDI_RXA_CTL, val);
1504
1505 val = I915_READ(_FDI_RXA_MISC);
1506 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1507 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1508 I915_WRITE(_FDI_RXA_MISC, val);
1509
1510 val = I915_READ(_FDI_RXA_CTL);
1511 val &= ~FDI_PCDCLK;
1512 I915_WRITE(_FDI_RXA_CTL, val);
1513
1514 val = I915_READ(_FDI_RXA_CTL);
1515 val &= ~FDI_RX_PLL_ENABLE;
1516 I915_WRITE(_FDI_RXA_CTL, val);
1517}
1518
00c09d70
PZ		 1519static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1520{
1521 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1522 int type = intel_encoder->type;
1523
1524 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1525 intel_dp_check_link_status(intel_dp);
1526}
1527
6801c18c
VS		 1528void intel_ddi_get_config(struct intel_encoder *encoder,
1529 struct intel_crtc_config *pipe_config)
045ac3b5
JB		 1530{
1531 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1532 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1533 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1534 u32 temp, flags = 0;
1535
1536 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1537 if (temp & TRANS_DDI_PHSYNC)
1538 flags |= DRM_MODE_FLAG_PHSYNC;
1539 else
1540 flags |= DRM_MODE_FLAG_NHSYNC;
1541 if (temp & TRANS_DDI_PVSYNC)
1542 flags |= DRM_MODE_FLAG_PVSYNC;
1543 else
1544 flags |= DRM_MODE_FLAG_NVSYNC;
1545
1546 pipe_config->adjusted_mode.flags |= flags;
42571aef
VS		 1547
1548 switch (temp & TRANS_DDI_BPC_MASK) {
1549 case TRANS_DDI_BPC_6:
1550 pipe_config->pipe_bpp = 18;
1551 break;
1552 case TRANS_DDI_BPC_8:
1553 pipe_config->pipe_bpp = 24;
1554 break;
1555 case TRANS_DDI_BPC_10:
1556 pipe_config->pipe_bpp = 30;
1557 break;
1558 case TRANS_DDI_BPC_12:
1559 pipe_config->pipe_bpp = 36;
1560 break;
1561 default:
1562 break;
1563 }
eb14cb74
VS		 1564
1565 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1566 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 1567 pipe_config->has_hdmi_sink = true;
eb14cb74
VS		 1568 case TRANS_DDI_MODE_SELECT_DVI:
1569 case TRANS_DDI_MODE_SELECT_FDI:
1570 break;
1571 case TRANS_DDI_MODE_SELECT_DP_SST:
1572 case TRANS_DDI_MODE_SELECT_DP_MST:
1573 pipe_config->has_dp_encoder = true;
1574 intel_dp_get_m_n(intel_crtc, pipe_config);
1575 break;
1576 default:
1577 break;
1578 }
10214420 1579
9ed109a7
DV		 1580 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1581 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1582 pipe_config->has_audio = true;
1583
10214420
DV		 1584 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1585 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1586 /*
1587 * This is a big fat ugly hack.
1588 *
1589 * Some machines in UEFI boot mode provide us a VBT that has 18
1590 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1591 * unknown we fail to light up. Yet the same BIOS boots up with
1592 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1593 * max, not what it tells us to use.
1594 *
1595 * Note: This will still be broken if the eDP panel is not lit
1596 * up by the BIOS, and thus we can't get the mode at module
1597 * load.
1598 */
1599 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1600 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1601 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1602 }
11578553
JB		 1603
1604 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 1605}
1606
00c09d70
PZ		 1607static void intel_ddi_destroy(struct drm_encoder *encoder)
1608{
1609 /* HDMI has nothing special to destroy, so we can go with this. */
1610 intel_dp_encoder_destroy(encoder);
1611}
1612
5bfe2ac0
DV		 1613static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1614 struct intel_crtc_config *pipe_config)
00c09d70 1615{
5bfe2ac0 1616 int type = encoder->type;
eccb140b 1617 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 1618
5bfe2ac0 1619 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 1620
eccb140b
DV		 1621 if (port == PORT_A)
1622 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1623
00c09d70 1624 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 1625 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 1626 else
5bfe2ac0 1627 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 1628}
1629
1630static const struct drm_encoder_funcs intel_ddi_funcs = {
1631 .destroy = intel_ddi_destroy,
1632};
1633
4a28ae58
PZ		 1634static struct intel_connector *
1635intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1636{
1637 struct intel_connector *connector;
1638 enum port port = intel_dig_port->port;
1639
1640 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1641 if (!connector)
1642 return NULL;
1643
1644 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1645 if (!intel_dp_init_connector(intel_dig_port, connector)) {
1646 kfree(connector);
1647 return NULL;
1648 }
1649
1650 return connector;
1651}
1652
1653static struct intel_connector *
1654intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1655{
1656 struct intel_connector *connector;
1657 enum port port = intel_dig_port->port;
1658
1659 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1660 if (!connector)
1661 return NULL;
1662
1663 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1664 intel_hdmi_init_connector(intel_dig_port, connector);
1665
1666 return connector;
1667}
1668
00c09d70
PZ		 1669void intel_ddi_init(struct drm_device *dev, enum port port)
1670{
876a8cdf 1671 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 1672 struct intel_digital_port *intel_dig_port;
1673 struct intel_encoder *intel_encoder;
1674 struct drm_encoder *encoder;
1675 struct intel_connector *hdmi_connector = NULL;
1676 struct intel_connector *dp_connector = NULL;
311a2094
PZ		 1677 bool init_hdmi, init_dp;
1678
1679 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1680 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1681 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1682 if (!init_dp && !init_hdmi) {
1683 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1684 port_name(port));
1685 init_hdmi = true;
1686 init_dp = true;
1687 }
00c09d70 1688
b14c5679 1689 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 1690 if (!intel_dig_port)
1691 return;
1692
00c09d70
PZ		 1693 intel_encoder = &intel_dig_port->base;
1694 encoder = &intel_encoder->base;
1695
1696 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1697 DRM_MODE_ENCODER_TMDS);
00c09d70 1698
5bfe2ac0 1699 intel_encoder->compute_config = intel_ddi_compute_config;
c7d8be30 1700 intel_encoder->mode_set = intel_ddi_mode_set;
00c09d70
PZ		 1701 intel_encoder->enable = intel_enable_ddi;
1702 intel_encoder->pre_enable = intel_ddi_pre_enable;
1703 intel_encoder->disable = intel_disable_ddi;
1704 intel_encoder->post_disable = intel_ddi_post_disable;
1705 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 1706 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 1707
1708 intel_dig_port->port = port;
bcf53de4
SM		 1709 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1710 (DDI_BUF_PORT_REVERSAL |
1711 DDI_A_4_LANES);
00c09d70
PZ		 1712
1713 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1714 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 1715 intel_encoder->cloneable = 0;
00c09d70
PZ		 1716 intel_encoder->hot_plug = intel_ddi_hot_plug;
1717
4a28ae58
PZ		 1718 if (init_dp)
1719 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
21a8e6a4 1720
311a2094
PZ		 1721 /* In theory we don't need the encoder->type check, but leave it just in
1722 * case we have some really bad VBTs... */
4a28ae58
PZ		 1723 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
1724 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
21a8e6a4 1725
4a28ae58
PZ		 1726 if (!dp_connector && !hdmi_connector) {
1727 drm_encoder_cleanup(encoder);
1728 kfree(intel_dig_port);
21a8e6a4 1729 }
00c09d70 1730}
Linux 6.x block layer and io_uring tree(s)