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drm/i915: Remove spll_refcount for hsw
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
31/* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45244b87
ED		 45};
46
47static const u32 hsw_ddi_translations_fdi[] = {
48 0x00FFFFFF, 0x0007000E, /* FDI parameters */
49 0x00D75FFF, 0x000F000A,
50 0x00C30FFF, 0x00060006,
51 0x00AAAFFF, 0x001E0000,
52 0x00FFFFFF, 0x000F000A,
53 0x00D75FFF, 0x00160004,
54 0x00C30FFF, 0x001E0000,
55 0x00FFFFFF, 0x00060006,
56 0x00D75FFF, 0x001E0000,
6acab15a
PZ		 57};
58
59static const u32 hsw_ddi_translations_hdmi[] = {
60 /* Idx NT mV diff T mV diff db */
61 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */
62 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */
63 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */
64 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */
65 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */
66 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */
67 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */
68 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */
69 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */
70 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */
71 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */
72 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */
45244b87
ED		 73};
74
300644c7 75static const u32 bdw_ddi_translations_edp[] = {
e1b22732 76 0x00FFFFFF, 0x00000012, /* eDP parameters */
300644c7
PZ		 77 0x00EBAFFF, 0x00020011,
78 0x00C71FFF, 0x0006000F,
9576c27f 79 0x00AAAFFF, 0x000E000A,
300644c7
PZ		 80 0x00FFFFFF, 0x00020011,
81 0x00DB6FFF, 0x0005000F,
82 0x00BEEFFF, 0x000A000C,
83 0x00FFFFFF, 0x0005000F,
84 0x00DB6FFF, 0x000A000C,
300644c7
PZ		 85 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
86};
87
e58623cb
AR		 88static const u32 bdw_ddi_translations_dp[] = {
89 0x00FFFFFF, 0x0007000E, /* DP parameters */
90 0x00D75FFF, 0x000E000A,
91 0x00BEFFFF, 0x00140006,
9576c27f 92 0x80B2CFFF, 0x001B0002,
e58623cb
AR		 93 0x00FFFFFF, 0x000E000A,
94 0x00D75FFF, 0x00180004,
95 0x80CB2FFF, 0x001B0002,
96 0x00F7DFFF, 0x00180004,
97 0x80D75FFF, 0x001B0002,
e58623cb
AR		 98 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
99};
100
101static const u32 bdw_ddi_translations_fdi[] = {
102 0x00FFFFFF, 0x0001000E, /* FDI parameters */
103 0x00D75FFF, 0x0004000A,
104 0x00C30FFF, 0x00070006,
105 0x00AAAFFF, 0x000C0000,
106 0x00FFFFFF, 0x0004000A,
107 0x00D75FFF, 0x00090004,
108 0x00C30FFF, 0x000C0000,
109 0x00FFFFFF, 0x00070006,
110 0x00D75FFF, 0x000C0000,
111 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/
112};
113
20f4dbe4 114enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
fc914639 115{
0bdee30e 116 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 117 int type = intel_encoder->type;
118
174edf1f 119 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 120 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 121 struct intel_digital_port *intel_dig_port =
122 enc_to_dig_port(encoder);
123 return intel_dig_port->port;
0bdee30e 124
fc914639
PZ		 125 } else if (type == INTEL_OUTPUT_ANALOG) {
126 return PORT_E;
0bdee30e 127
fc914639
PZ		 128 } else {
129 DRM_ERROR("Invalid DDI encoder type %d\n", type);
130 BUG();
131 }
132}
133
e58623cb
AR		 134/*
135 * Starting with Haswell, DDI port buffers must be programmed with correct
136 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 137 * but the HDMI/DVI fields are shared among those. So we program the DDI
138 * in either FDI or DP modes only, as HDMI connections will work with both
139 * of those
140 */
ad8d270c 141static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
45244b87
ED		 142{
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 u32 reg;
145 int i;
6acab15a 146 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
e58623cb
AR		 147 const u32 *ddi_translations_fdi;
148 const u32 *ddi_translations_dp;
300644c7 149 const u32 *ddi_translations_edp;
e58623cb
AR		 150 const u32 *ddi_translations;
151
152 if (IS_BROADWELL(dev)) {
153 ddi_translations_fdi = bdw_ddi_translations_fdi;
154 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 155 ddi_translations_edp = bdw_ddi_translations_edp;
e58623cb
AR		 156 } else if (IS_HASWELL(dev)) {
157 ddi_translations_fdi = hsw_ddi_translations_fdi;
158 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 159 ddi_translations_edp = hsw_ddi_translations_dp;
e58623cb
AR		 160 } else {
161 WARN(1, "ddi translation table missing\n");
300644c7 162 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 163 ddi_translations_fdi = bdw_ddi_translations_fdi;
164 ddi_translations_dp = bdw_ddi_translations_dp;
165 }
166
300644c7
PZ		 167 switch (port) {
168 case PORT_A:
169 ddi_translations = ddi_translations_edp;
170 break;
171 case PORT_B:
172 case PORT_C:
300644c7
PZ		 173 ddi_translations = ddi_translations_dp;
174 break;
77d8d009 175 case PORT_D:
5d8a7752 176 if (intel_dp_is_edp(dev, PORT_D))
77d8d009
PZ		 177 ddi_translations = ddi_translations_edp;
178 else
179 ddi_translations = ddi_translations_dp;
180 break;
300644c7
PZ		 181 case PORT_E:
182 ddi_translations = ddi_translations_fdi;
183 break;
184 default:
185 BUG();
186 }
45244b87 187
f72d19f0
PZ		 188 for (i = 0, reg = DDI_BUF_TRANS(port);
189 i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
45244b87
ED		 190 I915_WRITE(reg, ddi_translations[i]);
191 reg += 4;
192 }
6acab15a
PZ		 193 /* Entry 9 is for HDMI: */
194 for (i = 0; i < 2; i++) {
195 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
196 reg += 4;
197 }
45244b87
ED		 198}
199
200/* Program DDI buffers translations for DP. By default, program ports A-D in DP
201 * mode and port E for FDI.
202 */
203void intel_prepare_ddi(struct drm_device *dev)
204{
205 int port;
206
0d536cb4
PZ		 207 if (!HAS_DDI(dev))
208 return;
45244b87 209
ad8d270c
PZ		 210 for (port = PORT_A; port <= PORT_E; port++)
211 intel_prepare_ddi_buffers(dev, port);
45244b87 212}
c82e4d26
ED		 213
214static const long hsw_ddi_buf_ctl_values[] = {
215 DDI_BUF_EMP_400MV_0DB_HSW,
216 DDI_BUF_EMP_400MV_3_5DB_HSW,
217 DDI_BUF_EMP_400MV_6DB_HSW,
218 DDI_BUF_EMP_400MV_9_5DB_HSW,
219 DDI_BUF_EMP_600MV_0DB_HSW,
220 DDI_BUF_EMP_600MV_3_5DB_HSW,
221 DDI_BUF_EMP_600MV_6DB_HSW,
222 DDI_BUF_EMP_800MV_0DB_HSW,
223 DDI_BUF_EMP_800MV_3_5DB_HSW
224};
225
248138b5
PZ		 226static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
227 enum port port)
228{
229 uint32_t reg = DDI_BUF_CTL(port);
230 int i;
231
232 for (i = 0; i < 8; i++) {
233 udelay(1);
234 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
235 return;
236 }
237 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
238}
c82e4d26
ED		 239
240/* Starting with Haswell, different DDI ports can work in FDI mode for
241 * connection to the PCH-located connectors. For this, it is necessary to train
242 * both the DDI port and PCH receiver for the desired DDI buffer settings.
243 *
244 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
245 * please note that when FDI mode is active on DDI E, it shares 2 lines with
246 * DDI A (which is used for eDP)
247 */
248
249void hsw_fdi_link_train(struct drm_crtc *crtc)
250{
251 struct drm_device *dev = crtc->dev;
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 254 u32 temp, i, rx_ctl_val;
c82e4d26 255
04945641
PZ		 256 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
257 * mode set "sequence for CRT port" document:
258 * - TP1 to TP2 time with the default value
259 * - FDI delay to 90h
8693a824
DL		 260 *
261 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 262 */
263 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
264 FDI_RX_PWRDN_LANE0_VAL(2) |
265 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
266
267 /* Enable the PCH Receiver FDI PLL */
3e68320e 268 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 269 FDI_RX_PLL_ENABLE |
627eb5a3 270 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
04945641
PZ		 271 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
272 POSTING_READ(_FDI_RXA_CTL);
273 udelay(220);
274
275 /* Switch from Rawclk to PCDclk */
276 rx_ctl_val |= FDI_PCDCLK;
277 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
278
279 /* Configure Port Clock Select */
280 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
281
282 /* Start the training iterating through available voltages and emphasis,
283 * testing each value twice. */
284 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
c82e4d26
ED		 285 /* Configure DP_TP_CTL with auto-training */
286 I915_WRITE(DP_TP_CTL(PORT_E),
287 DP_TP_CTL_FDI_AUTOTRAIN |
288 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
289 DP_TP_CTL_LINK_TRAIN_PAT1 |
290 DP_TP_CTL_ENABLE);
291
876a8cdf
DL		 292 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
293 * DDI E does not support port reversal, the functionality is
294 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
295 * port reversal bit */
c82e4d26 296 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 297 DDI_BUF_CTL_ENABLE |
33d29b14 298 ((intel_crtc->config.fdi_lanes - 1) << 1) |
04945641
PZ		 299 hsw_ddi_buf_ctl_values[i / 2]);
300 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 301
302 udelay(600);
303
04945641
PZ		 304 /* Program PCH FDI Receiver TU */
305 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
306
307 /* Enable PCH FDI Receiver with auto-training */
308 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
309 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
310 POSTING_READ(_FDI_RXA_CTL);
311
312 /* Wait for FDI receiver lane calibration */
313 udelay(30);
314
315 /* Unset FDI_RX_MISC pwrdn lanes */
316 temp = I915_READ(_FDI_RXA_MISC);
317 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
318 I915_WRITE(_FDI_RXA_MISC, temp);
319 POSTING_READ(_FDI_RXA_MISC);
320
321 /* Wait for FDI auto training time */
322 udelay(5);
c82e4d26
ED		 323
324 temp = I915_READ(DP_TP_STATUS(PORT_E));
325 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 326 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 327
328 /* Enable normal pixel sending for FDI */
329 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 330 DP_TP_CTL_FDI_AUTOTRAIN |
331 DP_TP_CTL_LINK_TRAIN_NORMAL |
332 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
333 DP_TP_CTL_ENABLE);
c82e4d26 334
04945641 335 return;
c82e4d26 336 }
04945641 337
248138b5
PZ		 338 temp = I915_READ(DDI_BUF_CTL(PORT_E));
339 temp &= ~DDI_BUF_CTL_ENABLE;
340 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
341 POSTING_READ(DDI_BUF_CTL(PORT_E));
342
04945641 343 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 344 temp = I915_READ(DP_TP_CTL(PORT_E));
345 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
346 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
347 I915_WRITE(DP_TP_CTL(PORT_E), temp);
348 POSTING_READ(DP_TP_CTL(PORT_E));
349
350 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 351
352 rx_ctl_val &= ~FDI_RX_ENABLE;
353 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 354 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 355
356 /* Reset FDI_RX_MISC pwrdn lanes */
357 temp = I915_READ(_FDI_RXA_MISC);
358 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
359 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
360 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 361 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 362 }
363
04945641 364 DRM_ERROR("FDI link training failed!\n");
c82e4d26 365}
0e72a5b5 366
8d9ddbcb
PZ		 367static struct intel_encoder *
368intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
369{
370 struct drm_device *dev = crtc->dev;
371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
372 struct intel_encoder *intel_encoder, *ret = NULL;
373 int num_encoders = 0;
374
375 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
376 ret = intel_encoder;
377 num_encoders++;
378 }
379
380 if (num_encoders != 1)
84f44ce7
VS		 381 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
382 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 383
384 BUG_ON(ret == NULL);
385 return ret;
386}
387
6441ab5f
PZ		 388void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
389{
390 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
391 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
393 uint32_t val;
394
395 switch (intel_crtc->ddi_pll_sel) {
396 case PORT_CLK_SEL_SPLL:
7ca1ac13
DV		 397 DRM_DEBUG_KMS("Disabling SPLL\n");
398 val = I915_READ(SPLL_CTL);
399 WARN_ON(!(val & SPLL_PLL_ENABLE));
400 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
401 POSTING_READ(SPLL_CTL);
6441ab5f
PZ		 402 break;
403 case PORT_CLK_SEL_WRPLL1:
404 plls->wrpll1_refcount--;
405 if (plls->wrpll1_refcount == 0) {
406 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
407 val = I915_READ(WRPLL_CTL1);
408 WARN_ON(!(val & WRPLL_PLL_ENABLE));
409 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
410 POSTING_READ(WRPLL_CTL1);
411 }
412 break;
413 case PORT_CLK_SEL_WRPLL2:
414 plls->wrpll2_refcount--;
415 if (plls->wrpll2_refcount == 0) {
416 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
417 val = I915_READ(WRPLL_CTL2);
418 WARN_ON(!(val & WRPLL_PLL_ENABLE));
419 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
420 POSTING_READ(WRPLL_CTL2);
421 }
422 break;
423 }
424
6441ab5f
PZ		 425 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
426 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
427
428 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
429}
430
1c0b85c5
DL		 431#define LC_FREQ 2700
432#define LC_FREQ_2K (LC_FREQ * 2000)
433
434#define P_MIN 2
435#define P_MAX 64
436#define P_INC 2
437
438/* Constraints for PLL good behavior */
439#define REF_MIN 48
440#define REF_MAX 400
441#define VCO_MIN 2400
442#define VCO_MAX 4800
443
444#define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
445
446struct wrpll_rnp {
447 unsigned p, n2, r2;
448};
449
450static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 451{
1c0b85c5
DL		 452 unsigned budget;
453
454 switch (clock) {
455 case 25175000:
456 case 25200000:
457 case 27000000:
458 case 27027000:
459 case 37762500:
460 case 37800000:
461 case 40500000:
462 case 40541000:
463 case 54000000:
464 case 54054000:
465 case 59341000:
466 case 59400000:
467 case 72000000:
468 case 74176000:
469 case 74250000:
470 case 81000000:
471 case 81081000:
472 case 89012000:
473 case 89100000:
474 case 108000000:
475 case 108108000:
476 case 111264000:
477 case 111375000:
478 case 148352000:
479 case 148500000:
480 case 162000000:
481 case 162162000:
482 case 222525000:
483 case 222750000:
484 case 296703000:
485 case 297000000:
486 budget = 0;
487 break;
488 case 233500000:
489 case 245250000:
490 case 247750000:
491 case 253250000:
492 case 298000000:
493 budget = 1500;
494 break;
495 case 169128000:
496 case 169500000:
497 case 179500000:
498 case 202000000:
499 budget = 2000;
500 break;
501 case 256250000:
502 case 262500000:
503 case 270000000:
504 case 272500000:
505 case 273750000:
506 case 280750000:
507 case 281250000:
508 case 286000000:
509 case 291750000:
510 budget = 4000;
511 break;
512 case 267250000:
513 case 268500000:
514 budget = 5000;
515 break;
516 default:
517 budget = 1000;
518 break;
519 }
6441ab5f 520
1c0b85c5
DL		 521 return budget;
522}
523
524static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
525 unsigned r2, unsigned n2, unsigned p,
526 struct wrpll_rnp *best)
527{
528 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 529
1c0b85c5
DL		 530 /* No best (r,n,p) yet */
531 if (best->p == 0) {
532 best->p = p;
533 best->n2 = n2;
534 best->r2 = r2;
535 return;
536 }
6441ab5f 537
1c0b85c5
DL		 538 /*
539 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
540 * freq2k.
541 *
542 * delta = 1e6 *
543 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
544 * freq2k;
545 *
546 * and we would like delta <= budget.
547 *
548 * If the discrepancy is above the PPM-based budget, always prefer to
549 * improve upon the previous solution. However, if you're within the
550 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
551 */
552 a = freq2k * budget * p * r2;
553 b = freq2k * budget * best->p * best->r2;
554 diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
555 diff_best = ABS_DIFF((freq2k * best->p * best->r2),
556 (LC_FREQ_2K * best->n2));
557 c = 1000000 * diff;
558 d = 1000000 * diff_best;
559
560 if (a < c && b < d) {
561 /* If both are above the budget, pick the closer */
562 if (best->p * best->r2 * diff < p * r2 * diff_best) {
563 best->p = p;
564 best->n2 = n2;
565 best->r2 = r2;
566 }
567 } else if (a >= c && b < d) {
568 /* If A is below the threshold but B is above it? Update. */
569 best->p = p;
570 best->n2 = n2;
571 best->r2 = r2;
572 } else if (a >= c && b >= d) {
573 /* Both are below the limit, so pick the higher n2/(r2*r2) */
574 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
575 best->p = p;
576 best->n2 = n2;
577 best->r2 = r2;
578 }
579 }
580 /* Otherwise a < c && b >= d, do nothing */
581}
582
11578553
JB		 583static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
584 int reg)
585{
586 int refclk = LC_FREQ;
587 int n, p, r;
588 u32 wrpll;
589
590 wrpll = I915_READ(reg);
591 switch (wrpll & SPLL_PLL_REF_MASK) {
592 case SPLL_PLL_SSC:
593 case SPLL_PLL_NON_SSC:
594 /*
595 * We could calculate spread here, but our checking
596 * code only cares about 5% accuracy, and spread is a max of
597 * 0.5% downspread.
598 */
599 refclk = 135;
600 break;
601 case SPLL_PLL_LCPLL:
602 refclk = LC_FREQ;
603 break;
604 default:
605 WARN(1, "bad wrpll refclk\n");
606 return 0;
607 }
608
609 r = wrpll & WRPLL_DIVIDER_REF_MASK;
610 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
611 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
612
20f0ec16
JB		 613 /* Convert to KHz, p & r have a fixed point portion */
614 return (refclk * n * 100) / (p * r);
11578553
JB		 615}
616
617static void intel_ddi_clock_get(struct intel_encoder *encoder,
618 struct intel_crtc_config *pipe_config)
619{
620 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
621 enum port port = intel_ddi_get_encoder_port(encoder);
622 int link_clock = 0;
623 u32 val, pll;
624
625 val = I915_READ(PORT_CLK_SEL(port));
626 switch (val & PORT_CLK_SEL_MASK) {
627 case PORT_CLK_SEL_LCPLL_810:
628 link_clock = 81000;
629 break;
630 case PORT_CLK_SEL_LCPLL_1350:
631 link_clock = 135000;
632 break;
633 case PORT_CLK_SEL_LCPLL_2700:
634 link_clock = 270000;
635 break;
636 case PORT_CLK_SEL_WRPLL1:
637 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
638 break;
639 case PORT_CLK_SEL_WRPLL2:
640 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
641 break;
642 case PORT_CLK_SEL_SPLL:
643 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
644 if (pll == SPLL_PLL_FREQ_810MHz)
645 link_clock = 81000;
646 else if (pll == SPLL_PLL_FREQ_1350MHz)
647 link_clock = 135000;
648 else if (pll == SPLL_PLL_FREQ_2700MHz)
649 link_clock = 270000;
650 else {
651 WARN(1, "bad spll freq\n");
652 return;
653 }
654 break;
655 default:
656 WARN(1, "bad port clock sel\n");
657 return;
658 }
659
660 pipe_config->port_clock = link_clock * 2;
661
662 if (pipe_config->has_pch_encoder)
663 pipe_config->adjusted_mode.crtc_clock =
664 intel_dotclock_calculate(pipe_config->port_clock,
665 &pipe_config->fdi_m_n);
666 else if (pipe_config->has_dp_encoder)
667 pipe_config->adjusted_mode.crtc_clock =
668 intel_dotclock_calculate(pipe_config->port_clock,
669 &pipe_config->dp_m_n);
670 else
671 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
672}
673
1c0b85c5
DL		 674static void
675intel_ddi_calculate_wrpll(int clock /* in Hz */,
676 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
677{
678 uint64_t freq2k;
679 unsigned p, n2, r2;
680 struct wrpll_rnp best = { 0, 0, 0 };
681 unsigned budget;
682
683 freq2k = clock / 100;
684
685 budget = wrpll_get_budget_for_freq(clock);
686
687 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
688 * and directly pass the LC PLL to it. */
689 if (freq2k == 5400000) {
690 *n2_out = 2;
691 *p_out = 1;
692 *r2_out = 2;
693 return;
694 }
695
696 /*
697 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
698 * the WR PLL.
699 *
700 * We want R so that REF_MIN <= Ref <= REF_MAX.
701 * Injecting R2 = 2 * R gives:
702 * REF_MAX * r2 > LC_FREQ * 2 and
703 * REF_MIN * r2 < LC_FREQ * 2
704 *
705 * Which means the desired boundaries for r2 are:
706 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
707 *
708 */
709 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
710 r2 <= LC_FREQ * 2 / REF_MIN;
711 r2++) {
712
713 /*
714 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
715 *
716 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
717 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
718 * VCO_MAX * r2 > n2 * LC_FREQ and
719 * VCO_MIN * r2 < n2 * LC_FREQ)
720 *
721 * Which means the desired boundaries for n2 are:
722 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
723 */
724 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
725 n2 <= VCO_MAX * r2 / LC_FREQ;
726 n2++) {
727
728 for (p = P_MIN; p <= P_MAX; p += P_INC)
729 wrpll_update_rnp(freq2k, budget,
730 r2, n2, p, &best);
731 }
732 }
6441ab5f 733
1c0b85c5
DL		 734 *n2_out = best.n2;
735 *p_out = best.p;
736 *r2_out = best.r2;
6441ab5f
PZ		 737}
738
566b734a
PZ		 739/*
740 * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and
741 * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to
742 * steal the selected PLL. You need to call intel_ddi_pll_enable to actually
743 * enable the PLL.
744 */
745bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
6441ab5f 746{
566b734a 747 struct drm_crtc *crtc = &intel_crtc->base;
6441ab5f 748 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
068759bd 749 struct drm_encoder *encoder = &intel_encoder->base;
6441ab5f
PZ		 750 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
751 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
752 int type = intel_encoder->type;
753 enum pipe pipe = intel_crtc->pipe;
ff9a6750 754 int clock = intel_crtc->config.port_clock;
6441ab5f 755
6441ab5f
PZ		 756 intel_ddi_put_crtc_pll(crtc);
757
068759bd
PZ		 758 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
759 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
760
761 switch (intel_dp->link_bw) {
762 case DP_LINK_BW_1_62:
763 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
764 break;
765 case DP_LINK_BW_2_7:
766 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
767 break;
768 case DP_LINK_BW_5_4:
769 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
770 break;
771 default:
772 DRM_ERROR("Link bandwidth %d unsupported\n",
773 intel_dp->link_bw);
774 return false;
775 }
776
068759bd 777 } else if (type == INTEL_OUTPUT_HDMI) {
566b734a 778 uint32_t reg, val;
1c0b85c5 779 unsigned p, n2, r2;
6441ab5f 780
0694001b
PZ		 781 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
782
783 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
784 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
785 WRPLL_DIVIDER_POST(p);
786
787 if (val == I915_READ(WRPLL_CTL1)) {
788 DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
789 pipe_name(pipe));
790 reg = WRPLL_CTL1;
791 } else if (val == I915_READ(WRPLL_CTL2)) {
792 DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
793 pipe_name(pipe));
794 reg = WRPLL_CTL2;
795 } else if (plls->wrpll1_refcount == 0) {
6441ab5f
PZ		 796 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
797 pipe_name(pipe));
6441ab5f 798 reg = WRPLL_CTL1;
6441ab5f
PZ		 799 } else if (plls->wrpll2_refcount == 0) {
800 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
801 pipe_name(pipe));
6441ab5f 802 reg = WRPLL_CTL2;
6441ab5f
PZ		 803 } else {
804 DRM_ERROR("No WRPLLs available!\n");
805 return false;
806 }
807
566b734a
PZ		 808 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
809 clock, p, n2, r2);
810
0694001b
PZ		 811 if (reg == WRPLL_CTL1) {
812 plls->wrpll1_refcount++;
813 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
814 } else {
815 plls->wrpll2_refcount++;
816 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
817 }
6441ab5f
PZ		 818
819 } else if (type == INTEL_OUTPUT_ANALOG) {
7ca1ac13
DV		 820 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
821 pipe_name(pipe));
822 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
6441ab5f
PZ		 823 } else {
824 WARN(1, "Invalid DDI encoder type %d\n", type);
825 return false;
826 }
827
6441ab5f
PZ		 828 return true;
829}
830
566b734a
PZ		 831/*
832 * To be called after intel_ddi_pll_select(). That one selects the PLL to be
833 * used, this one actually enables the PLL.
834 */
835void intel_ddi_pll_enable(struct intel_crtc *crtc)
836{
837 struct drm_device *dev = crtc->base.dev;
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
840 int clock = crtc->config.port_clock;
841 uint32_t reg, cur_val, new_val;
842 int refcount;
843 const char *pll_name;
844 uint32_t enable_bit = (1 << 31);
845 unsigned int p, n2, r2;
846
847 BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
848 BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
849
850 switch (crtc->ddi_pll_sel) {
851 case PORT_CLK_SEL_LCPLL_2700:
852 case PORT_CLK_SEL_LCPLL_1350:
853 case PORT_CLK_SEL_LCPLL_810:
854 /*
855 * LCPLL should always be enabled at this point of the mode set
856 * sequence, so nothing to do.
857 */
858 return;
859
860 case PORT_CLK_SEL_SPLL:
566b734a
PZ		 861 new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
862 SPLL_PLL_SSC;
7ca1ac13
DV		 863 WARN(I915_READ(SPLL_CTL) & enable_bit, "SPLL already enabled\n");
864 I915_WRITE(SPLL_CTL, new_val);
865 POSTING_READ(SPLL_CTL);
866 udelay(20);
867 return;
566b734a
PZ		 868 case PORT_CLK_SEL_WRPLL1:
869 case PORT_CLK_SEL_WRPLL2:
870 if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
871 pll_name = "WRPLL1";
872 reg = WRPLL_CTL1;
873 refcount = plls->wrpll1_refcount;
874 } else {
875 pll_name = "WRPLL2";
876 reg = WRPLL_CTL2;
877 refcount = plls->wrpll2_refcount;
878 }
879
880 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
881
882 new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
883 WRPLL_DIVIDER_REFERENCE(r2) |
884 WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p);
885
886 break;
887
888 case PORT_CLK_SEL_NONE:
889 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
890 return;
891 default:
892 WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel);
893 return;
894 }
895
896 cur_val = I915_READ(reg);
897
898 WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount);
899 if (refcount == 1) {
900 WARN(cur_val & enable_bit, "%s already enabled\n", pll_name);
901 I915_WRITE(reg, new_val);
902 POSTING_READ(reg);
903 udelay(20);
904 } else {
905 WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name);
906 }
907}
908
dae84799
PZ		 909void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
910{
911 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
913 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3b117c8f 914 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
dae84799
PZ		 915 int type = intel_encoder->type;
916 uint32_t temp;
917
918 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
919
c9809791 920 temp = TRANS_MSA_SYNC_CLK;
965e0c48 921 switch (intel_crtc->config.pipe_bpp) {
dae84799 922 case 18:
c9809791 923 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 924 break;
925 case 24:
c9809791 926 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 927 break;
928 case 30:
c9809791 929 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 930 break;
931 case 36:
c9809791 932 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 933 break;
934 default:
4e53c2e0 935 BUG();
dae84799 936 }
c9809791 937 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 938 }
939}
940
8228c251 941void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 942{
943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
944 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 945 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 946 struct drm_device *dev = crtc->dev;
947 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 948 enum pipe pipe = intel_crtc->pipe;
3b117c8f 949 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
174edf1f 950 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 951 int type = intel_encoder->type;
8d9ddbcb
PZ		 952 uint32_t temp;
953
ad80a810
PZ		 954 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
955 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 956 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 957
965e0c48 958 switch (intel_crtc->config.pipe_bpp) {
dfcef252 959 case 18:
ad80a810 960 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 961 break;
962 case 24:
ad80a810 963 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 964 break;
965 case 30:
ad80a810 966 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 967 break;
968 case 36:
ad80a810 969 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 970 break;
971 default:
4e53c2e0 972 BUG();
dfcef252 973 }
72662e10 974
a666283e 975 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 976 temp |= TRANS_DDI_PVSYNC;
a666283e 977 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 978 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 979
e6f0bfc4
PZ		 980 if (cpu_transcoder == TRANSCODER_EDP) {
981 switch (pipe) {
982 case PIPE_A:
c7670b10
PZ		 983 /* On Haswell, can only use the always-on power well for
984 * eDP when not using the panel fitter, and when not
985 * using motion blur mitigation (which we don't
986 * support). */
fabf6e51
DV		 987 if (IS_HASWELL(dev) &&
988 (intel_crtc->config.pch_pfit.enabled ||
989 intel_crtc->config.pch_pfit.force_thru))
d6dd9eb1
DV		 990 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
991 else
992 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 993 break;
994 case PIPE_B:
995 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
996 break;
997 case PIPE_C:
998 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
999 break;
1000 default:
1001 BUG();
1002 break;
1003 }
1004 }
1005
7739c33b 1006 if (type == INTEL_OUTPUT_HDMI) {
6897b4b5 1007 if (intel_crtc->config.has_hdmi_sink)
ad80a810 1008 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1009 else
ad80a810 1010 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1011
7739c33b 1012 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1013 temp |= TRANS_DDI_MODE_SELECT_FDI;
33d29b14 1014 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
7739c33b
PZ		 1015
1016 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1017 type == INTEL_OUTPUT_EDP) {
1018 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1019
ad80a810 1020 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1021
17aa6be9 1022 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1023 } else {
84f44ce7
VS		 1024 WARN(1, "Invalid encoder type %d for pipe %c\n",
1025 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1026 }
1027
ad80a810 1028 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1029}
72662e10 1030
ad80a810
PZ		 1031void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1032 enum transcoder cpu_transcoder)
8d9ddbcb 1033{
ad80a810 1034 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1035 uint32_t val = I915_READ(reg);
1036
ad80a810
PZ		 1037 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1038 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1039 I915_WRITE(reg, val);
72662e10
ED		 1040}
1041
bcbc889b
PZ		 1042bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1043{
1044 struct drm_device *dev = intel_connector->base.dev;
1045 struct drm_i915_private *dev_priv = dev->dev_private;
1046 struct intel_encoder *intel_encoder = intel_connector->encoder;
1047 int type = intel_connector->base.connector_type;
1048 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1049 enum pipe pipe = 0;
1050 enum transcoder cpu_transcoder;
882244a3 1051 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1052 uint32_t tmp;
1053
882244a3
PZ		 1054 power_domain = intel_display_port_power_domain(intel_encoder);
1055 if (!intel_display_power_enabled(dev_priv, power_domain))
1056 return false;
1057
bcbc889b
PZ		 1058 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1059 return false;
1060
1061 if (port == PORT_A)
1062 cpu_transcoder = TRANSCODER_EDP;
1063 else
1a240d4d 1064 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1065
1066 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1067
1068 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1069 case TRANS_DDI_MODE_SELECT_HDMI:
1070 case TRANS_DDI_MODE_SELECT_DVI:
1071 return (type == DRM_MODE_CONNECTOR_HDMIA);
1072
1073 case TRANS_DDI_MODE_SELECT_DP_SST:
1074 if (type == DRM_MODE_CONNECTOR_eDP)
1075 return true;
1076 case TRANS_DDI_MODE_SELECT_DP_MST:
1077 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1078
1079 case TRANS_DDI_MODE_SELECT_FDI:
1080 return (type == DRM_MODE_CONNECTOR_VGA);
1081
1082 default:
1083 return false;
1084 }
1085}
1086
85234cdc
DV		 1087bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1088 enum pipe *pipe)
1089{
1090 struct drm_device *dev = encoder->base.dev;
1091 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1092 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1093 enum intel_display_power_domain power_domain;
85234cdc
DV		 1094 u32 tmp;
1095 int i;
1096
6d129bea
ID		 1097 power_domain = intel_display_port_power_domain(encoder);
1098 if (!intel_display_power_enabled(dev_priv, power_domain))
1099 return false;
1100
fe43d3f5 1101 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1102
1103 if (!(tmp & DDI_BUF_CTL_ENABLE))
1104 return false;
1105
ad80a810
PZ		 1106 if (port == PORT_A) {
1107 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1108
ad80a810
PZ		 1109 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1110 case TRANS_DDI_EDP_INPUT_A_ON:
1111 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1112 *pipe = PIPE_A;
1113 break;
1114 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1115 *pipe = PIPE_B;
1116 break;
1117 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1118 *pipe = PIPE_C;
1119 break;
1120 }
1121
1122 return true;
1123 } else {
1124 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1125 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1126
1127 if ((tmp & TRANS_DDI_PORT_MASK)
1128 == TRANS_DDI_SELECT_PORT(port)) {
1129 *pipe = i;
1130 return true;
1131 }
85234cdc
DV		 1132 }
1133 }
1134
84f44ce7 1135 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1136
22f9fe50 1137 return false;
85234cdc
DV		 1138}
1139
6441ab5f
PZ		 1140static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1141 enum pipe pipe)
1142{
1143 uint32_t temp, ret;
a42f704b 1144 enum port port = I915_MAX_PORTS;
ad80a810
PZ		 1145 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1146 pipe);
6441ab5f
PZ		 1147 int i;
1148
ad80a810
PZ		 1149 if (cpu_transcoder == TRANSCODER_EDP) {
1150 port = PORT_A;
1151 } else {
1152 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1153 temp &= TRANS_DDI_PORT_MASK;
1154
1155 for (i = PORT_B; i <= PORT_E; i++)
1156 if (temp == TRANS_DDI_SELECT_PORT(i))
1157 port = i;
1158 }
6441ab5f 1159
a42f704b
DL		 1160 if (port == I915_MAX_PORTS) {
1161 WARN(1, "Pipe %c enabled on an unknown port\n",
1162 pipe_name(pipe));
1163 ret = PORT_CLK_SEL_NONE;
1164 } else {
1165 ret = I915_READ(PORT_CLK_SEL(port));
1166 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1167 "0x%08x\n", pipe_name(pipe), port_name(port),
1168 ret);
1169 }
6441ab5f
PZ		 1170
1171 return ret;
1172}
1173
1174void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1175{
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 enum pipe pipe;
1178 struct intel_crtc *intel_crtc;
1179
0882dae9
PZ		 1180 dev_priv->ddi_plls.wrpll1_refcount = 0;
1181 dev_priv->ddi_plls.wrpll2_refcount = 0;
1182
6441ab5f
PZ		 1183 for_each_pipe(pipe) {
1184 intel_crtc =
1185 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1186
0882dae9
PZ		 1187 if (!intel_crtc->active) {
1188 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
6441ab5f 1189 continue;
0882dae9 1190 }
6441ab5f
PZ		 1191
1192 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1193 pipe);
1194
1195 switch (intel_crtc->ddi_pll_sel) {
6441ab5f
PZ		 1196 case PORT_CLK_SEL_WRPLL1:
1197 dev_priv->ddi_plls.wrpll1_refcount++;
1198 break;
1199 case PORT_CLK_SEL_WRPLL2:
1200 dev_priv->ddi_plls.wrpll2_refcount++;
1201 break;
1202 }
1203 }
1204}
1205
fc914639
PZ		 1206void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1207{
1208 struct drm_crtc *crtc = &intel_crtc->base;
1209 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1210 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1211 enum port port = intel_ddi_get_encoder_port(intel_encoder);
3b117c8f 1212 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1213
bb523fc0
PZ		 1214 if (cpu_transcoder != TRANSCODER_EDP)
1215 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1216 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1217}
1218
1219void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1220{
1221 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3b117c8f 1222 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
fc914639 1223
bb523fc0
PZ		 1224 if (cpu_transcoder != TRANSCODER_EDP)
1225 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1226 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1227}
1228
00c09d70 1229static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1230{
c19b0669 1231 struct drm_encoder *encoder = &intel_encoder->base;
c19b0669 1232 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
30cf6db8 1233 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1234 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1235 int type = intel_encoder->type;
6441ab5f 1236
30cf6db8
DV		 1237 if (crtc->config.has_audio) {
1238 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1239 pipe_name(crtc->pipe));
1240
1241 /* write eld */
1242 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1243 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1244 }
1245
82a4d9c0
PZ		 1246 if (type == INTEL_OUTPUT_EDP) {
1247 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1248 intel_edp_panel_on(intel_dp);
82a4d9c0 1249 }
6441ab5f 1250
30cf6db8
DV		 1251 WARN_ON(crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1252 I915_WRITE(PORT_CLK_SEL(port), crtc->ddi_pll_sel);
c19b0669 1253
82a4d9c0 1254 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1255 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8
DV		 1256 struct intel_digital_port *intel_dig_port =
1257 enc_to_dig_port(encoder);
1258
1259 intel_dp->DP = intel_dig_port->saved_port_bits |
1260 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
1261 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
c19b0669
PZ		 1262
1263 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1264 intel_dp_start_link_train(intel_dp);
1265 intel_dp_complete_link_train(intel_dp);
3ab9c637
ID		 1266 if (port != PORT_A)
1267 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1268 } else if (type == INTEL_OUTPUT_HDMI) {
1269 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1270
1271 intel_hdmi->set_infoframes(encoder,
1272 crtc->config.has_hdmi_sink,
1273 &crtc->config.adjusted_mode);
c19b0669 1274 }
6441ab5f
PZ		 1275}
1276
00c09d70 1277static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1278{
1279 struct drm_encoder *encoder = &intel_encoder->base;
1280 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1281 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1282 int type = intel_encoder->type;
2886e93f 1283 uint32_t val;
a836bdf9 1284 bool wait = false;
2886e93f
PZ		 1285
1286 val = I915_READ(DDI_BUF_CTL(port));
1287 if (val & DDI_BUF_CTL_ENABLE) {
1288 val &= ~DDI_BUF_CTL_ENABLE;
1289 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1290 wait = true;
2886e93f 1291 }
6441ab5f 1292
a836bdf9
PZ		 1293 val = I915_READ(DP_TP_CTL(port));
1294 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1295 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1296 I915_WRITE(DP_TP_CTL(port), val);
1297
1298 if (wait)
1299 intel_wait_ddi_buf_idle(dev_priv, port);
1300
76bb80ed 1301 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1302 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1303 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1304 intel_edp_panel_vdd_on(intel_dp);
4be73780 1305 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1306 }
1307
6441ab5f
PZ		 1308 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1309}
1310
00c09d70 1311static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1312{
6547fef8 1313 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1314 struct drm_crtc *crtc = encoder->crtc;
1315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1316 int pipe = intel_crtc->pipe;
6547fef8 1317 struct drm_device *dev = encoder->dev;
72662e10 1318 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1319 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1320 int type = intel_encoder->type;
7b9f35a6 1321 uint32_t tmp;
72662e10 1322
6547fef8 1323 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1324 struct intel_digital_port *intel_dig_port =
1325 enc_to_dig_port(encoder);
1326
6547fef8
PZ		 1327 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1328 * are ignored so nothing special needs to be done besides
1329 * enabling the port.
1330 */
876a8cdf 1331 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1332 intel_dig_port->saved_port_bits |
1333 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1334 } else if (type == INTEL_OUTPUT_EDP) {
1335 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1336
3ab9c637
ID		 1337 if (port == PORT_A)
1338 intel_dp_stop_link_train(intel_dp);
1339
4be73780 1340 intel_edp_backlight_on(intel_dp);
4906557e 1341 intel_edp_psr_enable(intel_dp);
6547fef8 1342 }
7b9f35a6 1343
9ed109a7 1344 if (intel_crtc->config.has_audio) {
d45a0bf5 1345 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
7b9f35a6
WX		 1346 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1347 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1348 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1349 }
5ab432ef
DV		 1350}
1351
00c09d70 1352static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1353{
d6c50ff8 1354 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1355 struct drm_crtc *crtc = encoder->crtc;
1356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1357 int pipe = intel_crtc->pipe;
d6c50ff8 1358 int type = intel_encoder->type;
7b9f35a6
WX		 1359 struct drm_device *dev = encoder->dev;
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 uint32_t tmp;
d6c50ff8 1362
d45a0bf5
PZ		 1363 /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1364 * register is part of the power well on Haswell. */
1365 if (intel_crtc->config.has_audio) {
1366 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1367 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1368 (pipe * 4));
1369 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1370 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1371 }
2831d842 1372
d6c50ff8
PZ		 1373 if (type == INTEL_OUTPUT_EDP) {
1374 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1375
4906557e 1376 intel_edp_psr_disable(intel_dp);
4be73780 1377 intel_edp_backlight_off(intel_dp);
d6c50ff8 1378 }
72662e10 1379}
79f689aa 1380
b8fc2f6a 1381int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa 1382{
e39bf98a 1383 struct drm_device *dev = dev_priv->dev;
a4006641 1384 uint32_t lcpll = I915_READ(LCPLL_CTL);
e39bf98a 1385 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
a4006641 1386
e39bf98a 1387 if (lcpll & LCPLL_CD_SOURCE_FCLK) {
a4006641 1388 return 800000;
e3589908 1389 } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
b2b877ff 1390 return 450000;
e39bf98a 1391 } else if (freq == LCPLL_CLK_FREQ_450) {
b2b877ff 1392 return 450000;
e39bf98a
PZ		 1393 } else if (IS_HASWELL(dev)) {
1394 if (IS_ULT(dev))
1395 return 337500;
1396 else
1397 return 540000;
1398 } else {
1399 if (freq == LCPLL_CLK_FREQ_54O_BDW)
1400 return 540000;
1401 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1402 return 337500;
1403 else
1404 return 675000;
1405 }
79f689aa
PZ		 1406}
1407
1408void intel_ddi_pll_init(struct drm_device *dev)
1409{
1410 struct drm_i915_private *dev_priv = dev->dev_private;
1411 uint32_t val = I915_READ(LCPLL_CTL);
1412
1413 /* The LCPLL register should be turned on by the BIOS. For now let's
1414 * just check its state and print errors in case something is wrong.
1415 * Don't even try to turn it on.
1416 */
1417
b2b877ff 1418 DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
79f689aa
PZ		 1419 intel_ddi_get_cdclk_freq(dev_priv));
1420
1421 if (val & LCPLL_CD_SOURCE_FCLK)
1422 DRM_ERROR("CDCLK source is not LCPLL\n");
1423
1424 if (val & LCPLL_PLL_DISABLE)
1425 DRM_ERROR("LCPLL is disabled\n");
1426}
c19b0669
PZ		 1427
1428void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1429{
174edf1f
PZ		 1430 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1431 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1432 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1433 enum port port = intel_dig_port->port;
c19b0669 1434 uint32_t val;
f3e227df 1435 bool wait = false;
c19b0669
PZ		 1436
1437 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1438 val = I915_READ(DDI_BUF_CTL(port));
1439 if (val & DDI_BUF_CTL_ENABLE) {
1440 val &= ~DDI_BUF_CTL_ENABLE;
1441 I915_WRITE(DDI_BUF_CTL(port), val);
1442 wait = true;
1443 }
1444
1445 val = I915_READ(DP_TP_CTL(port));
1446 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1447 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1448 I915_WRITE(DP_TP_CTL(port), val);
1449 POSTING_READ(DP_TP_CTL(port));
1450
1451 if (wait)
1452 intel_wait_ddi_buf_idle(dev_priv, port);
1453 }
1454
1455 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1456 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
6aba5b6c 1457 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
c19b0669
PZ		 1458 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1459 I915_WRITE(DP_TP_CTL(port), val);
1460 POSTING_READ(DP_TP_CTL(port));
1461
1462 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1463 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1464 POSTING_READ(DDI_BUF_CTL(port));
1465
1466 udelay(600);
1467}
00c09d70 1468
1ad960f2
PZ		 1469void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1470{
1471 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1472 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1473 uint32_t val;
1474
1475 intel_ddi_post_disable(intel_encoder);
1476
1477 val = I915_READ(_FDI_RXA_CTL);
1478 val &= ~FDI_RX_ENABLE;
1479 I915_WRITE(_FDI_RXA_CTL, val);
1480
1481 val = I915_READ(_FDI_RXA_MISC);
1482 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1483 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1484 I915_WRITE(_FDI_RXA_MISC, val);
1485
1486 val = I915_READ(_FDI_RXA_CTL);
1487 val &= ~FDI_PCDCLK;
1488 I915_WRITE(_FDI_RXA_CTL, val);
1489
1490 val = I915_READ(_FDI_RXA_CTL);
1491 val &= ~FDI_RX_PLL_ENABLE;
1492 I915_WRITE(_FDI_RXA_CTL, val);
1493}
1494
00c09d70
PZ		 1495static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1496{
1497 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1498 int type = intel_encoder->type;
1499
1500 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1501 intel_dp_check_link_status(intel_dp);
1502}
1503
6801c18c
VS		 1504void intel_ddi_get_config(struct intel_encoder *encoder,
1505 struct intel_crtc_config *pipe_config)
045ac3b5
JB		 1506{
1507 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1508 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1509 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1510 u32 temp, flags = 0;
1511
1512 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1513 if (temp & TRANS_DDI_PHSYNC)
1514 flags |= DRM_MODE_FLAG_PHSYNC;
1515 else
1516 flags |= DRM_MODE_FLAG_NHSYNC;
1517 if (temp & TRANS_DDI_PVSYNC)
1518 flags |= DRM_MODE_FLAG_PVSYNC;
1519 else
1520 flags |= DRM_MODE_FLAG_NVSYNC;
1521
1522 pipe_config->adjusted_mode.flags |= flags;
42571aef
VS		 1523
1524 switch (temp & TRANS_DDI_BPC_MASK) {
1525 case TRANS_DDI_BPC_6:
1526 pipe_config->pipe_bpp = 18;
1527 break;
1528 case TRANS_DDI_BPC_8:
1529 pipe_config->pipe_bpp = 24;
1530 break;
1531 case TRANS_DDI_BPC_10:
1532 pipe_config->pipe_bpp = 30;
1533 break;
1534 case TRANS_DDI_BPC_12:
1535 pipe_config->pipe_bpp = 36;
1536 break;
1537 default:
1538 break;
1539 }
eb14cb74
VS		 1540
1541 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1542 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 1543 pipe_config->has_hdmi_sink = true;
eb14cb74
VS		 1544 case TRANS_DDI_MODE_SELECT_DVI:
1545 case TRANS_DDI_MODE_SELECT_FDI:
1546 break;
1547 case TRANS_DDI_MODE_SELECT_DP_SST:
1548 case TRANS_DDI_MODE_SELECT_DP_MST:
1549 pipe_config->has_dp_encoder = true;
1550 intel_dp_get_m_n(intel_crtc, pipe_config);
1551 break;
1552 default:
1553 break;
1554 }
10214420 1555
a60551b1
PZ		 1556 if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1557 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1558 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1559 pipe_config->has_audio = true;
1560 }
9ed109a7 1561
10214420
DV		 1562 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1563 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1564 /*
1565 * This is a big fat ugly hack.
1566 *
1567 * Some machines in UEFI boot mode provide us a VBT that has 18
1568 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1569 * unknown we fail to light up. Yet the same BIOS boots up with
1570 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1571 * max, not what it tells us to use.
1572 *
1573 * Note: This will still be broken if the eDP panel is not lit
1574 * up by the BIOS, and thus we can't get the mode at module
1575 * load.
1576 */
1577 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1578 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1579 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1580 }
11578553
JB		 1581
1582 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 1583}
1584
00c09d70
PZ		 1585static void intel_ddi_destroy(struct drm_encoder *encoder)
1586{
1587 /* HDMI has nothing special to destroy, so we can go with this. */
1588 intel_dp_encoder_destroy(encoder);
1589}
1590
5bfe2ac0
DV		 1591static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1592 struct intel_crtc_config *pipe_config)
00c09d70 1593{
5bfe2ac0 1594 int type = encoder->type;
eccb140b 1595 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 1596
5bfe2ac0 1597 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 1598
eccb140b
DV		 1599 if (port == PORT_A)
1600 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1601
00c09d70 1602 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 1603 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 1604 else
5bfe2ac0 1605 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 1606}
1607
1608static const struct drm_encoder_funcs intel_ddi_funcs = {
1609 .destroy = intel_ddi_destroy,
1610};
1611
4a28ae58
PZ		 1612static struct intel_connector *
1613intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1614{
1615 struct intel_connector *connector;
1616 enum port port = intel_dig_port->port;
1617
1618 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1619 if (!connector)
1620 return NULL;
1621
1622 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1623 if (!intel_dp_init_connector(intel_dig_port, connector)) {
1624 kfree(connector);
1625 return NULL;
1626 }
1627
1628 return connector;
1629}
1630
1631static struct intel_connector *
1632intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1633{
1634 struct intel_connector *connector;
1635 enum port port = intel_dig_port->port;
1636
1637 connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1638 if (!connector)
1639 return NULL;
1640
1641 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1642 intel_hdmi_init_connector(intel_dig_port, connector);
1643
1644 return connector;
1645}
1646
00c09d70
PZ		 1647void intel_ddi_init(struct drm_device *dev, enum port port)
1648{
876a8cdf 1649 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 1650 struct intel_digital_port *intel_dig_port;
1651 struct intel_encoder *intel_encoder;
1652 struct drm_encoder *encoder;
1653 struct intel_connector *hdmi_connector = NULL;
1654 struct intel_connector *dp_connector = NULL;
311a2094
PZ		 1655 bool init_hdmi, init_dp;
1656
1657 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1658 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1659 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1660 if (!init_dp && !init_hdmi) {
1661 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1662 port_name(port));
1663 init_hdmi = true;
1664 init_dp = true;
1665 }
00c09d70 1666
b14c5679 1667 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 1668 if (!intel_dig_port)
1669 return;
1670
00c09d70
PZ		 1671 intel_encoder = &intel_dig_port->base;
1672 encoder = &intel_encoder->base;
1673
1674 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1675 DRM_MODE_ENCODER_TMDS);
00c09d70 1676
5bfe2ac0 1677 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 1678 intel_encoder->enable = intel_enable_ddi;
1679 intel_encoder->pre_enable = intel_ddi_pre_enable;
1680 intel_encoder->disable = intel_disable_ddi;
1681 intel_encoder->post_disable = intel_ddi_post_disable;
1682 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 1683 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 1684
1685 intel_dig_port->port = port;
bcf53de4
SM		 1686 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1687 (DDI_BUF_PORT_REVERSAL |
1688 DDI_A_4_LANES);
00c09d70
PZ		 1689
1690 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1691 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 1692 intel_encoder->cloneable = 0;
00c09d70
PZ		 1693 intel_encoder->hot_plug = intel_ddi_hot_plug;
1694
13cf5504
DA		 1695 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1696 dev_priv->hpd_irq_port[port] = intel_dig_port;
1697
4a28ae58
PZ		 1698 if (init_dp)
1699 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
21a8e6a4 1700
311a2094
PZ		 1701 /* In theory we don't need the encoder->type check, but leave it just in
1702 * case we have some really bad VBTs... */
4a28ae58
PZ		 1703 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
1704 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
21a8e6a4 1705
4a28ae58
PZ		 1706 if (!dp_connector && !hdmi_connector) {
1707 drm_encoder_cleanup(encoder);
1708 kfree(intel_dig_port);
21a8e6a4 1709 }
00c09d70 1710}
Linux 6.x block layer and io_uring tree(s)