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drm/i915: check the power down well on assert_pipe()
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
31/* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
34 */
35static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
46};
47
48static const u32 hsw_ddi_translations_fdi[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
59};
60
fc914639
PZ		 61static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
62{
0bdee30e 63 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 64 int type = intel_encoder->type;
65
174edf1f 66 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 67 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
174edf1f
PZ		 68 struct intel_digital_port *intel_dig_port =
69 enc_to_dig_port(encoder);
70 return intel_dig_port->port;
0bdee30e 71
fc914639
PZ		 72 } else if (type == INTEL_OUTPUT_ANALOG) {
73 return PORT_E;
0bdee30e 74
fc914639
PZ		 75 } else {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type);
77 BUG();
78 }
79}
80
45244b87
ED		 81/* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
85 * of those
86 */
c1f63f9d
PZ		 87static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
88 bool use_fdi_mode)
45244b87
ED		 89{
90 struct drm_i915_private *dev_priv = dev->dev_private;
91 u32 reg;
92 int i;
93 const u32 *ddi_translations = ((use_fdi_mode) ?
94 hsw_ddi_translations_fdi :
95 hsw_ddi_translations_dp);
96
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
98 port_name(port),
99 use_fdi_mode ? "FDI" : "DP");
100
101 WARN((use_fdi_mode && (port != PORT_E)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
103 port_name(port));
104
105 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
106 I915_WRITE(reg, ddi_translations[i]);
107 reg += 4;
108 }
109}
110
111/* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
113 */
114void intel_prepare_ddi(struct drm_device *dev)
115{
116 int port;
117
0d536cb4
PZ		 118 if (!HAS_DDI(dev))
119 return;
45244b87 120
0d536cb4
PZ		 121 for (port = PORT_A; port < PORT_E; port++)
122 intel_prepare_ddi_buffers(dev, port, false);
123
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
127 */
128 intel_prepare_ddi_buffers(dev, PORT_E, true);
45244b87 129}
c82e4d26
ED		 130
131static const long hsw_ddi_buf_ctl_values[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW,
133 DDI_BUF_EMP_400MV_3_5DB_HSW,
134 DDI_BUF_EMP_400MV_6DB_HSW,
135 DDI_BUF_EMP_400MV_9_5DB_HSW,
136 DDI_BUF_EMP_600MV_0DB_HSW,
137 DDI_BUF_EMP_600MV_3_5DB_HSW,
138 DDI_BUF_EMP_600MV_6DB_HSW,
139 DDI_BUF_EMP_800MV_0DB_HSW,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
141};
142
248138b5
PZ		 143static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
144 enum port port)
145{
146 uint32_t reg = DDI_BUF_CTL(port);
147 int i;
148
149 for (i = 0; i < 8; i++) {
150 udelay(1);
151 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
152 return;
153 }
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
155}
c82e4d26
ED		 156
157/* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
160 *
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
164 */
165
166void hsw_fdi_link_train(struct drm_crtc *crtc)
167{
168 struct drm_device *dev = crtc->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 171 u32 temp, i, rx_ctl_val;
c82e4d26 172
04945641
PZ		 173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
176 * - FDI delay to 90h
177 */
178 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
179 FDI_RX_PWRDN_LANE0_VAL(2) |
180 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
181
182 /* Enable the PCH Receiver FDI PLL */
183 rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
184 ((intel_crtc->fdi_lanes - 1) << 19);
68d18ad7
PZ		 185 if (dev_priv->fdi_rx_polarity_reversed)
186 rx_ctl_val |= FDI_RX_POLARITY_REVERSED_LPT;
04945641
PZ		 187 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
188 POSTING_READ(_FDI_RXA_CTL);
189 udelay(220);
190
191 /* Switch from Rawclk to PCDclk */
192 rx_ctl_val |= FDI_PCDCLK;
193 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
194
195 /* Configure Port Clock Select */
196 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
197
198 /* Start the training iterating through available voltages and emphasis,
199 * testing each value twice. */
200 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
c82e4d26
ED		 201 /* Configure DP_TP_CTL with auto-training */
202 I915_WRITE(DP_TP_CTL(PORT_E),
203 DP_TP_CTL_FDI_AUTOTRAIN |
204 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
205 DP_TP_CTL_LINK_TRAIN_PAT1 |
206 DP_TP_CTL_ENABLE);
207
208 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
c82e4d26 209 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641
PZ		 210 DDI_BUF_CTL_ENABLE |
211 ((intel_crtc->fdi_lanes - 1) << 1) |
212 hsw_ddi_buf_ctl_values[i / 2]);
213 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 214
215 udelay(600);
216
04945641
PZ		 217 /* Program PCH FDI Receiver TU */
218 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
219
220 /* Enable PCH FDI Receiver with auto-training */
221 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
222 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
223 POSTING_READ(_FDI_RXA_CTL);
224
225 /* Wait for FDI receiver lane calibration */
226 udelay(30);
227
228 /* Unset FDI_RX_MISC pwrdn lanes */
229 temp = I915_READ(_FDI_RXA_MISC);
230 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
231 I915_WRITE(_FDI_RXA_MISC, temp);
232 POSTING_READ(_FDI_RXA_MISC);
233
234 /* Wait for FDI auto training time */
235 udelay(5);
c82e4d26
ED		 236
237 temp = I915_READ(DP_TP_STATUS(PORT_E));
238 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 239 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 240
241 /* Enable normal pixel sending for FDI */
242 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 243 DP_TP_CTL_FDI_AUTOTRAIN |
244 DP_TP_CTL_LINK_TRAIN_NORMAL |
245 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
246 DP_TP_CTL_ENABLE);
c82e4d26 247
04945641 248 return;
c82e4d26 249 }
04945641 250
248138b5
PZ		 251 temp = I915_READ(DDI_BUF_CTL(PORT_E));
252 temp &= ~DDI_BUF_CTL_ENABLE;
253 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
254 POSTING_READ(DDI_BUF_CTL(PORT_E));
255
04945641 256 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 257 temp = I915_READ(DP_TP_CTL(PORT_E));
258 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
259 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
260 I915_WRITE(DP_TP_CTL(PORT_E), temp);
261 POSTING_READ(DP_TP_CTL(PORT_E));
262
263 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 264
265 rx_ctl_val &= ~FDI_RX_ENABLE;
266 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 267 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 268
269 /* Reset FDI_RX_MISC pwrdn lanes */
270 temp = I915_READ(_FDI_RXA_MISC);
271 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
272 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
273 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 274 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 275 }
276
04945641 277 DRM_ERROR("FDI link training failed!\n");
c82e4d26 278}
0e72a5b5 279
12a13a33
ED		 280/* WRPLL clock dividers */
281struct wrpll_tmds_clock {
282 u32 clock;
283 u16 p; /* Post divider */
284 u16 n2; /* Feedback divider */
285 u16 r2; /* Reference divider */
286};
287
126e9be8
PZ		 288/* Table of matching values for WRPLL clocks programming for each frequency.
289 * The code assumes this table is sorted. */
12a13a33
ED		 290static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
291 {19750, 38, 25, 18},
292 {20000, 48, 32, 18},
293 {21000, 36, 21, 15},
294 {21912, 42, 29, 17},
295 {22000, 36, 22, 15},
296 {23000, 36, 23, 15},
297 {23500, 40, 40, 23},
298 {23750, 26, 16, 14},
12a13a33
ED		 299 {24000, 36, 24, 15},
300 {25000, 36, 25, 15},
301 {25175, 26, 40, 33},
302 {25200, 30, 21, 15},
303 {26000, 36, 26, 15},
304 {27000, 30, 21, 14},
305 {27027, 18, 100, 111},
306 {27500, 30, 29, 19},
307 {28000, 34, 30, 17},
308 {28320, 26, 30, 22},
309 {28322, 32, 42, 25},
310 {28750, 24, 23, 18},
311 {29000, 30, 29, 18},
312 {29750, 32, 30, 17},
313 {30000, 30, 25, 15},
314 {30750, 30, 41, 24},
315 {31000, 30, 31, 18},
316 {31500, 30, 28, 16},
317 {32000, 30, 32, 18},
318 {32500, 28, 32, 19},
319 {33000, 24, 22, 15},
320 {34000, 28, 30, 17},
321 {35000, 26, 32, 19},
322 {35500, 24, 30, 19},
323 {36000, 26, 26, 15},
324 {36750, 26, 46, 26},
325 {37000, 24, 23, 14},
326 {37762, 22, 40, 26},
327 {37800, 20, 21, 15},
328 {38000, 24, 27, 16},
329 {38250, 24, 34, 20},
330 {39000, 24, 26, 15},
331 {40000, 24, 32, 18},
332 {40500, 20, 21, 14},
333 {40541, 22, 147, 89},
334 {40750, 18, 19, 14},
335 {41000, 16, 17, 14},
336 {41500, 22, 44, 26},
337 {41540, 22, 44, 26},
338 {42000, 18, 21, 15},
339 {42500, 22, 45, 26},
340 {43000, 20, 43, 27},
341 {43163, 20, 24, 15},
342 {44000, 18, 22, 15},
343 {44900, 20, 108, 65},
344 {45000, 20, 25, 15},
345 {45250, 20, 52, 31},
346 {46000, 18, 23, 15},
347 {46750, 20, 45, 26},
348 {47000, 20, 40, 23},
349 {48000, 18, 24, 15},
350 {49000, 18, 49, 30},
351 {49500, 16, 22, 15},
352 {50000, 18, 25, 15},
353 {50500, 18, 32, 19},
354 {51000, 18, 34, 20},
355 {52000, 18, 26, 15},
356 {52406, 14, 34, 25},
357 {53000, 16, 22, 14},
358 {54000, 16, 24, 15},
359 {54054, 16, 173, 108},
360 {54500, 14, 24, 17},
361 {55000, 12, 22, 18},
362 {56000, 14, 45, 31},
363 {56250, 16, 25, 15},
364 {56750, 14, 25, 17},
365 {57000, 16, 27, 16},
366 {58000, 16, 43, 25},
367 {58250, 16, 38, 22},
368 {58750, 16, 40, 23},
369 {59000, 14, 26, 17},
370 {59341, 14, 40, 26},
371 {59400, 16, 44, 25},
372 {60000, 16, 32, 18},
373 {60500, 12, 39, 29},
374 {61000, 14, 49, 31},
375 {62000, 14, 37, 23},
376 {62250, 14, 42, 26},
377 {63000, 12, 21, 15},
378 {63500, 14, 28, 17},
379 {64000, 12, 27, 19},
380 {65000, 14, 32, 19},
381 {65250, 12, 29, 20},
382 {65500, 12, 32, 22},
383 {66000, 12, 22, 15},
384 {66667, 14, 38, 22},
385 {66750, 10, 21, 17},
386 {67000, 14, 33, 19},
387 {67750, 14, 58, 33},
388 {68000, 14, 30, 17},
389 {68179, 14, 46, 26},
390 {68250, 14, 46, 26},
391 {69000, 12, 23, 15},
392 {70000, 12, 28, 18},
393 {71000, 12, 30, 19},
394 {72000, 12, 24, 15},
395 {73000, 10, 23, 17},
396 {74000, 12, 23, 14},
397 {74176, 8, 100, 91},
398 {74250, 10, 22, 16},
399 {74481, 12, 43, 26},
400 {74500, 10, 29, 21},
401 {75000, 12, 25, 15},
402 {75250, 10, 39, 28},
403 {76000, 12, 27, 16},
404 {77000, 12, 53, 31},
405 {78000, 12, 26, 15},
406 {78750, 12, 28, 16},
407 {79000, 10, 38, 26},
408 {79500, 10, 28, 19},
409 {80000, 12, 32, 18},
410 {81000, 10, 21, 14},
411 {81081, 6, 100, 111},
412 {81624, 8, 29, 24},
413 {82000, 8, 17, 14},
414 {83000, 10, 40, 26},
415 {83950, 10, 28, 18},
416 {84000, 10, 28, 18},
417 {84750, 6, 16, 17},
418 {85000, 6, 17, 18},
419 {85250, 10, 30, 19},
420 {85750, 10, 27, 17},
421 {86000, 10, 43, 27},
422 {87000, 10, 29, 18},
423 {88000, 10, 44, 27},
424 {88500, 10, 41, 25},
425 {89000, 10, 28, 17},
426 {89012, 6, 90, 91},
427 {89100, 10, 33, 20},
428 {90000, 10, 25, 15},
429 {91000, 10, 32, 19},
430 {92000, 10, 46, 27},
431 {93000, 10, 31, 18},
432 {94000, 10, 40, 23},
433 {94500, 10, 28, 16},
434 {95000, 10, 44, 25},
435 {95654, 10, 39, 22},
436 {95750, 10, 39, 22},
437 {96000, 10, 32, 18},
438 {97000, 8, 23, 16},
439 {97750, 8, 42, 29},
440 {98000, 8, 45, 31},
441 {99000, 8, 22, 15},
442 {99750, 8, 34, 23},
443 {100000, 6, 20, 18},
444 {100500, 6, 19, 17},
445 {101000, 6, 37, 33},
446 {101250, 8, 21, 14},
447 {102000, 6, 17, 15},
448 {102250, 6, 25, 22},
449 {103000, 8, 29, 19},
450 {104000, 8, 37, 24},
451 {105000, 8, 28, 18},
452 {106000, 8, 22, 14},
453 {107000, 8, 46, 29},
454 {107214, 8, 27, 17},
455 {108000, 8, 24, 15},
456 {108108, 8, 173, 108},
457 {109000, 6, 23, 19},
12a13a33
ED		 458 {110000, 6, 22, 18},
459 {110013, 6, 22, 18},
460 {110250, 8, 49, 30},
461 {110500, 8, 36, 22},
462 {111000, 8, 23, 14},
463 {111264, 8, 150, 91},
464 {111375, 8, 33, 20},
465 {112000, 8, 63, 38},
466 {112500, 8, 25, 15},
467 {113100, 8, 57, 34},
468 {113309, 8, 42, 25},
469 {114000, 8, 27, 16},
470 {115000, 6, 23, 18},
471 {116000, 8, 43, 25},
472 {117000, 8, 26, 15},
473 {117500, 8, 40, 23},
474 {118000, 6, 38, 29},
475 {119000, 8, 30, 17},
476 {119500, 8, 46, 26},
477 {119651, 8, 39, 22},
478 {120000, 8, 32, 18},
479 {121000, 6, 39, 29},
480 {121250, 6, 31, 23},
481 {121750, 6, 23, 17},
482 {122000, 6, 42, 31},
483 {122614, 6, 30, 22},
484 {123000, 6, 41, 30},
485 {123379, 6, 37, 27},
486 {124000, 6, 51, 37},
487 {125000, 6, 25, 18},
488 {125250, 4, 13, 14},
489 {125750, 4, 27, 29},
490 {126000, 6, 21, 15},
491 {127000, 6, 24, 17},
492 {127250, 6, 41, 29},
493 {128000, 6, 27, 19},
494 {129000, 6, 43, 30},
495 {129859, 4, 25, 26},
496 {130000, 6, 26, 18},
497 {130250, 6, 42, 29},
498 {131000, 6, 32, 22},
499 {131500, 6, 38, 26},
500 {131850, 6, 41, 28},
501 {132000, 6, 22, 15},
502 {132750, 6, 28, 19},
503 {133000, 6, 34, 23},
504 {133330, 6, 37, 25},
505 {134000, 6, 61, 41},
506 {135000, 6, 21, 14},
507 {135250, 6, 167, 111},
508 {136000, 6, 62, 41},
509 {137000, 6, 35, 23},
510 {138000, 6, 23, 15},
511 {138500, 6, 40, 26},
512 {138750, 6, 37, 24},
513 {139000, 6, 34, 22},
514 {139050, 6, 34, 22},
515 {139054, 6, 34, 22},
516 {140000, 6, 28, 18},
517 {141000, 6, 36, 23},
518 {141500, 6, 22, 14},
519 {142000, 6, 30, 19},
520 {143000, 6, 27, 17},
521 {143472, 4, 17, 16},
522 {144000, 6, 24, 15},
523 {145000, 6, 29, 18},
524 {146000, 6, 47, 29},
525 {146250, 6, 26, 16},
526 {147000, 6, 49, 30},
527 {147891, 6, 23, 14},
528 {148000, 6, 23, 14},
529 {148250, 6, 28, 17},
530 {148352, 4, 100, 91},
531 {148500, 6, 33, 20},
532 {149000, 6, 48, 29},
533 {150000, 6, 25, 15},
534 {151000, 4, 19, 17},
535 {152000, 6, 27, 16},
536 {152280, 6, 44, 26},
537 {153000, 6, 34, 20},
538 {154000, 6, 53, 31},
539 {155000, 6, 31, 18},
540 {155250, 6, 50, 29},
541 {155750, 6, 45, 26},
542 {156000, 6, 26, 15},
543 {157000, 6, 61, 35},
544 {157500, 6, 28, 16},
545 {158000, 6, 65, 37},
546 {158250, 6, 44, 25},
547 {159000, 6, 53, 30},
548 {159500, 6, 39, 22},
549 {160000, 6, 32, 18},
550 {161000, 4, 31, 26},
551 {162000, 4, 18, 15},
552 {162162, 4, 131, 109},
553 {162500, 4, 53, 44},
554 {163000, 4, 29, 24},
555 {164000, 4, 17, 14},
556 {165000, 4, 22, 18},
557 {166000, 4, 32, 26},
558 {167000, 4, 26, 21},
559 {168000, 4, 46, 37},
560 {169000, 4, 104, 83},
561 {169128, 4, 64, 51},
562 {169500, 4, 39, 31},
563 {170000, 4, 34, 27},
564 {171000, 4, 19, 15},
565 {172000, 4, 51, 40},
566 {172750, 4, 32, 25},
567 {172800, 4, 32, 25},
568 {173000, 4, 41, 32},
569 {174000, 4, 49, 38},
570 {174787, 4, 22, 17},
571 {175000, 4, 35, 27},
572 {176000, 4, 30, 23},
573 {177000, 4, 38, 29},
574 {178000, 4, 29, 22},
575 {178500, 4, 37, 28},
576 {179000, 4, 53, 40},
577 {179500, 4, 73, 55},
578 {180000, 4, 20, 15},
579 {181000, 4, 55, 41},
580 {182000, 4, 31, 23},
581 {183000, 4, 42, 31},
582 {184000, 4, 30, 22},
583 {184750, 4, 26, 19},
584 {185000, 4, 37, 27},
585 {186000, 4, 51, 37},
586 {187000, 4, 36, 26},
587 {188000, 4, 32, 23},
588 {189000, 4, 21, 15},
589 {190000, 4, 38, 27},
590 {190960, 4, 41, 29},
591 {191000, 4, 41, 29},
592 {192000, 4, 27, 19},
593 {192250, 4, 37, 26},
594 {193000, 4, 20, 14},
595 {193250, 4, 53, 37},
596 {194000, 4, 23, 16},
597 {194208, 4, 23, 16},
598 {195000, 4, 26, 18},
599 {196000, 4, 45, 31},
600 {197000, 4, 35, 24},
601 {197750, 4, 41, 28},
602 {198000, 4, 22, 15},
603 {198500, 4, 25, 17},
604 {199000, 4, 28, 19},
605 {200000, 4, 37, 25},
606 {201000, 4, 61, 41},
607 {202000, 4, 112, 75},
608 {202500, 4, 21, 14},
609 {203000, 4, 146, 97},
610 {204000, 4, 62, 41},
611 {204750, 4, 44, 29},
612 {205000, 4, 38, 25},
613 {206000, 4, 29, 19},
614 {207000, 4, 23, 15},
615 {207500, 4, 40, 26},
616 {208000, 4, 37, 24},
617 {208900, 4, 48, 31},
618 {209000, 4, 48, 31},
619 {209250, 4, 31, 20},
620 {210000, 4, 28, 18},
621 {211000, 4, 25, 16},
622 {212000, 4, 22, 14},
623 {213000, 4, 30, 19},
624 {213750, 4, 38, 24},
625 {214000, 4, 46, 29},
626 {214750, 4, 35, 22},
627 {215000, 4, 43, 27},
628 {216000, 4, 24, 15},
629 {217000, 4, 37, 23},
630 {218000, 4, 42, 26},
631 {218250, 4, 42, 26},
632 {218750, 4, 34, 21},
633 {219000, 4, 47, 29},
12a13a33
ED		 634 {220000, 4, 44, 27},
635 {220640, 4, 49, 30},
636 {220750, 4, 36, 22},
637 {221000, 4, 36, 22},
638 {222000, 4, 23, 14},
639 {222525, 4, 28, 17},
640 {222750, 4, 33, 20},
641 {227000, 4, 37, 22},
642 {230250, 4, 29, 17},
643 {233500, 4, 38, 22},
644 {235000, 4, 40, 23},
645 {238000, 4, 30, 17},
646 {241500, 2, 17, 19},
647 {245250, 2, 20, 22},
648 {247750, 2, 22, 24},
649 {253250, 2, 15, 16},
650 {256250, 2, 18, 19},
651 {262500, 2, 31, 32},
652 {267250, 2, 66, 67},
653 {268500, 2, 94, 95},
654 {270000, 2, 14, 14},
655 {272500, 2, 77, 76},
656 {273750, 2, 57, 56},
657 {280750, 2, 24, 23},
658 {281250, 2, 23, 22},
659 {286000, 2, 17, 16},
660 {291750, 2, 26, 24},
661 {296703, 2, 56, 51},
662 {297000, 2, 22, 20},
663 {298000, 2, 21, 19},
664};
72662e10 665
00c09d70
PZ		 666static void intel_ddi_mode_set(struct drm_encoder *encoder,
667 struct drm_display_mode *mode,
668 struct drm_display_mode *adjusted_mode)
72662e10 669{
72662e10
ED		 670 struct drm_crtc *crtc = encoder->crtc;
671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
247d89f6
PZ		 672 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
673 int port = intel_ddi_get_encoder_port(intel_encoder);
72662e10 674 int pipe = intel_crtc->pipe;
247d89f6 675 int type = intel_encoder->type;
72662e10 676
247d89f6
PZ		 677 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
678 port_name(port), pipe_name(pipe));
72662e10 679
7b9f35a6 680 intel_crtc->eld_vld = false;
247d89f6
PZ		 681 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
682 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4f07854d 683
247d89f6
PZ		 684 intel_dp->DP = DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
685 switch (intel_dp->lane_count) {
686 case 1:
687 intel_dp->DP |= DDI_PORT_WIDTH_X1;
688 break;
689 case 2:
690 intel_dp->DP |= DDI_PORT_WIDTH_X2;
691 break;
692 case 4:
693 intel_dp->DP |= DDI_PORT_WIDTH_X4;
694 break;
695 default:
696 intel_dp->DP |= DDI_PORT_WIDTH_X4;
697 WARN(1, "Unexpected DP lane count %d\n",
698 intel_dp->lane_count);
699 break;
700 }
701
8fed6193
TI		 702 if (intel_dp->has_audio) {
703 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
704 pipe_name(intel_crtc->pipe));
705
706 /* write eld */
707 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
708 intel_write_eld(encoder, adjusted_mode);
709 }
710
247d89f6
PZ		 711 intel_dp_init_link_config(intel_dp);
712
713 } else if (type == INTEL_OUTPUT_HDMI) {
714 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
715
716 if (intel_hdmi->has_audio) {
717 /* Proper support for digital audio needs a new logic
718 * and a new set of registers, so we leave it for future
719 * patch bombing.
720 */
721 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
722 pipe_name(intel_crtc->pipe));
723
724 /* write eld */
725 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
726 intel_write_eld(encoder, adjusted_mode);
727 }
72662e10 728
247d89f6
PZ		 729 intel_hdmi->set_infoframes(encoder, adjusted_mode);
730 }
8d9ddbcb
PZ		 731}
732
733static struct intel_encoder *
734intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
735{
736 struct drm_device *dev = crtc->dev;
737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
738 struct intel_encoder *intel_encoder, *ret = NULL;
739 int num_encoders = 0;
740
741 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
742 ret = intel_encoder;
743 num_encoders++;
744 }
745
746 if (num_encoders != 1)
747 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,
748 intel_crtc->pipe);
749
750 BUG_ON(ret == NULL);
751 return ret;
752}
753
6441ab5f
PZ		 754void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
755{
756 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
757 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759 uint32_t val;
760
761 switch (intel_crtc->ddi_pll_sel) {
762 case PORT_CLK_SEL_SPLL:
763 plls->spll_refcount--;
764 if (plls->spll_refcount == 0) {
765 DRM_DEBUG_KMS("Disabling SPLL\n");
766 val = I915_READ(SPLL_CTL);
767 WARN_ON(!(val & SPLL_PLL_ENABLE));
768 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
769 POSTING_READ(SPLL_CTL);
770 }
771 break;
772 case PORT_CLK_SEL_WRPLL1:
773 plls->wrpll1_refcount--;
774 if (plls->wrpll1_refcount == 0) {
775 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
776 val = I915_READ(WRPLL_CTL1);
777 WARN_ON(!(val & WRPLL_PLL_ENABLE));
778 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
779 POSTING_READ(WRPLL_CTL1);
780 }
781 break;
782 case PORT_CLK_SEL_WRPLL2:
783 plls->wrpll2_refcount--;
784 if (plls->wrpll2_refcount == 0) {
785 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
786 val = I915_READ(WRPLL_CTL2);
787 WARN_ON(!(val & WRPLL_PLL_ENABLE));
788 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
789 POSTING_READ(WRPLL_CTL2);
790 }
791 break;
792 }
793
794 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
795 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
796 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
797
798 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
799}
800
801static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2)
802{
803 u32 i;
804
805 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
806 if (clock <= wrpll_tmds_clock_table[i].clock)
807 break;
808
809 if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
810 i--;
811
812 *p = wrpll_tmds_clock_table[i].p;
813 *n2 = wrpll_tmds_clock_table[i].n2;
814 *r2 = wrpll_tmds_clock_table[i].r2;
815
816 if (wrpll_tmds_clock_table[i].clock != clock)
817 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
818 wrpll_tmds_clock_table[i].clock, clock);
819
820 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
821 clock, *p, *n2, *r2);
822}
823
824bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
825{
826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
827 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
068759bd 828 struct drm_encoder *encoder = &intel_encoder->base;
6441ab5f
PZ		 829 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
830 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
831 int type = intel_encoder->type;
832 enum pipe pipe = intel_crtc->pipe;
833 uint32_t reg, val;
834
835 /* TODO: reuse PLLs when possible (compare values) */
836
837 intel_ddi_put_crtc_pll(crtc);
838
068759bd
PZ		 839 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
840 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
841
842 switch (intel_dp->link_bw) {
843 case DP_LINK_BW_1_62:
844 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
845 break;
846 case DP_LINK_BW_2_7:
847 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
848 break;
849 case DP_LINK_BW_5_4:
850 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
851 break;
852 default:
853 DRM_ERROR("Link bandwidth %d unsupported\n",
854 intel_dp->link_bw);
855 return false;
856 }
857
858 /* We don't need to turn any PLL on because we'll use LCPLL. */
859 return true;
860
861 } else if (type == INTEL_OUTPUT_HDMI) {
6441ab5f
PZ		 862 int p, n2, r2;
863
864 if (plls->wrpll1_refcount == 0) {
865 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
866 pipe_name(pipe));
867 plls->wrpll1_refcount++;
868 reg = WRPLL_CTL1;
869 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
870 } else if (plls->wrpll2_refcount == 0) {
871 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
872 pipe_name(pipe));
873 plls->wrpll2_refcount++;
874 reg = WRPLL_CTL2;
875 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
876 } else {
877 DRM_ERROR("No WRPLLs available!\n");
878 return false;
879 }
880
881 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
882 "WRPLL already enabled\n");
883
884 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2);
885
886 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
887 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
888 WRPLL_DIVIDER_POST(p);
889
890 } else if (type == INTEL_OUTPUT_ANALOG) {
891 if (plls->spll_refcount == 0) {
892 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
893 pipe_name(pipe));
894 plls->spll_refcount++;
895 reg = SPLL_CTL;
896 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
897 }
898
899 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
900 "SPLL already enabled\n");
901
39bc66c9 902 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
6441ab5f
PZ		 903
904 } else {
905 WARN(1, "Invalid DDI encoder type %d\n", type);
906 return false;
907 }
908
909 I915_WRITE(reg, val);
910 udelay(20);
911
912 return true;
913}
914
dae84799
PZ		 915void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
916{
917 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
919 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
c9809791 920 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
dae84799
PZ		 921 int type = intel_encoder->type;
922 uint32_t temp;
923
924 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
925
c9809791 926 temp = TRANS_MSA_SYNC_CLK;
dae84799
PZ		 927 switch (intel_crtc->bpp) {
928 case 18:
c9809791 929 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 930 break;
931 case 24:
c9809791 932 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 933 break;
934 case 30:
c9809791 935 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 936 break;
937 case 36:
c9809791 938 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 939 break;
940 default:
c9809791
PZ		 941 temp |= TRANS_MSA_8_BPC;
942 WARN(1, "%d bpp unsupported by DDI function\n",
dae84799
PZ		 943 intel_crtc->bpp);
944 }
c9809791 945 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 946 }
947}
948
8d9ddbcb
PZ		 949void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
950{
951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
952 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 953 struct drm_encoder *encoder = &intel_encoder->base;
8d9ddbcb
PZ		 954 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
955 enum pipe pipe = intel_crtc->pipe;
ad80a810 956 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
174edf1f 957 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 958 int type = intel_encoder->type;
8d9ddbcb
PZ		 959 uint32_t temp;
960
ad80a810
PZ		 961 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
962 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 963 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252
PZ		 964
965 switch (intel_crtc->bpp) {
966 case 18:
ad80a810 967 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 968 break;
969 case 24:
ad80a810 970 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 971 break;
972 case 30:
ad80a810 973 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 974 break;
975 case 36:
ad80a810 976 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 977 break;
978 default:
ad80a810 979 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
dfcef252
PZ		 980 intel_crtc->bpp);
981 }
72662e10 982
8d9ddbcb 983 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 984 temp |= TRANS_DDI_PVSYNC;
8d9ddbcb 985 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 986 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 987
e6f0bfc4
PZ		 988 if (cpu_transcoder == TRANSCODER_EDP) {
989 switch (pipe) {
990 case PIPE_A:
991 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
992 break;
993 case PIPE_B:
994 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
995 break;
996 case PIPE_C:
997 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
998 break;
999 default:
1000 BUG();
1001 break;
1002 }
1003 }
1004
7739c33b
PZ		 1005 if (type == INTEL_OUTPUT_HDMI) {
1006 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
8d9ddbcb
PZ		 1007
1008 if (intel_hdmi->has_hdmi_sink)
ad80a810 1009 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1010 else
ad80a810 1011 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1012
7739c33b 1013 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1014 temp |= TRANS_DDI_MODE_SELECT_FDI;
349d7e5d 1015 temp |= (intel_crtc->fdi_lanes - 1) << 1;
7739c33b
PZ		 1016
1017 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1018 type == INTEL_OUTPUT_EDP) {
1019 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1020
ad80a810 1021 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b
PZ		 1022
1023 switch (intel_dp->lane_count) {
1024 case 1:
ad80a810 1025 temp |= TRANS_DDI_PORT_WIDTH_X1;
7739c33b
PZ		 1026 break;
1027 case 2:
ad80a810 1028 temp |= TRANS_DDI_PORT_WIDTH_X2;
7739c33b
PZ		 1029 break;
1030 case 4:
ad80a810 1031 temp |= TRANS_DDI_PORT_WIDTH_X4;
7739c33b
PZ		 1032 break;
1033 default:
ad80a810 1034 temp |= TRANS_DDI_PORT_WIDTH_X4;
7739c33b
PZ		 1035 WARN(1, "Unsupported lane count %d\n",
1036 intel_dp->lane_count);
1037 }
1038
8d9ddbcb
PZ		 1039 } else {
1040 WARN(1, "Invalid encoder type %d for pipe %d\n",
1041 intel_encoder->type, pipe);
1042 }
1043
ad80a810 1044 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1045}
72662e10 1046
ad80a810
PZ		 1047void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1048 enum transcoder cpu_transcoder)
8d9ddbcb 1049{
ad80a810 1050 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1051 uint32_t val = I915_READ(reg);
1052
ad80a810
PZ		 1053 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1054 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1055 I915_WRITE(reg, val);
72662e10
ED		 1056}
1057
bcbc889b
PZ		 1058bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1059{
1060 struct drm_device *dev = intel_connector->base.dev;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 struct intel_encoder *intel_encoder = intel_connector->encoder;
1063 int type = intel_connector->base.connector_type;
1064 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1065 enum pipe pipe = 0;
1066 enum transcoder cpu_transcoder;
1067 uint32_t tmp;
1068
1069 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1070 return false;
1071
1072 if (port == PORT_A)
1073 cpu_transcoder = TRANSCODER_EDP;
1074 else
1a240d4d 1075 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1076
1077 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1078
1079 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1080 case TRANS_DDI_MODE_SELECT_HDMI:
1081 case TRANS_DDI_MODE_SELECT_DVI:
1082 return (type == DRM_MODE_CONNECTOR_HDMIA);
1083
1084 case TRANS_DDI_MODE_SELECT_DP_SST:
1085 if (type == DRM_MODE_CONNECTOR_eDP)
1086 return true;
1087 case TRANS_DDI_MODE_SELECT_DP_MST:
1088 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1089
1090 case TRANS_DDI_MODE_SELECT_FDI:
1091 return (type == DRM_MODE_CONNECTOR_VGA);
1092
1093 default:
1094 return false;
1095 }
1096}
1097
85234cdc
DV		 1098bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1099 enum pipe *pipe)
1100{
1101 struct drm_device *dev = encoder->base.dev;
1102 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1103 enum port port = intel_ddi_get_encoder_port(encoder);
85234cdc
DV		 1104 u32 tmp;
1105 int i;
1106
fe43d3f5 1107 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1108
1109 if (!(tmp & DDI_BUF_CTL_ENABLE))
1110 return false;
1111
ad80a810
PZ		 1112 if (port == PORT_A) {
1113 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1114
ad80a810
PZ		 1115 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1116 case TRANS_DDI_EDP_INPUT_A_ON:
1117 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1118 *pipe = PIPE_A;
1119 break;
1120 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1121 *pipe = PIPE_B;
1122 break;
1123 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1124 *pipe = PIPE_C;
1125 break;
1126 }
1127
1128 return true;
1129 } else {
1130 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1131 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1132
1133 if ((tmp & TRANS_DDI_PORT_MASK)
1134 == TRANS_DDI_SELECT_PORT(port)) {
1135 *pipe = i;
1136 return true;
1137 }
85234cdc
DV		 1138 }
1139 }
1140
fe43d3f5 1141 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
85234cdc
DV		 1142
1143 return true;
1144}
1145
6441ab5f
PZ		 1146static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 uint32_t temp, ret;
1150 enum port port;
ad80a810
PZ		 1151 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1152 pipe);
6441ab5f
PZ		 1153 int i;
1154
ad80a810
PZ		 1155 if (cpu_transcoder == TRANSCODER_EDP) {
1156 port = PORT_A;
1157 } else {
1158 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1159 temp &= TRANS_DDI_PORT_MASK;
1160
1161 for (i = PORT_B; i <= PORT_E; i++)
1162 if (temp == TRANS_DDI_SELECT_PORT(i))
1163 port = i;
1164 }
6441ab5f
PZ		 1165
1166 ret = I915_READ(PORT_CLK_SEL(port));
1167
1168 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1169 pipe_name(pipe), port_name(port), ret);
1170
1171 return ret;
1172}
1173
1174void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1175{
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 enum pipe pipe;
1178 struct intel_crtc *intel_crtc;
1179
1180 for_each_pipe(pipe) {
1181 intel_crtc =
1182 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1183
1184 if (!intel_crtc->active)
1185 continue;
1186
1187 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1188 pipe);
1189
1190 switch (intel_crtc->ddi_pll_sel) {
1191 case PORT_CLK_SEL_SPLL:
1192 dev_priv->ddi_plls.spll_refcount++;
1193 break;
1194 case PORT_CLK_SEL_WRPLL1:
1195 dev_priv->ddi_plls.wrpll1_refcount++;
1196 break;
1197 case PORT_CLK_SEL_WRPLL2:
1198 dev_priv->ddi_plls.wrpll2_refcount++;
1199 break;
1200 }
1201 }
1202}
1203
fc914639
PZ		 1204void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1205{
1206 struct drm_crtc *crtc = &intel_crtc->base;
1207 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1208 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1209 enum port port = intel_ddi_get_encoder_port(intel_encoder);
bb523fc0 1210 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
fc914639 1211
bb523fc0
PZ		 1212 if (cpu_transcoder != TRANSCODER_EDP)
1213 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1214 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1215}
1216
1217void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1218{
1219 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
bb523fc0 1220 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
fc914639 1221
bb523fc0
PZ		 1222 if (cpu_transcoder != TRANSCODER_EDP)
1223 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1224 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1225}
1226
00c09d70 1227static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1228{
c19b0669
PZ		 1229 struct drm_encoder *encoder = &intel_encoder->base;
1230 struct drm_crtc *crtc = encoder->crtc;
1231 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
6441ab5f
PZ		 1232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1233 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1234 int type = intel_encoder->type;
6441ab5f 1235
82a4d9c0
PZ		 1236 if (type == INTEL_OUTPUT_EDP) {
1237 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1238 ironlake_edp_panel_vdd_on(intel_dp);
1239 ironlake_edp_panel_on(intel_dp);
1240 ironlake_edp_panel_vdd_off(intel_dp, true);
1241 }
6441ab5f 1242
82a4d9c0 1243 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
6441ab5f 1244 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
c19b0669 1245
82a4d9c0 1246 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669
PZ		 1247 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1248
1249 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1250 intel_dp_start_link_train(intel_dp);
1251 intel_dp_complete_link_train(intel_dp);
1252 }
6441ab5f
PZ		 1253}
1254
00c09d70 1255static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1256{
1257 struct drm_encoder *encoder = &intel_encoder->base;
1258 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1259 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1260 int type = intel_encoder->type;
2886e93f 1261 uint32_t val;
a836bdf9 1262 bool wait = false;
2886e93f
PZ		 1263
1264 val = I915_READ(DDI_BUF_CTL(port));
1265 if (val & DDI_BUF_CTL_ENABLE) {
1266 val &= ~DDI_BUF_CTL_ENABLE;
1267 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1268 wait = true;
2886e93f 1269 }
6441ab5f 1270
a836bdf9
PZ		 1271 val = I915_READ(DP_TP_CTL(port));
1272 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1273 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1274 I915_WRITE(DP_TP_CTL(port), val);
1275
1276 if (wait)
1277 intel_wait_ddi_buf_idle(dev_priv, port);
1278
82a4d9c0
PZ		 1279 if (type == INTEL_OUTPUT_EDP) {
1280 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1281 ironlake_edp_panel_vdd_on(intel_dp);
1282 ironlake_edp_panel_off(intel_dp);
1283 }
1284
6441ab5f
PZ		 1285 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1286}
1287
00c09d70 1288static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1289{
6547fef8 1290 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1291 struct drm_crtc *crtc = encoder->crtc;
1292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1293 int pipe = intel_crtc->pipe;
6547fef8 1294 struct drm_device *dev = encoder->dev;
72662e10 1295 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 1296 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1297 int type = intel_encoder->type;
7b9f35a6 1298 uint32_t tmp;
72662e10 1299
6547fef8
PZ		 1300 if (type == INTEL_OUTPUT_HDMI) {
1301 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1302 * are ignored so nothing special needs to be done besides
1303 * enabling the port.
1304 */
1305 I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1306 } else if (type == INTEL_OUTPUT_EDP) {
1307 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1308
1309 ironlake_edp_backlight_on(intel_dp);
6547fef8 1310 }
7b9f35a6
WX		 1311
1312 if (intel_crtc->eld_vld) {
1313 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1314 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1315 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1316 }
5ab432ef
DV		 1317}
1318
00c09d70 1319static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1320{
d6c50ff8 1321 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1322 struct drm_crtc *crtc = encoder->crtc;
1323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1324 int pipe = intel_crtc->pipe;
d6c50ff8 1325 int type = intel_encoder->type;
7b9f35a6
WX		 1326 struct drm_device *dev = encoder->dev;
1327 struct drm_i915_private *dev_priv = dev->dev_private;
1328 uint32_t tmp;
d6c50ff8
PZ		 1329
1330 if (type == INTEL_OUTPUT_EDP) {
1331 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1332
1333 ironlake_edp_backlight_off(intel_dp);
1334 }
7b9f35a6
WX		 1335
1336 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1337 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1338 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
72662e10 1339}
79f689aa 1340
b8fc2f6a 1341int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
79f689aa
PZ		 1342{
1343 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1344 return 450;
1345 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1346 LCPLL_CLK_FREQ_450)
1347 return 450;
d567b07f
PZ		 1348 else if (IS_ULT(dev_priv->dev))
1349 return 338;
79f689aa
PZ		 1350 else
1351 return 540;
1352}
1353
1354void intel_ddi_pll_init(struct drm_device *dev)
1355{
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 uint32_t val = I915_READ(LCPLL_CTL);
1358
1359 /* The LCPLL register should be turned on by the BIOS. For now let's
1360 * just check its state and print errors in case something is wrong.
1361 * Don't even try to turn it on.
1362 */
1363
1364 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1365 intel_ddi_get_cdclk_freq(dev_priv));
1366
1367 if (val & LCPLL_CD_SOURCE_FCLK)
1368 DRM_ERROR("CDCLK source is not LCPLL\n");
1369
1370 if (val & LCPLL_PLL_DISABLE)
1371 DRM_ERROR("LCPLL is disabled\n");
1372}
c19b0669
PZ		 1373
1374void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1375{
174edf1f
PZ		 1376 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1377 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 1378 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 1379 enum port port = intel_dig_port->port;
c19b0669
PZ		 1380 bool wait;
1381 uint32_t val;
1382
1383 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1384 val = I915_READ(DDI_BUF_CTL(port));
1385 if (val & DDI_BUF_CTL_ENABLE) {
1386 val &= ~DDI_BUF_CTL_ENABLE;
1387 I915_WRITE(DDI_BUF_CTL(port), val);
1388 wait = true;
1389 }
1390
1391 val = I915_READ(DP_TP_CTL(port));
1392 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1393 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1394 I915_WRITE(DP_TP_CTL(port), val);
1395 POSTING_READ(DP_TP_CTL(port));
1396
1397 if (wait)
1398 intel_wait_ddi_buf_idle(dev_priv, port);
1399 }
1400
1401 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1402 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1403 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1404 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1405 I915_WRITE(DP_TP_CTL(port), val);
1406 POSTING_READ(DP_TP_CTL(port));
1407
1408 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1409 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1410 POSTING_READ(DDI_BUF_CTL(port));
1411
1412 udelay(600);
1413}
00c09d70 1414
1ad960f2
PZ		 1415void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1416{
1417 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1418 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1419 uint32_t val;
1420
1421 intel_ddi_post_disable(intel_encoder);
1422
1423 val = I915_READ(_FDI_RXA_CTL);
1424 val &= ~FDI_RX_ENABLE;
1425 I915_WRITE(_FDI_RXA_CTL, val);
1426
1427 val = I915_READ(_FDI_RXA_MISC);
1428 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1429 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1430 I915_WRITE(_FDI_RXA_MISC, val);
1431
1432 val = I915_READ(_FDI_RXA_CTL);
1433 val &= ~FDI_PCDCLK;
1434 I915_WRITE(_FDI_RXA_CTL, val);
1435
1436 val = I915_READ(_FDI_RXA_CTL);
1437 val &= ~FDI_RX_PLL_ENABLE;
1438 I915_WRITE(_FDI_RXA_CTL, val);
1439}
1440
00c09d70
PZ		 1441static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1442{
1443 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1444 int type = intel_encoder->type;
1445
1446 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1447 intel_dp_check_link_status(intel_dp);
1448}
1449
1450static void intel_ddi_destroy(struct drm_encoder *encoder)
1451{
1452 /* HDMI has nothing special to destroy, so we can go with this. */
1453 intel_dp_encoder_destroy(encoder);
1454}
1455
1456static bool intel_ddi_mode_fixup(struct drm_encoder *encoder,
1457 const struct drm_display_mode *mode,
1458 struct drm_display_mode *adjusted_mode)
1459{
1460 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1461 int type = intel_encoder->type;
1462
1463 WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n");
1464
1465 if (type == INTEL_OUTPUT_HDMI)
1466 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode);
1467 else
1468 return intel_dp_mode_fixup(encoder, mode, adjusted_mode);
1469}
1470
1471static const struct drm_encoder_funcs intel_ddi_funcs = {
1472 .destroy = intel_ddi_destroy,
1473};
1474
1475static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1476 .mode_fixup = intel_ddi_mode_fixup,
1477 .mode_set = intel_ddi_mode_set,
1478 .disable = intel_encoder_noop,
1479};
1480
1481void intel_ddi_init(struct drm_device *dev, enum port port)
1482{
1483 struct intel_digital_port *intel_dig_port;
1484 struct intel_encoder *intel_encoder;
1485 struct drm_encoder *encoder;
1486 struct intel_connector *hdmi_connector = NULL;
1487 struct intel_connector *dp_connector = NULL;
1488
1489 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1490 if (!intel_dig_port)
1491 return;
1492
1493 dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1494 if (!dp_connector) {
1495 kfree(intel_dig_port);
1496 return;
1497 }
1498
1499 if (port != PORT_A) {
1500 hdmi_connector = kzalloc(sizeof(struct intel_connector),
1501 GFP_KERNEL);
1502 if (!hdmi_connector) {
1503 kfree(dp_connector);
1504 kfree(intel_dig_port);
1505 return;
1506 }
1507 }
1508
1509 intel_encoder = &intel_dig_port->base;
1510 encoder = &intel_encoder->base;
1511
1512 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1513 DRM_MODE_ENCODER_TMDS);
1514 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1515
1516 intel_encoder->enable = intel_enable_ddi;
1517 intel_encoder->pre_enable = intel_ddi_pre_enable;
1518 intel_encoder->disable = intel_disable_ddi;
1519 intel_encoder->post_disable = intel_ddi_post_disable;
1520 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1521
1522 intel_dig_port->port = port;
1523 if (hdmi_connector)
1524 intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port);
1525 else
1526 intel_dig_port->hdmi.sdvox_reg = 0;
1527 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1528
1529 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1530 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1531 intel_encoder->cloneable = false;
1532 intel_encoder->hot_plug = intel_ddi_hot_plug;
1533
1534 if (hdmi_connector)
1535 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1536 intel_dp_init_connector(intel_dig_port, dp_connector);
1537}
Linux 6.x block layer and io_uring tree(s)