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drm/i915/ddi: Fix eDP VDD handling during booting and suspend/resume
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
d7097cff 136 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
d7097cff 139 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 140 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 141 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 147 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 148 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 150 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x00000088, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 161 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 163 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 166 { 0x00000018, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
2e78416e 229 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 230 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 240 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
2e78416e 244 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 245 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
78ab0bae
VS		 304static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
305 u32 level, enum port port, int type);
f8896f5d 306
a1e6ad66
ID		 307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
fc914639 310{
0bdee30e 311 struct drm_encoder *encoder = &intel_encoder->base;
fc914639 312
8cd21b7f
JN		 313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
a1e6ad66
ID		 315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
8cd21b7f
JN		 317 break;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
a1e6ad66
ID		 322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
8cd21b7f
JN		 324 break;
325 case INTEL_OUTPUT_ANALOG:
a1e6ad66
ID		 326 *dig_port = NULL;
327 *port = PORT_E;
8cd21b7f
JN		 328 break;
329 default:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 break;
fc914639
PZ		 332 }
333}
334
a1e6ad66
ID		 335enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336{
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343}
344
acee2998 345static const struct ddi_buf_trans *
78ab0bae 346skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 347{
78ab0bae 348 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 349 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 350 return skl_y_ddi_translations_dp;
78ab0bae 351 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 352 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 353 return skl_u_ddi_translations_dp;
f8896f5d 354 } else {
f8896f5d 355 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 356 return skl_ddi_translations_dp;
f8896f5d 357 }
f8896f5d
DW		 358}
359
acee2998 360static const struct ddi_buf_trans *
78ab0bae 361skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 362{
cd1101cb 363 if (dev_priv->edp_low_vswing) {
78ab0bae 364 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 365 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 366 return skl_y_ddi_translations_edp;
78ab0bae 367 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 368 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 369 return skl_u_ddi_translations_edp;
f8896f5d 370 } else {
f8896f5d 371 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 372 return skl_ddi_translations_edp;
f8896f5d
DW		 373 }
374 }
cd1101cb 375
78ab0bae 376 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 377}
378
379static const struct ddi_buf_trans *
78ab0bae 380skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 381{
78ab0bae 382 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 384 return skl_y_ddi_translations_hdmi;
f8896f5d 385 } else {
f8896f5d 386 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 387 return skl_ddi_translations_hdmi;
f8896f5d 388 }
f8896f5d
DW		 389}
390
e58623cb
AR		 391/*
392 * Starting with Haswell, DDI port buffers must be programmed with correct
393 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 394 * but the HDMI/DVI fields are shared among those. So we program the DDI
395 * in either FDI or DP modes only, as HDMI connections will work with both
396 * of those
397 */
6a7e4f99 398void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
45244b87 399{
6a7e4f99 400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 401 u32 iboost_bit = 0;
7ff44670 402 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 403 size;
6a7e4f99
VS		 404 int hdmi_level;
405 enum port port;
10122051
JN		 406 const struct ddi_buf_trans *ddi_translations_fdi;
407 const struct ddi_buf_trans *ddi_translations_dp;
408 const struct ddi_buf_trans *ddi_translations_edp;
409 const struct ddi_buf_trans *ddi_translations_hdmi;
410 const struct ddi_buf_trans *ddi_translations;
e58623cb 411
6a7e4f99
VS		 412 port = intel_ddi_get_encoder_port(encoder);
413 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
414
78ab0bae 415 if (IS_BROXTON(dev_priv)) {
6a7e4f99 416 if (encoder->type != INTEL_OUTPUT_HDMI)
96fb9f9b
VK		 417 return;
418
419 /* Vswing programming for HDMI */
78ab0bae 420 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
96fb9f9b
VK		 421 INTEL_OUTPUT_HDMI);
422 return;
6a7e4f99
VS		 423 }
424
425 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c30400fc 426 ddi_translations_fdi = NULL;
f8896f5d 427 ddi_translations_dp =
78ab0bae 428 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
f8896f5d 429 ddi_translations_edp =
78ab0bae 430 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
f8896f5d 431 ddi_translations_hdmi =
78ab0bae 432 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
f8896f5d 433 hdmi_default_entry = 8;
75067dde
AK		 434 /* If we're boosting the current, set bit 31 of trans1 */
435 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
436 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
437 iboost_bit = 1<<31;
10afa0b6 438
ceccad59
VS		 439 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
440 port != PORT_A && port != PORT_E &&
441 n_edp_entries > 9))
10afa0b6 442 n_edp_entries = 9;
78ab0bae 443 } else if (IS_BROADWELL(dev_priv)) {
e58623cb
AR		 444 ddi_translations_fdi = bdw_ddi_translations_fdi;
445 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 446 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 447 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 448 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
449 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 450 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 451 hdmi_default_entry = 7;
78ab0bae 452 } else if (IS_HASWELL(dev_priv)) {
e58623cb
AR		 453 ddi_translations_fdi = hsw_ddi_translations_fdi;
454 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 455 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 456 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 457 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 458 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 459 hdmi_default_entry = 6;
e58623cb
AR		 460 } else {
461 WARN(1, "ddi translation table missing\n");
300644c7 462 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 463 ddi_translations_fdi = bdw_ddi_translations_fdi;
464 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 465 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 466 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
467 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 468 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 469 hdmi_default_entry = 7;
e58623cb
AR		 470 }
471
6a7e4f99
VS		 472 switch (encoder->type) {
473 case INTEL_OUTPUT_EDP:
300644c7 474 ddi_translations = ddi_translations_edp;
7ad14a29 475 size = n_edp_entries;
300644c7 476 break;
6a7e4f99
VS		 477 case INTEL_OUTPUT_DISPLAYPORT:
478 case INTEL_OUTPUT_HDMI:
300644c7 479 ddi_translations = ddi_translations_dp;
7ad14a29 480 size = n_dp_entries;
300644c7 481 break;
6a7e4f99
VS		 482 case INTEL_OUTPUT_ANALOG:
483 ddi_translations = ddi_translations_fdi;
7ad14a29 484 size = n_dp_entries;
300644c7
PZ		 485 break;
486 default:
487 BUG();
488 }
45244b87 489
9712e688
VS		 490 for (i = 0; i < size; i++) {
491 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
492 ddi_translations[i].trans1 | iboost_bit);
493 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
494 ddi_translations[i].trans2);
45244b87 495 }
ce4dd49e 496
6a7e4f99 497 if (encoder->type != INTEL_OUTPUT_HDMI)
ce3b7e9b
DL		 498 return;
499
ce4dd49e
DL		 500 /* Choose a good default if VBT is badly populated */
501 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
502 hdmi_level >= n_hdmi_entries)
7ff44670 503 hdmi_level = hdmi_default_entry;
ce4dd49e 504
6acab15a 505 /* Entry 9 is for HDMI: */
9712e688
VS		 506 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
507 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
508 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
509 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 510}
511
248138b5
PZ		 512static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
513 enum port port)
514{
f0f59a00 515 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 516 int i;
517
3449ca85 518 for (i = 0; i < 16; i++) {
248138b5
PZ		 519 udelay(1);
520 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
521 return;
522 }
523 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
524}
c82e4d26
ED		 525
526/* Starting with Haswell, different DDI ports can work in FDI mode for
527 * connection to the PCH-located connectors. For this, it is necessary to train
528 * both the DDI port and PCH receiver for the desired DDI buffer settings.
529 *
530 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
531 * please note that when FDI mode is active on DDI E, it shares 2 lines with
532 * DDI A (which is used for eDP)
533 */
534
535void hsw_fdi_link_train(struct drm_crtc *crtc)
536{
537 struct drm_device *dev = crtc->dev;
538 struct drm_i915_private *dev_priv = dev->dev_private;
539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6a7e4f99 540 struct intel_encoder *encoder;
04945641 541 u32 temp, i, rx_ctl_val;
c82e4d26 542
6a7e4f99
VS		 543 for_each_encoder_on_crtc(dev, crtc, encoder) {
544 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
545 intel_prepare_ddi_buffer(encoder);
546 }
547
04945641
PZ		 548 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
549 * mode set "sequence for CRT port" document:
550 * - TP1 to TP2 time with the default value
551 * - FDI delay to 90h
8693a824
DL		 552 *
553 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 554 */
eede3b53 555 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 556 FDI_RX_PWRDN_LANE0_VAL(2) |
557 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
558
559 /* Enable the PCH Receiver FDI PLL */
3e68320e 560 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 561 FDI_RX_PLL_ENABLE |
6e3c9717 562 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
eede3b53
VS		 563 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
564 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 565 udelay(220);
566
567 /* Switch from Rawclk to PCDclk */
568 rx_ctl_val |= FDI_PCDCLK;
eede3b53 569 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 570
571 /* Configure Port Clock Select */
6e3c9717
ACO		 572 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
573 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 574
575 /* Start the training iterating through available voltages and emphasis,
576 * testing each value twice. */
10122051 577 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 578 /* Configure DP_TP_CTL with auto-training */
579 I915_WRITE(DP_TP_CTL(PORT_E),
580 DP_TP_CTL_FDI_AUTOTRAIN |
581 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
582 DP_TP_CTL_LINK_TRAIN_PAT1 |
583 DP_TP_CTL_ENABLE);
584
876a8cdf
DL		 585 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
586 * DDI E does not support port reversal, the functionality is
587 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
588 * port reversal bit */
c82e4d26 589 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 590 DDI_BUF_CTL_ENABLE |
6e3c9717 591 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 592 DDI_BUF_TRANS_SELECT(i / 2));
04945641 593 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 594
595 udelay(600);
596
04945641 597 /* Program PCH FDI Receiver TU */
eede3b53 598 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 599
600 /* Enable PCH FDI Receiver with auto-training */
601 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 602 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
603 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 604
605 /* Wait for FDI receiver lane calibration */
606 udelay(30);
607
608 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 609 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 610 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 611 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
612 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 613
614 /* Wait for FDI auto training time */
615 udelay(5);
c82e4d26
ED		 616
617 temp = I915_READ(DP_TP_STATUS(PORT_E));
618 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 619 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 620 break;
621 }
c82e4d26 622
a308ccb3
VS		 623 /*
624 * Leave things enabled even if we failed to train FDI.
625 * Results in less fireworks from the state checker.
626 */
627 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
628 DRM_ERROR("FDI link training failed!\n");
629 break;
c82e4d26 630 }
04945641 631
248138b5
PZ		 632 temp = I915_READ(DDI_BUF_CTL(PORT_E));
633 temp &= ~DDI_BUF_CTL_ENABLE;
634 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
635 POSTING_READ(DDI_BUF_CTL(PORT_E));
636
04945641 637 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 638 temp = I915_READ(DP_TP_CTL(PORT_E));
639 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
640 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
641 I915_WRITE(DP_TP_CTL(PORT_E), temp);
642 POSTING_READ(DP_TP_CTL(PORT_E));
643
644 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 645
646 rx_ctl_val &= ~FDI_RX_ENABLE;
eede3b53
VS		 647 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
648 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 649
650 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 651 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 652 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
653 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 654 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
655 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 656 }
657
a308ccb3
VS		 658 /* Enable normal pixel sending for FDI */
659 I915_WRITE(DP_TP_CTL(PORT_E),
660 DP_TP_CTL_FDI_AUTOTRAIN |
661 DP_TP_CTL_LINK_TRAIN_NORMAL |
662 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
663 DP_TP_CTL_ENABLE);
c82e4d26 664}
0e72a5b5 665
44905a27
DA		 666void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
667{
668 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
669 struct intel_digital_port *intel_dig_port =
670 enc_to_dig_port(&encoder->base);
671
672 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 673 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 674 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 675}
676
8d9ddbcb
PZ		 677static struct intel_encoder *
678intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
679{
680 struct drm_device *dev = crtc->dev;
681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
682 struct intel_encoder *intel_encoder, *ret = NULL;
683 int num_encoders = 0;
684
685 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
686 ret = intel_encoder;
687 num_encoders++;
688 }
689
690 if (num_encoders != 1)
84f44ce7
VS		 691 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
692 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 693
694 BUG_ON(ret == NULL);
695 return ret;
696}
697
bcddf610 698struct intel_encoder *
3165c074 699intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 700{
3165c074
ACO		 701 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
702 struct intel_encoder *ret = NULL;
703 struct drm_atomic_state *state;
da3ced29
ACO		 704 struct drm_connector *connector;
705 struct drm_connector_state *connector_state;
d0737e1d 706 int num_encoders = 0;
3165c074 707 int i;
d0737e1d 708
3165c074
ACO		 709 state = crtc_state->base.state;
710
da3ced29
ACO		 711 for_each_connector_in_state(state, connector, connector_state, i) {
712 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 713 continue;
714
da3ced29 715 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 716 num_encoders++;
d0737e1d
ACO		 717 }
718
719 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
720 pipe_name(crtc->pipe));
721
722 BUG_ON(ret == NULL);
723 return ret;
724}
725
1c0b85c5 726#define LC_FREQ 2700
27893390 727#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 728
729#define P_MIN 2
730#define P_MAX 64
731#define P_INC 2
732
733/* Constraints for PLL good behavior */
734#define REF_MIN 48
735#define REF_MAX 400
736#define VCO_MIN 2400
737#define VCO_MAX 4800
738
27893390
DL		 739#define abs_diff(a, b) ({ \
740 typeof(a) __a = (a); \
741 typeof(b) __b = (b); \
742 (void) (&__a == &__b); \
743 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 744
63582983 745struct hsw_wrpll_rnp {
1c0b85c5
DL		 746 unsigned p, n2, r2;
747};
748
63582983 749static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 750{
1c0b85c5
DL		 751 unsigned budget;
752
753 switch (clock) {
754 case 25175000:
755 case 25200000:
756 case 27000000:
757 case 27027000:
758 case 37762500:
759 case 37800000:
760 case 40500000:
761 case 40541000:
762 case 54000000:
763 case 54054000:
764 case 59341000:
765 case 59400000:
766 case 72000000:
767 case 74176000:
768 case 74250000:
769 case 81000000:
770 case 81081000:
771 case 89012000:
772 case 89100000:
773 case 108000000:
774 case 108108000:
775 case 111264000:
776 case 111375000:
777 case 148352000:
778 case 148500000:
779 case 162000000:
780 case 162162000:
781 case 222525000:
782 case 222750000:
783 case 296703000:
784 case 297000000:
785 budget = 0;
786 break;
787 case 233500000:
788 case 245250000:
789 case 247750000:
790 case 253250000:
791 case 298000000:
792 budget = 1500;
793 break;
794 case 169128000:
795 case 169500000:
796 case 179500000:
797 case 202000000:
798 budget = 2000;
799 break;
800 case 256250000:
801 case 262500000:
802 case 270000000:
803 case 272500000:
804 case 273750000:
805 case 280750000:
806 case 281250000:
807 case 286000000:
808 case 291750000:
809 budget = 4000;
810 break;
811 case 267250000:
812 case 268500000:
813 budget = 5000;
814 break;
815 default:
816 budget = 1000;
817 break;
818 }
6441ab5f 819
1c0b85c5
DL		 820 return budget;
821}
822
63582983
DL		 823static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
824 unsigned r2, unsigned n2, unsigned p,
825 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 826{
827 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 828
1c0b85c5
DL		 829 /* No best (r,n,p) yet */
830 if (best->p == 0) {
831 best->p = p;
832 best->n2 = n2;
833 best->r2 = r2;
834 return;
835 }
6441ab5f 836
1c0b85c5
DL		 837 /*
838 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
839 * freq2k.
840 *
841 * delta = 1e6 *
842 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
843 * freq2k;
844 *
845 * and we would like delta <= budget.
846 *
847 * If the discrepancy is above the PPM-based budget, always prefer to
848 * improve upon the previous solution. However, if you're within the
849 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
850 */
851 a = freq2k * budget * p * r2;
852 b = freq2k * budget * best->p * best->r2;
27893390
DL		 853 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
854 diff_best = abs_diff(freq2k * best->p * best->r2,
855 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 856 c = 1000000 * diff;
857 d = 1000000 * diff_best;
858
859 if (a < c && b < d) {
860 /* If both are above the budget, pick the closer */
861 if (best->p * best->r2 * diff < p * r2 * diff_best) {
862 best->p = p;
863 best->n2 = n2;
864 best->r2 = r2;
865 }
866 } else if (a >= c && b < d) {
867 /* If A is below the threshold but B is above it? Update. */
868 best->p = p;
869 best->n2 = n2;
870 best->r2 = r2;
871 } else if (a >= c && b >= d) {
872 /* Both are below the limit, so pick the higher n2/(r2*r2) */
873 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
874 best->p = p;
875 best->n2 = n2;
876 best->r2 = r2;
877 }
878 }
879 /* Otherwise a < c && b >= d, do nothing */
880}
881
f0f59a00
VS		 882static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
883 i915_reg_t reg)
11578553
JB		 884{
885 int refclk = LC_FREQ;
886 int n, p, r;
887 u32 wrpll;
888
889 wrpll = I915_READ(reg);
114fe488
DV		 890 switch (wrpll & WRPLL_PLL_REF_MASK) {
891 case WRPLL_PLL_SSC:
892 case WRPLL_PLL_NON_SSC:
11578553
JB		 893 /*
894 * We could calculate spread here, but our checking
895 * code only cares about 5% accuracy, and spread is a max of
896 * 0.5% downspread.
897 */
898 refclk = 135;
899 break;
114fe488 900 case WRPLL_PLL_LCPLL:
11578553
JB		 901 refclk = LC_FREQ;
902 break;
903 default:
904 WARN(1, "bad wrpll refclk\n");
905 return 0;
906 }
907
908 r = wrpll & WRPLL_DIVIDER_REF_MASK;
909 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
910 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
911
20f0ec16
JB		 912 /* Convert to KHz, p & r have a fixed point portion */
913 return (refclk * n * 100) / (p * r);
11578553
JB		 914}
915
540e732c
S		 916static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
917 uint32_t dpll)
918{
f0f59a00 919 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 920 uint32_t cfgcr1_val, cfgcr2_val;
921 uint32_t p0, p1, p2, dco_freq;
922
923c1241
VS		 923 cfgcr1_reg = DPLL_CFGCR1(dpll);
924 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 925
926 cfgcr1_val = I915_READ(cfgcr1_reg);
927 cfgcr2_val = I915_READ(cfgcr2_reg);
928
929 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
930 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
931
932 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
933 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
934 else
935 p1 = 1;
936
937
938 switch (p0) {
939 case DPLL_CFGCR2_PDIV_1:
940 p0 = 1;
941 break;
942 case DPLL_CFGCR2_PDIV_2:
943 p0 = 2;
944 break;
945 case DPLL_CFGCR2_PDIV_3:
946 p0 = 3;
947 break;
948 case DPLL_CFGCR2_PDIV_7:
949 p0 = 7;
950 break;
951 }
952
953 switch (p2) {
954 case DPLL_CFGCR2_KDIV_5:
955 p2 = 5;
956 break;
957 case DPLL_CFGCR2_KDIV_2:
958 p2 = 2;
959 break;
960 case DPLL_CFGCR2_KDIV_3:
961 p2 = 3;
962 break;
963 case DPLL_CFGCR2_KDIV_1:
964 p2 = 1;
965 break;
966 }
967
968 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
969
970 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
971 1000) / 0x8000;
972
973 return dco_freq / (p0 * p1 * p2 * 5);
974}
975
398a017e
VS		 976static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
977{
978 int dotclock;
979
980 if (pipe_config->has_pch_encoder)
981 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
982 &pipe_config->fdi_m_n);
983 else if (pipe_config->has_dp_encoder)
984 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
985 &pipe_config->dp_m_n);
986 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
987 dotclock = pipe_config->port_clock * 2 / 3;
988 else
989 dotclock = pipe_config->port_clock;
990
991 if (pipe_config->pixel_multiplier)
992 dotclock /= pipe_config->pixel_multiplier;
993
994 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
995}
540e732c
S		 996
997static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 998 struct intel_crtc_state *pipe_config)
540e732c
S		 999{
1000 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1001 int link_clock = 0;
1002 uint32_t dpll_ctl1, dpll;
1003
134ffa44 1004 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1005
1006 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1007
1008 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1009 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1010 } else {
71cd8423
DL		 1011 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1012 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1013
1014 switch (link_clock) {
71cd8423 1015 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1016 link_clock = 81000;
1017 break;
71cd8423 1018 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1019 link_clock = 108000;
1020 break;
71cd8423 1021 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1022 link_clock = 135000;
1023 break;
71cd8423 1024 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1025 link_clock = 162000;
1026 break;
71cd8423 1027 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1028 link_clock = 216000;
1029 break;
71cd8423 1030 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1031 link_clock = 270000;
1032 break;
1033 default:
1034 WARN(1, "Unsupported link rate\n");
1035 break;
1036 }
1037 link_clock *= 2;
1038 }
1039
1040 pipe_config->port_clock = link_clock;
1041
398a017e 1042 ddi_dotclock_get(pipe_config);
540e732c
S		 1043}
1044
3d51278a 1045static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1046 struct intel_crtc_state *pipe_config)
11578553
JB		 1047{
1048 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1049 int link_clock = 0;
1050 u32 val, pll;
1051
26804afd 1052 val = pipe_config->ddi_pll_sel;
11578553
JB		 1053 switch (val & PORT_CLK_SEL_MASK) {
1054 case PORT_CLK_SEL_LCPLL_810:
1055 link_clock = 81000;
1056 break;
1057 case PORT_CLK_SEL_LCPLL_1350:
1058 link_clock = 135000;
1059 break;
1060 case PORT_CLK_SEL_LCPLL_2700:
1061 link_clock = 270000;
1062 break;
1063 case PORT_CLK_SEL_WRPLL1:
01403de3 1064 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1065 break;
1066 case PORT_CLK_SEL_WRPLL2:
01403de3 1067 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1068 break;
1069 case PORT_CLK_SEL_SPLL:
1070 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1071 if (pll == SPLL_PLL_FREQ_810MHz)
1072 link_clock = 81000;
1073 else if (pll == SPLL_PLL_FREQ_1350MHz)
1074 link_clock = 135000;
1075 else if (pll == SPLL_PLL_FREQ_2700MHz)
1076 link_clock = 270000;
1077 else {
1078 WARN(1, "bad spll freq\n");
1079 return;
1080 }
1081 break;
1082 default:
1083 WARN(1, "bad port clock sel\n");
1084 return;
1085 }
1086
1087 pipe_config->port_clock = link_clock * 2;
1088
398a017e 1089 ddi_dotclock_get(pipe_config);
11578553
JB		 1090}
1091
977bb38d
S		 1092static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1093 enum intel_dpll_id dpll)
1094{
aa610dcb
ID		 1095 struct intel_shared_dpll *pll;
1096 struct intel_dpll_hw_state *state;
1097 intel_clock_t clock;
1098
1099 /* For DDI ports we always use a shared PLL. */
1100 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1101 return 0;
1102
1103 pll = &dev_priv->shared_dplls[dpll];
1104 state = &pll->config.hw_state;
1105
1106 clock.m1 = 2;
1107 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1108 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1109 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1110 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1111 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1112 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1113
1114 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1115}
1116
1117static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1118 struct intel_crtc_state *pipe_config)
1119{
1120 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1121 enum port port = intel_ddi_get_encoder_port(encoder);
1122 uint32_t dpll = port;
1123
398a017e 1124 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1125
398a017e 1126 ddi_dotclock_get(pipe_config);
977bb38d
S		 1127}
1128
3d51278a 1129void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1130 struct intel_crtc_state *pipe_config)
3d51278a 1131{
22606a18
DL		 1132 struct drm_device *dev = encoder->base.dev;
1133
1134 if (INTEL_INFO(dev)->gen <= 8)
1135 hsw_ddi_clock_get(encoder, pipe_config);
ef11bdb3 1136 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
22606a18 1137 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1138 else if (IS_BROXTON(dev))
1139 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1140}
1141
1c0b85c5 1142static void
d664c0ce
DL		 1143hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1144 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1145{
1146 uint64_t freq2k;
1147 unsigned p, n2, r2;
63582983 1148 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1149 unsigned budget;
1150
1151 freq2k = clock / 100;
1152
63582983 1153 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1154
1155 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1156 * and directly pass the LC PLL to it. */
1157 if (freq2k == 5400000) {
1158 *n2_out = 2;
1159 *p_out = 1;
1160 *r2_out = 2;
1161 return;
1162 }
1163
1164 /*
1165 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1166 * the WR PLL.
1167 *
1168 * We want R so that REF_MIN <= Ref <= REF_MAX.
1169 * Injecting R2 = 2 * R gives:
1170 * REF_MAX * r2 > LC_FREQ * 2 and
1171 * REF_MIN * r2 < LC_FREQ * 2
1172 *
1173 * Which means the desired boundaries for r2 are:
1174 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1175 *
1176 */
1177 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1178 r2 <= LC_FREQ * 2 / REF_MIN;
1179 r2++) {
1180
1181 /*
1182 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1183 *
1184 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1185 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1186 * VCO_MAX * r2 > n2 * LC_FREQ and
1187 * VCO_MIN * r2 < n2 * LC_FREQ)
1188 *
1189 * Which means the desired boundaries for n2 are:
1190 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1191 */
1192 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1193 n2 <= VCO_MAX * r2 / LC_FREQ;
1194 n2++) {
1195
1196 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1197 hsw_wrpll_update_rnp(freq2k, budget,
1198 r2, n2, p, &best);
1c0b85c5
DL		 1199 }
1200 }
6441ab5f 1201
1c0b85c5
DL		 1202 *n2_out = best.n2;
1203 *p_out = best.p;
1204 *r2_out = best.r2;
6441ab5f
PZ		 1205}
1206
0220ab6e 1207static bool
d664c0ce 1208hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1209 struct intel_crtc_state *crtc_state,
96f3f1f9 1210 struct intel_encoder *intel_encoder)
6441ab5f 1211{
96f3f1f9
VS		 1212 int clock = crtc_state->port_clock;
1213
d664c0ce 1214 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1215 struct intel_shared_dpll *pll;
716c2e55 1216 uint32_t val;
1c0b85c5 1217 unsigned p, n2, r2;
6441ab5f 1218
d664c0ce 1219 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1220
114fe488 1221 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1222 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1223 WRPLL_DIVIDER_POST(p);
1224
dd3cd74a
ACO		 1225 memset(&crtc_state->dpll_hw_state, 0,
1226 sizeof(crtc_state->dpll_hw_state));
1227
190f68c5 1228 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1229
190f68c5 1230 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1231 if (pll == NULL) {
1232 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1233 pipe_name(intel_crtc->pipe));
1234 return false;
0694001b 1235 }
d452c5b6 1236
190f68c5 1237 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
00490c22
ML		 1238 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1239 struct drm_atomic_state *state = crtc_state->base.state;
1240 struct intel_shared_dpll_config *spll =
1241 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1242
1243 if (spll->crtc_mask &&
1244 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1245 return false;
1246
1247 crtc_state->shared_dpll = DPLL_ID_SPLL;
1248 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1249 spll->crtc_mask |= 1 << intel_crtc->pipe;
6441ab5f
PZ		 1250 }
1251
6441ab5f
PZ		 1252 return true;
1253}
1254
dc253813
DL		 1255struct skl_wrpll_context {
1256 uint64_t min_deviation; /* current minimal deviation */
1257 uint64_t central_freq; /* chosen central freq */
1258 uint64_t dco_freq; /* chosen dco freq */
1259 unsigned int p; /* chosen divider */
1260};
1261
1262static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1263{
1264 memset(ctx, 0, sizeof(*ctx));
1265
1266 ctx->min_deviation = U64_MAX;
1267}
1268
1269/* DCO freq must be within +1%/-6% of the DCO central freq */
1270#define SKL_DCO_MAX_PDEVIATION 100
1271#define SKL_DCO_MAX_NDEVIATION 600
1272
1273static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1274 uint64_t central_freq,
1275 uint64_t dco_freq,
1276 unsigned int divider)
1277{
1278 uint64_t deviation;
1279
1280 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1281 central_freq);
1282
1283 /* positive deviation */
1284 if (dco_freq >= central_freq) {
1285 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1286 deviation < ctx->min_deviation) {
1287 ctx->min_deviation = deviation;
1288 ctx->central_freq = central_freq;
1289 ctx->dco_freq = dco_freq;
1290 ctx->p = divider;
1291 }
1292 /* negative deviation */
1293 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1294 deviation < ctx->min_deviation) {
1295 ctx->min_deviation = deviation;
1296 ctx->central_freq = central_freq;
1297 ctx->dco_freq = dco_freq;
1298 ctx->p = divider;
1299 }
dc253813
DL		 1300}
1301
1302static void skl_wrpll_get_multipliers(unsigned int p,
1303 unsigned int *p0 /* out */,
1304 unsigned int *p1 /* out */,
1305 unsigned int *p2 /* out */)
1306{
1307 /* even dividers */
1308 if (p % 2 == 0) {
1309 unsigned int half = p / 2;
1310
1311 if (half == 1 || half == 2 || half == 3 || half == 5) {
1312 *p0 = 2;
1313 *p1 = 1;
1314 *p2 = half;
1315 } else if (half % 2 == 0) {
1316 *p0 = 2;
1317 *p1 = half / 2;
1318 *p2 = 2;
1319 } else if (half % 3 == 0) {
1320 *p0 = 3;
1321 *p1 = half / 3;
1322 *p2 = 2;
1323 } else if (half % 7 == 0) {
1324 *p0 = 7;
1325 *p1 = half / 7;
1326 *p2 = 2;
1327 }
1328 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1329 *p0 = 3;
1330 *p1 = 1;
1331 *p2 = p / 3;
1332 } else if (p == 5 || p == 7) {
1333 *p0 = p;
1334 *p1 = 1;
1335 *p2 = 1;
1336 } else if (p == 15) {
1337 *p0 = 3;
1338 *p1 = 1;
1339 *p2 = 5;
1340 } else if (p == 21) {
1341 *p0 = 7;
1342 *p1 = 1;
1343 *p2 = 3;
1344 } else if (p == 35) {
1345 *p0 = 7;
1346 *p1 = 1;
1347 *p2 = 5;
1348 }
1349}
1350
82d35437
S		 1351struct skl_wrpll_params {
1352 uint32_t dco_fraction;
1353 uint32_t dco_integer;
1354 uint32_t qdiv_ratio;
1355 uint32_t qdiv_mode;
1356 uint32_t kdiv;
1357 uint32_t pdiv;
1358 uint32_t central_freq;
1359};
1360
76516fbc
DL		 1361static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1362 uint64_t afe_clock,
1363 uint64_t central_freq,
1364 uint32_t p0, uint32_t p1, uint32_t p2)
1365{
1366 uint64_t dco_freq;
1367
76516fbc
DL		 1368 switch (central_freq) {
1369 case 9600000000ULL:
1370 params->central_freq = 0;
1371 break;
1372 case 9000000000ULL:
1373 params->central_freq = 1;
1374 break;
1375 case 8400000000ULL:
1376 params->central_freq = 3;
1377 }
1378
1379 switch (p0) {
1380 case 1:
1381 params->pdiv = 0;
1382 break;
1383 case 2:
1384 params->pdiv = 1;
1385 break;
1386 case 3:
1387 params->pdiv = 2;
1388 break;
1389 case 7:
1390 params->pdiv = 4;
1391 break;
1392 default:
1393 WARN(1, "Incorrect PDiv\n");
1394 }
1395
1396 switch (p2) {
1397 case 5:
1398 params->kdiv = 0;
1399 break;
1400 case 2:
1401 params->kdiv = 1;
1402 break;
1403 case 3:
1404 params->kdiv = 2;
1405 break;
1406 case 1:
1407 params->kdiv = 3;
1408 break;
1409 default:
1410 WARN(1, "Incorrect KDiv\n");
1411 }
1412
1413 params->qdiv_ratio = p1;
1414 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1415
1416 dco_freq = p0 * p1 * p2 * afe_clock;
1417
1418 /*
1419 * Intermediate values are in Hz.
1420 * Divide by MHz to match bsepc
1421 */
30a7862d 1422 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1423 params->dco_fraction =
30a7862d
DL		 1424 div_u64((div_u64(dco_freq, 24) -
1425 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1426}
1427
318bd821 1428static bool
82d35437
S		 1429skl_ddi_calculate_wrpll(int clock /* in Hz */,
1430 struct skl_wrpll_params *wrpll_params)
1431{
1432 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1433 uint64_t dco_central_freq[3] = {8400000000ULL,
1434 9000000000ULL,
1435 9600000000ULL};
dc253813
DL		 1436 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1437 24, 28, 30, 32, 36, 40, 42, 44,
1438 48, 52, 54, 56, 60, 64, 66, 68,
1439 70, 72, 76, 78, 80, 84, 88, 90,
1440 92, 96, 98 };
1441 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1442 static const struct {
1443 const int *list;
1444 int n_dividers;
1445 } dividers[] = {
1446 { even_dividers, ARRAY_SIZE(even_dividers) },
1447 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1448 };
1449 struct skl_wrpll_context ctx;
1450 unsigned int dco, d, i;
1451 unsigned int p0, p1, p2;
1452
1453 skl_wrpll_context_init(&ctx);
1454
1455 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1456 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1457 for (i = 0; i < dividers[d].n_dividers; i++) {
1458 unsigned int p = dividers[d].list[i];
1459 uint64_t dco_freq = p * afe_clock;
1460
1461 skl_wrpll_try_divider(&ctx,
1462 dco_central_freq[dco],
1463 dco_freq,
1464 p);
e7ad9878
DL		 1465 /*
1466 * Skip the remaining dividers if we're sure to
1467 * have found the definitive divider, we can't
1468 * improve a 0 deviation.
1469 */
1470 if (ctx.min_deviation == 0)
1471 goto skip_remaining_dividers;
82d35437
S		 1472 }
1473 }
267db663 1474
e7ad9878 1475skip_remaining_dividers:
267db663
DL		 1476 /*
1477 * If a solution is found with an even divider, prefer
1478 * this one.
1479 */
1480 if (d == 0 && ctx.p)
1481 break;
82d35437
S		 1482 }
1483
dc253813
DL		 1484 if (!ctx.p) {
1485 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1486 return false;
dc253813 1487 }
82d35437 1488
dc253813
DL		 1489 /*
1490 * gcc incorrectly analyses that these can be used without being
1491 * initialized. To be fair, it's hard to guess.
1492 */
1493 p0 = p1 = p2 = 0;
1494 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1495 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1496 p0, p1, p2);
318bd821
DL		 1497
1498 return true;
82d35437
S		 1499}
1500
82d35437
S		 1501static bool
1502skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1503 struct intel_crtc_state *crtc_state,
96f3f1f9 1504 struct intel_encoder *intel_encoder)
82d35437
S		 1505{
1506 struct intel_shared_dpll *pll;
1507 uint32_t ctrl1, cfgcr1, cfgcr2;
96f3f1f9 1508 int clock = crtc_state->port_clock;
82d35437
S		 1509
1510 /*
1511 * See comment in intel_dpll_hw_state to understand why we always use 0
1512 * as the DPLL id in this function.
1513 */
1514
1515 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1516
1517 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1518 struct skl_wrpll_params wrpll_params = { 0, };
1519
1520 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1521
318bd821
DL		 1522 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1523 return false;
82d35437
S		 1524
1525 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1526 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1527 wrpll_params.dco_integer;
1528
1529 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1530 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1531 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1532 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1533 wrpll_params.central_freq;
78385cb3
L		 1534 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1535 intel_encoder->type == INTEL_OUTPUT_DP_MST) {
840b32b7
VS		 1536 switch (crtc_state->port_clock / 2) {
1537 case 81000:
71cd8423 1538 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437 1539 break;
840b32b7 1540 case 135000:
71cd8423 1541 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437 1542 break;
840b32b7 1543 case 270000:
71cd8423 1544 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1545 break;
1546 }
1547
1548 cfgcr1 = cfgcr2 = 0;
5a01d5b6 1549 } else if (intel_encoder->type == INTEL_OUTPUT_EDP) {
82d35437 1550 return true;
5a01d5b6
L		 1551 } else
1552 return false;
82d35437 1553
dd3cd74a
ACO		 1554 memset(&crtc_state->dpll_hw_state, 0,
1555 sizeof(crtc_state->dpll_hw_state));
1556
190f68c5
ACO		 1557 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1558 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1559 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1560
190f68c5 1561 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1562 if (pll == NULL) {
1563 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1564 pipe_name(intel_crtc->pipe));
1565 return false;
1566 }
1567
1568 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1569 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1570
1571 return true;
1572}
0220ab6e 1573
d683f3bc
S		 1574/* bxt clock parameters */
1575struct bxt_clk_div {
64987fc5 1576 int clock;
d683f3bc
S		 1577 uint32_t p1;
1578 uint32_t p2;
1579 uint32_t m2_int;
1580 uint32_t m2_frac;
1581 bool m2_frac_en;
1582 uint32_t n;
d683f3bc
S		 1583};
1584
1585/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1586static const struct bxt_clk_div bxt_dp_clk_val[] = {
1587 {162000, 4, 2, 32, 1677722, 1, 1},
1588 {270000, 4, 1, 27, 0, 0, 1},
1589 {540000, 2, 1, 27, 0, 0, 1},
1590 {216000, 3, 2, 32, 1677722, 1, 1},
1591 {243000, 4, 1, 24, 1258291, 1, 1},
1592 {324000, 4, 1, 32, 1677722, 1, 1},
1593 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1594};
1595
1596static bool
1597bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1598 struct intel_crtc_state *crtc_state,
96f3f1f9 1599 struct intel_encoder *intel_encoder)
d683f3bc
S		 1600{
1601 struct intel_shared_dpll *pll;
1602 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1603 int vco = 0;
1604 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1605 uint32_t lanestagger;
96f3f1f9 1606 int clock = crtc_state->port_clock;
d683f3bc
S		 1607
1608 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1609 intel_clock_t best_clock;
1610
1611 /* Calculate HDMI div */
1612 /*
1613 * FIXME: tie the following calculation into
1614 * i9xx_crtc_compute_clock
1615 */
1616 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1617 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1618 clock, pipe_name(intel_crtc->pipe));
1619 return false;
1620 }
1621
1622 clk_div.p1 = best_clock.p1;
1623 clk_div.p2 = best_clock.p2;
1624 WARN_ON(best_clock.m1 != 2);
1625 clk_div.n = best_clock.n;
1626 clk_div.m2_int = best_clock.m2 >> 22;
1627 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1628 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1629
b6dc71f3 1630 vco = best_clock.vco;
d683f3bc
S		 1631 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1632 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1633 int i;
d683f3bc 1634
64987fc5
SJ		 1635 clk_div = bxt_dp_clk_val[0];
1636 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1637 if (bxt_dp_clk_val[i].clock == clock) {
1638 clk_div = bxt_dp_clk_val[i];
1639 break;
1640 }
d683f3bc 1641 }
b6dc71f3
VK		 1642 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1643 }
1644
e6292556 1645 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1646 prop_coef = 4;
1647 int_coef = 9;
1648 gain_ctl = 3;
1649 targ_cnt = 8;
1650 } else if ((vco > 5400000 && vco < 6200000) ||
1651 (vco >= 4800000 && vco < 5400000)) {
1652 prop_coef = 5;
1653 int_coef = 11;
1654 gain_ctl = 3;
1655 targ_cnt = 9;
b6dc71f3
VK		 1656 } else if (vco == 5400000) {
1657 prop_coef = 3;
1658 int_coef = 8;
1659 gain_ctl = 1;
1660 targ_cnt = 9;
1661 } else {
1662 DRM_ERROR("Invalid VCO\n");
1663 return false;
d683f3bc
S		 1664 }
1665
dd3cd74a
ACO		 1666 memset(&crtc_state->dpll_hw_state, 0,
1667 sizeof(crtc_state->dpll_hw_state));
1668
e0681e38
VK		 1669 if (clock > 270000)
1670 lanestagger = 0x18;
1671 else if (clock > 135000)
1672 lanestagger = 0x0d;
1673 else if (clock > 67000)
1674 lanestagger = 0x07;
1675 else if (clock > 33000)
1676 lanestagger = 0x04;
1677 else
1678 lanestagger = 0x02;
1679
d683f3bc
S		 1680 crtc_state->dpll_hw_state.ebb0 =
1681 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1682 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1683 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1684 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1685
1686 if (clk_div.m2_frac_en)
1687 crtc_state->dpll_hw_state.pll3 =
1688 PORT_PLL_M2_FRAC_ENABLE;
1689
1690 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1691 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1692 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1693 PORT_PLL_GAIN_CTL(gain_ctl);
1694
1695 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1696
05712c15
ID		 1697 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1698
e6292556
VK		 1699 crtc_state->dpll_hw_state.pll10 =
1700 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1701 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1702
05712c15
ID		 1703 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1704
d683f3bc 1705 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1706 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1707
1708 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1709 if (pll == NULL) {
1710 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1711 pipe_name(intel_crtc->pipe));
1712 return false;
1713 }
1714
1715 /* shared DPLL id 0 is DPLL A */
1716 crtc_state->ddi_pll_sel = pll->id;
1717
1718 return true;
1719}
1720
0220ab6e
DL		 1721/*
1722 * Tries to find a *shared* PLL for the CRTC and store it in
1723 * intel_crtc->ddi_pll_sel.
1724 *
1725 * For private DPLLs, compute_config() should do the selection for us. This
1726 * function should be folded into compute_config() eventually.
1727 */
190f68c5
ACO		 1728bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1729 struct intel_crtc_state *crtc_state)
0220ab6e 1730{
82d35437 1731 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1732 struct intel_encoder *intel_encoder =
3165c074 1733 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1734
ef11bdb3 1735 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
190f68c5 1736 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1737 intel_encoder);
d683f3bc
S		 1738 else if (IS_BROXTON(dev))
1739 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1740 intel_encoder);
82d35437 1741 else
190f68c5 1742 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1743 intel_encoder);
0220ab6e
DL		 1744}
1745
dae84799
PZ		 1746void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1747{
1748 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1750 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1751 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1752 int type = intel_encoder->type;
1753 uint32_t temp;
1754
0e32b39c 1755 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1756 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1757 switch (intel_crtc->config->pipe_bpp) {
dae84799 1758 case 18:
c9809791 1759 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1760 break;
1761 case 24:
c9809791 1762 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1763 break;
1764 case 30:
c9809791 1765 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1766 break;
1767 case 36:
c9809791 1768 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1769 break;
1770 default:
4e53c2e0 1771 BUG();
dae84799 1772 }
c9809791 1773 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1774 }
1775}
1776
0e32b39c
DA		 1777void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1778{
1779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1780 struct drm_device *dev = crtc->dev;
1781 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1782 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1783 uint32_t temp;
1784 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1785 if (state == true)
1786 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1787 else
1788 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1789 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1790}
1791
8228c251 1792void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1793{
1794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1795 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1796 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1797 struct drm_device *dev = crtc->dev;
1798 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1799 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1800 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1801 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1802 int type = intel_encoder->type;
8d9ddbcb
PZ		 1803 uint32_t temp;
1804
ad80a810
PZ		 1805 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1806 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1807 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1808
6e3c9717 1809 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1810 case 18:
ad80a810 1811 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1812 break;
1813 case 24:
ad80a810 1814 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1815 break;
1816 case 30:
ad80a810 1817 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1818 break;
1819 case 36:
ad80a810 1820 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1821 break;
1822 default:
4e53c2e0 1823 BUG();
dfcef252 1824 }
72662e10 1825
6e3c9717 1826 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1827 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1828 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1829 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1830
e6f0bfc4
PZ		 1831 if (cpu_transcoder == TRANSCODER_EDP) {
1832 switch (pipe) {
1833 case PIPE_A:
c7670b10
PZ		 1834 /* On Haswell, can only use the always-on power well for
1835 * eDP when not using the panel fitter, and when not
1836 * using motion blur mitigation (which we don't
1837 * support). */
fabf6e51 1838 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1839 (intel_crtc->config->pch_pfit.enabled ||
1840 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1841 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1842 else
1843 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1844 break;
1845 case PIPE_B:
1846 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1847 break;
1848 case PIPE_C:
1849 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1850 break;
1851 default:
1852 BUG();
1853 break;
1854 }
1855 }
1856
7739c33b 1857 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1858 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1859 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1860 else
ad80a810 1861 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1862
7739c33b 1863 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1864 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1865 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1866
1867 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1868 type == INTEL_OUTPUT_EDP) {
1869 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1870
0e32b39c
DA		 1871 if (intel_dp->is_mst) {
1872 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1873 } else
1874 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1875
90a6b7b0 1876 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1877 } else if (type == INTEL_OUTPUT_DP_MST) {
1878 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1879
1880 if (intel_dp->is_mst) {
1881 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1882 } else
1883 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1884
90a6b7b0 1885 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1886 } else {
84f44ce7
VS		 1887 WARN(1, "Invalid encoder type %d for pipe %c\n",
1888 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1889 }
1890
ad80a810 1891 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1892}
72662e10 1893
ad80a810
PZ		 1894void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1895 enum transcoder cpu_transcoder)
8d9ddbcb 1896{
f0f59a00 1897 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1898 uint32_t val = I915_READ(reg);
1899
0e32b39c 1900 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1901 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1902 I915_WRITE(reg, val);
72662e10
ED		 1903}
1904
bcbc889b
PZ		 1905bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1906{
1907 struct drm_device *dev = intel_connector->base.dev;
1908 struct drm_i915_private *dev_priv = dev->dev_private;
1909 struct intel_encoder *intel_encoder = intel_connector->encoder;
1910 int type = intel_connector->base.connector_type;
1911 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1912 enum pipe pipe = 0;
1913 enum transcoder cpu_transcoder;
882244a3 1914 enum intel_display_power_domain power_domain;
bcbc889b 1915 uint32_t tmp;
e27daab4 1916 bool ret;
bcbc889b 1917
882244a3 1918 power_domain = intel_display_port_power_domain(intel_encoder);
e27daab4 1919 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
882244a3
PZ		 1920 return false;
1921
e27daab4
ID		 1922 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1923 ret = false;
1924 goto out;
1925 }
bcbc889b
PZ		 1926
1927 if (port == PORT_A)
1928 cpu_transcoder = TRANSCODER_EDP;
1929 else
1a240d4d 1930 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1931
1932 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1933
1934 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1935 case TRANS_DDI_MODE_SELECT_HDMI:
1936 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1937 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1938 break;
bcbc889b
PZ		 1939
1940 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1941 ret = type == DRM_MODE_CONNECTOR_eDP ||
1942 type == DRM_MODE_CONNECTOR_DisplayPort;
1943 break;
1944
0e32b39c
DA		 1945 case TRANS_DDI_MODE_SELECT_DP_MST:
1946 /* if the transcoder is in MST state then
1947 * connector isn't connected */
e27daab4
ID		 1948 ret = false;
1949 break;
bcbc889b
PZ		 1950
1951 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1952 ret = type == DRM_MODE_CONNECTOR_VGA;
1953 break;
bcbc889b
PZ		 1954
1955 default:
e27daab4
ID		 1956 ret = false;
1957 break;
bcbc889b 1958 }
e27daab4
ID		 1959
1960out:
1961 intel_display_power_put(dev_priv, power_domain);
1962
1963 return ret;
bcbc889b
PZ		 1964}
1965
85234cdc
DV		 1966bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1967 enum pipe *pipe)
1968{
1969 struct drm_device *dev = encoder->base.dev;
1970 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1971 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1972 enum intel_display_power_domain power_domain;
85234cdc
DV		 1973 u32 tmp;
1974 int i;
e27daab4 1975 bool ret;
85234cdc 1976
6d129bea 1977 power_domain = intel_display_port_power_domain(encoder);
e27daab4 1978 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 1979 return false;
1980
e27daab4
ID		 1981 ret = false;
1982
fe43d3f5 1983 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1984
1985 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1986 goto out;
85234cdc 1987
ad80a810
PZ		 1988 if (port == PORT_A) {
1989 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1990
ad80a810
PZ		 1991 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1992 case TRANS_DDI_EDP_INPUT_A_ON:
1993 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1994 *pipe = PIPE_A;
1995 break;
1996 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1997 *pipe = PIPE_B;
1998 break;
1999 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2000 *pipe = PIPE_C;
2001 break;
2002 }
2003
e27daab4 2004 ret = true;
ad80a810 2005
e27daab4
ID		 2006 goto out;
2007 }
0e32b39c 2008
e27daab4
ID		 2009 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2010 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2011
2012 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
2013 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2014 TRANS_DDI_MODE_SELECT_DP_MST)
2015 goto out;
2016
2017 *pipe = i;
2018 ret = true;
2019
2020 goto out;
85234cdc
DV		 2021 }
2022 }
2023
84f44ce7 2024 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2025
e27daab4
ID		 2026out:
2027 intel_display_power_put(dev_priv, power_domain);
2028
2029 return ret;
85234cdc
DV		 2030}
2031
fc914639
PZ		 2032void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2033{
2034 struct drm_crtc *crtc = &intel_crtc->base;
7d4aefd0
SS		 2035 struct drm_device *dev = crtc->dev;
2036 struct drm_i915_private *dev_priv = dev->dev_private;
fc914639
PZ		 2037 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2038 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2039 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2040
bb523fc0
PZ		 2041 if (cpu_transcoder != TRANSCODER_EDP)
2042 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2043 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2044}
2045
2046void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2047{
2048 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2049 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2050
bb523fc0
PZ		 2051 if (cpu_transcoder != TRANSCODER_EDP)
2052 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2053 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2054}
2055
78ab0bae
VS		 2056static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2057 u32 level, enum port port, int type)
f8896f5d 2058{
f8896f5d
DW		 2059 const struct ddi_buf_trans *ddi_translations;
2060 uint8_t iboost;
75067dde 2061 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2062 int n_entries;
2063 u32 reg;
2064
75067dde
AK		 2065 /* VBT may override standard boost values */
2066 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2067 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2068
f8896f5d 2069 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2070 if (dp_iboost) {
2071 iboost = dp_iboost;
2072 } else {
78ab0bae 2073 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
e4d4c05b 2074 iboost = ddi_translations[level].i_boost;
75067dde 2075 }
f8896f5d 2076 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2077 if (dp_iboost) {
2078 iboost = dp_iboost;
2079 } else {
78ab0bae 2080 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 2081
2082 if (WARN_ON(port != PORT_A &&
2083 port != PORT_E && n_entries > 9))
2084 n_entries = 9;
2085
e4d4c05b 2086 iboost = ddi_translations[level].i_boost;
75067dde 2087 }
f8896f5d 2088 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2089 if (hdmi_iboost) {
2090 iboost = hdmi_iboost;
2091 } else {
78ab0bae 2092 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 2093 iboost = ddi_translations[level].i_boost;
75067dde 2094 }
f8896f5d
DW		 2095 } else {
2096 return;
2097 }
2098
2099 /* Make sure that the requested I_boost is valid */
2100 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2101 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2102 return;
2103 }
2104
2105 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2106 reg &= ~BALANCE_LEG_MASK(port);
2107 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2108
2109 if (iboost)
2110 reg |= iboost << BALANCE_LEG_SHIFT(port);
2111 else
2112 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2113
2114 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2115}
2116
78ab0bae
VS		 2117static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
2118 u32 level, enum port port, int type)
96fb9f9b 2119{
96fb9f9b
VK		 2120 const struct bxt_ddi_buf_trans *ddi_translations;
2121 u32 n_entries, i;
2122 uint32_t val;
2123
d9d7000d
SJ		 2124 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2125 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2126 ddi_translations = bxt_ddi_translations_edp;
2127 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2128 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 2129 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2130 ddi_translations = bxt_ddi_translations_dp;
2131 } else if (type == INTEL_OUTPUT_HDMI) {
2132 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2133 ddi_translations = bxt_ddi_translations_hdmi;
2134 } else {
2135 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2136 type);
2137 return;
2138 }
2139
2140 /* Check if default value has to be used */
2141 if (level >= n_entries ||
2142 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2143 for (i = 0; i < n_entries; i++) {
2144 if (ddi_translations[i].default_index) {
2145 level = i;
2146 break;
2147 }
2148 }
2149 }
2150
2151 /*
2152 * While we write to the group register to program all lanes at once we
2153 * can read only lane registers and we pick lanes 0/1 for that.
2154 */
2155 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2156 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2157 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2158
2159 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2160 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2161 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2162 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2163 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2164
2165 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
9c58a049 2166 val &= ~SCALE_DCOMP_METHOD;
96fb9f9b 2167 if (ddi_translations[level].enable)
9c58a049
SJ		 2168 val |= SCALE_DCOMP_METHOD;
2169
2170 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2171 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2172
96fb9f9b
VK		 2173 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2174
2175 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2176 val &= ~DE_EMPHASIS;
2177 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2178 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2179
2180 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2181 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2182 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2183}
2184
f8896f5d
DW		 2185static uint32_t translate_signal_level(int signal_levels)
2186{
2187 uint32_t level;
2188
2189 switch (signal_levels) {
2190 default:
2191 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2192 signal_levels);
2193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2194 level = 0;
2195 break;
2196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2197 level = 1;
2198 break;
2199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2200 level = 2;
2201 break;
2202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2203 level = 3;
2204 break;
2205
2206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2207 level = 4;
2208 break;
2209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2210 level = 5;
2211 break;
2212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2213 level = 6;
2214 break;
2215
2216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2217 level = 7;
2218 break;
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2220 level = 8;
2221 break;
2222
2223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2224 level = 9;
2225 break;
2226 }
2227
2228 return level;
2229}
2230
2231uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2232{
2233 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2234 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d
DW		 2235 struct intel_encoder *encoder = &dport->base;
2236 uint8_t train_set = intel_dp->train_set[0];
2237 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2238 DP_TRAIN_PRE_EMPHASIS_MASK);
2239 enum port port = dport->port;
2240 uint32_t level;
2241
2242 level = translate_signal_level(signal_levels);
2243
78ab0bae
VS		 2244 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2245 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
2246 else if (IS_BROXTON(dev_priv))
2247 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
f8896f5d
DW		 2248
2249 return DDI_BUF_TRANS_SELECT(level);
2250}
2251
e404ba8d
VS		 2252void intel_ddi_clk_select(struct intel_encoder *encoder,
2253 const struct intel_crtc_state *pipe_config)
6441ab5f 2254{
e404ba8d
VS		 2255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2256 enum port port = intel_ddi_get_encoder_port(encoder);
6441ab5f 2257
e404ba8d
VS		 2258 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2259 uint32_t dpll = pipe_config->ddi_pll_sel;
efa80add
S		 2260 uint32_t val;
2261
5416d871
DL		 2262 /*
2263 * DPLL0 is used for eDP and is the only "private" DPLL (as
2264 * opposed to shared) on SKL
2265 */
e404ba8d 2266 if (encoder->type == INTEL_OUTPUT_EDP) {
5416d871
DL		 2267 WARN_ON(dpll != SKL_DPLL0);
2268
2269 val = I915_READ(DPLL_CTRL1);
2270
2271 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2272 DPLL_CTRL1_SSC(dpll) |
71cd8423 2273 DPLL_CTRL1_LINK_RATE_MASK(dpll));
e404ba8d 2274 val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2275
2276 I915_WRITE(DPLL_CTRL1, val);
2277 POSTING_READ(DPLL_CTRL1);
2278 }
2279
2280 /* DDI -> PLL mapping */
efa80add
S		 2281 val = I915_READ(DPLL_CTRL2);
2282
2283 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2284 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2285 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2286 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2287
2288 I915_WRITE(DPLL_CTRL2, val);
5416d871 2289
e404ba8d
VS		 2290 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2291 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2292 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
efa80add 2293 }
e404ba8d
VS		 2294}
2295
2296static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2297{
2298 struct drm_encoder *encoder = &intel_encoder->base;
6a7e4f99 2299 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
e404ba8d
VS		 2300 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2301 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2302 int type = intel_encoder->type;
6a7e4f99
VS		 2303
2304 intel_prepare_ddi_buffer(intel_encoder);
e404ba8d
VS		 2305
2306 if (type == INTEL_OUTPUT_EDP) {
2307 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2308 intel_edp_panel_on(intel_dp);
2309 }
2310
2311 intel_ddi_clk_select(intel_encoder, crtc->config);
c19b0669 2312
82a4d9c0 2313 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2314 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2315
901c2daf
VS		 2316 intel_dp_set_link_params(intel_dp, crtc->config);
2317
44905a27 2318 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2319
2320 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2321 intel_dp_start_link_train(intel_dp);
6a7e4f99 2322 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
3ab9c637 2323 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2324 } else if (type == INTEL_OUTPUT_HDMI) {
2325 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2326
2327 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2328 crtc->config->has_hdmi_sink,
2329 &crtc->config->base.adjusted_mode);
c19b0669 2330 }
6441ab5f
PZ		 2331}
2332
00c09d70 2333static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2334{
2335 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2336 struct drm_device *dev = encoder->dev;
2337 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2338 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2339 int type = intel_encoder->type;
2886e93f 2340 uint32_t val;
a836bdf9 2341 bool wait = false;
2886e93f
PZ		 2342
2343 val = I915_READ(DDI_BUF_CTL(port));
2344 if (val & DDI_BUF_CTL_ENABLE) {
2345 val &= ~DDI_BUF_CTL_ENABLE;
2346 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2347 wait = true;
2886e93f 2348 }
6441ab5f 2349
a836bdf9
PZ		 2350 val = I915_READ(DP_TP_CTL(port));
2351 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2352 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2353 I915_WRITE(DP_TP_CTL(port), val);
2354
2355 if (wait)
2356 intel_wait_ddi_buf_idle(dev_priv, port);
2357
76bb80ed 2358 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2359 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2360 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2361 intel_edp_panel_vdd_on(intel_dp);
4be73780 2362 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2363 }
2364
ef11bdb3 2365 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
efa80add
S		 2366 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2367 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2368 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2369 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2370}
2371
00c09d70 2372static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2373{
6547fef8 2374 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2375 struct drm_crtc *crtc = encoder->crtc;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2377 struct drm_device *dev = encoder->dev;
72662e10 2378 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2379 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2380 int type = intel_encoder->type;
72662e10 2381
6547fef8 2382 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2383 struct intel_digital_port *intel_dig_port =
2384 enc_to_dig_port(encoder);
2385
6547fef8
PZ		 2386 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2387 * are ignored so nothing special needs to be done besides
2388 * enabling the port.
2389 */
876a8cdf 2390 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2391 intel_dig_port->saved_port_bits |
2392 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2393 } else if (type == INTEL_OUTPUT_EDP) {
2394 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2395
23f08d83 2396 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2397 intel_dp_stop_link_train(intel_dp);
2398
4be73780 2399 intel_edp_backlight_on(intel_dp);
0bc12bcb 2400 intel_psr_enable(intel_dp);
c395578e 2401 intel_edp_drrs_enable(intel_dp);
6547fef8 2402 }
7b9f35a6 2403
6e3c9717 2404 if (intel_crtc->config->has_audio) {
d45a0bf5 2405 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2406 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2407 }
5ab432ef
DV		 2408}
2409
00c09d70 2410static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2411{
d6c50ff8 2412 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2413 struct drm_crtc *crtc = encoder->crtc;
2414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2415 int type = intel_encoder->type;
7b9f35a6
WX		 2416 struct drm_device *dev = encoder->dev;
2417 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2418
6e3c9717 2419 if (intel_crtc->config->has_audio) {
69bfe1a9 2420 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2421 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2422 }
2831d842 2423
d6c50ff8
PZ		 2424 if (type == INTEL_OUTPUT_EDP) {
2425 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2426
c395578e 2427 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2428 intel_psr_disable(intel_dp);
4be73780 2429 intel_edp_backlight_off(intel_dp);
d6c50ff8 2430 }
72662e10 2431}
79f689aa 2432
00490c22 2433static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
e0b01be4
DV		 2434 struct intel_shared_dpll *pll)
2435{
3e369b76 2436 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2437 POSTING_READ(WRPLL_CTL(pll->id));
2438 udelay(20);
2439}
2440
00490c22 2441static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
12030431 2442 struct intel_shared_dpll *pll)
00490c22
ML		 2443{
2444 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2445 POSTING_READ(SPLL_CTL);
2446 udelay(20);
2447}
2448
2449static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2450 struct intel_shared_dpll *pll)
12030431
DV		 2451{
2452 uint32_t val;
2453
2454 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2455 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2456 POSTING_READ(WRPLL_CTL(pll->id));
2457}
2458
00490c22
ML		 2459static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2460 struct intel_shared_dpll *pll)
2461{
2462 uint32_t val;
2463
2464 val = I915_READ(SPLL_CTL);
2465 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2466 POSTING_READ(SPLL_CTL);
2467}
2468
2469static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2470 struct intel_shared_dpll *pll,
2471 struct intel_dpll_hw_state *hw_state)
d452c5b6
DV		 2472{
2473 uint32_t val;
2474
e27daab4 2475 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2476 return false;
2477
2478 val = I915_READ(WRPLL_CTL(pll->id));
2479 hw_state->wrpll = val;
2480
e27daab4
ID		 2481 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2482
d452c5b6
DV		 2483 return val & WRPLL_PLL_ENABLE;
2484}
2485
00490c22
ML		 2486static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2487 struct intel_shared_dpll *pll,
2488 struct intel_dpll_hw_state *hw_state)
2489{
2490 uint32_t val;
2491
e27daab4 2492 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
00490c22
ML		 2493 return false;
2494
2495 val = I915_READ(SPLL_CTL);
2496 hw_state->spll = val;
2497
e27daab4
ID		 2498 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2499
00490c22
ML		 2500 return val & SPLL_PLL_ENABLE;
2501}
2502
2503
ca1381b5 2504static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2505 "WRPLL 1",
2506 "WRPLL 2",
00490c22 2507 "SPLL"
9cd86933
DV		 2508};
2509
143b307c 2510static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2511{
9cd86933
DV		 2512 int i;
2513
00490c22 2514 dev_priv->num_shared_dpll = 3;
9cd86933 2515
00490c22 2516 for (i = 0; i < 2; i++) {
9cd86933
DV		 2517 dev_priv->shared_dplls[i].id = i;
2518 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
00490c22
ML		 2519 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2520 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
d452c5b6 2521 dev_priv->shared_dplls[i].get_hw_state =
00490c22 2522 hsw_ddi_wrpll_get_hw_state;
9cd86933 2523 }
00490c22
ML		 2524
2525 /* SPLL is special, but needs to be initialized anyway.. */
2526 dev_priv->shared_dplls[i].id = i;
2527 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2528 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2529 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2530 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2531
143b307c
DL		 2532}
2533
d1a2dc78
S		 2534static const char * const skl_ddi_pll_names[] = {
2535 "DPLL 1",
2536 "DPLL 2",
2537 "DPLL 3",
2538};
2539
2540struct skl_dpll_regs {
f0f59a00 2541 i915_reg_t ctl, cfgcr1, cfgcr2;
d1a2dc78
S		 2542};
2543
2544/* this array is indexed by the *shared* pll id */
2545static const struct skl_dpll_regs skl_dpll_regs[3] = {
2546 {
2547 /* DPLL 1 */
2548 .ctl = LCPLL2_CTL,
923c1241
VS		 2549 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2550 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
d1a2dc78
S		 2551 },
2552 {
2553 /* DPLL 2 */
01403de3 2554 .ctl = WRPLL_CTL(0),
923c1241
VS		 2555 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2556 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
d1a2dc78
S		 2557 },
2558 {
2559 /* DPLL 3 */
01403de3 2560 .ctl = WRPLL_CTL(1),
923c1241
VS		 2561 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2562 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
d1a2dc78
S		 2563 },
2564};
2565
2566static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2567 struct intel_shared_dpll *pll)
2568{
2569 uint32_t val;
2570 unsigned int dpll;
2571 const struct skl_dpll_regs *regs = skl_dpll_regs;
2572
2573 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2574 dpll = pll->id + 1;
2575
2576 val = I915_READ(DPLL_CTRL1);
2577
2578 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2579 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2580 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2581
2582 I915_WRITE(DPLL_CTRL1, val);
2583 POSTING_READ(DPLL_CTRL1);
2584
2585 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2586 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2587 POSTING_READ(regs[pll->id].cfgcr1);
2588 POSTING_READ(regs[pll->id].cfgcr2);
2589
2590 /* the enable bit is always bit 31 */
2591 I915_WRITE(regs[pll->id].ctl,
2592 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2593
2594 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2595 DRM_ERROR("DPLL %d not locked\n", dpll);
2596}
2597
2598static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2599 struct intel_shared_dpll *pll)
2600{
2601 const struct skl_dpll_regs *regs = skl_dpll_regs;
2602
2603 /* the enable bit is always bit 31 */
2604 I915_WRITE(regs[pll->id].ctl,
2605 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2606 POSTING_READ(regs[pll->id].ctl);
2607}
2608
2609static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2610 struct intel_shared_dpll *pll,
2611 struct intel_dpll_hw_state *hw_state)
2612{
2613 uint32_t val;
2614 unsigned int dpll;
2615 const struct skl_dpll_regs *regs = skl_dpll_regs;
e27daab4 2616 bool ret;
d1a2dc78 2617
e27daab4 2618 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
d1a2dc78
S		 2619 return false;
2620
e27daab4
ID		 2621 ret = false;
2622
d1a2dc78
S		 2623 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2624 dpll = pll->id + 1;
2625
2626 val = I915_READ(regs[pll->id].ctl);
2627 if (!(val & LCPLL_PLL_ENABLE))
e27daab4 2628 goto out;
d1a2dc78
S		 2629
2630 val = I915_READ(DPLL_CTRL1);
2631 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2632
2633 /* avoid reading back stale values if HDMI mode is not enabled */
2634 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2635 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2636 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2637 }
e27daab4 2638 ret = true;
d1a2dc78 2639
e27daab4
ID		 2640out:
2641 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2642
2643 return ret;
d1a2dc78
S		 2644}
2645
2646static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2647{
2648 int i;
2649
2650 dev_priv->num_shared_dpll = 3;
2651
2652 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2653 dev_priv->shared_dplls[i].id = i;
2654 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2655 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2656 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2657 dev_priv->shared_dplls[i].get_hw_state =
2658 skl_ddi_pll_get_hw_state;
2659 }
2660}
2661
5c6706e5
VK		 2662static void broxton_phy_init(struct drm_i915_private *dev_priv,
2663 enum dpio_phy phy)
2664{
2665 enum port port;
2666 uint32_t val;
2667
2668 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2669 val |= GT_DISPLAY_POWER_ON(phy);
2670 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2671
2672 /* Considering 10ms timeout until BSpec is updated */
2673 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2674 DRM_ERROR("timeout during PHY%d power on\n", phy);
2675
2676 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2677 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2678 int lane;
2679
2680 for (lane = 0; lane < 4; lane++) {
2681 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2682 /*
2683 * Note that on CHV this flag is called UPAR, but has
2684 * the same function.
2685 */
2686 val &= ~LATENCY_OPTIM;
2687 if (lane != 1)
2688 val |= LATENCY_OPTIM;
2689
2690 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2691 }
2692 }
2693
2694 /* Program PLL Rcomp code offset */
2695 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2696 val &= ~IREF0RC_OFFSET_MASK;
2697 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2698 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2699
2700 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2701 val &= ~IREF1RC_OFFSET_MASK;
2702 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2703 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2704
2705 /* Program power gating */
2706 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2707 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2708 SUS_CLK_CONFIG;
2709 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2710
2711 if (phy == DPIO_PHY0) {
2712 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2713 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2714 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2715 }
2716
2717 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2718 val &= ~OCL2_LDOFUSE_PWR_DIS;
2719 /*
2720 * On PHY1 disable power on the second channel, since no port is
2721 * connected there. On PHY0 both channels have a port, so leave it
2722 * enabled.
2723 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2724 * power down the second channel on PHY0 as well.
2725 */
2726 if (phy == DPIO_PHY1)
2727 val |= OCL2_LDOFUSE_PWR_DIS;
2728 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2729
2730 if (phy == DPIO_PHY0) {
2731 uint32_t grc_code;
2732 /*
2733 * PHY0 isn't connected to an RCOMP resistor so copy over
2734 * the corresponding calibrated value from PHY1, and disable
2735 * the automatic calibration on PHY0.
2736 */
2737 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2738 10))
2739 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2740
2741 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2742 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2743 grc_code = val << GRC_CODE_FAST_SHIFT |
2744 val << GRC_CODE_SLOW_SHIFT |
2745 val;
2746 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2747
2748 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2749 val |= GRC_DIS | GRC_RDY_OVRD;
2750 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2751 }
2752
2753 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2754 val |= COMMON_RESET_DIS;
2755 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2756}
2757
2758void broxton_ddi_phy_init(struct drm_device *dev)
2759{
2760 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2761 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2762 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2763}
2764
2765static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2766 enum dpio_phy phy)
2767{
2768 uint32_t val;
2769
2770 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2771 val &= ~COMMON_RESET_DIS;
2772 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2773}
2774
2775void broxton_ddi_phy_uninit(struct drm_device *dev)
2776{
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778
2779 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2780 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2781
2782 /* FIXME: do this in broxton_phy_uninit per phy */
2783 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2784}
2785
dfb82408
S		 2786static const char * const bxt_ddi_pll_names[] = {
2787 "PORT PLL A",
2788 "PORT PLL B",
2789 "PORT PLL C",
2790};
2791
2792static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2793 struct intel_shared_dpll *pll)
2794{
2795 uint32_t temp;
2796 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2797
2798 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2799 temp &= ~PORT_PLL_REF_SEL;
2800 /* Non-SSC reference */
2801 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2802
2803 /* Disable 10 bit clock */
2804 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2805 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2806 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2807
2808 /* Write P1 & P2 */
2809 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2810 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2811 temp |= pll->config.hw_state.ebb0;
2812 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2813
2814 /* Write M2 integer */
2815 temp = I915_READ(BXT_PORT_PLL(port, 0));
2816 temp &= ~PORT_PLL_M2_MASK;
2817 temp |= pll->config.hw_state.pll0;
2818 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2819
2820 /* Write N */
2821 temp = I915_READ(BXT_PORT_PLL(port, 1));
2822 temp &= ~PORT_PLL_N_MASK;
2823 temp |= pll->config.hw_state.pll1;
2824 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2825
2826 /* Write M2 fraction */
2827 temp = I915_READ(BXT_PORT_PLL(port, 2));
2828 temp &= ~PORT_PLL_M2_FRAC_MASK;
2829 temp |= pll->config.hw_state.pll2;
2830 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2831
2832 /* Write M2 fraction enable */
2833 temp = I915_READ(BXT_PORT_PLL(port, 3));
2834 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2835 temp |= pll->config.hw_state.pll3;
2836 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2837
2838 /* Write coeff */
2839 temp = I915_READ(BXT_PORT_PLL(port, 6));
2840 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2841 temp &= ~PORT_PLL_INT_COEFF_MASK;
2842 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2843 temp |= pll->config.hw_state.pll6;
2844 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2845
2846 /* Write calibration val */
2847 temp = I915_READ(BXT_PORT_PLL(port, 8));
2848 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2849 temp |= pll->config.hw_state.pll8;
2850 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2851
b6dc71f3
VK		 2852 temp = I915_READ(BXT_PORT_PLL(port, 9));
2853 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2854 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2855 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2856
2857 temp = I915_READ(BXT_PORT_PLL(port, 10));
2858 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2859 temp &= ~PORT_PLL_DCO_AMP_MASK;
2860 temp |= pll->config.hw_state.pll10;
2861 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2862
2863 /* Recalibrate with new settings */
2864 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2865 temp |= PORT_PLL_RECALIBRATE;
2866 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2867 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2868 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2869 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2870
2871 /* Enable PLL */
2872 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2873 temp |= PORT_PLL_ENABLE;
2874 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2875 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2876
2877 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2878 PORT_PLL_LOCK), 200))
2879 DRM_ERROR("PLL %d not locked\n", port);
2880
2881 /*
2882 * While we write to the group register to program all lanes at once we
2883 * can read only lane registers and we pick lanes 0/1 for that.
2884 */
2885 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2886 temp &= ~LANE_STAGGER_MASK;
2887 temp &= ~LANESTAGGER_STRAP_OVRD;
2888 temp |= pll->config.hw_state.pcsdw12;
2889 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2890}
2891
2892static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2893 struct intel_shared_dpll *pll)
2894{
2895 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2896 uint32_t temp;
2897
2898 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2899 temp &= ~PORT_PLL_ENABLE;
2900 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2901 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2902}
2903
2904static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2905 struct intel_shared_dpll *pll,
2906 struct intel_dpll_hw_state *hw_state)
2907{
2908 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2909 uint32_t val;
e27daab4 2910 bool ret;
dfb82408 2911
e27daab4 2912 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
dfb82408
S		 2913 return false;
2914
e27daab4
ID		 2915 ret = false;
2916
dfb82408
S		 2917 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2918 if (!(val & PORT_PLL_ENABLE))
e27daab4 2919 goto out;
dfb82408
S		 2920
2921 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2922 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2923
05712c15
ID		 2924 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2925 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2926
dfb82408 2927 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2928 hw_state->pll0 &= PORT_PLL_M2_MASK;
2929
dfb82408 2930 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2931 hw_state->pll1 &= PORT_PLL_N_MASK;
2932
dfb82408 2933 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2934 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2935
dfb82408 2936 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2937 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2938
dfb82408 2939 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2940 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2941 PORT_PLL_INT_COEFF_MASK |
2942 PORT_PLL_GAIN_CTL_MASK;
2943
dfb82408 2944 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2945 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2946
05712c15
ID		 2947 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2948 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2949
b6dc71f3 2950 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2951 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2952 PORT_PLL_DCO_AMP_MASK;
2953
dfb82408
S		 2954 /*
2955 * While we write to the group register to program all lanes at once we
2956 * can read only lane registers. We configure all lanes the same way, so
2957 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2958 */
2959 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
b5dada82 2960 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
dfb82408
S		 2961 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2962 hw_state->pcsdw12,
2963 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2964 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408 2965
e27daab4
ID		 2966 ret = true;
2967
2968out:
2969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
2970
2971 return ret;
dfb82408
S		 2972}
2973
2974static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2975{
2976 int i;
2977
2978 dev_priv->num_shared_dpll = 3;
2979
2980 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2981 dev_priv->shared_dplls[i].id = i;
2982 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2983 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2984 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2985 dev_priv->shared_dplls[i].get_hw_state =
2986 bxt_ddi_pll_get_hw_state;
2987 }
2988}
2989
143b307c
DL		 2990void intel_ddi_pll_init(struct drm_device *dev)
2991{
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 uint32_t val = I915_READ(LCPLL_CTL);
2994
ef11bdb3 2995 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
d1a2dc78 2996 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2997 else if (IS_BROXTON(dev))
2998 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2999 else
3000 hsw_shared_dplls_init(dev_priv);
79f689aa 3001
ef11bdb3 3002 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
d9062ae5
DL		 3003 int cdclk_freq;
3004
3005 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 3006 dev_priv->skl_boot_cdclk = cdclk_freq;
c73666f3
SK		 3007 if (skl_sanitize_cdclk(dev_priv))
3008 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
2f693e28
DL		 3009 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
3010 DRM_ERROR("LCPLL1 is disabled\n");
f8437dd1
VK		 3011 } else if (IS_BROXTON(dev)) {
3012 broxton_init_cdclk(dev);
5c6706e5 3013 broxton_ddi_phy_init(dev);
121643c2
S		 3014 } else {
3015 /*
3016 * The LCPLL register should be turned on by the BIOS. For now
3017 * let's just check its state and print errors in case
3018 * something is wrong. Don't even try to turn it on.
3019 */
3020
3021 if (val & LCPLL_CD_SOURCE_FCLK)
3022 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 3023
121643c2
S		 3024 if (val & LCPLL_PLL_DISABLE)
3025 DRM_ERROR("LCPLL is disabled\n");
3026 }
79f689aa 3027}
c19b0669 3028
ad64217b 3029void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3030{
ad64217b
ACO		 3031 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3032 struct drm_i915_private *dev_priv =
3033 to_i915(intel_dig_port->base.base.dev);
174edf1f 3034 enum port port = intel_dig_port->port;
c19b0669 3035 uint32_t val;
f3e227df 3036 bool wait = false;
c19b0669
PZ		 3037
3038 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3039 val = I915_READ(DDI_BUF_CTL(port));
3040 if (val & DDI_BUF_CTL_ENABLE) {
3041 val &= ~DDI_BUF_CTL_ENABLE;
3042 I915_WRITE(DDI_BUF_CTL(port), val);
3043 wait = true;
3044 }
3045
3046 val = I915_READ(DP_TP_CTL(port));
3047 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3048 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3049 I915_WRITE(DP_TP_CTL(port), val);
3050 POSTING_READ(DP_TP_CTL(port));
3051
3052 if (wait)
3053 intel_wait_ddi_buf_idle(dev_priv, port);
3054 }
3055
0e32b39c 3056 val = DP_TP_CTL_ENABLE |
c19b0669 3057 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 3058 if (intel_dp->is_mst)
3059 val |= DP_TP_CTL_MODE_MST;
3060 else {
3061 val |= DP_TP_CTL_MODE_SST;
3062 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3063 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3064 }
c19b0669
PZ		 3065 I915_WRITE(DP_TP_CTL(port), val);
3066 POSTING_READ(DP_TP_CTL(port));
3067
3068 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3069 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3070 POSTING_READ(DDI_BUF_CTL(port));
3071
3072 udelay(600);
3073}
00c09d70 3074
1ad960f2
PZ		 3075void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3076{
3077 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3078 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3079 uint32_t val;
3080
3081 intel_ddi_post_disable(intel_encoder);
3082
eede3b53 3083 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3084 val &= ~FDI_RX_ENABLE;
eede3b53 3085 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 3086
eede3b53 3087 val = I915_READ(FDI_RX_MISC(PIPE_A));
1ad960f2
PZ		 3088 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3089 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53 3090 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1ad960f2 3091
eede3b53 3092 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3093 val &= ~FDI_PCDCLK;
eede3b53 3094 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 3095
eede3b53 3096 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3097 val &= ~FDI_RX_PLL_ENABLE;
eede3b53 3098 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2
PZ		 3099}
3100
3d52ccf5
LY		 3101bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3102 struct intel_crtc *intel_crtc)
3103{
3104 u32 temp;
3105
e27daab4 3106 if (intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3d52ccf5 3107 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
e27daab4
ID		 3108
3109 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
3110
3d52ccf5
LY		 3111 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3112 return true;
3113 }
e27daab4 3114
3d52ccf5
LY		 3115 return false;
3116}
3117
6801c18c 3118void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3119 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3120{
3121 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3122 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3123 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3124 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3125 u32 temp, flags = 0;
3126
3127 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3128 if (temp & TRANS_DDI_PHSYNC)
3129 flags |= DRM_MODE_FLAG_PHSYNC;
3130 else
3131 flags |= DRM_MODE_FLAG_NHSYNC;
3132 if (temp & TRANS_DDI_PVSYNC)
3133 flags |= DRM_MODE_FLAG_PVSYNC;
3134 else
3135 flags |= DRM_MODE_FLAG_NVSYNC;
3136
2d112de7 3137 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3138
3139 switch (temp & TRANS_DDI_BPC_MASK) {
3140 case TRANS_DDI_BPC_6:
3141 pipe_config->pipe_bpp = 18;
3142 break;
3143 case TRANS_DDI_BPC_8:
3144 pipe_config->pipe_bpp = 24;
3145 break;
3146 case TRANS_DDI_BPC_10:
3147 pipe_config->pipe_bpp = 30;
3148 break;
3149 case TRANS_DDI_BPC_12:
3150 pipe_config->pipe_bpp = 36;
3151 break;
3152 default:
3153 break;
3154 }
eb14cb74
VS		 3155
3156 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3157 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3158 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3159 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3160
cda0aaaf 3161 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 3162 pipe_config->has_infoframe = true;
cbc572a9 3163 break;
eb14cb74
VS		 3164 case TRANS_DDI_MODE_SELECT_DVI:
3165 case TRANS_DDI_MODE_SELECT_FDI:
3166 break;
3167 case TRANS_DDI_MODE_SELECT_DP_SST:
3168 case TRANS_DDI_MODE_SELECT_DP_MST:
3169 pipe_config->has_dp_encoder = true;
90a6b7b0
VS		 3170 pipe_config->lane_count =
3171 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3172 intel_dp_get_m_n(intel_crtc, pipe_config);
3173 break;
3174 default:
3175 break;
3176 }
10214420 3177
3d52ccf5
LY		 3178 pipe_config->has_audio =
3179 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 3180
10214420
DV		 3181 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3182 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3183 /*
3184 * This is a big fat ugly hack.
3185 *
3186 * Some machines in UEFI boot mode provide us a VBT that has 18
3187 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3188 * unknown we fail to light up. Yet the same BIOS boots up with
3189 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3190 * max, not what it tells us to use.
3191 *
3192 * Note: This will still be broken if the eDP panel is not lit
3193 * up by the BIOS, and thus we can't get the mode at module
3194 * load.
3195 */
3196 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3197 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3198 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3199 }
11578553 3200
22606a18 3201 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3202}
3203
5bfe2ac0 3204static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3205 struct intel_crtc_state *pipe_config)
00c09d70 3206{
5bfe2ac0 3207 int type = encoder->type;
eccb140b 3208 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3209
5bfe2ac0 3210 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3211
eccb140b
DV		 3212 if (port == PORT_A)
3213 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3214
00c09d70 3215 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3216 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3217 else
5bfe2ac0 3218 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3219}
3220
3221static const struct drm_encoder_funcs intel_ddi_funcs = {
5eaa60c7
ID		 3222 .reset = intel_dp_encoder_reset,
3223 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 3224};
3225
4a28ae58
PZ		 3226static struct intel_connector *
3227intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3228{
3229 struct intel_connector *connector;
3230 enum port port = intel_dig_port->port;
3231
9bdbd0b9 3232 connector = intel_connector_alloc();
4a28ae58
PZ		 3233 if (!connector)
3234 return NULL;
3235
3236 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3237 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3238 kfree(connector);
3239 return NULL;
3240 }
3241
3242 return connector;
3243}
3244
3245static struct intel_connector *
3246intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3247{
3248 struct intel_connector *connector;
3249 enum port port = intel_dig_port->port;
3250
9bdbd0b9 3251 connector = intel_connector_alloc();
4a28ae58
PZ		 3252 if (!connector)
3253 return NULL;
3254
3255 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3256 intel_hdmi_init_connector(intel_dig_port, connector);
3257
3258 return connector;
3259}
3260
00c09d70
PZ		 3261void intel_ddi_init(struct drm_device *dev, enum port port)
3262{
876a8cdf 3263 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3264 struct intel_digital_port *intel_dig_port;
3265 struct intel_encoder *intel_encoder;
3266 struct drm_encoder *encoder;
311a2094 3267 bool init_hdmi, init_dp;
10e7bec3
VS		 3268 int max_lanes;
3269
3270 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
3271 switch (port) {
3272 case PORT_A:
3273 max_lanes = 4;
3274 break;
3275 case PORT_E:
3276 max_lanes = 0;
3277 break;
3278 default:
3279 max_lanes = 4;
3280 break;
3281 }
3282 } else {
3283 switch (port) {
3284 case PORT_A:
3285 max_lanes = 2;
3286 break;
3287 case PORT_E:
3288 max_lanes = 2;
3289 break;
3290 default:
3291 max_lanes = 4;
3292 break;
3293 }
3294 }
311a2094
PZ		 3295
3296 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3297 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3298 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3299 if (!init_dp && !init_hdmi) {
500ea70d 3300 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3301 port_name(port));
500ea70d 3302 return;
311a2094 3303 }
00c09d70 3304
b14c5679 3305 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3306 if (!intel_dig_port)
3307 return;
3308
00c09d70
PZ		 3309 intel_encoder = &intel_dig_port->base;
3310 encoder = &intel_encoder->base;
3311
3312 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
13a3d91f 3313 DRM_MODE_ENCODER_TMDS, NULL);
00c09d70 3314
5bfe2ac0 3315 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3316 intel_encoder->enable = intel_enable_ddi;
3317 intel_encoder->pre_enable = intel_ddi_pre_enable;
3318 intel_encoder->disable = intel_disable_ddi;
3319 intel_encoder->post_disable = intel_ddi_post_disable;
3320 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3321 intel_encoder->get_config = intel_ddi_get_config;
5eaa60c7 3322 intel_encoder->suspend = intel_dp_encoder_suspend;
00c09d70
PZ		 3323
3324 intel_dig_port->port = port;
bcf53de4
SM		 3325 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3326 (DDI_BUF_PORT_REVERSAL |
3327 DDI_A_4_LANES);
00c09d70 3328
6c566dc9
MR		 3329 /*
3330 * Bspec says that DDI_A_4_LANES is the only supported configuration
3331 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
3332 * wasn't lit up at boot. Force this bit on in our internal
3333 * configuration so that we use the proper lane count for our
3334 * calculations.
3335 */
3336 if (IS_BROXTON(dev) && port == PORT_A) {
3337 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
3338 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3339 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 3340 max_lanes = 4;
6c566dc9
MR		 3341 }
3342 }
3343
ed8d60f4
MR		 3344 intel_dig_port->max_lanes = max_lanes;
3345
00c09d70 3346 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3347 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3348 intel_encoder->cloneable = 0;
00c09d70 3349
f68d697e
CW		 3350 if (init_dp) {
3351 if (!intel_ddi_init_dp_connector(intel_dig_port))
3352 goto err;
13cf5504 3353
f68d697e 3354 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 3355 /*
3356 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3357 * interrupts to check the external panel connection.
3358 */
e87a005d 3359 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
cf1d5883
SJ		 3360 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3361 else
3362 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3363 }
21a8e6a4 3364
311a2094
PZ		 3365 /* In theory we don't need the encoder->type check, but leave it just in
3366 * case we have some really bad VBTs... */
f68d697e
CW		 3367 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3368 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3369 goto err;
21a8e6a4 3370 }
f68d697e
CW		 3371
3372 return;
3373
3374err:
3375 drm_encoder_cleanup(encoder);
3376 kfree(intel_dig_port);
00c09d70 3377}
Linux 6.x block layer and io_uring tree(s)