projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Zero unused WM1 watermarks on VLV/CHV
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
7ad14a29
SJ		 142/* eDP 1.4 low vswing translation parameters */
143static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154};
155
156
7f88e3af 157static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
b7192a56
SJ		 158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
7f88e3af
DL		 169};
170
96fb9f9b
VK		 171struct bxt_ddi_buf_trans {
172 u32 margin; /* swing value */
173 u32 scale; /* scale value */
174 u32 enable; /* scale enable */
175 u32 deemphasis;
176 bool default_index; /* true if the entry represents default value */
177};
178
179/* BSpec does not define separate vswing/pre-emphasis values for eDP.
180 * Using DP values for eDP as well.
181 */
182static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
183 /* Idx NT mV diff db */
fe4c63c8
ID		 184 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
185 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
186 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
187 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
188 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
189 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
190 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
191 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
192 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 193 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
194};
195
196/* BSpec has 2 recommended values - entries 0 and 8.
197 * Using the entry with higher vswing.
198 */
199static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
200 /* Idx NT mV diff db */
fe4c63c8
ID		 201 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
202 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
203 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
204 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
205 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
206 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
207 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
208 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
209 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 210 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
211};
212
a1e6ad66
ID		 213static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
214 struct intel_digital_port **dig_port,
215 enum port *port)
fc914639 216{
0bdee30e 217 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 218 int type = intel_encoder->type;
219
0e32b39c 220 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 221 *dig_port = enc_to_mst(encoder)->primary;
222 *port = (*dig_port)->port;
0e32b39c 223 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 224 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 225 *dig_port = enc_to_dig_port(encoder);
226 *port = (*dig_port)->port;
fc914639 227 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 228 *dig_port = NULL;
229 *port = PORT_E;
fc914639
PZ		 230 } else {
231 DRM_ERROR("Invalid DDI encoder type %d\n", type);
232 BUG();
233 }
234}
235
a1e6ad66
ID		 236enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
237{
238 struct intel_digital_port *dig_port;
239 enum port port;
240
241 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
242
243 return port;
244}
245
ce3b7e9b
DL		 246static bool
247intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
248{
249 return intel_dig_port->hdmi.hdmi_reg;
250}
251
e58623cb
AR		 252/*
253 * Starting with Haswell, DDI port buffers must be programmed with correct
254 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 255 * but the HDMI/DVI fields are shared among those. So we program the DDI
256 * in either FDI or DP modes only, as HDMI connections will work with both
257 * of those
258 */
faa0cdbe
ID		 259static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
260 bool supports_hdmi)
45244b87
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 u32 reg;
7ff44670 264 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 265 size;
6acab15a 266 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 267 const struct ddi_buf_trans *ddi_translations_fdi;
268 const struct ddi_buf_trans *ddi_translations_dp;
269 const struct ddi_buf_trans *ddi_translations_edp;
270 const struct ddi_buf_trans *ddi_translations_hdmi;
271 const struct ddi_buf_trans *ddi_translations;
e58623cb 272
96fb9f9b 273 if (IS_BROXTON(dev)) {
faa0cdbe 274 if (!supports_hdmi)
96fb9f9b
VK		 275 return;
276
277 /* Vswing programming for HDMI */
278 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
279 INTEL_OUTPUT_HDMI);
280 return;
281 } else if (IS_SKYLAKE(dev)) {
7f88e3af
DL		 282 ddi_translations_fdi = NULL;
283 ddi_translations_dp = skl_ddi_translations_dp;
7ad14a29 284 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
9e458034 285 if (dev_priv->edp_low_vswing) {
7ad14a29
SJ		 286 ddi_translations_edp = skl_ddi_translations_edp;
287 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
288 } else {
289 ddi_translations_edp = skl_ddi_translations_dp;
290 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
291 }
292
7f88e3af
DL		 293 ddi_translations_hdmi = skl_ddi_translations_hdmi;
294 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
b7192a56 295 hdmi_default_entry = 7;
7f88e3af 296 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 297 ddi_translations_fdi = bdw_ddi_translations_fdi;
298 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 299 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 300 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 301 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
302 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 303 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 304 hdmi_default_entry = 7;
e58623cb
AR		 305 } else if (IS_HASWELL(dev)) {
306 ddi_translations_fdi = hsw_ddi_translations_fdi;
307 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 308 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 309 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 310 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 311 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 312 hdmi_default_entry = 6;
e58623cb
AR		 313 } else {
314 WARN(1, "ddi translation table missing\n");
300644c7 315 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 316 ddi_translations_fdi = bdw_ddi_translations_fdi;
317 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 318 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 319 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
320 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 321 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 322 hdmi_default_entry = 7;
e58623cb
AR		 323 }
324
300644c7
PZ		 325 switch (port) {
326 case PORT_A:
327 ddi_translations = ddi_translations_edp;
7ad14a29 328 size = n_edp_entries;
300644c7
PZ		 329 break;
330 case PORT_B:
331 case PORT_C:
300644c7 332 ddi_translations = ddi_translations_dp;
7ad14a29 333 size = n_dp_entries;
300644c7 334 break;
77d8d009 335 case PORT_D:
7ad14a29 336 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 337 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 338 size = n_edp_entries;
339 } else {
77d8d009 340 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 341 size = n_dp_entries;
342 }
77d8d009 343 break;
300644c7 344 case PORT_E:
7f88e3af
DL		 345 if (ddi_translations_fdi)
346 ddi_translations = ddi_translations_fdi;
347 else
348 ddi_translations = ddi_translations_dp;
7ad14a29 349 size = n_dp_entries;
300644c7
PZ		 350 break;
351 default:
352 BUG();
353 }
45244b87 354
7ad14a29 355 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 356 I915_WRITE(reg, ddi_translations[i].trans1);
357 reg += 4;
358 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 359 reg += 4;
360 }
ce4dd49e 361
faa0cdbe 362 if (!supports_hdmi)
ce3b7e9b
DL		 363 return;
364
ce4dd49e
DL		 365 /* Choose a good default if VBT is badly populated */
366 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
367 hdmi_level >= n_hdmi_entries)
7ff44670 368 hdmi_level = hdmi_default_entry;
ce4dd49e 369
6acab15a 370 /* Entry 9 is for HDMI: */
10122051
JN		 371 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
372 reg += 4;
373 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
374 reg += 4;
45244b87
ED		 375}
376
377/* Program DDI buffers translations for DP. By default, program ports A-D in DP
378 * mode and port E for FDI.
379 */
380void intel_prepare_ddi(struct drm_device *dev)
381{
faa0cdbe 382 struct intel_encoder *intel_encoder;
b403745c 383 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 384
0d536cb4
PZ		 385 if (!HAS_DDI(dev))
386 return;
45244b87 387
faa0cdbe
ID		 388 for_each_intel_encoder(dev, intel_encoder) {
389 struct intel_digital_port *intel_dig_port;
390 enum port port;
391 bool supports_hdmi;
392
393 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
394
395 if (visited[port])
b403745c
DL		 396 continue;
397
faa0cdbe
ID		 398 supports_hdmi = intel_dig_port &&
399 intel_dig_port_supports_hdmi(intel_dig_port);
400
401 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
402 visited[port] = true;
b403745c 403 }
45244b87 404}
c82e4d26 405
248138b5
PZ		 406static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
407 enum port port)
408{
409 uint32_t reg = DDI_BUF_CTL(port);
410 int i;
411
3449ca85 412 for (i = 0; i < 16; i++) {
248138b5
PZ		 413 udelay(1);
414 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
415 return;
416 }
417 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
418}
c82e4d26
ED		 419
420/* Starting with Haswell, different DDI ports can work in FDI mode for
421 * connection to the PCH-located connectors. For this, it is necessary to train
422 * both the DDI port and PCH receiver for the desired DDI buffer settings.
423 *
424 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
425 * please note that when FDI mode is active on DDI E, it shares 2 lines with
426 * DDI A (which is used for eDP)
427 */
428
429void hsw_fdi_link_train(struct drm_crtc *crtc)
430{
431 struct drm_device *dev = crtc->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 434 u32 temp, i, rx_ctl_val;
c82e4d26 435
04945641
PZ		 436 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
437 * mode set "sequence for CRT port" document:
438 * - TP1 to TP2 time with the default value
439 * - FDI delay to 90h
8693a824
DL		 440 *
441 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 442 */
443 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
444 FDI_RX_PWRDN_LANE0_VAL(2) |
445 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
446
447 /* Enable the PCH Receiver FDI PLL */
3e68320e 448 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 449 FDI_RX_PLL_ENABLE |
6e3c9717 450 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 451 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
452 POSTING_READ(_FDI_RXA_CTL);
453 udelay(220);
454
455 /* Switch from Rawclk to PCDclk */
456 rx_ctl_val |= FDI_PCDCLK;
457 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
458
459 /* Configure Port Clock Select */
6e3c9717
ACO		 460 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
461 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 462
463 /* Start the training iterating through available voltages and emphasis,
464 * testing each value twice. */
10122051 465 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 466 /* Configure DP_TP_CTL with auto-training */
467 I915_WRITE(DP_TP_CTL(PORT_E),
468 DP_TP_CTL_FDI_AUTOTRAIN |
469 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
470 DP_TP_CTL_LINK_TRAIN_PAT1 |
471 DP_TP_CTL_ENABLE);
472
876a8cdf
DL		 473 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
474 * DDI E does not support port reversal, the functionality is
475 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
476 * port reversal bit */
c82e4d26 477 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 478 DDI_BUF_CTL_ENABLE |
6e3c9717 479 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 480 DDI_BUF_TRANS_SELECT(i / 2));
04945641 481 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 482
483 udelay(600);
484
04945641
PZ		 485 /* Program PCH FDI Receiver TU */
486 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
487
488 /* Enable PCH FDI Receiver with auto-training */
489 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
490 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
491 POSTING_READ(_FDI_RXA_CTL);
492
493 /* Wait for FDI receiver lane calibration */
494 udelay(30);
495
496 /* Unset FDI_RX_MISC pwrdn lanes */
497 temp = I915_READ(_FDI_RXA_MISC);
498 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
499 I915_WRITE(_FDI_RXA_MISC, temp);
500 POSTING_READ(_FDI_RXA_MISC);
501
502 /* Wait for FDI auto training time */
503 udelay(5);
c82e4d26
ED		 504
505 temp = I915_READ(DP_TP_STATUS(PORT_E));
506 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 507 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 508
509 /* Enable normal pixel sending for FDI */
510 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 511 DP_TP_CTL_FDI_AUTOTRAIN |
512 DP_TP_CTL_LINK_TRAIN_NORMAL |
513 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
514 DP_TP_CTL_ENABLE);
c82e4d26 515
04945641 516 return;
c82e4d26 517 }
04945641 518
248138b5
PZ		 519 temp = I915_READ(DDI_BUF_CTL(PORT_E));
520 temp &= ~DDI_BUF_CTL_ENABLE;
521 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
522 POSTING_READ(DDI_BUF_CTL(PORT_E));
523
04945641 524 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 525 temp = I915_READ(DP_TP_CTL(PORT_E));
526 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
527 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
528 I915_WRITE(DP_TP_CTL(PORT_E), temp);
529 POSTING_READ(DP_TP_CTL(PORT_E));
530
531 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 532
533 rx_ctl_val &= ~FDI_RX_ENABLE;
534 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 535 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 536
537 /* Reset FDI_RX_MISC pwrdn lanes */
538 temp = I915_READ(_FDI_RXA_MISC);
539 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
540 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
541 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 542 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 543 }
544
04945641 545 DRM_ERROR("FDI link training failed!\n");
c82e4d26 546}
0e72a5b5 547
44905a27
DA		 548void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
549{
550 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
551 struct intel_digital_port *intel_dig_port =
552 enc_to_dig_port(&encoder->base);
553
554 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 555 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 556 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
557
558}
559
8d9ddbcb
PZ		 560static struct intel_encoder *
561intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
562{
563 struct drm_device *dev = crtc->dev;
564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
565 struct intel_encoder *intel_encoder, *ret = NULL;
566 int num_encoders = 0;
567
568 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
569 ret = intel_encoder;
570 num_encoders++;
571 }
572
573 if (num_encoders != 1)
84f44ce7
VS		 574 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
575 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 576
577 BUG_ON(ret == NULL);
578 return ret;
579}
580
bcddf610 581struct intel_encoder *
3165c074 582intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 583{
3165c074
ACO		 584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
585 struct intel_encoder *ret = NULL;
586 struct drm_atomic_state *state;
da3ced29
ACO		 587 struct drm_connector *connector;
588 struct drm_connector_state *connector_state;
d0737e1d 589 int num_encoders = 0;
3165c074 590 int i;
d0737e1d 591
3165c074
ACO		 592 state = crtc_state->base.state;
593
da3ced29
ACO		 594 for_each_connector_in_state(state, connector, connector_state, i) {
595 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 596 continue;
597
da3ced29 598 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 599 num_encoders++;
d0737e1d
ACO		 600 }
601
602 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
603 pipe_name(crtc->pipe));
604
605 BUG_ON(ret == NULL);
606 return ret;
607}
608
1c0b85c5 609#define LC_FREQ 2700
27893390 610#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 611
612#define P_MIN 2
613#define P_MAX 64
614#define P_INC 2
615
616/* Constraints for PLL good behavior */
617#define REF_MIN 48
618#define REF_MAX 400
619#define VCO_MIN 2400
620#define VCO_MAX 4800
621
27893390
DL		 622#define abs_diff(a, b) ({ \
623 typeof(a) __a = (a); \
624 typeof(b) __b = (b); \
625 (void) (&__a == &__b); \
626 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 627
63582983 628struct hsw_wrpll_rnp {
1c0b85c5
DL		 629 unsigned p, n2, r2;
630};
631
63582983 632static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 633{
1c0b85c5
DL		 634 unsigned budget;
635
636 switch (clock) {
637 case 25175000:
638 case 25200000:
639 case 27000000:
640 case 27027000:
641 case 37762500:
642 case 37800000:
643 case 40500000:
644 case 40541000:
645 case 54000000:
646 case 54054000:
647 case 59341000:
648 case 59400000:
649 case 72000000:
650 case 74176000:
651 case 74250000:
652 case 81000000:
653 case 81081000:
654 case 89012000:
655 case 89100000:
656 case 108000000:
657 case 108108000:
658 case 111264000:
659 case 111375000:
660 case 148352000:
661 case 148500000:
662 case 162000000:
663 case 162162000:
664 case 222525000:
665 case 222750000:
666 case 296703000:
667 case 297000000:
668 budget = 0;
669 break;
670 case 233500000:
671 case 245250000:
672 case 247750000:
673 case 253250000:
674 case 298000000:
675 budget = 1500;
676 break;
677 case 169128000:
678 case 169500000:
679 case 179500000:
680 case 202000000:
681 budget = 2000;
682 break;
683 case 256250000:
684 case 262500000:
685 case 270000000:
686 case 272500000:
687 case 273750000:
688 case 280750000:
689 case 281250000:
690 case 286000000:
691 case 291750000:
692 budget = 4000;
693 break;
694 case 267250000:
695 case 268500000:
696 budget = 5000;
697 break;
698 default:
699 budget = 1000;
700 break;
701 }
6441ab5f 702
1c0b85c5
DL		 703 return budget;
704}
705
63582983
DL		 706static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
707 unsigned r2, unsigned n2, unsigned p,
708 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 709{
710 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 711
1c0b85c5
DL		 712 /* No best (r,n,p) yet */
713 if (best->p == 0) {
714 best->p = p;
715 best->n2 = n2;
716 best->r2 = r2;
717 return;
718 }
6441ab5f 719
1c0b85c5
DL		 720 /*
721 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
722 * freq2k.
723 *
724 * delta = 1e6 *
725 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
726 * freq2k;
727 *
728 * and we would like delta <= budget.
729 *
730 * If the discrepancy is above the PPM-based budget, always prefer to
731 * improve upon the previous solution. However, if you're within the
732 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
733 */
734 a = freq2k * budget * p * r2;
735 b = freq2k * budget * best->p * best->r2;
27893390
DL		 736 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
737 diff_best = abs_diff(freq2k * best->p * best->r2,
738 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 739 c = 1000000 * diff;
740 d = 1000000 * diff_best;
741
742 if (a < c && b < d) {
743 /* If both are above the budget, pick the closer */
744 if (best->p * best->r2 * diff < p * r2 * diff_best) {
745 best->p = p;
746 best->n2 = n2;
747 best->r2 = r2;
748 }
749 } else if (a >= c && b < d) {
750 /* If A is below the threshold but B is above it? Update. */
751 best->p = p;
752 best->n2 = n2;
753 best->r2 = r2;
754 } else if (a >= c && b >= d) {
755 /* Both are below the limit, so pick the higher n2/(r2*r2) */
756 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
757 best->p = p;
758 best->n2 = n2;
759 best->r2 = r2;
760 }
761 }
762 /* Otherwise a < c && b >= d, do nothing */
763}
764
63582983 765static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 766{
767 int refclk = LC_FREQ;
768 int n, p, r;
769 u32 wrpll;
770
771 wrpll = I915_READ(reg);
114fe488
DV		 772 switch (wrpll & WRPLL_PLL_REF_MASK) {
773 case WRPLL_PLL_SSC:
774 case WRPLL_PLL_NON_SSC:
11578553
JB		 775 /*
776 * We could calculate spread here, but our checking
777 * code only cares about 5% accuracy, and spread is a max of
778 * 0.5% downspread.
779 */
780 refclk = 135;
781 break;
114fe488 782 case WRPLL_PLL_LCPLL:
11578553
JB		 783 refclk = LC_FREQ;
784 break;
785 default:
786 WARN(1, "bad wrpll refclk\n");
787 return 0;
788 }
789
790 r = wrpll & WRPLL_DIVIDER_REF_MASK;
791 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
792 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
793
20f0ec16
JB		 794 /* Convert to KHz, p & r have a fixed point portion */
795 return (refclk * n * 100) / (p * r);
11578553
JB		 796}
797
540e732c
S		 798static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
799 uint32_t dpll)
800{
801 uint32_t cfgcr1_reg, cfgcr2_reg;
802 uint32_t cfgcr1_val, cfgcr2_val;
803 uint32_t p0, p1, p2, dco_freq;
804
805 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
806 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
807
808 cfgcr1_val = I915_READ(cfgcr1_reg);
809 cfgcr2_val = I915_READ(cfgcr2_reg);
810
811 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
812 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
813
814 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
815 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
816 else
817 p1 = 1;
818
819
820 switch (p0) {
821 case DPLL_CFGCR2_PDIV_1:
822 p0 = 1;
823 break;
824 case DPLL_CFGCR2_PDIV_2:
825 p0 = 2;
826 break;
827 case DPLL_CFGCR2_PDIV_3:
828 p0 = 3;
829 break;
830 case DPLL_CFGCR2_PDIV_7:
831 p0 = 7;
832 break;
833 }
834
835 switch (p2) {
836 case DPLL_CFGCR2_KDIV_5:
837 p2 = 5;
838 break;
839 case DPLL_CFGCR2_KDIV_2:
840 p2 = 2;
841 break;
842 case DPLL_CFGCR2_KDIV_3:
843 p2 = 3;
844 break;
845 case DPLL_CFGCR2_KDIV_1:
846 p2 = 1;
847 break;
848 }
849
850 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
851
852 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
853 1000) / 0x8000;
854
855 return dco_freq / (p0 * p1 * p2 * 5);
856}
857
858
859static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 860 struct intel_crtc_state *pipe_config)
540e732c
S		 861{
862 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 863 int link_clock = 0;
864 uint32_t dpll_ctl1, dpll;
865
134ffa44 866 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 867
868 dpll_ctl1 = I915_READ(DPLL_CTRL1);
869
870 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
871 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
872 } else {
71cd8423
DL		 873 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
874 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 875
876 switch (link_clock) {
71cd8423 877 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 878 link_clock = 81000;
879 break;
71cd8423 880 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 881 link_clock = 108000;
882 break;
71cd8423 883 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 884 link_clock = 135000;
885 break;
71cd8423 886 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 887 link_clock = 162000;
888 break;
71cd8423 889 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 890 link_clock = 216000;
891 break;
71cd8423 892 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 893 link_clock = 270000;
894 break;
895 default:
896 WARN(1, "Unsupported link rate\n");
897 break;
898 }
899 link_clock *= 2;
900 }
901
902 pipe_config->port_clock = link_clock;
903
904 if (pipe_config->has_dp_encoder)
2d112de7 905 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 906 intel_dotclock_calculate(pipe_config->port_clock,
907 &pipe_config->dp_m_n);
908 else
2d112de7 909 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 910}
911
3d51278a 912static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 913 struct intel_crtc_state *pipe_config)
11578553
JB		 914{
915 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 916 int link_clock = 0;
917 u32 val, pll;
918
26804afd 919 val = pipe_config->ddi_pll_sel;
11578553
JB		 920 switch (val & PORT_CLK_SEL_MASK) {
921 case PORT_CLK_SEL_LCPLL_810:
922 link_clock = 81000;
923 break;
924 case PORT_CLK_SEL_LCPLL_1350:
925 link_clock = 135000;
926 break;
927 case PORT_CLK_SEL_LCPLL_2700:
928 link_clock = 270000;
929 break;
930 case PORT_CLK_SEL_WRPLL1:
63582983 931 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 932 break;
933 case PORT_CLK_SEL_WRPLL2:
63582983 934 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 935 break;
936 case PORT_CLK_SEL_SPLL:
937 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
938 if (pll == SPLL_PLL_FREQ_810MHz)
939 link_clock = 81000;
940 else if (pll == SPLL_PLL_FREQ_1350MHz)
941 link_clock = 135000;
942 else if (pll == SPLL_PLL_FREQ_2700MHz)
943 link_clock = 270000;
944 else {
945 WARN(1, "bad spll freq\n");
946 return;
947 }
948 break;
949 default:
950 WARN(1, "bad port clock sel\n");
951 return;
952 }
953
954 pipe_config->port_clock = link_clock * 2;
955
956 if (pipe_config->has_pch_encoder)
2d112de7 957 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 958 intel_dotclock_calculate(pipe_config->port_clock,
959 &pipe_config->fdi_m_n);
960 else if (pipe_config->has_dp_encoder)
2d112de7 961 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 962 intel_dotclock_calculate(pipe_config->port_clock,
963 &pipe_config->dp_m_n);
964 else
2d112de7 965 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 966}
967
977bb38d
S		 968static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
969 enum intel_dpll_id dpll)
970{
971 /* FIXME formula not available in bspec */
972 return 0;
973}
974
975static void bxt_ddi_clock_get(struct intel_encoder *encoder,
976 struct intel_crtc_state *pipe_config)
977{
978 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
979 enum port port = intel_ddi_get_encoder_port(encoder);
980 uint32_t dpll = port;
981
982 pipe_config->port_clock =
983 bxt_calc_pll_link(dev_priv, dpll);
984
985 if (pipe_config->has_dp_encoder)
986 pipe_config->base.adjusted_mode.crtc_clock =
987 intel_dotclock_calculate(pipe_config->port_clock,
988 &pipe_config->dp_m_n);
989 else
990 pipe_config->base.adjusted_mode.crtc_clock =
991 pipe_config->port_clock;
992}
993
3d51278a 994void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 995 struct intel_crtc_state *pipe_config)
3d51278a 996{
22606a18
DL		 997 struct drm_device *dev = encoder->base.dev;
998
999 if (INTEL_INFO(dev)->gen <= 8)
1000 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1001 else if (IS_SKYLAKE(dev))
22606a18 1002 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1003 else if (IS_BROXTON(dev))
1004 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1005}
1006
1c0b85c5 1007static void
d664c0ce
DL		 1008hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1009 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1010{
1011 uint64_t freq2k;
1012 unsigned p, n2, r2;
63582983 1013 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1014 unsigned budget;
1015
1016 freq2k = clock / 100;
1017
63582983 1018 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1019
1020 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1021 * and directly pass the LC PLL to it. */
1022 if (freq2k == 5400000) {
1023 *n2_out = 2;
1024 *p_out = 1;
1025 *r2_out = 2;
1026 return;
1027 }
1028
1029 /*
1030 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1031 * the WR PLL.
1032 *
1033 * We want R so that REF_MIN <= Ref <= REF_MAX.
1034 * Injecting R2 = 2 * R gives:
1035 * REF_MAX * r2 > LC_FREQ * 2 and
1036 * REF_MIN * r2 < LC_FREQ * 2
1037 *
1038 * Which means the desired boundaries for r2 are:
1039 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1040 *
1041 */
1042 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1043 r2 <= LC_FREQ * 2 / REF_MIN;
1044 r2++) {
1045
1046 /*
1047 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1048 *
1049 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1050 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1051 * VCO_MAX * r2 > n2 * LC_FREQ and
1052 * VCO_MIN * r2 < n2 * LC_FREQ)
1053 *
1054 * Which means the desired boundaries for n2 are:
1055 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1056 */
1057 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1058 n2 <= VCO_MAX * r2 / LC_FREQ;
1059 n2++) {
1060
1061 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1062 hsw_wrpll_update_rnp(freq2k, budget,
1063 r2, n2, p, &best);
1c0b85c5
DL		 1064 }
1065 }
6441ab5f 1066
1c0b85c5
DL		 1067 *n2_out = best.n2;
1068 *p_out = best.p;
1069 *r2_out = best.r2;
6441ab5f
PZ		 1070}
1071
0220ab6e 1072static bool
d664c0ce 1073hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1074 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1075 struct intel_encoder *intel_encoder,
1076 int clock)
6441ab5f 1077{
d664c0ce 1078 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1079 struct intel_shared_dpll *pll;
716c2e55 1080 uint32_t val;
1c0b85c5 1081 unsigned p, n2, r2;
6441ab5f 1082
d664c0ce 1083 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1084
114fe488 1085 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1086 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1087 WRPLL_DIVIDER_POST(p);
1088
dd3cd74a
ACO		 1089 memset(&crtc_state->dpll_hw_state, 0,
1090 sizeof(crtc_state->dpll_hw_state));
1091
190f68c5 1092 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1093
190f68c5 1094 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1095 if (pll == NULL) {
1096 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1097 pipe_name(intel_crtc->pipe));
1098 return false;
0694001b 1099 }
d452c5b6 1100
190f68c5 1101 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1102 }
1103
6441ab5f
PZ		 1104 return true;
1105}
1106
dc253813
DL		 1107struct skl_wrpll_context {
1108 uint64_t min_deviation; /* current minimal deviation */
1109 uint64_t central_freq; /* chosen central freq */
1110 uint64_t dco_freq; /* chosen dco freq */
1111 unsigned int p; /* chosen divider */
1112};
1113
1114static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1115{
1116 memset(ctx, 0, sizeof(*ctx));
1117
1118 ctx->min_deviation = U64_MAX;
1119}
1120
1121/* DCO freq must be within +1%/-6% of the DCO central freq */
1122#define SKL_DCO_MAX_PDEVIATION 100
1123#define SKL_DCO_MAX_NDEVIATION 600
1124
1125static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1126 uint64_t central_freq,
1127 uint64_t dco_freq,
1128 unsigned int divider)
1129{
1130 uint64_t deviation;
1131
1132 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1133 central_freq);
1134
1135 /* positive deviation */
1136 if (dco_freq >= central_freq) {
1137 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1138 deviation < ctx->min_deviation) {
1139 ctx->min_deviation = deviation;
1140 ctx->central_freq = central_freq;
1141 ctx->dco_freq = dco_freq;
1142 ctx->p = divider;
1143 }
1144 /* negative deviation */
1145 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1146 deviation < ctx->min_deviation) {
1147 ctx->min_deviation = deviation;
1148 ctx->central_freq = central_freq;
1149 ctx->dco_freq = dco_freq;
1150 ctx->p = divider;
1151 }
dc253813
DL		 1152}
1153
1154static void skl_wrpll_get_multipliers(unsigned int p,
1155 unsigned int *p0 /* out */,
1156 unsigned int *p1 /* out */,
1157 unsigned int *p2 /* out */)
1158{
1159 /* even dividers */
1160 if (p % 2 == 0) {
1161 unsigned int half = p / 2;
1162
1163 if (half == 1 || half == 2 || half == 3 || half == 5) {
1164 *p0 = 2;
1165 *p1 = 1;
1166 *p2 = half;
1167 } else if (half % 2 == 0) {
1168 *p0 = 2;
1169 *p1 = half / 2;
1170 *p2 = 2;
1171 } else if (half % 3 == 0) {
1172 *p0 = 3;
1173 *p1 = half / 3;
1174 *p2 = 2;
1175 } else if (half % 7 == 0) {
1176 *p0 = 7;
1177 *p1 = half / 7;
1178 *p2 = 2;
1179 }
1180 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1181 *p0 = 3;
1182 *p1 = 1;
1183 *p2 = p / 3;
1184 } else if (p == 5 || p == 7) {
1185 *p0 = p;
1186 *p1 = 1;
1187 *p2 = 1;
1188 } else if (p == 15) {
1189 *p0 = 3;
1190 *p1 = 1;
1191 *p2 = 5;
1192 } else if (p == 21) {
1193 *p0 = 7;
1194 *p1 = 1;
1195 *p2 = 3;
1196 } else if (p == 35) {
1197 *p0 = 7;
1198 *p1 = 1;
1199 *p2 = 5;
1200 }
1201}
1202
82d35437
S		 1203struct skl_wrpll_params {
1204 uint32_t dco_fraction;
1205 uint32_t dco_integer;
1206 uint32_t qdiv_ratio;
1207 uint32_t qdiv_mode;
1208 uint32_t kdiv;
1209 uint32_t pdiv;
1210 uint32_t central_freq;
1211};
1212
76516fbc
DL		 1213static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1214 uint64_t afe_clock,
1215 uint64_t central_freq,
1216 uint32_t p0, uint32_t p1, uint32_t p2)
1217{
1218 uint64_t dco_freq;
1219
76516fbc
DL		 1220 switch (central_freq) {
1221 case 9600000000ULL:
1222 params->central_freq = 0;
1223 break;
1224 case 9000000000ULL:
1225 params->central_freq = 1;
1226 break;
1227 case 8400000000ULL:
1228 params->central_freq = 3;
1229 }
1230
1231 switch (p0) {
1232 case 1:
1233 params->pdiv = 0;
1234 break;
1235 case 2:
1236 params->pdiv = 1;
1237 break;
1238 case 3:
1239 params->pdiv = 2;
1240 break;
1241 case 7:
1242 params->pdiv = 4;
1243 break;
1244 default:
1245 WARN(1, "Incorrect PDiv\n");
1246 }
1247
1248 switch (p2) {
1249 case 5:
1250 params->kdiv = 0;
1251 break;
1252 case 2:
1253 params->kdiv = 1;
1254 break;
1255 case 3:
1256 params->kdiv = 2;
1257 break;
1258 case 1:
1259 params->kdiv = 3;
1260 break;
1261 default:
1262 WARN(1, "Incorrect KDiv\n");
1263 }
1264
1265 params->qdiv_ratio = p1;
1266 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1267
1268 dco_freq = p0 * p1 * p2 * afe_clock;
1269
1270 /*
1271 * Intermediate values are in Hz.
1272 * Divide by MHz to match bsepc
1273 */
30a7862d 1274 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1275 params->dco_fraction =
30a7862d
DL		 1276 div_u64((div_u64(dco_freq, 24) -
1277 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1278}
1279
318bd821 1280static bool
82d35437
S		 1281skl_ddi_calculate_wrpll(int clock /* in Hz */,
1282 struct skl_wrpll_params *wrpll_params)
1283{
1284 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1285 uint64_t dco_central_freq[3] = {8400000000ULL,
1286 9000000000ULL,
1287 9600000000ULL};
dc253813
DL		 1288 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1289 24, 28, 30, 32, 36, 40, 42, 44,
1290 48, 52, 54, 56, 60, 64, 66, 68,
1291 70, 72, 76, 78, 80, 84, 88, 90,
1292 92, 96, 98 };
1293 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1294 static const struct {
1295 const int *list;
1296 int n_dividers;
1297 } dividers[] = {
1298 { even_dividers, ARRAY_SIZE(even_dividers) },
1299 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1300 };
1301 struct skl_wrpll_context ctx;
1302 unsigned int dco, d, i;
1303 unsigned int p0, p1, p2;
1304
1305 skl_wrpll_context_init(&ctx);
1306
1307 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1308 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1309 for (i = 0; i < dividers[d].n_dividers; i++) {
1310 unsigned int p = dividers[d].list[i];
1311 uint64_t dco_freq = p * afe_clock;
1312
1313 skl_wrpll_try_divider(&ctx,
1314 dco_central_freq[dco],
1315 dco_freq,
1316 p);
e7ad9878
DL		 1317 /*
1318 * Skip the remaining dividers if we're sure to
1319 * have found the definitive divider, we can't
1320 * improve a 0 deviation.
1321 */
1322 if (ctx.min_deviation == 0)
1323 goto skip_remaining_dividers;
82d35437
S		 1324 }
1325 }
267db663 1326
e7ad9878 1327skip_remaining_dividers:
267db663
DL		 1328 /*
1329 * If a solution is found with an even divider, prefer
1330 * this one.
1331 */
1332 if (d == 0 && ctx.p)
1333 break;
82d35437
S		 1334 }
1335
dc253813
DL		 1336 if (!ctx.p) {
1337 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1338 return false;
dc253813 1339 }
82d35437 1340
dc253813
DL		 1341 /*
1342 * gcc incorrectly analyses that these can be used without being
1343 * initialized. To be fair, it's hard to guess.
1344 */
1345 p0 = p1 = p2 = 0;
1346 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1347 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1348 p0, p1, p2);
318bd821
DL		 1349
1350 return true;
82d35437
S		 1351}
1352
82d35437
S		 1353static bool
1354skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1355 struct intel_crtc_state *crtc_state,
82d35437
S		 1356 struct intel_encoder *intel_encoder,
1357 int clock)
1358{
1359 struct intel_shared_dpll *pll;
1360 uint32_t ctrl1, cfgcr1, cfgcr2;
1361
1362 /*
1363 * See comment in intel_dpll_hw_state to understand why we always use 0
1364 * as the DPLL id in this function.
1365 */
1366
1367 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1368
1369 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1370 struct skl_wrpll_params wrpll_params = { 0, };
1371
1372 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1373
318bd821
DL		 1374 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1375 return false;
82d35437
S		 1376
1377 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1378 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1379 wrpll_params.dco_integer;
1380
1381 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1382 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1383 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1384 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1385 wrpll_params.central_freq;
1386 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1387 struct drm_encoder *encoder = &intel_encoder->base;
1388 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1389
1390 switch (intel_dp->link_bw) {
1391 case DP_LINK_BW_1_62:
71cd8423 1392 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437
S		 1393 break;
1394 case DP_LINK_BW_2_7:
71cd8423 1395 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437
S		 1396 break;
1397 case DP_LINK_BW_5_4:
71cd8423 1398 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1399 break;
1400 }
1401
1402 cfgcr1 = cfgcr2 = 0;
1403 } else /* eDP */
1404 return true;
1405
dd3cd74a
ACO		 1406 memset(&crtc_state->dpll_hw_state, 0,
1407 sizeof(crtc_state->dpll_hw_state));
1408
190f68c5
ACO		 1409 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1410 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1411 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1412
190f68c5 1413 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1414 if (pll == NULL) {
1415 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1416 pipe_name(intel_crtc->pipe));
1417 return false;
1418 }
1419
1420 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1421 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1422
1423 return true;
1424}
0220ab6e 1425
d683f3bc
S		 1426/* bxt clock parameters */
1427struct bxt_clk_div {
64987fc5 1428 int clock;
d683f3bc
S		 1429 uint32_t p1;
1430 uint32_t p2;
1431 uint32_t m2_int;
1432 uint32_t m2_frac;
1433 bool m2_frac_en;
1434 uint32_t n;
d683f3bc
S		 1435};
1436
1437/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1438static const struct bxt_clk_div bxt_dp_clk_val[] = {
1439 {162000, 4, 2, 32, 1677722, 1, 1},
1440 {270000, 4, 1, 27, 0, 0, 1},
1441 {540000, 2, 1, 27, 0, 0, 1},
1442 {216000, 3, 2, 32, 1677722, 1, 1},
1443 {243000, 4, 1, 24, 1258291, 1, 1},
1444 {324000, 4, 1, 32, 1677722, 1, 1},
1445 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1446};
1447
1448static bool
1449bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1450 struct intel_crtc_state *crtc_state,
1451 struct intel_encoder *intel_encoder,
1452 int clock)
1453{
1454 struct intel_shared_dpll *pll;
1455 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1456 int vco = 0;
1457 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e0681e38 1458 uint32_t dcoampovr_en_h, dco_amp, lanestagger;
d683f3bc
S		 1459
1460 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1461 intel_clock_t best_clock;
1462
1463 /* Calculate HDMI div */
1464 /*
1465 * FIXME: tie the following calculation into
1466 * i9xx_crtc_compute_clock
1467 */
1468 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1469 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1470 clock, pipe_name(intel_crtc->pipe));
1471 return false;
1472 }
1473
1474 clk_div.p1 = best_clock.p1;
1475 clk_div.p2 = best_clock.p2;
1476 WARN_ON(best_clock.m1 != 2);
1477 clk_div.n = best_clock.n;
1478 clk_div.m2_int = best_clock.m2 >> 22;
1479 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1480 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1481
b6dc71f3 1482 vco = best_clock.vco;
d683f3bc
S		 1483 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1484 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1485 int i;
d683f3bc 1486
64987fc5
SJ		 1487 clk_div = bxt_dp_clk_val[0];
1488 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1489 if (bxt_dp_clk_val[i].clock == clock) {
1490 clk_div = bxt_dp_clk_val[i];
1491 break;
1492 }
d683f3bc 1493 }
b6dc71f3
VK		 1494 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1495 }
1496
1497 dco_amp = 15;
1498 dcoampovr_en_h = 0;
1499 if (vco >= 6200000 && vco <= 6480000) {
1500 prop_coef = 4;
1501 int_coef = 9;
1502 gain_ctl = 3;
1503 targ_cnt = 8;
1504 } else if ((vco > 5400000 && vco < 6200000) ||
1505 (vco >= 4800000 && vco < 5400000)) {
1506 prop_coef = 5;
1507 int_coef = 11;
1508 gain_ctl = 3;
1509 targ_cnt = 9;
1510 if (vco >= 4800000 && vco < 5400000)
1511 dcoampovr_en_h = 1;
1512 } else if (vco == 5400000) {
1513 prop_coef = 3;
1514 int_coef = 8;
1515 gain_ctl = 1;
1516 targ_cnt = 9;
1517 } else {
1518 DRM_ERROR("Invalid VCO\n");
1519 return false;
d683f3bc
S		 1520 }
1521
dd3cd74a
ACO		 1522 memset(&crtc_state->dpll_hw_state, 0,
1523 sizeof(crtc_state->dpll_hw_state));
1524
e0681e38
VK		 1525 if (clock > 270000)
1526 lanestagger = 0x18;
1527 else if (clock > 135000)
1528 lanestagger = 0x0d;
1529 else if (clock > 67000)
1530 lanestagger = 0x07;
1531 else if (clock > 33000)
1532 lanestagger = 0x04;
1533 else
1534 lanestagger = 0x02;
1535
d683f3bc
S		 1536 crtc_state->dpll_hw_state.ebb0 =
1537 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1538 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1539 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1540 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1541
1542 if (clk_div.m2_frac_en)
1543 crtc_state->dpll_hw_state.pll3 =
1544 PORT_PLL_M2_FRAC_ENABLE;
1545
1546 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1547 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1548 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1549 PORT_PLL_GAIN_CTL(gain_ctl);
1550
1551 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1552
b6dc71f3
VK		 1553 if (dcoampovr_en_h)
1554 crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
1555
1556 crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
d683f3bc
S		 1557
1558 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1559 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1560
1561 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1562 if (pll == NULL) {
1563 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1564 pipe_name(intel_crtc->pipe));
1565 return false;
1566 }
1567
1568 /* shared DPLL id 0 is DPLL A */
1569 crtc_state->ddi_pll_sel = pll->id;
1570
1571 return true;
1572}
1573
0220ab6e
DL		 1574/*
1575 * Tries to find a *shared* PLL for the CRTC and store it in
1576 * intel_crtc->ddi_pll_sel.
1577 *
1578 * For private DPLLs, compute_config() should do the selection for us. This
1579 * function should be folded into compute_config() eventually.
1580 */
190f68c5
ACO		 1581bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1582 struct intel_crtc_state *crtc_state)
0220ab6e 1583{
82d35437 1584 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1585 struct intel_encoder *intel_encoder =
3165c074 1586 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1587 int clock = crtc_state->port_clock;
0220ab6e 1588
82d35437 1589 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1590 return skl_ddi_pll_select(intel_crtc, crtc_state,
1591 intel_encoder, clock);
d683f3bc
S		 1592 else if (IS_BROXTON(dev))
1593 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1594 intel_encoder, clock);
82d35437 1595 else
190f68c5
ACO		 1596 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1597 intel_encoder, clock);
0220ab6e
DL		 1598}
1599
dae84799
PZ		 1600void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1601{
1602 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1604 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1605 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1606 int type = intel_encoder->type;
1607 uint32_t temp;
1608
0e32b39c 1609 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1610 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1611 switch (intel_crtc->config->pipe_bpp) {
dae84799 1612 case 18:
c9809791 1613 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1614 break;
1615 case 24:
c9809791 1616 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1617 break;
1618 case 30:
c9809791 1619 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1620 break;
1621 case 36:
c9809791 1622 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1623 break;
1624 default:
4e53c2e0 1625 BUG();
dae84799 1626 }
c9809791 1627 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1628 }
1629}
1630
0e32b39c
DA		 1631void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1632{
1633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1634 struct drm_device *dev = crtc->dev;
1635 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1636 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1637 uint32_t temp;
1638 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1639 if (state == true)
1640 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1641 else
1642 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1643 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1644}
1645
8228c251 1646void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1647{
1648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1649 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1650 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1651 struct drm_device *dev = crtc->dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1653 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1654 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1655 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1656 int type = intel_encoder->type;
8d9ddbcb
PZ		 1657 uint32_t temp;
1658
ad80a810
PZ		 1659 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1660 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1661 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1662
6e3c9717 1663 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1664 case 18:
ad80a810 1665 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1666 break;
1667 case 24:
ad80a810 1668 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1669 break;
1670 case 30:
ad80a810 1671 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1672 break;
1673 case 36:
ad80a810 1674 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1675 break;
1676 default:
4e53c2e0 1677 BUG();
dfcef252 1678 }
72662e10 1679
6e3c9717 1680 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1681 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1682 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1683 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1684
e6f0bfc4
PZ		 1685 if (cpu_transcoder == TRANSCODER_EDP) {
1686 switch (pipe) {
1687 case PIPE_A:
c7670b10
PZ		 1688 /* On Haswell, can only use the always-on power well for
1689 * eDP when not using the panel fitter, and when not
1690 * using motion blur mitigation (which we don't
1691 * support). */
fabf6e51 1692 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1693 (intel_crtc->config->pch_pfit.enabled ||
1694 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1695 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1696 else
1697 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1698 break;
1699 case PIPE_B:
1700 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1701 break;
1702 case PIPE_C:
1703 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1704 break;
1705 default:
1706 BUG();
1707 break;
1708 }
1709 }
1710
7739c33b 1711 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1712 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1713 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1714 else
ad80a810 1715 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1716
7739c33b 1717 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1718 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1719 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1720
1721 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1722 type == INTEL_OUTPUT_EDP) {
1723 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1724
0e32b39c
DA		 1725 if (intel_dp->is_mst) {
1726 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1727 } else
1728 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1729
1730 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1731 } else if (type == INTEL_OUTPUT_DP_MST) {
1732 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1733
1734 if (intel_dp->is_mst) {
1735 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1736 } else
1737 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1738
17aa6be9 1739 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1740 } else {
84f44ce7
VS		 1741 WARN(1, "Invalid encoder type %d for pipe %c\n",
1742 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1743 }
1744
ad80a810 1745 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1746}
72662e10 1747
ad80a810
PZ		 1748void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1749 enum transcoder cpu_transcoder)
8d9ddbcb 1750{
ad80a810 1751 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1752 uint32_t val = I915_READ(reg);
1753
0e32b39c 1754 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1755 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1756 I915_WRITE(reg, val);
72662e10
ED		 1757}
1758
bcbc889b
PZ		 1759bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1760{
1761 struct drm_device *dev = intel_connector->base.dev;
1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763 struct intel_encoder *intel_encoder = intel_connector->encoder;
1764 int type = intel_connector->base.connector_type;
1765 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1766 enum pipe pipe = 0;
1767 enum transcoder cpu_transcoder;
882244a3 1768 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1769 uint32_t tmp;
1770
882244a3 1771 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1772 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1773 return false;
1774
bcbc889b
PZ		 1775 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1776 return false;
1777
1778 if (port == PORT_A)
1779 cpu_transcoder = TRANSCODER_EDP;
1780 else
1a240d4d 1781 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1782
1783 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1784
1785 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1786 case TRANS_DDI_MODE_SELECT_HDMI:
1787 case TRANS_DDI_MODE_SELECT_DVI:
1788 return (type == DRM_MODE_CONNECTOR_HDMIA);
1789
1790 case TRANS_DDI_MODE_SELECT_DP_SST:
1791 if (type == DRM_MODE_CONNECTOR_eDP)
1792 return true;
bcbc889b 1793 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1794 case TRANS_DDI_MODE_SELECT_DP_MST:
1795 /* if the transcoder is in MST state then
1796 * connector isn't connected */
1797 return false;
bcbc889b
PZ		 1798
1799 case TRANS_DDI_MODE_SELECT_FDI:
1800 return (type == DRM_MODE_CONNECTOR_VGA);
1801
1802 default:
1803 return false;
1804 }
1805}
1806
85234cdc
DV		 1807bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1808 enum pipe *pipe)
1809{
1810 struct drm_device *dev = encoder->base.dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1812 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1813 enum intel_display_power_domain power_domain;
85234cdc
DV		 1814 u32 tmp;
1815 int i;
1816
6d129bea 1817 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1818 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1819 return false;
1820
fe43d3f5 1821 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1822
1823 if (!(tmp & DDI_BUF_CTL_ENABLE))
1824 return false;
1825
ad80a810
PZ		 1826 if (port == PORT_A) {
1827 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1828
ad80a810
PZ		 1829 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1830 case TRANS_DDI_EDP_INPUT_A_ON:
1831 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1832 *pipe = PIPE_A;
1833 break;
1834 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1835 *pipe = PIPE_B;
1836 break;
1837 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1838 *pipe = PIPE_C;
1839 break;
1840 }
1841
1842 return true;
1843 } else {
1844 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1845 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1846
1847 if ((tmp & TRANS_DDI_PORT_MASK)
1848 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1849 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1850 return false;
1851
ad80a810
PZ		 1852 *pipe = i;
1853 return true;
1854 }
85234cdc
DV		 1855 }
1856 }
1857
84f44ce7 1858 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1859
22f9fe50 1860 return false;
85234cdc
DV		 1861}
1862
fc914639
PZ		 1863void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1864{
1865 struct drm_crtc *crtc = &intel_crtc->base;
1866 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1867 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1868 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1869 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1870
bb523fc0
PZ		 1871 if (cpu_transcoder != TRANSCODER_EDP)
1872 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1873 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1874}
1875
1876void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1877{
1878 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1879 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1880
bb523fc0
PZ		 1881 if (cpu_transcoder != TRANSCODER_EDP)
1882 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1883 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1884}
1885
96fb9f9b
VK		 1886void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
1887 enum port port, int type)
1888{
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 const struct bxt_ddi_buf_trans *ddi_translations;
1891 u32 n_entries, i;
1892 uint32_t val;
1893
1894 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1895 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1896 ddi_translations = bxt_ddi_translations_dp;
1897 } else if (type == INTEL_OUTPUT_HDMI) {
1898 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1899 ddi_translations = bxt_ddi_translations_hdmi;
1900 } else {
1901 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1902 type);
1903 return;
1904 }
1905
1906 /* Check if default value has to be used */
1907 if (level >= n_entries ||
1908 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1909 for (i = 0; i < n_entries; i++) {
1910 if (ddi_translations[i].default_index) {
1911 level = i;
1912 break;
1913 }
1914 }
1915 }
1916
1917 /*
1918 * While we write to the group register to program all lanes at once we
1919 * can read only lane registers and we pick lanes 0/1 for that.
1920 */
1921 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1922 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1923 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1924
1925 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1926 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1927 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1928 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1929 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1930
1931 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1932 val &= ~UNIQE_TRANGE_EN_METHOD;
1933 if (ddi_translations[level].enable)
1934 val |= UNIQE_TRANGE_EN_METHOD;
1935 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1936
1937 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1938 val &= ~DE_EMPHASIS;
1939 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1940 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1941
1942 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1943 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1944 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1945}
1946
00c09d70 1947static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1948{
c19b0669 1949 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1950 struct drm_device *dev = encoder->dev;
1951 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1952 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1953 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1954 int type = intel_encoder->type;
96fb9f9b 1955 int hdmi_level;
6441ab5f 1956
82a4d9c0
PZ		 1957 if (type == INTEL_OUTPUT_EDP) {
1958 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1959 intel_edp_panel_on(intel_dp);
82a4d9c0 1960 }
6441ab5f 1961
efa80add 1962 if (IS_SKYLAKE(dev)) {
6e3c9717 1963 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1964 uint32_t val;
1965
5416d871
DL		 1966 /*
1967 * DPLL0 is used for eDP and is the only "private" DPLL (as
1968 * opposed to shared) on SKL
1969 */
1970 if (type == INTEL_OUTPUT_EDP) {
1971 WARN_ON(dpll != SKL_DPLL0);
1972
1973 val = I915_READ(DPLL_CTRL1);
1974
1975 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1976 DPLL_CTRL1_SSC(dpll) |
71cd8423 1977 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 1978 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1979
1980 I915_WRITE(DPLL_CTRL1, val);
1981 POSTING_READ(DPLL_CTRL1);
1982 }
1983
1984 /* DDI -> PLL mapping */
efa80add
S		 1985 val = I915_READ(DPLL_CTRL2);
1986
1987 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1988 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1989 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1990 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1991
1992 I915_WRITE(DPLL_CTRL2, val);
5416d871 1993
1ab23380 1994 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 1995 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1996 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1997 }
c19b0669 1998
82a4d9c0 1999 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2000 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2001
44905a27 2002 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2003
2004 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2005 intel_dp_start_link_train(intel_dp);
2006 intel_dp_complete_link_train(intel_dp);
23f08d83 2007 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2008 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2009 } else if (type == INTEL_OUTPUT_HDMI) {
2010 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2011
96fb9f9b
VK		 2012 if (IS_BROXTON(dev)) {
2013 hdmi_level = dev_priv->vbt.
2014 ddi_port_info[port].hdmi_level_shift;
2015 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2016 INTEL_OUTPUT_HDMI);
2017 }
30cf6db8 2018 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2019 crtc->config->has_hdmi_sink,
2020 &crtc->config->base.adjusted_mode);
c19b0669 2021 }
6441ab5f
PZ		 2022}
2023
00c09d70 2024static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2025{
2026 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2027 struct drm_device *dev = encoder->dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2029 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2030 int type = intel_encoder->type;
2886e93f 2031 uint32_t val;
a836bdf9 2032 bool wait = false;
2886e93f
PZ		 2033
2034 val = I915_READ(DDI_BUF_CTL(port));
2035 if (val & DDI_BUF_CTL_ENABLE) {
2036 val &= ~DDI_BUF_CTL_ENABLE;
2037 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2038 wait = true;
2886e93f 2039 }
6441ab5f 2040
a836bdf9
PZ		 2041 val = I915_READ(DP_TP_CTL(port));
2042 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2043 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2044 I915_WRITE(DP_TP_CTL(port), val);
2045
2046 if (wait)
2047 intel_wait_ddi_buf_idle(dev_priv, port);
2048
76bb80ed 2049 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2050 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2051 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2052 intel_edp_panel_vdd_on(intel_dp);
4be73780 2053 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2054 }
2055
efa80add
S		 2056 if (IS_SKYLAKE(dev))
2057 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2058 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2059 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2060 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2061}
2062
00c09d70 2063static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2064{
6547fef8 2065 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2066 struct drm_crtc *crtc = encoder->crtc;
2067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2068 struct drm_device *dev = encoder->dev;
72662e10 2069 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2070 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2071 int type = intel_encoder->type;
72662e10 2072
6547fef8 2073 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2074 struct intel_digital_port *intel_dig_port =
2075 enc_to_dig_port(encoder);
2076
6547fef8
PZ		 2077 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2078 * are ignored so nothing special needs to be done besides
2079 * enabling the port.
2080 */
876a8cdf 2081 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2082 intel_dig_port->saved_port_bits |
2083 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2084 } else if (type == INTEL_OUTPUT_EDP) {
2085 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2086
23f08d83 2087 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2088 intel_dp_stop_link_train(intel_dp);
2089
4be73780 2090 intel_edp_backlight_on(intel_dp);
0bc12bcb 2091 intel_psr_enable(intel_dp);
c395578e 2092 intel_edp_drrs_enable(intel_dp);
6547fef8 2093 }
7b9f35a6 2094
6e3c9717 2095 if (intel_crtc->config->has_audio) {
d45a0bf5 2096 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2097 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2098 }
5ab432ef
DV		 2099}
2100
00c09d70 2101static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2102{
d6c50ff8 2103 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2104 struct drm_crtc *crtc = encoder->crtc;
2105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2106 int type = intel_encoder->type;
7b9f35a6
WX		 2107 struct drm_device *dev = encoder->dev;
2108 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2109
6e3c9717 2110 if (intel_crtc->config->has_audio) {
69bfe1a9 2111 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2112 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2113 }
2831d842 2114
d6c50ff8
PZ		 2115 if (type == INTEL_OUTPUT_EDP) {
2116 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2117
c395578e 2118 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2119 intel_psr_disable(intel_dp);
4be73780 2120 intel_edp_backlight_off(intel_dp);
d6c50ff8 2121 }
72662e10 2122}
79f689aa 2123
e0b01be4
DV		 2124static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2125 struct intel_shared_dpll *pll)
2126{
3e369b76 2127 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2128 POSTING_READ(WRPLL_CTL(pll->id));
2129 udelay(20);
2130}
2131
12030431
DV		 2132static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2133 struct intel_shared_dpll *pll)
2134{
2135 uint32_t val;
2136
2137 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2138 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2139 POSTING_READ(WRPLL_CTL(pll->id));
2140}
2141
d452c5b6
DV		 2142static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2143 struct intel_shared_dpll *pll,
2144 struct intel_dpll_hw_state *hw_state)
2145{
2146 uint32_t val;
2147
f458ebbc 2148 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2149 return false;
2150
2151 val = I915_READ(WRPLL_CTL(pll->id));
2152 hw_state->wrpll = val;
2153
2154 return val & WRPLL_PLL_ENABLE;
2155}
2156
ca1381b5 2157static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2158 "WRPLL 1",
2159 "WRPLL 2",
2160};
2161
143b307c 2162static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2163{
9cd86933
DV		 2164 int i;
2165
716c2e55 2166 dev_priv->num_shared_dpll = 2;
9cd86933 2167
716c2e55 2168 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2169 dev_priv->shared_dplls[i].id = i;
2170 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2171 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2172 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2173 dev_priv->shared_dplls[i].get_hw_state =
2174 hsw_ddi_pll_get_hw_state;
9cd86933 2175 }
143b307c
DL		 2176}
2177
d1a2dc78
S		 2178static const char * const skl_ddi_pll_names[] = {
2179 "DPLL 1",
2180 "DPLL 2",
2181 "DPLL 3",
2182};
2183
2184struct skl_dpll_regs {
2185 u32 ctl, cfgcr1, cfgcr2;
2186};
2187
2188/* this array is indexed by the *shared* pll id */
2189static const struct skl_dpll_regs skl_dpll_regs[3] = {
2190 {
2191 /* DPLL 1 */
2192 .ctl = LCPLL2_CTL,
2193 .cfgcr1 = DPLL1_CFGCR1,
2194 .cfgcr2 = DPLL1_CFGCR2,
2195 },
2196 {
2197 /* DPLL 2 */
2198 .ctl = WRPLL_CTL1,
2199 .cfgcr1 = DPLL2_CFGCR1,
2200 .cfgcr2 = DPLL2_CFGCR2,
2201 },
2202 {
2203 /* DPLL 3 */
2204 .ctl = WRPLL_CTL2,
2205 .cfgcr1 = DPLL3_CFGCR1,
2206 .cfgcr2 = DPLL3_CFGCR2,
2207 },
2208};
2209
2210static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2211 struct intel_shared_dpll *pll)
2212{
2213 uint32_t val;
2214 unsigned int dpll;
2215 const struct skl_dpll_regs *regs = skl_dpll_regs;
2216
2217 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2218 dpll = pll->id + 1;
2219
2220 val = I915_READ(DPLL_CTRL1);
2221
2222 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2223 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2224 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2225
2226 I915_WRITE(DPLL_CTRL1, val);
2227 POSTING_READ(DPLL_CTRL1);
2228
2229 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2230 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2231 POSTING_READ(regs[pll->id].cfgcr1);
2232 POSTING_READ(regs[pll->id].cfgcr2);
2233
2234 /* the enable bit is always bit 31 */
2235 I915_WRITE(regs[pll->id].ctl,
2236 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2237
2238 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2239 DRM_ERROR("DPLL %d not locked\n", dpll);
2240}
2241
2242static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2243 struct intel_shared_dpll *pll)
2244{
2245 const struct skl_dpll_regs *regs = skl_dpll_regs;
2246
2247 /* the enable bit is always bit 31 */
2248 I915_WRITE(regs[pll->id].ctl,
2249 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2250 POSTING_READ(regs[pll->id].ctl);
2251}
2252
2253static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2254 struct intel_shared_dpll *pll,
2255 struct intel_dpll_hw_state *hw_state)
2256{
2257 uint32_t val;
2258 unsigned int dpll;
2259 const struct skl_dpll_regs *regs = skl_dpll_regs;
2260
2261 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2262 return false;
2263
2264 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2265 dpll = pll->id + 1;
2266
2267 val = I915_READ(regs[pll->id].ctl);
2268 if (!(val & LCPLL_PLL_ENABLE))
2269 return false;
2270
2271 val = I915_READ(DPLL_CTRL1);
2272 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2273
2274 /* avoid reading back stale values if HDMI mode is not enabled */
2275 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2276 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2277 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2278 }
2279
2280 return true;
2281}
2282
2283static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2284{
2285 int i;
2286
2287 dev_priv->num_shared_dpll = 3;
2288
2289 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2290 dev_priv->shared_dplls[i].id = i;
2291 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2292 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2293 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2294 dev_priv->shared_dplls[i].get_hw_state =
2295 skl_ddi_pll_get_hw_state;
2296 }
2297}
2298
5c6706e5
VK		 2299static void broxton_phy_init(struct drm_i915_private *dev_priv,
2300 enum dpio_phy phy)
2301{
2302 enum port port;
2303 uint32_t val;
2304
2305 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2306 val |= GT_DISPLAY_POWER_ON(phy);
2307 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2308
2309 /* Considering 10ms timeout until BSpec is updated */
2310 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2311 DRM_ERROR("timeout during PHY%d power on\n", phy);
2312
2313 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2314 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2315 int lane;
2316
2317 for (lane = 0; lane < 4; lane++) {
2318 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2319 /*
2320 * Note that on CHV this flag is called UPAR, but has
2321 * the same function.
2322 */
2323 val &= ~LATENCY_OPTIM;
2324 if (lane != 1)
2325 val |= LATENCY_OPTIM;
2326
2327 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2328 }
2329 }
2330
2331 /* Program PLL Rcomp code offset */
2332 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2333 val &= ~IREF0RC_OFFSET_MASK;
2334 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2335 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2336
2337 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2338 val &= ~IREF1RC_OFFSET_MASK;
2339 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2340 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2341
2342 /* Program power gating */
2343 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2344 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2345 SUS_CLK_CONFIG;
2346 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2347
2348 if (phy == DPIO_PHY0) {
2349 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2350 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2351 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2352 }
2353
2354 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2355 val &= ~OCL2_LDOFUSE_PWR_DIS;
2356 /*
2357 * On PHY1 disable power on the second channel, since no port is
2358 * connected there. On PHY0 both channels have a port, so leave it
2359 * enabled.
2360 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2361 * power down the second channel on PHY0 as well.
2362 */
2363 if (phy == DPIO_PHY1)
2364 val |= OCL2_LDOFUSE_PWR_DIS;
2365 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2366
2367 if (phy == DPIO_PHY0) {
2368 uint32_t grc_code;
2369 /*
2370 * PHY0 isn't connected to an RCOMP resistor so copy over
2371 * the corresponding calibrated value from PHY1, and disable
2372 * the automatic calibration on PHY0.
2373 */
2374 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2375 10))
2376 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2377
2378 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2379 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2380 grc_code = val << GRC_CODE_FAST_SHIFT |
2381 val << GRC_CODE_SLOW_SHIFT |
2382 val;
2383 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2384
2385 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2386 val |= GRC_DIS | GRC_RDY_OVRD;
2387 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2388 }
2389
2390 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2391 val |= COMMON_RESET_DIS;
2392 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2393}
2394
2395void broxton_ddi_phy_init(struct drm_device *dev)
2396{
2397 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2398 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2399 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2400}
2401
2402static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2403 enum dpio_phy phy)
2404{
2405 uint32_t val;
2406
2407 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2408 val &= ~COMMON_RESET_DIS;
2409 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2410}
2411
2412void broxton_ddi_phy_uninit(struct drm_device *dev)
2413{
2414 struct drm_i915_private *dev_priv = dev->dev_private;
2415
2416 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2417 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2418
2419 /* FIXME: do this in broxton_phy_uninit per phy */
2420 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2421}
2422
dfb82408
S		 2423static const char * const bxt_ddi_pll_names[] = {
2424 "PORT PLL A",
2425 "PORT PLL B",
2426 "PORT PLL C",
2427};
2428
2429static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2430 struct intel_shared_dpll *pll)
2431{
2432 uint32_t temp;
2433 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2434
2435 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2436 temp &= ~PORT_PLL_REF_SEL;
2437 /* Non-SSC reference */
2438 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2439
2440 /* Disable 10 bit clock */
2441 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2442 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2443 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2444
2445 /* Write P1 & P2 */
2446 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2447 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2448 temp |= pll->config.hw_state.ebb0;
2449 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2450
2451 /* Write M2 integer */
2452 temp = I915_READ(BXT_PORT_PLL(port, 0));
2453 temp &= ~PORT_PLL_M2_MASK;
2454 temp |= pll->config.hw_state.pll0;
2455 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2456
2457 /* Write N */
2458 temp = I915_READ(BXT_PORT_PLL(port, 1));
2459 temp &= ~PORT_PLL_N_MASK;
2460 temp |= pll->config.hw_state.pll1;
2461 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2462
2463 /* Write M2 fraction */
2464 temp = I915_READ(BXT_PORT_PLL(port, 2));
2465 temp &= ~PORT_PLL_M2_FRAC_MASK;
2466 temp |= pll->config.hw_state.pll2;
2467 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2468
2469 /* Write M2 fraction enable */
2470 temp = I915_READ(BXT_PORT_PLL(port, 3));
2471 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2472 temp |= pll->config.hw_state.pll3;
2473 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2474
2475 /* Write coeff */
2476 temp = I915_READ(BXT_PORT_PLL(port, 6));
2477 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2478 temp &= ~PORT_PLL_INT_COEFF_MASK;
2479 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2480 temp |= pll->config.hw_state.pll6;
2481 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2482
2483 /* Write calibration val */
2484 temp = I915_READ(BXT_PORT_PLL(port, 8));
2485 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2486 temp |= pll->config.hw_state.pll8;
2487 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2488
b6dc71f3
VK		 2489 temp = I915_READ(BXT_PORT_PLL(port, 9));
2490 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2491 temp |= (5 << 1);
2492 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2493
2494 temp = I915_READ(BXT_PORT_PLL(port, 10));
2495 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2496 temp &= ~PORT_PLL_DCO_AMP_MASK;
2497 temp |= pll->config.hw_state.pll10;
2498 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2499
2500 /* Recalibrate with new settings */
2501 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2502 temp |= PORT_PLL_RECALIBRATE;
2503 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2504 /* Enable 10 bit clock */
2505 temp |= PORT_PLL_10BIT_CLK_ENABLE;
2506 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2507
2508 /* Enable PLL */
2509 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2510 temp |= PORT_PLL_ENABLE;
2511 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2512 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2513
2514 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2515 PORT_PLL_LOCK), 200))
2516 DRM_ERROR("PLL %d not locked\n", port);
2517
2518 /*
2519 * While we write to the group register to program all lanes at once we
2520 * can read only lane registers and we pick lanes 0/1 for that.
2521 */
2522 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2523 temp &= ~LANE_STAGGER_MASK;
2524 temp &= ~LANESTAGGER_STRAP_OVRD;
2525 temp |= pll->config.hw_state.pcsdw12;
2526 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2527}
2528
2529static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2530 struct intel_shared_dpll *pll)
2531{
2532 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2533 uint32_t temp;
2534
2535 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2536 temp &= ~PORT_PLL_ENABLE;
2537 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2538 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2539}
2540
2541static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2542 struct intel_shared_dpll *pll,
2543 struct intel_dpll_hw_state *hw_state)
2544{
2545 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2546 uint32_t val;
2547
2548 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2549 return false;
2550
2551 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2552 if (!(val & PORT_PLL_ENABLE))
2553 return false;
2554
2555 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2556 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2557 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2558 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2559 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2560 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2561 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
b6dc71f3 2562 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
dfb82408
S		 2563 /*
2564 * While we write to the group register to program all lanes at once we
2565 * can read only lane registers. We configure all lanes the same way, so
2566 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2567 */
2568 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2569 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2570 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2571 hw_state->pcsdw12,
2572 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2573
2574 return true;
2575}
2576
2577static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2578{
2579 int i;
2580
2581 dev_priv->num_shared_dpll = 3;
2582
2583 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2584 dev_priv->shared_dplls[i].id = i;
2585 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2586 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2587 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2588 dev_priv->shared_dplls[i].get_hw_state =
2589 bxt_ddi_pll_get_hw_state;
2590 }
2591}
2592
143b307c
DL		 2593void intel_ddi_pll_init(struct drm_device *dev)
2594{
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 uint32_t val = I915_READ(LCPLL_CTL);
2597
d1a2dc78
S		 2598 if (IS_SKYLAKE(dev))
2599 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2600 else if (IS_BROXTON(dev))
2601 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2602 else
2603 hsw_shared_dplls_init(dev_priv);
79f689aa 2604
121643c2 2605 if (IS_SKYLAKE(dev)) {
d9062ae5
DL		 2606 int cdclk_freq;
2607
2608 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2609 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2610 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2611 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2612 else
2613 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2614 } else if (IS_BROXTON(dev)) {
2615 broxton_init_cdclk(dev);
5c6706e5 2616 broxton_ddi_phy_init(dev);
121643c2
S		 2617 } else {
2618 /*
2619 * The LCPLL register should be turned on by the BIOS. For now
2620 * let's just check its state and print errors in case
2621 * something is wrong. Don't even try to turn it on.
2622 */
2623
2624 if (val & LCPLL_CD_SOURCE_FCLK)
2625 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2626
121643c2
S		 2627 if (val & LCPLL_PLL_DISABLE)
2628 DRM_ERROR("LCPLL is disabled\n");
2629 }
79f689aa 2630}
c19b0669
PZ		 2631
2632void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2633{
174edf1f
PZ		 2634 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2635 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2636 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2637 enum port port = intel_dig_port->port;
c19b0669 2638 uint32_t val;
f3e227df 2639 bool wait = false;
c19b0669
PZ		 2640
2641 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2642 val = I915_READ(DDI_BUF_CTL(port));
2643 if (val & DDI_BUF_CTL_ENABLE) {
2644 val &= ~DDI_BUF_CTL_ENABLE;
2645 I915_WRITE(DDI_BUF_CTL(port), val);
2646 wait = true;
2647 }
2648
2649 val = I915_READ(DP_TP_CTL(port));
2650 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2651 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2652 I915_WRITE(DP_TP_CTL(port), val);
2653 POSTING_READ(DP_TP_CTL(port));
2654
2655 if (wait)
2656 intel_wait_ddi_buf_idle(dev_priv, port);
2657 }
2658
0e32b39c 2659 val = DP_TP_CTL_ENABLE |
c19b0669 2660 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2661 if (intel_dp->is_mst)
2662 val |= DP_TP_CTL_MODE_MST;
2663 else {
2664 val |= DP_TP_CTL_MODE_SST;
2665 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2666 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2667 }
c19b0669
PZ		 2668 I915_WRITE(DP_TP_CTL(port), val);
2669 POSTING_READ(DP_TP_CTL(port));
2670
2671 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2672 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2673 POSTING_READ(DDI_BUF_CTL(port));
2674
2675 udelay(600);
2676}
00c09d70 2677
1ad960f2
PZ		 2678void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2679{
2680 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2681 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2682 uint32_t val;
2683
2684 intel_ddi_post_disable(intel_encoder);
2685
2686 val = I915_READ(_FDI_RXA_CTL);
2687 val &= ~FDI_RX_ENABLE;
2688 I915_WRITE(_FDI_RXA_CTL, val);
2689
2690 val = I915_READ(_FDI_RXA_MISC);
2691 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2692 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2693 I915_WRITE(_FDI_RXA_MISC, val);
2694
2695 val = I915_READ(_FDI_RXA_CTL);
2696 val &= ~FDI_PCDCLK;
2697 I915_WRITE(_FDI_RXA_CTL, val);
2698
2699 val = I915_READ(_FDI_RXA_CTL);
2700 val &= ~FDI_RX_PLL_ENABLE;
2701 I915_WRITE(_FDI_RXA_CTL, val);
2702}
2703
6801c18c 2704void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2705 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2706{
2707 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2708 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2709 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2710 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2711 u32 temp, flags = 0;
2712
2713 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2714 if (temp & TRANS_DDI_PHSYNC)
2715 flags |= DRM_MODE_FLAG_PHSYNC;
2716 else
2717 flags |= DRM_MODE_FLAG_NHSYNC;
2718 if (temp & TRANS_DDI_PVSYNC)
2719 flags |= DRM_MODE_FLAG_PVSYNC;
2720 else
2721 flags |= DRM_MODE_FLAG_NVSYNC;
2722
2d112de7 2723 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2724
2725 switch (temp & TRANS_DDI_BPC_MASK) {
2726 case TRANS_DDI_BPC_6:
2727 pipe_config->pipe_bpp = 18;
2728 break;
2729 case TRANS_DDI_BPC_8:
2730 pipe_config->pipe_bpp = 24;
2731 break;
2732 case TRANS_DDI_BPC_10:
2733 pipe_config->pipe_bpp = 30;
2734 break;
2735 case TRANS_DDI_BPC_12:
2736 pipe_config->pipe_bpp = 36;
2737 break;
2738 default:
2739 break;
2740 }
eb14cb74
VS		 2741
2742 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2743 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2744 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2745 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2746
2747 if (intel_hdmi->infoframe_enabled(&encoder->base))
2748 pipe_config->has_infoframe = true;
cbc572a9 2749 break;
eb14cb74
VS		 2750 case TRANS_DDI_MODE_SELECT_DVI:
2751 case TRANS_DDI_MODE_SELECT_FDI:
2752 break;
2753 case TRANS_DDI_MODE_SELECT_DP_SST:
2754 case TRANS_DDI_MODE_SELECT_DP_MST:
2755 pipe_config->has_dp_encoder = true;
2756 intel_dp_get_m_n(intel_crtc, pipe_config);
2757 break;
2758 default:
2759 break;
2760 }
10214420 2761
f458ebbc 2762 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2763 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2764 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2765 pipe_config->has_audio = true;
2766 }
9ed109a7 2767
10214420
DV		 2768 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2769 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2770 /*
2771 * This is a big fat ugly hack.
2772 *
2773 * Some machines in UEFI boot mode provide us a VBT that has 18
2774 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2775 * unknown we fail to light up. Yet the same BIOS boots up with
2776 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2777 * max, not what it tells us to use.
2778 *
2779 * Note: This will still be broken if the eDP panel is not lit
2780 * up by the BIOS, and thus we can't get the mode at module
2781 * load.
2782 */
2783 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2784 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2785 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2786 }
11578553 2787
22606a18 2788 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2789}
2790
00c09d70
PZ		 2791static void intel_ddi_destroy(struct drm_encoder *encoder)
2792{
2793 /* HDMI has nothing special to destroy, so we can go with this. */
2794 intel_dp_encoder_destroy(encoder);
2795}
2796
5bfe2ac0 2797static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2798 struct intel_crtc_state *pipe_config)
00c09d70 2799{
5bfe2ac0 2800 int type = encoder->type;
eccb140b 2801 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2802
5bfe2ac0 2803 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2804
eccb140b
DV		 2805 if (port == PORT_A)
2806 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2807
00c09d70 2808 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2809 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2810 else
5bfe2ac0 2811 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2812}
2813
2814static const struct drm_encoder_funcs intel_ddi_funcs = {
2815 .destroy = intel_ddi_destroy,
2816};
2817
4a28ae58
PZ		 2818static struct intel_connector *
2819intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2820{
2821 struct intel_connector *connector;
2822 enum port port = intel_dig_port->port;
2823
9bdbd0b9 2824 connector = intel_connector_alloc();
4a28ae58
PZ		 2825 if (!connector)
2826 return NULL;
2827
2828 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2829 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2830 kfree(connector);
2831 return NULL;
2832 }
2833
2834 return connector;
2835}
2836
2837static struct intel_connector *
2838intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2839{
2840 struct intel_connector *connector;
2841 enum port port = intel_dig_port->port;
2842
9bdbd0b9 2843 connector = intel_connector_alloc();
4a28ae58
PZ		 2844 if (!connector)
2845 return NULL;
2846
2847 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2848 intel_hdmi_init_connector(intel_dig_port, connector);
2849
2850 return connector;
2851}
2852
00c09d70
PZ		 2853void intel_ddi_init(struct drm_device *dev, enum port port)
2854{
876a8cdf 2855 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2856 struct intel_digital_port *intel_dig_port;
2857 struct intel_encoder *intel_encoder;
2858 struct drm_encoder *encoder;
311a2094
PZ		 2859 bool init_hdmi, init_dp;
2860
2861 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2862 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2863 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2864 if (!init_dp && !init_hdmi) {
f68d697e 2865 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2866 port_name(port));
2867 init_hdmi = true;
2868 init_dp = true;
2869 }
00c09d70 2870
b14c5679 2871 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2872 if (!intel_dig_port)
2873 return;
2874
00c09d70
PZ		 2875 intel_encoder = &intel_dig_port->base;
2876 encoder = &intel_encoder->base;
2877
2878 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2879 DRM_MODE_ENCODER_TMDS);
00c09d70 2880
5bfe2ac0 2881 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2882 intel_encoder->enable = intel_enable_ddi;
2883 intel_encoder->pre_enable = intel_ddi_pre_enable;
2884 intel_encoder->disable = intel_disable_ddi;
2885 intel_encoder->post_disable = intel_ddi_post_disable;
2886 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2887 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2888
2889 intel_dig_port->port = port;
bcf53de4
SM		 2890 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2891 (DDI_BUF_PORT_REVERSAL |
2892 DDI_A_4_LANES);
00c09d70
PZ		 2893
2894 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2895 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2896 intel_encoder->cloneable = 0;
00c09d70 2897
f68d697e
CW		 2898 if (init_dp) {
2899 if (!intel_ddi_init_dp_connector(intel_dig_port))
2900 goto err;
13cf5504 2901
f68d697e 2902 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 2903 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2904 }
21a8e6a4 2905
311a2094
PZ		 2906 /* In theory we don't need the encoder->type check, but leave it just in
2907 * case we have some really bad VBTs... */
f68d697e
CW		 2908 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2909 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2910 goto err;
21a8e6a4 2911 }
f68d697e
CW		 2912
2913 return;
2914
2915err:
2916 drm_encoder_cleanup(encoder);
2917 kfree(intel_dig_port);
00c09d70 2918}
Linux 6.x block layer and io_uring tree(s)