projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Reject >9 ddi translation entried if port != A/E on SKL
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
d7097cff 136 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
d7097cff 139 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 140 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 141 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 147 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 148 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 150 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x00000088, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 161 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 163 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 166 { 0x00000018, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
2e78416e 229 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 230 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 240 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
2e78416e 244 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 245 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
78ab0bae
VS		 304static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
305 u32 level, enum port port, int type);
f8896f5d 306
a1e6ad66
ID		 307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
fc914639 310{
0bdee30e 311 struct drm_encoder *encoder = &intel_encoder->base;
fc914639 312
8cd21b7f
JN		 313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
a1e6ad66
ID		 315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
8cd21b7f
JN		 317 break;
318 case INTEL_OUTPUT_DISPLAYPORT:
319 case INTEL_OUTPUT_EDP:
320 case INTEL_OUTPUT_HDMI:
321 case INTEL_OUTPUT_UNKNOWN:
a1e6ad66
ID		 322 *dig_port = enc_to_dig_port(encoder);
323 *port = (*dig_port)->port;
8cd21b7f
JN		 324 break;
325 case INTEL_OUTPUT_ANALOG:
a1e6ad66
ID		 326 *dig_port = NULL;
327 *port = PORT_E;
8cd21b7f
JN		 328 break;
329 default:
330 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 break;
fc914639
PZ		 332 }
333}
334
a1e6ad66
ID		 335enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336{
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343}
344
ce3b7e9b
DL		 345static bool
346intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
347{
f0f59a00 348 return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg);
ce3b7e9b
DL		 349}
350
acee2998 351static const struct ddi_buf_trans *
78ab0bae 352skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 353{
78ab0bae 354 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 355 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 356 return skl_y_ddi_translations_dp;
78ab0bae 357 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 358 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 359 return skl_u_ddi_translations_dp;
f8896f5d 360 } else {
f8896f5d 361 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 362 return skl_ddi_translations_dp;
f8896f5d 363 }
f8896f5d
DW		 364}
365
acee2998 366static const struct ddi_buf_trans *
78ab0bae 367skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 368{
cd1101cb 369 if (dev_priv->edp_low_vswing) {
78ab0bae 370 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 371 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 372 return skl_y_ddi_translations_edp;
78ab0bae 373 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 374 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 375 return skl_u_ddi_translations_edp;
f8896f5d 376 } else {
f8896f5d 377 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 378 return skl_ddi_translations_edp;
f8896f5d
DW		 379 }
380 }
cd1101cb 381
78ab0bae 382 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 383}
384
385static const struct ddi_buf_trans *
78ab0bae 386skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 387{
78ab0bae 388 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 389 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 390 return skl_y_ddi_translations_hdmi;
f8896f5d 391 } else {
f8896f5d 392 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 393 return skl_ddi_translations_hdmi;
f8896f5d 394 }
f8896f5d
DW		 395}
396
e58623cb
AR		 397/*
398 * Starting with Haswell, DDI port buffers must be programmed with correct
399 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 400 * but the HDMI/DVI fields are shared among those. So we program the DDI
401 * in either FDI or DP modes only, as HDMI connections will work with both
402 * of those
403 */
78ab0bae
VS		 404static void intel_prepare_ddi_buffers(struct drm_i915_private *dev_priv,
405 enum port port, bool supports_hdmi)
45244b87 406{
75067dde 407 u32 iboost_bit = 0;
7ff44670 408 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 409 size;
6acab15a 410 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 411 const struct ddi_buf_trans *ddi_translations_fdi;
412 const struct ddi_buf_trans *ddi_translations_dp;
413 const struct ddi_buf_trans *ddi_translations_edp;
414 const struct ddi_buf_trans *ddi_translations_hdmi;
415 const struct ddi_buf_trans *ddi_translations;
e58623cb 416
78ab0bae 417 if (IS_BROXTON(dev_priv)) {
faa0cdbe 418 if (!supports_hdmi)
96fb9f9b
VK		 419 return;
420
421 /* Vswing programming for HDMI */
78ab0bae 422 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
96fb9f9b
VK		 423 INTEL_OUTPUT_HDMI);
424 return;
78ab0bae 425 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c30400fc 426 ddi_translations_fdi = NULL;
f8896f5d 427 ddi_translations_dp =
78ab0bae 428 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
f8896f5d 429 ddi_translations_edp =
78ab0bae 430 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
f8896f5d 431 ddi_translations_hdmi =
78ab0bae 432 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
f8896f5d 433 hdmi_default_entry = 8;
75067dde
AK		 434 /* If we're boosting the current, set bit 31 of trans1 */
435 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
436 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
437 iboost_bit = 1<<31;
10afa0b6
VS		 438
439 if (WARN_ON(port != PORT_A &&
440 port != PORT_E && n_edp_entries > 9))
441 n_edp_entries = 9;
78ab0bae 442 } else if (IS_BROADWELL(dev_priv)) {
e58623cb
AR		 443 ddi_translations_fdi = bdw_ddi_translations_fdi;
444 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 445 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 446 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 447 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
448 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 449 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 450 hdmi_default_entry = 7;
78ab0bae 451 } else if (IS_HASWELL(dev_priv)) {
e58623cb
AR		 452 ddi_translations_fdi = hsw_ddi_translations_fdi;
453 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 454 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 455 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 456 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 457 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 458 hdmi_default_entry = 6;
e58623cb
AR		 459 } else {
460 WARN(1, "ddi translation table missing\n");
300644c7 461 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 462 ddi_translations_fdi = bdw_ddi_translations_fdi;
463 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 464 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 465 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
466 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 467 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 468 hdmi_default_entry = 7;
e58623cb
AR		 469 }
470
300644c7
PZ		 471 switch (port) {
472 case PORT_A:
473 ddi_translations = ddi_translations_edp;
7ad14a29 474 size = n_edp_entries;
300644c7
PZ		 475 break;
476 case PORT_B:
477 case PORT_C:
300644c7 478 ddi_translations = ddi_translations_dp;
7ad14a29 479 size = n_dp_entries;
300644c7 480 break;
77d8d009 481 case PORT_D:
78ab0bae 482 if (intel_dp_is_edp(dev_priv->dev, PORT_D)) {
77d8d009 483 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 484 size = n_edp_entries;
485 } else {
77d8d009 486 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 487 size = n_dp_entries;
488 }
77d8d009 489 break;
300644c7 490 case PORT_E:
7f88e3af
DL		 491 if (ddi_translations_fdi)
492 ddi_translations = ddi_translations_fdi;
493 else
494 ddi_translations = ddi_translations_dp;
7ad14a29 495 size = n_dp_entries;
300644c7
PZ		 496 break;
497 default:
498 BUG();
499 }
45244b87 500
9712e688
VS		 501 for (i = 0; i < size; i++) {
502 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
503 ddi_translations[i].trans1 | iboost_bit);
504 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
505 ddi_translations[i].trans2);
45244b87 506 }
ce4dd49e 507
faa0cdbe 508 if (!supports_hdmi)
ce3b7e9b
DL		 509 return;
510
ce4dd49e
DL		 511 /* Choose a good default if VBT is badly populated */
512 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
513 hdmi_level >= n_hdmi_entries)
7ff44670 514 hdmi_level = hdmi_default_entry;
ce4dd49e 515
6acab15a 516 /* Entry 9 is for HDMI: */
9712e688
VS		 517 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
518 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
519 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
520 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 521}
522
523/* Program DDI buffers translations for DP. By default, program ports A-D in DP
524 * mode and port E for FDI.
525 */
526void intel_prepare_ddi(struct drm_device *dev)
527{
faa0cdbe 528 struct intel_encoder *intel_encoder;
b403745c 529 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 530
0d536cb4
PZ		 531 if (!HAS_DDI(dev))
532 return;
45244b87 533
faa0cdbe
ID		 534 for_each_intel_encoder(dev, intel_encoder) {
535 struct intel_digital_port *intel_dig_port;
536 enum port port;
537 bool supports_hdmi;
538
7d4aefd0
SS		 539 if (intel_encoder->type == INTEL_OUTPUT_DSI)
540 continue;
faa0cdbe 541
7d4aefd0 542 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
faa0cdbe 543 if (visited[port])
b403745c
DL		 544 continue;
545
faa0cdbe
ID		 546 supports_hdmi = intel_dig_port &&
547 intel_dig_port_supports_hdmi(intel_dig_port);
548
78ab0bae 549 intel_prepare_ddi_buffers(to_i915(dev), port, supports_hdmi);
faa0cdbe 550 visited[port] = true;
b403745c 551 }
45244b87 552}
c82e4d26 553
248138b5
PZ		 554static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
555 enum port port)
556{
f0f59a00 557 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 558 int i;
559
3449ca85 560 for (i = 0; i < 16; i++) {
248138b5
PZ		 561 udelay(1);
562 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
563 return;
564 }
565 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
566}
c82e4d26
ED		 567
568/* Starting with Haswell, different DDI ports can work in FDI mode for
569 * connection to the PCH-located connectors. For this, it is necessary to train
570 * both the DDI port and PCH receiver for the desired DDI buffer settings.
571 *
572 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
573 * please note that when FDI mode is active on DDI E, it shares 2 lines with
574 * DDI A (which is used for eDP)
575 */
576
577void hsw_fdi_link_train(struct drm_crtc *crtc)
578{
579 struct drm_device *dev = crtc->dev;
580 struct drm_i915_private *dev_priv = dev->dev_private;
581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 582 u32 temp, i, rx_ctl_val;
c82e4d26 583
04945641
PZ		 584 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
585 * mode set "sequence for CRT port" document:
586 * - TP1 to TP2 time with the default value
587 * - FDI delay to 90h
8693a824
DL		 588 *
589 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 590 */
eede3b53 591 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 592 FDI_RX_PWRDN_LANE0_VAL(2) |
593 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
594
595 /* Enable the PCH Receiver FDI PLL */
3e68320e 596 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 597 FDI_RX_PLL_ENABLE |
6e3c9717 598 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
eede3b53
VS		 599 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
600 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 601 udelay(220);
602
603 /* Switch from Rawclk to PCDclk */
604 rx_ctl_val |= FDI_PCDCLK;
eede3b53 605 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 606
607 /* Configure Port Clock Select */
6e3c9717
ACO		 608 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
609 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 610
611 /* Start the training iterating through available voltages and emphasis,
612 * testing each value twice. */
10122051 613 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 614 /* Configure DP_TP_CTL with auto-training */
615 I915_WRITE(DP_TP_CTL(PORT_E),
616 DP_TP_CTL_FDI_AUTOTRAIN |
617 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
618 DP_TP_CTL_LINK_TRAIN_PAT1 |
619 DP_TP_CTL_ENABLE);
620
876a8cdf
DL		 621 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
622 * DDI E does not support port reversal, the functionality is
623 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
624 * port reversal bit */
c82e4d26 625 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 626 DDI_BUF_CTL_ENABLE |
6e3c9717 627 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 628 DDI_BUF_TRANS_SELECT(i / 2));
04945641 629 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 630
631 udelay(600);
632
04945641 633 /* Program PCH FDI Receiver TU */
eede3b53 634 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 635
636 /* Enable PCH FDI Receiver with auto-training */
637 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 638 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
639 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 640
641 /* Wait for FDI receiver lane calibration */
642 udelay(30);
643
644 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 645 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 646 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 647 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
648 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 649
650 /* Wait for FDI auto training time */
651 udelay(5);
c82e4d26
ED		 652
653 temp = I915_READ(DP_TP_STATUS(PORT_E));
654 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 655 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 656 break;
657 }
c82e4d26 658
a308ccb3
VS		 659 /*
660 * Leave things enabled even if we failed to train FDI.
661 * Results in less fireworks from the state checker.
662 */
663 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
664 DRM_ERROR("FDI link training failed!\n");
665 break;
c82e4d26 666 }
04945641 667
248138b5
PZ		 668 temp = I915_READ(DDI_BUF_CTL(PORT_E));
669 temp &= ~DDI_BUF_CTL_ENABLE;
670 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
671 POSTING_READ(DDI_BUF_CTL(PORT_E));
672
04945641 673 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 674 temp = I915_READ(DP_TP_CTL(PORT_E));
675 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
676 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
677 I915_WRITE(DP_TP_CTL(PORT_E), temp);
678 POSTING_READ(DP_TP_CTL(PORT_E));
679
680 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 681
682 rx_ctl_val &= ~FDI_RX_ENABLE;
eede3b53
VS		 683 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
684 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 685
686 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 687 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 688 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
689 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 690 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
691 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 692 }
693
a308ccb3
VS		 694 /* Enable normal pixel sending for FDI */
695 I915_WRITE(DP_TP_CTL(PORT_E),
696 DP_TP_CTL_FDI_AUTOTRAIN |
697 DP_TP_CTL_LINK_TRAIN_NORMAL |
698 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
699 DP_TP_CTL_ENABLE);
c82e4d26 700}
0e72a5b5 701
44905a27
DA		 702void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
703{
704 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
705 struct intel_digital_port *intel_dig_port =
706 enc_to_dig_port(&encoder->base);
707
708 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 709 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 710 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 711}
712
8d9ddbcb
PZ		 713static struct intel_encoder *
714intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
715{
716 struct drm_device *dev = crtc->dev;
717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
718 struct intel_encoder *intel_encoder, *ret = NULL;
719 int num_encoders = 0;
720
721 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
722 ret = intel_encoder;
723 num_encoders++;
724 }
725
726 if (num_encoders != 1)
84f44ce7
VS		 727 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
728 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 729
730 BUG_ON(ret == NULL);
731 return ret;
732}
733
bcddf610 734struct intel_encoder *
3165c074 735intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 736{
3165c074
ACO		 737 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
738 struct intel_encoder *ret = NULL;
739 struct drm_atomic_state *state;
da3ced29
ACO		 740 struct drm_connector *connector;
741 struct drm_connector_state *connector_state;
d0737e1d 742 int num_encoders = 0;
3165c074 743 int i;
d0737e1d 744
3165c074
ACO		 745 state = crtc_state->base.state;
746
da3ced29
ACO		 747 for_each_connector_in_state(state, connector, connector_state, i) {
748 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 749 continue;
750
da3ced29 751 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 752 num_encoders++;
d0737e1d
ACO		 753 }
754
755 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
756 pipe_name(crtc->pipe));
757
758 BUG_ON(ret == NULL);
759 return ret;
760}
761
1c0b85c5 762#define LC_FREQ 2700
27893390 763#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 764
765#define P_MIN 2
766#define P_MAX 64
767#define P_INC 2
768
769/* Constraints for PLL good behavior */
770#define REF_MIN 48
771#define REF_MAX 400
772#define VCO_MIN 2400
773#define VCO_MAX 4800
774
27893390
DL		 775#define abs_diff(a, b) ({ \
776 typeof(a) __a = (a); \
777 typeof(b) __b = (b); \
778 (void) (&__a == &__b); \
779 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 780
63582983 781struct hsw_wrpll_rnp {
1c0b85c5
DL		 782 unsigned p, n2, r2;
783};
784
63582983 785static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 786{
1c0b85c5
DL		 787 unsigned budget;
788
789 switch (clock) {
790 case 25175000:
791 case 25200000:
792 case 27000000:
793 case 27027000:
794 case 37762500:
795 case 37800000:
796 case 40500000:
797 case 40541000:
798 case 54000000:
799 case 54054000:
800 case 59341000:
801 case 59400000:
802 case 72000000:
803 case 74176000:
804 case 74250000:
805 case 81000000:
806 case 81081000:
807 case 89012000:
808 case 89100000:
809 case 108000000:
810 case 108108000:
811 case 111264000:
812 case 111375000:
813 case 148352000:
814 case 148500000:
815 case 162000000:
816 case 162162000:
817 case 222525000:
818 case 222750000:
819 case 296703000:
820 case 297000000:
821 budget = 0;
822 break;
823 case 233500000:
824 case 245250000:
825 case 247750000:
826 case 253250000:
827 case 298000000:
828 budget = 1500;
829 break;
830 case 169128000:
831 case 169500000:
832 case 179500000:
833 case 202000000:
834 budget = 2000;
835 break;
836 case 256250000:
837 case 262500000:
838 case 270000000:
839 case 272500000:
840 case 273750000:
841 case 280750000:
842 case 281250000:
843 case 286000000:
844 case 291750000:
845 budget = 4000;
846 break;
847 case 267250000:
848 case 268500000:
849 budget = 5000;
850 break;
851 default:
852 budget = 1000;
853 break;
854 }
6441ab5f 855
1c0b85c5
DL		 856 return budget;
857}
858
63582983
DL		 859static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
860 unsigned r2, unsigned n2, unsigned p,
861 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 862{
863 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 864
1c0b85c5
DL		 865 /* No best (r,n,p) yet */
866 if (best->p == 0) {
867 best->p = p;
868 best->n2 = n2;
869 best->r2 = r2;
870 return;
871 }
6441ab5f 872
1c0b85c5
DL		 873 /*
874 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
875 * freq2k.
876 *
877 * delta = 1e6 *
878 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
879 * freq2k;
880 *
881 * and we would like delta <= budget.
882 *
883 * If the discrepancy is above the PPM-based budget, always prefer to
884 * improve upon the previous solution. However, if you're within the
885 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
886 */
887 a = freq2k * budget * p * r2;
888 b = freq2k * budget * best->p * best->r2;
27893390
DL		 889 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
890 diff_best = abs_diff(freq2k * best->p * best->r2,
891 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 892 c = 1000000 * diff;
893 d = 1000000 * diff_best;
894
895 if (a < c && b < d) {
896 /* If both are above the budget, pick the closer */
897 if (best->p * best->r2 * diff < p * r2 * diff_best) {
898 best->p = p;
899 best->n2 = n2;
900 best->r2 = r2;
901 }
902 } else if (a >= c && b < d) {
903 /* If A is below the threshold but B is above it? Update. */
904 best->p = p;
905 best->n2 = n2;
906 best->r2 = r2;
907 } else if (a >= c && b >= d) {
908 /* Both are below the limit, so pick the higher n2/(r2*r2) */
909 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
910 best->p = p;
911 best->n2 = n2;
912 best->r2 = r2;
913 }
914 }
915 /* Otherwise a < c && b >= d, do nothing */
916}
917
f0f59a00
VS		 918static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
919 i915_reg_t reg)
11578553
JB		 920{
921 int refclk = LC_FREQ;
922 int n, p, r;
923 u32 wrpll;
924
925 wrpll = I915_READ(reg);
114fe488
DV		 926 switch (wrpll & WRPLL_PLL_REF_MASK) {
927 case WRPLL_PLL_SSC:
928 case WRPLL_PLL_NON_SSC:
11578553
JB		 929 /*
930 * We could calculate spread here, but our checking
931 * code only cares about 5% accuracy, and spread is a max of
932 * 0.5% downspread.
933 */
934 refclk = 135;
935 break;
114fe488 936 case WRPLL_PLL_LCPLL:
11578553
JB		 937 refclk = LC_FREQ;
938 break;
939 default:
940 WARN(1, "bad wrpll refclk\n");
941 return 0;
942 }
943
944 r = wrpll & WRPLL_DIVIDER_REF_MASK;
945 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
946 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
947
20f0ec16
JB		 948 /* Convert to KHz, p & r have a fixed point portion */
949 return (refclk * n * 100) / (p * r);
11578553
JB		 950}
951
540e732c
S		 952static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
953 uint32_t dpll)
954{
f0f59a00 955 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 956 uint32_t cfgcr1_val, cfgcr2_val;
957 uint32_t p0, p1, p2, dco_freq;
958
923c1241
VS		 959 cfgcr1_reg = DPLL_CFGCR1(dpll);
960 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 961
962 cfgcr1_val = I915_READ(cfgcr1_reg);
963 cfgcr2_val = I915_READ(cfgcr2_reg);
964
965 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
966 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
967
968 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
969 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
970 else
971 p1 = 1;
972
973
974 switch (p0) {
975 case DPLL_CFGCR2_PDIV_1:
976 p0 = 1;
977 break;
978 case DPLL_CFGCR2_PDIV_2:
979 p0 = 2;
980 break;
981 case DPLL_CFGCR2_PDIV_3:
982 p0 = 3;
983 break;
984 case DPLL_CFGCR2_PDIV_7:
985 p0 = 7;
986 break;
987 }
988
989 switch (p2) {
990 case DPLL_CFGCR2_KDIV_5:
991 p2 = 5;
992 break;
993 case DPLL_CFGCR2_KDIV_2:
994 p2 = 2;
995 break;
996 case DPLL_CFGCR2_KDIV_3:
997 p2 = 3;
998 break;
999 case DPLL_CFGCR2_KDIV_1:
1000 p2 = 1;
1001 break;
1002 }
1003
1004 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1005
1006 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1007 1000) / 0x8000;
1008
1009 return dco_freq / (p0 * p1 * p2 * 5);
1010}
1011
398a017e
VS		 1012static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1013{
1014 int dotclock;
1015
1016 if (pipe_config->has_pch_encoder)
1017 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1018 &pipe_config->fdi_m_n);
1019 else if (pipe_config->has_dp_encoder)
1020 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1021 &pipe_config->dp_m_n);
1022 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1023 dotclock = pipe_config->port_clock * 2 / 3;
1024 else
1025 dotclock = pipe_config->port_clock;
1026
1027 if (pipe_config->pixel_multiplier)
1028 dotclock /= pipe_config->pixel_multiplier;
1029
1030 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1031}
540e732c
S		 1032
1033static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1034 struct intel_crtc_state *pipe_config)
540e732c
S		 1035{
1036 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1037 int link_clock = 0;
1038 uint32_t dpll_ctl1, dpll;
1039
134ffa44 1040 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1041
1042 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1043
1044 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1045 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1046 } else {
71cd8423
DL		 1047 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1048 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1049
1050 switch (link_clock) {
71cd8423 1051 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1052 link_clock = 81000;
1053 break;
71cd8423 1054 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1055 link_clock = 108000;
1056 break;
71cd8423 1057 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1058 link_clock = 135000;
1059 break;
71cd8423 1060 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1061 link_clock = 162000;
1062 break;
71cd8423 1063 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1064 link_clock = 216000;
1065 break;
71cd8423 1066 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1067 link_clock = 270000;
1068 break;
1069 default:
1070 WARN(1, "Unsupported link rate\n");
1071 break;
1072 }
1073 link_clock *= 2;
1074 }
1075
1076 pipe_config->port_clock = link_clock;
1077
398a017e 1078 ddi_dotclock_get(pipe_config);
540e732c
S		 1079}
1080
3d51278a 1081static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1082 struct intel_crtc_state *pipe_config)
11578553
JB		 1083{
1084 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1085 int link_clock = 0;
1086 u32 val, pll;
1087
26804afd 1088 val = pipe_config->ddi_pll_sel;
11578553
JB		 1089 switch (val & PORT_CLK_SEL_MASK) {
1090 case PORT_CLK_SEL_LCPLL_810:
1091 link_clock = 81000;
1092 break;
1093 case PORT_CLK_SEL_LCPLL_1350:
1094 link_clock = 135000;
1095 break;
1096 case PORT_CLK_SEL_LCPLL_2700:
1097 link_clock = 270000;
1098 break;
1099 case PORT_CLK_SEL_WRPLL1:
01403de3 1100 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 1101 break;
1102 case PORT_CLK_SEL_WRPLL2:
01403de3 1103 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 1104 break;
1105 case PORT_CLK_SEL_SPLL:
1106 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1107 if (pll == SPLL_PLL_FREQ_810MHz)
1108 link_clock = 81000;
1109 else if (pll == SPLL_PLL_FREQ_1350MHz)
1110 link_clock = 135000;
1111 else if (pll == SPLL_PLL_FREQ_2700MHz)
1112 link_clock = 270000;
1113 else {
1114 WARN(1, "bad spll freq\n");
1115 return;
1116 }
1117 break;
1118 default:
1119 WARN(1, "bad port clock sel\n");
1120 return;
1121 }
1122
1123 pipe_config->port_clock = link_clock * 2;
1124
398a017e 1125 ddi_dotclock_get(pipe_config);
11578553
JB		 1126}
1127
977bb38d
S		 1128static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1129 enum intel_dpll_id dpll)
1130{
aa610dcb
ID		 1131 struct intel_shared_dpll *pll;
1132 struct intel_dpll_hw_state *state;
1133 intel_clock_t clock;
1134
1135 /* For DDI ports we always use a shared PLL. */
1136 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1137 return 0;
1138
1139 pll = &dev_priv->shared_dplls[dpll];
1140 state = &pll->config.hw_state;
1141
1142 clock.m1 = 2;
1143 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1144 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1145 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1146 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1147 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1148 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1149
1150 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 1151}
1152
1153static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1154 struct intel_crtc_state *pipe_config)
1155{
1156 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1157 enum port port = intel_ddi_get_encoder_port(encoder);
1158 uint32_t dpll = port;
1159
398a017e 1160 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 1161
398a017e 1162 ddi_dotclock_get(pipe_config);
977bb38d
S		 1163}
1164
3d51278a 1165void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1166 struct intel_crtc_state *pipe_config)
3d51278a 1167{
22606a18
DL		 1168 struct drm_device *dev = encoder->base.dev;
1169
1170 if (INTEL_INFO(dev)->gen <= 8)
1171 hsw_ddi_clock_get(encoder, pipe_config);
ef11bdb3 1172 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
22606a18 1173 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1174 else if (IS_BROXTON(dev))
1175 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1176}
1177
1c0b85c5 1178static void
d664c0ce
DL		 1179hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1180 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1181{
1182 uint64_t freq2k;
1183 unsigned p, n2, r2;
63582983 1184 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1185 unsigned budget;
1186
1187 freq2k = clock / 100;
1188
63582983 1189 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1190
1191 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1192 * and directly pass the LC PLL to it. */
1193 if (freq2k == 5400000) {
1194 *n2_out = 2;
1195 *p_out = 1;
1196 *r2_out = 2;
1197 return;
1198 }
1199
1200 /*
1201 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1202 * the WR PLL.
1203 *
1204 * We want R so that REF_MIN <= Ref <= REF_MAX.
1205 * Injecting R2 = 2 * R gives:
1206 * REF_MAX * r2 > LC_FREQ * 2 and
1207 * REF_MIN * r2 < LC_FREQ * 2
1208 *
1209 * Which means the desired boundaries for r2 are:
1210 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1211 *
1212 */
1213 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1214 r2 <= LC_FREQ * 2 / REF_MIN;
1215 r2++) {
1216
1217 /*
1218 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1219 *
1220 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1221 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1222 * VCO_MAX * r2 > n2 * LC_FREQ and
1223 * VCO_MIN * r2 < n2 * LC_FREQ)
1224 *
1225 * Which means the desired boundaries for n2 are:
1226 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1227 */
1228 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1229 n2 <= VCO_MAX * r2 / LC_FREQ;
1230 n2++) {
1231
1232 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1233 hsw_wrpll_update_rnp(freq2k, budget,
1234 r2, n2, p, &best);
1c0b85c5
DL		 1235 }
1236 }
6441ab5f 1237
1c0b85c5
DL		 1238 *n2_out = best.n2;
1239 *p_out = best.p;
1240 *r2_out = best.r2;
6441ab5f
PZ		 1241}
1242
0220ab6e 1243static bool
d664c0ce 1244hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1245 struct intel_crtc_state *crtc_state,
96f3f1f9 1246 struct intel_encoder *intel_encoder)
6441ab5f 1247{
96f3f1f9
VS		 1248 int clock = crtc_state->port_clock;
1249
d664c0ce 1250 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1251 struct intel_shared_dpll *pll;
716c2e55 1252 uint32_t val;
1c0b85c5 1253 unsigned p, n2, r2;
6441ab5f 1254
d664c0ce 1255 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1256
114fe488 1257 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1258 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1259 WRPLL_DIVIDER_POST(p);
1260
dd3cd74a
ACO		 1261 memset(&crtc_state->dpll_hw_state, 0,
1262 sizeof(crtc_state->dpll_hw_state));
1263
190f68c5 1264 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1265
190f68c5 1266 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1267 if (pll == NULL) {
1268 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1269 pipe_name(intel_crtc->pipe));
1270 return false;
0694001b 1271 }
d452c5b6 1272
190f68c5 1273 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
00490c22
ML		 1274 } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1275 struct drm_atomic_state *state = crtc_state->base.state;
1276 struct intel_shared_dpll_config *spll =
1277 &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1278
1279 if (spll->crtc_mask &&
1280 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1281 return false;
1282
1283 crtc_state->shared_dpll = DPLL_ID_SPLL;
1284 spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1285 spll->crtc_mask |= 1 << intel_crtc->pipe;
6441ab5f
PZ		 1286 }
1287
6441ab5f
PZ		 1288 return true;
1289}
1290
dc253813
DL		 1291struct skl_wrpll_context {
1292 uint64_t min_deviation; /* current minimal deviation */
1293 uint64_t central_freq; /* chosen central freq */
1294 uint64_t dco_freq; /* chosen dco freq */
1295 unsigned int p; /* chosen divider */
1296};
1297
1298static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1299{
1300 memset(ctx, 0, sizeof(*ctx));
1301
1302 ctx->min_deviation = U64_MAX;
1303}
1304
1305/* DCO freq must be within +1%/-6% of the DCO central freq */
1306#define SKL_DCO_MAX_PDEVIATION 100
1307#define SKL_DCO_MAX_NDEVIATION 600
1308
1309static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1310 uint64_t central_freq,
1311 uint64_t dco_freq,
1312 unsigned int divider)
1313{
1314 uint64_t deviation;
1315
1316 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1317 central_freq);
1318
1319 /* positive deviation */
1320 if (dco_freq >= central_freq) {
1321 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1322 deviation < ctx->min_deviation) {
1323 ctx->min_deviation = deviation;
1324 ctx->central_freq = central_freq;
1325 ctx->dco_freq = dco_freq;
1326 ctx->p = divider;
1327 }
1328 /* negative deviation */
1329 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1330 deviation < ctx->min_deviation) {
1331 ctx->min_deviation = deviation;
1332 ctx->central_freq = central_freq;
1333 ctx->dco_freq = dco_freq;
1334 ctx->p = divider;
1335 }
dc253813
DL		 1336}
1337
1338static void skl_wrpll_get_multipliers(unsigned int p,
1339 unsigned int *p0 /* out */,
1340 unsigned int *p1 /* out */,
1341 unsigned int *p2 /* out */)
1342{
1343 /* even dividers */
1344 if (p % 2 == 0) {
1345 unsigned int half = p / 2;
1346
1347 if (half == 1 || half == 2 || half == 3 || half == 5) {
1348 *p0 = 2;
1349 *p1 = 1;
1350 *p2 = half;
1351 } else if (half % 2 == 0) {
1352 *p0 = 2;
1353 *p1 = half / 2;
1354 *p2 = 2;
1355 } else if (half % 3 == 0) {
1356 *p0 = 3;
1357 *p1 = half / 3;
1358 *p2 = 2;
1359 } else if (half % 7 == 0) {
1360 *p0 = 7;
1361 *p1 = half / 7;
1362 *p2 = 2;
1363 }
1364 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1365 *p0 = 3;
1366 *p1 = 1;
1367 *p2 = p / 3;
1368 } else if (p == 5 || p == 7) {
1369 *p0 = p;
1370 *p1 = 1;
1371 *p2 = 1;
1372 } else if (p == 15) {
1373 *p0 = 3;
1374 *p1 = 1;
1375 *p2 = 5;
1376 } else if (p == 21) {
1377 *p0 = 7;
1378 *p1 = 1;
1379 *p2 = 3;
1380 } else if (p == 35) {
1381 *p0 = 7;
1382 *p1 = 1;
1383 *p2 = 5;
1384 }
1385}
1386
82d35437
S		 1387struct skl_wrpll_params {
1388 uint32_t dco_fraction;
1389 uint32_t dco_integer;
1390 uint32_t qdiv_ratio;
1391 uint32_t qdiv_mode;
1392 uint32_t kdiv;
1393 uint32_t pdiv;
1394 uint32_t central_freq;
1395};
1396
76516fbc
DL		 1397static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1398 uint64_t afe_clock,
1399 uint64_t central_freq,
1400 uint32_t p0, uint32_t p1, uint32_t p2)
1401{
1402 uint64_t dco_freq;
1403
76516fbc
DL		 1404 switch (central_freq) {
1405 case 9600000000ULL:
1406 params->central_freq = 0;
1407 break;
1408 case 9000000000ULL:
1409 params->central_freq = 1;
1410 break;
1411 case 8400000000ULL:
1412 params->central_freq = 3;
1413 }
1414
1415 switch (p0) {
1416 case 1:
1417 params->pdiv = 0;
1418 break;
1419 case 2:
1420 params->pdiv = 1;
1421 break;
1422 case 3:
1423 params->pdiv = 2;
1424 break;
1425 case 7:
1426 params->pdiv = 4;
1427 break;
1428 default:
1429 WARN(1, "Incorrect PDiv\n");
1430 }
1431
1432 switch (p2) {
1433 case 5:
1434 params->kdiv = 0;
1435 break;
1436 case 2:
1437 params->kdiv = 1;
1438 break;
1439 case 3:
1440 params->kdiv = 2;
1441 break;
1442 case 1:
1443 params->kdiv = 3;
1444 break;
1445 default:
1446 WARN(1, "Incorrect KDiv\n");
1447 }
1448
1449 params->qdiv_ratio = p1;
1450 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1451
1452 dco_freq = p0 * p1 * p2 * afe_clock;
1453
1454 /*
1455 * Intermediate values are in Hz.
1456 * Divide by MHz to match bsepc
1457 */
30a7862d 1458 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1459 params->dco_fraction =
30a7862d
DL		 1460 div_u64((div_u64(dco_freq, 24) -
1461 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1462}
1463
318bd821 1464static bool
82d35437
S		 1465skl_ddi_calculate_wrpll(int clock /* in Hz */,
1466 struct skl_wrpll_params *wrpll_params)
1467{
1468 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1469 uint64_t dco_central_freq[3] = {8400000000ULL,
1470 9000000000ULL,
1471 9600000000ULL};
dc253813
DL		 1472 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1473 24, 28, 30, 32, 36, 40, 42, 44,
1474 48, 52, 54, 56, 60, 64, 66, 68,
1475 70, 72, 76, 78, 80, 84, 88, 90,
1476 92, 96, 98 };
1477 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1478 static const struct {
1479 const int *list;
1480 int n_dividers;
1481 } dividers[] = {
1482 { even_dividers, ARRAY_SIZE(even_dividers) },
1483 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1484 };
1485 struct skl_wrpll_context ctx;
1486 unsigned int dco, d, i;
1487 unsigned int p0, p1, p2;
1488
1489 skl_wrpll_context_init(&ctx);
1490
1491 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1492 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1493 for (i = 0; i < dividers[d].n_dividers; i++) {
1494 unsigned int p = dividers[d].list[i];
1495 uint64_t dco_freq = p * afe_clock;
1496
1497 skl_wrpll_try_divider(&ctx,
1498 dco_central_freq[dco],
1499 dco_freq,
1500 p);
e7ad9878
DL		 1501 /*
1502 * Skip the remaining dividers if we're sure to
1503 * have found the definitive divider, we can't
1504 * improve a 0 deviation.
1505 */
1506 if (ctx.min_deviation == 0)
1507 goto skip_remaining_dividers;
82d35437
S		 1508 }
1509 }
267db663 1510
e7ad9878 1511skip_remaining_dividers:
267db663
DL		 1512 /*
1513 * If a solution is found with an even divider, prefer
1514 * this one.
1515 */
1516 if (d == 0 && ctx.p)
1517 break;
82d35437
S		 1518 }
1519
dc253813
DL		 1520 if (!ctx.p) {
1521 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1522 return false;
dc253813 1523 }
82d35437 1524
dc253813
DL		 1525 /*
1526 * gcc incorrectly analyses that these can be used without being
1527 * initialized. To be fair, it's hard to guess.
1528 */
1529 p0 = p1 = p2 = 0;
1530 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1531 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1532 p0, p1, p2);
318bd821
DL		 1533
1534 return true;
82d35437
S		 1535}
1536
82d35437
S		 1537static bool
1538skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1539 struct intel_crtc_state *crtc_state,
96f3f1f9 1540 struct intel_encoder *intel_encoder)
82d35437
S		 1541{
1542 struct intel_shared_dpll *pll;
1543 uint32_t ctrl1, cfgcr1, cfgcr2;
96f3f1f9 1544 int clock = crtc_state->port_clock;
82d35437
S		 1545
1546 /*
1547 * See comment in intel_dpll_hw_state to understand why we always use 0
1548 * as the DPLL id in this function.
1549 */
1550
1551 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1552
1553 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1554 struct skl_wrpll_params wrpll_params = { 0, };
1555
1556 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1557
318bd821
DL		 1558 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1559 return false;
82d35437
S		 1560
1561 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1562 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1563 wrpll_params.dco_integer;
1564
1565 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1566 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1567 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1568 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1569 wrpll_params.central_freq;
1570 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
840b32b7
VS		 1571 switch (crtc_state->port_clock / 2) {
1572 case 81000:
71cd8423 1573 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437 1574 break;
840b32b7 1575 case 135000:
71cd8423 1576 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437 1577 break;
840b32b7 1578 case 270000:
71cd8423 1579 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1580 break;
1581 }
1582
1583 cfgcr1 = cfgcr2 = 0;
1584 } else /* eDP */
1585 return true;
1586
dd3cd74a
ACO		 1587 memset(&crtc_state->dpll_hw_state, 0,
1588 sizeof(crtc_state->dpll_hw_state));
1589
190f68c5
ACO		 1590 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1591 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1592 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1593
190f68c5 1594 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1595 if (pll == NULL) {
1596 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1597 pipe_name(intel_crtc->pipe));
1598 return false;
1599 }
1600
1601 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1602 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1603
1604 return true;
1605}
0220ab6e 1606
d683f3bc
S		 1607/* bxt clock parameters */
1608struct bxt_clk_div {
64987fc5 1609 int clock;
d683f3bc
S		 1610 uint32_t p1;
1611 uint32_t p2;
1612 uint32_t m2_int;
1613 uint32_t m2_frac;
1614 bool m2_frac_en;
1615 uint32_t n;
d683f3bc
S		 1616};
1617
1618/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1619static const struct bxt_clk_div bxt_dp_clk_val[] = {
1620 {162000, 4, 2, 32, 1677722, 1, 1},
1621 {270000, 4, 1, 27, 0, 0, 1},
1622 {540000, 2, 1, 27, 0, 0, 1},
1623 {216000, 3, 2, 32, 1677722, 1, 1},
1624 {243000, 4, 1, 24, 1258291, 1, 1},
1625 {324000, 4, 1, 32, 1677722, 1, 1},
1626 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1627};
1628
1629static bool
1630bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1631 struct intel_crtc_state *crtc_state,
96f3f1f9 1632 struct intel_encoder *intel_encoder)
d683f3bc
S		 1633{
1634 struct intel_shared_dpll *pll;
1635 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1636 int vco = 0;
1637 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e6292556 1638 uint32_t lanestagger;
96f3f1f9 1639 int clock = crtc_state->port_clock;
d683f3bc
S		 1640
1641 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1642 intel_clock_t best_clock;
1643
1644 /* Calculate HDMI div */
1645 /*
1646 * FIXME: tie the following calculation into
1647 * i9xx_crtc_compute_clock
1648 */
1649 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1650 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1651 clock, pipe_name(intel_crtc->pipe));
1652 return false;
1653 }
1654
1655 clk_div.p1 = best_clock.p1;
1656 clk_div.p2 = best_clock.p2;
1657 WARN_ON(best_clock.m1 != 2);
1658 clk_div.n = best_clock.n;
1659 clk_div.m2_int = best_clock.m2 >> 22;
1660 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1661 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1662
b6dc71f3 1663 vco = best_clock.vco;
d683f3bc
S		 1664 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1665 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1666 int i;
d683f3bc 1667
64987fc5
SJ		 1668 clk_div = bxt_dp_clk_val[0];
1669 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1670 if (bxt_dp_clk_val[i].clock == clock) {
1671 clk_div = bxt_dp_clk_val[i];
1672 break;
1673 }
d683f3bc 1674 }
b6dc71f3
VK		 1675 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1676 }
1677
e6292556 1678 if (vco >= 6200000 && vco <= 6700000) {
b6dc71f3
VK		 1679 prop_coef = 4;
1680 int_coef = 9;
1681 gain_ctl = 3;
1682 targ_cnt = 8;
1683 } else if ((vco > 5400000 && vco < 6200000) ||
1684 (vco >= 4800000 && vco < 5400000)) {
1685 prop_coef = 5;
1686 int_coef = 11;
1687 gain_ctl = 3;
1688 targ_cnt = 9;
b6dc71f3
VK		 1689 } else if (vco == 5400000) {
1690 prop_coef = 3;
1691 int_coef = 8;
1692 gain_ctl = 1;
1693 targ_cnt = 9;
1694 } else {
1695 DRM_ERROR("Invalid VCO\n");
1696 return false;
d683f3bc
S		 1697 }
1698
dd3cd74a
ACO		 1699 memset(&crtc_state->dpll_hw_state, 0,
1700 sizeof(crtc_state->dpll_hw_state));
1701
e0681e38
VK		 1702 if (clock > 270000)
1703 lanestagger = 0x18;
1704 else if (clock > 135000)
1705 lanestagger = 0x0d;
1706 else if (clock > 67000)
1707 lanestagger = 0x07;
1708 else if (clock > 33000)
1709 lanestagger = 0x04;
1710 else
1711 lanestagger = 0x02;
1712
d683f3bc
S		 1713 crtc_state->dpll_hw_state.ebb0 =
1714 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1715 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1716 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1717 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1718
1719 if (clk_div.m2_frac_en)
1720 crtc_state->dpll_hw_state.pll3 =
1721 PORT_PLL_M2_FRAC_ENABLE;
1722
1723 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1724 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1725 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1726 PORT_PLL_GAIN_CTL(gain_ctl);
1727
1728 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1729
05712c15
ID		 1730 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1731
e6292556
VK		 1732 crtc_state->dpll_hw_state.pll10 =
1733 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1734 | PORT_PLL_DCO_AMP_OVR_EN_H;
d683f3bc 1735
05712c15
ID		 1736 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1737
d683f3bc 1738 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1739 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1740
1741 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1742 if (pll == NULL) {
1743 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1744 pipe_name(intel_crtc->pipe));
1745 return false;
1746 }
1747
1748 /* shared DPLL id 0 is DPLL A */
1749 crtc_state->ddi_pll_sel = pll->id;
1750
1751 return true;
1752}
1753
0220ab6e
DL		 1754/*
1755 * Tries to find a *shared* PLL for the CRTC and store it in
1756 * intel_crtc->ddi_pll_sel.
1757 *
1758 * For private DPLLs, compute_config() should do the selection for us. This
1759 * function should be folded into compute_config() eventually.
1760 */
190f68c5
ACO		 1761bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1762 struct intel_crtc_state *crtc_state)
0220ab6e 1763{
82d35437 1764 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1765 struct intel_encoder *intel_encoder =
3165c074 1766 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1767
ef11bdb3 1768 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
190f68c5 1769 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1770 intel_encoder);
d683f3bc
S		 1771 else if (IS_BROXTON(dev))
1772 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1773 intel_encoder);
82d35437 1774 else
190f68c5 1775 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1776 intel_encoder);
0220ab6e
DL		 1777}
1778
dae84799
PZ		 1779void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1780{
1781 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1783 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1784 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1785 int type = intel_encoder->type;
1786 uint32_t temp;
1787
0e32b39c 1788 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1789 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1790 switch (intel_crtc->config->pipe_bpp) {
dae84799 1791 case 18:
c9809791 1792 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1793 break;
1794 case 24:
c9809791 1795 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1796 break;
1797 case 30:
c9809791 1798 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1799 break;
1800 case 36:
c9809791 1801 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1802 break;
1803 default:
4e53c2e0 1804 BUG();
dae84799 1805 }
c9809791 1806 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1807 }
1808}
1809
0e32b39c
DA		 1810void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1811{
1812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1813 struct drm_device *dev = crtc->dev;
1814 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1815 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1816 uint32_t temp;
1817 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1818 if (state == true)
1819 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1820 else
1821 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1822 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1823}
1824
8228c251 1825void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1826{
1827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1828 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1829 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1830 struct drm_device *dev = crtc->dev;
1831 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1832 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1833 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1834 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1835 int type = intel_encoder->type;
8d9ddbcb
PZ		 1836 uint32_t temp;
1837
ad80a810
PZ		 1838 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1839 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1840 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1841
6e3c9717 1842 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1843 case 18:
ad80a810 1844 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1845 break;
1846 case 24:
ad80a810 1847 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1848 break;
1849 case 30:
ad80a810 1850 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1851 break;
1852 case 36:
ad80a810 1853 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1854 break;
1855 default:
4e53c2e0 1856 BUG();
dfcef252 1857 }
72662e10 1858
6e3c9717 1859 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1860 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1861 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1862 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1863
e6f0bfc4
PZ		 1864 if (cpu_transcoder == TRANSCODER_EDP) {
1865 switch (pipe) {
1866 case PIPE_A:
c7670b10
PZ		 1867 /* On Haswell, can only use the always-on power well for
1868 * eDP when not using the panel fitter, and when not
1869 * using motion blur mitigation (which we don't
1870 * support). */
fabf6e51 1871 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1872 (intel_crtc->config->pch_pfit.enabled ||
1873 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1874 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1875 else
1876 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1877 break;
1878 case PIPE_B:
1879 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1880 break;
1881 case PIPE_C:
1882 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1883 break;
1884 default:
1885 BUG();
1886 break;
1887 }
1888 }
1889
7739c33b 1890 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1891 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1892 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1893 else
ad80a810 1894 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1895
7739c33b 1896 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1897 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1898 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1899
1900 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1901 type == INTEL_OUTPUT_EDP) {
1902 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1903
0e32b39c
DA		 1904 if (intel_dp->is_mst) {
1905 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1906 } else
1907 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1908
90a6b7b0 1909 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1910 } else if (type == INTEL_OUTPUT_DP_MST) {
1911 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1912
1913 if (intel_dp->is_mst) {
1914 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1915 } else
1916 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1917
90a6b7b0 1918 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1919 } else {
84f44ce7
VS		 1920 WARN(1, "Invalid encoder type %d for pipe %c\n",
1921 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1922 }
1923
ad80a810 1924 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1925}
72662e10 1926
ad80a810
PZ		 1927void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1928 enum transcoder cpu_transcoder)
8d9ddbcb 1929{
f0f59a00 1930 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1931 uint32_t val = I915_READ(reg);
1932
0e32b39c 1933 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1934 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1935 I915_WRITE(reg, val);
72662e10
ED		 1936}
1937
bcbc889b
PZ		 1938bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1939{
1940 struct drm_device *dev = intel_connector->base.dev;
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942 struct intel_encoder *intel_encoder = intel_connector->encoder;
1943 int type = intel_connector->base.connector_type;
1944 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1945 enum pipe pipe = 0;
1946 enum transcoder cpu_transcoder;
882244a3 1947 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1948 uint32_t tmp;
1949
882244a3 1950 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1951 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1952 return false;
1953
bcbc889b
PZ		 1954 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1955 return false;
1956
1957 if (port == PORT_A)
1958 cpu_transcoder = TRANSCODER_EDP;
1959 else
1a240d4d 1960 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1961
1962 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1963
1964 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1965 case TRANS_DDI_MODE_SELECT_HDMI:
1966 case TRANS_DDI_MODE_SELECT_DVI:
1967 return (type == DRM_MODE_CONNECTOR_HDMIA);
1968
1969 case TRANS_DDI_MODE_SELECT_DP_SST:
1970 if (type == DRM_MODE_CONNECTOR_eDP)
1971 return true;
bcbc889b 1972 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1973 case TRANS_DDI_MODE_SELECT_DP_MST:
1974 /* if the transcoder is in MST state then
1975 * connector isn't connected */
1976 return false;
bcbc889b
PZ		 1977
1978 case TRANS_DDI_MODE_SELECT_FDI:
1979 return (type == DRM_MODE_CONNECTOR_VGA);
1980
1981 default:
1982 return false;
1983 }
1984}
1985
85234cdc
DV		 1986bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1987 enum pipe *pipe)
1988{
1989 struct drm_device *dev = encoder->base.dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1991 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1992 enum intel_display_power_domain power_domain;
85234cdc
DV		 1993 u32 tmp;
1994 int i;
1995
6d129bea 1996 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1997 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1998 return false;
1999
fe43d3f5 2000 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 2001
2002 if (!(tmp & DDI_BUF_CTL_ENABLE))
2003 return false;
2004
ad80a810
PZ		 2005 if (port == PORT_A) {
2006 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2007
ad80a810
PZ		 2008 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2009 case TRANS_DDI_EDP_INPUT_A_ON:
2010 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2011 *pipe = PIPE_A;
2012 break;
2013 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2014 *pipe = PIPE_B;
2015 break;
2016 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2017 *pipe = PIPE_C;
2018 break;
2019 }
2020
2021 return true;
2022 } else {
2023 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2024 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2025
2026 if ((tmp & TRANS_DDI_PORT_MASK)
2027 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2028 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2029 return false;
2030
ad80a810
PZ		 2031 *pipe = i;
2032 return true;
2033 }
85234cdc
DV		 2034 }
2035 }
2036
84f44ce7 2037 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2038
22f9fe50 2039 return false;
85234cdc
DV		 2040}
2041
fc914639
PZ		 2042void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2043{
2044 struct drm_crtc *crtc = &intel_crtc->base;
7d4aefd0
SS		 2045 struct drm_device *dev = crtc->dev;
2046 struct drm_i915_private *dev_priv = dev->dev_private;
fc914639
PZ		 2047 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2048 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2049 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2050
bb523fc0
PZ		 2051 if (cpu_transcoder != TRANSCODER_EDP)
2052 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2053 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2054}
2055
2056void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2057{
2058 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2059 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2060
bb523fc0
PZ		 2061 if (cpu_transcoder != TRANSCODER_EDP)
2062 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2063 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2064}
2065
78ab0bae
VS		 2066static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2067 u32 level, enum port port, int type)
f8896f5d 2068{
f8896f5d
DW		 2069 const struct ddi_buf_trans *ddi_translations;
2070 uint8_t iboost;
75067dde 2071 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 2072 int n_entries;
2073 u32 reg;
2074
75067dde
AK		 2075 /* VBT may override standard boost values */
2076 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2077 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2078
f8896f5d 2079 if (type == INTEL_OUTPUT_DISPLAYPORT) {
75067dde
AK		 2080 if (dp_iboost) {
2081 iboost = dp_iboost;
2082 } else {
78ab0bae 2083 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
e4d4c05b 2084 iboost = ddi_translations[level].i_boost;
75067dde 2085 }
f8896f5d 2086 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 2087 if (dp_iboost) {
2088 iboost = dp_iboost;
2089 } else {
78ab0bae 2090 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 2091
2092 if (WARN_ON(port != PORT_A &&
2093 port != PORT_E && n_entries > 9))
2094 n_entries = 9;
2095
e4d4c05b 2096 iboost = ddi_translations[level].i_boost;
75067dde 2097 }
f8896f5d 2098 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 2099 if (hdmi_iboost) {
2100 iboost = hdmi_iboost;
2101 } else {
78ab0bae 2102 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 2103 iboost = ddi_translations[level].i_boost;
75067dde 2104 }
f8896f5d
DW		 2105 } else {
2106 return;
2107 }
2108
2109 /* Make sure that the requested I_boost is valid */
2110 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2111 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2112 return;
2113 }
2114
2115 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2116 reg &= ~BALANCE_LEG_MASK(port);
2117 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2118
2119 if (iboost)
2120 reg |= iboost << BALANCE_LEG_SHIFT(port);
2121 else
2122 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2123
2124 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2125}
2126
78ab0bae
VS		 2127static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
2128 u32 level, enum port port, int type)
96fb9f9b 2129{
96fb9f9b
VK		 2130 const struct bxt_ddi_buf_trans *ddi_translations;
2131 u32 n_entries, i;
2132 uint32_t val;
2133
d9d7000d
SJ		 2134 if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2135 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2136 ddi_translations = bxt_ddi_translations_edp;
2137 } else if (type == INTEL_OUTPUT_DISPLAYPORT
2138 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 2139 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2140 ddi_translations = bxt_ddi_translations_dp;
2141 } else if (type == INTEL_OUTPUT_HDMI) {
2142 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2143 ddi_translations = bxt_ddi_translations_hdmi;
2144 } else {
2145 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2146 type);
2147 return;
2148 }
2149
2150 /* Check if default value has to be used */
2151 if (level >= n_entries ||
2152 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2153 for (i = 0; i < n_entries; i++) {
2154 if (ddi_translations[i].default_index) {
2155 level = i;
2156 break;
2157 }
2158 }
2159 }
2160
2161 /*
2162 * While we write to the group register to program all lanes at once we
2163 * can read only lane registers and we pick lanes 0/1 for that.
2164 */
2165 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2166 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2167 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2168
2169 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2170 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2171 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2172 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2173 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2174
2175 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
9c58a049 2176 val &= ~SCALE_DCOMP_METHOD;
96fb9f9b 2177 if (ddi_translations[level].enable)
9c58a049
SJ		 2178 val |= SCALE_DCOMP_METHOD;
2179
2180 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2181 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2182
96fb9f9b
VK		 2183 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2184
2185 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2186 val &= ~DE_EMPHASIS;
2187 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2188 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2189
2190 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2191 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2192 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2193}
2194
f8896f5d
DW		 2195static uint32_t translate_signal_level(int signal_levels)
2196{
2197 uint32_t level;
2198
2199 switch (signal_levels) {
2200 default:
2201 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2202 signal_levels);
2203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2204 level = 0;
2205 break;
2206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2207 level = 1;
2208 break;
2209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2210 level = 2;
2211 break;
2212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2213 level = 3;
2214 break;
2215
2216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2217 level = 4;
2218 break;
2219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2220 level = 5;
2221 break;
2222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2223 level = 6;
2224 break;
2225
2226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2227 level = 7;
2228 break;
2229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2230 level = 8;
2231 break;
2232
2233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2234 level = 9;
2235 break;
2236 }
2237
2238 return level;
2239}
2240
2241uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2242{
2243 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 2244 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d
DW		 2245 struct intel_encoder *encoder = &dport->base;
2246 uint8_t train_set = intel_dp->train_set[0];
2247 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2248 DP_TRAIN_PRE_EMPHASIS_MASK);
2249 enum port port = dport->port;
2250 uint32_t level;
2251
2252 level = translate_signal_level(signal_levels);
2253
78ab0bae
VS		 2254 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2255 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
2256 else if (IS_BROXTON(dev_priv))
2257 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
f8896f5d
DW		 2258
2259 return DDI_BUF_TRANS_SELECT(level);
2260}
2261
e404ba8d
VS		 2262void intel_ddi_clk_select(struct intel_encoder *encoder,
2263 const struct intel_crtc_state *pipe_config)
6441ab5f 2264{
e404ba8d
VS		 2265 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2266 enum port port = intel_ddi_get_encoder_port(encoder);
6441ab5f 2267
e404ba8d
VS		 2268 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2269 uint32_t dpll = pipe_config->ddi_pll_sel;
efa80add
S		 2270 uint32_t val;
2271
5416d871
DL		 2272 /*
2273 * DPLL0 is used for eDP and is the only "private" DPLL (as
2274 * opposed to shared) on SKL
2275 */
e404ba8d 2276 if (encoder->type == INTEL_OUTPUT_EDP) {
5416d871
DL		 2277 WARN_ON(dpll != SKL_DPLL0);
2278
2279 val = I915_READ(DPLL_CTRL1);
2280
2281 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2282 DPLL_CTRL1_SSC(dpll) |
71cd8423 2283 DPLL_CTRL1_LINK_RATE_MASK(dpll));
e404ba8d 2284 val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2285
2286 I915_WRITE(DPLL_CTRL1, val);
2287 POSTING_READ(DPLL_CTRL1);
2288 }
2289
2290 /* DDI -> PLL mapping */
efa80add
S		 2291 val = I915_READ(DPLL_CTRL2);
2292
2293 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2294 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2295 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2296 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2297
2298 I915_WRITE(DPLL_CTRL2, val);
5416d871 2299
e404ba8d
VS		 2300 } else if (INTEL_INFO(dev_priv)->gen < 9) {
2301 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2302 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
efa80add 2303 }
e404ba8d
VS		 2304}
2305
2306static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2307{
2308 struct drm_encoder *encoder = &intel_encoder->base;
2309 struct drm_device *dev = encoder->dev;
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2312 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2313 int type = intel_encoder->type;
2314 int hdmi_level;
2315
2316 if (type == INTEL_OUTPUT_EDP) {
2317 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2318 intel_edp_panel_on(intel_dp);
2319 }
2320
2321 intel_ddi_clk_select(intel_encoder, crtc->config);
c19b0669 2322
82a4d9c0 2323 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2324 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2325
901c2daf
VS		 2326 intel_dp_set_link_params(intel_dp, crtc->config);
2327
44905a27 2328 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2329
2330 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2331 intel_dp_start_link_train(intel_dp);
23f08d83 2332 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2333 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2334 } else if (type == INTEL_OUTPUT_HDMI) {
2335 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2336
96fb9f9b
VK		 2337 if (IS_BROXTON(dev)) {
2338 hdmi_level = dev_priv->vbt.
2339 ddi_port_info[port].hdmi_level_shift;
78ab0bae
VS		 2340 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
2341 INTEL_OUTPUT_HDMI);
96fb9f9b 2342 }
30cf6db8 2343 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2344 crtc->config->has_hdmi_sink,
2345 &crtc->config->base.adjusted_mode);
c19b0669 2346 }
6441ab5f
PZ		 2347}
2348
00c09d70 2349static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2350{
2351 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2352 struct drm_device *dev = encoder->dev;
2353 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2354 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2355 int type = intel_encoder->type;
2886e93f 2356 uint32_t val;
a836bdf9 2357 bool wait = false;
2886e93f
PZ		 2358
2359 val = I915_READ(DDI_BUF_CTL(port));
2360 if (val & DDI_BUF_CTL_ENABLE) {
2361 val &= ~DDI_BUF_CTL_ENABLE;
2362 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2363 wait = true;
2886e93f 2364 }
6441ab5f 2365
a836bdf9
PZ		 2366 val = I915_READ(DP_TP_CTL(port));
2367 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2368 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2369 I915_WRITE(DP_TP_CTL(port), val);
2370
2371 if (wait)
2372 intel_wait_ddi_buf_idle(dev_priv, port);
2373
76bb80ed 2374 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2375 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2376 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2377 intel_edp_panel_vdd_on(intel_dp);
4be73780 2378 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2379 }
2380
ef11bdb3 2381 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
efa80add
S		 2382 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2383 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2384 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2385 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2386}
2387
00c09d70 2388static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2389{
6547fef8 2390 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2391 struct drm_crtc *crtc = encoder->crtc;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2393 struct drm_device *dev = encoder->dev;
72662e10 2394 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2395 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2396 int type = intel_encoder->type;
72662e10 2397
6547fef8 2398 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2399 struct intel_digital_port *intel_dig_port =
2400 enc_to_dig_port(encoder);
2401
6547fef8
PZ		 2402 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2403 * are ignored so nothing special needs to be done besides
2404 * enabling the port.
2405 */
876a8cdf 2406 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2407 intel_dig_port->saved_port_bits |
2408 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2409 } else if (type == INTEL_OUTPUT_EDP) {
2410 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2411
23f08d83 2412 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2413 intel_dp_stop_link_train(intel_dp);
2414
4be73780 2415 intel_edp_backlight_on(intel_dp);
0bc12bcb 2416 intel_psr_enable(intel_dp);
c395578e 2417 intel_edp_drrs_enable(intel_dp);
6547fef8 2418 }
7b9f35a6 2419
6e3c9717 2420 if (intel_crtc->config->has_audio) {
d45a0bf5 2421 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2422 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2423 }
5ab432ef
DV		 2424}
2425
00c09d70 2426static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2427{
d6c50ff8 2428 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2429 struct drm_crtc *crtc = encoder->crtc;
2430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2431 int type = intel_encoder->type;
7b9f35a6
WX		 2432 struct drm_device *dev = encoder->dev;
2433 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2434
6e3c9717 2435 if (intel_crtc->config->has_audio) {
69bfe1a9 2436 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2437 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2438 }
2831d842 2439
d6c50ff8
PZ		 2440 if (type == INTEL_OUTPUT_EDP) {
2441 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2442
c395578e 2443 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2444 intel_psr_disable(intel_dp);
4be73780 2445 intel_edp_backlight_off(intel_dp);
d6c50ff8 2446 }
72662e10 2447}
79f689aa 2448
00490c22 2449static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
e0b01be4
DV		 2450 struct intel_shared_dpll *pll)
2451{
3e369b76 2452 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2453 POSTING_READ(WRPLL_CTL(pll->id));
2454 udelay(20);
2455}
2456
00490c22 2457static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
12030431 2458 struct intel_shared_dpll *pll)
00490c22
ML		 2459{
2460 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2461 POSTING_READ(SPLL_CTL);
2462 udelay(20);
2463}
2464
2465static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2466 struct intel_shared_dpll *pll)
12030431
DV		 2467{
2468 uint32_t val;
2469
2470 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2471 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2472 POSTING_READ(WRPLL_CTL(pll->id));
2473}
2474
00490c22
ML		 2475static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2476 struct intel_shared_dpll *pll)
2477{
2478 uint32_t val;
2479
2480 val = I915_READ(SPLL_CTL);
2481 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2482 POSTING_READ(SPLL_CTL);
2483}
2484
2485static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2486 struct intel_shared_dpll *pll,
2487 struct intel_dpll_hw_state *hw_state)
d452c5b6
DV		 2488{
2489 uint32_t val;
2490
f458ebbc 2491 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2492 return false;
2493
2494 val = I915_READ(WRPLL_CTL(pll->id));
2495 hw_state->wrpll = val;
2496
2497 return val & WRPLL_PLL_ENABLE;
2498}
2499
00490c22
ML		 2500static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2501 struct intel_shared_dpll *pll,
2502 struct intel_dpll_hw_state *hw_state)
2503{
2504 uint32_t val;
2505
2506 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2507 return false;
2508
2509 val = I915_READ(SPLL_CTL);
2510 hw_state->spll = val;
2511
2512 return val & SPLL_PLL_ENABLE;
2513}
2514
2515
ca1381b5 2516static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2517 "WRPLL 1",
2518 "WRPLL 2",
00490c22 2519 "SPLL"
9cd86933
DV		 2520};
2521
143b307c 2522static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2523{
9cd86933
DV		 2524 int i;
2525
00490c22 2526 dev_priv->num_shared_dpll = 3;
9cd86933 2527
00490c22 2528 for (i = 0; i < 2; i++) {
9cd86933
DV		 2529 dev_priv->shared_dplls[i].id = i;
2530 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
00490c22
ML		 2531 dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2532 dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
d452c5b6 2533 dev_priv->shared_dplls[i].get_hw_state =
00490c22 2534 hsw_ddi_wrpll_get_hw_state;
9cd86933 2535 }
00490c22
ML		 2536
2537 /* SPLL is special, but needs to be initialized anyway.. */
2538 dev_priv->shared_dplls[i].id = i;
2539 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2540 dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2541 dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2542 dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2543
143b307c
DL		 2544}
2545
d1a2dc78
S		 2546static const char * const skl_ddi_pll_names[] = {
2547 "DPLL 1",
2548 "DPLL 2",
2549 "DPLL 3",
2550};
2551
2552struct skl_dpll_regs {
f0f59a00 2553 i915_reg_t ctl, cfgcr1, cfgcr2;
d1a2dc78
S		 2554};
2555
2556/* this array is indexed by the *shared* pll id */
2557static const struct skl_dpll_regs skl_dpll_regs[3] = {
2558 {
2559 /* DPLL 1 */
2560 .ctl = LCPLL2_CTL,
923c1241
VS		 2561 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2562 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
d1a2dc78
S		 2563 },
2564 {
2565 /* DPLL 2 */
01403de3 2566 .ctl = WRPLL_CTL(0),
923c1241
VS		 2567 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2568 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
d1a2dc78
S		 2569 },
2570 {
2571 /* DPLL 3 */
01403de3 2572 .ctl = WRPLL_CTL(1),
923c1241
VS		 2573 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2574 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
d1a2dc78
S		 2575 },
2576};
2577
2578static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2579 struct intel_shared_dpll *pll)
2580{
2581 uint32_t val;
2582 unsigned int dpll;
2583 const struct skl_dpll_regs *regs = skl_dpll_regs;
2584
2585 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2586 dpll = pll->id + 1;
2587
2588 val = I915_READ(DPLL_CTRL1);
2589
2590 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2591 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2592 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2593
2594 I915_WRITE(DPLL_CTRL1, val);
2595 POSTING_READ(DPLL_CTRL1);
2596
2597 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2598 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2599 POSTING_READ(regs[pll->id].cfgcr1);
2600 POSTING_READ(regs[pll->id].cfgcr2);
2601
2602 /* the enable bit is always bit 31 */
2603 I915_WRITE(regs[pll->id].ctl,
2604 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2605
2606 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2607 DRM_ERROR("DPLL %d not locked\n", dpll);
2608}
2609
2610static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2611 struct intel_shared_dpll *pll)
2612{
2613 const struct skl_dpll_regs *regs = skl_dpll_regs;
2614
2615 /* the enable bit is always bit 31 */
2616 I915_WRITE(regs[pll->id].ctl,
2617 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2618 POSTING_READ(regs[pll->id].ctl);
2619}
2620
2621static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2622 struct intel_shared_dpll *pll,
2623 struct intel_dpll_hw_state *hw_state)
2624{
2625 uint32_t val;
2626 unsigned int dpll;
2627 const struct skl_dpll_regs *regs = skl_dpll_regs;
2628
2629 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2630 return false;
2631
2632 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2633 dpll = pll->id + 1;
2634
2635 val = I915_READ(regs[pll->id].ctl);
2636 if (!(val & LCPLL_PLL_ENABLE))
2637 return false;
2638
2639 val = I915_READ(DPLL_CTRL1);
2640 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2641
2642 /* avoid reading back stale values if HDMI mode is not enabled */
2643 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2644 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2645 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2646 }
2647
2648 return true;
2649}
2650
2651static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2652{
2653 int i;
2654
2655 dev_priv->num_shared_dpll = 3;
2656
2657 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2658 dev_priv->shared_dplls[i].id = i;
2659 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2660 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2661 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2662 dev_priv->shared_dplls[i].get_hw_state =
2663 skl_ddi_pll_get_hw_state;
2664 }
2665}
2666
5c6706e5
VK		 2667static void broxton_phy_init(struct drm_i915_private *dev_priv,
2668 enum dpio_phy phy)
2669{
2670 enum port port;
2671 uint32_t val;
2672
2673 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2674 val |= GT_DISPLAY_POWER_ON(phy);
2675 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2676
2677 /* Considering 10ms timeout until BSpec is updated */
2678 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2679 DRM_ERROR("timeout during PHY%d power on\n", phy);
2680
2681 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2682 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2683 int lane;
2684
2685 for (lane = 0; lane < 4; lane++) {
2686 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2687 /*
2688 * Note that on CHV this flag is called UPAR, but has
2689 * the same function.
2690 */
2691 val &= ~LATENCY_OPTIM;
2692 if (lane != 1)
2693 val |= LATENCY_OPTIM;
2694
2695 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2696 }
2697 }
2698
2699 /* Program PLL Rcomp code offset */
2700 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2701 val &= ~IREF0RC_OFFSET_MASK;
2702 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2703 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2704
2705 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2706 val &= ~IREF1RC_OFFSET_MASK;
2707 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2708 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2709
2710 /* Program power gating */
2711 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2712 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2713 SUS_CLK_CONFIG;
2714 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2715
2716 if (phy == DPIO_PHY0) {
2717 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2718 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2719 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2720 }
2721
2722 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2723 val &= ~OCL2_LDOFUSE_PWR_DIS;
2724 /*
2725 * On PHY1 disable power on the second channel, since no port is
2726 * connected there. On PHY0 both channels have a port, so leave it
2727 * enabled.
2728 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2729 * power down the second channel on PHY0 as well.
2730 */
2731 if (phy == DPIO_PHY1)
2732 val |= OCL2_LDOFUSE_PWR_DIS;
2733 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2734
2735 if (phy == DPIO_PHY0) {
2736 uint32_t grc_code;
2737 /*
2738 * PHY0 isn't connected to an RCOMP resistor so copy over
2739 * the corresponding calibrated value from PHY1, and disable
2740 * the automatic calibration on PHY0.
2741 */
2742 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2743 10))
2744 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2745
2746 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2747 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2748 grc_code = val << GRC_CODE_FAST_SHIFT |
2749 val << GRC_CODE_SLOW_SHIFT |
2750 val;
2751 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2752
2753 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2754 val |= GRC_DIS | GRC_RDY_OVRD;
2755 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2756 }
2757
2758 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2759 val |= COMMON_RESET_DIS;
2760 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2761}
2762
2763void broxton_ddi_phy_init(struct drm_device *dev)
2764{
2765 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2766 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2767 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2768}
2769
2770static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2771 enum dpio_phy phy)
2772{
2773 uint32_t val;
2774
2775 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2776 val &= ~COMMON_RESET_DIS;
2777 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2778}
2779
2780void broxton_ddi_phy_uninit(struct drm_device *dev)
2781{
2782 struct drm_i915_private *dev_priv = dev->dev_private;
2783
2784 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2785 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2786
2787 /* FIXME: do this in broxton_phy_uninit per phy */
2788 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2789}
2790
dfb82408
S		 2791static const char * const bxt_ddi_pll_names[] = {
2792 "PORT PLL A",
2793 "PORT PLL B",
2794 "PORT PLL C",
2795};
2796
2797static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2798 struct intel_shared_dpll *pll)
2799{
2800 uint32_t temp;
2801 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2802
2803 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2804 temp &= ~PORT_PLL_REF_SEL;
2805 /* Non-SSC reference */
2806 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2807
2808 /* Disable 10 bit clock */
2809 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2810 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2811 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2812
2813 /* Write P1 & P2 */
2814 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2815 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2816 temp |= pll->config.hw_state.ebb0;
2817 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2818
2819 /* Write M2 integer */
2820 temp = I915_READ(BXT_PORT_PLL(port, 0));
2821 temp &= ~PORT_PLL_M2_MASK;
2822 temp |= pll->config.hw_state.pll0;
2823 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2824
2825 /* Write N */
2826 temp = I915_READ(BXT_PORT_PLL(port, 1));
2827 temp &= ~PORT_PLL_N_MASK;
2828 temp |= pll->config.hw_state.pll1;
2829 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2830
2831 /* Write M2 fraction */
2832 temp = I915_READ(BXT_PORT_PLL(port, 2));
2833 temp &= ~PORT_PLL_M2_FRAC_MASK;
2834 temp |= pll->config.hw_state.pll2;
2835 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2836
2837 /* Write M2 fraction enable */
2838 temp = I915_READ(BXT_PORT_PLL(port, 3));
2839 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2840 temp |= pll->config.hw_state.pll3;
2841 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2842
2843 /* Write coeff */
2844 temp = I915_READ(BXT_PORT_PLL(port, 6));
2845 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2846 temp &= ~PORT_PLL_INT_COEFF_MASK;
2847 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2848 temp |= pll->config.hw_state.pll6;
2849 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2850
2851 /* Write calibration val */
2852 temp = I915_READ(BXT_PORT_PLL(port, 8));
2853 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2854 temp |= pll->config.hw_state.pll8;
2855 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2856
b6dc71f3
VK		 2857 temp = I915_READ(BXT_PORT_PLL(port, 9));
2858 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
05712c15 2859 temp |= pll->config.hw_state.pll9;
b6dc71f3
VK		 2860 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2861
2862 temp = I915_READ(BXT_PORT_PLL(port, 10));
2863 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2864 temp &= ~PORT_PLL_DCO_AMP_MASK;
2865 temp |= pll->config.hw_state.pll10;
2866 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2867
2868 /* Recalibrate with new settings */
2869 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2870 temp |= PORT_PLL_RECALIBRATE;
2871 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
05712c15
ID		 2872 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2873 temp |= pll->config.hw_state.ebb4;
dfb82408
S		 2874 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2875
2876 /* Enable PLL */
2877 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2878 temp |= PORT_PLL_ENABLE;
2879 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2880 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2881
2882 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2883 PORT_PLL_LOCK), 200))
2884 DRM_ERROR("PLL %d not locked\n", port);
2885
2886 /*
2887 * While we write to the group register to program all lanes at once we
2888 * can read only lane registers and we pick lanes 0/1 for that.
2889 */
2890 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2891 temp &= ~LANE_STAGGER_MASK;
2892 temp &= ~LANESTAGGER_STRAP_OVRD;
2893 temp |= pll->config.hw_state.pcsdw12;
2894 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2895}
2896
2897static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2898 struct intel_shared_dpll *pll)
2899{
2900 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2901 uint32_t temp;
2902
2903 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2904 temp &= ~PORT_PLL_ENABLE;
2905 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2906 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2907}
2908
2909static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2910 struct intel_shared_dpll *pll,
2911 struct intel_dpll_hw_state *hw_state)
2912{
2913 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2914 uint32_t val;
2915
2916 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2917 return false;
2918
2919 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2920 if (!(val & PORT_PLL_ENABLE))
2921 return false;
2922
2923 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
793dfa59
ID		 2924 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2925
05712c15
ID		 2926 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2927 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2928
dfb82408 2929 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
793dfa59
ID		 2930 hw_state->pll0 &= PORT_PLL_M2_MASK;
2931
dfb82408 2932 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
793dfa59
ID		 2933 hw_state->pll1 &= PORT_PLL_N_MASK;
2934
dfb82408 2935 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
793dfa59
ID		 2936 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2937
dfb82408 2938 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
793dfa59
ID		 2939 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2940
dfb82408 2941 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
793dfa59
ID		 2942 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2943 PORT_PLL_INT_COEFF_MASK |
2944 PORT_PLL_GAIN_CTL_MASK;
2945
dfb82408 2946 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
793dfa59
ID		 2947 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2948
05712c15
ID		 2949 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2950 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2951
b6dc71f3 2952 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
793dfa59
ID		 2953 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2954 PORT_PLL_DCO_AMP_MASK;
2955
dfb82408
S		 2956 /*
2957 * While we write to the group register to program all lanes at once we
2958 * can read only lane registers. We configure all lanes the same way, so
2959 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2960 */
2961 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
b5dada82 2962 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
dfb82408
S		 2963 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2964 hw_state->pcsdw12,
2965 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
793dfa59 2966 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
dfb82408
S		 2967
2968 return true;
2969}
2970
2971static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2972{
2973 int i;
2974
2975 dev_priv->num_shared_dpll = 3;
2976
2977 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2978 dev_priv->shared_dplls[i].id = i;
2979 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2980 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2981 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2982 dev_priv->shared_dplls[i].get_hw_state =
2983 bxt_ddi_pll_get_hw_state;
2984 }
2985}
2986
143b307c
DL		 2987void intel_ddi_pll_init(struct drm_device *dev)
2988{
2989 struct drm_i915_private *dev_priv = dev->dev_private;
2990 uint32_t val = I915_READ(LCPLL_CTL);
2991
ef11bdb3 2992 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
d1a2dc78 2993 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2994 else if (IS_BROXTON(dev))
2995 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2996 else
2997 hsw_shared_dplls_init(dev_priv);
79f689aa 2998
ef11bdb3 2999 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
d9062ae5
DL		 3000 int cdclk_freq;
3001
3002 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 3003 dev_priv->skl_boot_cdclk = cdclk_freq;
c73666f3
SK		 3004 if (skl_sanitize_cdclk(dev_priv))
3005 DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n");
2f693e28
DL		 3006 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
3007 DRM_ERROR("LCPLL1 is disabled\n");
f8437dd1
VK		 3008 } else if (IS_BROXTON(dev)) {
3009 broxton_init_cdclk(dev);
5c6706e5 3010 broxton_ddi_phy_init(dev);
121643c2
S		 3011 } else {
3012 /*
3013 * The LCPLL register should be turned on by the BIOS. For now
3014 * let's just check its state and print errors in case
3015 * something is wrong. Don't even try to turn it on.
3016 */
3017
3018 if (val & LCPLL_CD_SOURCE_FCLK)
3019 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 3020
121643c2
S		 3021 if (val & LCPLL_PLL_DISABLE)
3022 DRM_ERROR("LCPLL is disabled\n");
3023 }
79f689aa 3024}
c19b0669 3025
ad64217b 3026void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 3027{
ad64217b
ACO		 3028 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3029 struct drm_i915_private *dev_priv =
3030 to_i915(intel_dig_port->base.base.dev);
174edf1f 3031 enum port port = intel_dig_port->port;
c19b0669 3032 uint32_t val;
f3e227df 3033 bool wait = false;
c19b0669
PZ		 3034
3035 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3036 val = I915_READ(DDI_BUF_CTL(port));
3037 if (val & DDI_BUF_CTL_ENABLE) {
3038 val &= ~DDI_BUF_CTL_ENABLE;
3039 I915_WRITE(DDI_BUF_CTL(port), val);
3040 wait = true;
3041 }
3042
3043 val = I915_READ(DP_TP_CTL(port));
3044 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3045 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3046 I915_WRITE(DP_TP_CTL(port), val);
3047 POSTING_READ(DP_TP_CTL(port));
3048
3049 if (wait)
3050 intel_wait_ddi_buf_idle(dev_priv, port);
3051 }
3052
0e32b39c 3053 val = DP_TP_CTL_ENABLE |
c19b0669 3054 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 3055 if (intel_dp->is_mst)
3056 val |= DP_TP_CTL_MODE_MST;
3057 else {
3058 val |= DP_TP_CTL_MODE_SST;
3059 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3060 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3061 }
c19b0669
PZ		 3062 I915_WRITE(DP_TP_CTL(port), val);
3063 POSTING_READ(DP_TP_CTL(port));
3064
3065 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3066 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3067 POSTING_READ(DDI_BUF_CTL(port));
3068
3069 udelay(600);
3070}
00c09d70 3071
1ad960f2
PZ		 3072void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3073{
3074 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3075 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3076 uint32_t val;
3077
3078 intel_ddi_post_disable(intel_encoder);
3079
eede3b53 3080 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3081 val &= ~FDI_RX_ENABLE;
eede3b53 3082 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 3083
eede3b53 3084 val = I915_READ(FDI_RX_MISC(PIPE_A));
1ad960f2
PZ		 3085 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3086 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53 3087 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1ad960f2 3088
eede3b53 3089 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3090 val &= ~FDI_PCDCLK;
eede3b53 3091 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 3092
eede3b53 3093 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 3094 val &= ~FDI_RX_PLL_ENABLE;
eede3b53 3095 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2
PZ		 3096}
3097
3d52ccf5
LY		 3098bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3099 struct intel_crtc *intel_crtc)
3100{
3101 u32 temp;
3102
3103 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3104 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3105 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3106 return true;
3107 }
3108 return false;
3109}
3110
6801c18c 3111void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 3112 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 3113{
3114 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3115 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 3116 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 3117 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 3118 u32 temp, flags = 0;
3119
3120 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3121 if (temp & TRANS_DDI_PHSYNC)
3122 flags |= DRM_MODE_FLAG_PHSYNC;
3123 else
3124 flags |= DRM_MODE_FLAG_NHSYNC;
3125 if (temp & TRANS_DDI_PVSYNC)
3126 flags |= DRM_MODE_FLAG_PVSYNC;
3127 else
3128 flags |= DRM_MODE_FLAG_NVSYNC;
3129
2d112de7 3130 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3131
3132 switch (temp & TRANS_DDI_BPC_MASK) {
3133 case TRANS_DDI_BPC_6:
3134 pipe_config->pipe_bpp = 18;
3135 break;
3136 case TRANS_DDI_BPC_8:
3137 pipe_config->pipe_bpp = 24;
3138 break;
3139 case TRANS_DDI_BPC_10:
3140 pipe_config->pipe_bpp = 30;
3141 break;
3142 case TRANS_DDI_BPC_12:
3143 pipe_config->pipe_bpp = 36;
3144 break;
3145 default:
3146 break;
3147 }
eb14cb74
VS		 3148
3149 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3150 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3151 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3152 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3153
cda0aaaf 3154 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 3155 pipe_config->has_infoframe = true;
cbc572a9 3156 break;
eb14cb74
VS		 3157 case TRANS_DDI_MODE_SELECT_DVI:
3158 case TRANS_DDI_MODE_SELECT_FDI:
3159 break;
3160 case TRANS_DDI_MODE_SELECT_DP_SST:
3161 case TRANS_DDI_MODE_SELECT_DP_MST:
3162 pipe_config->has_dp_encoder = true;
90a6b7b0
VS		 3163 pipe_config->lane_count =
3164 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 3165 intel_dp_get_m_n(intel_crtc, pipe_config);
3166 break;
3167 default:
3168 break;
3169 }
10214420 3170
3d52ccf5
LY		 3171 pipe_config->has_audio =
3172 intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
9ed109a7 3173
10214420
DV		 3174 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3175 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3176 /*
3177 * This is a big fat ugly hack.
3178 *
3179 * Some machines in UEFI boot mode provide us a VBT that has 18
3180 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3181 * unknown we fail to light up. Yet the same BIOS boots up with
3182 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3183 * max, not what it tells us to use.
3184 *
3185 * Note: This will still be broken if the eDP panel is not lit
3186 * up by the BIOS, and thus we can't get the mode at module
3187 * load.
3188 */
3189 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3190 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3191 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3192 }
11578553 3193
22606a18 3194 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3195}
3196
00c09d70
PZ		 3197static void intel_ddi_destroy(struct drm_encoder *encoder)
3198{
3199 /* HDMI has nothing special to destroy, so we can go with this. */
3200 intel_dp_encoder_destroy(encoder);
3201}
3202
5bfe2ac0 3203static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3204 struct intel_crtc_state *pipe_config)
00c09d70 3205{
5bfe2ac0 3206 int type = encoder->type;
eccb140b 3207 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3208
5bfe2ac0 3209 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3210
eccb140b
DV		 3211 if (port == PORT_A)
3212 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3213
00c09d70 3214 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3215 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3216 else
5bfe2ac0 3217 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3218}
3219
3220static const struct drm_encoder_funcs intel_ddi_funcs = {
3221 .destroy = intel_ddi_destroy,
3222};
3223
4a28ae58
PZ		 3224static struct intel_connector *
3225intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3226{
3227 struct intel_connector *connector;
3228 enum port port = intel_dig_port->port;
3229
9bdbd0b9 3230 connector = intel_connector_alloc();
4a28ae58
PZ		 3231 if (!connector)
3232 return NULL;
3233
3234 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3235 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3236 kfree(connector);
3237 return NULL;
3238 }
3239
3240 return connector;
3241}
3242
3243static struct intel_connector *
3244intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3245{
3246 struct intel_connector *connector;
3247 enum port port = intel_dig_port->port;
3248
9bdbd0b9 3249 connector = intel_connector_alloc();
4a28ae58
PZ		 3250 if (!connector)
3251 return NULL;
3252
3253 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3254 intel_hdmi_init_connector(intel_dig_port, connector);
3255
3256 return connector;
3257}
3258
00c09d70
PZ		 3259void intel_ddi_init(struct drm_device *dev, enum port port)
3260{
876a8cdf 3261 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3262 struct intel_digital_port *intel_dig_port;
3263 struct intel_encoder *intel_encoder;
3264 struct drm_encoder *encoder;
311a2094 3265 bool init_hdmi, init_dp;
10e7bec3
VS		 3266 int max_lanes;
3267
3268 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
3269 switch (port) {
3270 case PORT_A:
3271 max_lanes = 4;
3272 break;
3273 case PORT_E:
3274 max_lanes = 0;
3275 break;
3276 default:
3277 max_lanes = 4;
3278 break;
3279 }
3280 } else {
3281 switch (port) {
3282 case PORT_A:
3283 max_lanes = 2;
3284 break;
3285 case PORT_E:
3286 max_lanes = 2;
3287 break;
3288 default:
3289 max_lanes = 4;
3290 break;
3291 }
3292 }
311a2094
PZ		 3293
3294 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3295 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3296 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3297 if (!init_dp && !init_hdmi) {
500ea70d 3298 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 3299 port_name(port));
500ea70d 3300 return;
311a2094 3301 }
00c09d70 3302
b14c5679 3303 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3304 if (!intel_dig_port)
3305 return;
3306
00c09d70
PZ		 3307 intel_encoder = &intel_dig_port->base;
3308 encoder = &intel_encoder->base;
3309
3310 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3311 DRM_MODE_ENCODER_TMDS);
00c09d70 3312
5bfe2ac0 3313 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3314 intel_encoder->enable = intel_enable_ddi;
3315 intel_encoder->pre_enable = intel_ddi_pre_enable;
3316 intel_encoder->disable = intel_disable_ddi;
3317 intel_encoder->post_disable = intel_ddi_post_disable;
3318 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3319 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3320
3321 intel_dig_port->port = port;
0bdf5a05 3322 dev_priv->dig_port_map[port] = intel_encoder;
bcf53de4
SM		 3323 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3324 (DDI_BUF_PORT_REVERSAL |
3325 DDI_A_4_LANES);
ccb1a831 3326 intel_dig_port->max_lanes = max_lanes;
00c09d70 3327
6c566dc9
MR		 3328 /*
3329 * Bspec says that DDI_A_4_LANES is the only supported configuration
3330 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
3331 * wasn't lit up at boot. Force this bit on in our internal
3332 * configuration so that we use the proper lane count for our
3333 * calculations.
3334 */
3335 if (IS_BROXTON(dev) && port == PORT_A) {
3336 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
3337 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
3338 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
3339 }
3340 }
3341
00c09d70 3342 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3343 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3344 intel_encoder->cloneable = 0;
00c09d70 3345
f68d697e
CW		 3346 if (init_dp) {
3347 if (!intel_ddi_init_dp_connector(intel_dig_port))
3348 goto err;
13cf5504 3349
f68d697e 3350 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 3351 /*
3352 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3353 * interrupts to check the external panel connection.
3354 */
e87a005d 3355 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
cf1d5883
SJ		 3356 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3357 else
3358 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3359 }
21a8e6a4 3360
311a2094
PZ		 3361 /* In theory we don't need the encoder->type check, but leave it just in
3362 * case we have some really bad VBTs... */
f68d697e
CW		 3363 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3364 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3365 goto err;
21a8e6a4 3366 }
f68d697e
CW		 3367
3368 return;
3369
3370err:
3371 drm_encoder_cleanup(encoder);
3372 kfree(intel_dig_port);
00c09d70 3373}
Linux 6.x block layer and io_uring tree(s)