[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_csr.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */
#include <linux/firmware.h>
#include "i915_drv.h"
#include "i915_reg.h"

/**
 * DOC: csr support for dmc
 *
 * Display Context Save and Restore (CSR) firmware support added from gen9
 * onwards to drive newly added DMC (Display microcontroller) in display
 * engine to save and restore the state of display engine when it enter into
 * low-power state and comes back to normal.
 *
 * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
 * FW_LOADED, FW_FAILED.
 *
 * Once the firmware is written into the registers status will be moved from
 * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
 * be moved to FW_FAILED.
 */

#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"

#define FIRMWARE_URL  "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"

MODULE_FIRMWARE(I915_CSR_SKL);
MODULE_FIRMWARE(I915_CSR_BXT);

#define SKL_CSR_VERSION_REQUIRED	CSR_VERSION(1, 23)

#define CSR_MAX_FW_SIZE			0x2FFF
#define CSR_DEFAULT_FW_OFFSET		0xFFFFFFFF

struct intel_css_header {
	/* 0x09 for DMC */
	uint32_t module_type;

	/* Includes the DMC specific header in dwords */
	uint32_t header_len;

	/* always value would be 0x10000 */
	uint32_t header_ver;

	/* Not used */
	uint32_t module_id;

	/* Not used */
	uint32_t module_vendor;

	/* in YYYYMMDD format */
	uint32_t date;

	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
	uint32_t size;

	/* Not used */
	uint32_t key_size;

	/* Not used */
	uint32_t modulus_size;

	/* Not used */
	uint32_t exponent_size;

	/* Not used */
	uint32_t reserved1[12];

	/* Major Minor */
	uint32_t version;

	/* Not used */
	uint32_t reserved2[8];

	/* Not used */
	uint32_t kernel_header_info;
} __packed;

struct intel_fw_info {
	uint16_t reserved1;

	/* Stepping (A, B, C, ..., *). * is a wildcard */
	char stepping;

	/* Sub-stepping (0, 1, ..., *). * is a wildcard */
	char substepping;

	uint32_t offset;
	uint32_t reserved2;
} __packed;

struct intel_package_header {
	/* DMC container header length in dwords */
	unsigned char header_len;

	/* always value would be 0x01 */
	unsigned char header_ver;

	unsigned char reserved[10];

	/* Number of valid entries in the FWInfo array below */
	uint32_t num_entries;

	struct intel_fw_info fw_info[20];
} __packed;

struct intel_dmc_header {
	/* always value would be 0x40403E3E */
	uint32_t signature;

	/* DMC binary header length */
	unsigned char header_len;

	/* 0x01 */
	unsigned char header_ver;

	/* Reserved */
	uint16_t dmcc_ver;

	/* Major, Minor */
	uint32_t	project;

	/* Firmware program size (excluding header) in dwords */
	uint32_t	fw_size;

	/* Major Minor version */
	uint32_t fw_version;

	/* Number of valid MMIO cycles present. */
	uint32_t mmio_count;

	/* MMIO address */
	uint32_t mmioaddr[8];

	/* MMIO data */
	uint32_t mmiodata[8];

	/* FW filename  */
	unsigned char dfile[32];

	uint32_t reserved1[2];
} __packed;

struct stepping_info {
	char stepping;
	char substepping;
};

/*
 * Kabylake derivated from Skylake H0, so SKL H0
 * is the right firmware for KBL A0 (revid 0).
 */
static const struct stepping_info kbl_stepping_info[] = {
	{'H', '0'}, {'I', '0'}
};

static const struct stepping_info skl_stepping_info[] = {
	{'A', '0'}, {'B', '0'}, {'C', '0'},
	{'D', '0'}, {'E', '0'}, {'F', '0'},
	{'G', '0'}, {'H', '0'}, {'I', '0'},
	{'J', '0'}, {'K', '0'}
};

static const struct stepping_info bxt_stepping_info[] = {
	{'A', '0'}, {'A', '1'}, {'A', '2'},
	{'B', '0'}, {'B', '1'}, {'B', '2'}
};

static const struct stepping_info *intel_get_stepping_info(struct drm_device *dev)
{
	const struct stepping_info *si;
	unsigned int size;

	if (IS_KABYLAKE(dev)) {
		size = ARRAY_SIZE(kbl_stepping_info);
		si = kbl_stepping_info;
	} else if (IS_SKYLAKE(dev)) {
		size = ARRAY_SIZE(skl_stepping_info);
		si = skl_stepping_info;
	} else if (IS_BROXTON(dev)) {
		size = ARRAY_SIZE(bxt_stepping_info);
		si = bxt_stepping_info;
	} else {
		return NULL;
	}

	if (INTEL_REVID(dev) < size)
		return si + INTEL_REVID(dev);

	return NULL;
}

/**
 * intel_csr_load_program() - write the firmware from memory to register.
 * @dev_priv: i915 drm device.
 *
 * CSR firmware is read from a .bin file and kept in internal memory one time.
 * Everytime display comes back from low power state this function is called to
 * copy the firmware from internal memory to registers.
 */
bool intel_csr_load_program(struct drm_i915_private *dev_priv)
{
	u32 *payload = dev_priv->csr.dmc_payload;
	uint32_t i, fw_size;

	if (!IS_GEN9(dev_priv)) {
		DRM_ERROR("No CSR support available for this platform\n");
		return false;
	}

	if (!dev_priv->csr.dmc_payload) {
		DRM_ERROR("Tried to program CSR with empty payload\n");
		return false;
	}

	fw_size = dev_priv->csr.dmc_fw_size;
	for (i = 0; i < fw_size; i++)
		I915_WRITE(CSR_PROGRAM(i), payload[i]);

	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
		I915_WRITE(dev_priv->csr.mmioaddr[i],
			   dev_priv->csr.mmiodata[i]);
	}

	dev_priv->csr.dc_state = 0;

	return true;
}

static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
			      const struct firmware *fw)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_css_header *css_header;
	struct intel_package_header *package_header;
	struct intel_dmc_header *dmc_header;
	struct intel_csr *csr = &dev_priv->csr;
	const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
	char stepping, substepping;
	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
	uint32_t i;
	uint32_t *dmc_payload;

	if (!fw)
		return NULL;

	if (!stepping_info) {
		DRM_ERROR("Unknown stepping info, firmware loading failed\n");
		return NULL;
	}

	stepping = stepping_info->stepping;
	substepping = stepping_info->substepping;

	/* Extract CSS Header information*/
	css_header = (struct intel_css_header *)fw->data;
	if (sizeof(struct intel_css_header) !=
	    (css_header->header_len * 4)) {
		DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
			  (css_header->header_len * 4));
		return NULL;
	}

	csr->version = css_header->version;

	if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
	    csr->version < SKL_CSR_VERSION_REQUIRED) {
		DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
			 " please upgrade to v%u.%u or later"
			   " [" FIRMWARE_URL "].\n",
			 CSR_VERSION_MAJOR(csr->version),
			 CSR_VERSION_MINOR(csr->version),
			 CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
			 CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
		return NULL;
	}

	readcount += sizeof(struct intel_css_header);

	/* Extract Package Header information*/
	package_header = (struct intel_package_header *)
		&fw->data[readcount];
	if (sizeof(struct intel_package_header) !=
	    (package_header->header_len * 4)) {
		DRM_ERROR("Firmware has wrong package header length %u bytes\n",
			  (package_header->header_len * 4));
		return NULL;
	}
	readcount += sizeof(struct intel_package_header);

	/* Search for dmc_offset to find firware binary. */
	for (i = 0; i < package_header->num_entries; i++) {
		if (package_header->fw_info[i].substepping == '*' &&
		    stepping == package_header->fw_info[i].stepping) {
			dmc_offset = package_header->fw_info[i].offset;
			break;
		} else if (stepping == package_header->fw_info[i].stepping &&
			substepping == package_header->fw_info[i].substepping) {
			dmc_offset = package_header->fw_info[i].offset;
			break;
		} else if (package_header->fw_info[i].stepping == '*' &&
			   package_header->fw_info[i].substepping == '*')
			dmc_offset = package_header->fw_info[i].offset;
	}
	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
		DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
		return NULL;
	}
	readcount += dmc_offset;

	/* Extract dmc_header information. */
	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
		DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
			  (dmc_header->header_len));
		return NULL;
	}
	readcount += sizeof(struct intel_dmc_header);

	/* Cache the dmc header info. */
	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
		DRM_ERROR("Firmware has wrong mmio count %u\n",
			  dmc_header->mmio_count);
		return NULL;
	}
	csr->mmio_count = dmc_header->mmio_count;
	for (i = 0; i < dmc_header->mmio_count; i++) {
		if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
		    dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
			DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
				  dmc_header->mmioaddr[i]);
			return NULL;
		}
		csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
		csr->mmiodata[i] = dmc_header->mmiodata[i];
	}

	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
	nbytes = dmc_header->fw_size * 4;
	if (nbytes > CSR_MAX_FW_SIZE) {
		DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
		return NULL;
	}
	csr->dmc_fw_size = dmc_header->fw_size;

	dmc_payload = kmalloc(nbytes, GFP_KERNEL);
	if (!dmc_payload) {
		DRM_ERROR("Memory allocation failed for dmc payload\n");
		return NULL;
	}

	memcpy(dmc_payload, &fw->data[readcount], nbytes);

	return dmc_payload;
}

static void csr_load_work_fn(struct work_struct *work)
{
	struct drm_i915_private *dev_priv;
	struct intel_csr *csr;
	const struct firmware *fw;
	int ret;

	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
	csr = &dev_priv->csr;

	ret = request_firmware(&fw, dev_priv->csr.fw_path,
			       &dev_priv->dev->pdev->dev);
	if (!fw)
		goto out;

	dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
	if (!dev_priv->csr.dmc_payload)
		goto out;

	/* load csr program during system boot, as needed for DC states */
	intel_csr_load_program(dev_priv);

out:
	if (dev_priv->csr.dmc_payload) {
		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);

		DRM_INFO("Finished loading %s (v%u.%u)\n",
			 dev_priv->csr.fw_path,
			 CSR_VERSION_MAJOR(csr->version),
			 CSR_VERSION_MINOR(csr->version));
	} else {
		dev_notice(dev_priv->dev->dev,
			   "Failed to load DMC firmware"
			   " [" FIRMWARE_URL "],"
			   " disabling runtime power management.\n");
	}

	release_firmware(fw);
}

/**
 * intel_csr_ucode_init() - initialize the firmware loading.
 * @dev_priv: i915 drm device.
 *
 * This function is called at the time of loading the display driver to read
 * firmware from a .bin file and copied into a internal memory.
 */
void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
{
	struct intel_csr *csr = &dev_priv->csr;

	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);

	if (!HAS_CSR(dev_priv))
		return;

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
		csr->fw_path = I915_CSR_SKL;
	else if (IS_BROXTON(dev_priv))
		csr->fw_path = I915_CSR_BXT;
	else {
		DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
		return;
	}

	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);

	/*
	 * Obtain a runtime pm reference, until CSR is loaded,
	 * to avoid entering runtime-suspend.
	 */
	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

	schedule_work(&dev_priv->csr.work);
}

/**
 * intel_csr_ucode_fini() - unload the CSR firmware.
 * @dev_priv: i915 drm device.
 *
 * Firmmware unloading includes freeing the internal momory and reset the
 * firmware loading status.
 */
void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
{
	if (!HAS_CSR(dev_priv))
		return;

	flush_work(&dev_priv->csr.work);

	kfree(dev_priv->csr.dmc_payload);
}
Commit	Line	Data
eb805623 DV	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24	#include <linux/firmware.h>
	25	#include "i915_drv.h"
	26	#include "i915_reg.h"
	27
aa9145c4 AM	28	/**
	29	* DOC: csr support for dmc
	30	*
	31	* Display Context Save and Restore (CSR) firmware support added from gen9
	32	* onwards to drive newly added DMC (Display microcontroller) in display
	33	* engine to save and restore the state of display engine when it enter into
	34	* low-power state and comes back to normal.
	35	*
	36	* Firmware loading status will be one of the below states: FW_UNINITIALIZED,
	37	* FW_LOADED, FW_FAILED.
	38	*
	39	* Once the firmware is written into the registers status will be moved from
	40	* FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
	41	* be moved to FW_FAILED.
	42	*/
	43
bf546f81	44	#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
18c237c0	45	#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
eb805623	46
cbfc2d26 CW	47	#define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
cbfc2d26 CW	48
eb805623	49	MODULE_FIRMWARE(I915_CSR_SKL);
18c237c0	50	MODULE_FIRMWARE(I915_CSR_BXT);
eb805623	51
9c5308ea MK	52	#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
9c5308ea MK	53
eb805623 DV	54	#define CSR_MAX_FW_SIZE 0x2FFF
eb805623 DV	55	#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
eb805623 DV	56
	57	struct intel_css_header {
	58	/* 0x09 for DMC */
	59	uint32_t module_type;
	60
	61	/* Includes the DMC specific header in dwords */
	62	uint32_t header_len;
	63
	64	/* always value would be 0x10000 */
	65	uint32_t header_ver;
	66
	67	/* Not used */
	68	uint32_t module_id;
	69
	70	/* Not used */
	71	uint32_t module_vendor;
	72
	73	/* in YYYYMMDD format */
	74	uint32_t date;
	75
	76	/* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
	77	uint32_t size;
	78
	79	/* Not used */
	80	uint32_t key_size;
	81
	82	/* Not used */
	83	uint32_t modulus_size;
	84
	85	/* Not used */
	86	uint32_t exponent_size;
	87
	88	/* Not used */
	89	uint32_t reserved1[12];
	90
	91	/* Major Minor */
	92	uint32_t version;
	93
	94	/* Not used */
	95	uint32_t reserved2[8];
	96
	97	/* Not used */
	98	uint32_t kernel_header_info;
	99	} __packed;
	100
	101	struct intel_fw_info {
	102	uint16_t reserved1;
	103
	104	/* Stepping (A, B, C, ..., ). is a wildcard */
	105	char stepping;
	106
	107	/* Sub-stepping (0, 1, ..., ). is a wildcard */
	108	char substepping;
	109
	110	uint32_t offset;
	111	uint32_t reserved2;
	112	} __packed;
	113
	114	struct intel_package_header {
	115	/* DMC container header length in dwords */
	116	unsigned char header_len;
	117
	118	/* always value would be 0x01 */
	119	unsigned char header_ver;
120
121	unsigned char reserved[10];
122
123	/* Number of valid entries in the FWInfo array below */
124	uint32_t num_entries;
125
126	struct intel_fw_info fw_info[20];
127	} __packed;
128
129	struct intel_dmc_header {
130	/* always value would be 0x40403E3E */
131	uint32_t signature;
132
133	/* DMC binary header length */
134	unsigned char header_len;
135
136	/* 0x01 */
137	unsigned char header_ver;
138
139	/* Reserved */
140	uint16_t dmcc_ver;
141
142	/* Major, Minor */
143	uint32_t project;
144
145	/* Firmware program size (excluding header) in dwords */
146	uint32_t fw_size;
147
148	/* Major Minor version */
149	uint32_t fw_version;
150
151	/* Number of valid MMIO cycles present. */
152	uint32_t mmio_count;
153
154	/* MMIO address */
155	uint32_t mmioaddr[8];
156
157	/* MMIO data */
158	uint32_t mmiodata[8];
159
160	/* FW filename */
161	unsigned char dfile[32];
162
163	uint32_t reserved1[2];
164	} __packed;
165
166	struct stepping_info {
167	char stepping;
168	char substepping;
169	};
170
a25c9f00 RV	171	/*
	172	* Kabylake derivated from Skylake H0, so SKL H0
	173	* is the right firmware for KBL A0 (revid 0).
	174	*/
	175	static const struct stepping_info kbl_stepping_info[] = {
	176	{'H', '0'}, {'I', '0'}
	177	};
	178
eb805623	179	static const struct stepping_info skl_stepping_info[] = {
84cb00ec JN	180	{'A', '0'}, {'B', '0'}, {'C', '0'},
84cb00ec JN	181	{'D', '0'}, {'E', '0'}, {'F', '0'},
a41c8882 MM	182	{'G', '0'}, {'H', '0'}, {'I', '0'},
a41c8882 MM	183	{'J', '0'}, {'K', '0'}
eb805623 DV	184	};
eb805623 DV	185
b9cd5bfd	186	static const struct stepping_info bxt_stepping_info[] = {
cff765fb AM	187	{'A', '0'}, {'A', '1'}, {'A', '2'},
	188	{'B', '0'}, {'B', '1'}, {'B', '2'}
	189	};
	190
b1a14c6e	191	static const struct stepping_info intel_get_stepping_info(struct drm_device dev)
eb805623	192	{
b1a14c6e JN	193	const struct stepping_info *si;
	194	unsigned int size;
	195
a25c9f00 RV	196	if (IS_KABYLAKE(dev)) {
	197	size = ARRAY_SIZE(kbl_stepping_info);
	198	si = kbl_stepping_info;
	199	} else if (IS_SKYLAKE(dev)) {
b1a14c6e JN	200	size = ARRAY_SIZE(skl_stepping_info);
	201	si = skl_stepping_info;
	202	} else if (IS_BROXTON(dev)) {
	203	size = ARRAY_SIZE(bxt_stepping_info);
	204	si = bxt_stepping_info;
	205	} else {
	206	return NULL;
	207	}
eb805623	208
b1a14c6e JN	209	if (INTEL_REVID(dev) < size)
	210	return si + INTEL_REVID(dev);
	211
	212	return NULL;
eb805623 DV	213	}
eb805623 DV	214
aa9145c4 AM	215	/**
aa9145c4 AM	216	* intel_csr_load_program() - write the firmware from memory to register.
f4448375	217	* @dev_priv: i915 drm device.
aa9145c4 AM	218	*
	219	* CSR firmware is read from a .bin file and kept in internal memory one time.
	220	* Everytime display comes back from low power state this function is called to
	221	* copy the firmware from internal memory to registers.
	222	*/
1e657ad7	223	bool intel_csr_load_program(struct drm_i915_private *dev_priv)
eb805623	224	{
a7f749f9	225	u32 *payload = dev_priv->csr.dmc_payload;
eb805623 DV	226	uint32_t i, fw_size;
eb805623 DV	227
f4448375	228	if (!IS_GEN9(dev_priv)) {
eb805623	229	DRM_ERROR("No CSR support available for this platform\n");
1e657ad7	230	return false;
eb805623 DV	231	}
eb805623 DV	232
fc131bf2 PJ	233	if (!dev_priv->csr.dmc_payload) {
fc131bf2 PJ	234	DRM_ERROR("Tried to program CSR with empty payload\n");
1e657ad7	235	return false;
fc131bf2	236	}
4b7ab5fc	237
eb805623 DV	238	fw_size = dev_priv->csr.dmc_fw_size;
eb805623 DV	239	for (i = 0; i < fw_size; i++)
d2aa5ae8	240	I915_WRITE(CSR_PROGRAM(i), payload[i]);
eb805623 DV	241
	242	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
	243	I915_WRITE(dev_priv->csr.mmioaddr[i],
f98f70d9	244	dev_priv->csr.mmiodata[i]);
eb805623	245	}
832dba88 PJ	246
832dba88 PJ	247	dev_priv->csr.dc_state = 0;
1e657ad7 MK	248
1e657ad7 MK	249	return true;
eb805623 DV	250	}
eb805623 DV	251
6a6582bf DV	252	static uint32_t parse_csr_fw(struct drm_i915_private dev_priv,
6a6582bf DV	253	const struct firmware *fw)
eb805623	254	{
eb805623 DV	255	struct drm_device *dev = dev_priv->dev;
	256	struct intel_css_header *css_header;
	257	struct intel_package_header *package_header;
	258	struct intel_dmc_header *dmc_header;
	259	struct intel_csr *csr = &dev_priv->csr;
b1a14c6e JN	260	const struct stepping_info *stepping_info = intel_get_stepping_info(dev);
b1a14c6e JN	261	char stepping, substepping;
eb805623 DV	262	uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
eb805623 DV	263	uint32_t i;
a7f749f9	264	uint32_t *dmc_payload;
eb805623	265
9c5308ea	266	if (!fw)
6a6582bf	267	return NULL;
eb805623	268
b1a14c6e	269	if (!stepping_info) {
eb805623	270	DRM_ERROR("Unknown stepping info, firmware loading failed\n");
6a6582bf	271	return NULL;
eb805623 DV	272	}
eb805623 DV	273
b1a14c6e JN	274	stepping = stepping_info->stepping;
	275	substepping = stepping_info->substepping;
	276
eb805623 DV	277	/* Extract CSS Header information*/
	278	css_header = (struct intel_css_header *)fw->data;
	279	if (sizeof(struct intel_css_header) !=
f98f70d9	280	(css_header->header_len * 4)) {
eb805623	281	DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
f98f70d9	282	(css_header->header_len * 4));
6a6582bf	283	return NULL;
eb805623	284	}
b6e7d894 DL	285
	286	csr->version = css_header->version;
	287
8d7a1c4a RV	288	if ((IS_SKYLAKE(dev) \|\| IS_KABYLAKE(dev)) &&
8d7a1c4a RV	289	csr->version < SKL_CSR_VERSION_REQUIRED) {
9c5308ea MK	290	DRM_INFO("Refusing to load old Skylake DMC firmware v%u.%u,"
9c5308ea MK	291	" please upgrade to v%u.%u or later"
cbfc2d26	292	" [" FIRMWARE_URL "].\n",
9c5308ea MK	293	CSR_VERSION_MAJOR(csr->version),
	294	CSR_VERSION_MINOR(csr->version),
	295	CSR_VERSION_MAJOR(SKL_CSR_VERSION_REQUIRED),
	296	CSR_VERSION_MINOR(SKL_CSR_VERSION_REQUIRED));
6a6582bf	297	return NULL;
9c5308ea MK	298	}
9c5308ea MK	299
eb805623 DV	300	readcount += sizeof(struct intel_css_header);
	301
	302	/* Extract Package Header information*/
	303	package_header = (struct intel_package_header *)
f98f70d9	304	&fw->data[readcount];
eb805623	305	if (sizeof(struct intel_package_header) !=
f98f70d9	306	(package_header->header_len * 4)) {
eb805623	307	DRM_ERROR("Firmware has wrong package header length %u bytes\n",
f98f70d9	308	(package_header->header_len * 4));
6a6582bf	309	return NULL;
eb805623 DV	310	}
	311	readcount += sizeof(struct intel_package_header);
	312
	313	/* Search for dmc_offset to find firware binary. */
	314	for (i = 0; i < package_header->num_entries; i++) {
	315	if (package_header->fw_info[i].substepping == '*' &&
f98f70d9	316	stepping == package_header->fw_info[i].stepping) {
eb805623 DV	317	dmc_offset = package_header->fw_info[i].offset;
	318	break;
	319	} else if (stepping == package_header->fw_info[i].stepping &&
	320	substepping == package_header->fw_info[i].substepping) {
	321	dmc_offset = package_header->fw_info[i].offset;
	322	break;
	323	} else if (package_header->fw_info[i].stepping == '*' &&
f98f70d9	324	package_header->fw_info[i].substepping == '*')
eb805623 DV	325	dmc_offset = package_header->fw_info[i].offset;
	326	}
	327	if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
	328	DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
6a6582bf	329	return NULL;
eb805623 DV	330	}
	331	readcount += dmc_offset;
	332
	333	/* Extract dmc_header information. */
	334	dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
	335	if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
	336	DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
f98f70d9	337	(dmc_header->header_len));
6a6582bf	338	return NULL;
eb805623 DV	339	}
	340	readcount += sizeof(struct intel_dmc_header);
	341
	342	/* Cache the dmc header info. */
	343	if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
	344	DRM_ERROR("Firmware has wrong mmio count %u\n",
f98f70d9	345	dmc_header->mmio_count);
6a6582bf	346	return NULL;
eb805623 DV	347	}
	348	csr->mmio_count = dmc_header->mmio_count;
	349	for (i = 0; i < dmc_header->mmio_count; i++) {
982b0b2d	350	if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE \|\|
f98f70d9	351	dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
eb805623	352	DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
f98f70d9	353	dmc_header->mmioaddr[i]);
6a6582bf	354	return NULL;
eb805623	355	}
f0f59a00	356	csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
eb805623 DV	357	csr->mmiodata[i] = dmc_header->mmiodata[i];
	358	}
	359
	360	/* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
	361	nbytes = dmc_header->fw_size * 4;
	362	if (nbytes > CSR_MAX_FW_SIZE) {
	363	DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
6a6582bf	364	return NULL;
eb805623 DV	365	}
	366	csr->dmc_fw_size = dmc_header->fw_size;
	367
6a6582bf DV	368	dmc_payload = kmalloc(nbytes, GFP_KERNEL);
6a6582bf DV	369	if (!dmc_payload) {
eb805623	370	DRM_ERROR("Memory allocation failed for dmc payload\n");
6a6582bf	371	return NULL;
eb805623 DV	372	}
eb805623 DV	373
a7f749f9	374	memcpy(dmc_payload, &fw->data[readcount], nbytes);
eb805623	375
6a6582bf DV	376	return dmc_payload;
	377	}
	378
8144ac59	379	static void csr_load_work_fn(struct work_struct *work)
6a6582bf	380	{
8144ac59 DV	381	struct drm_i915_private *dev_priv;
	382	struct intel_csr *csr;
	383	const struct firmware *fw;
	384	int ret;
	385
	386	dev_priv = container_of(work, typeof(*dev_priv), csr.work);
	387	csr = &dev_priv->csr;
6a6582bf	388
8144ac59 DV	389	ret = request_firmware(&fw, dev_priv->csr.fw_path,
8144ac59 DV	390	&dev_priv->dev->pdev->dev);
6a6582bf DV	391	if (!fw)
	392	goto out;
	393
	394	dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
	395	if (!dev_priv->csr.dmc_payload)
	396	goto out;
	397
eb805623	398	/* load csr program during system boot, as needed for DC states */
f4448375	399	intel_csr_load_program(dev_priv);
dc174300	400
eb805623	401	out:
6a6582bf	402	if (dev_priv->csr.dmc_payload) {
01a6908c	403	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
9c5308ea MK	404
	405	DRM_INFO("Finished loading %s (v%u.%u)\n",
	406	dev_priv->csr.fw_path,
	407	CSR_VERSION_MAJOR(csr->version),
	408	CSR_VERSION_MINOR(csr->version));
	409	} else {
cbfc2d26 CW	410	dev_notice(dev_priv->dev->dev,
	411	"Failed to load DMC firmware"
	412	" [" FIRMWARE_URL "],"
	413	" disabling runtime power management.\n");
9c5308ea MK	414	}
9c5308ea MK	415
eb805623 DV	416	release_firmware(fw);
	417	}
	418
aa9145c4 AM	419	/**
aa9145c4 AM	420	* intel_csr_ucode_init() - initialize the firmware loading.
f4448375	421	* @dev_priv: i915 drm device.
aa9145c4 AM	422	*
	423	* This function is called at the time of loading the display driver to read
	424	* firmware from a .bin file and copied into a internal memory.
	425	*/
f4448375	426	void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
eb805623	427	{
eb805623	428	struct intel_csr *csr = &dev_priv->csr;
8144ac59 DV	429
8144ac59 DV	430	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
eb805623	431
f4448375	432	if (!HAS_CSR(dev_priv))
eb805623 DV	433	return;
eb805623 DV	434
8d7a1c4a	435	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv))
eb805623	436	csr->fw_path = I915_CSR_SKL;
18c237c0 AM	437	else if (IS_BROXTON(dev_priv))
18c237c0 AM	438	csr->fw_path = I915_CSR_BXT;
eb805623 DV	439	else {
	440	DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
	441	return;
	442	}
	443
abd41dc9 DL	444	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
abd41dc9 DL	445
dc174300 SS	446	/*
	447	* Obtain a runtime pm reference, until CSR is loaded,
	448	* to avoid entering runtime-suspend.
	449	*/
01a6908c	450	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
dc174300	451
8144ac59	452	schedule_work(&dev_priv->csr.work);
eb805623 DV	453	}
eb805623 DV	454
aa9145c4 AM	455	/**
aa9145c4 AM	456	* intel_csr_ucode_fini() - unload the CSR firmware.
f4448375	457	* @dev_priv: i915 drm device.
aa9145c4 AM	458	*
	459	* Firmmware unloading includes freeing the internal momory and reset the
	460	* firmware loading status.
	461	*/
f4448375	462	void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
eb805623	463	{
f4448375	464	if (!HAS_CSR(dev_priv))
eb805623 DV	465	return;
eb805623 DV	466
15e72c1f AM	467	flush_work(&dev_priv->csr.work);
15e72c1f AM	468
eb805623 DV	469	kfree(dev_priv->csr.dmc_payload);
eb805623 DV	470	}