Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
d2ee2e8a | 30 | |
c6f95f27 | 31 | #include <drm/drm_atomic_helper.h> |
760285e7 | 32 | #include <drm/drm_crtc.h> |
760285e7 | 33 | #include <drm/drm_edid.h> |
fcd70cd3 | 34 | #include <drm/drm_probe_helper.h> |
760285e7 | 35 | #include <drm/i915_drm.h> |
d2ee2e8a | 36 | |
79e53945 | 37 | #include "i915_drv.h" |
d2ee2e8a | 38 | #include "intel_crt.h" |
fdc24cf3 | 39 | #include "intel_ddi.h" |
d2ee2e8a | 40 | #include "intel_drv.h" |
79e53945 | 41 | |
e7dbb2f2 KP |
42 | /* Here's the desired hotplug mode */ |
43 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
44 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
45 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
46 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
47 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
48 | ADPA_CRT_HOTPLUG_ENABLE) | |
49 | ||
c9a1c4cd CW |
50 | struct intel_crt { |
51 | struct intel_encoder base; | |
637f44d2 AJ |
52 | /* DPMS state is stored in the connector, which we need in the |
53 | * encoder's enable/disable callbacks */ | |
54 | struct intel_connector *connector; | |
e7dbb2f2 | 55 | bool force_hotplug_required; |
f0f59a00 | 56 | i915_reg_t adpa_reg; |
c9a1c4cd CW |
57 | }; |
58 | ||
eebe6f0b | 59 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 60 | { |
eebe6f0b | 61 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
62 | } |
63 | ||
eebe6f0b | 64 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 65 | { |
eebe6f0b | 66 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
67 | } |
68 | ||
6102a8ee VS |
69 | bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, |
70 | i915_reg_t adpa_reg, enum pipe *pipe) | |
71 | { | |
72 | u32 val; | |
73 | ||
74 | val = I915_READ(adpa_reg); | |
75 | ||
76 | /* asserts want to know the pipe even if the port is disabled */ | |
77 | if (HAS_PCH_CPT(dev_priv)) | |
78 | *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; | |
79 | else | |
80 | *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; | |
81 | ||
82 | return val & ADPA_DAC_ENABLE; | |
83 | } | |
84 | ||
e403fc94 DV |
85 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
86 | enum pipe *pipe) | |
79e53945 | 87 | { |
6102a8ee | 88 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e403fc94 | 89 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
0e6e0be4 | 90 | intel_wakeref_t wakeref; |
1c8fdda1 | 91 | bool ret; |
e403fc94 | 92 | |
0e6e0be4 CW |
93 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
94 | encoder->power_domain); | |
95 | if (!wakeref) | |
6d129bea ID |
96 | return false; |
97 | ||
6102a8ee | 98 | ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); |
e403fc94 | 99 | |
0e6e0be4 | 100 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
1c8fdda1 ID |
101 | |
102 | return ret; | |
e403fc94 DV |
103 | } |
104 | ||
6801c18c | 105 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 | 106 | { |
fac5e23e | 107 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 JB |
108 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
109 | u32 tmp, flags = 0; | |
110 | ||
111 | tmp = I915_READ(crt->adpa_reg); | |
112 | ||
113 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
114 | flags |= DRM_MODE_FLAG_PHSYNC; | |
115 | else | |
116 | flags |= DRM_MODE_FLAG_NHSYNC; | |
117 | ||
118 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
119 | flags |= DRM_MODE_FLAG_PVSYNC; | |
120 | else | |
121 | flags |= DRM_MODE_FLAG_NVSYNC; | |
122 | ||
6801c18c VS |
123 | return flags; |
124 | } | |
125 | ||
126 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 127 | struct intel_crtc_state *pipe_config) |
6801c18c | 128 | { |
e1214b95 VS |
129 | pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); |
130 | ||
2d112de7 | 131 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 | 132 | |
e3b247da | 133 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
134 | } |
135 | ||
6801c18c | 136 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 137 | struct intel_crtc_state *pipe_config) |
6801c18c | 138 | { |
8802e5b6 VS |
139 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
140 | ||
6801c18c VS |
141 | intel_ddi_get_config(encoder, pipe_config); |
142 | ||
2d112de7 | 143 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
144 | DRM_MODE_FLAG_NHSYNC | |
145 | DRM_MODE_FLAG_PVSYNC | | |
146 | DRM_MODE_FLAG_NVSYNC); | |
2d112de7 | 147 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
8802e5b6 VS |
148 | |
149 | pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); | |
6801c18c VS |
150 | } |
151 | ||
b2cabb0e DV |
152 | /* Note: The caller is required to filter out dpms modes not supported by the |
153 | * platform. */ | |
225cc348 | 154 | static void intel_crt_set_dpms(struct intel_encoder *encoder, |
5f88a9c6 | 155 | const struct intel_crtc_state *crtc_state, |
225cc348 | 156 | int mode) |
df0323c4 | 157 | { |
66478475 | 158 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b2cabb0e | 159 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
225cc348 ML |
160 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
161 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; | |
894ed1ec DV |
162 | u32 adpa; |
163 | ||
66478475 | 164 | if (INTEL_GEN(dev_priv) >= 5) |
894ed1ec DV |
165 | adpa = ADPA_HOTPLUG_BITS; |
166 | else | |
167 | adpa = 0; | |
df0323c4 | 168 | |
894ed1ec DV |
169 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
170 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
171 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
172 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
173 | ||
174 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
6e266956 | 175 | if (HAS_PCH_LPT(dev_priv)) |
894ed1ec | 176 | ; /* Those bits don't exist here */ |
6e266956 | 177 | else if (HAS_PCH_CPT(dev_priv)) |
6102a8ee | 178 | adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); |
894ed1ec | 179 | else |
6102a8ee | 180 | adpa |= ADPA_PIPE_SEL(crtc->pipe); |
894ed1ec | 181 | |
6e266956 | 182 | if (!HAS_PCH_SPLIT(dev_priv)) |
894ed1ec | 183 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
79e53945 | 184 | |
0206e353 | 185 | switch (mode) { |
79e53945 | 186 | case DRM_MODE_DPMS_ON: |
894ed1ec | 187 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
188 | break; |
189 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 190 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
191 | break; |
192 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 193 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
194 | break; |
195 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 196 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
197 | break; |
198 | } | |
199 | ||
894ed1ec | 200 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 201 | } |
2c07245f | 202 | |
fd6bbda9 | 203 | static void intel_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
204 | const struct intel_crtc_state *old_crtc_state, |
205 | const struct drm_connector_state *old_conn_state) | |
637f44d2 | 206 | { |
225cc348 | 207 | intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); |
637f44d2 AJ |
208 | } |
209 | ||
fd6bbda9 | 210 | static void pch_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
211 | const struct intel_crtc_state *old_crtc_state, |
212 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 VS |
213 | { |
214 | } | |
215 | ||
fd6bbda9 | 216 | static void pch_post_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
217 | const struct intel_crtc_state *old_crtc_state, |
218 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 | 219 | { |
fd6bbda9 | 220 | intel_disable_crt(encoder, old_crtc_state, old_conn_state); |
1ea56e26 | 221 | } |
abfdc1e3 | 222 | |
3daa3cee JN |
223 | static void hsw_disable_crt(struct intel_encoder *encoder, |
224 | const struct intel_crtc_state *old_crtc_state, | |
225 | const struct drm_connector_state *old_conn_state) | |
226 | { | |
c249f1f4 | 227 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3daa3cee | 228 | |
c249f1f4 | 229 | WARN_ON(!old_crtc_state->has_pch_encoder); |
3daa3cee JN |
230 | |
231 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
232 | } | |
233 | ||
b7076546 | 234 | static void hsw_post_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
235 | const struct intel_crtc_state *old_crtc_state, |
236 | const struct drm_connector_state *old_conn_state) | |
b7076546 ML |
237 | { |
238 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
239 | ||
afb2c443 ID |
240 | intel_ddi_disable_pipe_clock(old_crtc_state); |
241 | ||
b7076546 ML |
242 | pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); |
243 | ||
244 | lpt_disable_pch_transcoder(dev_priv); | |
245 | lpt_disable_iclkip(dev_priv); | |
246 | ||
247 | intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); | |
3daa3cee JN |
248 | |
249 | WARN_ON(!old_crtc_state->has_pch_encoder); | |
250 | ||
251 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
b7076546 ML |
252 | } |
253 | ||
51c4fa69 | 254 | static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder, |
c249f1f4 | 255 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
256 | const struct drm_connector_state *conn_state) |
257 | { | |
c249f1f4 | 258 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
51c4fa69 | 259 | |
c249f1f4 | 260 | WARN_ON(!crtc_state->has_pch_encoder); |
51c4fa69 JN |
261 | |
262 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
263 | } | |
264 | ||
265 | static void hsw_pre_enable_crt(struct intel_encoder *encoder, | |
c249f1f4 | 266 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
267 | const struct drm_connector_state *conn_state) |
268 | { | |
c249f1f4 VS |
269 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
270 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
271 | enum pipe pipe = crtc->pipe; | |
51c4fa69 | 272 | |
c249f1f4 | 273 | WARN_ON(!crtc_state->has_pch_encoder); |
51c4fa69 JN |
274 | |
275 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
27d81c28 | 276 | |
c249f1f4 | 277 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
afb2c443 ID |
278 | |
279 | intel_ddi_enable_pipe_clock(crtc_state); | |
51c4fa69 JN |
280 | } |
281 | ||
282 | static void hsw_enable_crt(struct intel_encoder *encoder, | |
c249f1f4 | 283 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
284 | const struct drm_connector_state *conn_state) |
285 | { | |
c249f1f4 VS |
286 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
287 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
288 | enum pipe pipe = crtc->pipe; | |
51c4fa69 | 289 | |
c249f1f4 | 290 | WARN_ON(!crtc_state->has_pch_encoder); |
51c4fa69 | 291 | |
c249f1f4 | 292 | intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); |
51c4fa69 JN |
293 | |
294 | intel_wait_for_vblank(dev_priv, pipe); | |
295 | intel_wait_for_vblank(dev_priv, pipe); | |
296 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
297 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
298 | } | |
299 | ||
fd6bbda9 | 300 | static void intel_enable_crt(struct intel_encoder *encoder, |
c249f1f4 | 301 | const struct intel_crtc_state *crtc_state, |
5f88a9c6 | 302 | const struct drm_connector_state *conn_state) |
637f44d2 | 303 | { |
c249f1f4 | 304 | intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); |
637f44d2 AJ |
305 | } |
306 | ||
c19de8eb DL |
307 | static enum drm_mode_status |
308 | intel_crt_mode_valid(struct drm_connector *connector, | |
309 | struct drm_display_mode *mode) | |
79e53945 | 310 | { |
6bcdcd9e | 311 | struct drm_device *dev = connector->dev; |
6e266956 TU |
312 | struct drm_i915_private *dev_priv = to_i915(dev); |
313 | int max_dotclk = dev_priv->max_dotclk_freq; | |
debded84 | 314 | int max_clock; |
6bcdcd9e | 315 | |
e4dd27aa VS |
316 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
317 | return MODE_NO_DBLESCAN; | |
318 | ||
6bcdcd9e ZY |
319 | if (mode->clock < 25000) |
320 | return MODE_CLOCK_LOW; | |
321 | ||
6e266956 | 322 | if (HAS_PCH_LPT(dev_priv)) |
debded84 | 323 | max_clock = 180000; |
11a914c2 | 324 | else if (IS_VALLEYVIEW(dev_priv)) |
debded84 VS |
325 | /* |
326 | * 270 MHz due to current DPLL limits, | |
327 | * DAC limit supposedly 355 MHz. | |
328 | */ | |
329 | max_clock = 270000; | |
f3ce44a0 | 330 | else if (IS_GEN_RANGE(dev_priv, 3, 4)) |
6bcdcd9e | 331 | max_clock = 400000; |
debded84 VS |
332 | else |
333 | max_clock = 350000; | |
6bcdcd9e ZY |
334 | if (mode->clock > max_clock) |
335 | return MODE_CLOCK_HIGH; | |
79e53945 | 336 | |
f8700b34 MK |
337 | if (mode->clock > max_dotclk) |
338 | return MODE_CLOCK_HIGH; | |
339 | ||
d4b1931c | 340 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
6e266956 | 341 | if (HAS_PCH_LPT(dev_priv) && |
d4b1931c PZ |
342 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
343 | return MODE_CLOCK_HIGH; | |
344 | ||
ad193bc6 VS |
345 | /* HSW/BDW FDI limited to 4k */ |
346 | if (mode->hdisplay > 4096) | |
347 | return MODE_H_ILLEGAL; | |
348 | ||
79e53945 JB |
349 | return MODE_OK; |
350 | } | |
351 | ||
204474a6 LP |
352 | static int intel_crt_compute_config(struct intel_encoder *encoder, |
353 | struct intel_crtc_state *pipe_config, | |
354 | struct drm_connector_state *conn_state) | |
2f26cdc0 | 355 | { |
e4dd27aa VS |
356 | struct drm_display_mode *adjusted_mode = |
357 | &pipe_config->base.adjusted_mode; | |
358 | ||
359 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 360 | return -EINVAL; |
e4dd27aa | 361 | |
d9facae6 | 362 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
204474a6 LP |
363 | |
364 | return 0; | |
2f26cdc0 JN |
365 | } |
366 | ||
204474a6 LP |
367 | static int pch_crt_compute_config(struct intel_encoder *encoder, |
368 | struct intel_crtc_state *pipe_config, | |
369 | struct drm_connector_state *conn_state) | |
2f26cdc0 | 370 | { |
e4dd27aa VS |
371 | struct drm_display_mode *adjusted_mode = |
372 | &pipe_config->base.adjusted_mode; | |
373 | ||
374 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 375 | return -EINVAL; |
e4dd27aa | 376 | |
2f26cdc0 | 377 | pipe_config->has_pch_encoder = true; |
d9facae6 | 378 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
2f26cdc0 | 379 | |
204474a6 | 380 | return 0; |
2f26cdc0 JN |
381 | } |
382 | ||
204474a6 LP |
383 | static int hsw_crt_compute_config(struct intel_encoder *encoder, |
384 | struct intel_crtc_state *pipe_config, | |
385 | struct drm_connector_state *conn_state) | |
79e53945 | 386 | { |
4f8036a2 | 387 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e4dd27aa VS |
388 | struct drm_display_mode *adjusted_mode = |
389 | &pipe_config->base.adjusted_mode; | |
390 | ||
391 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 392 | return -EINVAL; |
5bfe2ac0 | 393 | |
ad193bc6 VS |
394 | /* HSW/BDW FDI limited to 4k */ |
395 | if (adjusted_mode->crtc_hdisplay > 4096 || | |
396 | adjusted_mode->crtc_hblank_start > 4096) | |
204474a6 | 397 | return -EINVAL; |
ad193bc6 | 398 | |
2f26cdc0 | 399 | pipe_config->has_pch_encoder = true; |
d9facae6 | 400 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
5bfe2ac0 | 401 | |
2a7aceec | 402 | /* LPT FDI RX only supports 8bpc. */ |
4f8036a2 | 403 | if (HAS_PCH_LPT(dev_priv)) { |
f58a1acc DV |
404 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { |
405 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); | |
204474a6 | 406 | return -EINVAL; |
f58a1acc DV |
407 | } |
408 | ||
2a7aceec | 409 | pipe_config->pipe_bpp = 24; |
f58a1acc | 410 | } |
2a7aceec | 411 | |
8f7abfd8 | 412 | /* FDI must always be 2.7 GHz */ |
2f26cdc0 | 413 | pipe_config->port_clock = 135000 * 2; |
00490c22 | 414 | |
204474a6 | 415 | return 0; |
79e53945 JB |
416 | } |
417 | ||
f2b115e6 | 418 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
419 | { |
420 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 421 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 422 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7dbb2f2 | 423 | u32 adpa; |
2c07245f ZW |
424 | bool ret; |
425 | ||
e7dbb2f2 KP |
426 | /* The first time through, trigger an explicit detection cycle */ |
427 | if (crt->force_hotplug_required) { | |
6e266956 | 428 | bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); |
e7dbb2f2 | 429 | u32 save_adpa; |
67941da2 | 430 | |
e7dbb2f2 KP |
431 | crt->force_hotplug_required = 0; |
432 | ||
ca54b810 | 433 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
434 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
435 | ||
436 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
437 | if (turn_off_dac) | |
438 | adpa &= ~ADPA_DAC_ENABLE; | |
439 | ||
ca54b810 | 440 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 441 | |
97a04e0d | 442 | if (intel_wait_for_register(&dev_priv->uncore, |
e1672d1c CW |
443 | crt->adpa_reg, |
444 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, | |
445 | 1000)) | |
e7dbb2f2 KP |
446 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
447 | ||
448 | if (turn_off_dac) { | |
ca54b810 VS |
449 | I915_WRITE(crt->adpa_reg, save_adpa); |
450 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 451 | } |
a4a6b901 ZW |
452 | } |
453 | ||
2c07245f | 454 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 455 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 456 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
457 | ret = true; |
458 | else | |
459 | ret = false; | |
e7dbb2f2 | 460 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 461 | |
2c07245f | 462 | return ret; |
79e53945 JB |
463 | } |
464 | ||
7d2c24e8 JB |
465 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
466 | { | |
467 | struct drm_device *dev = connector->dev; | |
ca54b810 | 468 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 469 | struct drm_i915_private *dev_priv = to_i915(dev); |
b236d7c8 | 470 | bool reenable_hpd; |
7d2c24e8 JB |
471 | u32 adpa; |
472 | bool ret; | |
473 | u32 save_adpa; | |
474 | ||
b236d7c8 L |
475 | /* |
476 | * Doing a force trigger causes a hpd interrupt to get sent, which can | |
477 | * get us stuck in a loop if we're polling: | |
478 | * - We enable power wells and reset the ADPA | |
479 | * - output_poll_exec does force probe on VGA, triggering a hpd | |
480 | * - HPD handler waits for poll to unlock dev->mode_config.mutex | |
481 | * - output_poll_exec shuts off the ADPA, unlocks | |
482 | * dev->mode_config.mutex | |
483 | * - HPD handler runs, resets ADPA and brings us back to the start | |
484 | * | |
485 | * Just disable HPD interrupts here to prevent this | |
486 | */ | |
487 | reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); | |
488 | ||
ca54b810 | 489 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
490 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
491 | ||
492 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
493 | ||
ca54b810 | 494 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 495 | |
97a04e0d | 496 | if (intel_wait_for_register(&dev_priv->uncore, |
a522ae4b CW |
497 | crt->adpa_reg, |
498 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, | |
499 | 1000)) { | |
7d2c24e8 | 500 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
ca54b810 | 501 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
502 | } |
503 | ||
504 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 505 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
506 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
507 | ret = true; | |
508 | else | |
509 | ret = false; | |
510 | ||
511 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
512 | ||
b236d7c8 L |
513 | if (reenable_hpd) |
514 | intel_hpd_enable(dev_priv, crt->base.hpd_pin); | |
515 | ||
7d2c24e8 JB |
516 | return ret; |
517 | } | |
518 | ||
79e53945 JB |
519 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
520 | { | |
521 | struct drm_device *dev = connector->dev; | |
fac5e23e | 522 | struct drm_i915_private *dev_priv = to_i915(dev); |
0706f17c | 523 | u32 stat; |
7a772c49 | 524 | bool ret = false; |
771cb081 | 525 | int i, tries = 0; |
2c07245f | 526 | |
6e266956 | 527 | if (HAS_PCH_SPLIT(dev_priv)) |
f2b115e6 | 528 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 529 | |
11a914c2 | 530 | if (IS_VALLEYVIEW(dev_priv)) |
7d2c24e8 JB |
531 | return valleyview_crt_detect_hotplug(connector); |
532 | ||
771cb081 ZY |
533 | /* |
534 | * On 4 series desktop, CRT detect sequence need to be done twice | |
535 | * to get a reliable result. | |
536 | */ | |
79e53945 | 537 | |
1c0f1b3d | 538 | if (IS_G45(dev_priv)) |
771cb081 ZY |
539 | tries = 2; |
540 | else | |
541 | tries = 1; | |
771cb081 | 542 | |
771cb081 | 543 | for (i = 0; i < tries ; i++) { |
771cb081 | 544 | /* turn on the FORCE_DETECT */ |
0706f17c EE |
545 | i915_hotplug_interrupt_update(dev_priv, |
546 | CRT_HOTPLUG_FORCE_DETECT, | |
547 | CRT_HOTPLUG_FORCE_DETECT); | |
771cb081 | 548 | /* wait for FORCE_DETECT to go off */ |
97a04e0d | 549 | if (intel_wait_for_register(&dev_priv->uncore, PORT_HOTPLUG_EN, |
fd3790d4 CW |
550 | CRT_HOTPLUG_FORCE_DETECT, 0, |
551 | 1000)) | |
79077319 | 552 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 553 | } |
79e53945 | 554 | |
7a772c49 AJ |
555 | stat = I915_READ(PORT_HOTPLUG_STAT); |
556 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
557 | ret = true; | |
558 | ||
559 | /* clear the interrupt we just generated, if any */ | |
560 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 561 | |
0706f17c | 562 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
7a772c49 AJ |
563 | |
564 | return ret; | |
79e53945 JB |
565 | } |
566 | ||
f1a2f5b7 JN |
567 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
568 | struct i2c_adapter *i2c) | |
569 | { | |
570 | struct edid *edid; | |
571 | ||
572 | edid = drm_get_edid(connector, i2c); | |
573 | ||
574 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
575 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
576 | intel_gmbus_force_bit(i2c, true); | |
577 | edid = drm_get_edid(connector, i2c); | |
578 | intel_gmbus_force_bit(i2c, false); | |
579 | } | |
580 | ||
581 | return edid; | |
582 | } | |
583 | ||
584 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
585 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
586 | struct i2c_adapter *adapter) | |
587 | { | |
588 | struct edid *edid; | |
ebda95a9 | 589 | int ret; |
f1a2f5b7 JN |
590 | |
591 | edid = intel_crt_get_edid(connector, adapter); | |
592 | if (!edid) | |
593 | return 0; | |
594 | ||
ebda95a9 JN |
595 | ret = intel_connector_update_modes(connector, edid); |
596 | kfree(edid); | |
597 | ||
598 | return ret; | |
f1a2f5b7 JN |
599 | } |
600 | ||
f5afcd3d | 601 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 602 | { |
f5afcd3d | 603 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 604 | struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); |
a2bd1f54 DV |
605 | struct edid *edid; |
606 | struct i2c_adapter *i2c; | |
c96b63a6 | 607 | bool ret = false; |
79e53945 | 608 | |
a2bd1f54 | 609 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 610 | |
41aa3448 | 611 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 612 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
613 | |
614 | if (edid) { | |
615 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 616 | |
f5afcd3d DM |
617 | /* |
618 | * This may be a DVI-I connector with a shared DDC | |
619 | * link between analog and digital outputs, so we | |
620 | * have to check the EDID input spec of the attached device. | |
621 | */ | |
f5afcd3d DM |
622 | if (!is_digital) { |
623 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
c96b63a6 ACO |
624 | ret = true; |
625 | } else { | |
626 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
f5afcd3d | 627 | } |
a2bd1f54 DV |
628 | } else { |
629 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
630 | } |
631 | ||
a2bd1f54 DV |
632 | kfree(edid); |
633 | ||
c96b63a6 | 634 | return ret; |
79e53945 JB |
635 | } |
636 | ||
e4a5d54f | 637 | static enum drm_connector_status |
c7cc5216 | 638 | intel_crt_load_detect(struct intel_crt *crt, u32 pipe) |
e4a5d54f | 639 | { |
7173188d | 640 | struct drm_device *dev = crt->base.base.dev; |
fac5e23e | 641 | struct drm_i915_private *dev_priv = to_i915(dev); |
c7cc5216 JN |
642 | u32 save_bclrpat; |
643 | u32 save_vtotal; | |
644 | u32 vtotal, vactive; | |
645 | u32 vsample; | |
646 | u32 vblank, vblank_start, vblank_end; | |
647 | u32 dsl; | |
f0f59a00 VS |
648 | i915_reg_t bclrpat_reg, vtotal_reg, |
649 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; | |
c7cc5216 | 650 | u8 st00; |
e4a5d54f ML |
651 | enum drm_connector_status status; |
652 | ||
6ec3d0c0 CW |
653 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
654 | ||
9db4a9c7 JB |
655 | bclrpat_reg = BCLRPAT(pipe); |
656 | vtotal_reg = VTOTAL(pipe); | |
657 | vblank_reg = VBLANK(pipe); | |
658 | vsync_reg = VSYNC(pipe); | |
659 | pipeconf_reg = PIPECONF(pipe); | |
660 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
661 | |
662 | save_bclrpat = I915_READ(bclrpat_reg); | |
663 | save_vtotal = I915_READ(vtotal_reg); | |
664 | vblank = I915_READ(vblank_reg); | |
665 | ||
666 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
667 | vactive = (save_vtotal & 0x7ff) + 1; | |
668 | ||
669 | vblank_start = (vblank & 0xfff) + 1; | |
670 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
671 | ||
672 | /* Set the border color to purple. */ | |
673 | I915_WRITE(bclrpat_reg, 0x500050); | |
674 | ||
cf819eff | 675 | if (!IS_GEN(dev_priv, 2)) { |
c7cc5216 | 676 | u32 pipeconf = I915_READ(pipeconf_reg); |
e4a5d54f | 677 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
19c55da1 | 678 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
679 | /* Wait for next Vblank to substitue |
680 | * border color for Color info */ | |
0f0f74bc | 681 | intel_wait_for_vblank(dev_priv, pipe); |
f0f59a00 | 682 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
683 | status = ((st00 & (1 << 4)) != 0) ? |
684 | connector_status_connected : | |
685 | connector_status_disconnected; | |
686 | ||
687 | I915_WRITE(pipeconf_reg, pipeconf); | |
688 | } else { | |
689 | bool restore_vblank = false; | |
690 | int count, detect; | |
691 | ||
692 | /* | |
693 | * If there isn't any border, add some. | |
694 | * Yes, this will flicker | |
695 | */ | |
696 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
c7cc5216 JN |
697 | u32 vsync = I915_READ(vsync_reg); |
698 | u32 vsync_start = (vsync & 0xffff) + 1; | |
e4a5d54f ML |
699 | |
700 | vblank_start = vsync_start; | |
701 | I915_WRITE(vblank_reg, | |
702 | (vblank_start - 1) | | |
703 | ((vblank_end - 1) << 16)); | |
704 | restore_vblank = true; | |
705 | } | |
706 | /* sample in the vertical border, selecting the larger one */ | |
707 | if (vblank_start - vactive >= vtotal - vblank_end) | |
708 | vsample = (vblank_start + vactive) >> 1; | |
709 | else | |
710 | vsample = (vtotal + vblank_end) >> 1; | |
711 | ||
712 | /* | |
713 | * Wait for the border to be displayed | |
714 | */ | |
715 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
716 | ; | |
717 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
718 | ; | |
719 | /* | |
720 | * Watch ST00 for an entire scanline | |
721 | */ | |
722 | detect = 0; | |
723 | count = 0; | |
724 | do { | |
725 | count++; | |
726 | /* Read the ST00 VGA status register */ | |
f0f59a00 | 727 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
728 | if (st00 & (1 << 4)) |
729 | detect++; | |
730 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
731 | ||
732 | /* restore vblank if necessary */ | |
733 | if (restore_vblank) | |
734 | I915_WRITE(vblank_reg, vblank); | |
735 | /* | |
736 | * If more than 3/4 of the scanline detected a monitor, | |
737 | * then it is assumed to be present. This works even on i830, | |
738 | * where there isn't any way to force the border color across | |
739 | * the screen | |
740 | */ | |
741 | status = detect * 4 > count * 3 ? | |
742 | connector_status_connected : | |
743 | connector_status_disconnected; | |
744 | } | |
745 | ||
746 | /* Restore previous settings */ | |
747 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
748 | ||
749 | return status; | |
750 | } | |
751 | ||
f0dfb1a8 VS |
752 | static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) |
753 | { | |
754 | DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); | |
755 | return 1; | |
756 | } | |
757 | ||
758 | static const struct dmi_system_id intel_spurious_crt_detect[] = { | |
759 | { | |
760 | .callback = intel_spurious_crt_detect_dmi_callback, | |
761 | .ident = "ACER ZGB", | |
762 | .matches = { | |
763 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
764 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
765 | }, | |
766 | }, | |
69a44b16 VS |
767 | { |
768 | .callback = intel_spurious_crt_detect_dmi_callback, | |
769 | .ident = "Intel DZ77BH-55K", | |
770 | .matches = { | |
771 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), | |
772 | DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), | |
773 | }, | |
774 | }, | |
f0dfb1a8 VS |
775 | { } |
776 | }; | |
777 | ||
6c5ed5ae ML |
778 | static int |
779 | intel_crt_detect(struct drm_connector *connector, | |
780 | struct drm_modeset_acquire_ctx *ctx, | |
781 | bool force) | |
79e53945 | 782 | { |
66478475 | 783 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
c9a1c4cd | 784 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 | 785 | struct intel_encoder *intel_encoder = &crt->base; |
0e6e0be4 | 786 | intel_wakeref_t wakeref; |
6c5ed5ae | 787 | int status, ret; |
e95c8438 | 788 | struct intel_load_detect_pipe tmp; |
79e53945 | 789 | |
164c8598 | 790 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 791 | connector->base.id, connector->name, |
164c8598 CW |
792 | force); |
793 | ||
4165791d | 794 | if (i915_modparams.load_detect_test) { |
0e6e0be4 CW |
795 | wakeref = intel_display_power_get(dev_priv, |
796 | intel_encoder->power_domain); | |
4165791d VS |
797 | goto load_detect; |
798 | } | |
799 | ||
f0dfb1a8 VS |
800 | /* Skip machines without VGA that falsely report hotplug events */ |
801 | if (dmi_check_system(intel_spurious_crt_detect)) | |
802 | return connector_status_disconnected; | |
803 | ||
0e6e0be4 CW |
804 | wakeref = intel_display_power_get(dev_priv, |
805 | intel_encoder->power_domain); | |
671dedd2 | 806 | |
56b857a5 | 807 | if (I915_HAS_HOTPLUG(dev_priv)) { |
aaa37730 DV |
808 | /* We can not rely on the HPD pin always being correctly wired |
809 | * up, for example many KVM do not pass it through, and so | |
810 | * only trust an assertion that the monitor is connected. | |
811 | */ | |
6ec3d0c0 CW |
812 | if (intel_crt_detect_hotplug(connector)) { |
813 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
814 | status = connector_status_connected; |
815 | goto out; | |
aaa37730 | 816 | } else |
e7dbb2f2 | 817 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
818 | } |
819 | ||
c19a0df2 PZ |
820 | if (intel_crt_detect_ddc(connector)) { |
821 | status = connector_status_connected; | |
822 | goto out; | |
823 | } | |
79e53945 | 824 | |
aaa37730 DV |
825 | /* Load detection is broken on HPD capable machines. Whoever wants a |
826 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
827 | * to have the right resistors for HP detection) needs to fix this up. | |
828 | * For now just bail out. */ | |
4165791d | 829 | if (I915_HAS_HOTPLUG(dev_priv)) { |
c19a0df2 PZ |
830 | status = connector_status_disconnected; |
831 | goto out; | |
832 | } | |
aaa37730 | 833 | |
4165791d | 834 | load_detect: |
c19a0df2 PZ |
835 | if (!force) { |
836 | status = connector->status; | |
837 | goto out; | |
838 | } | |
7b334fcb | 839 | |
e4a5d54f | 840 | /* for pre-945g platforms use load detect */ |
6c5ed5ae ML |
841 | ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx); |
842 | if (ret > 0) { | |
e95c8438 DV |
843 | if (intel_crt_detect_ddc(connector)) |
844 | status = connector_status_connected; | |
66478475 | 845 | else if (INTEL_GEN(dev_priv) < 4) |
c8ecb2f1 ML |
846 | status = intel_crt_load_detect(crt, |
847 | to_intel_crtc(connector->state->crtc)->pipe); | |
4f044a88 | 848 | else if (i915_modparams.load_detect_test) |
32fff610 | 849 | status = connector_status_disconnected; |
5bedeb2d DV |
850 | else |
851 | status = connector_status_unknown; | |
6c5ed5ae | 852 | intel_release_load_detect_pipe(connector, &tmp, ctx); |
2927e421 | 853 | } else if (ret == 0) { |
e95c8438 | 854 | status = connector_status_unknown; |
2927e421 | 855 | } else { |
6c5ed5ae | 856 | status = ret; |
2927e421 | 857 | } |
208bf9fd | 858 | |
c19a0df2 | 859 | out: |
0e6e0be4 | 860 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
e4a5d54f | 861 | return status; |
79e53945 JB |
862 | } |
863 | ||
79e53945 JB |
864 | static int intel_crt_get_modes(struct drm_connector *connector) |
865 | { | |
8e4d36b9 | 866 | struct drm_device *dev = connector->dev; |
fac5e23e | 867 | struct drm_i915_private *dev_priv = to_i915(dev); |
671dedd2 ID |
868 | struct intel_crt *crt = intel_attached_crt(connector); |
869 | struct intel_encoder *intel_encoder = &crt->base; | |
0e6e0be4 | 870 | intel_wakeref_t wakeref; |
3bd7d909 | 871 | struct i2c_adapter *i2c; |
0e6e0be4 | 872 | int ret; |
8e4d36b9 | 873 | |
0e6e0be4 CW |
874 | wakeref = intel_display_power_get(dev_priv, |
875 | intel_encoder->power_domain); | |
671dedd2 | 876 | |
41aa3448 | 877 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 878 | ret = intel_crt_ddc_get_modes(connector, i2c); |
9beb5fea | 879 | if (ret || !IS_G4X(dev_priv)) |
671dedd2 | 880 | goto out; |
8e4d36b9 | 881 | |
8e4d36b9 | 882 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
988c7015 | 883 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
671dedd2 ID |
884 | ret = intel_crt_ddc_get_modes(connector, i2c); |
885 | ||
886 | out: | |
0e6e0be4 | 887 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
671dedd2 ID |
888 | |
889 | return ret; | |
79e53945 JB |
890 | } |
891 | ||
9504a892 | 892 | void intel_crt_reset(struct drm_encoder *encoder) |
f3269058 | 893 | { |
66478475 | 894 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
28cf71ce | 895 | struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); |
f3269058 | 896 | |
66478475 | 897 | if (INTEL_GEN(dev_priv) >= 5) { |
2e938892 DV |
898 | u32 adpa; |
899 | ||
ca54b810 | 900 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
901 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
902 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
903 | I915_WRITE(crt->adpa_reg, adpa); |
904 | POSTING_READ(crt->adpa_reg); | |
2e938892 | 905 | |
0039a4b3 | 906 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
f3269058 | 907 | crt->force_hotplug_required = 1; |
2e938892 DV |
908 | } |
909 | ||
f3269058 CW |
910 | } |
911 | ||
79e53945 JB |
912 | /* |
913 | * Routines for controlling stuff on the analog port | |
914 | */ | |
915 | ||
79e53945 | 916 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
79e53945 | 917 | .fill_modes = drm_helper_probe_single_connector_modes, |
1ebaa0b9 | 918 | .late_register = intel_connector_register, |
c191eca1 | 919 | .early_unregister = intel_connector_unregister, |
d4b26e4f | 920 | .destroy = intel_connector_destroy, |
c6f95f27 | 921 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 922 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
923 | }; |
924 | ||
925 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
6c5ed5ae | 926 | .detect_ctx = intel_crt_detect, |
79e53945 JB |
927 | .mode_valid = intel_crt_mode_valid, |
928 | .get_modes = intel_crt_get_modes, | |
79e53945 JB |
929 | }; |
930 | ||
79e53945 | 931 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
28cf71ce | 932 | .reset = intel_crt_reset, |
ea5b213a | 933 | .destroy = intel_encoder_destroy, |
79e53945 JB |
934 | }; |
935 | ||
c39055b0 | 936 | void intel_crt_init(struct drm_i915_private *dev_priv) |
79e53945 JB |
937 | { |
938 | struct drm_connector *connector; | |
c9a1c4cd | 939 | struct intel_crt *crt; |
454c1ca8 | 940 | struct intel_connector *intel_connector; |
6c03a6bd VS |
941 | i915_reg_t adpa_reg; |
942 | u32 adpa; | |
79e53945 | 943 | |
6e266956 | 944 | if (HAS_PCH_SPLIT(dev_priv)) |
6c03a6bd | 945 | adpa_reg = PCH_ADPA; |
11a914c2 | 946 | else if (IS_VALLEYVIEW(dev_priv)) |
6c03a6bd VS |
947 | adpa_reg = VLV_ADPA; |
948 | else | |
949 | adpa_reg = ADPA; | |
950 | ||
951 | adpa = I915_READ(adpa_reg); | |
952 | if ((adpa & ADPA_DAC_ENABLE) == 0) { | |
953 | /* | |
954 | * On some machines (some IVB at least) CRT can be | |
955 | * fused off, but there's no known fuse bit to | |
956 | * indicate that. On these machine the ADPA register | |
957 | * works normally, except the DAC enable bit won't | |
958 | * take. So the only way to tell is attempt to enable | |
959 | * it and see what happens. | |
960 | */ | |
961 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | | |
962 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | |
963 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) | |
964 | return; | |
965 | I915_WRITE(adpa_reg, adpa); | |
966 | } | |
967 | ||
c9a1c4cd CW |
968 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
969 | if (!crt) | |
79e53945 JB |
970 | return; |
971 | ||
9bdbd0b9 | 972 | intel_connector = intel_connector_alloc(); |
454c1ca8 | 973 | if (!intel_connector) { |
c9a1c4cd | 974 | kfree(crt); |
454c1ca8 ZW |
975 | return; |
976 | } | |
977 | ||
978 | connector = &intel_connector->base; | |
637f44d2 | 979 | crt->connector = intel_connector; |
c39055b0 | 980 | drm_connector_init(&dev_priv->drm, &intel_connector->base, |
79e53945 JB |
981 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
982 | ||
c39055b0 | 983 | drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, |
580d8ed5 | 984 | DRM_MODE_ENCODER_DAC, "CRT"); |
79e53945 | 985 | |
c9a1c4cd | 986 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 987 | |
c9a1c4cd | 988 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 989 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
50a0bc90 | 990 | if (IS_I830(dev_priv)) |
59c859d6 ED |
991 | crt->base.crtc_mask = (1 << 0); |
992 | else | |
0826874a | 993 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 994 | |
cf819eff | 995 | if (IS_GEN(dev_priv, 2)) |
dbb02575 DV |
996 | connector->interlace_allowed = 0; |
997 | else | |
998 | connector->interlace_allowed = 1; | |
79e53945 JB |
999 | connector->doublescan_allowed = 0; |
1000 | ||
6c03a6bd | 1001 | crt->adpa_reg = adpa_reg; |
540a8950 | 1002 | |
79f255a0 ACO |
1003 | crt->base.power_domain = POWER_DOMAIN_PORT_CRT; |
1004 | ||
56b857a5 | 1005 | if (I915_HAS_HOTPLUG(dev_priv) && |
dba14b27 | 1006 | !dmi_check_system(intel_spurious_crt_detect)) { |
1d843f9d | 1007 | crt->base.hpd_pin = HPD_CRT; |
dba14b27 VS |
1008 | crt->base.hotplug = intel_encoder_hotplug; |
1009 | } | |
c5ce4ef3 | 1010 | |
4f8036a2 | 1011 | if (HAS_DDI(dev_priv)) { |
03cdc1d4 | 1012 | crt->base.port = PORT_E; |
a2985791 | 1013 | crt->base.get_config = hsw_crt_get_config; |
4eda01b2 | 1014 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
2f26cdc0 | 1015 | crt->base.compute_config = hsw_crt_compute_config; |
51c4fa69 JN |
1016 | crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; |
1017 | crt->base.pre_enable = hsw_pre_enable_crt; | |
1018 | crt->base.enable = hsw_enable_crt; | |
3daa3cee | 1019 | crt->base.disable = hsw_disable_crt; |
b7076546 | 1020 | crt->base.post_disable = hsw_post_disable_crt; |
a2985791 | 1021 | } else { |
c5ce4ef3 | 1022 | if (HAS_PCH_SPLIT(dev_priv)) { |
2f26cdc0 | 1023 | crt->base.compute_config = pch_crt_compute_config; |
c5ce4ef3 JN |
1024 | crt->base.disable = pch_disable_crt; |
1025 | crt->base.post_disable = pch_post_disable_crt; | |
1026 | } else { | |
2f26cdc0 | 1027 | crt->base.compute_config = intel_crt_compute_config; |
c5ce4ef3 JN |
1028 | crt->base.disable = intel_disable_crt; |
1029 | } | |
03cdc1d4 | 1030 | crt->base.port = PORT_NONE; |
a2985791 | 1031 | crt->base.get_config = intel_crt_get_config; |
4eda01b2 | 1032 | crt->base.get_hw_state = intel_crt_get_hw_state; |
51c4fa69 | 1033 | crt->base.enable = intel_enable_crt; |
a2985791 | 1034 | } |
e403fc94 | 1035 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
df0323c4 | 1036 | |
79e53945 JB |
1037 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
1038 | ||
56b857a5 | 1039 | if (!I915_HAS_HOTPLUG(dev_priv)) |
821450c6 | 1040 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
eb1f8e4f | 1041 | |
e7dbb2f2 KP |
1042 | /* |
1043 | * Configure the automatic hotplug detection stuff | |
1044 | */ | |
1045 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 1046 | |
68d18ad7 | 1047 | /* |
3e68320e DL |
1048 | * TODO: find a proper way to discover whether we need to set the the |
1049 | * polarity and link reversal bits or not, instead of relying on the | |
1050 | * BIOS. | |
68d18ad7 | 1051 | */ |
6e266956 | 1052 | if (HAS_PCH_LPT(dev_priv)) { |
3e68320e DL |
1053 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
1054 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
1055 | ||
eede3b53 | 1056 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
3e68320e | 1057 | } |
754970ee | 1058 | |
28cf71ce | 1059 | intel_crt_reset(&crt->base.base); |
79e53945 | 1060 | } |