drm/i915: PLL registers need an offset on VLV
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_crt.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
8ca4013d 27#include <linux/dmi.h>
79e53945 28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
760285e7
DH
30#include <drm/drmP.h>
31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_edid.h>
79e53945 34#include "intel_drv.h"
760285e7 35#include <drm/i915_drm.h>
79e53945
JB
36#include "i915_drv.h"
37
e7dbb2f2
KP
38/* Here's the desired hotplug mode */
39#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
40 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
41 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
42 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
43 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
44 ADPA_CRT_HOTPLUG_ENABLE)
45
c9a1c4cd
CW
46struct intel_crt {
47 struct intel_encoder base;
e7dbb2f2 48 bool force_hotplug_required;
540a8950 49 u32 adpa_reg;
c9a1c4cd
CW
50};
51
52static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
53{
54 return container_of(intel_attached_encoder(connector),
55 struct intel_crt, base);
56}
57
540a8950 58static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
79e53945 59{
540a8950
DV
60 return container_of(encoder, struct intel_crt, base);
61}
62
e403fc94
DV
63static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
64 enum pipe *pipe)
79e53945 65{
e403fc94 66 struct drm_device *dev = encoder->base.dev;
79e53945 67 struct drm_i915_private *dev_priv = dev->dev_private;
e403fc94
DV
68 struct intel_crt *crt = intel_encoder_to_crt(encoder);
69 u32 tmp;
70
71 tmp = I915_READ(crt->adpa_reg);
72
73 if (!(tmp & ADPA_DAC_ENABLE))
74 return false;
75
76 if (HAS_PCH_CPT(dev))
77 *pipe = PORT_TO_PIPE_CPT(tmp);
78 else
79 *pipe = PORT_TO_PIPE(tmp);
80
81 return true;
82}
83
2124604b
DV
84static void intel_disable_crt(struct intel_encoder *encoder)
85{
86 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
87 struct intel_crt *crt = intel_encoder_to_crt(encoder);
df0323c4 88 u32 temp;
79e53945 89
2124604b
DV
90 temp = I915_READ(crt->adpa_reg);
91 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
df0323c4 92 temp &= ~ADPA_DAC_ENABLE;
2124604b
DV
93 I915_WRITE(crt->adpa_reg, temp);
94}
df0323c4 95
2124604b
DV
96static void intel_enable_crt(struct intel_encoder *encoder)
97{
98 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
99 struct intel_crt *crt = intel_encoder_to_crt(encoder);
100 u32 temp;
df0323c4 101
2124604b
DV
102 temp = I915_READ(crt->adpa_reg);
103 temp |= ADPA_DAC_ENABLE;
104 I915_WRITE(crt->adpa_reg, temp);
df0323c4 105}
2c07245f 106
b2cabb0e
DV
107/* Note: The caller is required to filter out dpms modes not supported by the
108 * platform. */
109static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
df0323c4 110{
b2cabb0e 111 struct drm_device *dev = encoder->base.dev;
df0323c4 112 struct drm_i915_private *dev_priv = dev->dev_private;
b2cabb0e 113 struct intel_crt *crt = intel_encoder_to_crt(encoder);
df0323c4
JB
114 u32 temp;
115
b2cabb0e 116 temp = I915_READ(crt->adpa_reg);
79e53945 117 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
febc7694 118 temp &= ~ADPA_DAC_ENABLE;
79e53945 119
0206e353 120 switch (mode) {
79e53945
JB
121 case DRM_MODE_DPMS_ON:
122 temp |= ADPA_DAC_ENABLE;
123 break;
124 case DRM_MODE_DPMS_STANDBY:
125 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
126 break;
127 case DRM_MODE_DPMS_SUSPEND:
128 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
129 break;
130 case DRM_MODE_DPMS_OFF:
131 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
132 break;
133 }
134
b2cabb0e 135 I915_WRITE(crt->adpa_reg, temp);
df0323c4 136}
2c07245f 137
b2cabb0e 138static void intel_crt_dpms(struct drm_connector *connector, int mode)
df0323c4 139{
b2cabb0e
DV
140 struct drm_device *dev = connector->dev;
141 struct intel_encoder *encoder = intel_attached_encoder(connector);
142 struct drm_crtc *crtc;
143 int old_dpms;
79e53945 144
b2cabb0e 145 /* PCH platforms and VLV only support on/off. */
4a8dece2 146 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
bd9e8413
JB
147 mode = DRM_MODE_DPMS_OFF;
148
b2cabb0e
DV
149 if (mode == connector->dpms)
150 return;
151
152 old_dpms = connector->dpms;
153 connector->dpms = mode;
154
155 /* Only need to change hw state when actually enabled */
156 crtc = encoder->base.crtc;
157 if (!crtc) {
158 encoder->connectors_active = false;
159 return;
79e53945
JB
160 }
161
b2cabb0e
DV
162 /* We need the pipe to run for anything but OFF. */
163 if (mode == DRM_MODE_DPMS_OFF)
164 encoder->connectors_active = false;
165 else
166 encoder->connectors_active = true;
167
168 if (mode < old_dpms) {
169 /* From off to on, enable the pipe first. */
170 intel_crtc_update_dpms(crtc);
171
172 intel_crt_set_dpms(encoder, mode);
173 } else {
174 intel_crt_set_dpms(encoder, mode);
175
176 intel_crtc_update_dpms(crtc);
177 }
0a91ca29 178
b980514c 179 intel_modeset_check_state(connector->dev);
79e53945
JB
180}
181
182static int intel_crt_mode_valid(struct drm_connector *connector,
183 struct drm_display_mode *mode)
184{
6bcdcd9e
ZY
185 struct drm_device *dev = connector->dev;
186
187 int max_clock = 0;
79e53945
JB
188 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
189 return MODE_NO_DBLESCAN;
190
6bcdcd9e
ZY
191 if (mode->clock < 25000)
192 return MODE_CLOCK_LOW;
193
a6c45cf0 194 if (IS_GEN2(dev))
6bcdcd9e
ZY
195 max_clock = 350000;
196 else
197 max_clock = 400000;
198 if (mode->clock > max_clock)
199 return MODE_CLOCK_HIGH;
79e53945 200
d4b1931c
PZ
201 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
202 if (HAS_PCH_LPT(dev) &&
203 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
204 return MODE_CLOCK_HIGH;
205
79e53945
JB
206 return MODE_OK;
207}
208
209static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
e811f5ae 210 const struct drm_display_mode *mode,
79e53945
JB
211 struct drm_display_mode *adjusted_mode)
212{
213 return true;
214}
215
216static void intel_crt_mode_set(struct drm_encoder *encoder,
217 struct drm_display_mode *mode,
218 struct drm_display_mode *adjusted_mode)
219{
220
221 struct drm_device *dev = encoder->dev;
222 struct drm_crtc *crtc = encoder->crtc;
540a8950
DV
223 struct intel_crt *crt =
224 intel_encoder_to_crt(to_intel_encoder(encoder));
79e53945
JB
225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
226 struct drm_i915_private *dev_priv = dev->dev_private;
6478d414 227 u32 adpa;
79e53945 228
912d812e
DV
229 if (HAS_PCH_SPLIT(dev))
230 adpa = ADPA_HOTPLUG_BITS;
231 else
232 adpa = 0;
233
79e53945
JB
234 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
235 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
236 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
237 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
238
75770564 239 /* For CPT allow 3 pipe config, for others just use A or B */
4837813a
PZ
240 if (HAS_PCH_LPT(dev))
241 ; /* Those bits don't exist here */
242 else if (HAS_PCH_CPT(dev))
75770564
JB
243 adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
244 else if (intel_crtc->pipe == 0)
245 adpa |= ADPA_PIPE_A_SELECT;
246 else
247 adpa |= ADPA_PIPE_B_SELECT;
79e53945 248
9db4a9c7
JB
249 if (!HAS_PCH_SPLIT(dev))
250 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
251
540a8950 252 I915_WRITE(crt->adpa_reg, adpa);
2c07245f
ZW
253}
254
f2b115e6 255static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
2c07245f
ZW
256{
257 struct drm_device *dev = connector->dev;
e7dbb2f2 258 struct intel_crt *crt = intel_attached_crt(connector);
2c07245f 259 struct drm_i915_private *dev_priv = dev->dev_private;
e7dbb2f2 260 u32 adpa;
2c07245f
ZW
261 bool ret;
262
e7dbb2f2
KP
263 /* The first time through, trigger an explicit detection cycle */
264 if (crt->force_hotplug_required) {
265 bool turn_off_dac = HAS_PCH_SPLIT(dev);
266 u32 save_adpa;
67941da2 267
e7dbb2f2
KP
268 crt->force_hotplug_required = 0;
269
270 save_adpa = adpa = I915_READ(PCH_ADPA);
271 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
272
273 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
274 if (turn_off_dac)
275 adpa &= ~ADPA_DAC_ENABLE;
276
277 I915_WRITE(PCH_ADPA, adpa);
278
279 if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
280 1000))
281 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
282
283 if (turn_off_dac) {
284 I915_WRITE(PCH_ADPA, save_adpa);
285 POSTING_READ(PCH_ADPA);
286 }
a4a6b901
ZW
287 }
288
2c07245f
ZW
289 /* Check the status to see if both blue and green are on now */
290 adpa = I915_READ(PCH_ADPA);
e7dbb2f2 291 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
2c07245f
ZW
292 ret = true;
293 else
294 ret = false;
e7dbb2f2 295 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
2c07245f 296
2c07245f 297 return ret;
79e53945
JB
298}
299
7d2c24e8
JB
300static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
301{
302 struct drm_device *dev = connector->dev;
303 struct drm_i915_private *dev_priv = dev->dev_private;
304 u32 adpa;
305 bool ret;
306 u32 save_adpa;
307
308 save_adpa = adpa = I915_READ(ADPA);
309 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
310
311 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
312
313 I915_WRITE(ADPA, adpa);
314
315 if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
316 1000)) {
317 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
318 I915_WRITE(ADPA, save_adpa);
319 }
320
321 /* Check the status to see if both blue and green are on now */
322 adpa = I915_READ(ADPA);
323 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
324 ret = true;
325 else
326 ret = false;
327
328 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
329
330 /* FIXME: debug force function and remove */
331 ret = true;
332
333 return ret;
334}
335
79e53945
JB
336/**
337 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
338 *
339 * Not for i915G/i915GM
340 *
341 * \return true if CRT is connected.
342 * \return false if CRT is disconnected.
343 */
344static bool intel_crt_detect_hotplug(struct drm_connector *connector)
345{
346 struct drm_device *dev = connector->dev;
347 struct drm_i915_private *dev_priv = dev->dev_private;
7a772c49
AJ
348 u32 hotplug_en, orig, stat;
349 bool ret = false;
771cb081 350 int i, tries = 0;
2c07245f 351
bad720ff 352 if (HAS_PCH_SPLIT(dev))
f2b115e6 353 return intel_ironlake_crt_detect_hotplug(connector);
2c07245f 354
7d2c24e8
JB
355 if (IS_VALLEYVIEW(dev))
356 return valleyview_crt_detect_hotplug(connector);
357
771cb081
ZY
358 /*
359 * On 4 series desktop, CRT detect sequence need to be done twice
360 * to get a reliable result.
361 */
79e53945 362
771cb081
ZY
363 if (IS_G4X(dev) && !IS_GM45(dev))
364 tries = 2;
365 else
366 tries = 1;
7a772c49 367 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
771cb081
ZY
368 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
369
771cb081 370 for (i = 0; i < tries ; i++) {
771cb081
ZY
371 /* turn on the FORCE_DETECT */
372 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
771cb081 373 /* wait for FORCE_DETECT to go off */
913d8d11
CW
374 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
375 CRT_HOTPLUG_FORCE_DETECT) == 0,
481b6af3 376 1000))
79077319 377 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
771cb081 378 }
79e53945 379
7a772c49
AJ
380 stat = I915_READ(PORT_HOTPLUG_STAT);
381 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
382 ret = true;
383
384 /* clear the interrupt we just generated, if any */
385 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
79e53945 386
7a772c49
AJ
387 /* and put the bits back */
388 I915_WRITE(PORT_HOTPLUG_EN, orig);
389
390 return ret;
79e53945
JB
391}
392
f1a2f5b7
JN
393static struct edid *intel_crt_get_edid(struct drm_connector *connector,
394 struct i2c_adapter *i2c)
395{
396 struct edid *edid;
397
398 edid = drm_get_edid(connector, i2c);
399
400 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
401 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
402 intel_gmbus_force_bit(i2c, true);
403 edid = drm_get_edid(connector, i2c);
404 intel_gmbus_force_bit(i2c, false);
405 }
406
407 return edid;
408}
409
410/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
411static int intel_crt_ddc_get_modes(struct drm_connector *connector,
412 struct i2c_adapter *adapter)
413{
414 struct edid *edid;
ebda95a9 415 int ret;
f1a2f5b7
JN
416
417 edid = intel_crt_get_edid(connector, adapter);
418 if (!edid)
419 return 0;
420
ebda95a9
JN
421 ret = intel_connector_update_modes(connector, edid);
422 kfree(edid);
423
424 return ret;
f1a2f5b7
JN
425}
426
f5afcd3d 427static bool intel_crt_detect_ddc(struct drm_connector *connector)
79e53945 428{
f5afcd3d 429 struct intel_crt *crt = intel_attached_crt(connector);
c9a1c4cd 430 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
a2bd1f54
DV
431 struct edid *edid;
432 struct i2c_adapter *i2c;
79e53945 433
a2bd1f54 434 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
79e53945 435
a2bd1f54 436 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
f1a2f5b7 437 edid = intel_crt_get_edid(connector, i2c);
a2bd1f54
DV
438
439 if (edid) {
440 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
f5afcd3d 441
f5afcd3d
DM
442 /*
443 * This may be a DVI-I connector with a shared DDC
444 * link between analog and digital outputs, so we
445 * have to check the EDID input spec of the attached device.
446 */
f5afcd3d
DM
447 if (!is_digital) {
448 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
449 return true;
450 }
a2bd1f54
DV
451
452 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
453 } else {
454 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
6ec3d0c0
CW
455 }
456
a2bd1f54
DV
457 kfree(edid);
458
6ec3d0c0 459 return false;
79e53945
JB
460}
461
e4a5d54f 462static enum drm_connector_status
7173188d 463intel_crt_load_detect(struct intel_crt *crt)
e4a5d54f 464{
7173188d 465 struct drm_device *dev = crt->base.base.dev;
e4a5d54f 466 struct drm_i915_private *dev_priv = dev->dev_private;
7173188d 467 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
e4a5d54f
ML
468 uint32_t save_bclrpat;
469 uint32_t save_vtotal;
470 uint32_t vtotal, vactive;
471 uint32_t vsample;
472 uint32_t vblank, vblank_start, vblank_end;
473 uint32_t dsl;
474 uint32_t bclrpat_reg;
475 uint32_t vtotal_reg;
476 uint32_t vblank_reg;
477 uint32_t vsync_reg;
478 uint32_t pipeconf_reg;
479 uint32_t pipe_dsl_reg;
480 uint8_t st00;
481 enum drm_connector_status status;
482
6ec3d0c0
CW
483 DRM_DEBUG_KMS("starting load-detect on CRT\n");
484
9db4a9c7
JB
485 bclrpat_reg = BCLRPAT(pipe);
486 vtotal_reg = VTOTAL(pipe);
487 vblank_reg = VBLANK(pipe);
488 vsync_reg = VSYNC(pipe);
489 pipeconf_reg = PIPECONF(pipe);
490 pipe_dsl_reg = PIPEDSL(pipe);
e4a5d54f
ML
491
492 save_bclrpat = I915_READ(bclrpat_reg);
493 save_vtotal = I915_READ(vtotal_reg);
494 vblank = I915_READ(vblank_reg);
495
496 vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
497 vactive = (save_vtotal & 0x7ff) + 1;
498
499 vblank_start = (vblank & 0xfff) + 1;
500 vblank_end = ((vblank >> 16) & 0xfff) + 1;
501
502 /* Set the border color to purple. */
503 I915_WRITE(bclrpat_reg, 0x500050);
504
a6c45cf0 505 if (!IS_GEN2(dev)) {
e4a5d54f
ML
506 uint32_t pipeconf = I915_READ(pipeconf_reg);
507 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
19c55da1 508 POSTING_READ(pipeconf_reg);
e4a5d54f
ML
509 /* Wait for next Vblank to substitue
510 * border color for Color info */
9d0498a2 511 intel_wait_for_vblank(dev, pipe);
e4a5d54f
ML
512 st00 = I915_READ8(VGA_MSR_WRITE);
513 status = ((st00 & (1 << 4)) != 0) ?
514 connector_status_connected :
515 connector_status_disconnected;
516
517 I915_WRITE(pipeconf_reg, pipeconf);
518 } else {
519 bool restore_vblank = false;
520 int count, detect;
521
522 /*
523 * If there isn't any border, add some.
524 * Yes, this will flicker
525 */
526 if (vblank_start <= vactive && vblank_end >= vtotal) {
527 uint32_t vsync = I915_READ(vsync_reg);
528 uint32_t vsync_start = (vsync & 0xffff) + 1;
529
530 vblank_start = vsync_start;
531 I915_WRITE(vblank_reg,
532 (vblank_start - 1) |
533 ((vblank_end - 1) << 16));
534 restore_vblank = true;
535 }
536 /* sample in the vertical border, selecting the larger one */
537 if (vblank_start - vactive >= vtotal - vblank_end)
538 vsample = (vblank_start + vactive) >> 1;
539 else
540 vsample = (vtotal + vblank_end) >> 1;
541
542 /*
543 * Wait for the border to be displayed
544 */
545 while (I915_READ(pipe_dsl_reg) >= vactive)
546 ;
547 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
548 ;
549 /*
550 * Watch ST00 for an entire scanline
551 */
552 detect = 0;
553 count = 0;
554 do {
555 count++;
556 /* Read the ST00 VGA status register */
557 st00 = I915_READ8(VGA_MSR_WRITE);
558 if (st00 & (1 << 4))
559 detect++;
560 } while ((I915_READ(pipe_dsl_reg) == dsl));
561
562 /* restore vblank if necessary */
563 if (restore_vblank)
564 I915_WRITE(vblank_reg, vblank);
565 /*
566 * If more than 3/4 of the scanline detected a monitor,
567 * then it is assumed to be present. This works even on i830,
568 * where there isn't any way to force the border color across
569 * the screen
570 */
571 status = detect * 4 > count * 3 ?
572 connector_status_connected :
573 connector_status_disconnected;
574 }
575
576 /* Restore previous settings */
577 I915_WRITE(bclrpat_reg, save_bclrpat);
578
579 return status;
580}
581
7b334fcb 582static enum drm_connector_status
930a9e28 583intel_crt_detect(struct drm_connector *connector, bool force)
79e53945
JB
584{
585 struct drm_device *dev = connector->dev;
c9a1c4cd 586 struct intel_crt *crt = intel_attached_crt(connector);
e4a5d54f 587 enum drm_connector_status status;
e95c8438 588 struct intel_load_detect_pipe tmp;
79e53945 589
a6c45cf0 590 if (I915_HAS_HOTPLUG(dev)) {
aaa37730
DV
591 /* We can not rely on the HPD pin always being correctly wired
592 * up, for example many KVM do not pass it through, and so
593 * only trust an assertion that the monitor is connected.
594 */
6ec3d0c0
CW
595 if (intel_crt_detect_hotplug(connector)) {
596 DRM_DEBUG_KMS("CRT detected via hotplug\n");
79e53945 597 return connector_status_connected;
aaa37730 598 } else
e7dbb2f2 599 DRM_DEBUG_KMS("CRT not detected via hotplug\n");
79e53945
JB
600 }
601
f5afcd3d 602 if (intel_crt_detect_ddc(connector))
79e53945
JB
603 return connector_status_connected;
604
aaa37730
DV
605 /* Load detection is broken on HPD capable machines. Whoever wants a
606 * broken monitor (without edid) to work behind a broken kvm (that fails
607 * to have the right resistors for HP detection) needs to fix this up.
608 * For now just bail out. */
609 if (I915_HAS_HOTPLUG(dev))
610 return connector_status_disconnected;
611
930a9e28 612 if (!force)
7b334fcb
CW
613 return connector->status;
614
e4a5d54f 615 /* for pre-945g platforms use load detect */
d2434ab7 616 if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
e95c8438
DV
617 if (intel_crt_detect_ddc(connector))
618 status = connector_status_connected;
619 else
620 status = intel_crt_load_detect(crt);
d2434ab7 621 intel_release_load_detect_pipe(connector, &tmp);
e95c8438
DV
622 } else
623 status = connector_status_unknown;
e4a5d54f
ML
624
625 return status;
79e53945
JB
626}
627
628static void intel_crt_destroy(struct drm_connector *connector)
629{
79e53945
JB
630 drm_sysfs_connector_remove(connector);
631 drm_connector_cleanup(connector);
632 kfree(connector);
633}
634
635static int intel_crt_get_modes(struct drm_connector *connector)
636{
8e4d36b9 637 struct drm_device *dev = connector->dev;
f899fc64 638 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 639 int ret;
3bd7d909 640 struct i2c_adapter *i2c;
8e4d36b9 641
3bd7d909 642 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
f1a2f5b7 643 ret = intel_crt_ddc_get_modes(connector, i2c);
8e4d36b9 644 if (ret || !IS_G4X(dev))
f899fc64 645 return ret;
8e4d36b9 646
8e4d36b9 647 /* Try to probe digital port for output in DVI-I -> VGA mode. */
3bd7d909 648 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
f1a2f5b7 649 return intel_crt_ddc_get_modes(connector, i2c);
79e53945
JB
650}
651
652static int intel_crt_set_property(struct drm_connector *connector,
653 struct drm_property *property,
654 uint64_t value)
655{
79e53945
JB
656 return 0;
657}
658
f3269058
CW
659static void intel_crt_reset(struct drm_connector *connector)
660{
661 struct drm_device *dev = connector->dev;
2e938892 662 struct drm_i915_private *dev_priv = dev->dev_private;
f3269058
CW
663 struct intel_crt *crt = intel_attached_crt(connector);
664
2e938892
DV
665 if (HAS_PCH_SPLIT(dev)) {
666 u32 adpa;
667
668 adpa = I915_READ(PCH_ADPA);
669 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
670 adpa |= ADPA_HOTPLUG_BITS;
671 I915_WRITE(PCH_ADPA, adpa);
672 POSTING_READ(PCH_ADPA);
673
674 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
f3269058 675 crt->force_hotplug_required = 1;
2e938892
DV
676 }
677
f3269058
CW
678}
679
79e53945
JB
680/*
681 * Routines for controlling stuff on the analog port
682 */
683
b2cabb0e 684static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
df0323c4 685 .mode_fixup = intel_crt_mode_fixup,
df0323c4 686 .mode_set = intel_crt_mode_set,
1f703855 687 .disable = intel_encoder_noop,
79e53945
JB
688};
689
690static const struct drm_connector_funcs intel_crt_connector_funcs = {
f3269058 691 .reset = intel_crt_reset,
b2cabb0e 692 .dpms = intel_crt_dpms,
79e53945
JB
693 .detect = intel_crt_detect,
694 .fill_modes = drm_helper_probe_single_connector_modes,
695 .destroy = intel_crt_destroy,
696 .set_property = intel_crt_set_property,
697};
698
699static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
700 .mode_valid = intel_crt_mode_valid,
701 .get_modes = intel_crt_get_modes,
df0e9248 702 .best_encoder = intel_best_encoder,
79e53945
JB
703};
704
79e53945 705static const struct drm_encoder_funcs intel_crt_enc_funcs = {
ea5b213a 706 .destroy = intel_encoder_destroy,
79e53945
JB
707};
708
8ca4013d
DL
709static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
710{
bc0daf48 711 DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
8ca4013d
DL
712 return 1;
713}
714
715static const struct dmi_system_id intel_no_crt[] = {
716 {
717 .callback = intel_no_crt_dmi_callback,
718 .ident = "ACER ZGB",
719 .matches = {
720 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
721 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
722 },
723 },
724 { }
725};
726
79e53945
JB
727void intel_crt_init(struct drm_device *dev)
728{
729 struct drm_connector *connector;
c9a1c4cd 730 struct intel_crt *crt;
454c1ca8 731 struct intel_connector *intel_connector;
db545019 732 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 733
8ca4013d
DL
734 /* Skip machines without VGA that falsely report hotplug events */
735 if (dmi_check_system(intel_no_crt))
736 return;
737
c9a1c4cd
CW
738 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
739 if (!crt)
79e53945
JB
740 return;
741
454c1ca8
ZW
742 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
743 if (!intel_connector) {
c9a1c4cd 744 kfree(crt);
454c1ca8
ZW
745 return;
746 }
747
748 connector = &intel_connector->base;
749 drm_connector_init(dev, &intel_connector->base,
79e53945
JB
750 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
751
c9a1c4cd 752 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
79e53945
JB
753 DRM_MODE_ENCODER_DAC);
754
c9a1c4cd 755 intel_connector_attach_encoder(intel_connector, &crt->base);
79e53945 756
c9a1c4cd 757 crt->base.type = INTEL_OUTPUT_ANALOG;
66a9278e 758 crt->base.cloneable = true;
d63fa0dc 759 if (IS_I830(dev))
59c859d6
ED
760 crt->base.crtc_mask = (1 << 0);
761 else
0826874a 762 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
59c859d6 763
dbb02575
DV
764 if (IS_GEN2(dev))
765 connector->interlace_allowed = 0;
766 else
767 connector->interlace_allowed = 1;
79e53945
JB
768 connector->doublescan_allowed = 0;
769
df0323c4 770 if (HAS_PCH_SPLIT(dev))
540a8950
DV
771 crt->adpa_reg = PCH_ADPA;
772 else if (IS_VALLEYVIEW(dev))
773 crt->adpa_reg = VLV_ADPA;
df0323c4 774 else
540a8950
DV
775 crt->adpa_reg = ADPA;
776
2124604b
DV
777 crt->base.disable = intel_disable_crt;
778 crt->base.enable = intel_enable_crt;
affa9354 779 if (HAS_DDI(dev))
4eda01b2
PZ
780 crt->base.get_hw_state = intel_ddi_get_hw_state;
781 else
782 crt->base.get_hw_state = intel_crt_get_hw_state;
e403fc94 783 intel_connector->get_hw_state = intel_connector_get_hw_state;
df0323c4 784
b2cabb0e 785 drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
79e53945
JB
786 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
787
788 drm_sysfs_connector_add(connector);
b01f2c3a 789
eb1f8e4f
DA
790 if (I915_HAS_HOTPLUG(dev))
791 connector->polled = DRM_CONNECTOR_POLL_HPD;
792 else
793 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
794
e7dbb2f2
KP
795 /*
796 * Configure the automatic hotplug detection stuff
797 */
798 crt->force_hotplug_required = 0;
e7dbb2f2 799
b01f2c3a 800 dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
68d18ad7
PZ
801
802 /*
803 * TODO: find a proper way to discover whether we need to set the
804 * polarity reversal bit or not, instead of relying on the BIOS.
805 */
806 if (HAS_PCH_LPT(dev))
807 dev_priv->fdi_rx_polarity_reversed =
808 !!(I915_READ(_FDI_RXA_CTL) & FDI_RX_POLARITY_REVERSED_LPT);
79e53945 809}