Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 DH |
30 | #include <drm/drmP.h> |
31 | #include <drm/drm_crtc.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
33 | #include <drm/drm_edid.h> | |
79e53945 | 34 | #include "intel_drv.h" |
760285e7 | 35 | #include <drm/i915_drm.h> |
79e53945 JB |
36 | #include "i915_drv.h" |
37 | ||
e7dbb2f2 KP |
38 | /* Here's the desired hotplug mode */ |
39 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
40 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
41 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
42 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
43 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
44 | ADPA_CRT_HOTPLUG_ENABLE) | |
45 | ||
c9a1c4cd CW |
46 | struct intel_crt { |
47 | struct intel_encoder base; | |
637f44d2 AJ |
48 | /* DPMS state is stored in the connector, which we need in the |
49 | * encoder's enable/disable callbacks */ | |
50 | struct intel_connector *connector; | |
e7dbb2f2 | 51 | bool force_hotplug_required; |
540a8950 | 52 | u32 adpa_reg; |
c9a1c4cd CW |
53 | }; |
54 | ||
55 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) | |
56 | { | |
57 | return container_of(intel_attached_encoder(connector), | |
58 | struct intel_crt, base); | |
59 | } | |
60 | ||
540a8950 | 61 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
79e53945 | 62 | { |
540a8950 DV |
63 | return container_of(encoder, struct intel_crt, base); |
64 | } | |
65 | ||
e403fc94 DV |
66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
67 | enum pipe *pipe) | |
79e53945 | 68 | { |
e403fc94 | 69 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
e403fc94 DV |
71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
72 | u32 tmp; | |
73 | ||
74 | tmp = I915_READ(crt->adpa_reg); | |
75 | ||
76 | if (!(tmp & ADPA_DAC_ENABLE)) | |
77 | return false; | |
78 | ||
79 | if (HAS_PCH_CPT(dev)) | |
80 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
81 | else | |
82 | *pipe = PORT_TO_PIPE(tmp); | |
83 | ||
84 | return true; | |
85 | } | |
86 | ||
b2cabb0e DV |
87 | /* Note: The caller is required to filter out dpms modes not supported by the |
88 | * platform. */ | |
89 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) | |
df0323c4 | 90 | { |
b2cabb0e | 91 | struct drm_device *dev = encoder->base.dev; |
df0323c4 | 92 | struct drm_i915_private *dev_priv = dev->dev_private; |
b2cabb0e | 93 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
df0323c4 JB |
94 | u32 temp; |
95 | ||
b2cabb0e | 96 | temp = I915_READ(crt->adpa_reg); |
79e53945 | 97 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
febc7694 | 98 | temp &= ~ADPA_DAC_ENABLE; |
79e53945 | 99 | |
0206e353 | 100 | switch (mode) { |
79e53945 JB |
101 | case DRM_MODE_DPMS_ON: |
102 | temp |= ADPA_DAC_ENABLE; | |
103 | break; | |
104 | case DRM_MODE_DPMS_STANDBY: | |
105 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | |
106 | break; | |
107 | case DRM_MODE_DPMS_SUSPEND: | |
108 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | |
109 | break; | |
110 | case DRM_MODE_DPMS_OFF: | |
111 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | |
112 | break; | |
113 | } | |
114 | ||
b2cabb0e | 115 | I915_WRITE(crt->adpa_reg, temp); |
df0323c4 | 116 | } |
2c07245f | 117 | |
637f44d2 AJ |
118 | static void intel_disable_crt(struct intel_encoder *encoder) |
119 | { | |
120 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); | |
121 | } | |
122 | ||
123 | static void intel_enable_crt(struct intel_encoder *encoder) | |
124 | { | |
125 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
126 | ||
127 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); | |
128 | } | |
129 | ||
130 | ||
b2cabb0e | 131 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
df0323c4 | 132 | { |
b2cabb0e DV |
133 | struct drm_device *dev = connector->dev; |
134 | struct intel_encoder *encoder = intel_attached_encoder(connector); | |
135 | struct drm_crtc *crtc; | |
136 | int old_dpms; | |
79e53945 | 137 | |
b2cabb0e | 138 | /* PCH platforms and VLV only support on/off. */ |
4a8dece2 | 139 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
bd9e8413 JB |
140 | mode = DRM_MODE_DPMS_OFF; |
141 | ||
b2cabb0e DV |
142 | if (mode == connector->dpms) |
143 | return; | |
144 | ||
145 | old_dpms = connector->dpms; | |
146 | connector->dpms = mode; | |
147 | ||
148 | /* Only need to change hw state when actually enabled */ | |
149 | crtc = encoder->base.crtc; | |
150 | if (!crtc) { | |
151 | encoder->connectors_active = false; | |
152 | return; | |
79e53945 JB |
153 | } |
154 | ||
b2cabb0e DV |
155 | /* We need the pipe to run for anything but OFF. */ |
156 | if (mode == DRM_MODE_DPMS_OFF) | |
157 | encoder->connectors_active = false; | |
158 | else | |
159 | encoder->connectors_active = true; | |
160 | ||
161 | if (mode < old_dpms) { | |
162 | /* From off to on, enable the pipe first. */ | |
163 | intel_crtc_update_dpms(crtc); | |
164 | ||
165 | intel_crt_set_dpms(encoder, mode); | |
166 | } else { | |
167 | intel_crt_set_dpms(encoder, mode); | |
168 | ||
169 | intel_crtc_update_dpms(crtc); | |
170 | } | |
0a91ca29 | 171 | |
b980514c | 172 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
173 | } |
174 | ||
175 | static int intel_crt_mode_valid(struct drm_connector *connector, | |
176 | struct drm_display_mode *mode) | |
177 | { | |
6bcdcd9e ZY |
178 | struct drm_device *dev = connector->dev; |
179 | ||
180 | int max_clock = 0; | |
79e53945 JB |
181 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
182 | return MODE_NO_DBLESCAN; | |
183 | ||
6bcdcd9e ZY |
184 | if (mode->clock < 25000) |
185 | return MODE_CLOCK_LOW; | |
186 | ||
a6c45cf0 | 187 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
188 | max_clock = 350000; |
189 | else | |
190 | max_clock = 400000; | |
191 | if (mode->clock > max_clock) | |
192 | return MODE_CLOCK_HIGH; | |
79e53945 | 193 | |
d4b1931c PZ |
194 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
195 | if (HAS_PCH_LPT(dev) && | |
196 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) | |
197 | return MODE_CLOCK_HIGH; | |
198 | ||
79e53945 JB |
199 | return MODE_OK; |
200 | } | |
201 | ||
5bfe2ac0 DV |
202 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
203 | struct intel_crtc_config *pipe_config) | |
79e53945 | 204 | { |
5bfe2ac0 DV |
205 | struct drm_device *dev = encoder->base.dev; |
206 | ||
207 | if (HAS_PCH_SPLIT(dev)) | |
208 | pipe_config->has_pch_encoder = true; | |
209 | ||
2a7aceec DV |
210 | /* LPT FDI RX only supports 8bpc. */ |
211 | if (HAS_PCH_LPT(dev)) | |
212 | pipe_config->pipe_bpp = 24; | |
213 | ||
79e53945 JB |
214 | return true; |
215 | } | |
216 | ||
217 | static void intel_crt_mode_set(struct drm_encoder *encoder, | |
218 | struct drm_display_mode *mode, | |
219 | struct drm_display_mode *adjusted_mode) | |
220 | { | |
221 | ||
222 | struct drm_device *dev = encoder->dev; | |
223 | struct drm_crtc *crtc = encoder->crtc; | |
540a8950 DV |
224 | struct intel_crt *crt = |
225 | intel_encoder_to_crt(to_intel_encoder(encoder)); | |
79e53945 JB |
226 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6478d414 | 228 | u32 adpa; |
79e53945 | 229 | |
912d812e DV |
230 | if (HAS_PCH_SPLIT(dev)) |
231 | adpa = ADPA_HOTPLUG_BITS; | |
232 | else | |
233 | adpa = 0; | |
234 | ||
79e53945 JB |
235 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
236 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
237 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
238 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
239 | ||
75770564 | 240 | /* For CPT allow 3 pipe config, for others just use A or B */ |
4837813a PZ |
241 | if (HAS_PCH_LPT(dev)) |
242 | ; /* Those bits don't exist here */ | |
243 | else if (HAS_PCH_CPT(dev)) | |
75770564 JB |
244 | adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
245 | else if (intel_crtc->pipe == 0) | |
246 | adpa |= ADPA_PIPE_A_SELECT; | |
247 | else | |
248 | adpa |= ADPA_PIPE_B_SELECT; | |
79e53945 | 249 | |
9db4a9c7 JB |
250 | if (!HAS_PCH_SPLIT(dev)) |
251 | I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); | |
252 | ||
540a8950 | 253 | I915_WRITE(crt->adpa_reg, adpa); |
2c07245f ZW |
254 | } |
255 | ||
f2b115e6 | 256 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
257 | { |
258 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 259 | struct intel_crt *crt = intel_attached_crt(connector); |
2c07245f | 260 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7dbb2f2 | 261 | u32 adpa; |
2c07245f ZW |
262 | bool ret; |
263 | ||
e7dbb2f2 KP |
264 | /* The first time through, trigger an explicit detection cycle */ |
265 | if (crt->force_hotplug_required) { | |
266 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
267 | u32 save_adpa; | |
67941da2 | 268 | |
e7dbb2f2 KP |
269 | crt->force_hotplug_required = 0; |
270 | ||
ca54b810 | 271 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
272 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
273 | ||
274 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
275 | if (turn_off_dac) | |
276 | adpa &= ~ADPA_DAC_ENABLE; | |
277 | ||
ca54b810 | 278 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 279 | |
ca54b810 | 280 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
e7dbb2f2 KP |
281 | 1000)) |
282 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
283 | ||
284 | if (turn_off_dac) { | |
ca54b810 VS |
285 | I915_WRITE(crt->adpa_reg, save_adpa); |
286 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 287 | } |
a4a6b901 ZW |
288 | } |
289 | ||
2c07245f | 290 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 291 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 292 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
293 | ret = true; |
294 | else | |
295 | ret = false; | |
e7dbb2f2 | 296 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 297 | |
2c07245f | 298 | return ret; |
79e53945 JB |
299 | } |
300 | ||
7d2c24e8 JB |
301 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
302 | { | |
303 | struct drm_device *dev = connector->dev; | |
ca54b810 | 304 | struct intel_crt *crt = intel_attached_crt(connector); |
7d2c24e8 JB |
305 | struct drm_i915_private *dev_priv = dev->dev_private; |
306 | u32 adpa; | |
307 | bool ret; | |
308 | u32 save_adpa; | |
309 | ||
ca54b810 | 310 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
311 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
312 | ||
313 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
314 | ||
ca54b810 | 315 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 316 | |
ca54b810 | 317 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
7d2c24e8 JB |
318 | 1000)) { |
319 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
ca54b810 | 320 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
321 | } |
322 | ||
323 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 324 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
325 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
326 | ret = true; | |
327 | else | |
328 | ret = false; | |
329 | ||
330 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
331 | ||
332 | /* FIXME: debug force function and remove */ | |
333 | ret = true; | |
334 | ||
335 | return ret; | |
336 | } | |
337 | ||
79e53945 JB |
338 | /** |
339 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
340 | * | |
341 | * Not for i915G/i915GM | |
342 | * | |
343 | * \return true if CRT is connected. | |
344 | * \return false if CRT is disconnected. | |
345 | */ | |
346 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
347 | { | |
348 | struct drm_device *dev = connector->dev; | |
349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a772c49 AJ |
350 | u32 hotplug_en, orig, stat; |
351 | bool ret = false; | |
771cb081 | 352 | int i, tries = 0; |
2c07245f | 353 | |
bad720ff | 354 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 355 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 356 | |
7d2c24e8 JB |
357 | if (IS_VALLEYVIEW(dev)) |
358 | return valleyview_crt_detect_hotplug(connector); | |
359 | ||
771cb081 ZY |
360 | /* |
361 | * On 4 series desktop, CRT detect sequence need to be done twice | |
362 | * to get a reliable result. | |
363 | */ | |
79e53945 | 364 | |
771cb081 ZY |
365 | if (IS_G4X(dev) && !IS_GM45(dev)) |
366 | tries = 2; | |
367 | else | |
368 | tries = 1; | |
7a772c49 | 369 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
771cb081 ZY |
370 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
371 | ||
771cb081 | 372 | for (i = 0; i < tries ; i++) { |
771cb081 ZY |
373 | /* turn on the FORCE_DETECT */ |
374 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
771cb081 | 375 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
376 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
377 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 378 | 1000)) |
79077319 | 379 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 380 | } |
79e53945 | 381 | |
7a772c49 AJ |
382 | stat = I915_READ(PORT_HOTPLUG_STAT); |
383 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
384 | ret = true; | |
385 | ||
386 | /* clear the interrupt we just generated, if any */ | |
387 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 388 | |
7a772c49 AJ |
389 | /* and put the bits back */ |
390 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
391 | ||
392 | return ret; | |
79e53945 JB |
393 | } |
394 | ||
f1a2f5b7 JN |
395 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
396 | struct i2c_adapter *i2c) | |
397 | { | |
398 | struct edid *edid; | |
399 | ||
400 | edid = drm_get_edid(connector, i2c); | |
401 | ||
402 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
403 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
404 | intel_gmbus_force_bit(i2c, true); | |
405 | edid = drm_get_edid(connector, i2c); | |
406 | intel_gmbus_force_bit(i2c, false); | |
407 | } | |
408 | ||
409 | return edid; | |
410 | } | |
411 | ||
412 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
413 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
414 | struct i2c_adapter *adapter) | |
415 | { | |
416 | struct edid *edid; | |
ebda95a9 | 417 | int ret; |
f1a2f5b7 JN |
418 | |
419 | edid = intel_crt_get_edid(connector, adapter); | |
420 | if (!edid) | |
421 | return 0; | |
422 | ||
ebda95a9 JN |
423 | ret = intel_connector_update_modes(connector, edid); |
424 | kfree(edid); | |
425 | ||
426 | return ret; | |
f1a2f5b7 JN |
427 | } |
428 | ||
f5afcd3d | 429 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 430 | { |
f5afcd3d | 431 | struct intel_crt *crt = intel_attached_crt(connector); |
c9a1c4cd | 432 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
a2bd1f54 DV |
433 | struct edid *edid; |
434 | struct i2c_adapter *i2c; | |
79e53945 | 435 | |
a2bd1f54 | 436 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 437 | |
41aa3448 | 438 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 439 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
440 | |
441 | if (edid) { | |
442 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 443 | |
f5afcd3d DM |
444 | /* |
445 | * This may be a DVI-I connector with a shared DDC | |
446 | * link between analog and digital outputs, so we | |
447 | * have to check the EDID input spec of the attached device. | |
448 | */ | |
f5afcd3d DM |
449 | if (!is_digital) { |
450 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
451 | return true; | |
452 | } | |
a2bd1f54 DV |
453 | |
454 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
455 | } else { | |
456 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
457 | } |
458 | ||
a2bd1f54 DV |
459 | kfree(edid); |
460 | ||
6ec3d0c0 | 461 | return false; |
79e53945 JB |
462 | } |
463 | ||
e4a5d54f | 464 | static enum drm_connector_status |
7173188d | 465 | intel_crt_load_detect(struct intel_crt *crt) |
e4a5d54f | 466 | { |
7173188d | 467 | struct drm_device *dev = crt->base.base.dev; |
e4a5d54f | 468 | struct drm_i915_private *dev_priv = dev->dev_private; |
7173188d | 469 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
e4a5d54f ML |
470 | uint32_t save_bclrpat; |
471 | uint32_t save_vtotal; | |
472 | uint32_t vtotal, vactive; | |
473 | uint32_t vsample; | |
474 | uint32_t vblank, vblank_start, vblank_end; | |
475 | uint32_t dsl; | |
476 | uint32_t bclrpat_reg; | |
477 | uint32_t vtotal_reg; | |
478 | uint32_t vblank_reg; | |
479 | uint32_t vsync_reg; | |
480 | uint32_t pipeconf_reg; | |
481 | uint32_t pipe_dsl_reg; | |
482 | uint8_t st00; | |
483 | enum drm_connector_status status; | |
484 | ||
6ec3d0c0 CW |
485 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
486 | ||
9db4a9c7 JB |
487 | bclrpat_reg = BCLRPAT(pipe); |
488 | vtotal_reg = VTOTAL(pipe); | |
489 | vblank_reg = VBLANK(pipe); | |
490 | vsync_reg = VSYNC(pipe); | |
491 | pipeconf_reg = PIPECONF(pipe); | |
492 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
493 | |
494 | save_bclrpat = I915_READ(bclrpat_reg); | |
495 | save_vtotal = I915_READ(vtotal_reg); | |
496 | vblank = I915_READ(vblank_reg); | |
497 | ||
498 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
499 | vactive = (save_vtotal & 0x7ff) + 1; | |
500 | ||
501 | vblank_start = (vblank & 0xfff) + 1; | |
502 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
503 | ||
504 | /* Set the border color to purple. */ | |
505 | I915_WRITE(bclrpat_reg, 0x500050); | |
506 | ||
a6c45cf0 | 507 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
508 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
509 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 510 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
511 | /* Wait for next Vblank to substitue |
512 | * border color for Color info */ | |
9d0498a2 | 513 | intel_wait_for_vblank(dev, pipe); |
e4a5d54f ML |
514 | st00 = I915_READ8(VGA_MSR_WRITE); |
515 | status = ((st00 & (1 << 4)) != 0) ? | |
516 | connector_status_connected : | |
517 | connector_status_disconnected; | |
518 | ||
519 | I915_WRITE(pipeconf_reg, pipeconf); | |
520 | } else { | |
521 | bool restore_vblank = false; | |
522 | int count, detect; | |
523 | ||
524 | /* | |
525 | * If there isn't any border, add some. | |
526 | * Yes, this will flicker | |
527 | */ | |
528 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
529 | uint32_t vsync = I915_READ(vsync_reg); | |
530 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
531 | ||
532 | vblank_start = vsync_start; | |
533 | I915_WRITE(vblank_reg, | |
534 | (vblank_start - 1) | | |
535 | ((vblank_end - 1) << 16)); | |
536 | restore_vblank = true; | |
537 | } | |
538 | /* sample in the vertical border, selecting the larger one */ | |
539 | if (vblank_start - vactive >= vtotal - vblank_end) | |
540 | vsample = (vblank_start + vactive) >> 1; | |
541 | else | |
542 | vsample = (vtotal + vblank_end) >> 1; | |
543 | ||
544 | /* | |
545 | * Wait for the border to be displayed | |
546 | */ | |
547 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
548 | ; | |
549 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
550 | ; | |
551 | /* | |
552 | * Watch ST00 for an entire scanline | |
553 | */ | |
554 | detect = 0; | |
555 | count = 0; | |
556 | do { | |
557 | count++; | |
558 | /* Read the ST00 VGA status register */ | |
559 | st00 = I915_READ8(VGA_MSR_WRITE); | |
560 | if (st00 & (1 << 4)) | |
561 | detect++; | |
562 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
563 | ||
564 | /* restore vblank if necessary */ | |
565 | if (restore_vblank) | |
566 | I915_WRITE(vblank_reg, vblank); | |
567 | /* | |
568 | * If more than 3/4 of the scanline detected a monitor, | |
569 | * then it is assumed to be present. This works even on i830, | |
570 | * where there isn't any way to force the border color across | |
571 | * the screen | |
572 | */ | |
573 | status = detect * 4 > count * 3 ? | |
574 | connector_status_connected : | |
575 | connector_status_disconnected; | |
576 | } | |
577 | ||
578 | /* Restore previous settings */ | |
579 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
580 | ||
581 | return status; | |
582 | } | |
583 | ||
7b334fcb | 584 | static enum drm_connector_status |
930a9e28 | 585 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
586 | { |
587 | struct drm_device *dev = connector->dev; | |
c9a1c4cd | 588 | struct intel_crt *crt = intel_attached_crt(connector); |
e4a5d54f | 589 | enum drm_connector_status status; |
e95c8438 | 590 | struct intel_load_detect_pipe tmp; |
79e53945 | 591 | |
a6c45cf0 | 592 | if (I915_HAS_HOTPLUG(dev)) { |
aaa37730 DV |
593 | /* We can not rely on the HPD pin always being correctly wired |
594 | * up, for example many KVM do not pass it through, and so | |
595 | * only trust an assertion that the monitor is connected. | |
596 | */ | |
6ec3d0c0 CW |
597 | if (intel_crt_detect_hotplug(connector)) { |
598 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
79e53945 | 599 | return connector_status_connected; |
aaa37730 | 600 | } else |
e7dbb2f2 | 601 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
602 | } |
603 | ||
f5afcd3d | 604 | if (intel_crt_detect_ddc(connector)) |
79e53945 JB |
605 | return connector_status_connected; |
606 | ||
aaa37730 DV |
607 | /* Load detection is broken on HPD capable machines. Whoever wants a |
608 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
609 | * to have the right resistors for HP detection) needs to fix this up. | |
610 | * For now just bail out. */ | |
611 | if (I915_HAS_HOTPLUG(dev)) | |
612 | return connector_status_disconnected; | |
613 | ||
930a9e28 | 614 | if (!force) |
7b334fcb CW |
615 | return connector->status; |
616 | ||
e4a5d54f | 617 | /* for pre-945g platforms use load detect */ |
d2434ab7 | 618 | if (intel_get_load_detect_pipe(connector, NULL, &tmp)) { |
e95c8438 DV |
619 | if (intel_crt_detect_ddc(connector)) |
620 | status = connector_status_connected; | |
621 | else | |
622 | status = intel_crt_load_detect(crt); | |
d2434ab7 | 623 | intel_release_load_detect_pipe(connector, &tmp); |
e95c8438 DV |
624 | } else |
625 | status = connector_status_unknown; | |
e4a5d54f ML |
626 | |
627 | return status; | |
79e53945 JB |
628 | } |
629 | ||
630 | static void intel_crt_destroy(struct drm_connector *connector) | |
631 | { | |
79e53945 JB |
632 | drm_sysfs_connector_remove(connector); |
633 | drm_connector_cleanup(connector); | |
634 | kfree(connector); | |
635 | } | |
636 | ||
637 | static int intel_crt_get_modes(struct drm_connector *connector) | |
638 | { | |
8e4d36b9 | 639 | struct drm_device *dev = connector->dev; |
f899fc64 | 640 | struct drm_i915_private *dev_priv = dev->dev_private; |
890f3359 | 641 | int ret; |
3bd7d909 | 642 | struct i2c_adapter *i2c; |
8e4d36b9 | 643 | |
41aa3448 | 644 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 645 | ret = intel_crt_ddc_get_modes(connector, i2c); |
8e4d36b9 | 646 | if (ret || !IS_G4X(dev)) |
f899fc64 | 647 | return ret; |
8e4d36b9 | 648 | |
8e4d36b9 | 649 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
3bd7d909 | 650 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
f1a2f5b7 | 651 | return intel_crt_ddc_get_modes(connector, i2c); |
79e53945 JB |
652 | } |
653 | ||
654 | static int intel_crt_set_property(struct drm_connector *connector, | |
655 | struct drm_property *property, | |
656 | uint64_t value) | |
657 | { | |
79e53945 JB |
658 | return 0; |
659 | } | |
660 | ||
f3269058 CW |
661 | static void intel_crt_reset(struct drm_connector *connector) |
662 | { | |
663 | struct drm_device *dev = connector->dev; | |
2e938892 | 664 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3269058 CW |
665 | struct intel_crt *crt = intel_attached_crt(connector); |
666 | ||
2e938892 DV |
667 | if (HAS_PCH_SPLIT(dev)) { |
668 | u32 adpa; | |
669 | ||
ca54b810 | 670 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
671 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
672 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
673 | I915_WRITE(crt->adpa_reg, adpa); |
674 | POSTING_READ(crt->adpa_reg); | |
2e938892 DV |
675 | |
676 | DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa); | |
f3269058 | 677 | crt->force_hotplug_required = 1; |
2e938892 DV |
678 | } |
679 | ||
f3269058 CW |
680 | } |
681 | ||
79e53945 JB |
682 | /* |
683 | * Routines for controlling stuff on the analog port | |
684 | */ | |
685 | ||
b2cabb0e | 686 | static const struct drm_encoder_helper_funcs crt_encoder_funcs = { |
df0323c4 | 687 | .mode_set = intel_crt_mode_set, |
79e53945 JB |
688 | }; |
689 | ||
690 | static const struct drm_connector_funcs intel_crt_connector_funcs = { | |
f3269058 | 691 | .reset = intel_crt_reset, |
b2cabb0e | 692 | .dpms = intel_crt_dpms, |
79e53945 JB |
693 | .detect = intel_crt_detect, |
694 | .fill_modes = drm_helper_probe_single_connector_modes, | |
695 | .destroy = intel_crt_destroy, | |
696 | .set_property = intel_crt_set_property, | |
697 | }; | |
698 | ||
699 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
700 | .mode_valid = intel_crt_mode_valid, | |
701 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 702 | .best_encoder = intel_best_encoder, |
79e53945 JB |
703 | }; |
704 | ||
79e53945 | 705 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 706 | .destroy = intel_encoder_destroy, |
79e53945 JB |
707 | }; |
708 | ||
8ca4013d DL |
709 | static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
710 | { | |
bc0daf48 | 711 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
712 | return 1; |
713 | } | |
714 | ||
715 | static const struct dmi_system_id intel_no_crt[] = { | |
716 | { | |
717 | .callback = intel_no_crt_dmi_callback, | |
718 | .ident = "ACER ZGB", | |
719 | .matches = { | |
720 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
721 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
722 | }, | |
723 | }, | |
724 | { } | |
725 | }; | |
726 | ||
79e53945 JB |
727 | void intel_crt_init(struct drm_device *dev) |
728 | { | |
729 | struct drm_connector *connector; | |
c9a1c4cd | 730 | struct intel_crt *crt; |
454c1ca8 | 731 | struct intel_connector *intel_connector; |
db545019 | 732 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 733 | |
8ca4013d DL |
734 | /* Skip machines without VGA that falsely report hotplug events */ |
735 | if (dmi_check_system(intel_no_crt)) | |
736 | return; | |
737 | ||
c9a1c4cd CW |
738 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
739 | if (!crt) | |
79e53945 JB |
740 | return; |
741 | ||
454c1ca8 ZW |
742 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
743 | if (!intel_connector) { | |
c9a1c4cd | 744 | kfree(crt); |
454c1ca8 ZW |
745 | return; |
746 | } | |
747 | ||
748 | connector = &intel_connector->base; | |
637f44d2 | 749 | crt->connector = intel_connector; |
454c1ca8 | 750 | drm_connector_init(dev, &intel_connector->base, |
79e53945 JB |
751 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
752 | ||
c9a1c4cd | 753 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
79e53945 JB |
754 | DRM_MODE_ENCODER_DAC); |
755 | ||
c9a1c4cd | 756 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 757 | |
c9a1c4cd | 758 | crt->base.type = INTEL_OUTPUT_ANALOG; |
66a9278e | 759 | crt->base.cloneable = true; |
d63fa0dc | 760 | if (IS_I830(dev)) |
59c859d6 ED |
761 | crt->base.crtc_mask = (1 << 0); |
762 | else | |
0826874a | 763 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 764 | |
dbb02575 DV |
765 | if (IS_GEN2(dev)) |
766 | connector->interlace_allowed = 0; | |
767 | else | |
768 | connector->interlace_allowed = 1; | |
79e53945 JB |
769 | connector->doublescan_allowed = 0; |
770 | ||
df0323c4 | 771 | if (HAS_PCH_SPLIT(dev)) |
540a8950 DV |
772 | crt->adpa_reg = PCH_ADPA; |
773 | else if (IS_VALLEYVIEW(dev)) | |
774 | crt->adpa_reg = VLV_ADPA; | |
df0323c4 | 775 | else |
540a8950 DV |
776 | crt->adpa_reg = ADPA; |
777 | ||
5bfe2ac0 | 778 | crt->base.compute_config = intel_crt_compute_config; |
2124604b DV |
779 | crt->base.disable = intel_disable_crt; |
780 | crt->base.enable = intel_enable_crt; | |
1d843f9d EE |
781 | if (I915_HAS_HOTPLUG(dev)) |
782 | crt->base.hpd_pin = HPD_CRT; | |
affa9354 | 783 | if (HAS_DDI(dev)) |
4eda01b2 PZ |
784 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
785 | else | |
786 | crt->base.get_hw_state = intel_crt_get_hw_state; | |
e403fc94 | 787 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
df0323c4 | 788 | |
b2cabb0e | 789 | drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs); |
79e53945 JB |
790 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
791 | ||
792 | drm_sysfs_connector_add(connector); | |
b01f2c3a | 793 | |
821450c6 EE |
794 | if (!I915_HAS_HOTPLUG(dev)) |
795 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
eb1f8e4f | 796 | |
e7dbb2f2 KP |
797 | /* |
798 | * Configure the automatic hotplug detection stuff | |
799 | */ | |
800 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 801 | |
68d18ad7 | 802 | /* |
3e68320e DL |
803 | * TODO: find a proper way to discover whether we need to set the the |
804 | * polarity and link reversal bits or not, instead of relying on the | |
805 | * BIOS. | |
68d18ad7 | 806 | */ |
3e68320e DL |
807 | if (HAS_PCH_LPT(dev)) { |
808 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | | |
809 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
810 | ||
811 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; | |
812 | } | |
79e53945 | 813 | } |