[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_crt.c

/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "drm_edid.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

/* Here's the desired hotplug mode */
#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |		\
			   ADPA_CRT_HOTPLUG_WARMUP_10MS |		\
			   ADPA_CRT_HOTPLUG_SAMPLE_4S |			\
			   ADPA_CRT_HOTPLUG_VOLTAGE_50 |		\
			   ADPA_CRT_HOTPLUG_VOLREF_325MV |		\
			   ADPA_CRT_HOTPLUG_ENABLE)

struct intel_crt {
	struct intel_encoder base;
	bool force_hotplug_required;
};

static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_crt, base);
}

static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 temp, reg;

	if (HAS_PCH_SPLIT(dev))
		reg = PCH_ADPA;
	else
		reg = ADPA;

	temp = I915_READ(reg);
	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
	temp &= ~ADPA_DAC_ENABLE;

	switch(mode) {
	case DRM_MODE_DPMS_ON:
		temp |= ADPA_DAC_ENABLE;
		break;
	case DRM_MODE_DPMS_STANDBY:
		temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_SUSPEND:
		temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_OFF:
		temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	}

	I915_WRITE(reg, temp);
}

static int intel_crt_mode_valid(struct drm_connector *connector,
				struct drm_display_mode *mode)
{
	struct drm_device *dev = connector->dev;

	int max_clock = 0;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	if (mode->clock < 25000)
		return MODE_CLOCK_LOW;

	if (IS_GEN2(dev))
		max_clock = 350000;
	else
		max_clock = 400000;
	if (mode->clock > max_clock)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
				 struct drm_display_mode *mode,
				 struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void intel_crt_mode_set(struct drm_encoder *encoder,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode)
{

	struct drm_device *dev = encoder->dev;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_i915_private *dev_priv = dev->dev_private;
	int dpll_md_reg;
	u32 adpa, dpll_md;
	u32 adpa_reg;

	dpll_md_reg = DPLL_MD(intel_crtc->pipe);

	if (HAS_PCH_SPLIT(dev))
		adpa_reg = PCH_ADPA;
	else
		adpa_reg = ADPA;

	/*
	 * Disable separate mode multiplier used when cloning SDVO to CRT
	 * XXX this needs to be adjusted when we really are cloning
	 */
	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
		dpll_md = I915_READ(dpll_md_reg);
		I915_WRITE(dpll_md_reg,
			   dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
	}

	adpa = ADPA_HOTPLUG_BITS;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		adpa |= ADPA_VSYNC_ACTIVE_HIGH;

	if (intel_crtc->pipe == 0) {
		if (HAS_PCH_CPT(dev))
			adpa |= PORT_TRANS_A_SEL_CPT;
		else
			adpa |= ADPA_PIPE_A_SELECT;
	} else {
		if (HAS_PCH_CPT(dev))
			adpa |= PORT_TRANS_B_SEL_CPT;
		else
			adpa |= ADPA_PIPE_B_SELECT;
	}

	if (!HAS_PCH_SPLIT(dev))
		I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);

	I915_WRITE(adpa_reg, adpa);
}

static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 adpa;
	bool ret;

	/* The first time through, trigger an explicit detection cycle */
	if (crt->force_hotplug_required) {
		bool turn_off_dac = HAS_PCH_SPLIT(dev);
		u32 save_adpa;

		crt->force_hotplug_required = 0;

		save_adpa = adpa = I915_READ(PCH_ADPA);
		DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);

		adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
		if (turn_off_dac)
			adpa &= ~ADPA_DAC_ENABLE;

		I915_WRITE(PCH_ADPA, adpa);

		if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
			     1000))
			DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");

		if (turn_off_dac) {
			I915_WRITE(PCH_ADPA, save_adpa);
			POSTING_READ(PCH_ADPA);
		}
	}

	/* Check the status to see if both blue and green are on now */
	adpa = I915_READ(PCH_ADPA);
	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
		ret = true;
	else
		ret = false;
	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);

	return ret;
}

/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 *
 * Not for i915G/i915GM
 *
 * \return true if CRT is connected.
 * \return false if CRT is disconnected.
 */
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_en, orig, stat;
	bool ret = false;
	int i, tries = 0;

	if (HAS_PCH_SPLIT(dev))
		return intel_ironlake_crt_detect_hotplug(connector);

	/*
	 * On 4 series desktop, CRT detect sequence need to be done twice
	 * to get a reliable result.
	 */

	if (IS_G4X(dev) && !IS_GM45(dev))
		tries = 2;
	else
		tries = 1;
	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
	hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;

	for (i = 0; i < tries ; i++) {
		/* turn on the FORCE_DETECT */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
		/* wait for FORCE_DETECT to go off */
		if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
			      CRT_HOTPLUG_FORCE_DETECT) == 0,
			     1000))
			DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
	}

	stat = I915_READ(PORT_HOTPLUG_STAT);
	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
		ret = true;

	/* clear the interrupt we just generated, if any */
	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);

	/* and put the bits back */
	I915_WRITE(PORT_HOTPLUG_EN, orig);

	return ret;
}

static bool intel_crt_detect_ddc(struct drm_connector *connector)
{
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;

	/* CRT should always be at 0, but check anyway */
	if (crt->base.type != INTEL_OUTPUT_ANALOG)
		return false;

	if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
		struct edid *edid;
		bool is_digital = false;

		edid = drm_get_edid(connector,
			&dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
		/*
		 * This may be a DVI-I connector with a shared DDC
		 * link between analog and digital outputs, so we
		 * have to check the EDID input spec of the attached device.
		 *
		 * On the other hand, what should we do if it is a broken EDID?
		 */
		if (edid != NULL) {
			is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
			connector->display_info.raw_edid = NULL;
			kfree(edid);
		}

		if (!is_digital) {
			DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
			return true;
		} else {
			DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
		}
	}

	return false;
}

static enum drm_connector_status
intel_crt_load_detect(struct intel_crt *crt)
{
	struct drm_device *dev = crt->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
	uint32_t save_bclrpat;
	uint32_t save_vtotal;
	uint32_t vtotal, vactive;
	uint32_t vsample;
	uint32_t vblank, vblank_start, vblank_end;
	uint32_t dsl;
	uint32_t bclrpat_reg;
	uint32_t vtotal_reg;
	uint32_t vblank_reg;
	uint32_t vsync_reg;
	uint32_t pipeconf_reg;
	uint32_t pipe_dsl_reg;
	uint8_t	st00;
	enum drm_connector_status status;

	DRM_DEBUG_KMS("starting load-detect on CRT\n");

	bclrpat_reg = BCLRPAT(pipe);
	vtotal_reg = VTOTAL(pipe);
	vblank_reg = VBLANK(pipe);
	vsync_reg = VSYNC(pipe);
	pipeconf_reg = PIPECONF(pipe);
	pipe_dsl_reg = PIPEDSL(pipe);

	save_bclrpat = I915_READ(bclrpat_reg);
	save_vtotal = I915_READ(vtotal_reg);
	vblank = I915_READ(vblank_reg);

	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	vactive = (save_vtotal & 0x7ff) + 1;

	vblank_start = (vblank & 0xfff) + 1;
	vblank_end = ((vblank >> 16) & 0xfff) + 1;

	/* Set the border color to purple. */
	I915_WRITE(bclrpat_reg, 0x500050);

	if (!IS_GEN2(dev)) {
		uint32_t pipeconf = I915_READ(pipeconf_reg);
		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
		POSTING_READ(pipeconf_reg);
		/* Wait for next Vblank to substitue
		 * border color for Color info */
		intel_wait_for_vblank(dev, pipe);
		st00 = I915_READ8(VGA_MSR_WRITE);
		status = ((st00 & (1 << 4)) != 0) ?
			connector_status_connected :
			connector_status_disconnected;

		I915_WRITE(pipeconf_reg, pipeconf);
	} else {
		bool restore_vblank = false;
		int count, detect;

		/*
		* If there isn't any border, add some.
		* Yes, this will flicker
		*/
		if (vblank_start <= vactive && vblank_end >= vtotal) {
			uint32_t vsync = I915_READ(vsync_reg);
			uint32_t vsync_start = (vsync & 0xffff) + 1;

			vblank_start = vsync_start;
			I915_WRITE(vblank_reg,
				   (vblank_start - 1) |
				   ((vblank_end - 1) << 16));
			restore_vblank = true;
		}
		/* sample in the vertical border, selecting the larger one */
		if (vblank_start - vactive >= vtotal - vblank_end)
			vsample = (vblank_start + vactive) >> 1;
		else
			vsample = (vtotal + vblank_end) >> 1;

		/*
		 * Wait for the border to be displayed
		 */
		while (I915_READ(pipe_dsl_reg) >= vactive)
			;
		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
			;
		/*
		 * Watch ST00 for an entire scanline
		 */
		detect = 0;
		count = 0;
		do {
			count++;
			/* Read the ST00 VGA status register */
			st00 = I915_READ8(VGA_MSR_WRITE);
			if (st00 & (1 << 4))
				detect++;
		} while ((I915_READ(pipe_dsl_reg) == dsl));

		/* restore vblank if necessary */
		if (restore_vblank)
			I915_WRITE(vblank_reg, vblank);
		/*
		 * If more than 3/4 of the scanline detected a monitor,
		 * then it is assumed to be present. This works even on i830,
		 * where there isn't any way to force the border color across
		 * the screen
		 */
		status = detect * 4 > count * 3 ?
			 connector_status_connected :
			 connector_status_disconnected;
	}

	/* Restore previous settings */
	I915_WRITE(bclrpat_reg, save_bclrpat);

	return status;
}

static enum drm_connector_status
intel_crt_detect(struct drm_connector *connector, bool force)
{
	struct drm_device *dev = connector->dev;
	struct intel_crt *crt = intel_attached_crt(connector);
	struct drm_crtc *crtc;
	enum drm_connector_status status;

	if (I915_HAS_HOTPLUG(dev)) {
		if (intel_crt_detect_hotplug(connector)) {
			DRM_DEBUG_KMS("CRT detected via hotplug\n");
			return connector_status_connected;
		} else {
			DRM_DEBUG_KMS("CRT not detected via hotplug\n");
			return connector_status_disconnected;
		}
	}

	if (intel_crt_detect_ddc(connector))
		return connector_status_connected;

	if (!force)
		return connector->status;

	/* for pre-945g platforms use load detect */
	crtc = crt->base.base.crtc;
	if (crtc && crtc->enabled) {
		status = intel_crt_load_detect(crt);
	} else {
		struct intel_load_detect_pipe tmp;

		if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
					       &tmp)) {
			if (intel_crt_detect_ddc(connector))
				status = connector_status_connected;
			else
				status = intel_crt_load_detect(crt);
			intel_release_load_detect_pipe(&crt->base, connector,
						       &tmp);
		} else
			status = connector_status_unknown;
	}

	return status;
}

static void intel_crt_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

static int intel_crt_get_modes(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	ret = intel_ddc_get_modes(connector,
				 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
	if (ret || !IS_G4X(dev))
		return ret;

	/* Try to probe digital port for output in DVI-I -> VGA mode. */
	return intel_ddc_get_modes(connector,
				   &dev_priv->gmbus[GMBUS_PORT_DPB].adapter);
}

static int intel_crt_set_property(struct drm_connector *connector,
				  struct drm_property *property,
				  uint64_t value)
{
	return 0;
}

static void intel_crt_reset(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct intel_crt *crt = intel_attached_crt(connector);

	if (HAS_PCH_SPLIT(dev))
		crt->force_hotplug_required = 1;
}

/*
 * Routines for controlling stuff on the analog port
 */

static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
	.dpms = intel_crt_dpms,
	.mode_fixup = intel_crt_mode_fixup,
	.prepare = intel_encoder_prepare,
	.commit = intel_encoder_commit,
	.mode_set = intel_crt_mode_set,
};

static const struct drm_connector_funcs intel_crt_connector_funcs = {
	.reset = intel_crt_reset,
	.dpms = drm_helper_connector_dpms,
	.detect = intel_crt_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = intel_crt_destroy,
	.set_property = intel_crt_set_property,
};

static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	.mode_valid = intel_crt_mode_valid,
	.get_modes = intel_crt_get_modes,
	.best_encoder = intel_best_encoder,
};

static const struct drm_encoder_funcs intel_crt_enc_funcs = {
	.destroy = intel_encoder_destroy,
};

void intel_crt_init(struct drm_device *dev)
{
	struct drm_connector *connector;
	struct intel_crt *crt;
	struct intel_connector *intel_connector;
	struct drm_i915_private *dev_priv = dev->dev_private;

	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
	if (!crt)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(crt);
		return;
	}

	connector = &intel_connector->base;
	drm_connector_init(dev, &intel_connector->base,
			   &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);

	drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
			 DRM_MODE_ENCODER_DAC);

	intel_connector_attach_encoder(intel_connector, &crt->base);

	crt->base.type = INTEL_OUTPUT_ANALOG;
	crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT |
				1 << INTEL_ANALOG_CLONE_BIT |
				1 << INTEL_SDVO_LVDS_CLONE_BIT);
	crt->base.crtc_mask = (1 << 0) | (1 << 1);
	connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;

	drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);

	drm_sysfs_connector_add(connector);

	if (I915_HAS_HOTPLUG(dev))
		connector->polled = DRM_CONNECTOR_POLL_HPD;
	else
		connector->polled = DRM_CONNECTOR_POLL_CONNECT;

	/*
	 * Configure the automatic hotplug detection stuff
	 */
	crt->force_hotplug_required = 0;
	if (HAS_PCH_SPLIT(dev)) {
		u32 adpa;

		adpa = I915_READ(PCH_ADPA);
		adpa &= ~ADPA_CRT_HOTPLUG_MASK;
		adpa |= ADPA_HOTPLUG_BITS;
		I915_WRITE(PCH_ADPA, adpa);
		POSTING_READ(PCH_ADPA);

		DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
		crt->force_hotplug_required = 1;
	}

	dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright © 2006-2007 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*/
	26
	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
79e53945 JB	29	#include "drmP.h"
	30	#include "drm.h"
	31	#include "drm_crtc.h"
	32	#include "drm_crtc_helper.h"
f5afcd3d	33	#include "drm_edid.h"
79e53945 JB	34	#include "intel_drv.h"
	35	#include "i915_drm.h"
	36	#include "i915_drv.h"
	37
e7dbb2f2 KP	38	/* Here's the desired hotplug mode */
	39	#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 \| \
	40	ADPA_CRT_HOTPLUG_WARMUP_10MS \| \
	41	ADPA_CRT_HOTPLUG_SAMPLE_4S \| \
	42	ADPA_CRT_HOTPLUG_VOLTAGE_50 \| \
	43	ADPA_CRT_HOTPLUG_VOLREF_325MV \| \
	44	ADPA_CRT_HOTPLUG_ENABLE)
	45
c9a1c4cd CW	46	struct intel_crt {
c9a1c4cd CW	47	struct intel_encoder base;
e7dbb2f2	48	bool force_hotplug_required;
c9a1c4cd CW	49	};
	50
	51	static struct intel_crt intel_attached_crt(struct drm_connector connector)
	52	{
	53	return container_of(intel_attached_encoder(connector),
	54	struct intel_crt, base);
	55	}
	56
79e53945 JB	57	static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
	58	{
	59	struct drm_device *dev = encoder->dev;
	60	struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f	61	u32 temp, reg;
79e53945	62
bad720ff	63	if (HAS_PCH_SPLIT(dev))
2c07245f ZW	64	reg = PCH_ADPA;
	65	else
	66	reg = ADPA;
	67
	68	temp = I915_READ(reg);
79e53945	69	temp &= ~(ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE);
febc7694	70	temp &= ~ADPA_DAC_ENABLE;
79e53945 JB	71
	72	switch(mode) {
	73	case DRM_MODE_DPMS_ON:
	74	temp \|= ADPA_DAC_ENABLE;
	75	break;
	76	case DRM_MODE_DPMS_STANDBY:
	77	temp \|= ADPA_DAC_ENABLE \| ADPA_HSYNC_CNTL_DISABLE;
	78	break;
	79	case DRM_MODE_DPMS_SUSPEND:
	80	temp \|= ADPA_DAC_ENABLE \| ADPA_VSYNC_CNTL_DISABLE;
	81	break;
	82	case DRM_MODE_DPMS_OFF:
	83	temp \|= ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE;
	84	break;
	85	}
	86
2c07245f	87	I915_WRITE(reg, temp);
79e53945 JB	88	}
	89
	90	static int intel_crt_mode_valid(struct drm_connector *connector,
	91	struct drm_display_mode *mode)
	92	{
6bcdcd9e ZY	93	struct drm_device *dev = connector->dev;
	94
	95	int max_clock = 0;
79e53945 JB	96	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	97	return MODE_NO_DBLESCAN;
	98
6bcdcd9e ZY	99	if (mode->clock < 25000)
	100	return MODE_CLOCK_LOW;
	101
a6c45cf0	102	if (IS_GEN2(dev))
6bcdcd9e ZY	103	max_clock = 350000;
	104	else
	105	max_clock = 400000;
	106	if (mode->clock > max_clock)
	107	return MODE_CLOCK_HIGH;
79e53945 JB	108
	109	return MODE_OK;
	110	}
	111
	112	static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
	113	struct drm_display_mode *mode,
	114	struct drm_display_mode *adjusted_mode)
	115	{
	116	return true;
	117	}
	118
	119	static void intel_crt_mode_set(struct drm_encoder *encoder,
	120	struct drm_display_mode *mode,
	121	struct drm_display_mode *adjusted_mode)
	122	{
	123
	124	struct drm_device *dev = encoder->dev;
	125	struct drm_crtc *crtc = encoder->crtc;
	126	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	127	struct drm_i915_private *dev_priv = dev->dev_private;
	128	int dpll_md_reg;
	129	u32 adpa, dpll_md;
2c07245f	130	u32 adpa_reg;
79e53945	131
9db4a9c7	132	dpll_md_reg = DPLL_MD(intel_crtc->pipe);
79e53945	133
bad720ff	134	if (HAS_PCH_SPLIT(dev))
2c07245f ZW	135	adpa_reg = PCH_ADPA;
	136	else
	137	adpa_reg = ADPA;
	138
79e53945 JB	139	/*
	140	* Disable separate mode multiplier used when cloning SDVO to CRT
	141	* XXX this needs to be adjusted when we really are cloning
	142	*/
a6c45cf0	143	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
79e53945 JB	144	dpll_md = I915_READ(dpll_md_reg);
	145	I915_WRITE(dpll_md_reg,
	146	dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
	147	}
	148
e7dbb2f2	149	adpa = ADPA_HOTPLUG_BITS;
79e53945 JB	150	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	151	adpa \|= ADPA_HSYNC_ACTIVE_HIGH;
	152	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	153	adpa \|= ADPA_VSYNC_ACTIVE_HIGH;
	154
6bcdcd9e	155	if (intel_crtc->pipe == 0) {
8db9d77b ZW	156	if (HAS_PCH_CPT(dev))
	157	adpa \|= PORT_TRANS_A_SEL_CPT;
	158	else
	159	adpa \|= ADPA_PIPE_A_SELECT;
6bcdcd9e	160	} else {
8db9d77b ZW	161	if (HAS_PCH_CPT(dev))
	162	adpa \|= PORT_TRANS_B_SEL_CPT;
	163	else
	164	adpa \|= ADPA_PIPE_B_SELECT;
6bcdcd9e	165	}
79e53945	166
9db4a9c7 JB	167	if (!HAS_PCH_SPLIT(dev))
	168	I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
	169
2c07245f ZW	170	I915_WRITE(adpa_reg, adpa);
	171	}
	172
f2b115e6	173	static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
2c07245f ZW	174	{
2c07245f ZW	175	struct drm_device *dev = connector->dev;
e7dbb2f2	176	struct intel_crt *crt = intel_attached_crt(connector);
2c07245f	177	struct drm_i915_private *dev_priv = dev->dev_private;
e7dbb2f2	178	u32 adpa;
2c07245f ZW	179	bool ret;
2c07245f ZW	180
e7dbb2f2 KP	181	/* The first time through, trigger an explicit detection cycle */
	182	if (crt->force_hotplug_required) {
	183	bool turn_off_dac = HAS_PCH_SPLIT(dev);
	184	u32 save_adpa;
67941da2	185
e7dbb2f2 KP	186	crt->force_hotplug_required = 0;
	187
	188	save_adpa = adpa = I915_READ(PCH_ADPA);
	189	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
	190
	191	adpa \|= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
	192	if (turn_off_dac)
	193	adpa &= ~ADPA_DAC_ENABLE;
	194
	195	I915_WRITE(PCH_ADPA, adpa);
	196
	197	if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
	198	1000))
	199	DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
	200
	201	if (turn_off_dac) {
	202	I915_WRITE(PCH_ADPA, save_adpa);
	203	POSTING_READ(PCH_ADPA);
	204	}
a4a6b901 ZW	205	}
a4a6b901 ZW	206
2c07245f ZW	207	/* Check the status to see if both blue and green are on now */
2c07245f ZW	208	adpa = I915_READ(PCH_ADPA);
e7dbb2f2	209	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
2c07245f ZW	210	ret = true;
	211	else
	212	ret = false;
e7dbb2f2	213	DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
2c07245f	214
2c07245f	215	return ret;
79e53945 JB	216	}
	217
	218	/**
	219	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
	220	*
	221	* Not for i915G/i915GM
	222	*
	223	* \return true if CRT is connected.
	224	* \return false if CRT is disconnected.
	225	*/
	226	static bool intel_crt_detect_hotplug(struct drm_connector *connector)
	227	{
	228	struct drm_device *dev = connector->dev;
	229	struct drm_i915_private *dev_priv = dev->dev_private;
7a772c49 AJ	230	u32 hotplug_en, orig, stat;
7a772c49 AJ	231	bool ret = false;
771cb081	232	int i, tries = 0;
2c07245f	233
bad720ff	234	if (HAS_PCH_SPLIT(dev))
f2b115e6	235	return intel_ironlake_crt_detect_hotplug(connector);
2c07245f	236
771cb081 ZY	237	/*
	238	* On 4 series desktop, CRT detect sequence need to be done twice
	239	* to get a reliable result.
	240	*/
79e53945	241
771cb081 ZY	242	if (IS_G4X(dev) && !IS_GM45(dev))
	243	tries = 2;
	244	else
	245	tries = 1;
7a772c49	246	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
771cb081 ZY	247	hotplug_en \|= CRT_HOTPLUG_FORCE_DETECT;
771cb081 ZY	248
771cb081	249	for (i = 0; i < tries ; i++) {
771cb081 ZY	250	/* turn on the FORCE_DETECT */
771cb081 ZY	251	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
771cb081	252	/* wait for FORCE_DETECT to go off */
913d8d11 CW	253	if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
913d8d11 CW	254	CRT_HOTPLUG_FORCE_DETECT) == 0,
481b6af3	255	1000))
79077319	256	DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
771cb081	257	}
79e53945	258
7a772c49 AJ	259	stat = I915_READ(PORT_HOTPLUG_STAT);
	260	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
	261	ret = true;
	262
	263	/* clear the interrupt we just generated, if any */
	264	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
79e53945	265
7a772c49 AJ	266	/* and put the bits back */
	267	I915_WRITE(PORT_HOTPLUG_EN, orig);
	268
	269	return ret;
79e53945 JB	270	}
79e53945 JB	271
f5afcd3d	272	static bool intel_crt_detect_ddc(struct drm_connector *connector)
79e53945	273	{
f5afcd3d	274	struct intel_crt *crt = intel_attached_crt(connector);
c9a1c4cd	275	struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
79e53945 JB	276
79e53945 JB	277	/* CRT should always be at 0, but check anyway */
c9a1c4cd	278	if (crt->base.type != INTEL_OUTPUT_ANALOG)
79e53945 JB	279	return false;
79e53945 JB	280
c9a1c4cd	281	if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
f5afcd3d DM	282	struct edid *edid;
	283	bool is_digital = false;
	284
	285	edid = drm_get_edid(connector,
	286	&dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
	287	/*
	288	* This may be a DVI-I connector with a shared DDC
	289	* link between analog and digital outputs, so we
	290	* have to check the EDID input spec of the attached device.
d3bcb757 CW	291	*
d3bcb757 CW	292	* On the other hand, what should we do if it is a broken EDID?
f5afcd3d DM	293	*/
	294	if (edid != NULL) {
	295	is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
	296	connector->display_info.raw_edid = NULL;
	297	kfree(edid);
	298	}
	299
	300	if (!is_digital) {
	301	DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
	302	return true;
d3bcb757 CW	303	} else {
d3bcb757 CW	304	DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
f5afcd3d	305	}
6ec3d0c0 CW	306	}
	307
	308	return false;
79e53945 JB	309	}
79e53945 JB	310
e4a5d54f	311	static enum drm_connector_status
7173188d	312	intel_crt_load_detect(struct intel_crt *crt)
e4a5d54f	313	{
7173188d	314	struct drm_device *dev = crt->base.base.dev;
e4a5d54f	315	struct drm_i915_private *dev_priv = dev->dev_private;
7173188d	316	uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
e4a5d54f ML	317	uint32_t save_bclrpat;
	318	uint32_t save_vtotal;
	319	uint32_t vtotal, vactive;
	320	uint32_t vsample;
	321	uint32_t vblank, vblank_start, vblank_end;
	322	uint32_t dsl;
	323	uint32_t bclrpat_reg;
	324	uint32_t vtotal_reg;
	325	uint32_t vblank_reg;
	326	uint32_t vsync_reg;
	327	uint32_t pipeconf_reg;
	328	uint32_t pipe_dsl_reg;
	329	uint8_t st00;
	330	enum drm_connector_status status;
	331
6ec3d0c0 CW	332	DRM_DEBUG_KMS("starting load-detect on CRT\n");
6ec3d0c0 CW	333
9db4a9c7 JB	334	bclrpat_reg = BCLRPAT(pipe);
	335	vtotal_reg = VTOTAL(pipe);
	336	vblank_reg = VBLANK(pipe);
	337	vsync_reg = VSYNC(pipe);
	338	pipeconf_reg = PIPECONF(pipe);
	339	pipe_dsl_reg = PIPEDSL(pipe);
e4a5d54f ML	340
	341	save_bclrpat = I915_READ(bclrpat_reg);
	342	save_vtotal = I915_READ(vtotal_reg);
	343	vblank = I915_READ(vblank_reg);
	344
	345	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	346	vactive = (save_vtotal & 0x7ff) + 1;
	347
	348	vblank_start = (vblank & 0xfff) + 1;
	349	vblank_end = ((vblank >> 16) & 0xfff) + 1;
	350
	351	/* Set the border color to purple. */
	352	I915_WRITE(bclrpat_reg, 0x500050);
	353
a6c45cf0	354	if (!IS_GEN2(dev)) {
e4a5d54f ML	355	uint32_t pipeconf = I915_READ(pipeconf_reg);
e4a5d54f ML	356	I915_WRITE(pipeconf_reg, pipeconf \| PIPECONF_FORCE_BORDER);
19c55da1	357	POSTING_READ(pipeconf_reg);
e4a5d54f ML	358	/* Wait for next Vblank to substitue
e4a5d54f ML	359	* border color for Color info */
9d0498a2	360	intel_wait_for_vblank(dev, pipe);
e4a5d54f ML	361	st00 = I915_READ8(VGA_MSR_WRITE);
	362	status = ((st00 & (1 << 4)) != 0) ?
	363	connector_status_connected :
	364	connector_status_disconnected;
	365
	366	I915_WRITE(pipeconf_reg, pipeconf);
	367	} else {
	368	bool restore_vblank = false;
	369	int count, detect;
	370
	371	/*
	372	* If there isn't any border, add some.
	373	* Yes, this will flicker
	374	*/
	375	if (vblank_start <= vactive && vblank_end >= vtotal) {
	376	uint32_t vsync = I915_READ(vsync_reg);
	377	uint32_t vsync_start = (vsync & 0xffff) + 1;
	378
	379	vblank_start = vsync_start;
	380	I915_WRITE(vblank_reg,
	381	(vblank_start - 1) \|
	382	((vblank_end - 1) << 16));
	383	restore_vblank = true;
	384	}
	385	/* sample in the vertical border, selecting the larger one */
	386	if (vblank_start - vactive >= vtotal - vblank_end)
	387	vsample = (vblank_start + vactive) >> 1;
	388	else
	389	vsample = (vtotal + vblank_end) >> 1;
	390
	391	/*
	392	* Wait for the border to be displayed
	393	*/
	394	while (I915_READ(pipe_dsl_reg) >= vactive)
	395	;
	396	while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
	397	;
	398	/*
	399	* Watch ST00 for an entire scanline
	400	*/
	401	detect = 0;
	402	count = 0;
	403	do {
	404	count++;
	405	/* Read the ST00 VGA status register */
	406	st00 = I915_READ8(VGA_MSR_WRITE);
	407	if (st00 & (1 << 4))
	408	detect++;
	409	} while ((I915_READ(pipe_dsl_reg) == dsl));
	410
	411	/* restore vblank if necessary */
	412	if (restore_vblank)
	413	I915_WRITE(vblank_reg, vblank);
	414	/*
	415	* If more than 3/4 of the scanline detected a monitor,
	416	* then it is assumed to be present. This works even on i830,
	417	* where there isn't any way to force the border color across
	418	* the screen
	419	*/
	420	status = detect * 4 > count * 3 ?
	421	connector_status_connected :
	422	connector_status_disconnected;
	423	}
	424
425	/* Restore previous settings */
426	I915_WRITE(bclrpat_reg, save_bclrpat);
427
428	return status;
429	}
430
7b334fcb	431	static enum drm_connector_status
930a9e28	432	intel_crt_detect(struct drm_connector *connector, bool force)
79e53945 JB	433	{
79e53945 JB	434	struct drm_device *dev = connector->dev;
c9a1c4cd	435	struct intel_crt *crt = intel_attached_crt(connector);
e4a5d54f	436	struct drm_crtc *crtc;
e4a5d54f	437	enum drm_connector_status status;
79e53945	438
a6c45cf0	439	if (I915_HAS_HOTPLUG(dev)) {
6ec3d0c0 CW	440	if (intel_crt_detect_hotplug(connector)) {
6ec3d0c0 CW	441	DRM_DEBUG_KMS("CRT detected via hotplug\n");
79e53945	442	return connector_status_connected;
e7dbb2f2 KP	443	} else {
e7dbb2f2 KP	444	DRM_DEBUG_KMS("CRT not detected via hotplug\n");
79e53945	445	return connector_status_disconnected;
e7dbb2f2	446	}
79e53945 JB	447	}
79e53945 JB	448
f5afcd3d	449	if (intel_crt_detect_ddc(connector))
79e53945 JB	450	return connector_status_connected;
79e53945 JB	451
930a9e28	452	if (!force)
7b334fcb CW	453	return connector->status;
7b334fcb CW	454
e4a5d54f	455	/* for pre-945g platforms use load detect */
c9a1c4cd CW	456	crtc = crt->base.base.crtc;
c9a1c4cd CW	457	if (crtc && crtc->enabled) {
7173188d	458	status = intel_crt_load_detect(crt);
e4a5d54f	459	} else {
8261b191 CW	460	struct intel_load_detect_pipe tmp;
	461
	462	if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
	463	&tmp)) {
f5afcd3d	464	if (intel_crt_detect_ddc(connector))
6ec3d0c0 CW	465	status = connector_status_connected;
6ec3d0c0 CW	466	else
7173188d	467	status = intel_crt_load_detect(crt);
8261b191 CW	468	intel_release_load_detect_pipe(&crt->base, connector,
8261b191 CW	469	&tmp);
e4a5d54f ML	470	} else
	471	status = connector_status_unknown;
	472	}
	473
	474	return status;
79e53945 JB	475	}
	476
	477	static void intel_crt_destroy(struct drm_connector *connector)
	478	{
79e53945 JB	479	drm_sysfs_connector_remove(connector);
	480	drm_connector_cleanup(connector);
	481	kfree(connector);
	482	}
	483
	484	static int intel_crt_get_modes(struct drm_connector *connector)
	485	{
8e4d36b9	486	struct drm_device *dev = connector->dev;
f899fc64	487	struct drm_i915_private *dev_priv = dev->dev_private;
890f3359	488	int ret;
8e4d36b9	489
f899fc64 CW	490	ret = intel_ddc_get_modes(connector,
f899fc64 CW	491	&dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
8e4d36b9	492	if (ret \|\| !IS_G4X(dev))
f899fc64	493	return ret;
8e4d36b9	494
8e4d36b9	495	/* Try to probe digital port for output in DVI-I -> VGA mode. */
f899fc64 CW	496	return intel_ddc_get_modes(connector,
f899fc64 CW	497	&dev_priv->gmbus[GMBUS_PORT_DPB].adapter);
79e53945 JB	498	}
	499
	500	static int intel_crt_set_property(struct drm_connector *connector,
	501	struct drm_property *property,
	502	uint64_t value)
	503	{
79e53945 JB	504	return 0;
	505	}
	506
f3269058 CW	507	static void intel_crt_reset(struct drm_connector *connector)
	508	{
	509	struct drm_device *dev = connector->dev;
	510	struct intel_crt *crt = intel_attached_crt(connector);
	511
	512	if (HAS_PCH_SPLIT(dev))
	513	crt->force_hotplug_required = 1;
	514	}
	515
79e53945 JB	516	/*
	517	* Routines for controlling stuff on the analog port
	518	*/
	519
	520	static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
	521	.dpms = intel_crt_dpms,
	522	.mode_fixup = intel_crt_mode_fixup,
	523	.prepare = intel_encoder_prepare,
	524	.commit = intel_encoder_commit,
	525	.mode_set = intel_crt_mode_set,
	526	};
	527
	528	static const struct drm_connector_funcs intel_crt_connector_funcs = {
f3269058	529	.reset = intel_crt_reset,
c9fb15f6	530	.dpms = drm_helper_connector_dpms,
79e53945 JB	531	.detect = intel_crt_detect,
	532	.fill_modes = drm_helper_probe_single_connector_modes,
	533	.destroy = intel_crt_destroy,
	534	.set_property = intel_crt_set_property,
	535	};
	536
	537	static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	538	.mode_valid = intel_crt_mode_valid,
	539	.get_modes = intel_crt_get_modes,
df0e9248	540	.best_encoder = intel_best_encoder,
79e53945 JB	541	};
79e53945 JB	542
79e53945	543	static const struct drm_encoder_funcs intel_crt_enc_funcs = {
ea5b213a	544	.destroy = intel_encoder_destroy,
79e53945 JB	545	};
	546
	547	void intel_crt_init(struct drm_device *dev)
	548	{
	549	struct drm_connector *connector;
c9a1c4cd	550	struct intel_crt *crt;
454c1ca8	551	struct intel_connector *intel_connector;
db545019	552	struct drm_i915_private *dev_priv = dev->dev_private;
79e53945	553
c9a1c4cd CW	554	crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
c9a1c4cd CW	555	if (!crt)
79e53945 JB	556	return;
79e53945 JB	557
454c1ca8 ZW	558	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
454c1ca8 ZW	559	if (!intel_connector) {
c9a1c4cd	560	kfree(crt);
454c1ca8 ZW	561	return;
	562	}
	563
	564	connector = &intel_connector->base;
	565	drm_connector_init(dev, &intel_connector->base,
79e53945 JB	566	&intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
79e53945 JB	567
c9a1c4cd	568	drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
79e53945 JB	569	DRM_MODE_ENCODER_DAC);
79e53945 JB	570
c9a1c4cd	571	intel_connector_attach_encoder(intel_connector, &crt->base);
79e53945	572
c9a1c4cd CW	573	crt->base.type = INTEL_OUTPUT_ANALOG;
	574	crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT \|
	575	1 << INTEL_ANALOG_CLONE_BIT \|
	576	1 << INTEL_SDVO_LVDS_CLONE_BIT);
	577	crt->base.crtc_mask = (1 << 0) \| (1 << 1);
734b4157	578	connector->interlace_allowed = 1;
79e53945 JB	579	connector->doublescan_allowed = 0;
79e53945 JB	580
c9a1c4cd	581	drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
79e53945 JB	582	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
	583
	584	drm_sysfs_connector_add(connector);
b01f2c3a	585
eb1f8e4f DA	586	if (I915_HAS_HOTPLUG(dev))
	587	connector->polled = DRM_CONNECTOR_POLL_HPD;
	588	else
	589	connector->polled = DRM_CONNECTOR_POLL_CONNECT;
	590
e7dbb2f2 KP	591	/*
	592	* Configure the automatic hotplug detection stuff
	593	*/
	594	crt->force_hotplug_required = 0;
	595	if (HAS_PCH_SPLIT(dev)) {
	596	u32 adpa;
	597
	598	adpa = I915_READ(PCH_ADPA);
	599	adpa &= ~ADPA_CRT_HOTPLUG_MASK;
	600	adpa \|= ADPA_HOTPLUG_BITS;
	601	I915_WRITE(PCH_ADPA, adpa);
	602	POSTING_READ(PCH_ADPA);
	603
	604	DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
	605	crt->force_hotplug_required = 1;
	606	}
	607
b01f2c3a	608	dev_priv->hotplug_supported_mask \|= CRT_HOTPLUG_INT_STATUS;
79e53945	609	}