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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "drm_crtc.h" | |
31 | #include "drm_crtc_helper.h" | |
32 | #include "intel_drv.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
35 | ||
36 | static void intel_crt_dpms(struct drm_encoder *encoder, int mode) | |
37 | { | |
38 | struct drm_device *dev = encoder->dev; | |
39 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 40 | u32 temp, reg; |
79e53945 | 41 | |
f2b115e6 | 42 | if (IS_IRONLAKE(dev)) |
2c07245f ZW |
43 | reg = PCH_ADPA; |
44 | else | |
45 | reg = ADPA; | |
46 | ||
47 | temp = I915_READ(reg); | |
79e53945 | 48 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
febc7694 | 49 | temp &= ~ADPA_DAC_ENABLE; |
79e53945 JB |
50 | |
51 | switch(mode) { | |
52 | case DRM_MODE_DPMS_ON: | |
53 | temp |= ADPA_DAC_ENABLE; | |
54 | break; | |
55 | case DRM_MODE_DPMS_STANDBY: | |
56 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | |
57 | break; | |
58 | case DRM_MODE_DPMS_SUSPEND: | |
59 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | |
60 | break; | |
61 | case DRM_MODE_DPMS_OFF: | |
62 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | |
63 | break; | |
64 | } | |
65 | ||
2c07245f | 66 | I915_WRITE(reg, temp); |
79e53945 JB |
67 | } |
68 | ||
69 | static int intel_crt_mode_valid(struct drm_connector *connector, | |
70 | struct drm_display_mode *mode) | |
71 | { | |
6bcdcd9e ZY |
72 | struct drm_device *dev = connector->dev; |
73 | ||
74 | int max_clock = 0; | |
79e53945 JB |
75 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
76 | return MODE_NO_DBLESCAN; | |
77 | ||
6bcdcd9e ZY |
78 | if (mode->clock < 25000) |
79 | return MODE_CLOCK_LOW; | |
80 | ||
81 | if (!IS_I9XX(dev)) | |
82 | max_clock = 350000; | |
83 | else | |
84 | max_clock = 400000; | |
85 | if (mode->clock > max_clock) | |
86 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
87 | |
88 | return MODE_OK; | |
89 | } | |
90 | ||
91 | static bool intel_crt_mode_fixup(struct drm_encoder *encoder, | |
92 | struct drm_display_mode *mode, | |
93 | struct drm_display_mode *adjusted_mode) | |
94 | { | |
95 | return true; | |
96 | } | |
97 | ||
98 | static void intel_crt_mode_set(struct drm_encoder *encoder, | |
99 | struct drm_display_mode *mode, | |
100 | struct drm_display_mode *adjusted_mode) | |
101 | { | |
102 | ||
103 | struct drm_device *dev = encoder->dev; | |
104 | struct drm_crtc *crtc = encoder->crtc; | |
105 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
107 | int dpll_md_reg; | |
108 | u32 adpa, dpll_md; | |
2c07245f | 109 | u32 adpa_reg; |
79e53945 JB |
110 | |
111 | if (intel_crtc->pipe == 0) | |
112 | dpll_md_reg = DPLL_A_MD; | |
113 | else | |
114 | dpll_md_reg = DPLL_B_MD; | |
115 | ||
f2b115e6 | 116 | if (IS_IRONLAKE(dev)) |
2c07245f ZW |
117 | adpa_reg = PCH_ADPA; |
118 | else | |
119 | adpa_reg = ADPA; | |
120 | ||
79e53945 JB |
121 | /* |
122 | * Disable separate mode multiplier used when cloning SDVO to CRT | |
123 | * XXX this needs to be adjusted when we really are cloning | |
124 | */ | |
f2b115e6 | 125 | if (IS_I965G(dev) && !IS_IRONLAKE(dev)) { |
79e53945 JB |
126 | dpll_md = I915_READ(dpll_md_reg); |
127 | I915_WRITE(dpll_md_reg, | |
128 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); | |
129 | } | |
130 | ||
131 | adpa = 0; | |
132 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
133 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
134 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
135 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
136 | ||
6bcdcd9e | 137 | if (intel_crtc->pipe == 0) { |
79e53945 | 138 | adpa |= ADPA_PIPE_A_SELECT; |
f2b115e6 | 139 | if (!IS_IRONLAKE(dev)) |
2c07245f | 140 | I915_WRITE(BCLRPAT_A, 0); |
6bcdcd9e | 141 | } else { |
79e53945 | 142 | adpa |= ADPA_PIPE_B_SELECT; |
f2b115e6 | 143 | if (!IS_IRONLAKE(dev)) |
2c07245f | 144 | I915_WRITE(BCLRPAT_B, 0); |
6bcdcd9e | 145 | } |
79e53945 | 146 | |
2c07245f ZW |
147 | I915_WRITE(adpa_reg, adpa); |
148 | } | |
149 | ||
f2b115e6 | 150 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
151 | { |
152 | struct drm_device *dev = connector->dev; | |
153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
730915d6 | 154 | u32 adpa; |
2c07245f ZW |
155 | bool ret; |
156 | ||
730915d6 | 157 | adpa = I915_READ(PCH_ADPA); |
67941da2 | 158 | |
2c07245f ZW |
159 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
160 | ||
161 | adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | | |
162 | ADPA_CRT_HOTPLUG_WARMUP_10MS | | |
163 | ADPA_CRT_HOTPLUG_SAMPLE_4S | | |
164 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */ | |
165 | ADPA_CRT_HOTPLUG_VOLREF_325MV | | |
166 | ADPA_CRT_HOTPLUG_ENABLE | | |
167 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER); | |
168 | ||
28c97730 | 169 | DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa); |
2c07245f ZW |
170 | I915_WRITE(PCH_ADPA, adpa); |
171 | ||
67941da2 ZW |
172 | while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0) |
173 | ; | |
2c07245f ZW |
174 | |
175 | /* Check the status to see if both blue and green are on now */ | |
176 | adpa = I915_READ(PCH_ADPA); | |
67941da2 ZW |
177 | adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK; |
178 | if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) || | |
179 | (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO)) | |
2c07245f ZW |
180 | ret = true; |
181 | else | |
182 | ret = false; | |
183 | ||
2c07245f | 184 | return ret; |
79e53945 JB |
185 | } |
186 | ||
187 | /** | |
188 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
189 | * | |
190 | * Not for i915G/i915GM | |
191 | * | |
192 | * \return true if CRT is connected. | |
193 | * \return false if CRT is disconnected. | |
194 | */ | |
195 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
196 | { | |
197 | struct drm_device *dev = connector->dev; | |
198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
771cb081 ZY |
199 | u32 hotplug_en; |
200 | int i, tries = 0; | |
2c07245f | 201 | |
f2b115e6 AJ |
202 | if (IS_IRONLAKE(dev)) |
203 | return intel_ironlake_crt_detect_hotplug(connector); | |
2c07245f | 204 | |
771cb081 ZY |
205 | /* |
206 | * On 4 series desktop, CRT detect sequence need to be done twice | |
207 | * to get a reliable result. | |
208 | */ | |
79e53945 | 209 | |
771cb081 ZY |
210 | if (IS_G4X(dev) && !IS_GM45(dev)) |
211 | tries = 2; | |
212 | else | |
213 | tries = 1; | |
214 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
5ca58282 | 215 | hotplug_en &= CRT_FORCE_HOTPLUG_MASK; |
771cb081 ZY |
216 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
217 | ||
e92597cf | 218 | if (IS_G4X(dev)) |
771cb081 ZY |
219 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
220 | ||
221 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
222 | ||
223 | for (i = 0; i < tries ; i++) { | |
224 | unsigned long timeout; | |
225 | /* turn on the FORCE_DETECT */ | |
226 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
227 | timeout = jiffies + msecs_to_jiffies(1000); | |
228 | /* wait for FORCE_DETECT to go off */ | |
229 | do { | |
230 | if (!(I915_READ(PORT_HOTPLUG_EN) & | |
231 | CRT_HOTPLUG_FORCE_DETECT)) | |
232 | break; | |
233 | msleep(1); | |
234 | } while (time_after(timeout, jiffies)); | |
235 | } | |
79e53945 | 236 | |
8e9e0eea ZW |
237 | if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != |
238 | CRT_HOTPLUG_MONITOR_NONE) | |
79e53945 JB |
239 | return true; |
240 | ||
241 | return false; | |
242 | } | |
243 | ||
244 | static bool intel_crt_detect_ddc(struct drm_connector *connector) | |
245 | { | |
246 | struct intel_output *intel_output = to_intel_output(connector); | |
247 | ||
248 | /* CRT should always be at 0, but check anyway */ | |
249 | if (intel_output->type != INTEL_OUTPUT_ANALOG) | |
250 | return false; | |
251 | ||
252 | return intel_ddc_probe(intel_output); | |
253 | } | |
254 | ||
e4a5d54f ML |
255 | static enum drm_connector_status |
256 | intel_crt_load_detect(struct drm_crtc *crtc, struct intel_output *intel_output) | |
257 | { | |
258 | struct drm_encoder *encoder = &intel_output->enc; | |
259 | struct drm_device *dev = encoder->dev; | |
260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
261 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
262 | uint32_t pipe = intel_crtc->pipe; | |
263 | uint32_t save_bclrpat; | |
264 | uint32_t save_vtotal; | |
265 | uint32_t vtotal, vactive; | |
266 | uint32_t vsample; | |
267 | uint32_t vblank, vblank_start, vblank_end; | |
268 | uint32_t dsl; | |
269 | uint32_t bclrpat_reg; | |
270 | uint32_t vtotal_reg; | |
271 | uint32_t vblank_reg; | |
272 | uint32_t vsync_reg; | |
273 | uint32_t pipeconf_reg; | |
274 | uint32_t pipe_dsl_reg; | |
275 | uint8_t st00; | |
276 | enum drm_connector_status status; | |
277 | ||
278 | if (pipe == 0) { | |
279 | bclrpat_reg = BCLRPAT_A; | |
280 | vtotal_reg = VTOTAL_A; | |
281 | vblank_reg = VBLANK_A; | |
282 | vsync_reg = VSYNC_A; | |
283 | pipeconf_reg = PIPEACONF; | |
284 | pipe_dsl_reg = PIPEADSL; | |
285 | } else { | |
286 | bclrpat_reg = BCLRPAT_B; | |
287 | vtotal_reg = VTOTAL_B; | |
288 | vblank_reg = VBLANK_B; | |
289 | vsync_reg = VSYNC_B; | |
290 | pipeconf_reg = PIPEBCONF; | |
291 | pipe_dsl_reg = PIPEBDSL; | |
292 | } | |
293 | ||
294 | save_bclrpat = I915_READ(bclrpat_reg); | |
295 | save_vtotal = I915_READ(vtotal_reg); | |
296 | vblank = I915_READ(vblank_reg); | |
297 | ||
298 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
299 | vactive = (save_vtotal & 0x7ff) + 1; | |
300 | ||
301 | vblank_start = (vblank & 0xfff) + 1; | |
302 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
303 | ||
304 | /* Set the border color to purple. */ | |
305 | I915_WRITE(bclrpat_reg, 0x500050); | |
306 | ||
307 | if (IS_I9XX(dev)) { | |
308 | uint32_t pipeconf = I915_READ(pipeconf_reg); | |
309 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
310 | /* Wait for next Vblank to substitue | |
311 | * border color for Color info */ | |
312 | intel_wait_for_vblank(dev); | |
313 | st00 = I915_READ8(VGA_MSR_WRITE); | |
314 | status = ((st00 & (1 << 4)) != 0) ? | |
315 | connector_status_connected : | |
316 | connector_status_disconnected; | |
317 | ||
318 | I915_WRITE(pipeconf_reg, pipeconf); | |
319 | } else { | |
320 | bool restore_vblank = false; | |
321 | int count, detect; | |
322 | ||
323 | /* | |
324 | * If there isn't any border, add some. | |
325 | * Yes, this will flicker | |
326 | */ | |
327 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
328 | uint32_t vsync = I915_READ(vsync_reg); | |
329 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
330 | ||
331 | vblank_start = vsync_start; | |
332 | I915_WRITE(vblank_reg, | |
333 | (vblank_start - 1) | | |
334 | ((vblank_end - 1) << 16)); | |
335 | restore_vblank = true; | |
336 | } | |
337 | /* sample in the vertical border, selecting the larger one */ | |
338 | if (vblank_start - vactive >= vtotal - vblank_end) | |
339 | vsample = (vblank_start + vactive) >> 1; | |
340 | else | |
341 | vsample = (vtotal + vblank_end) >> 1; | |
342 | ||
343 | /* | |
344 | * Wait for the border to be displayed | |
345 | */ | |
346 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
347 | ; | |
348 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
349 | ; | |
350 | /* | |
351 | * Watch ST00 for an entire scanline | |
352 | */ | |
353 | detect = 0; | |
354 | count = 0; | |
355 | do { | |
356 | count++; | |
357 | /* Read the ST00 VGA status register */ | |
358 | st00 = I915_READ8(VGA_MSR_WRITE); | |
359 | if (st00 & (1 << 4)) | |
360 | detect++; | |
361 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
362 | ||
363 | /* restore vblank if necessary */ | |
364 | if (restore_vblank) | |
365 | I915_WRITE(vblank_reg, vblank); | |
366 | /* | |
367 | * If more than 3/4 of the scanline detected a monitor, | |
368 | * then it is assumed to be present. This works even on i830, | |
369 | * where there isn't any way to force the border color across | |
370 | * the screen | |
371 | */ | |
372 | status = detect * 4 > count * 3 ? | |
373 | connector_status_connected : | |
374 | connector_status_disconnected; | |
375 | } | |
376 | ||
377 | /* Restore previous settings */ | |
378 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
379 | ||
380 | return status; | |
381 | } | |
382 | ||
79e53945 JB |
383 | static enum drm_connector_status intel_crt_detect(struct drm_connector *connector) |
384 | { | |
385 | struct drm_device *dev = connector->dev; | |
e4a5d54f ML |
386 | struct intel_output *intel_output = to_intel_output(connector); |
387 | struct drm_encoder *encoder = &intel_output->enc; | |
388 | struct drm_crtc *crtc; | |
389 | int dpms_mode; | |
390 | enum drm_connector_status status; | |
79e53945 JB |
391 | |
392 | if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) { | |
393 | if (intel_crt_detect_hotplug(connector)) | |
394 | return connector_status_connected; | |
395 | else | |
396 | return connector_status_disconnected; | |
397 | } | |
398 | ||
399 | if (intel_crt_detect_ddc(connector)) | |
400 | return connector_status_connected; | |
401 | ||
e4a5d54f ML |
402 | /* for pre-945g platforms use load detect */ |
403 | if (encoder->crtc && encoder->crtc->enabled) { | |
404 | status = intel_crt_load_detect(encoder->crtc, intel_output); | |
405 | } else { | |
406 | crtc = intel_get_load_detect_pipe(intel_output, | |
407 | NULL, &dpms_mode); | |
408 | if (crtc) { | |
409 | status = intel_crt_load_detect(crtc, intel_output); | |
410 | intel_release_load_detect_pipe(intel_output, dpms_mode); | |
411 | } else | |
412 | status = connector_status_unknown; | |
413 | } | |
414 | ||
415 | return status; | |
79e53945 JB |
416 | } |
417 | ||
418 | static void intel_crt_destroy(struct drm_connector *connector) | |
419 | { | |
420 | struct intel_output *intel_output = to_intel_output(connector); | |
421 | ||
422 | intel_i2c_destroy(intel_output->ddc_bus); | |
423 | drm_sysfs_connector_remove(connector); | |
424 | drm_connector_cleanup(connector); | |
425 | kfree(connector); | |
426 | } | |
427 | ||
428 | static int intel_crt_get_modes(struct drm_connector *connector) | |
429 | { | |
8e4d36b9 | 430 | int ret; |
79e53945 | 431 | struct intel_output *intel_output = to_intel_output(connector); |
883e860d | 432 | struct i2c_adapter *ddcbus; |
8e4d36b9 | 433 | struct drm_device *dev = connector->dev; |
434 | ||
435 | ||
436 | ret = intel_ddc_get_modes(intel_output); | |
437 | if (ret || !IS_G4X(dev)) | |
438 | goto end; | |
439 | ||
440 | ddcbus = intel_output->ddc_bus; | |
441 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ | |
442 | intel_output->ddc_bus = | |
443 | intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D"); | |
444 | ||
445 | if (!intel_output->ddc_bus) { | |
446 | intel_output->ddc_bus = ddcbus; | |
447 | dev_printk(KERN_ERR, &connector->dev->pdev->dev, | |
448 | "DDC bus registration failed for CRTDDC_D.\n"); | |
449 | goto end; | |
450 | } | |
451 | /* Try to get modes by GPIOD port */ | |
452 | ret = intel_ddc_get_modes(intel_output); | |
453 | intel_i2c_destroy(ddcbus); | |
454 | ||
455 | end: | |
456 | return ret; | |
457 | ||
79e53945 JB |
458 | } |
459 | ||
460 | static int intel_crt_set_property(struct drm_connector *connector, | |
461 | struct drm_property *property, | |
462 | uint64_t value) | |
463 | { | |
79e53945 JB |
464 | return 0; |
465 | } | |
466 | ||
467 | /* | |
468 | * Routines for controlling stuff on the analog port | |
469 | */ | |
470 | ||
471 | static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = { | |
472 | .dpms = intel_crt_dpms, | |
473 | .mode_fixup = intel_crt_mode_fixup, | |
474 | .prepare = intel_encoder_prepare, | |
475 | .commit = intel_encoder_commit, | |
476 | .mode_set = intel_crt_mode_set, | |
477 | }; | |
478 | ||
479 | static const struct drm_connector_funcs intel_crt_connector_funcs = { | |
c9fb15f6 | 480 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
481 | .detect = intel_crt_detect, |
482 | .fill_modes = drm_helper_probe_single_connector_modes, | |
483 | .destroy = intel_crt_destroy, | |
484 | .set_property = intel_crt_set_property, | |
485 | }; | |
486 | ||
487 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
488 | .mode_valid = intel_crt_mode_valid, | |
489 | .get_modes = intel_crt_get_modes, | |
490 | .best_encoder = intel_best_encoder, | |
491 | }; | |
492 | ||
b358d0a6 | 493 | static void intel_crt_enc_destroy(struct drm_encoder *encoder) |
79e53945 JB |
494 | { |
495 | drm_encoder_cleanup(encoder); | |
496 | } | |
497 | ||
498 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { | |
499 | .destroy = intel_crt_enc_destroy, | |
500 | }; | |
501 | ||
502 | void intel_crt_init(struct drm_device *dev) | |
503 | { | |
504 | struct drm_connector *connector; | |
505 | struct intel_output *intel_output; | |
db545019 | 506 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 507 | u32 i2c_reg; |
79e53945 JB |
508 | |
509 | intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); | |
510 | if (!intel_output) | |
511 | return; | |
512 | ||
513 | connector = &intel_output->base; | |
514 | drm_connector_init(dev, &intel_output->base, | |
515 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); | |
516 | ||
517 | drm_encoder_init(dev, &intel_output->enc, &intel_crt_enc_funcs, | |
518 | DRM_MODE_ENCODER_DAC); | |
519 | ||
520 | drm_mode_connector_attach_encoder(&intel_output->base, | |
521 | &intel_output->enc); | |
522 | ||
523 | /* Set up the DDC bus. */ | |
f2b115e6 | 524 | if (IS_IRONLAKE(dev)) |
2c07245f | 525 | i2c_reg = PCH_GPIOA; |
db545019 | 526 | else { |
2c07245f | 527 | i2c_reg = GPIOA; |
db545019 | 528 | /* Use VBT information for CRT DDC if available */ |
29874f44 | 529 | if (dev_priv->crt_ddc_bus != 0) |
db545019 DMEA |
530 | i2c_reg = dev_priv->crt_ddc_bus; |
531 | } | |
2c07245f | 532 | intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); |
79e53945 JB |
533 | if (!intel_output->ddc_bus) { |
534 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " | |
535 | "failed.\n"); | |
536 | return; | |
537 | } | |
538 | ||
539 | intel_output->type = INTEL_OUTPUT_ANALOG; | |
f8aed700 ML |
540 | intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
541 | (1 << INTEL_ANALOG_CLONE_BIT) | | |
542 | (1 << INTEL_SDVO_LVDS_CLONE_BIT); | |
543 | intel_output->crtc_mask = (1 << 0) | (1 << 1); | |
79e53945 JB |
544 | connector->interlace_allowed = 0; |
545 | connector->doublescan_allowed = 0; | |
546 | ||
547 | drm_encoder_helper_add(&intel_output->enc, &intel_crt_helper_funcs); | |
548 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); | |
549 | ||
550 | drm_sysfs_connector_add(connector); | |
551 | } |