Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 | 30 | #include <drm/drmP.h> |
c6f95f27 | 31 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
79e53945 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
79e53945 JB |
37 | #include "i915_drv.h" |
38 | ||
e7dbb2f2 KP |
39 | /* Here's the desired hotplug mode */ |
40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
45 | ADPA_CRT_HOTPLUG_ENABLE) | |
46 | ||
c9a1c4cd CW |
47 | struct intel_crt { |
48 | struct intel_encoder base; | |
637f44d2 AJ |
49 | /* DPMS state is stored in the connector, which we need in the |
50 | * encoder's enable/disable callbacks */ | |
51 | struct intel_connector *connector; | |
e7dbb2f2 | 52 | bool force_hotplug_required; |
f0f59a00 | 53 | i915_reg_t adpa_reg; |
c9a1c4cd CW |
54 | }; |
55 | ||
eebe6f0b | 56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 57 | { |
eebe6f0b | 58 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
59 | } |
60 | ||
eebe6f0b | 61 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 62 | { |
eebe6f0b | 63 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
64 | } |
65 | ||
e403fc94 DV |
66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
67 | enum pipe *pipe) | |
79e53945 | 68 | { |
e403fc94 | 69 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
e403fc94 | 71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
6d129bea | 72 | enum intel_display_power_domain power_domain; |
e403fc94 DV |
73 | u32 tmp; |
74 | ||
6d129bea | 75 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 76 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
77 | return false; |
78 | ||
e403fc94 DV |
79 | tmp = I915_READ(crt->adpa_reg); |
80 | ||
81 | if (!(tmp & ADPA_DAC_ENABLE)) | |
82 | return false; | |
83 | ||
84 | if (HAS_PCH_CPT(dev)) | |
85 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
86 | else | |
87 | *pipe = PORT_TO_PIPE(tmp); | |
88 | ||
89 | return true; | |
90 | } | |
91 | ||
6801c18c | 92 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 JB |
93 | { |
94 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
95 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
96 | u32 tmp, flags = 0; | |
97 | ||
98 | tmp = I915_READ(crt->adpa_reg); | |
99 | ||
100 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
101 | flags |= DRM_MODE_FLAG_PHSYNC; | |
102 | else | |
103 | flags |= DRM_MODE_FLAG_NHSYNC; | |
104 | ||
105 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
106 | flags |= DRM_MODE_FLAG_PVSYNC; | |
107 | else | |
108 | flags |= DRM_MODE_FLAG_NVSYNC; | |
109 | ||
6801c18c VS |
110 | return flags; |
111 | } | |
112 | ||
113 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 114 | struct intel_crtc_state *pipe_config) |
6801c18c VS |
115 | { |
116 | struct drm_device *dev = encoder->base.dev; | |
117 | int dotclock; | |
118 | ||
2d112de7 | 119 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 VS |
120 | |
121 | dotclock = pipe_config->port_clock; | |
122 | ||
6801c18c | 123 | if (HAS_PCH_SPLIT(dev)) |
18442d08 VS |
124 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
125 | ||
2d112de7 | 126 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
127 | } |
128 | ||
6801c18c | 129 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 130 | struct intel_crtc_state *pipe_config) |
6801c18c VS |
131 | { |
132 | intel_ddi_get_config(encoder, pipe_config); | |
133 | ||
2d112de7 | 134 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
135 | DRM_MODE_FLAG_NHSYNC | |
136 | DRM_MODE_FLAG_PVSYNC | | |
137 | DRM_MODE_FLAG_NVSYNC); | |
2d112de7 | 138 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
6801c18c VS |
139 | } |
140 | ||
b2cabb0e DV |
141 | /* Note: The caller is required to filter out dpms modes not supported by the |
142 | * platform. */ | |
143 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) | |
df0323c4 | 144 | { |
b2cabb0e | 145 | struct drm_device *dev = encoder->base.dev; |
df0323c4 | 146 | struct drm_i915_private *dev_priv = dev->dev_private; |
b2cabb0e | 147 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
894ed1ec | 148 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
7c5f93b0 | 149 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
894ed1ec DV |
150 | u32 adpa; |
151 | ||
152 | if (INTEL_INFO(dev)->gen >= 5) | |
153 | adpa = ADPA_HOTPLUG_BITS; | |
154 | else | |
155 | adpa = 0; | |
df0323c4 | 156 | |
894ed1ec DV |
157 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
158 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
159 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
160 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
161 | ||
162 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
163 | if (HAS_PCH_LPT(dev)) | |
164 | ; /* Those bits don't exist here */ | |
165 | else if (HAS_PCH_CPT(dev)) | |
166 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); | |
167 | else if (crtc->pipe == 0) | |
168 | adpa |= ADPA_PIPE_A_SELECT; | |
169 | else | |
170 | adpa |= ADPA_PIPE_B_SELECT; | |
171 | ||
172 | if (!HAS_PCH_SPLIT(dev)) | |
173 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
79e53945 | 174 | |
0206e353 | 175 | switch (mode) { |
79e53945 | 176 | case DRM_MODE_DPMS_ON: |
894ed1ec | 177 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
178 | break; |
179 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 180 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
181 | break; |
182 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 183 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
184 | break; |
185 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 186 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
187 | break; |
188 | } | |
189 | ||
894ed1ec | 190 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 191 | } |
2c07245f | 192 | |
637f44d2 AJ |
193 | static void intel_disable_crt(struct intel_encoder *encoder) |
194 | { | |
195 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); | |
196 | } | |
197 | ||
1ea56e26 VS |
198 | static void pch_disable_crt(struct intel_encoder *encoder) |
199 | { | |
200 | } | |
201 | ||
202 | static void pch_post_disable_crt(struct intel_encoder *encoder) | |
203 | { | |
204 | intel_disable_crt(encoder); | |
205 | } | |
abfdc1e3 | 206 | |
637f44d2 AJ |
207 | static void intel_enable_crt(struct intel_encoder *encoder) |
208 | { | |
209 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
210 | ||
211 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); | |
212 | } | |
213 | ||
c19de8eb DL |
214 | static enum drm_mode_status |
215 | intel_crt_mode_valid(struct drm_connector *connector, | |
216 | struct drm_display_mode *mode) | |
79e53945 | 217 | { |
6bcdcd9e | 218 | struct drm_device *dev = connector->dev; |
f8700b34 | 219 | int max_dotclk = to_i915(dev)->max_dotclk_freq; |
6bcdcd9e ZY |
220 | |
221 | int max_clock = 0; | |
79e53945 JB |
222 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
223 | return MODE_NO_DBLESCAN; | |
224 | ||
6bcdcd9e ZY |
225 | if (mode->clock < 25000) |
226 | return MODE_CLOCK_LOW; | |
227 | ||
a6c45cf0 | 228 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
229 | max_clock = 350000; |
230 | else | |
231 | max_clock = 400000; | |
232 | if (mode->clock > max_clock) | |
233 | return MODE_CLOCK_HIGH; | |
79e53945 | 234 | |
f8700b34 MK |
235 | if (mode->clock > max_dotclk) |
236 | return MODE_CLOCK_HIGH; | |
237 | ||
d4b1931c PZ |
238 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
239 | if (HAS_PCH_LPT(dev) && | |
240 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) | |
241 | return MODE_CLOCK_HIGH; | |
242 | ||
79e53945 JB |
243 | return MODE_OK; |
244 | } | |
245 | ||
5bfe2ac0 | 246 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
5cec258b | 247 | struct intel_crtc_state *pipe_config) |
79e53945 | 248 | { |
5bfe2ac0 DV |
249 | struct drm_device *dev = encoder->base.dev; |
250 | ||
251 | if (HAS_PCH_SPLIT(dev)) | |
252 | pipe_config->has_pch_encoder = true; | |
253 | ||
2a7aceec DV |
254 | /* LPT FDI RX only supports 8bpc. */ |
255 | if (HAS_PCH_LPT(dev)) | |
256 | pipe_config->pipe_bpp = 24; | |
257 | ||
8f7abfd8 | 258 | /* FDI must always be 2.7 GHz */ |
0e50338c DV |
259 | if (HAS_DDI(dev)) { |
260 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
8f7abfd8 | 261 | pipe_config->port_clock = 135000 * 2; |
00490c22 ML |
262 | |
263 | pipe_config->dpll_hw_state.wrpll = 0; | |
264 | pipe_config->dpll_hw_state.spll = | |
265 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; | |
0e50338c | 266 | } |
8f7abfd8 | 267 | |
79e53945 JB |
268 | return true; |
269 | } | |
270 | ||
f2b115e6 | 271 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
272 | { |
273 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 274 | struct intel_crt *crt = intel_attached_crt(connector); |
2c07245f | 275 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7dbb2f2 | 276 | u32 adpa; |
2c07245f ZW |
277 | bool ret; |
278 | ||
e7dbb2f2 KP |
279 | /* The first time through, trigger an explicit detection cycle */ |
280 | if (crt->force_hotplug_required) { | |
281 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
282 | u32 save_adpa; | |
67941da2 | 283 | |
e7dbb2f2 KP |
284 | crt->force_hotplug_required = 0; |
285 | ||
ca54b810 | 286 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
287 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
288 | ||
289 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
290 | if (turn_off_dac) | |
291 | adpa &= ~ADPA_DAC_ENABLE; | |
292 | ||
ca54b810 | 293 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 294 | |
ca54b810 | 295 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
e7dbb2f2 KP |
296 | 1000)) |
297 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
298 | ||
299 | if (turn_off_dac) { | |
ca54b810 VS |
300 | I915_WRITE(crt->adpa_reg, save_adpa); |
301 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 302 | } |
a4a6b901 ZW |
303 | } |
304 | ||
2c07245f | 305 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 306 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 307 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
308 | ret = true; |
309 | else | |
310 | ret = false; | |
e7dbb2f2 | 311 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 312 | |
2c07245f | 313 | return ret; |
79e53945 JB |
314 | } |
315 | ||
7d2c24e8 JB |
316 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
317 | { | |
318 | struct drm_device *dev = connector->dev; | |
ca54b810 | 319 | struct intel_crt *crt = intel_attached_crt(connector); |
7d2c24e8 JB |
320 | struct drm_i915_private *dev_priv = dev->dev_private; |
321 | u32 adpa; | |
322 | bool ret; | |
323 | u32 save_adpa; | |
324 | ||
ca54b810 | 325 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
326 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
327 | ||
328 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
329 | ||
ca54b810 | 330 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 331 | |
ca54b810 | 332 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
7d2c24e8 JB |
333 | 1000)) { |
334 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
ca54b810 | 335 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
336 | } |
337 | ||
338 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 339 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
340 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
341 | ret = true; | |
342 | else | |
343 | ret = false; | |
344 | ||
345 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
346 | ||
7d2c24e8 JB |
347 | return ret; |
348 | } | |
349 | ||
79e53945 JB |
350 | /** |
351 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
352 | * | |
353 | * Not for i915G/i915GM | |
354 | * | |
355 | * \return true if CRT is connected. | |
356 | * \return false if CRT is disconnected. | |
357 | */ | |
358 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
359 | { | |
360 | struct drm_device *dev = connector->dev; | |
361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0706f17c | 362 | u32 stat; |
7a772c49 | 363 | bool ret = false; |
771cb081 | 364 | int i, tries = 0; |
2c07245f | 365 | |
bad720ff | 366 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 367 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 368 | |
7d2c24e8 JB |
369 | if (IS_VALLEYVIEW(dev)) |
370 | return valleyview_crt_detect_hotplug(connector); | |
371 | ||
771cb081 ZY |
372 | /* |
373 | * On 4 series desktop, CRT detect sequence need to be done twice | |
374 | * to get a reliable result. | |
375 | */ | |
79e53945 | 376 | |
771cb081 ZY |
377 | if (IS_G4X(dev) && !IS_GM45(dev)) |
378 | tries = 2; | |
379 | else | |
380 | tries = 1; | |
771cb081 | 381 | |
771cb081 | 382 | for (i = 0; i < tries ; i++) { |
771cb081 | 383 | /* turn on the FORCE_DETECT */ |
0706f17c EE |
384 | i915_hotplug_interrupt_update(dev_priv, |
385 | CRT_HOTPLUG_FORCE_DETECT, | |
386 | CRT_HOTPLUG_FORCE_DETECT); | |
771cb081 | 387 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
388 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
389 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 390 | 1000)) |
79077319 | 391 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 392 | } |
79e53945 | 393 | |
7a772c49 AJ |
394 | stat = I915_READ(PORT_HOTPLUG_STAT); |
395 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
396 | ret = true; | |
397 | ||
398 | /* clear the interrupt we just generated, if any */ | |
399 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 400 | |
0706f17c | 401 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
7a772c49 AJ |
402 | |
403 | return ret; | |
79e53945 JB |
404 | } |
405 | ||
f1a2f5b7 JN |
406 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
407 | struct i2c_adapter *i2c) | |
408 | { | |
409 | struct edid *edid; | |
410 | ||
411 | edid = drm_get_edid(connector, i2c); | |
412 | ||
413 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
414 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
415 | intel_gmbus_force_bit(i2c, true); | |
416 | edid = drm_get_edid(connector, i2c); | |
417 | intel_gmbus_force_bit(i2c, false); | |
418 | } | |
419 | ||
420 | return edid; | |
421 | } | |
422 | ||
423 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
424 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
425 | struct i2c_adapter *adapter) | |
426 | { | |
427 | struct edid *edid; | |
ebda95a9 | 428 | int ret; |
f1a2f5b7 JN |
429 | |
430 | edid = intel_crt_get_edid(connector, adapter); | |
431 | if (!edid) | |
432 | return 0; | |
433 | ||
ebda95a9 JN |
434 | ret = intel_connector_update_modes(connector, edid); |
435 | kfree(edid); | |
436 | ||
437 | return ret; | |
f1a2f5b7 JN |
438 | } |
439 | ||
f5afcd3d | 440 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 441 | { |
f5afcd3d | 442 | struct intel_crt *crt = intel_attached_crt(connector); |
c9a1c4cd | 443 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
a2bd1f54 DV |
444 | struct edid *edid; |
445 | struct i2c_adapter *i2c; | |
79e53945 | 446 | |
a2bd1f54 | 447 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 448 | |
41aa3448 | 449 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 450 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
451 | |
452 | if (edid) { | |
453 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 454 | |
f5afcd3d DM |
455 | /* |
456 | * This may be a DVI-I connector with a shared DDC | |
457 | * link between analog and digital outputs, so we | |
458 | * have to check the EDID input spec of the attached device. | |
459 | */ | |
f5afcd3d DM |
460 | if (!is_digital) { |
461 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
462 | return true; | |
463 | } | |
a2bd1f54 DV |
464 | |
465 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
466 | } else { | |
467 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
468 | } |
469 | ||
a2bd1f54 DV |
470 | kfree(edid); |
471 | ||
6ec3d0c0 | 472 | return false; |
79e53945 JB |
473 | } |
474 | ||
e4a5d54f | 475 | static enum drm_connector_status |
7173188d | 476 | intel_crt_load_detect(struct intel_crt *crt) |
e4a5d54f | 477 | { |
7173188d | 478 | struct drm_device *dev = crt->base.base.dev; |
e4a5d54f | 479 | struct drm_i915_private *dev_priv = dev->dev_private; |
7173188d | 480 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
e4a5d54f ML |
481 | uint32_t save_bclrpat; |
482 | uint32_t save_vtotal; | |
483 | uint32_t vtotal, vactive; | |
484 | uint32_t vsample; | |
485 | uint32_t vblank, vblank_start, vblank_end; | |
486 | uint32_t dsl; | |
f0f59a00 VS |
487 | i915_reg_t bclrpat_reg, vtotal_reg, |
488 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; | |
e4a5d54f ML |
489 | uint8_t st00; |
490 | enum drm_connector_status status; | |
491 | ||
6ec3d0c0 CW |
492 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
493 | ||
9db4a9c7 JB |
494 | bclrpat_reg = BCLRPAT(pipe); |
495 | vtotal_reg = VTOTAL(pipe); | |
496 | vblank_reg = VBLANK(pipe); | |
497 | vsync_reg = VSYNC(pipe); | |
498 | pipeconf_reg = PIPECONF(pipe); | |
499 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
500 | |
501 | save_bclrpat = I915_READ(bclrpat_reg); | |
502 | save_vtotal = I915_READ(vtotal_reg); | |
503 | vblank = I915_READ(vblank_reg); | |
504 | ||
505 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
506 | vactive = (save_vtotal & 0x7ff) + 1; | |
507 | ||
508 | vblank_start = (vblank & 0xfff) + 1; | |
509 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
510 | ||
511 | /* Set the border color to purple. */ | |
512 | I915_WRITE(bclrpat_reg, 0x500050); | |
513 | ||
a6c45cf0 | 514 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
515 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
516 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 517 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
518 | /* Wait for next Vblank to substitue |
519 | * border color for Color info */ | |
9d0498a2 | 520 | intel_wait_for_vblank(dev, pipe); |
f0f59a00 | 521 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
522 | status = ((st00 & (1 << 4)) != 0) ? |
523 | connector_status_connected : | |
524 | connector_status_disconnected; | |
525 | ||
526 | I915_WRITE(pipeconf_reg, pipeconf); | |
527 | } else { | |
528 | bool restore_vblank = false; | |
529 | int count, detect; | |
530 | ||
531 | /* | |
532 | * If there isn't any border, add some. | |
533 | * Yes, this will flicker | |
534 | */ | |
535 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
536 | uint32_t vsync = I915_READ(vsync_reg); | |
537 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
538 | ||
539 | vblank_start = vsync_start; | |
540 | I915_WRITE(vblank_reg, | |
541 | (vblank_start - 1) | | |
542 | ((vblank_end - 1) << 16)); | |
543 | restore_vblank = true; | |
544 | } | |
545 | /* sample in the vertical border, selecting the larger one */ | |
546 | if (vblank_start - vactive >= vtotal - vblank_end) | |
547 | vsample = (vblank_start + vactive) >> 1; | |
548 | else | |
549 | vsample = (vtotal + vblank_end) >> 1; | |
550 | ||
551 | /* | |
552 | * Wait for the border to be displayed | |
553 | */ | |
554 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
555 | ; | |
556 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
557 | ; | |
558 | /* | |
559 | * Watch ST00 for an entire scanline | |
560 | */ | |
561 | detect = 0; | |
562 | count = 0; | |
563 | do { | |
564 | count++; | |
565 | /* Read the ST00 VGA status register */ | |
f0f59a00 | 566 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
567 | if (st00 & (1 << 4)) |
568 | detect++; | |
569 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
570 | ||
571 | /* restore vblank if necessary */ | |
572 | if (restore_vblank) | |
573 | I915_WRITE(vblank_reg, vblank); | |
574 | /* | |
575 | * If more than 3/4 of the scanline detected a monitor, | |
576 | * then it is assumed to be present. This works even on i830, | |
577 | * where there isn't any way to force the border color across | |
578 | * the screen | |
579 | */ | |
580 | status = detect * 4 > count * 3 ? | |
581 | connector_status_connected : | |
582 | connector_status_disconnected; | |
583 | } | |
584 | ||
585 | /* Restore previous settings */ | |
586 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
587 | ||
588 | return status; | |
589 | } | |
590 | ||
7b334fcb | 591 | static enum drm_connector_status |
930a9e28 | 592 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
593 | { |
594 | struct drm_device *dev = connector->dev; | |
c19a0df2 | 595 | struct drm_i915_private *dev_priv = dev->dev_private; |
c9a1c4cd | 596 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 ID |
597 | struct intel_encoder *intel_encoder = &crt->base; |
598 | enum intel_display_power_domain power_domain; | |
e4a5d54f | 599 | enum drm_connector_status status; |
e95c8438 | 600 | struct intel_load_detect_pipe tmp; |
51fd371b | 601 | struct drm_modeset_acquire_ctx ctx; |
79e53945 | 602 | |
164c8598 | 603 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 604 | connector->base.id, connector->name, |
164c8598 CW |
605 | force); |
606 | ||
671dedd2 ID |
607 | power_domain = intel_display_port_power_domain(intel_encoder); |
608 | intel_display_power_get(dev_priv, power_domain); | |
609 | ||
a6c45cf0 | 610 | if (I915_HAS_HOTPLUG(dev)) { |
aaa37730 DV |
611 | /* We can not rely on the HPD pin always being correctly wired |
612 | * up, for example many KVM do not pass it through, and so | |
613 | * only trust an assertion that the monitor is connected. | |
614 | */ | |
6ec3d0c0 CW |
615 | if (intel_crt_detect_hotplug(connector)) { |
616 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
617 | status = connector_status_connected; |
618 | goto out; | |
aaa37730 | 619 | } else |
e7dbb2f2 | 620 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
621 | } |
622 | ||
c19a0df2 PZ |
623 | if (intel_crt_detect_ddc(connector)) { |
624 | status = connector_status_connected; | |
625 | goto out; | |
626 | } | |
79e53945 | 627 | |
aaa37730 DV |
628 | /* Load detection is broken on HPD capable machines. Whoever wants a |
629 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
630 | * to have the right resistors for HP detection) needs to fix this up. | |
631 | * For now just bail out. */ | |
5bedeb2d | 632 | if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { |
c19a0df2 PZ |
633 | status = connector_status_disconnected; |
634 | goto out; | |
635 | } | |
aaa37730 | 636 | |
c19a0df2 PZ |
637 | if (!force) { |
638 | status = connector->status; | |
639 | goto out; | |
640 | } | |
7b334fcb | 641 | |
208bf9fd VS |
642 | drm_modeset_acquire_init(&ctx, 0); |
643 | ||
e4a5d54f | 644 | /* for pre-945g platforms use load detect */ |
51fd371b | 645 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
e95c8438 DV |
646 | if (intel_crt_detect_ddc(connector)) |
647 | status = connector_status_connected; | |
5bedeb2d | 648 | else if (INTEL_INFO(dev)->gen < 4) |
e95c8438 | 649 | status = intel_crt_load_detect(crt); |
5bedeb2d DV |
650 | else |
651 | status = connector_status_unknown; | |
49172fee | 652 | intel_release_load_detect_pipe(connector, &tmp, &ctx); |
e95c8438 DV |
653 | } else |
654 | status = connector_status_unknown; | |
e4a5d54f | 655 | |
208bf9fd VS |
656 | drm_modeset_drop_locks(&ctx); |
657 | drm_modeset_acquire_fini(&ctx); | |
658 | ||
c19a0df2 | 659 | out: |
671dedd2 | 660 | intel_display_power_put(dev_priv, power_domain); |
e4a5d54f | 661 | return status; |
79e53945 JB |
662 | } |
663 | ||
664 | static void intel_crt_destroy(struct drm_connector *connector) | |
665 | { | |
79e53945 JB |
666 | drm_connector_cleanup(connector); |
667 | kfree(connector); | |
668 | } | |
669 | ||
670 | static int intel_crt_get_modes(struct drm_connector *connector) | |
671 | { | |
8e4d36b9 | 672 | struct drm_device *dev = connector->dev; |
f899fc64 | 673 | struct drm_i915_private *dev_priv = dev->dev_private; |
671dedd2 ID |
674 | struct intel_crt *crt = intel_attached_crt(connector); |
675 | struct intel_encoder *intel_encoder = &crt->base; | |
676 | enum intel_display_power_domain power_domain; | |
890f3359 | 677 | int ret; |
3bd7d909 | 678 | struct i2c_adapter *i2c; |
8e4d36b9 | 679 | |
671dedd2 ID |
680 | power_domain = intel_display_port_power_domain(intel_encoder); |
681 | intel_display_power_get(dev_priv, power_domain); | |
682 | ||
41aa3448 | 683 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 684 | ret = intel_crt_ddc_get_modes(connector, i2c); |
8e4d36b9 | 685 | if (ret || !IS_G4X(dev)) |
671dedd2 | 686 | goto out; |
8e4d36b9 | 687 | |
8e4d36b9 | 688 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
988c7015 | 689 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
671dedd2 ID |
690 | ret = intel_crt_ddc_get_modes(connector, i2c); |
691 | ||
692 | out: | |
693 | intel_display_power_put(dev_priv, power_domain); | |
694 | ||
695 | return ret; | |
79e53945 JB |
696 | } |
697 | ||
698 | static int intel_crt_set_property(struct drm_connector *connector, | |
699 | struct drm_property *property, | |
700 | uint64_t value) | |
701 | { | |
79e53945 JB |
702 | return 0; |
703 | } | |
704 | ||
f3269058 CW |
705 | static void intel_crt_reset(struct drm_connector *connector) |
706 | { | |
707 | struct drm_device *dev = connector->dev; | |
2e938892 | 708 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3269058 CW |
709 | struct intel_crt *crt = intel_attached_crt(connector); |
710 | ||
10603caa | 711 | if (INTEL_INFO(dev)->gen >= 5) { |
2e938892 DV |
712 | u32 adpa; |
713 | ||
ca54b810 | 714 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
715 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
716 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
717 | I915_WRITE(crt->adpa_reg, adpa); |
718 | POSTING_READ(crt->adpa_reg); | |
2e938892 | 719 | |
0039a4b3 | 720 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
f3269058 | 721 | crt->force_hotplug_required = 1; |
2e938892 DV |
722 | } |
723 | ||
f3269058 CW |
724 | } |
725 | ||
79e53945 JB |
726 | /* |
727 | * Routines for controlling stuff on the analog port | |
728 | */ | |
729 | ||
79e53945 | 730 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
f3269058 | 731 | .reset = intel_crt_reset, |
4d688a2a | 732 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 JB |
733 | .detect = intel_crt_detect, |
734 | .fill_modes = drm_helper_probe_single_connector_modes, | |
735 | .destroy = intel_crt_destroy, | |
736 | .set_property = intel_crt_set_property, | |
c6f95f27 | 737 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 738 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
2545e4a6 | 739 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 JB |
740 | }; |
741 | ||
742 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
743 | .mode_valid = intel_crt_mode_valid, | |
744 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 745 | .best_encoder = intel_best_encoder, |
79e53945 JB |
746 | }; |
747 | ||
79e53945 | 748 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 749 | .destroy = intel_encoder_destroy, |
79e53945 JB |
750 | }; |
751 | ||
bbe1c274 | 752 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
8ca4013d | 753 | { |
bc0daf48 | 754 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
755 | return 1; |
756 | } | |
757 | ||
758 | static const struct dmi_system_id intel_no_crt[] = { | |
759 | { | |
760 | .callback = intel_no_crt_dmi_callback, | |
761 | .ident = "ACER ZGB", | |
762 | .matches = { | |
763 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
764 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
765 | }, | |
766 | }, | |
10b6ee4a GC |
767 | { |
768 | .callback = intel_no_crt_dmi_callback, | |
769 | .ident = "DELL XPS 8700", | |
770 | .matches = { | |
771 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
772 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), | |
773 | }, | |
774 | }, | |
8ca4013d DL |
775 | { } |
776 | }; | |
777 | ||
79e53945 JB |
778 | void intel_crt_init(struct drm_device *dev) |
779 | { | |
780 | struct drm_connector *connector; | |
c9a1c4cd | 781 | struct intel_crt *crt; |
454c1ca8 | 782 | struct intel_connector *intel_connector; |
db545019 | 783 | struct drm_i915_private *dev_priv = dev->dev_private; |
6c03a6bd VS |
784 | i915_reg_t adpa_reg; |
785 | u32 adpa; | |
79e53945 | 786 | |
8ca4013d DL |
787 | /* Skip machines without VGA that falsely report hotplug events */ |
788 | if (dmi_check_system(intel_no_crt)) | |
789 | return; | |
790 | ||
6c03a6bd VS |
791 | if (HAS_PCH_SPLIT(dev)) |
792 | adpa_reg = PCH_ADPA; | |
793 | else if (IS_VALLEYVIEW(dev)) | |
794 | adpa_reg = VLV_ADPA; | |
795 | else | |
796 | adpa_reg = ADPA; | |
797 | ||
798 | adpa = I915_READ(adpa_reg); | |
799 | if ((adpa & ADPA_DAC_ENABLE) == 0) { | |
800 | /* | |
801 | * On some machines (some IVB at least) CRT can be | |
802 | * fused off, but there's no known fuse bit to | |
803 | * indicate that. On these machine the ADPA register | |
804 | * works normally, except the DAC enable bit won't | |
805 | * take. So the only way to tell is attempt to enable | |
806 | * it and see what happens. | |
807 | */ | |
808 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | | |
809 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | |
810 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) | |
811 | return; | |
812 | I915_WRITE(adpa_reg, adpa); | |
813 | } | |
814 | ||
c9a1c4cd CW |
815 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
816 | if (!crt) | |
79e53945 JB |
817 | return; |
818 | ||
9bdbd0b9 | 819 | intel_connector = intel_connector_alloc(); |
454c1ca8 | 820 | if (!intel_connector) { |
c9a1c4cd | 821 | kfree(crt); |
454c1ca8 ZW |
822 | return; |
823 | } | |
824 | ||
825 | connector = &intel_connector->base; | |
637f44d2 | 826 | crt->connector = intel_connector; |
454c1ca8 | 827 | drm_connector_init(dev, &intel_connector->base, |
79e53945 JB |
828 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
829 | ||
c9a1c4cd | 830 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
13a3d91f | 831 | DRM_MODE_ENCODER_DAC, NULL); |
79e53945 | 832 | |
c9a1c4cd | 833 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 834 | |
c9a1c4cd | 835 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 836 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
d63fa0dc | 837 | if (IS_I830(dev)) |
59c859d6 ED |
838 | crt->base.crtc_mask = (1 << 0); |
839 | else | |
0826874a | 840 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 841 | |
dbb02575 DV |
842 | if (IS_GEN2(dev)) |
843 | connector->interlace_allowed = 0; | |
844 | else | |
845 | connector->interlace_allowed = 1; | |
79e53945 JB |
846 | connector->doublescan_allowed = 0; |
847 | ||
6c03a6bd | 848 | crt->adpa_reg = adpa_reg; |
540a8950 | 849 | |
5bfe2ac0 | 850 | crt->base.compute_config = intel_crt_compute_config; |
92966a37 | 851 | if (HAS_PCH_SPLIT(dev)) { |
1ea56e26 VS |
852 | crt->base.disable = pch_disable_crt; |
853 | crt->base.post_disable = pch_post_disable_crt; | |
854 | } else { | |
855 | crt->base.disable = intel_disable_crt; | |
856 | } | |
2124604b | 857 | crt->base.enable = intel_enable_crt; |
1d843f9d EE |
858 | if (I915_HAS_HOTPLUG(dev)) |
859 | crt->base.hpd_pin = HPD_CRT; | |
a2985791 VS |
860 | if (HAS_DDI(dev)) { |
861 | crt->base.get_config = hsw_crt_get_config; | |
4eda01b2 | 862 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
a2985791 VS |
863 | } else { |
864 | crt->base.get_config = intel_crt_get_config; | |
4eda01b2 | 865 | crt->base.get_hw_state = intel_crt_get_hw_state; |
a2985791 | 866 | } |
e403fc94 | 867 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 868 | intel_connector->unregister = intel_connector_unregister; |
df0323c4 | 869 | |
79e53945 JB |
870 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
871 | ||
34ea3d38 | 872 | drm_connector_register(connector); |
b01f2c3a | 873 | |
821450c6 EE |
874 | if (!I915_HAS_HOTPLUG(dev)) |
875 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
eb1f8e4f | 876 | |
e7dbb2f2 KP |
877 | /* |
878 | * Configure the automatic hotplug detection stuff | |
879 | */ | |
880 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 881 | |
68d18ad7 | 882 | /* |
3e68320e DL |
883 | * TODO: find a proper way to discover whether we need to set the the |
884 | * polarity and link reversal bits or not, instead of relying on the | |
885 | * BIOS. | |
68d18ad7 | 886 | */ |
3e68320e DL |
887 | if (HAS_PCH_LPT(dev)) { |
888 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | | |
889 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
890 | ||
eede3b53 | 891 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
3e68320e | 892 | } |
754970ee DV |
893 | |
894 | intel_crt_reset(connector); | |
79e53945 | 895 | } |