Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 | 30 | #include <drm/drmP.h> |
c6f95f27 | 31 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
79e53945 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
79e53945 JB |
37 | #include "i915_drv.h" |
38 | ||
e7dbb2f2 KP |
39 | /* Here's the desired hotplug mode */ |
40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
45 | ADPA_CRT_HOTPLUG_ENABLE) | |
46 | ||
c9a1c4cd CW |
47 | struct intel_crt { |
48 | struct intel_encoder base; | |
637f44d2 AJ |
49 | /* DPMS state is stored in the connector, which we need in the |
50 | * encoder's enable/disable callbacks */ | |
51 | struct intel_connector *connector; | |
e7dbb2f2 | 52 | bool force_hotplug_required; |
540a8950 | 53 | u32 adpa_reg; |
c9a1c4cd CW |
54 | }; |
55 | ||
eebe6f0b | 56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 57 | { |
eebe6f0b | 58 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
59 | } |
60 | ||
eebe6f0b | 61 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 62 | { |
eebe6f0b | 63 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
64 | } |
65 | ||
e403fc94 DV |
66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
67 | enum pipe *pipe) | |
79e53945 | 68 | { |
e403fc94 | 69 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
e403fc94 | 71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
6d129bea | 72 | enum intel_display_power_domain power_domain; |
e403fc94 DV |
73 | u32 tmp; |
74 | ||
6d129bea | 75 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 76 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
77 | return false; |
78 | ||
e403fc94 DV |
79 | tmp = I915_READ(crt->adpa_reg); |
80 | ||
81 | if (!(tmp & ADPA_DAC_ENABLE)) | |
82 | return false; | |
83 | ||
84 | if (HAS_PCH_CPT(dev)) | |
85 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
86 | else | |
87 | *pipe = PORT_TO_PIPE(tmp); | |
88 | ||
89 | return true; | |
90 | } | |
91 | ||
6801c18c | 92 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 JB |
93 | { |
94 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
95 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
96 | u32 tmp, flags = 0; | |
97 | ||
98 | tmp = I915_READ(crt->adpa_reg); | |
99 | ||
100 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
101 | flags |= DRM_MODE_FLAG_PHSYNC; | |
102 | else | |
103 | flags |= DRM_MODE_FLAG_NHSYNC; | |
104 | ||
105 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
106 | flags |= DRM_MODE_FLAG_PVSYNC; | |
107 | else | |
108 | flags |= DRM_MODE_FLAG_NVSYNC; | |
109 | ||
6801c18c VS |
110 | return flags; |
111 | } | |
112 | ||
113 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 114 | struct intel_crtc_state *pipe_config) |
6801c18c VS |
115 | { |
116 | struct drm_device *dev = encoder->base.dev; | |
117 | int dotclock; | |
118 | ||
2d112de7 | 119 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 VS |
120 | |
121 | dotclock = pipe_config->port_clock; | |
122 | ||
6801c18c | 123 | if (HAS_PCH_SPLIT(dev)) |
18442d08 VS |
124 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
125 | ||
2d112de7 | 126 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
127 | } |
128 | ||
6801c18c | 129 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 130 | struct intel_crtc_state *pipe_config) |
6801c18c VS |
131 | { |
132 | intel_ddi_get_config(encoder, pipe_config); | |
133 | ||
2d112de7 | 134 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
135 | DRM_MODE_FLAG_NHSYNC | |
136 | DRM_MODE_FLAG_PVSYNC | | |
137 | DRM_MODE_FLAG_NVSYNC); | |
2d112de7 | 138 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
6801c18c VS |
139 | } |
140 | ||
082717ea DV |
141 | static void hsw_crt_pre_enable(struct intel_encoder *encoder) |
142 | { | |
143 | struct drm_device *dev = encoder->base.dev; | |
144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
145 | ||
146 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); | |
147 | I915_WRITE(SPLL_CTL, | |
148 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); | |
149 | POSTING_READ(SPLL_CTL); | |
150 | udelay(20); | |
151 | } | |
152 | ||
b2cabb0e DV |
153 | /* Note: The caller is required to filter out dpms modes not supported by the |
154 | * platform. */ | |
155 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) | |
df0323c4 | 156 | { |
b2cabb0e | 157 | struct drm_device *dev = encoder->base.dev; |
df0323c4 | 158 | struct drm_i915_private *dev_priv = dev->dev_private; |
b2cabb0e | 159 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
894ed1ec | 160 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
6e3c9717 | 161 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
894ed1ec DV |
162 | u32 adpa; |
163 | ||
164 | if (INTEL_INFO(dev)->gen >= 5) | |
165 | adpa = ADPA_HOTPLUG_BITS; | |
166 | else | |
167 | adpa = 0; | |
df0323c4 | 168 | |
894ed1ec DV |
169 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
170 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
171 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
172 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
173 | ||
174 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
175 | if (HAS_PCH_LPT(dev)) | |
176 | ; /* Those bits don't exist here */ | |
177 | else if (HAS_PCH_CPT(dev)) | |
178 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); | |
179 | else if (crtc->pipe == 0) | |
180 | adpa |= ADPA_PIPE_A_SELECT; | |
181 | else | |
182 | adpa |= ADPA_PIPE_B_SELECT; | |
183 | ||
184 | if (!HAS_PCH_SPLIT(dev)) | |
185 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
79e53945 | 186 | |
0206e353 | 187 | switch (mode) { |
79e53945 | 188 | case DRM_MODE_DPMS_ON: |
894ed1ec | 189 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
190 | break; |
191 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 192 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
193 | break; |
194 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 195 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
196 | break; |
197 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 198 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
199 | break; |
200 | } | |
201 | ||
894ed1ec | 202 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 203 | } |
2c07245f | 204 | |
637f44d2 AJ |
205 | static void intel_disable_crt(struct intel_encoder *encoder) |
206 | { | |
207 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); | |
208 | } | |
209 | ||
1ea56e26 VS |
210 | static void pch_disable_crt(struct intel_encoder *encoder) |
211 | { | |
212 | } | |
213 | ||
214 | static void pch_post_disable_crt(struct intel_encoder *encoder) | |
215 | { | |
216 | intel_disable_crt(encoder); | |
217 | } | |
abfdc1e3 DV |
218 | |
219 | static void hsw_crt_post_disable(struct intel_encoder *encoder) | |
220 | { | |
221 | struct drm_device *dev = encoder->base.dev; | |
222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
223 | uint32_t val; | |
224 | ||
225 | DRM_DEBUG_KMS("Disabling SPLL\n"); | |
226 | val = I915_READ(SPLL_CTL); | |
227 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | |
228 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
229 | POSTING_READ(SPLL_CTL); | |
230 | } | |
231 | ||
637f44d2 AJ |
232 | static void intel_enable_crt(struct intel_encoder *encoder) |
233 | { | |
234 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
235 | ||
236 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); | |
237 | } | |
238 | ||
6b1c087b | 239 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
9a69a9ac | 240 | static int intel_crt_dpms(struct drm_connector *connector, int mode) |
df0323c4 | 241 | { |
b2cabb0e DV |
242 | struct drm_device *dev = connector->dev; |
243 | struct intel_encoder *encoder = intel_attached_encoder(connector); | |
244 | struct drm_crtc *crtc; | |
245 | int old_dpms; | |
79e53945 | 246 | |
b2cabb0e | 247 | /* PCH platforms and VLV only support on/off. */ |
4a8dece2 | 248 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
bd9e8413 JB |
249 | mode = DRM_MODE_DPMS_OFF; |
250 | ||
b2cabb0e | 251 | if (mode == connector->dpms) |
9a69a9ac | 252 | return 0; |
b2cabb0e DV |
253 | |
254 | old_dpms = connector->dpms; | |
255 | connector->dpms = mode; | |
256 | ||
257 | /* Only need to change hw state when actually enabled */ | |
258 | crtc = encoder->base.crtc; | |
259 | if (!crtc) { | |
260 | encoder->connectors_active = false; | |
9a69a9ac | 261 | return 0; |
79e53945 JB |
262 | } |
263 | ||
b2cabb0e DV |
264 | /* We need the pipe to run for anything but OFF. */ |
265 | if (mode == DRM_MODE_DPMS_OFF) | |
266 | encoder->connectors_active = false; | |
267 | else | |
268 | encoder->connectors_active = true; | |
269 | ||
6b1c087b JN |
270 | /* We call connector dpms manually below in case pipe dpms doesn't |
271 | * change due to cloning. */ | |
b2cabb0e DV |
272 | if (mode < old_dpms) { |
273 | /* From off to on, enable the pipe first. */ | |
274 | intel_crtc_update_dpms(crtc); | |
275 | ||
276 | intel_crt_set_dpms(encoder, mode); | |
277 | } else { | |
278 | intel_crt_set_dpms(encoder, mode); | |
279 | ||
280 | intel_crtc_update_dpms(crtc); | |
281 | } | |
0a91ca29 | 282 | |
9a69a9ac | 283 | return 0; |
79e53945 JB |
284 | } |
285 | ||
c19de8eb DL |
286 | static enum drm_mode_status |
287 | intel_crt_mode_valid(struct drm_connector *connector, | |
288 | struct drm_display_mode *mode) | |
79e53945 | 289 | { |
6bcdcd9e ZY |
290 | struct drm_device *dev = connector->dev; |
291 | ||
292 | int max_clock = 0; | |
79e53945 JB |
293 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
294 | return MODE_NO_DBLESCAN; | |
295 | ||
6bcdcd9e ZY |
296 | if (mode->clock < 25000) |
297 | return MODE_CLOCK_LOW; | |
298 | ||
a6c45cf0 | 299 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
300 | max_clock = 350000; |
301 | else | |
302 | max_clock = 400000; | |
303 | if (mode->clock > max_clock) | |
304 | return MODE_CLOCK_HIGH; | |
79e53945 | 305 | |
d4b1931c PZ |
306 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
307 | if (HAS_PCH_LPT(dev) && | |
308 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) | |
309 | return MODE_CLOCK_HIGH; | |
310 | ||
79e53945 JB |
311 | return MODE_OK; |
312 | } | |
313 | ||
5bfe2ac0 | 314 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
5cec258b | 315 | struct intel_crtc_state *pipe_config) |
79e53945 | 316 | { |
5bfe2ac0 DV |
317 | struct drm_device *dev = encoder->base.dev; |
318 | ||
319 | if (HAS_PCH_SPLIT(dev)) | |
320 | pipe_config->has_pch_encoder = true; | |
321 | ||
2a7aceec DV |
322 | /* LPT FDI RX only supports 8bpc. */ |
323 | if (HAS_PCH_LPT(dev)) | |
324 | pipe_config->pipe_bpp = 24; | |
325 | ||
8f7abfd8 | 326 | /* FDI must always be 2.7 GHz */ |
0e50338c DV |
327 | if (HAS_DDI(dev)) { |
328 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
8f7abfd8 | 329 | pipe_config->port_clock = 135000 * 2; |
0e50338c | 330 | } |
8f7abfd8 | 331 | |
79e53945 JB |
332 | return true; |
333 | } | |
334 | ||
f2b115e6 | 335 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
336 | { |
337 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 338 | struct intel_crt *crt = intel_attached_crt(connector); |
2c07245f | 339 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7dbb2f2 | 340 | u32 adpa; |
2c07245f ZW |
341 | bool ret; |
342 | ||
e7dbb2f2 KP |
343 | /* The first time through, trigger an explicit detection cycle */ |
344 | if (crt->force_hotplug_required) { | |
345 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
346 | u32 save_adpa; | |
67941da2 | 347 | |
e7dbb2f2 KP |
348 | crt->force_hotplug_required = 0; |
349 | ||
ca54b810 | 350 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
351 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
352 | ||
353 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
354 | if (turn_off_dac) | |
355 | adpa &= ~ADPA_DAC_ENABLE; | |
356 | ||
ca54b810 | 357 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 358 | |
ca54b810 | 359 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
e7dbb2f2 KP |
360 | 1000)) |
361 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
362 | ||
363 | if (turn_off_dac) { | |
ca54b810 VS |
364 | I915_WRITE(crt->adpa_reg, save_adpa); |
365 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 366 | } |
a4a6b901 ZW |
367 | } |
368 | ||
2c07245f | 369 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 370 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 371 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
372 | ret = true; |
373 | else | |
374 | ret = false; | |
e7dbb2f2 | 375 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 376 | |
2c07245f | 377 | return ret; |
79e53945 JB |
378 | } |
379 | ||
7d2c24e8 JB |
380 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
381 | { | |
382 | struct drm_device *dev = connector->dev; | |
ca54b810 | 383 | struct intel_crt *crt = intel_attached_crt(connector); |
7d2c24e8 JB |
384 | struct drm_i915_private *dev_priv = dev->dev_private; |
385 | u32 adpa; | |
386 | bool ret; | |
387 | u32 save_adpa; | |
388 | ||
ca54b810 | 389 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
390 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
391 | ||
392 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
393 | ||
ca54b810 | 394 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 395 | |
ca54b810 | 396 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
7d2c24e8 JB |
397 | 1000)) { |
398 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
ca54b810 | 399 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
400 | } |
401 | ||
402 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 403 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
404 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
405 | ret = true; | |
406 | else | |
407 | ret = false; | |
408 | ||
409 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
410 | ||
7d2c24e8 JB |
411 | return ret; |
412 | } | |
413 | ||
79e53945 JB |
414 | /** |
415 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
416 | * | |
417 | * Not for i915G/i915GM | |
418 | * | |
419 | * \return true if CRT is connected. | |
420 | * \return false if CRT is disconnected. | |
421 | */ | |
422 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
423 | { | |
424 | struct drm_device *dev = connector->dev; | |
425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a772c49 AJ |
426 | u32 hotplug_en, orig, stat; |
427 | bool ret = false; | |
771cb081 | 428 | int i, tries = 0; |
2c07245f | 429 | |
bad720ff | 430 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 431 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 432 | |
7d2c24e8 JB |
433 | if (IS_VALLEYVIEW(dev)) |
434 | return valleyview_crt_detect_hotplug(connector); | |
435 | ||
771cb081 ZY |
436 | /* |
437 | * On 4 series desktop, CRT detect sequence need to be done twice | |
438 | * to get a reliable result. | |
439 | */ | |
79e53945 | 440 | |
771cb081 ZY |
441 | if (IS_G4X(dev) && !IS_GM45(dev)) |
442 | tries = 2; | |
443 | else | |
444 | tries = 1; | |
7a772c49 | 445 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
771cb081 ZY |
446 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
447 | ||
771cb081 | 448 | for (i = 0; i < tries ; i++) { |
771cb081 ZY |
449 | /* turn on the FORCE_DETECT */ |
450 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
771cb081 | 451 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
452 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
453 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 454 | 1000)) |
79077319 | 455 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 456 | } |
79e53945 | 457 | |
7a772c49 AJ |
458 | stat = I915_READ(PORT_HOTPLUG_STAT); |
459 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
460 | ret = true; | |
461 | ||
462 | /* clear the interrupt we just generated, if any */ | |
463 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 464 | |
7a772c49 AJ |
465 | /* and put the bits back */ |
466 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
467 | ||
468 | return ret; | |
79e53945 JB |
469 | } |
470 | ||
f1a2f5b7 JN |
471 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
472 | struct i2c_adapter *i2c) | |
473 | { | |
474 | struct edid *edid; | |
475 | ||
476 | edid = drm_get_edid(connector, i2c); | |
477 | ||
478 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
479 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
480 | intel_gmbus_force_bit(i2c, true); | |
481 | edid = drm_get_edid(connector, i2c); | |
482 | intel_gmbus_force_bit(i2c, false); | |
483 | } | |
484 | ||
485 | return edid; | |
486 | } | |
487 | ||
488 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
489 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
490 | struct i2c_adapter *adapter) | |
491 | { | |
492 | struct edid *edid; | |
ebda95a9 | 493 | int ret; |
f1a2f5b7 JN |
494 | |
495 | edid = intel_crt_get_edid(connector, adapter); | |
496 | if (!edid) | |
497 | return 0; | |
498 | ||
ebda95a9 JN |
499 | ret = intel_connector_update_modes(connector, edid); |
500 | kfree(edid); | |
501 | ||
502 | return ret; | |
f1a2f5b7 JN |
503 | } |
504 | ||
f5afcd3d | 505 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 506 | { |
f5afcd3d | 507 | struct intel_crt *crt = intel_attached_crt(connector); |
c9a1c4cd | 508 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
a2bd1f54 DV |
509 | struct edid *edid; |
510 | struct i2c_adapter *i2c; | |
79e53945 | 511 | |
a2bd1f54 | 512 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 513 | |
41aa3448 | 514 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 515 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
516 | |
517 | if (edid) { | |
518 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 519 | |
f5afcd3d DM |
520 | /* |
521 | * This may be a DVI-I connector with a shared DDC | |
522 | * link between analog and digital outputs, so we | |
523 | * have to check the EDID input spec of the attached device. | |
524 | */ | |
f5afcd3d DM |
525 | if (!is_digital) { |
526 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
527 | return true; | |
528 | } | |
a2bd1f54 DV |
529 | |
530 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
531 | } else { | |
532 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
533 | } |
534 | ||
a2bd1f54 DV |
535 | kfree(edid); |
536 | ||
6ec3d0c0 | 537 | return false; |
79e53945 JB |
538 | } |
539 | ||
e4a5d54f | 540 | static enum drm_connector_status |
7173188d | 541 | intel_crt_load_detect(struct intel_crt *crt) |
e4a5d54f | 542 | { |
7173188d | 543 | struct drm_device *dev = crt->base.base.dev; |
e4a5d54f | 544 | struct drm_i915_private *dev_priv = dev->dev_private; |
7173188d | 545 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
e4a5d54f ML |
546 | uint32_t save_bclrpat; |
547 | uint32_t save_vtotal; | |
548 | uint32_t vtotal, vactive; | |
549 | uint32_t vsample; | |
550 | uint32_t vblank, vblank_start, vblank_end; | |
551 | uint32_t dsl; | |
552 | uint32_t bclrpat_reg; | |
553 | uint32_t vtotal_reg; | |
554 | uint32_t vblank_reg; | |
555 | uint32_t vsync_reg; | |
556 | uint32_t pipeconf_reg; | |
557 | uint32_t pipe_dsl_reg; | |
558 | uint8_t st00; | |
559 | enum drm_connector_status status; | |
560 | ||
6ec3d0c0 CW |
561 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
562 | ||
9db4a9c7 JB |
563 | bclrpat_reg = BCLRPAT(pipe); |
564 | vtotal_reg = VTOTAL(pipe); | |
565 | vblank_reg = VBLANK(pipe); | |
566 | vsync_reg = VSYNC(pipe); | |
567 | pipeconf_reg = PIPECONF(pipe); | |
568 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
569 | |
570 | save_bclrpat = I915_READ(bclrpat_reg); | |
571 | save_vtotal = I915_READ(vtotal_reg); | |
572 | vblank = I915_READ(vblank_reg); | |
573 | ||
574 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
575 | vactive = (save_vtotal & 0x7ff) + 1; | |
576 | ||
577 | vblank_start = (vblank & 0xfff) + 1; | |
578 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
579 | ||
580 | /* Set the border color to purple. */ | |
581 | I915_WRITE(bclrpat_reg, 0x500050); | |
582 | ||
a6c45cf0 | 583 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
584 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
585 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 586 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
587 | /* Wait for next Vblank to substitue |
588 | * border color for Color info */ | |
9d0498a2 | 589 | intel_wait_for_vblank(dev, pipe); |
e4a5d54f ML |
590 | st00 = I915_READ8(VGA_MSR_WRITE); |
591 | status = ((st00 & (1 << 4)) != 0) ? | |
592 | connector_status_connected : | |
593 | connector_status_disconnected; | |
594 | ||
595 | I915_WRITE(pipeconf_reg, pipeconf); | |
596 | } else { | |
597 | bool restore_vblank = false; | |
598 | int count, detect; | |
599 | ||
600 | /* | |
601 | * If there isn't any border, add some. | |
602 | * Yes, this will flicker | |
603 | */ | |
604 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
605 | uint32_t vsync = I915_READ(vsync_reg); | |
606 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
607 | ||
608 | vblank_start = vsync_start; | |
609 | I915_WRITE(vblank_reg, | |
610 | (vblank_start - 1) | | |
611 | ((vblank_end - 1) << 16)); | |
612 | restore_vblank = true; | |
613 | } | |
614 | /* sample in the vertical border, selecting the larger one */ | |
615 | if (vblank_start - vactive >= vtotal - vblank_end) | |
616 | vsample = (vblank_start + vactive) >> 1; | |
617 | else | |
618 | vsample = (vtotal + vblank_end) >> 1; | |
619 | ||
620 | /* | |
621 | * Wait for the border to be displayed | |
622 | */ | |
623 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
624 | ; | |
625 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
626 | ; | |
627 | /* | |
628 | * Watch ST00 for an entire scanline | |
629 | */ | |
630 | detect = 0; | |
631 | count = 0; | |
632 | do { | |
633 | count++; | |
634 | /* Read the ST00 VGA status register */ | |
635 | st00 = I915_READ8(VGA_MSR_WRITE); | |
636 | if (st00 & (1 << 4)) | |
637 | detect++; | |
638 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
639 | ||
640 | /* restore vblank if necessary */ | |
641 | if (restore_vblank) | |
642 | I915_WRITE(vblank_reg, vblank); | |
643 | /* | |
644 | * If more than 3/4 of the scanline detected a monitor, | |
645 | * then it is assumed to be present. This works even on i830, | |
646 | * where there isn't any way to force the border color across | |
647 | * the screen | |
648 | */ | |
649 | status = detect * 4 > count * 3 ? | |
650 | connector_status_connected : | |
651 | connector_status_disconnected; | |
652 | } | |
653 | ||
654 | /* Restore previous settings */ | |
655 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
656 | ||
657 | return status; | |
658 | } | |
659 | ||
7b334fcb | 660 | static enum drm_connector_status |
930a9e28 | 661 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
662 | { |
663 | struct drm_device *dev = connector->dev; | |
c19a0df2 | 664 | struct drm_i915_private *dev_priv = dev->dev_private; |
c9a1c4cd | 665 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 ID |
666 | struct intel_encoder *intel_encoder = &crt->base; |
667 | enum intel_display_power_domain power_domain; | |
e4a5d54f | 668 | enum drm_connector_status status; |
e95c8438 | 669 | struct intel_load_detect_pipe tmp; |
51fd371b | 670 | struct drm_modeset_acquire_ctx ctx; |
79e53945 | 671 | |
164c8598 | 672 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 673 | connector->base.id, connector->name, |
164c8598 CW |
674 | force); |
675 | ||
671dedd2 ID |
676 | power_domain = intel_display_port_power_domain(intel_encoder); |
677 | intel_display_power_get(dev_priv, power_domain); | |
678 | ||
a6c45cf0 | 679 | if (I915_HAS_HOTPLUG(dev)) { |
aaa37730 DV |
680 | /* We can not rely on the HPD pin always being correctly wired |
681 | * up, for example many KVM do not pass it through, and so | |
682 | * only trust an assertion that the monitor is connected. | |
683 | */ | |
6ec3d0c0 CW |
684 | if (intel_crt_detect_hotplug(connector)) { |
685 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
686 | status = connector_status_connected; |
687 | goto out; | |
aaa37730 | 688 | } else |
e7dbb2f2 | 689 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
690 | } |
691 | ||
c19a0df2 PZ |
692 | if (intel_crt_detect_ddc(connector)) { |
693 | status = connector_status_connected; | |
694 | goto out; | |
695 | } | |
79e53945 | 696 | |
aaa37730 DV |
697 | /* Load detection is broken on HPD capable machines. Whoever wants a |
698 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
699 | * to have the right resistors for HP detection) needs to fix this up. | |
700 | * For now just bail out. */ | |
5bedeb2d | 701 | if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { |
c19a0df2 PZ |
702 | status = connector_status_disconnected; |
703 | goto out; | |
704 | } | |
aaa37730 | 705 | |
c19a0df2 PZ |
706 | if (!force) { |
707 | status = connector->status; | |
708 | goto out; | |
709 | } | |
7b334fcb | 710 | |
208bf9fd VS |
711 | drm_modeset_acquire_init(&ctx, 0); |
712 | ||
e4a5d54f | 713 | /* for pre-945g platforms use load detect */ |
51fd371b | 714 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
e95c8438 DV |
715 | if (intel_crt_detect_ddc(connector)) |
716 | status = connector_status_connected; | |
5bedeb2d | 717 | else if (INTEL_INFO(dev)->gen < 4) |
e95c8438 | 718 | status = intel_crt_load_detect(crt); |
5bedeb2d DV |
719 | else |
720 | status = connector_status_unknown; | |
49172fee | 721 | intel_release_load_detect_pipe(connector, &tmp, &ctx); |
e95c8438 DV |
722 | } else |
723 | status = connector_status_unknown; | |
e4a5d54f | 724 | |
208bf9fd VS |
725 | drm_modeset_drop_locks(&ctx); |
726 | drm_modeset_acquire_fini(&ctx); | |
727 | ||
c19a0df2 | 728 | out: |
671dedd2 | 729 | intel_display_power_put(dev_priv, power_domain); |
e4a5d54f | 730 | return status; |
79e53945 JB |
731 | } |
732 | ||
733 | static void intel_crt_destroy(struct drm_connector *connector) | |
734 | { | |
79e53945 JB |
735 | drm_connector_cleanup(connector); |
736 | kfree(connector); | |
737 | } | |
738 | ||
739 | static int intel_crt_get_modes(struct drm_connector *connector) | |
740 | { | |
8e4d36b9 | 741 | struct drm_device *dev = connector->dev; |
f899fc64 | 742 | struct drm_i915_private *dev_priv = dev->dev_private; |
671dedd2 ID |
743 | struct intel_crt *crt = intel_attached_crt(connector); |
744 | struct intel_encoder *intel_encoder = &crt->base; | |
745 | enum intel_display_power_domain power_domain; | |
890f3359 | 746 | int ret; |
3bd7d909 | 747 | struct i2c_adapter *i2c; |
8e4d36b9 | 748 | |
671dedd2 ID |
749 | power_domain = intel_display_port_power_domain(intel_encoder); |
750 | intel_display_power_get(dev_priv, power_domain); | |
751 | ||
41aa3448 | 752 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 753 | ret = intel_crt_ddc_get_modes(connector, i2c); |
8e4d36b9 | 754 | if (ret || !IS_G4X(dev)) |
671dedd2 | 755 | goto out; |
8e4d36b9 | 756 | |
8e4d36b9 | 757 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
988c7015 | 758 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
671dedd2 ID |
759 | ret = intel_crt_ddc_get_modes(connector, i2c); |
760 | ||
761 | out: | |
762 | intel_display_power_put(dev_priv, power_domain); | |
763 | ||
764 | return ret; | |
79e53945 JB |
765 | } |
766 | ||
767 | static int intel_crt_set_property(struct drm_connector *connector, | |
768 | struct drm_property *property, | |
769 | uint64_t value) | |
770 | { | |
79e53945 JB |
771 | return 0; |
772 | } | |
773 | ||
f3269058 CW |
774 | static void intel_crt_reset(struct drm_connector *connector) |
775 | { | |
776 | struct drm_device *dev = connector->dev; | |
2e938892 | 777 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3269058 CW |
778 | struct intel_crt *crt = intel_attached_crt(connector); |
779 | ||
10603caa | 780 | if (INTEL_INFO(dev)->gen >= 5) { |
2e938892 DV |
781 | u32 adpa; |
782 | ||
ca54b810 | 783 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
784 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
785 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
786 | I915_WRITE(crt->adpa_reg, adpa); |
787 | POSTING_READ(crt->adpa_reg); | |
2e938892 | 788 | |
0039a4b3 | 789 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
f3269058 | 790 | crt->force_hotplug_required = 1; |
2e938892 DV |
791 | } |
792 | ||
f3269058 CW |
793 | } |
794 | ||
79e53945 JB |
795 | /* |
796 | * Routines for controlling stuff on the analog port | |
797 | */ | |
798 | ||
79e53945 | 799 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
f3269058 | 800 | .reset = intel_crt_reset, |
b2cabb0e | 801 | .dpms = intel_crt_dpms, |
79e53945 JB |
802 | .detect = intel_crt_detect, |
803 | .fill_modes = drm_helper_probe_single_connector_modes, | |
804 | .destroy = intel_crt_destroy, | |
805 | .set_property = intel_crt_set_property, | |
c6f95f27 | 806 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 807 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
2545e4a6 | 808 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 JB |
809 | }; |
810 | ||
811 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
812 | .mode_valid = intel_crt_mode_valid, | |
813 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 814 | .best_encoder = intel_best_encoder, |
79e53945 JB |
815 | }; |
816 | ||
79e53945 | 817 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 818 | .destroy = intel_encoder_destroy, |
79e53945 JB |
819 | }; |
820 | ||
bbe1c274 | 821 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
8ca4013d | 822 | { |
bc0daf48 | 823 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
824 | return 1; |
825 | } | |
826 | ||
827 | static const struct dmi_system_id intel_no_crt[] = { | |
828 | { | |
829 | .callback = intel_no_crt_dmi_callback, | |
830 | .ident = "ACER ZGB", | |
831 | .matches = { | |
832 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
833 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
834 | }, | |
835 | }, | |
10b6ee4a GC |
836 | { |
837 | .callback = intel_no_crt_dmi_callback, | |
838 | .ident = "DELL XPS 8700", | |
839 | .matches = { | |
840 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
841 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), | |
842 | }, | |
843 | }, | |
8ca4013d DL |
844 | { } |
845 | }; | |
846 | ||
79e53945 JB |
847 | void intel_crt_init(struct drm_device *dev) |
848 | { | |
849 | struct drm_connector *connector; | |
c9a1c4cd | 850 | struct intel_crt *crt; |
454c1ca8 | 851 | struct intel_connector *intel_connector; |
db545019 | 852 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 853 | |
8ca4013d DL |
854 | /* Skip machines without VGA that falsely report hotplug events */ |
855 | if (dmi_check_system(intel_no_crt)) | |
856 | return; | |
857 | ||
c9a1c4cd CW |
858 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
859 | if (!crt) | |
79e53945 JB |
860 | return; |
861 | ||
9bdbd0b9 | 862 | intel_connector = intel_connector_alloc(); |
454c1ca8 | 863 | if (!intel_connector) { |
c9a1c4cd | 864 | kfree(crt); |
454c1ca8 ZW |
865 | return; |
866 | } | |
867 | ||
868 | connector = &intel_connector->base; | |
637f44d2 | 869 | crt->connector = intel_connector; |
454c1ca8 | 870 | drm_connector_init(dev, &intel_connector->base, |
79e53945 JB |
871 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
872 | ||
c9a1c4cd | 873 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
79e53945 JB |
874 | DRM_MODE_ENCODER_DAC); |
875 | ||
c9a1c4cd | 876 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 877 | |
c9a1c4cd | 878 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 879 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
d63fa0dc | 880 | if (IS_I830(dev)) |
59c859d6 ED |
881 | crt->base.crtc_mask = (1 << 0); |
882 | else | |
0826874a | 883 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 884 | |
dbb02575 DV |
885 | if (IS_GEN2(dev)) |
886 | connector->interlace_allowed = 0; | |
887 | else | |
888 | connector->interlace_allowed = 1; | |
79e53945 JB |
889 | connector->doublescan_allowed = 0; |
890 | ||
df0323c4 | 891 | if (HAS_PCH_SPLIT(dev)) |
540a8950 DV |
892 | crt->adpa_reg = PCH_ADPA; |
893 | else if (IS_VALLEYVIEW(dev)) | |
894 | crt->adpa_reg = VLV_ADPA; | |
df0323c4 | 895 | else |
540a8950 DV |
896 | crt->adpa_reg = ADPA; |
897 | ||
5bfe2ac0 | 898 | crt->base.compute_config = intel_crt_compute_config; |
1ea56e26 VS |
899 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) { |
900 | crt->base.disable = pch_disable_crt; | |
901 | crt->base.post_disable = pch_post_disable_crt; | |
902 | } else { | |
903 | crt->base.disable = intel_disable_crt; | |
904 | } | |
2124604b | 905 | crt->base.enable = intel_enable_crt; |
1d843f9d EE |
906 | if (I915_HAS_HOTPLUG(dev)) |
907 | crt->base.hpd_pin = HPD_CRT; | |
a2985791 VS |
908 | if (HAS_DDI(dev)) { |
909 | crt->base.get_config = hsw_crt_get_config; | |
4eda01b2 | 910 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
082717ea | 911 | crt->base.pre_enable = hsw_crt_pre_enable; |
abfdc1e3 | 912 | crt->base.post_disable = hsw_crt_post_disable; |
a2985791 VS |
913 | } else { |
914 | crt->base.get_config = intel_crt_get_config; | |
4eda01b2 | 915 | crt->base.get_hw_state = intel_crt_get_hw_state; |
a2985791 | 916 | } |
e403fc94 | 917 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 918 | intel_connector->unregister = intel_connector_unregister; |
df0323c4 | 919 | |
79e53945 JB |
920 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
921 | ||
34ea3d38 | 922 | drm_connector_register(connector); |
b01f2c3a | 923 | |
821450c6 EE |
924 | if (!I915_HAS_HOTPLUG(dev)) |
925 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
eb1f8e4f | 926 | |
e7dbb2f2 KP |
927 | /* |
928 | * Configure the automatic hotplug detection stuff | |
929 | */ | |
930 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 931 | |
68d18ad7 | 932 | /* |
3e68320e DL |
933 | * TODO: find a proper way to discover whether we need to set the the |
934 | * polarity and link reversal bits or not, instead of relying on the | |
935 | * BIOS. | |
68d18ad7 | 936 | */ |
3e68320e DL |
937 | if (HAS_PCH_LPT(dev)) { |
938 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | | |
939 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
940 | ||
941 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; | |
942 | } | |
754970ee DV |
943 | |
944 | intel_crt_reset(connector); | |
79e53945 | 945 | } |