[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_crt.c

/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 temp, reg;

	if (HAS_PCH_SPLIT(dev))
		reg = PCH_ADPA;
	else
		reg = ADPA;

	temp = I915_READ(reg);
	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
	temp &= ~ADPA_DAC_ENABLE;

	switch(mode) {
	case DRM_MODE_DPMS_ON:
		temp |= ADPA_DAC_ENABLE;
		break;
	case DRM_MODE_DPMS_STANDBY:
		temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_SUSPEND:
		temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	case DRM_MODE_DPMS_OFF:
		temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
		break;
	}

	I915_WRITE(reg, temp);
}

static int intel_crt_mode_valid(struct drm_connector *connector,
				struct drm_display_mode *mode)
{
	struct drm_device *dev = connector->dev;

	int max_clock = 0;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	if (mode->clock < 25000)
		return MODE_CLOCK_LOW;

	if (!IS_I9XX(dev))
		max_clock = 350000;
	else
		max_clock = 400000;
	if (mode->clock > max_clock)
		return MODE_CLOCK_HIGH;

	return MODE_OK;
}

static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
				 struct drm_display_mode *mode,
				 struct drm_display_mode *adjusted_mode)
{
	return true;
}

static void intel_crt_mode_set(struct drm_encoder *encoder,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode)
{

	struct drm_device *dev = encoder->dev;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_i915_private *dev_priv = dev->dev_private;
	int dpll_md_reg;
	u32 adpa, dpll_md;
	u32 adpa_reg;

	if (intel_crtc->pipe == 0)
		dpll_md_reg = DPLL_A_MD;
	else
		dpll_md_reg = DPLL_B_MD;

	if (HAS_PCH_SPLIT(dev))
		adpa_reg = PCH_ADPA;
	else
		adpa_reg = ADPA;

	/*
	 * Disable separate mode multiplier used when cloning SDVO to CRT
	 * XXX this needs to be adjusted when we really are cloning
	 */
	if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
		dpll_md = I915_READ(dpll_md_reg);
		I915_WRITE(dpll_md_reg,
			   dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
	}

	adpa = 0;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		adpa |= ADPA_VSYNC_ACTIVE_HIGH;

	if (intel_crtc->pipe == 0) {
		if (HAS_PCH_CPT(dev))
			adpa |= PORT_TRANS_A_SEL_CPT;
		else
			adpa |= ADPA_PIPE_A_SELECT;
		if (!HAS_PCH_SPLIT(dev))
			I915_WRITE(BCLRPAT_A, 0);
	} else {
		if (HAS_PCH_CPT(dev))
			adpa |= PORT_TRANS_B_SEL_CPT;
		else
			adpa |= ADPA_PIPE_B_SELECT;
		if (!HAS_PCH_SPLIT(dev))
			I915_WRITE(BCLRPAT_B, 0);
	}

	I915_WRITE(adpa_reg, adpa);
}

static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 adpa, temp;
	bool ret;
	bool turn_off_dac = false;

	temp = adpa = I915_READ(PCH_ADPA);

	if (HAS_PCH_SPLIT(dev))
		turn_off_dac = true;

	adpa &= ~ADPA_CRT_HOTPLUG_MASK;
	if (turn_off_dac)
		adpa &= ~ADPA_DAC_ENABLE;

	/* disable HPD first */
	I915_WRITE(PCH_ADPA, adpa);
	(void)I915_READ(PCH_ADPA);

	adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
			ADPA_CRT_HOTPLUG_WARMUP_10MS |
			ADPA_CRT_HOTPLUG_SAMPLE_4S |
			ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */
			ADPA_CRT_HOTPLUG_VOLREF_325MV |
			ADPA_CRT_HOTPLUG_ENABLE |
			ADPA_CRT_HOTPLUG_FORCE_TRIGGER);

	DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
	I915_WRITE(PCH_ADPA, adpa);

	if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
		     1000))
		DRM_ERROR("timed out waiting for FORCE_TRIGGER");

	if (turn_off_dac) {
		I915_WRITE(PCH_ADPA, temp);
		(void)I915_READ(PCH_ADPA);
	}

	/* Check the status to see if both blue and green are on now */
	adpa = I915_READ(PCH_ADPA);
	adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
	if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) ||
		(adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
		ret = true;
	else
		ret = false;

	return ret;
}

/**
 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 *
 * Not for i915G/i915GM
 *
 * \return true if CRT is connected.
 * \return false if CRT is disconnected.
 */
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 hotplug_en, orig, stat;
	bool ret = false;
	int i, tries = 0;

	if (HAS_PCH_SPLIT(dev))
		return intel_ironlake_crt_detect_hotplug(connector);

	/*
	 * On 4 series desktop, CRT detect sequence need to be done twice
	 * to get a reliable result.
	 */

	if (IS_G4X(dev) && !IS_GM45(dev))
		tries = 2;
	else
		tries = 1;
	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
	hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;

	for (i = 0; i < tries ; i++) {
		/* turn on the FORCE_DETECT */
		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
		/* wait for FORCE_DETECT to go off */
		if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
			      CRT_HOTPLUG_FORCE_DETECT) == 0,
			     1000))
			DRM_ERROR("timed out waiting for FORCE_DETECT to go off");
	}

	stat = I915_READ(PORT_HOTPLUG_STAT);
	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
		ret = true;

	/* clear the interrupt we just generated, if any */
	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);

	/* and put the bits back */
	I915_WRITE(PORT_HOTPLUG_EN, orig);

	return ret;
}

static bool intel_crt_detect_ddc(struct drm_encoder *encoder)
{
	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

	/* CRT should always be at 0, but check anyway */
	if (intel_encoder->type != INTEL_OUTPUT_ANALOG)
		return false;

	return intel_ddc_probe(intel_encoder);
}

static enum drm_connector_status
intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder)
{
	struct drm_encoder *encoder = &intel_encoder->base;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	uint32_t pipe = intel_crtc->pipe;
	uint32_t save_bclrpat;
	uint32_t save_vtotal;
	uint32_t vtotal, vactive;
	uint32_t vsample;
	uint32_t vblank, vblank_start, vblank_end;
	uint32_t dsl;
	uint32_t bclrpat_reg;
	uint32_t vtotal_reg;
	uint32_t vblank_reg;
	uint32_t vsync_reg;
	uint32_t pipeconf_reg;
	uint32_t pipe_dsl_reg;
	uint8_t	st00;
	enum drm_connector_status status;

	if (pipe == 0) {
		bclrpat_reg = BCLRPAT_A;
		vtotal_reg = VTOTAL_A;
		vblank_reg = VBLANK_A;
		vsync_reg = VSYNC_A;
		pipeconf_reg = PIPEACONF;
		pipe_dsl_reg = PIPEADSL;
	} else {
		bclrpat_reg = BCLRPAT_B;
		vtotal_reg = VTOTAL_B;
		vblank_reg = VBLANK_B;
		vsync_reg = VSYNC_B;
		pipeconf_reg = PIPEBCONF;
		pipe_dsl_reg = PIPEBDSL;
	}

	save_bclrpat = I915_READ(bclrpat_reg);
	save_vtotal = I915_READ(vtotal_reg);
	vblank = I915_READ(vblank_reg);

	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	vactive = (save_vtotal & 0x7ff) + 1;

	vblank_start = (vblank & 0xfff) + 1;
	vblank_end = ((vblank >> 16) & 0xfff) + 1;

	/* Set the border color to purple. */
	I915_WRITE(bclrpat_reg, 0x500050);

	if (IS_I9XX(dev)) {
		uint32_t pipeconf = I915_READ(pipeconf_reg);
		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
		POSTING_READ(pipeconf_reg);
		/* Wait for next Vblank to substitue
		 * border color for Color info */
		intel_wait_for_vblank(dev, pipe);
		st00 = I915_READ8(VGA_MSR_WRITE);
		status = ((st00 & (1 << 4)) != 0) ?
			connector_status_connected :
			connector_status_disconnected;

		I915_WRITE(pipeconf_reg, pipeconf);
	} else {
		bool restore_vblank = false;
		int count, detect;

		/*
		* If there isn't any border, add some.
		* Yes, this will flicker
		*/
		if (vblank_start <= vactive && vblank_end >= vtotal) {
			uint32_t vsync = I915_READ(vsync_reg);
			uint32_t vsync_start = (vsync & 0xffff) + 1;

			vblank_start = vsync_start;
			I915_WRITE(vblank_reg,
				   (vblank_start - 1) |
				   ((vblank_end - 1) << 16));
			restore_vblank = true;
		}
		/* sample in the vertical border, selecting the larger one */
		if (vblank_start - vactive >= vtotal - vblank_end)
			vsample = (vblank_start + vactive) >> 1;
		else
			vsample = (vtotal + vblank_end) >> 1;

		/*
		 * Wait for the border to be displayed
		 */
		while (I915_READ(pipe_dsl_reg) >= vactive)
			;
		while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
			;
		/*
		 * Watch ST00 for an entire scanline
		 */
		detect = 0;
		count = 0;
		do {
			count++;
			/* Read the ST00 VGA status register */
			st00 = I915_READ8(VGA_MSR_WRITE);
			if (st00 & (1 << 4))
				detect++;
		} while ((I915_READ(pipe_dsl_reg) == dsl));

		/* restore vblank if necessary */
		if (restore_vblank)
			I915_WRITE(vblank_reg, vblank);
		/*
		 * If more than 3/4 of the scanline detected a monitor,
		 * then it is assumed to be present. This works even on i830,
		 * where there isn't any way to force the border color across
		 * the screen
		 */
		status = detect * 4 > count * 3 ?
			 connector_status_connected :
			 connector_status_disconnected;
	}

	/* Restore previous settings */
	I915_WRITE(bclrpat_reg, save_bclrpat);

	return status;
}

static enum drm_connector_status intel_crt_detect(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct intel_encoder *encoder = intel_attached_encoder(connector);
	struct drm_crtc *crtc;
	int dpms_mode;
	enum drm_connector_status status;

	if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
		if (intel_crt_detect_hotplug(connector))
			return connector_status_connected;
		else
			return connector_status_disconnected;
	}

	if (intel_crt_detect_ddc(&encoder->base))
		return connector_status_connected;

	/* for pre-945g platforms use load detect */
	if (encoder->base.crtc && encoder->base.crtc->enabled) {
		status = intel_crt_load_detect(encoder->base.crtc, encoder);
	} else {
		crtc = intel_get_load_detect_pipe(encoder, connector,
						  NULL, &dpms_mode);
		if (crtc) {
			status = intel_crt_load_detect(crtc, encoder);
			intel_release_load_detect_pipe(encoder,
						       connector, dpms_mode);
		} else
			status = connector_status_unknown;
	}

	return status;
}

static void intel_crt_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

static int intel_crt_get_modes(struct drm_connector *connector)
{
	struct intel_encoder *encoder = intel_attached_encoder(connector);
	struct i2c_adapter *ddc_bus;
	struct drm_device *dev = connector->dev;
	int ret;

	ret = intel_ddc_get_modes(connector, encoder->ddc_bus);
	if (ret || !IS_G4X(dev))
		goto end;

	/* Try to probe digital port for output in DVI-I -> VGA mode. */
	ddc_bus = intel_i2c_create(encoder, GPIOD, "CRTDDC_D");
	if (!ddc_bus) {
		dev_printk(KERN_ERR, &connector->dev->pdev->dev,
			   "DDC bus registration failed for CRTDDC_D.\n");
		goto end;
	}
	/* Try to get modes by GPIOD port */
	ret = intel_ddc_get_modes(connector, ddc_bus);
	intel_i2c_destroy(ddc_bus);

end:
	return ret;

}

static int intel_crt_set_property(struct drm_connector *connector,
				  struct drm_property *property,
				  uint64_t value)
{
	return 0;
}

/*
 * Routines for controlling stuff on the analog port
 */

static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
	.dpms = intel_crt_dpms,
	.mode_fixup = intel_crt_mode_fixup,
	.prepare = intel_encoder_prepare,
	.commit = intel_encoder_commit,
	.mode_set = intel_crt_mode_set,
};

static const struct drm_connector_funcs intel_crt_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = intel_crt_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = intel_crt_destroy,
	.set_property = intel_crt_set_property,
};

static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	.mode_valid = intel_crt_mode_valid,
	.get_modes = intel_crt_get_modes,
	.best_encoder = intel_best_encoder,
};

static const struct drm_encoder_funcs intel_crt_enc_funcs = {
	.destroy = intel_encoder_destroy,
};

void intel_crt_init(struct drm_device *dev)
{
	struct drm_connector *connector;
	struct intel_encoder *intel_encoder;
	struct intel_connector *intel_connector;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 i2c_reg;

	intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL);
	if (!intel_encoder)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_encoder);
		return;
	}

	connector = &intel_connector->base;
	drm_connector_init(dev, &intel_connector->base,
			   &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);

	drm_encoder_init(dev, &intel_encoder->base, &intel_crt_enc_funcs,
			 DRM_MODE_ENCODER_DAC);

	intel_connector_attach_encoder(intel_connector, intel_encoder);

	/* Set up the DDC bus. */
	if (HAS_PCH_SPLIT(dev))
		i2c_reg = PCH_GPIOA;
	else {
		i2c_reg = GPIOA;
		/* Use VBT information for CRT DDC if available */
		if (dev_priv->crt_ddc_bus != 0)
			i2c_reg = dev_priv->crt_ddc_bus;
	}
	intel_encoder->ddc_bus = intel_i2c_create(intel_encoder,
						  i2c_reg, "CRTDDC_A");
	if (!intel_encoder->ddc_bus) {
		dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
			   "failed.\n");
		drm_connector_cleanup(&intel_connector->base);
		kfree(intel_connector);
		drm_encoder_cleanup(&intel_encoder->base);
		kfree(intel_encoder);
		return;
	}

	intel_encoder->type = INTEL_OUTPUT_ANALOG;
	intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
				   (1 << INTEL_ANALOG_CLONE_BIT) |
				   (1 << INTEL_SDVO_LVDS_CLONE_BIT);
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	connector->interlace_allowed = 1;
	connector->doublescan_allowed = 0;

	drm_encoder_helper_add(&intel_encoder->base, &intel_crt_helper_funcs);
	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);

	drm_sysfs_connector_add(connector);

	if (I915_HAS_HOTPLUG(dev))
		connector->polled = DRM_CONNECTOR_POLL_HPD;
	else
		connector->polled = DRM_CONNECTOR_POLL_CONNECT;

	dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright © 2006-2007 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	*/
	26
	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
79e53945 JB	29	#include "drmP.h"
	30	#include "drm.h"
	31	#include "drm_crtc.h"
	32	#include "drm_crtc_helper.h"
	33	#include "intel_drv.h"
	34	#include "i915_drm.h"
	35	#include "i915_drv.h"
	36
	37	static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
	38	{
	39	struct drm_device *dev = encoder->dev;
	40	struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f	41	u32 temp, reg;
79e53945	42
bad720ff	43	if (HAS_PCH_SPLIT(dev))
2c07245f ZW	44	reg = PCH_ADPA;
	45	else
	46	reg = ADPA;
	47
	48	temp = I915_READ(reg);
79e53945	49	temp &= ~(ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE);
febc7694	50	temp &= ~ADPA_DAC_ENABLE;
79e53945 JB	51
	52	switch(mode) {
	53	case DRM_MODE_DPMS_ON:
	54	temp \|= ADPA_DAC_ENABLE;
	55	break;
	56	case DRM_MODE_DPMS_STANDBY:
	57	temp \|= ADPA_DAC_ENABLE \| ADPA_HSYNC_CNTL_DISABLE;
	58	break;
	59	case DRM_MODE_DPMS_SUSPEND:
	60	temp \|= ADPA_DAC_ENABLE \| ADPA_VSYNC_CNTL_DISABLE;
	61	break;
	62	case DRM_MODE_DPMS_OFF:
	63	temp \|= ADPA_HSYNC_CNTL_DISABLE \| ADPA_VSYNC_CNTL_DISABLE;
	64	break;
	65	}
	66
2c07245f	67	I915_WRITE(reg, temp);
79e53945 JB	68	}
	69
	70	static int intel_crt_mode_valid(struct drm_connector *connector,
	71	struct drm_display_mode *mode)
	72	{
6bcdcd9e ZY	73	struct drm_device *dev = connector->dev;
	74
	75	int max_clock = 0;
79e53945 JB	76	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	77	return MODE_NO_DBLESCAN;
	78
6bcdcd9e ZY	79	if (mode->clock < 25000)
	80	return MODE_CLOCK_LOW;
	81
	82	if (!IS_I9XX(dev))
	83	max_clock = 350000;
	84	else
	85	max_clock = 400000;
	86	if (mode->clock > max_clock)
	87	return MODE_CLOCK_HIGH;
79e53945 JB	88
	89	return MODE_OK;
	90	}
	91
	92	static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
	93	struct drm_display_mode *mode,
	94	struct drm_display_mode *adjusted_mode)
	95	{
	96	return true;
	97	}
	98
	99	static void intel_crt_mode_set(struct drm_encoder *encoder,
	100	struct drm_display_mode *mode,
	101	struct drm_display_mode *adjusted_mode)
	102	{
	103
	104	struct drm_device *dev = encoder->dev;
	105	struct drm_crtc *crtc = encoder->crtc;
	106	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	107	struct drm_i915_private *dev_priv = dev->dev_private;
	108	int dpll_md_reg;
	109	u32 adpa, dpll_md;
2c07245f	110	u32 adpa_reg;
79e53945 JB	111
	112	if (intel_crtc->pipe == 0)
	113	dpll_md_reg = DPLL_A_MD;
	114	else
	115	dpll_md_reg = DPLL_B_MD;
	116
bad720ff	117	if (HAS_PCH_SPLIT(dev))
2c07245f ZW	118	adpa_reg = PCH_ADPA;
	119	else
	120	adpa_reg = ADPA;
	121
79e53945 JB	122	/*
	123	* Disable separate mode multiplier used when cloning SDVO to CRT
	124	* XXX this needs to be adjusted when we really are cloning
	125	*/
bad720ff	126	if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
79e53945 JB	127	dpll_md = I915_READ(dpll_md_reg);
	128	I915_WRITE(dpll_md_reg,
	129	dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
	130	}
	131
	132	adpa = 0;
	133	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	134	adpa \|= ADPA_HSYNC_ACTIVE_HIGH;
	135	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	136	adpa \|= ADPA_VSYNC_ACTIVE_HIGH;
	137
6bcdcd9e	138	if (intel_crtc->pipe == 0) {
8db9d77b ZW	139	if (HAS_PCH_CPT(dev))
	140	adpa \|= PORT_TRANS_A_SEL_CPT;
	141	else
	142	adpa \|= ADPA_PIPE_A_SELECT;
bad720ff	143	if (!HAS_PCH_SPLIT(dev))
2c07245f	144	I915_WRITE(BCLRPAT_A, 0);
6bcdcd9e	145	} else {
8db9d77b ZW	146	if (HAS_PCH_CPT(dev))
	147	adpa \|= PORT_TRANS_B_SEL_CPT;
	148	else
	149	adpa \|= ADPA_PIPE_B_SELECT;
bad720ff	150	if (!HAS_PCH_SPLIT(dev))
2c07245f	151	I915_WRITE(BCLRPAT_B, 0);
6bcdcd9e	152	}
79e53945	153
2c07245f ZW	154	I915_WRITE(adpa_reg, adpa);
	155	}
	156
f2b115e6	157	static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
2c07245f ZW	158	{
	159	struct drm_device *dev = connector->dev;
	160	struct drm_i915_private *dev_priv = dev->dev_private;
a4a6b901	161	u32 adpa, temp;
2c07245f	162	bool ret;
d5dd96cb	163	bool turn_off_dac = false;
2c07245f	164
a4a6b901	165	temp = adpa = I915_READ(PCH_ADPA);
67941da2	166
d5dd96cb DA	167	if (HAS_PCH_SPLIT(dev))
	168	turn_off_dac = true;
	169
	170	adpa &= ~ADPA_CRT_HOTPLUG_MASK;
	171	if (turn_off_dac)
	172	adpa &= ~ADPA_DAC_ENABLE;
	173
	174	/* disable HPD first */
	175	I915_WRITE(PCH_ADPA, adpa);
	176	(void)I915_READ(PCH_ADPA);
2c07245f ZW	177
	178	adpa \|= (ADPA_CRT_HOTPLUG_PERIOD_128 \|
	179	ADPA_CRT_HOTPLUG_WARMUP_10MS \|
	180	ADPA_CRT_HOTPLUG_SAMPLE_4S \|
	181	ADPA_CRT_HOTPLUG_VOLTAGE_50 \| /* default */
	182	ADPA_CRT_HOTPLUG_VOLREF_325MV \|
	183	ADPA_CRT_HOTPLUG_ENABLE \|
	184	ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
	185
28c97730	186	DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
2c07245f ZW	187	I915_WRITE(PCH_ADPA, adpa);
2c07245f ZW	188
913d8d11	189	if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
481b6af3	190	1000))
913d8d11	191	DRM_ERROR("timed out waiting for FORCE_TRIGGER");
2c07245f	192
d5dd96cb	193	if (turn_off_dac) {
a4a6b901 ZW	194	I915_WRITE(PCH_ADPA, temp);
	195	(void)I915_READ(PCH_ADPA);
	196	}
	197
2c07245f ZW	198	/* Check the status to see if both blue and green are on now */
2c07245f ZW	199	adpa = I915_READ(PCH_ADPA);
67941da2 ZW	200	adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
	201	if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) \|\|
	202	(adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
2c07245f ZW	203	ret = true;
	204	else
	205	ret = false;
	206
2c07245f	207	return ret;
79e53945 JB	208	}
	209
	210	/**
	211	* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
	212	*
	213	* Not for i915G/i915GM
	214	*
	215	* \return true if CRT is connected.
	216	* \return false if CRT is disconnected.
	217	*/
	218	static bool intel_crt_detect_hotplug(struct drm_connector *connector)
	219	{
	220	struct drm_device *dev = connector->dev;
	221	struct drm_i915_private *dev_priv = dev->dev_private;
7a772c49 AJ	222	u32 hotplug_en, orig, stat;
7a772c49 AJ	223	bool ret = false;
771cb081	224	int i, tries = 0;
2c07245f	225
bad720ff	226	if (HAS_PCH_SPLIT(dev))
f2b115e6	227	return intel_ironlake_crt_detect_hotplug(connector);
2c07245f	228
771cb081 ZY	229	/*
	230	* On 4 series desktop, CRT detect sequence need to be done twice
	231	* to get a reliable result.
	232	*/
79e53945	233
771cb081 ZY	234	if (IS_G4X(dev) && !IS_GM45(dev))
	235	tries = 2;
	236	else
	237	tries = 1;
7a772c49	238	hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
771cb081 ZY	239	hotplug_en \|= CRT_HOTPLUG_FORCE_DETECT;
771cb081 ZY	240
771cb081	241	for (i = 0; i < tries ; i++) {
771cb081 ZY	242	/* turn on the FORCE_DETECT */
771cb081 ZY	243	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
771cb081	244	/* wait for FORCE_DETECT to go off */
913d8d11 CW	245	if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
913d8d11 CW	246	CRT_HOTPLUG_FORCE_DETECT) == 0,
481b6af3	247	1000))
913d8d11	248	DRM_ERROR("timed out waiting for FORCE_DETECT to go off");
771cb081	249	}
79e53945	250
7a772c49 AJ	251	stat = I915_READ(PORT_HOTPLUG_STAT);
	252	if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
	253	ret = true;
	254
	255	/* clear the interrupt we just generated, if any */
	256	I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
79e53945	257
7a772c49 AJ	258	/* and put the bits back */
	259	I915_WRITE(PORT_HOTPLUG_EN, orig);
	260
	261	return ret;
79e53945 JB	262	}
79e53945 JB	263
454c1ca8	264	static bool intel_crt_detect_ddc(struct drm_encoder *encoder)
79e53945	265	{
4ef69c7a	266	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
79e53945 JB	267
79e53945 JB	268	/* CRT should always be at 0, but check anyway */
21d40d37	269	if (intel_encoder->type != INTEL_OUTPUT_ANALOG)
79e53945 JB	270	return false;
79e53945 JB	271
21d40d37	272	return intel_ddc_probe(intel_encoder);
79e53945 JB	273	}
79e53945 JB	274
e4a5d54f	275	static enum drm_connector_status
21d40d37	276	intel_crt_load_detect(struct drm_crtc crtc, struct intel_encoder intel_encoder)
e4a5d54f	277	{
4ef69c7a	278	struct drm_encoder *encoder = &intel_encoder->base;
e4a5d54f ML	279	struct drm_device *dev = encoder->dev;
	280	struct drm_i915_private *dev_priv = dev->dev_private;
	281	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	282	uint32_t pipe = intel_crtc->pipe;
	283	uint32_t save_bclrpat;
	284	uint32_t save_vtotal;
	285	uint32_t vtotal, vactive;
	286	uint32_t vsample;
	287	uint32_t vblank, vblank_start, vblank_end;
	288	uint32_t dsl;
	289	uint32_t bclrpat_reg;
	290	uint32_t vtotal_reg;
	291	uint32_t vblank_reg;
	292	uint32_t vsync_reg;
	293	uint32_t pipeconf_reg;
	294	uint32_t pipe_dsl_reg;
	295	uint8_t st00;
	296	enum drm_connector_status status;
	297
	298	if (pipe == 0) {
	299	bclrpat_reg = BCLRPAT_A;
	300	vtotal_reg = VTOTAL_A;
	301	vblank_reg = VBLANK_A;
	302	vsync_reg = VSYNC_A;
	303	pipeconf_reg = PIPEACONF;
	304	pipe_dsl_reg = PIPEADSL;
	305	} else {
	306	bclrpat_reg = BCLRPAT_B;
	307	vtotal_reg = VTOTAL_B;
	308	vblank_reg = VBLANK_B;
	309	vsync_reg = VSYNC_B;
	310	pipeconf_reg = PIPEBCONF;
	311	pipe_dsl_reg = PIPEBDSL;
	312	}
	313
	314	save_bclrpat = I915_READ(bclrpat_reg);
	315	save_vtotal = I915_READ(vtotal_reg);
	316	vblank = I915_READ(vblank_reg);
	317
	318	vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
	319	vactive = (save_vtotal & 0x7ff) + 1;
	320
	321	vblank_start = (vblank & 0xfff) + 1;
	322	vblank_end = ((vblank >> 16) & 0xfff) + 1;
	323
	324	/* Set the border color to purple. */
	325	I915_WRITE(bclrpat_reg, 0x500050);
	326
	327	if (IS_I9XX(dev)) {
	328	uint32_t pipeconf = I915_READ(pipeconf_reg);
	329	I915_WRITE(pipeconf_reg, pipeconf \| PIPECONF_FORCE_BORDER);
19c55da1	330	POSTING_READ(pipeconf_reg);
e4a5d54f ML	331	/* Wait for next Vblank to substitue
e4a5d54f ML	332	* border color for Color info */
9d0498a2	333	intel_wait_for_vblank(dev, pipe);
e4a5d54f ML	334	st00 = I915_READ8(VGA_MSR_WRITE);
	335	status = ((st00 & (1 << 4)) != 0) ?
	336	connector_status_connected :
	337	connector_status_disconnected;
	338
	339	I915_WRITE(pipeconf_reg, pipeconf);
	340	} else {
	341	bool restore_vblank = false;
	342	int count, detect;
	343
	344	/*
	345	* If there isn't any border, add some.
	346	* Yes, this will flicker
	347	*/
	348	if (vblank_start <= vactive && vblank_end >= vtotal) {
	349	uint32_t vsync = I915_READ(vsync_reg);
	350	uint32_t vsync_start = (vsync & 0xffff) + 1;
	351
	352	vblank_start = vsync_start;
	353	I915_WRITE(vblank_reg,
	354	(vblank_start - 1) \|
	355	((vblank_end - 1) << 16));
	356	restore_vblank = true;
	357	}
	358	/* sample in the vertical border, selecting the larger one */
	359	if (vblank_start - vactive >= vtotal - vblank_end)
	360	vsample = (vblank_start + vactive) >> 1;
	361	else
	362	vsample = (vtotal + vblank_end) >> 1;
	363
	364	/*
	365	* Wait for the border to be displayed
	366	*/
	367	while (I915_READ(pipe_dsl_reg) >= vactive)
	368	;
	369	while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
	370	;
	371	/*
	372	* Watch ST00 for an entire scanline
	373	*/
	374	detect = 0;
	375	count = 0;
	376	do {
	377	count++;
	378	/* Read the ST00 VGA status register */
	379	st00 = I915_READ8(VGA_MSR_WRITE);
	380	if (st00 & (1 << 4))
	381	detect++;
	382	} while ((I915_READ(pipe_dsl_reg) == dsl));
	383
	384	/* restore vblank if necessary */
	385	if (restore_vblank)
	386	I915_WRITE(vblank_reg, vblank);
	387	/*
	388	* If more than 3/4 of the scanline detected a monitor,
	389	* then it is assumed to be present. This works even on i830,
	390	* where there isn't any way to force the border color across
	391	* the screen
	392	*/
	393	status = detect * 4 > count * 3 ?
	394	connector_status_connected :
	395	connector_status_disconnected;
	396	}
	397
398	/* Restore previous settings */
399	I915_WRITE(bclrpat_reg, save_bclrpat);
400
401	return status;
402	}
403
79e53945 JB	404	static enum drm_connector_status intel_crt_detect(struct drm_connector *connector)
	405	{
	406	struct drm_device *dev = connector->dev;
df0e9248	407	struct intel_encoder *encoder = intel_attached_encoder(connector);
e4a5d54f ML	408	struct drm_crtc *crtc;
	409	int dpms_mode;
	410	enum drm_connector_status status;
79e53945 JB	411
	412	if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
	413	if (intel_crt_detect_hotplug(connector))
	414	return connector_status_connected;
	415	else
	416	return connector_status_disconnected;
	417	}
	418
df0e9248	419	if (intel_crt_detect_ddc(&encoder->base))
79e53945 JB	420	return connector_status_connected;
79e53945 JB	421
e4a5d54f	422	/* for pre-945g platforms use load detect */
df0e9248 CW	423	if (encoder->base.crtc && encoder->base.crtc->enabled) {
df0e9248 CW	424	status = intel_crt_load_detect(encoder->base.crtc, encoder);
e4a5d54f	425	} else {
df0e9248	426	crtc = intel_get_load_detect_pipe(encoder, connector,
e4a5d54f ML	427	NULL, &dpms_mode);
e4a5d54f ML	428	if (crtc) {
df0e9248 CW	429	status = intel_crt_load_detect(crtc, encoder);
df0e9248 CW	430	intel_release_load_detect_pipe(encoder,
c1c43977	431	connector, dpms_mode);
e4a5d54f ML	432	} else
	433	status = connector_status_unknown;
	434	}
	435
	436	return status;
79e53945 JB	437	}
	438
	439	static void intel_crt_destroy(struct drm_connector *connector)
	440	{
79e53945 JB	441	drm_sysfs_connector_remove(connector);
	442	drm_connector_cleanup(connector);
	443	kfree(connector);
	444	}
	445
	446	static int intel_crt_get_modes(struct drm_connector *connector)
	447	{
df0e9248	448	struct intel_encoder *encoder = intel_attached_encoder(connector);
335af9a2	449	struct i2c_adapter *ddc_bus;
8e4d36b9	450	struct drm_device *dev = connector->dev;
890f3359	451	int ret;
8e4d36b9	452
df0e9248	453	ret = intel_ddc_get_modes(connector, encoder->ddc_bus);
8e4d36b9	454	if (ret \|\| !IS_G4X(dev))
	455	goto end;
	456
8e4d36b9	457	/* Try to probe digital port for output in DVI-I -> VGA mode. */
890f3359	458	ddc_bus = intel_i2c_create(encoder, GPIOD, "CRTDDC_D");
335af9a2	459	if (!ddc_bus) {
8e4d36b9	460	dev_printk(KERN_ERR, &connector->dev->pdev->dev,
	461	"DDC bus registration failed for CRTDDC_D.\n");
	462	goto end;
	463	}
	464	/* Try to get modes by GPIOD port */
335af9a2 ZW	465	ret = intel_ddc_get_modes(connector, ddc_bus);
335af9a2 ZW	466	intel_i2c_destroy(ddc_bus);
8e4d36b9	467
	468	end:
	469	return ret;
	470
79e53945 JB	471	}
	472
	473	static int intel_crt_set_property(struct drm_connector *connector,
	474	struct drm_property *property,
	475	uint64_t value)
	476	{
79e53945 JB	477	return 0;
	478	}
	479
	480	/*
	481	* Routines for controlling stuff on the analog port
	482	*/
	483
	484	static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
	485	.dpms = intel_crt_dpms,
	486	.mode_fixup = intel_crt_mode_fixup,
	487	.prepare = intel_encoder_prepare,
	488	.commit = intel_encoder_commit,
	489	.mode_set = intel_crt_mode_set,
	490	};
	491
	492	static const struct drm_connector_funcs intel_crt_connector_funcs = {
c9fb15f6	493	.dpms = drm_helper_connector_dpms,
79e53945 JB	494	.detect = intel_crt_detect,
	495	.fill_modes = drm_helper_probe_single_connector_modes,
	496	.destroy = intel_crt_destroy,
	497	.set_property = intel_crt_set_property,
	498	};
	499
	500	static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
	501	.mode_valid = intel_crt_mode_valid,
	502	.get_modes = intel_crt_get_modes,
df0e9248	503	.best_encoder = intel_best_encoder,
79e53945 JB	504	};
79e53945 JB	505
79e53945	506	static const struct drm_encoder_funcs intel_crt_enc_funcs = {
ea5b213a	507	.destroy = intel_encoder_destroy,
79e53945 JB	508	};
	509
	510	void intel_crt_init(struct drm_device *dev)
	511	{
	512	struct drm_connector *connector;
21d40d37	513	struct intel_encoder *intel_encoder;
454c1ca8	514	struct intel_connector *intel_connector;
db545019	515	struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f	516	u32 i2c_reg;
79e53945	517
21d40d37 EA	518	intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL);
21d40d37 EA	519	if (!intel_encoder)
79e53945 JB	520	return;
79e53945 JB	521
454c1ca8 ZW	522	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	523	if (!intel_connector) {
	524	kfree(intel_encoder);
	525	return;
	526	}
	527
	528	connector = &intel_connector->base;
	529	drm_connector_init(dev, &intel_connector->base,
79e53945 JB	530	&intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
79e53945 JB	531
4ef69c7a	532	drm_encoder_init(dev, &intel_encoder->base, &intel_crt_enc_funcs,
79e53945 JB	533	DRM_MODE_ENCODER_DAC);
79e53945 JB	534
df0e9248	535	intel_connector_attach_encoder(intel_connector, intel_encoder);
79e53945 JB	536
79e53945 JB	537	/* Set up the DDC bus. */
bad720ff	538	if (HAS_PCH_SPLIT(dev))
2c07245f	539	i2c_reg = PCH_GPIOA;
db545019	540	else {
2c07245f	541	i2c_reg = GPIOA;
db545019	542	/* Use VBT information for CRT DDC if available */
29874f44	543	if (dev_priv->crt_ddc_bus != 0)
db545019 DMEA	544	i2c_reg = dev_priv->crt_ddc_bus;
db545019 DMEA	545	}
890f3359 CW	546	intel_encoder->ddc_bus = intel_i2c_create(intel_encoder,
890f3359 CW	547	i2c_reg, "CRTDDC_A");
21d40d37	548	if (!intel_encoder->ddc_bus) {
79e53945 JB	549	dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
79e53945 JB	550	"failed.\n");
373a3cf7 CW	551	drm_connector_cleanup(&intel_connector->base);
	552	kfree(intel_connector);
	553	drm_encoder_cleanup(&intel_encoder->base);
	554	kfree(intel_encoder);
79e53945 JB	555	return;
	556	}
	557
21d40d37 EA	558	intel_encoder->type = INTEL_OUTPUT_ANALOG;
21d40d37 EA	559	intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) \|
f8aed700 ML	560	(1 << INTEL_ANALOG_CLONE_BIT) \|
f8aed700 ML	561	(1 << INTEL_SDVO_LVDS_CLONE_BIT);
21d40d37	562	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
734b4157	563	connector->interlace_allowed = 1;
79e53945 JB	564	connector->doublescan_allowed = 0;
79e53945 JB	565
4ef69c7a	566	drm_encoder_helper_add(&intel_encoder->base, &intel_crt_helper_funcs);
79e53945 JB	567	drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
	568
	569	drm_sysfs_connector_add(connector);
b01f2c3a	570
eb1f8e4f DA	571	if (I915_HAS_HOTPLUG(dev))
	572	connector->polled = DRM_CONNECTOR_POLL_HPD;
	573	else
	574	connector->polled = DRM_CONNECTOR_POLL_CONNECT;
	575
b01f2c3a	576	dev_priv->hotplug_supported_mask \|= CRT_HOTPLUG_INT_STATUS;
79e53945	577	}