Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 | 30 | #include <drm/drmP.h> |
c6f95f27 | 31 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
79e53945 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
79e53945 JB |
37 | #include "i915_drv.h" |
38 | ||
e7dbb2f2 KP |
39 | /* Here's the desired hotplug mode */ |
40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
45 | ADPA_CRT_HOTPLUG_ENABLE) | |
46 | ||
c9a1c4cd CW |
47 | struct intel_crt { |
48 | struct intel_encoder base; | |
637f44d2 AJ |
49 | /* DPMS state is stored in the connector, which we need in the |
50 | * encoder's enable/disable callbacks */ | |
51 | struct intel_connector *connector; | |
e7dbb2f2 | 52 | bool force_hotplug_required; |
f0f59a00 | 53 | i915_reg_t adpa_reg; |
c9a1c4cd CW |
54 | }; |
55 | ||
eebe6f0b | 56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 57 | { |
eebe6f0b | 58 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
59 | } |
60 | ||
eebe6f0b | 61 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 62 | { |
eebe6f0b | 63 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
64 | } |
65 | ||
e403fc94 DV |
66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
67 | enum pipe *pipe) | |
79e53945 | 68 | { |
e403fc94 | 69 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 70 | struct drm_i915_private *dev_priv = to_i915(dev); |
e403fc94 DV |
71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
72 | u32 tmp; | |
1c8fdda1 | 73 | bool ret; |
e403fc94 | 74 | |
79f255a0 ACO |
75 | if (!intel_display_power_get_if_enabled(dev_priv, |
76 | encoder->power_domain)) | |
6d129bea ID |
77 | return false; |
78 | ||
1c8fdda1 ID |
79 | ret = false; |
80 | ||
e403fc94 DV |
81 | tmp = I915_READ(crt->adpa_reg); |
82 | ||
83 | if (!(tmp & ADPA_DAC_ENABLE)) | |
1c8fdda1 | 84 | goto out; |
e403fc94 | 85 | |
6e266956 | 86 | if (HAS_PCH_CPT(dev_priv)) |
e403fc94 DV |
87 | *pipe = PORT_TO_PIPE_CPT(tmp); |
88 | else | |
89 | *pipe = PORT_TO_PIPE(tmp); | |
90 | ||
1c8fdda1 ID |
91 | ret = true; |
92 | out: | |
79f255a0 | 93 | intel_display_power_put(dev_priv, encoder->power_domain); |
1c8fdda1 ID |
94 | |
95 | return ret; | |
e403fc94 DV |
96 | } |
97 | ||
6801c18c | 98 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 | 99 | { |
fac5e23e | 100 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 JB |
101 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
102 | u32 tmp, flags = 0; | |
103 | ||
104 | tmp = I915_READ(crt->adpa_reg); | |
105 | ||
106 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
107 | flags |= DRM_MODE_FLAG_PHSYNC; | |
108 | else | |
109 | flags |= DRM_MODE_FLAG_NHSYNC; | |
110 | ||
111 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
112 | flags |= DRM_MODE_FLAG_PVSYNC; | |
113 | else | |
114 | flags |= DRM_MODE_FLAG_NVSYNC; | |
115 | ||
6801c18c VS |
116 | return flags; |
117 | } | |
118 | ||
119 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 120 | struct intel_crtc_state *pipe_config) |
6801c18c | 121 | { |
e1214b95 VS |
122 | pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); |
123 | ||
2d112de7 | 124 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 | 125 | |
e3b247da | 126 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
127 | } |
128 | ||
6801c18c | 129 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 130 | struct intel_crtc_state *pipe_config) |
6801c18c | 131 | { |
8802e5b6 VS |
132 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
133 | ||
6801c18c VS |
134 | intel_ddi_get_config(encoder, pipe_config); |
135 | ||
2d112de7 | 136 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
137 | DRM_MODE_FLAG_NHSYNC | |
138 | DRM_MODE_FLAG_PVSYNC | | |
139 | DRM_MODE_FLAG_NVSYNC); | |
2d112de7 | 140 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
8802e5b6 VS |
141 | |
142 | pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); | |
6801c18c VS |
143 | } |
144 | ||
b2cabb0e DV |
145 | /* Note: The caller is required to filter out dpms modes not supported by the |
146 | * platform. */ | |
225cc348 | 147 | static void intel_crt_set_dpms(struct intel_encoder *encoder, |
5f88a9c6 | 148 | const struct intel_crtc_state *crtc_state, |
225cc348 | 149 | int mode) |
df0323c4 | 150 | { |
66478475 | 151 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b2cabb0e | 152 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
225cc348 ML |
153 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
154 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; | |
894ed1ec DV |
155 | u32 adpa; |
156 | ||
66478475 | 157 | if (INTEL_GEN(dev_priv) >= 5) |
894ed1ec DV |
158 | adpa = ADPA_HOTPLUG_BITS; |
159 | else | |
160 | adpa = 0; | |
df0323c4 | 161 | |
894ed1ec DV |
162 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
163 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
164 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
165 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
166 | ||
167 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
6e266956 | 168 | if (HAS_PCH_LPT(dev_priv)) |
894ed1ec | 169 | ; /* Those bits don't exist here */ |
6e266956 | 170 | else if (HAS_PCH_CPT(dev_priv)) |
894ed1ec DV |
171 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
172 | else if (crtc->pipe == 0) | |
173 | adpa |= ADPA_PIPE_A_SELECT; | |
174 | else | |
175 | adpa |= ADPA_PIPE_B_SELECT; | |
176 | ||
6e266956 | 177 | if (!HAS_PCH_SPLIT(dev_priv)) |
894ed1ec | 178 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
79e53945 | 179 | |
0206e353 | 180 | switch (mode) { |
79e53945 | 181 | case DRM_MODE_DPMS_ON: |
894ed1ec | 182 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
183 | break; |
184 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 185 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
186 | break; |
187 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 188 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
189 | break; |
190 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 191 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
192 | break; |
193 | } | |
194 | ||
894ed1ec | 195 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 196 | } |
2c07245f | 197 | |
fd6bbda9 | 198 | static void intel_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
199 | const struct intel_crtc_state *old_crtc_state, |
200 | const struct drm_connector_state *old_conn_state) | |
637f44d2 | 201 | { |
225cc348 | 202 | intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); |
637f44d2 AJ |
203 | } |
204 | ||
fd6bbda9 | 205 | static void pch_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
206 | const struct intel_crtc_state *old_crtc_state, |
207 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 VS |
208 | { |
209 | } | |
210 | ||
fd6bbda9 | 211 | static void pch_post_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
212 | const struct intel_crtc_state *old_crtc_state, |
213 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 | 214 | { |
fd6bbda9 | 215 | intel_disable_crt(encoder, old_crtc_state, old_conn_state); |
1ea56e26 | 216 | } |
abfdc1e3 | 217 | |
3daa3cee JN |
218 | static void hsw_disable_crt(struct intel_encoder *encoder, |
219 | const struct intel_crtc_state *old_crtc_state, | |
220 | const struct drm_connector_state *old_conn_state) | |
221 | { | |
222 | struct drm_crtc *crtc = old_crtc_state->base.crtc; | |
223 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
225 | ||
226 | WARN_ON(!intel_crtc->config->has_pch_encoder); | |
227 | ||
228 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
229 | } | |
230 | ||
b7076546 | 231 | static void hsw_post_disable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
232 | const struct intel_crtc_state *old_crtc_state, |
233 | const struct drm_connector_state *old_conn_state) | |
b7076546 ML |
234 | { |
235 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
236 | ||
237 | pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); | |
238 | ||
239 | lpt_disable_pch_transcoder(dev_priv); | |
240 | lpt_disable_iclkip(dev_priv); | |
241 | ||
242 | intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); | |
3daa3cee JN |
243 | |
244 | WARN_ON(!old_crtc_state->has_pch_encoder); | |
245 | ||
246 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
b7076546 ML |
247 | } |
248 | ||
51c4fa69 JN |
249 | static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder, |
250 | const struct intel_crtc_state *pipe_config, | |
251 | const struct drm_connector_state *conn_state) | |
252 | { | |
253 | struct drm_crtc *crtc = pipe_config->base.crtc; | |
254 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
255 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
256 | ||
257 | WARN_ON(!intel_crtc->config->has_pch_encoder); | |
258 | ||
259 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
260 | } | |
261 | ||
262 | static void hsw_pre_enable_crt(struct intel_encoder *encoder, | |
263 | const struct intel_crtc_state *pipe_config, | |
264 | const struct drm_connector_state *conn_state) | |
265 | { | |
266 | struct drm_crtc *crtc = pipe_config->base.crtc; | |
267 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
268 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
269 | int pipe = intel_crtc->pipe; | |
270 | ||
271 | WARN_ON(!intel_crtc->config->has_pch_encoder); | |
272 | ||
273 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
27d81c28 JN |
274 | |
275 | dev_priv->display.fdi_link_train(intel_crtc, pipe_config); | |
51c4fa69 JN |
276 | } |
277 | ||
278 | static void hsw_enable_crt(struct intel_encoder *encoder, | |
279 | const struct intel_crtc_state *pipe_config, | |
280 | const struct drm_connector_state *conn_state) | |
281 | { | |
282 | struct drm_crtc *crtc = pipe_config->base.crtc; | |
283 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
285 | int pipe = intel_crtc->pipe; | |
286 | ||
287 | WARN_ON(!intel_crtc->config->has_pch_encoder); | |
288 | ||
289 | intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON); | |
290 | ||
291 | intel_wait_for_vblank(dev_priv, pipe); | |
292 | intel_wait_for_vblank(dev_priv, pipe); | |
293 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
294 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
295 | } | |
296 | ||
fd6bbda9 | 297 | static void intel_enable_crt(struct intel_encoder *encoder, |
5f88a9c6 VS |
298 | const struct intel_crtc_state *pipe_config, |
299 | const struct drm_connector_state *conn_state) | |
637f44d2 | 300 | { |
225cc348 | 301 | intel_crt_set_dpms(encoder, pipe_config, DRM_MODE_DPMS_ON); |
637f44d2 AJ |
302 | } |
303 | ||
c19de8eb DL |
304 | static enum drm_mode_status |
305 | intel_crt_mode_valid(struct drm_connector *connector, | |
306 | struct drm_display_mode *mode) | |
79e53945 | 307 | { |
6bcdcd9e | 308 | struct drm_device *dev = connector->dev; |
6e266956 TU |
309 | struct drm_i915_private *dev_priv = to_i915(dev); |
310 | int max_dotclk = dev_priv->max_dotclk_freq; | |
debded84 | 311 | int max_clock; |
6bcdcd9e | 312 | |
79e53945 JB |
313 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
314 | return MODE_NO_DBLESCAN; | |
315 | ||
6bcdcd9e ZY |
316 | if (mode->clock < 25000) |
317 | return MODE_CLOCK_LOW; | |
318 | ||
6e266956 | 319 | if (HAS_PCH_LPT(dev_priv)) |
debded84 | 320 | max_clock = 180000; |
11a914c2 | 321 | else if (IS_VALLEYVIEW(dev_priv)) |
debded84 VS |
322 | /* |
323 | * 270 MHz due to current DPLL limits, | |
324 | * DAC limit supposedly 355 MHz. | |
325 | */ | |
326 | max_clock = 270000; | |
5db94019 | 327 | else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) |
6bcdcd9e | 328 | max_clock = 400000; |
debded84 VS |
329 | else |
330 | max_clock = 350000; | |
6bcdcd9e ZY |
331 | if (mode->clock > max_clock) |
332 | return MODE_CLOCK_HIGH; | |
79e53945 | 333 | |
f8700b34 MK |
334 | if (mode->clock > max_dotclk) |
335 | return MODE_CLOCK_HIGH; | |
336 | ||
d4b1931c | 337 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
6e266956 | 338 | if (HAS_PCH_LPT(dev_priv) && |
d4b1931c PZ |
339 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
340 | return MODE_CLOCK_HIGH; | |
341 | ||
79e53945 JB |
342 | return MODE_OK; |
343 | } | |
344 | ||
5bfe2ac0 | 345 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
346 | struct intel_crtc_state *pipe_config, |
347 | struct drm_connector_state *conn_state) | |
2f26cdc0 JN |
348 | { |
349 | return true; | |
350 | } | |
351 | ||
352 | static bool pch_crt_compute_config(struct intel_encoder *encoder, | |
353 | struct intel_crtc_state *pipe_config, | |
354 | struct drm_connector_state *conn_state) | |
355 | { | |
356 | pipe_config->has_pch_encoder = true; | |
357 | ||
358 | return true; | |
359 | } | |
360 | ||
361 | static bool hsw_crt_compute_config(struct intel_encoder *encoder, | |
362 | struct intel_crtc_state *pipe_config, | |
363 | struct drm_connector_state *conn_state) | |
79e53945 | 364 | { |
4f8036a2 | 365 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5bfe2ac0 | 366 | |
2f26cdc0 | 367 | pipe_config->has_pch_encoder = true; |
5bfe2ac0 | 368 | |
2a7aceec | 369 | /* LPT FDI RX only supports 8bpc. */ |
4f8036a2 | 370 | if (HAS_PCH_LPT(dev_priv)) { |
f58a1acc DV |
371 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { |
372 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); | |
373 | return false; | |
374 | } | |
375 | ||
2a7aceec | 376 | pipe_config->pipe_bpp = 24; |
f58a1acc | 377 | } |
2a7aceec | 378 | |
8f7abfd8 | 379 | /* FDI must always be 2.7 GHz */ |
2f26cdc0 | 380 | pipe_config->port_clock = 135000 * 2; |
00490c22 | 381 | |
79e53945 JB |
382 | return true; |
383 | } | |
384 | ||
f2b115e6 | 385 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
386 | { |
387 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 388 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 389 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7dbb2f2 | 390 | u32 adpa; |
2c07245f ZW |
391 | bool ret; |
392 | ||
e7dbb2f2 KP |
393 | /* The first time through, trigger an explicit detection cycle */ |
394 | if (crt->force_hotplug_required) { | |
6e266956 | 395 | bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); |
e7dbb2f2 | 396 | u32 save_adpa; |
67941da2 | 397 | |
e7dbb2f2 KP |
398 | crt->force_hotplug_required = 0; |
399 | ||
ca54b810 | 400 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
401 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
402 | ||
403 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
404 | if (turn_off_dac) | |
405 | adpa &= ~ADPA_DAC_ENABLE; | |
406 | ||
ca54b810 | 407 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 408 | |
e1672d1c CW |
409 | if (intel_wait_for_register(dev_priv, |
410 | crt->adpa_reg, | |
411 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, | |
412 | 1000)) | |
e7dbb2f2 KP |
413 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
414 | ||
415 | if (turn_off_dac) { | |
ca54b810 VS |
416 | I915_WRITE(crt->adpa_reg, save_adpa); |
417 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 418 | } |
a4a6b901 ZW |
419 | } |
420 | ||
2c07245f | 421 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 422 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 423 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
424 | ret = true; |
425 | else | |
426 | ret = false; | |
e7dbb2f2 | 427 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 428 | |
2c07245f | 429 | return ret; |
79e53945 JB |
430 | } |
431 | ||
7d2c24e8 JB |
432 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
433 | { | |
434 | struct drm_device *dev = connector->dev; | |
ca54b810 | 435 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 436 | struct drm_i915_private *dev_priv = to_i915(dev); |
b236d7c8 | 437 | bool reenable_hpd; |
7d2c24e8 JB |
438 | u32 adpa; |
439 | bool ret; | |
440 | u32 save_adpa; | |
441 | ||
b236d7c8 L |
442 | /* |
443 | * Doing a force trigger causes a hpd interrupt to get sent, which can | |
444 | * get us stuck in a loop if we're polling: | |
445 | * - We enable power wells and reset the ADPA | |
446 | * - output_poll_exec does force probe on VGA, triggering a hpd | |
447 | * - HPD handler waits for poll to unlock dev->mode_config.mutex | |
448 | * - output_poll_exec shuts off the ADPA, unlocks | |
449 | * dev->mode_config.mutex | |
450 | * - HPD handler runs, resets ADPA and brings us back to the start | |
451 | * | |
452 | * Just disable HPD interrupts here to prevent this | |
453 | */ | |
454 | reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); | |
455 | ||
ca54b810 | 456 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
457 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
458 | ||
459 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
460 | ||
ca54b810 | 461 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 462 | |
a522ae4b CW |
463 | if (intel_wait_for_register(dev_priv, |
464 | crt->adpa_reg, | |
465 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0, | |
466 | 1000)) { | |
7d2c24e8 | 467 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
ca54b810 | 468 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
469 | } |
470 | ||
471 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 472 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
473 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
474 | ret = true; | |
475 | else | |
476 | ret = false; | |
477 | ||
478 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
479 | ||
b236d7c8 L |
480 | if (reenable_hpd) |
481 | intel_hpd_enable(dev_priv, crt->base.hpd_pin); | |
482 | ||
7d2c24e8 JB |
483 | return ret; |
484 | } | |
485 | ||
79e53945 JB |
486 | /** |
487 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
488 | * | |
489 | * Not for i915G/i915GM | |
490 | * | |
491 | * \return true if CRT is connected. | |
492 | * \return false if CRT is disconnected. | |
493 | */ | |
494 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
495 | { | |
496 | struct drm_device *dev = connector->dev; | |
fac5e23e | 497 | struct drm_i915_private *dev_priv = to_i915(dev); |
0706f17c | 498 | u32 stat; |
7a772c49 | 499 | bool ret = false; |
771cb081 | 500 | int i, tries = 0; |
2c07245f | 501 | |
6e266956 | 502 | if (HAS_PCH_SPLIT(dev_priv)) |
f2b115e6 | 503 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 504 | |
11a914c2 | 505 | if (IS_VALLEYVIEW(dev_priv)) |
7d2c24e8 JB |
506 | return valleyview_crt_detect_hotplug(connector); |
507 | ||
771cb081 ZY |
508 | /* |
509 | * On 4 series desktop, CRT detect sequence need to be done twice | |
510 | * to get a reliable result. | |
511 | */ | |
79e53945 | 512 | |
50a0bc90 | 513 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) |
771cb081 ZY |
514 | tries = 2; |
515 | else | |
516 | tries = 1; | |
771cb081 | 517 | |
771cb081 | 518 | for (i = 0; i < tries ; i++) { |
771cb081 | 519 | /* turn on the FORCE_DETECT */ |
0706f17c EE |
520 | i915_hotplug_interrupt_update(dev_priv, |
521 | CRT_HOTPLUG_FORCE_DETECT, | |
522 | CRT_HOTPLUG_FORCE_DETECT); | |
771cb081 | 523 | /* wait for FORCE_DETECT to go off */ |
fd3790d4 CW |
524 | if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN, |
525 | CRT_HOTPLUG_FORCE_DETECT, 0, | |
526 | 1000)) | |
79077319 | 527 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 528 | } |
79e53945 | 529 | |
7a772c49 AJ |
530 | stat = I915_READ(PORT_HOTPLUG_STAT); |
531 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
532 | ret = true; | |
533 | ||
534 | /* clear the interrupt we just generated, if any */ | |
535 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 536 | |
0706f17c | 537 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
7a772c49 AJ |
538 | |
539 | return ret; | |
79e53945 JB |
540 | } |
541 | ||
f1a2f5b7 JN |
542 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
543 | struct i2c_adapter *i2c) | |
544 | { | |
545 | struct edid *edid; | |
546 | ||
547 | edid = drm_get_edid(connector, i2c); | |
548 | ||
549 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
550 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
551 | intel_gmbus_force_bit(i2c, true); | |
552 | edid = drm_get_edid(connector, i2c); | |
553 | intel_gmbus_force_bit(i2c, false); | |
554 | } | |
555 | ||
556 | return edid; | |
557 | } | |
558 | ||
559 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
560 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
561 | struct i2c_adapter *adapter) | |
562 | { | |
563 | struct edid *edid; | |
ebda95a9 | 564 | int ret; |
f1a2f5b7 JN |
565 | |
566 | edid = intel_crt_get_edid(connector, adapter); | |
567 | if (!edid) | |
568 | return 0; | |
569 | ||
ebda95a9 JN |
570 | ret = intel_connector_update_modes(connector, edid); |
571 | kfree(edid); | |
572 | ||
573 | return ret; | |
f1a2f5b7 JN |
574 | } |
575 | ||
f5afcd3d | 576 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 577 | { |
f5afcd3d | 578 | struct intel_crt *crt = intel_attached_crt(connector); |
fac5e23e | 579 | struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); |
a2bd1f54 DV |
580 | struct edid *edid; |
581 | struct i2c_adapter *i2c; | |
c96b63a6 | 582 | bool ret = false; |
79e53945 | 583 | |
a2bd1f54 | 584 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 585 | |
41aa3448 | 586 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 587 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
588 | |
589 | if (edid) { | |
590 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 591 | |
f5afcd3d DM |
592 | /* |
593 | * This may be a DVI-I connector with a shared DDC | |
594 | * link between analog and digital outputs, so we | |
595 | * have to check the EDID input spec of the attached device. | |
596 | */ | |
f5afcd3d DM |
597 | if (!is_digital) { |
598 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
c96b63a6 ACO |
599 | ret = true; |
600 | } else { | |
601 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
f5afcd3d | 602 | } |
a2bd1f54 DV |
603 | } else { |
604 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
605 | } |
606 | ||
a2bd1f54 DV |
607 | kfree(edid); |
608 | ||
c96b63a6 | 609 | return ret; |
79e53945 JB |
610 | } |
611 | ||
e4a5d54f | 612 | static enum drm_connector_status |
c8ecb2f1 | 613 | intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) |
e4a5d54f | 614 | { |
7173188d | 615 | struct drm_device *dev = crt->base.base.dev; |
fac5e23e | 616 | struct drm_i915_private *dev_priv = to_i915(dev); |
e4a5d54f ML |
617 | uint32_t save_bclrpat; |
618 | uint32_t save_vtotal; | |
619 | uint32_t vtotal, vactive; | |
620 | uint32_t vsample; | |
621 | uint32_t vblank, vblank_start, vblank_end; | |
622 | uint32_t dsl; | |
f0f59a00 VS |
623 | i915_reg_t bclrpat_reg, vtotal_reg, |
624 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; | |
e4a5d54f ML |
625 | uint8_t st00; |
626 | enum drm_connector_status status; | |
627 | ||
6ec3d0c0 CW |
628 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
629 | ||
9db4a9c7 JB |
630 | bclrpat_reg = BCLRPAT(pipe); |
631 | vtotal_reg = VTOTAL(pipe); | |
632 | vblank_reg = VBLANK(pipe); | |
633 | vsync_reg = VSYNC(pipe); | |
634 | pipeconf_reg = PIPECONF(pipe); | |
635 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
636 | |
637 | save_bclrpat = I915_READ(bclrpat_reg); | |
638 | save_vtotal = I915_READ(vtotal_reg); | |
639 | vblank = I915_READ(vblank_reg); | |
640 | ||
641 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
642 | vactive = (save_vtotal & 0x7ff) + 1; | |
643 | ||
644 | vblank_start = (vblank & 0xfff) + 1; | |
645 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
646 | ||
647 | /* Set the border color to purple. */ | |
648 | I915_WRITE(bclrpat_reg, 0x500050); | |
649 | ||
5db94019 | 650 | if (!IS_GEN2(dev_priv)) { |
e4a5d54f ML |
651 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
652 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 653 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
654 | /* Wait for next Vblank to substitue |
655 | * border color for Color info */ | |
0f0f74bc | 656 | intel_wait_for_vblank(dev_priv, pipe); |
f0f59a00 | 657 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
658 | status = ((st00 & (1 << 4)) != 0) ? |
659 | connector_status_connected : | |
660 | connector_status_disconnected; | |
661 | ||
662 | I915_WRITE(pipeconf_reg, pipeconf); | |
663 | } else { | |
664 | bool restore_vblank = false; | |
665 | int count, detect; | |
666 | ||
667 | /* | |
668 | * If there isn't any border, add some. | |
669 | * Yes, this will flicker | |
670 | */ | |
671 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
672 | uint32_t vsync = I915_READ(vsync_reg); | |
673 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
674 | ||
675 | vblank_start = vsync_start; | |
676 | I915_WRITE(vblank_reg, | |
677 | (vblank_start - 1) | | |
678 | ((vblank_end - 1) << 16)); | |
679 | restore_vblank = true; | |
680 | } | |
681 | /* sample in the vertical border, selecting the larger one */ | |
682 | if (vblank_start - vactive >= vtotal - vblank_end) | |
683 | vsample = (vblank_start + vactive) >> 1; | |
684 | else | |
685 | vsample = (vtotal + vblank_end) >> 1; | |
686 | ||
687 | /* | |
688 | * Wait for the border to be displayed | |
689 | */ | |
690 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
691 | ; | |
692 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
693 | ; | |
694 | /* | |
695 | * Watch ST00 for an entire scanline | |
696 | */ | |
697 | detect = 0; | |
698 | count = 0; | |
699 | do { | |
700 | count++; | |
701 | /* Read the ST00 VGA status register */ | |
f0f59a00 | 702 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
703 | if (st00 & (1 << 4)) |
704 | detect++; | |
705 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
706 | ||
707 | /* restore vblank if necessary */ | |
708 | if (restore_vblank) | |
709 | I915_WRITE(vblank_reg, vblank); | |
710 | /* | |
711 | * If more than 3/4 of the scanline detected a monitor, | |
712 | * then it is assumed to be present. This works even on i830, | |
713 | * where there isn't any way to force the border color across | |
714 | * the screen | |
715 | */ | |
716 | status = detect * 4 > count * 3 ? | |
717 | connector_status_connected : | |
718 | connector_status_disconnected; | |
719 | } | |
720 | ||
721 | /* Restore previous settings */ | |
722 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
723 | ||
724 | return status; | |
725 | } | |
726 | ||
f0dfb1a8 VS |
727 | static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) |
728 | { | |
729 | DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); | |
730 | return 1; | |
731 | } | |
732 | ||
733 | static const struct dmi_system_id intel_spurious_crt_detect[] = { | |
734 | { | |
735 | .callback = intel_spurious_crt_detect_dmi_callback, | |
736 | .ident = "ACER ZGB", | |
737 | .matches = { | |
738 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
739 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
740 | }, | |
741 | }, | |
69a44b16 VS |
742 | { |
743 | .callback = intel_spurious_crt_detect_dmi_callback, | |
744 | .ident = "Intel DZ77BH-55K", | |
745 | .matches = { | |
746 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), | |
747 | DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), | |
748 | }, | |
749 | }, | |
f0dfb1a8 VS |
750 | { } |
751 | }; | |
752 | ||
6c5ed5ae ML |
753 | static int |
754 | intel_crt_detect(struct drm_connector *connector, | |
755 | struct drm_modeset_acquire_ctx *ctx, | |
756 | bool force) | |
79e53945 | 757 | { |
66478475 | 758 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
c9a1c4cd | 759 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 | 760 | struct intel_encoder *intel_encoder = &crt->base; |
6c5ed5ae | 761 | int status, ret; |
e95c8438 | 762 | struct intel_load_detect_pipe tmp; |
79e53945 | 763 | |
164c8598 | 764 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 765 | connector->base.id, connector->name, |
164c8598 CW |
766 | force); |
767 | ||
f0dfb1a8 VS |
768 | /* Skip machines without VGA that falsely report hotplug events */ |
769 | if (dmi_check_system(intel_spurious_crt_detect)) | |
770 | return connector_status_disconnected; | |
771 | ||
79f255a0 | 772 | intel_display_power_get(dev_priv, intel_encoder->power_domain); |
671dedd2 | 773 | |
56b857a5 | 774 | if (I915_HAS_HOTPLUG(dev_priv)) { |
aaa37730 DV |
775 | /* We can not rely on the HPD pin always being correctly wired |
776 | * up, for example many KVM do not pass it through, and so | |
777 | * only trust an assertion that the monitor is connected. | |
778 | */ | |
6ec3d0c0 CW |
779 | if (intel_crt_detect_hotplug(connector)) { |
780 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
781 | status = connector_status_connected; |
782 | goto out; | |
aaa37730 | 783 | } else |
e7dbb2f2 | 784 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
785 | } |
786 | ||
c19a0df2 PZ |
787 | if (intel_crt_detect_ddc(connector)) { |
788 | status = connector_status_connected; | |
789 | goto out; | |
790 | } | |
79e53945 | 791 | |
aaa37730 DV |
792 | /* Load detection is broken on HPD capable machines. Whoever wants a |
793 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
794 | * to have the right resistors for HP detection) needs to fix this up. | |
795 | * For now just bail out. */ | |
4f044a88 | 796 | if (I915_HAS_HOTPLUG(dev_priv) && !i915_modparams.load_detect_test) { |
c19a0df2 PZ |
797 | status = connector_status_disconnected; |
798 | goto out; | |
799 | } | |
aaa37730 | 800 | |
c19a0df2 PZ |
801 | if (!force) { |
802 | status = connector->status; | |
803 | goto out; | |
804 | } | |
7b334fcb | 805 | |
e4a5d54f | 806 | /* for pre-945g platforms use load detect */ |
6c5ed5ae ML |
807 | ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx); |
808 | if (ret > 0) { | |
e95c8438 DV |
809 | if (intel_crt_detect_ddc(connector)) |
810 | status = connector_status_connected; | |
66478475 | 811 | else if (INTEL_GEN(dev_priv) < 4) |
c8ecb2f1 ML |
812 | status = intel_crt_load_detect(crt, |
813 | to_intel_crtc(connector->state->crtc)->pipe); | |
4f044a88 | 814 | else if (i915_modparams.load_detect_test) |
32fff610 | 815 | status = connector_status_disconnected; |
5bedeb2d DV |
816 | else |
817 | status = connector_status_unknown; | |
6c5ed5ae ML |
818 | intel_release_load_detect_pipe(connector, &tmp, ctx); |
819 | } else if (ret == 0) | |
e95c8438 | 820 | status = connector_status_unknown; |
6c5ed5ae ML |
821 | else if (ret < 0) |
822 | status = ret; | |
208bf9fd | 823 | |
c19a0df2 | 824 | out: |
79f255a0 | 825 | intel_display_power_put(dev_priv, intel_encoder->power_domain); |
e4a5d54f | 826 | return status; |
79e53945 JB |
827 | } |
828 | ||
829 | static void intel_crt_destroy(struct drm_connector *connector) | |
830 | { | |
79e53945 JB |
831 | drm_connector_cleanup(connector); |
832 | kfree(connector); | |
833 | } | |
834 | ||
835 | static int intel_crt_get_modes(struct drm_connector *connector) | |
836 | { | |
8e4d36b9 | 837 | struct drm_device *dev = connector->dev; |
fac5e23e | 838 | struct drm_i915_private *dev_priv = to_i915(dev); |
671dedd2 ID |
839 | struct intel_crt *crt = intel_attached_crt(connector); |
840 | struct intel_encoder *intel_encoder = &crt->base; | |
890f3359 | 841 | int ret; |
3bd7d909 | 842 | struct i2c_adapter *i2c; |
8e4d36b9 | 843 | |
79f255a0 | 844 | intel_display_power_get(dev_priv, intel_encoder->power_domain); |
671dedd2 | 845 | |
41aa3448 | 846 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 847 | ret = intel_crt_ddc_get_modes(connector, i2c); |
9beb5fea | 848 | if (ret || !IS_G4X(dev_priv)) |
671dedd2 | 849 | goto out; |
8e4d36b9 | 850 | |
8e4d36b9 | 851 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
988c7015 | 852 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
671dedd2 ID |
853 | ret = intel_crt_ddc_get_modes(connector, i2c); |
854 | ||
855 | out: | |
79f255a0 | 856 | intel_display_power_put(dev_priv, intel_encoder->power_domain); |
671dedd2 ID |
857 | |
858 | return ret; | |
79e53945 JB |
859 | } |
860 | ||
9504a892 | 861 | void intel_crt_reset(struct drm_encoder *encoder) |
f3269058 | 862 | { |
66478475 | 863 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
28cf71ce | 864 | struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); |
f3269058 | 865 | |
66478475 | 866 | if (INTEL_GEN(dev_priv) >= 5) { |
2e938892 DV |
867 | u32 adpa; |
868 | ||
ca54b810 | 869 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
870 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
871 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
872 | I915_WRITE(crt->adpa_reg, adpa); |
873 | POSTING_READ(crt->adpa_reg); | |
2e938892 | 874 | |
0039a4b3 | 875 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
f3269058 | 876 | crt->force_hotplug_required = 1; |
2e938892 DV |
877 | } |
878 | ||
f3269058 CW |
879 | } |
880 | ||
79e53945 JB |
881 | /* |
882 | * Routines for controlling stuff on the analog port | |
883 | */ | |
884 | ||
79e53945 | 885 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
79e53945 | 886 | .fill_modes = drm_helper_probe_single_connector_modes, |
1ebaa0b9 | 887 | .late_register = intel_connector_register, |
c191eca1 | 888 | .early_unregister = intel_connector_unregister, |
79e53945 | 889 | .destroy = intel_crt_destroy, |
c6f95f27 | 890 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 891 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
892 | }; |
893 | ||
894 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
6c5ed5ae | 895 | .detect_ctx = intel_crt_detect, |
79e53945 JB |
896 | .mode_valid = intel_crt_mode_valid, |
897 | .get_modes = intel_crt_get_modes, | |
79e53945 JB |
898 | }; |
899 | ||
79e53945 | 900 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
28cf71ce | 901 | .reset = intel_crt_reset, |
ea5b213a | 902 | .destroy = intel_encoder_destroy, |
79e53945 JB |
903 | }; |
904 | ||
c39055b0 | 905 | void intel_crt_init(struct drm_i915_private *dev_priv) |
79e53945 JB |
906 | { |
907 | struct drm_connector *connector; | |
c9a1c4cd | 908 | struct intel_crt *crt; |
454c1ca8 | 909 | struct intel_connector *intel_connector; |
6c03a6bd VS |
910 | i915_reg_t adpa_reg; |
911 | u32 adpa; | |
79e53945 | 912 | |
6e266956 | 913 | if (HAS_PCH_SPLIT(dev_priv)) |
6c03a6bd | 914 | adpa_reg = PCH_ADPA; |
11a914c2 | 915 | else if (IS_VALLEYVIEW(dev_priv)) |
6c03a6bd VS |
916 | adpa_reg = VLV_ADPA; |
917 | else | |
918 | adpa_reg = ADPA; | |
919 | ||
920 | adpa = I915_READ(adpa_reg); | |
921 | if ((adpa & ADPA_DAC_ENABLE) == 0) { | |
922 | /* | |
923 | * On some machines (some IVB at least) CRT can be | |
924 | * fused off, but there's no known fuse bit to | |
925 | * indicate that. On these machine the ADPA register | |
926 | * works normally, except the DAC enable bit won't | |
927 | * take. So the only way to tell is attempt to enable | |
928 | * it and see what happens. | |
929 | */ | |
930 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | | |
931 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | |
932 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) | |
933 | return; | |
934 | I915_WRITE(adpa_reg, adpa); | |
935 | } | |
936 | ||
c9a1c4cd CW |
937 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
938 | if (!crt) | |
79e53945 JB |
939 | return; |
940 | ||
9bdbd0b9 | 941 | intel_connector = intel_connector_alloc(); |
454c1ca8 | 942 | if (!intel_connector) { |
c9a1c4cd | 943 | kfree(crt); |
454c1ca8 ZW |
944 | return; |
945 | } | |
946 | ||
947 | connector = &intel_connector->base; | |
637f44d2 | 948 | crt->connector = intel_connector; |
c39055b0 | 949 | drm_connector_init(&dev_priv->drm, &intel_connector->base, |
79e53945 JB |
950 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
951 | ||
c39055b0 | 952 | drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, |
580d8ed5 | 953 | DRM_MODE_ENCODER_DAC, "CRT"); |
79e53945 | 954 | |
c9a1c4cd | 955 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 956 | |
c9a1c4cd | 957 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 958 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
50a0bc90 | 959 | if (IS_I830(dev_priv)) |
59c859d6 ED |
960 | crt->base.crtc_mask = (1 << 0); |
961 | else | |
0826874a | 962 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 963 | |
5db94019 | 964 | if (IS_GEN2(dev_priv)) |
dbb02575 DV |
965 | connector->interlace_allowed = 0; |
966 | else | |
967 | connector->interlace_allowed = 1; | |
79e53945 JB |
968 | connector->doublescan_allowed = 0; |
969 | ||
6c03a6bd | 970 | crt->adpa_reg = adpa_reg; |
540a8950 | 971 | |
79f255a0 ACO |
972 | crt->base.power_domain = POWER_DOMAIN_PORT_CRT; |
973 | ||
56b857a5 | 974 | if (I915_HAS_HOTPLUG(dev_priv) && |
f0dfb1a8 | 975 | !dmi_check_system(intel_spurious_crt_detect)) |
1d843f9d | 976 | crt->base.hpd_pin = HPD_CRT; |
c5ce4ef3 | 977 | |
4f8036a2 | 978 | if (HAS_DDI(dev_priv)) { |
03cdc1d4 | 979 | crt->base.port = PORT_E; |
a2985791 | 980 | crt->base.get_config = hsw_crt_get_config; |
4eda01b2 | 981 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
2f26cdc0 | 982 | crt->base.compute_config = hsw_crt_compute_config; |
51c4fa69 JN |
983 | crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; |
984 | crt->base.pre_enable = hsw_pre_enable_crt; | |
985 | crt->base.enable = hsw_enable_crt; | |
3daa3cee | 986 | crt->base.disable = hsw_disable_crt; |
b7076546 | 987 | crt->base.post_disable = hsw_post_disable_crt; |
a2985791 | 988 | } else { |
c5ce4ef3 | 989 | if (HAS_PCH_SPLIT(dev_priv)) { |
2f26cdc0 | 990 | crt->base.compute_config = pch_crt_compute_config; |
c5ce4ef3 JN |
991 | crt->base.disable = pch_disable_crt; |
992 | crt->base.post_disable = pch_post_disable_crt; | |
993 | } else { | |
2f26cdc0 | 994 | crt->base.compute_config = intel_crt_compute_config; |
c5ce4ef3 JN |
995 | crt->base.disable = intel_disable_crt; |
996 | } | |
03cdc1d4 | 997 | crt->base.port = PORT_NONE; |
a2985791 | 998 | crt->base.get_config = intel_crt_get_config; |
4eda01b2 | 999 | crt->base.get_hw_state = intel_crt_get_hw_state; |
51c4fa69 | 1000 | crt->base.enable = intel_enable_crt; |
a2985791 | 1001 | } |
e403fc94 | 1002 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
df0323c4 | 1003 | |
79e53945 JB |
1004 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
1005 | ||
56b857a5 | 1006 | if (!I915_HAS_HOTPLUG(dev_priv)) |
821450c6 | 1007 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
eb1f8e4f | 1008 | |
e7dbb2f2 KP |
1009 | /* |
1010 | * Configure the automatic hotplug detection stuff | |
1011 | */ | |
1012 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 1013 | |
68d18ad7 | 1014 | /* |
3e68320e DL |
1015 | * TODO: find a proper way to discover whether we need to set the the |
1016 | * polarity and link reversal bits or not, instead of relying on the | |
1017 | * BIOS. | |
68d18ad7 | 1018 | */ |
6e266956 | 1019 | if (HAS_PCH_LPT(dev_priv)) { |
3e68320e DL |
1020 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
1021 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
1022 | ||
eede3b53 | 1023 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
3e68320e | 1024 | } |
754970ee | 1025 | |
28cf71ce | 1026 | intel_crt_reset(&crt->base.base); |
79e53945 | 1027 | } |