Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 | 30 | #include <drm/drmP.h> |
c6f95f27 | 31 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
79e53945 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
79e53945 JB |
37 | #include "i915_drv.h" |
38 | ||
e7dbb2f2 KP |
39 | /* Here's the desired hotplug mode */ |
40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
45 | ADPA_CRT_HOTPLUG_ENABLE) | |
46 | ||
c9a1c4cd CW |
47 | struct intel_crt { |
48 | struct intel_encoder base; | |
637f44d2 AJ |
49 | /* DPMS state is stored in the connector, which we need in the |
50 | * encoder's enable/disable callbacks */ | |
51 | struct intel_connector *connector; | |
e7dbb2f2 | 52 | bool force_hotplug_required; |
f0f59a00 | 53 | i915_reg_t adpa_reg; |
c9a1c4cd CW |
54 | }; |
55 | ||
eebe6f0b | 56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 57 | { |
eebe6f0b | 58 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
59 | } |
60 | ||
eebe6f0b | 61 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 62 | { |
eebe6f0b | 63 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
64 | } |
65 | ||
e403fc94 DV |
66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
67 | enum pipe *pipe) | |
79e53945 | 68 | { |
e403fc94 | 69 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
e403fc94 | 71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
6d129bea | 72 | enum intel_display_power_domain power_domain; |
e403fc94 | 73 | u32 tmp; |
1c8fdda1 | 74 | bool ret; |
e403fc94 | 75 | |
6d129bea | 76 | power_domain = intel_display_port_power_domain(encoder); |
1c8fdda1 | 77 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
78 | return false; |
79 | ||
1c8fdda1 ID |
80 | ret = false; |
81 | ||
e403fc94 DV |
82 | tmp = I915_READ(crt->adpa_reg); |
83 | ||
84 | if (!(tmp & ADPA_DAC_ENABLE)) | |
1c8fdda1 | 85 | goto out; |
e403fc94 DV |
86 | |
87 | if (HAS_PCH_CPT(dev)) | |
88 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
89 | else | |
90 | *pipe = PORT_TO_PIPE(tmp); | |
91 | ||
1c8fdda1 ID |
92 | ret = true; |
93 | out: | |
94 | intel_display_power_put(dev_priv, power_domain); | |
95 | ||
96 | return ret; | |
e403fc94 DV |
97 | } |
98 | ||
6801c18c | 99 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 JB |
100 | { |
101 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
102 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
103 | u32 tmp, flags = 0; | |
104 | ||
105 | tmp = I915_READ(crt->adpa_reg); | |
106 | ||
107 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
108 | flags |= DRM_MODE_FLAG_PHSYNC; | |
109 | else | |
110 | flags |= DRM_MODE_FLAG_NHSYNC; | |
111 | ||
112 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
113 | flags |= DRM_MODE_FLAG_PVSYNC; | |
114 | else | |
115 | flags |= DRM_MODE_FLAG_NVSYNC; | |
116 | ||
6801c18c VS |
117 | return flags; |
118 | } | |
119 | ||
120 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 121 | struct intel_crtc_state *pipe_config) |
6801c18c VS |
122 | { |
123 | struct drm_device *dev = encoder->base.dev; | |
124 | int dotclock; | |
125 | ||
2d112de7 | 126 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 VS |
127 | |
128 | dotclock = pipe_config->port_clock; | |
129 | ||
6801c18c | 130 | if (HAS_PCH_SPLIT(dev)) |
18442d08 VS |
131 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
132 | ||
2d112de7 | 133 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
134 | } |
135 | ||
6801c18c | 136 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 137 | struct intel_crtc_state *pipe_config) |
6801c18c VS |
138 | { |
139 | intel_ddi_get_config(encoder, pipe_config); | |
140 | ||
2d112de7 | 141 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
142 | DRM_MODE_FLAG_NHSYNC | |
143 | DRM_MODE_FLAG_PVSYNC | | |
144 | DRM_MODE_FLAG_NVSYNC); | |
2d112de7 | 145 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
6801c18c VS |
146 | } |
147 | ||
b2cabb0e DV |
148 | /* Note: The caller is required to filter out dpms modes not supported by the |
149 | * platform. */ | |
150 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) | |
df0323c4 | 151 | { |
b2cabb0e | 152 | struct drm_device *dev = encoder->base.dev; |
df0323c4 | 153 | struct drm_i915_private *dev_priv = dev->dev_private; |
b2cabb0e | 154 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
894ed1ec | 155 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
7c5f93b0 | 156 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
894ed1ec DV |
157 | u32 adpa; |
158 | ||
159 | if (INTEL_INFO(dev)->gen >= 5) | |
160 | adpa = ADPA_HOTPLUG_BITS; | |
161 | else | |
162 | adpa = 0; | |
df0323c4 | 163 | |
894ed1ec DV |
164 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
165 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
166 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
167 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
168 | ||
169 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
170 | if (HAS_PCH_LPT(dev)) | |
171 | ; /* Those bits don't exist here */ | |
172 | else if (HAS_PCH_CPT(dev)) | |
173 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); | |
174 | else if (crtc->pipe == 0) | |
175 | adpa |= ADPA_PIPE_A_SELECT; | |
176 | else | |
177 | adpa |= ADPA_PIPE_B_SELECT; | |
178 | ||
179 | if (!HAS_PCH_SPLIT(dev)) | |
180 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
79e53945 | 181 | |
0206e353 | 182 | switch (mode) { |
79e53945 | 183 | case DRM_MODE_DPMS_ON: |
894ed1ec | 184 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
185 | break; |
186 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 187 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
188 | break; |
189 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 190 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
191 | break; |
192 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 193 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
194 | break; |
195 | } | |
196 | ||
894ed1ec | 197 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 198 | } |
2c07245f | 199 | |
637f44d2 AJ |
200 | static void intel_disable_crt(struct intel_encoder *encoder) |
201 | { | |
202 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); | |
203 | } | |
204 | ||
1ea56e26 VS |
205 | static void pch_disable_crt(struct intel_encoder *encoder) |
206 | { | |
207 | } | |
208 | ||
209 | static void pch_post_disable_crt(struct intel_encoder *encoder) | |
210 | { | |
211 | intel_disable_crt(encoder); | |
212 | } | |
abfdc1e3 | 213 | |
637f44d2 AJ |
214 | static void intel_enable_crt(struct intel_encoder *encoder) |
215 | { | |
216 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
217 | ||
218 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); | |
219 | } | |
220 | ||
c19de8eb DL |
221 | static enum drm_mode_status |
222 | intel_crt_mode_valid(struct drm_connector *connector, | |
223 | struct drm_display_mode *mode) | |
79e53945 | 224 | { |
6bcdcd9e | 225 | struct drm_device *dev = connector->dev; |
f8700b34 | 226 | int max_dotclk = to_i915(dev)->max_dotclk_freq; |
6bcdcd9e ZY |
227 | |
228 | int max_clock = 0; | |
79e53945 JB |
229 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
230 | return MODE_NO_DBLESCAN; | |
231 | ||
6bcdcd9e ZY |
232 | if (mode->clock < 25000) |
233 | return MODE_CLOCK_LOW; | |
234 | ||
a6c45cf0 | 235 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
236 | max_clock = 350000; |
237 | else | |
238 | max_clock = 400000; | |
239 | if (mode->clock > max_clock) | |
240 | return MODE_CLOCK_HIGH; | |
79e53945 | 241 | |
f8700b34 MK |
242 | if (mode->clock > max_dotclk) |
243 | return MODE_CLOCK_HIGH; | |
244 | ||
d4b1931c PZ |
245 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
246 | if (HAS_PCH_LPT(dev) && | |
247 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) | |
248 | return MODE_CLOCK_HIGH; | |
249 | ||
79e53945 JB |
250 | return MODE_OK; |
251 | } | |
252 | ||
5bfe2ac0 | 253 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
5cec258b | 254 | struct intel_crtc_state *pipe_config) |
79e53945 | 255 | { |
5bfe2ac0 DV |
256 | struct drm_device *dev = encoder->base.dev; |
257 | ||
258 | if (HAS_PCH_SPLIT(dev)) | |
259 | pipe_config->has_pch_encoder = true; | |
260 | ||
2a7aceec DV |
261 | /* LPT FDI RX only supports 8bpc. */ |
262 | if (HAS_PCH_LPT(dev)) | |
263 | pipe_config->pipe_bpp = 24; | |
264 | ||
8f7abfd8 | 265 | /* FDI must always be 2.7 GHz */ |
0e50338c DV |
266 | if (HAS_DDI(dev)) { |
267 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
8f7abfd8 | 268 | pipe_config->port_clock = 135000 * 2; |
00490c22 ML |
269 | |
270 | pipe_config->dpll_hw_state.wrpll = 0; | |
271 | pipe_config->dpll_hw_state.spll = | |
272 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; | |
0e50338c | 273 | } |
8f7abfd8 | 274 | |
79e53945 JB |
275 | return true; |
276 | } | |
277 | ||
f2b115e6 | 278 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
279 | { |
280 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 281 | struct intel_crt *crt = intel_attached_crt(connector); |
2c07245f | 282 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7dbb2f2 | 283 | u32 adpa; |
2c07245f ZW |
284 | bool ret; |
285 | ||
e7dbb2f2 KP |
286 | /* The first time through, trigger an explicit detection cycle */ |
287 | if (crt->force_hotplug_required) { | |
288 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
289 | u32 save_adpa; | |
67941da2 | 290 | |
e7dbb2f2 KP |
291 | crt->force_hotplug_required = 0; |
292 | ||
ca54b810 | 293 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
294 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
295 | ||
296 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
297 | if (turn_off_dac) | |
298 | adpa &= ~ADPA_DAC_ENABLE; | |
299 | ||
ca54b810 | 300 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 301 | |
ca54b810 | 302 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
e7dbb2f2 KP |
303 | 1000)) |
304 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
305 | ||
306 | if (turn_off_dac) { | |
ca54b810 VS |
307 | I915_WRITE(crt->adpa_reg, save_adpa); |
308 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 309 | } |
a4a6b901 ZW |
310 | } |
311 | ||
2c07245f | 312 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 313 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 314 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
315 | ret = true; |
316 | else | |
317 | ret = false; | |
e7dbb2f2 | 318 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 319 | |
2c07245f | 320 | return ret; |
79e53945 JB |
321 | } |
322 | ||
7d2c24e8 JB |
323 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
324 | { | |
325 | struct drm_device *dev = connector->dev; | |
ca54b810 | 326 | struct intel_crt *crt = intel_attached_crt(connector); |
7d2c24e8 JB |
327 | struct drm_i915_private *dev_priv = dev->dev_private; |
328 | u32 adpa; | |
329 | bool ret; | |
330 | u32 save_adpa; | |
331 | ||
ca54b810 | 332 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
333 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
334 | ||
335 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
336 | ||
ca54b810 | 337 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 338 | |
ca54b810 | 339 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
7d2c24e8 JB |
340 | 1000)) { |
341 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
ca54b810 | 342 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
343 | } |
344 | ||
345 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 346 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
347 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
348 | ret = true; | |
349 | else | |
350 | ret = false; | |
351 | ||
352 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
353 | ||
7d2c24e8 JB |
354 | return ret; |
355 | } | |
356 | ||
79e53945 JB |
357 | /** |
358 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
359 | * | |
360 | * Not for i915G/i915GM | |
361 | * | |
362 | * \return true if CRT is connected. | |
363 | * \return false if CRT is disconnected. | |
364 | */ | |
365 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
366 | { | |
367 | struct drm_device *dev = connector->dev; | |
368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0706f17c | 369 | u32 stat; |
7a772c49 | 370 | bool ret = false; |
771cb081 | 371 | int i, tries = 0; |
2c07245f | 372 | |
bad720ff | 373 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 374 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 375 | |
7d2c24e8 JB |
376 | if (IS_VALLEYVIEW(dev)) |
377 | return valleyview_crt_detect_hotplug(connector); | |
378 | ||
771cb081 ZY |
379 | /* |
380 | * On 4 series desktop, CRT detect sequence need to be done twice | |
381 | * to get a reliable result. | |
382 | */ | |
79e53945 | 383 | |
771cb081 ZY |
384 | if (IS_G4X(dev) && !IS_GM45(dev)) |
385 | tries = 2; | |
386 | else | |
387 | tries = 1; | |
771cb081 | 388 | |
771cb081 | 389 | for (i = 0; i < tries ; i++) { |
771cb081 | 390 | /* turn on the FORCE_DETECT */ |
0706f17c EE |
391 | i915_hotplug_interrupt_update(dev_priv, |
392 | CRT_HOTPLUG_FORCE_DETECT, | |
393 | CRT_HOTPLUG_FORCE_DETECT); | |
771cb081 | 394 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
395 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
396 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 397 | 1000)) |
79077319 | 398 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 399 | } |
79e53945 | 400 | |
7a772c49 AJ |
401 | stat = I915_READ(PORT_HOTPLUG_STAT); |
402 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
403 | ret = true; | |
404 | ||
405 | /* clear the interrupt we just generated, if any */ | |
406 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 407 | |
0706f17c | 408 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
7a772c49 AJ |
409 | |
410 | return ret; | |
79e53945 JB |
411 | } |
412 | ||
f1a2f5b7 JN |
413 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
414 | struct i2c_adapter *i2c) | |
415 | { | |
416 | struct edid *edid; | |
417 | ||
418 | edid = drm_get_edid(connector, i2c); | |
419 | ||
420 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
421 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
422 | intel_gmbus_force_bit(i2c, true); | |
423 | edid = drm_get_edid(connector, i2c); | |
424 | intel_gmbus_force_bit(i2c, false); | |
425 | } | |
426 | ||
427 | return edid; | |
428 | } | |
429 | ||
430 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
431 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
432 | struct i2c_adapter *adapter) | |
433 | { | |
434 | struct edid *edid; | |
ebda95a9 | 435 | int ret; |
f1a2f5b7 JN |
436 | |
437 | edid = intel_crt_get_edid(connector, adapter); | |
438 | if (!edid) | |
439 | return 0; | |
440 | ||
ebda95a9 JN |
441 | ret = intel_connector_update_modes(connector, edid); |
442 | kfree(edid); | |
443 | ||
444 | return ret; | |
f1a2f5b7 JN |
445 | } |
446 | ||
f5afcd3d | 447 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 448 | { |
f5afcd3d | 449 | struct intel_crt *crt = intel_attached_crt(connector); |
c9a1c4cd | 450 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
a2bd1f54 DV |
451 | struct edid *edid; |
452 | struct i2c_adapter *i2c; | |
79e53945 | 453 | |
a2bd1f54 | 454 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 455 | |
41aa3448 | 456 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 457 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
458 | |
459 | if (edid) { | |
460 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 461 | |
f5afcd3d DM |
462 | /* |
463 | * This may be a DVI-I connector with a shared DDC | |
464 | * link between analog and digital outputs, so we | |
465 | * have to check the EDID input spec of the attached device. | |
466 | */ | |
f5afcd3d DM |
467 | if (!is_digital) { |
468 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
469 | return true; | |
470 | } | |
a2bd1f54 DV |
471 | |
472 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
473 | } else { | |
474 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
475 | } |
476 | ||
a2bd1f54 DV |
477 | kfree(edid); |
478 | ||
6ec3d0c0 | 479 | return false; |
79e53945 JB |
480 | } |
481 | ||
e4a5d54f | 482 | static enum drm_connector_status |
c8ecb2f1 | 483 | intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) |
e4a5d54f | 484 | { |
7173188d | 485 | struct drm_device *dev = crt->base.base.dev; |
e4a5d54f | 486 | struct drm_i915_private *dev_priv = dev->dev_private; |
e4a5d54f ML |
487 | uint32_t save_bclrpat; |
488 | uint32_t save_vtotal; | |
489 | uint32_t vtotal, vactive; | |
490 | uint32_t vsample; | |
491 | uint32_t vblank, vblank_start, vblank_end; | |
492 | uint32_t dsl; | |
f0f59a00 VS |
493 | i915_reg_t bclrpat_reg, vtotal_reg, |
494 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; | |
e4a5d54f ML |
495 | uint8_t st00; |
496 | enum drm_connector_status status; | |
497 | ||
6ec3d0c0 CW |
498 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
499 | ||
9db4a9c7 JB |
500 | bclrpat_reg = BCLRPAT(pipe); |
501 | vtotal_reg = VTOTAL(pipe); | |
502 | vblank_reg = VBLANK(pipe); | |
503 | vsync_reg = VSYNC(pipe); | |
504 | pipeconf_reg = PIPECONF(pipe); | |
505 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
506 | |
507 | save_bclrpat = I915_READ(bclrpat_reg); | |
508 | save_vtotal = I915_READ(vtotal_reg); | |
509 | vblank = I915_READ(vblank_reg); | |
510 | ||
511 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
512 | vactive = (save_vtotal & 0x7ff) + 1; | |
513 | ||
514 | vblank_start = (vblank & 0xfff) + 1; | |
515 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
516 | ||
517 | /* Set the border color to purple. */ | |
518 | I915_WRITE(bclrpat_reg, 0x500050); | |
519 | ||
a6c45cf0 | 520 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
521 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
522 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 523 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
524 | /* Wait for next Vblank to substitue |
525 | * border color for Color info */ | |
9d0498a2 | 526 | intel_wait_for_vblank(dev, pipe); |
f0f59a00 | 527 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
528 | status = ((st00 & (1 << 4)) != 0) ? |
529 | connector_status_connected : | |
530 | connector_status_disconnected; | |
531 | ||
532 | I915_WRITE(pipeconf_reg, pipeconf); | |
533 | } else { | |
534 | bool restore_vblank = false; | |
535 | int count, detect; | |
536 | ||
537 | /* | |
538 | * If there isn't any border, add some. | |
539 | * Yes, this will flicker | |
540 | */ | |
541 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
542 | uint32_t vsync = I915_READ(vsync_reg); | |
543 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
544 | ||
545 | vblank_start = vsync_start; | |
546 | I915_WRITE(vblank_reg, | |
547 | (vblank_start - 1) | | |
548 | ((vblank_end - 1) << 16)); | |
549 | restore_vblank = true; | |
550 | } | |
551 | /* sample in the vertical border, selecting the larger one */ | |
552 | if (vblank_start - vactive >= vtotal - vblank_end) | |
553 | vsample = (vblank_start + vactive) >> 1; | |
554 | else | |
555 | vsample = (vtotal + vblank_end) >> 1; | |
556 | ||
557 | /* | |
558 | * Wait for the border to be displayed | |
559 | */ | |
560 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
561 | ; | |
562 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
563 | ; | |
564 | /* | |
565 | * Watch ST00 for an entire scanline | |
566 | */ | |
567 | detect = 0; | |
568 | count = 0; | |
569 | do { | |
570 | count++; | |
571 | /* Read the ST00 VGA status register */ | |
f0f59a00 | 572 | st00 = I915_READ8(_VGA_MSR_WRITE); |
e4a5d54f ML |
573 | if (st00 & (1 << 4)) |
574 | detect++; | |
575 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
576 | ||
577 | /* restore vblank if necessary */ | |
578 | if (restore_vblank) | |
579 | I915_WRITE(vblank_reg, vblank); | |
580 | /* | |
581 | * If more than 3/4 of the scanline detected a monitor, | |
582 | * then it is assumed to be present. This works even on i830, | |
583 | * where there isn't any way to force the border color across | |
584 | * the screen | |
585 | */ | |
586 | status = detect * 4 > count * 3 ? | |
587 | connector_status_connected : | |
588 | connector_status_disconnected; | |
589 | } | |
590 | ||
591 | /* Restore previous settings */ | |
592 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
593 | ||
594 | return status; | |
595 | } | |
596 | ||
7b334fcb | 597 | static enum drm_connector_status |
930a9e28 | 598 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
599 | { |
600 | struct drm_device *dev = connector->dev; | |
c19a0df2 | 601 | struct drm_i915_private *dev_priv = dev->dev_private; |
c9a1c4cd | 602 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 ID |
603 | struct intel_encoder *intel_encoder = &crt->base; |
604 | enum intel_display_power_domain power_domain; | |
e4a5d54f | 605 | enum drm_connector_status status; |
e95c8438 | 606 | struct intel_load_detect_pipe tmp; |
51fd371b | 607 | struct drm_modeset_acquire_ctx ctx; |
79e53945 | 608 | |
164c8598 | 609 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 610 | connector->base.id, connector->name, |
164c8598 CW |
611 | force); |
612 | ||
671dedd2 ID |
613 | power_domain = intel_display_port_power_domain(intel_encoder); |
614 | intel_display_power_get(dev_priv, power_domain); | |
615 | ||
a6c45cf0 | 616 | if (I915_HAS_HOTPLUG(dev)) { |
aaa37730 DV |
617 | /* We can not rely on the HPD pin always being correctly wired |
618 | * up, for example many KVM do not pass it through, and so | |
619 | * only trust an assertion that the monitor is connected. | |
620 | */ | |
6ec3d0c0 CW |
621 | if (intel_crt_detect_hotplug(connector)) { |
622 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
623 | status = connector_status_connected; |
624 | goto out; | |
aaa37730 | 625 | } else |
e7dbb2f2 | 626 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
627 | } |
628 | ||
c19a0df2 PZ |
629 | if (intel_crt_detect_ddc(connector)) { |
630 | status = connector_status_connected; | |
631 | goto out; | |
632 | } | |
79e53945 | 633 | |
aaa37730 DV |
634 | /* Load detection is broken on HPD capable machines. Whoever wants a |
635 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
636 | * to have the right resistors for HP detection) needs to fix this up. | |
637 | * For now just bail out. */ | |
5bedeb2d | 638 | if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { |
c19a0df2 PZ |
639 | status = connector_status_disconnected; |
640 | goto out; | |
641 | } | |
aaa37730 | 642 | |
c19a0df2 PZ |
643 | if (!force) { |
644 | status = connector->status; | |
645 | goto out; | |
646 | } | |
7b334fcb | 647 | |
208bf9fd VS |
648 | drm_modeset_acquire_init(&ctx, 0); |
649 | ||
e4a5d54f | 650 | /* for pre-945g platforms use load detect */ |
51fd371b | 651 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
e95c8438 DV |
652 | if (intel_crt_detect_ddc(connector)) |
653 | status = connector_status_connected; | |
5bedeb2d | 654 | else if (INTEL_INFO(dev)->gen < 4) |
c8ecb2f1 ML |
655 | status = intel_crt_load_detect(crt, |
656 | to_intel_crtc(connector->state->crtc)->pipe); | |
5bedeb2d DV |
657 | else |
658 | status = connector_status_unknown; | |
49172fee | 659 | intel_release_load_detect_pipe(connector, &tmp, &ctx); |
e95c8438 DV |
660 | } else |
661 | status = connector_status_unknown; | |
e4a5d54f | 662 | |
208bf9fd VS |
663 | drm_modeset_drop_locks(&ctx); |
664 | drm_modeset_acquire_fini(&ctx); | |
665 | ||
c19a0df2 | 666 | out: |
671dedd2 | 667 | intel_display_power_put(dev_priv, power_domain); |
e4a5d54f | 668 | return status; |
79e53945 JB |
669 | } |
670 | ||
671 | static void intel_crt_destroy(struct drm_connector *connector) | |
672 | { | |
79e53945 JB |
673 | drm_connector_cleanup(connector); |
674 | kfree(connector); | |
675 | } | |
676 | ||
677 | static int intel_crt_get_modes(struct drm_connector *connector) | |
678 | { | |
8e4d36b9 | 679 | struct drm_device *dev = connector->dev; |
f899fc64 | 680 | struct drm_i915_private *dev_priv = dev->dev_private; |
671dedd2 ID |
681 | struct intel_crt *crt = intel_attached_crt(connector); |
682 | struct intel_encoder *intel_encoder = &crt->base; | |
683 | enum intel_display_power_domain power_domain; | |
890f3359 | 684 | int ret; |
3bd7d909 | 685 | struct i2c_adapter *i2c; |
8e4d36b9 | 686 | |
671dedd2 ID |
687 | power_domain = intel_display_port_power_domain(intel_encoder); |
688 | intel_display_power_get(dev_priv, power_domain); | |
689 | ||
41aa3448 | 690 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 691 | ret = intel_crt_ddc_get_modes(connector, i2c); |
8e4d36b9 | 692 | if (ret || !IS_G4X(dev)) |
671dedd2 | 693 | goto out; |
8e4d36b9 | 694 | |
8e4d36b9 | 695 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
988c7015 | 696 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
671dedd2 ID |
697 | ret = intel_crt_ddc_get_modes(connector, i2c); |
698 | ||
699 | out: | |
700 | intel_display_power_put(dev_priv, power_domain); | |
701 | ||
702 | return ret; | |
79e53945 JB |
703 | } |
704 | ||
705 | static int intel_crt_set_property(struct drm_connector *connector, | |
706 | struct drm_property *property, | |
707 | uint64_t value) | |
708 | { | |
79e53945 JB |
709 | return 0; |
710 | } | |
711 | ||
f3269058 CW |
712 | static void intel_crt_reset(struct drm_connector *connector) |
713 | { | |
714 | struct drm_device *dev = connector->dev; | |
2e938892 | 715 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3269058 CW |
716 | struct intel_crt *crt = intel_attached_crt(connector); |
717 | ||
10603caa | 718 | if (INTEL_INFO(dev)->gen >= 5) { |
2e938892 DV |
719 | u32 adpa; |
720 | ||
ca54b810 | 721 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
722 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
723 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
724 | I915_WRITE(crt->adpa_reg, adpa); |
725 | POSTING_READ(crt->adpa_reg); | |
2e938892 | 726 | |
0039a4b3 | 727 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
f3269058 | 728 | crt->force_hotplug_required = 1; |
2e938892 DV |
729 | } |
730 | ||
f3269058 CW |
731 | } |
732 | ||
79e53945 JB |
733 | /* |
734 | * Routines for controlling stuff on the analog port | |
735 | */ | |
736 | ||
79e53945 | 737 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
f3269058 | 738 | .reset = intel_crt_reset, |
4d688a2a | 739 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 JB |
740 | .detect = intel_crt_detect, |
741 | .fill_modes = drm_helper_probe_single_connector_modes, | |
742 | .destroy = intel_crt_destroy, | |
743 | .set_property = intel_crt_set_property, | |
c6f95f27 | 744 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 745 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
2545e4a6 | 746 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 JB |
747 | }; |
748 | ||
749 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
750 | .mode_valid = intel_crt_mode_valid, | |
751 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 752 | .best_encoder = intel_best_encoder, |
79e53945 JB |
753 | }; |
754 | ||
79e53945 | 755 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 756 | .destroy = intel_encoder_destroy, |
79e53945 JB |
757 | }; |
758 | ||
bbe1c274 | 759 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
8ca4013d | 760 | { |
bc0daf48 | 761 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
762 | return 1; |
763 | } | |
764 | ||
765 | static const struct dmi_system_id intel_no_crt[] = { | |
766 | { | |
767 | .callback = intel_no_crt_dmi_callback, | |
768 | .ident = "ACER ZGB", | |
769 | .matches = { | |
770 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
771 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
772 | }, | |
773 | }, | |
10b6ee4a GC |
774 | { |
775 | .callback = intel_no_crt_dmi_callback, | |
776 | .ident = "DELL XPS 8700", | |
777 | .matches = { | |
778 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
779 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), | |
780 | }, | |
781 | }, | |
8ca4013d DL |
782 | { } |
783 | }; | |
784 | ||
79e53945 JB |
785 | void intel_crt_init(struct drm_device *dev) |
786 | { | |
787 | struct drm_connector *connector; | |
c9a1c4cd | 788 | struct intel_crt *crt; |
454c1ca8 | 789 | struct intel_connector *intel_connector; |
db545019 | 790 | struct drm_i915_private *dev_priv = dev->dev_private; |
6c03a6bd VS |
791 | i915_reg_t adpa_reg; |
792 | u32 adpa; | |
79e53945 | 793 | |
8ca4013d DL |
794 | /* Skip machines without VGA that falsely report hotplug events */ |
795 | if (dmi_check_system(intel_no_crt)) | |
796 | return; | |
797 | ||
6c03a6bd VS |
798 | if (HAS_PCH_SPLIT(dev)) |
799 | adpa_reg = PCH_ADPA; | |
800 | else if (IS_VALLEYVIEW(dev)) | |
801 | adpa_reg = VLV_ADPA; | |
802 | else | |
803 | adpa_reg = ADPA; | |
804 | ||
805 | adpa = I915_READ(adpa_reg); | |
806 | if ((adpa & ADPA_DAC_ENABLE) == 0) { | |
807 | /* | |
808 | * On some machines (some IVB at least) CRT can be | |
809 | * fused off, but there's no known fuse bit to | |
810 | * indicate that. On these machine the ADPA register | |
811 | * works normally, except the DAC enable bit won't | |
812 | * take. So the only way to tell is attempt to enable | |
813 | * it and see what happens. | |
814 | */ | |
815 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | | |
816 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | |
817 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) | |
818 | return; | |
819 | I915_WRITE(adpa_reg, adpa); | |
820 | } | |
821 | ||
c9a1c4cd CW |
822 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
823 | if (!crt) | |
79e53945 JB |
824 | return; |
825 | ||
9bdbd0b9 | 826 | intel_connector = intel_connector_alloc(); |
454c1ca8 | 827 | if (!intel_connector) { |
c9a1c4cd | 828 | kfree(crt); |
454c1ca8 ZW |
829 | return; |
830 | } | |
831 | ||
832 | connector = &intel_connector->base; | |
637f44d2 | 833 | crt->connector = intel_connector; |
454c1ca8 | 834 | drm_connector_init(dev, &intel_connector->base, |
79e53945 JB |
835 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
836 | ||
c9a1c4cd | 837 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
13a3d91f | 838 | DRM_MODE_ENCODER_DAC, NULL); |
79e53945 | 839 | |
c9a1c4cd | 840 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 841 | |
c9a1c4cd | 842 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 843 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
d63fa0dc | 844 | if (IS_I830(dev)) |
59c859d6 ED |
845 | crt->base.crtc_mask = (1 << 0); |
846 | else | |
0826874a | 847 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 848 | |
dbb02575 DV |
849 | if (IS_GEN2(dev)) |
850 | connector->interlace_allowed = 0; | |
851 | else | |
852 | connector->interlace_allowed = 1; | |
79e53945 JB |
853 | connector->doublescan_allowed = 0; |
854 | ||
6c03a6bd | 855 | crt->adpa_reg = adpa_reg; |
540a8950 | 856 | |
5bfe2ac0 | 857 | crt->base.compute_config = intel_crt_compute_config; |
92966a37 | 858 | if (HAS_PCH_SPLIT(dev)) { |
1ea56e26 VS |
859 | crt->base.disable = pch_disable_crt; |
860 | crt->base.post_disable = pch_post_disable_crt; | |
861 | } else { | |
862 | crt->base.disable = intel_disable_crt; | |
863 | } | |
2124604b | 864 | crt->base.enable = intel_enable_crt; |
1d843f9d EE |
865 | if (I915_HAS_HOTPLUG(dev)) |
866 | crt->base.hpd_pin = HPD_CRT; | |
a2985791 VS |
867 | if (HAS_DDI(dev)) { |
868 | crt->base.get_config = hsw_crt_get_config; | |
4eda01b2 | 869 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
a2985791 VS |
870 | } else { |
871 | crt->base.get_config = intel_crt_get_config; | |
4eda01b2 | 872 | crt->base.get_hw_state = intel_crt_get_hw_state; |
a2985791 | 873 | } |
e403fc94 | 874 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 875 | intel_connector->unregister = intel_connector_unregister; |
df0323c4 | 876 | |
79e53945 JB |
877 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
878 | ||
34ea3d38 | 879 | drm_connector_register(connector); |
b01f2c3a | 880 | |
821450c6 EE |
881 | if (!I915_HAS_HOTPLUG(dev)) |
882 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
eb1f8e4f | 883 | |
e7dbb2f2 KP |
884 | /* |
885 | * Configure the automatic hotplug detection stuff | |
886 | */ | |
887 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 888 | |
68d18ad7 | 889 | /* |
3e68320e DL |
890 | * TODO: find a proper way to discover whether we need to set the the |
891 | * polarity and link reversal bits or not, instead of relying on the | |
892 | * BIOS. | |
68d18ad7 | 893 | */ |
3e68320e DL |
894 | if (HAS_PCH_LPT(dev)) { |
895 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | | |
896 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
897 | ||
eede3b53 | 898 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
3e68320e | 899 | } |
754970ee DV |
900 | |
901 | intel_crt_reset(connector); | |
79e53945 | 902 | } |