Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
79e53945 JB |
29 | #include "drmP.h" |
30 | #include "drm.h" | |
31 | #include "drm_crtc.h" | |
32 | #include "drm_crtc_helper.h" | |
33 | #include "intel_drv.h" | |
34 | #include "i915_drm.h" | |
35 | #include "i915_drv.h" | |
36 | ||
37 | static void intel_crt_dpms(struct drm_encoder *encoder, int mode) | |
38 | { | |
39 | struct drm_device *dev = encoder->dev; | |
40 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 41 | u32 temp, reg; |
79e53945 | 42 | |
bad720ff | 43 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
44 | reg = PCH_ADPA; |
45 | else | |
46 | reg = ADPA; | |
47 | ||
48 | temp = I915_READ(reg); | |
79e53945 | 49 | temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
febc7694 | 50 | temp &= ~ADPA_DAC_ENABLE; |
79e53945 JB |
51 | |
52 | switch(mode) { | |
53 | case DRM_MODE_DPMS_ON: | |
54 | temp |= ADPA_DAC_ENABLE; | |
55 | break; | |
56 | case DRM_MODE_DPMS_STANDBY: | |
57 | temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; | |
58 | break; | |
59 | case DRM_MODE_DPMS_SUSPEND: | |
60 | temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; | |
61 | break; | |
62 | case DRM_MODE_DPMS_OFF: | |
63 | temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; | |
64 | break; | |
65 | } | |
66 | ||
2c07245f | 67 | I915_WRITE(reg, temp); |
79e53945 JB |
68 | } |
69 | ||
70 | static int intel_crt_mode_valid(struct drm_connector *connector, | |
71 | struct drm_display_mode *mode) | |
72 | { | |
6bcdcd9e ZY |
73 | struct drm_device *dev = connector->dev; |
74 | ||
75 | int max_clock = 0; | |
79e53945 JB |
76 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
77 | return MODE_NO_DBLESCAN; | |
78 | ||
6bcdcd9e ZY |
79 | if (mode->clock < 25000) |
80 | return MODE_CLOCK_LOW; | |
81 | ||
82 | if (!IS_I9XX(dev)) | |
83 | max_clock = 350000; | |
84 | else | |
85 | max_clock = 400000; | |
86 | if (mode->clock > max_clock) | |
87 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
88 | |
89 | return MODE_OK; | |
90 | } | |
91 | ||
92 | static bool intel_crt_mode_fixup(struct drm_encoder *encoder, | |
93 | struct drm_display_mode *mode, | |
94 | struct drm_display_mode *adjusted_mode) | |
95 | { | |
96 | return true; | |
97 | } | |
98 | ||
99 | static void intel_crt_mode_set(struct drm_encoder *encoder, | |
100 | struct drm_display_mode *mode, | |
101 | struct drm_display_mode *adjusted_mode) | |
102 | { | |
103 | ||
104 | struct drm_device *dev = encoder->dev; | |
105 | struct drm_crtc *crtc = encoder->crtc; | |
106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
108 | int dpll_md_reg; | |
109 | u32 adpa, dpll_md; | |
2c07245f | 110 | u32 adpa_reg; |
79e53945 JB |
111 | |
112 | if (intel_crtc->pipe == 0) | |
113 | dpll_md_reg = DPLL_A_MD; | |
114 | else | |
115 | dpll_md_reg = DPLL_B_MD; | |
116 | ||
bad720ff | 117 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
118 | adpa_reg = PCH_ADPA; |
119 | else | |
120 | adpa_reg = ADPA; | |
121 | ||
79e53945 JB |
122 | /* |
123 | * Disable separate mode multiplier used when cloning SDVO to CRT | |
124 | * XXX this needs to be adjusted when we really are cloning | |
125 | */ | |
bad720ff | 126 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { |
79e53945 JB |
127 | dpll_md = I915_READ(dpll_md_reg); |
128 | I915_WRITE(dpll_md_reg, | |
129 | dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); | |
130 | } | |
131 | ||
132 | adpa = 0; | |
133 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
134 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
135 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
136 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
137 | ||
6bcdcd9e | 138 | if (intel_crtc->pipe == 0) { |
8db9d77b ZW |
139 | if (HAS_PCH_CPT(dev)) |
140 | adpa |= PORT_TRANS_A_SEL_CPT; | |
141 | else | |
142 | adpa |= ADPA_PIPE_A_SELECT; | |
bad720ff | 143 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f | 144 | I915_WRITE(BCLRPAT_A, 0); |
6bcdcd9e | 145 | } else { |
8db9d77b ZW |
146 | if (HAS_PCH_CPT(dev)) |
147 | adpa |= PORT_TRANS_B_SEL_CPT; | |
148 | else | |
149 | adpa |= ADPA_PIPE_B_SELECT; | |
bad720ff | 150 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f | 151 | I915_WRITE(BCLRPAT_B, 0); |
6bcdcd9e | 152 | } |
79e53945 | 153 | |
2c07245f ZW |
154 | I915_WRITE(adpa_reg, adpa); |
155 | } | |
156 | ||
f2b115e6 | 157 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
158 | { |
159 | struct drm_device *dev = connector->dev; | |
160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a6b901 | 161 | u32 adpa, temp; |
2c07245f ZW |
162 | bool ret; |
163 | ||
a4a6b901 | 164 | temp = adpa = I915_READ(PCH_ADPA); |
67941da2 | 165 | |
a4a6b901 ZW |
166 | if (HAS_PCH_CPT(dev)) { |
167 | /* Disable DAC before force detect */ | |
168 | I915_WRITE(PCH_ADPA, adpa & ~ADPA_DAC_ENABLE); | |
169 | (void)I915_READ(PCH_ADPA); | |
170 | } else { | |
171 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; | |
172 | /* disable HPD first */ | |
173 | I915_WRITE(PCH_ADPA, adpa); | |
174 | (void)I915_READ(PCH_ADPA); | |
175 | } | |
2c07245f ZW |
176 | |
177 | adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | | |
178 | ADPA_CRT_HOTPLUG_WARMUP_10MS | | |
179 | ADPA_CRT_HOTPLUG_SAMPLE_4S | | |
180 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */ | |
181 | ADPA_CRT_HOTPLUG_VOLREF_325MV | | |
182 | ADPA_CRT_HOTPLUG_ENABLE | | |
183 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER); | |
184 | ||
28c97730 | 185 | DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa); |
2c07245f ZW |
186 | I915_WRITE(PCH_ADPA, adpa); |
187 | ||
67941da2 ZW |
188 | while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0) |
189 | ; | |
2c07245f | 190 | |
a4a6b901 ZW |
191 | if (HAS_PCH_CPT(dev)) { |
192 | I915_WRITE(PCH_ADPA, temp); | |
193 | (void)I915_READ(PCH_ADPA); | |
194 | } | |
195 | ||
2c07245f ZW |
196 | /* Check the status to see if both blue and green are on now */ |
197 | adpa = I915_READ(PCH_ADPA); | |
67941da2 ZW |
198 | adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK; |
199 | if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) || | |
200 | (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO)) | |
2c07245f ZW |
201 | ret = true; |
202 | else | |
203 | ret = false; | |
204 | ||
2c07245f | 205 | return ret; |
79e53945 JB |
206 | } |
207 | ||
208 | /** | |
209 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
210 | * | |
211 | * Not for i915G/i915GM | |
212 | * | |
213 | * \return true if CRT is connected. | |
214 | * \return false if CRT is disconnected. | |
215 | */ | |
216 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
217 | { | |
218 | struct drm_device *dev = connector->dev; | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
771cb081 ZY |
220 | u32 hotplug_en; |
221 | int i, tries = 0; | |
2c07245f | 222 | |
bad720ff | 223 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 224 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 225 | |
771cb081 ZY |
226 | /* |
227 | * On 4 series desktop, CRT detect sequence need to be done twice | |
228 | * to get a reliable result. | |
229 | */ | |
79e53945 | 230 | |
771cb081 ZY |
231 | if (IS_G4X(dev) && !IS_GM45(dev)) |
232 | tries = 2; | |
233 | else | |
234 | tries = 1; | |
235 | hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
5ca58282 | 236 | hotplug_en &= CRT_FORCE_HOTPLUG_MASK; |
771cb081 ZY |
237 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
238 | ||
e92597cf | 239 | if (IS_G4X(dev)) |
771cb081 ZY |
240 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; |
241 | ||
242 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
243 | ||
244 | for (i = 0; i < tries ; i++) { | |
245 | unsigned long timeout; | |
246 | /* turn on the FORCE_DETECT */ | |
247 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
248 | timeout = jiffies + msecs_to_jiffies(1000); | |
249 | /* wait for FORCE_DETECT to go off */ | |
250 | do { | |
251 | if (!(I915_READ(PORT_HOTPLUG_EN) & | |
252 | CRT_HOTPLUG_FORCE_DETECT)) | |
253 | break; | |
254 | msleep(1); | |
255 | } while (time_after(timeout, jiffies)); | |
256 | } | |
79e53945 | 257 | |
8e9e0eea ZW |
258 | if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != |
259 | CRT_HOTPLUG_MONITOR_NONE) | |
79e53945 JB |
260 | return true; |
261 | ||
262 | return false; | |
263 | } | |
264 | ||
454c1ca8 | 265 | static bool intel_crt_detect_ddc(struct drm_encoder *encoder) |
79e53945 | 266 | { |
454c1ca8 | 267 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
79e53945 JB |
268 | |
269 | /* CRT should always be at 0, but check anyway */ | |
21d40d37 | 270 | if (intel_encoder->type != INTEL_OUTPUT_ANALOG) |
79e53945 JB |
271 | return false; |
272 | ||
21d40d37 | 273 | return intel_ddc_probe(intel_encoder); |
79e53945 JB |
274 | } |
275 | ||
e4a5d54f | 276 | static enum drm_connector_status |
21d40d37 | 277 | intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder) |
e4a5d54f | 278 | { |
21d40d37 | 279 | struct drm_encoder *encoder = &intel_encoder->enc; |
e4a5d54f ML |
280 | struct drm_device *dev = encoder->dev; |
281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
282 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
283 | uint32_t pipe = intel_crtc->pipe; | |
284 | uint32_t save_bclrpat; | |
285 | uint32_t save_vtotal; | |
286 | uint32_t vtotal, vactive; | |
287 | uint32_t vsample; | |
288 | uint32_t vblank, vblank_start, vblank_end; | |
289 | uint32_t dsl; | |
290 | uint32_t bclrpat_reg; | |
291 | uint32_t vtotal_reg; | |
292 | uint32_t vblank_reg; | |
293 | uint32_t vsync_reg; | |
294 | uint32_t pipeconf_reg; | |
295 | uint32_t pipe_dsl_reg; | |
296 | uint8_t st00; | |
297 | enum drm_connector_status status; | |
298 | ||
299 | if (pipe == 0) { | |
300 | bclrpat_reg = BCLRPAT_A; | |
301 | vtotal_reg = VTOTAL_A; | |
302 | vblank_reg = VBLANK_A; | |
303 | vsync_reg = VSYNC_A; | |
304 | pipeconf_reg = PIPEACONF; | |
305 | pipe_dsl_reg = PIPEADSL; | |
306 | } else { | |
307 | bclrpat_reg = BCLRPAT_B; | |
308 | vtotal_reg = VTOTAL_B; | |
309 | vblank_reg = VBLANK_B; | |
310 | vsync_reg = VSYNC_B; | |
311 | pipeconf_reg = PIPEBCONF; | |
312 | pipe_dsl_reg = PIPEBDSL; | |
313 | } | |
314 | ||
315 | save_bclrpat = I915_READ(bclrpat_reg); | |
316 | save_vtotal = I915_READ(vtotal_reg); | |
317 | vblank = I915_READ(vblank_reg); | |
318 | ||
319 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
320 | vactive = (save_vtotal & 0x7ff) + 1; | |
321 | ||
322 | vblank_start = (vblank & 0xfff) + 1; | |
323 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
324 | ||
325 | /* Set the border color to purple. */ | |
326 | I915_WRITE(bclrpat_reg, 0x500050); | |
327 | ||
328 | if (IS_I9XX(dev)) { | |
329 | uint32_t pipeconf = I915_READ(pipeconf_reg); | |
330 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
331 | /* Wait for next Vblank to substitue | |
332 | * border color for Color info */ | |
333 | intel_wait_for_vblank(dev); | |
334 | st00 = I915_READ8(VGA_MSR_WRITE); | |
335 | status = ((st00 & (1 << 4)) != 0) ? | |
336 | connector_status_connected : | |
337 | connector_status_disconnected; | |
338 | ||
339 | I915_WRITE(pipeconf_reg, pipeconf); | |
340 | } else { | |
341 | bool restore_vblank = false; | |
342 | int count, detect; | |
343 | ||
344 | /* | |
345 | * If there isn't any border, add some. | |
346 | * Yes, this will flicker | |
347 | */ | |
348 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
349 | uint32_t vsync = I915_READ(vsync_reg); | |
350 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
351 | ||
352 | vblank_start = vsync_start; | |
353 | I915_WRITE(vblank_reg, | |
354 | (vblank_start - 1) | | |
355 | ((vblank_end - 1) << 16)); | |
356 | restore_vblank = true; | |
357 | } | |
358 | /* sample in the vertical border, selecting the larger one */ | |
359 | if (vblank_start - vactive >= vtotal - vblank_end) | |
360 | vsample = (vblank_start + vactive) >> 1; | |
361 | else | |
362 | vsample = (vtotal + vblank_end) >> 1; | |
363 | ||
364 | /* | |
365 | * Wait for the border to be displayed | |
366 | */ | |
367 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
368 | ; | |
369 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
370 | ; | |
371 | /* | |
372 | * Watch ST00 for an entire scanline | |
373 | */ | |
374 | detect = 0; | |
375 | count = 0; | |
376 | do { | |
377 | count++; | |
378 | /* Read the ST00 VGA status register */ | |
379 | st00 = I915_READ8(VGA_MSR_WRITE); | |
380 | if (st00 & (1 << 4)) | |
381 | detect++; | |
382 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
383 | ||
384 | /* restore vblank if necessary */ | |
385 | if (restore_vblank) | |
386 | I915_WRITE(vblank_reg, vblank); | |
387 | /* | |
388 | * If more than 3/4 of the scanline detected a monitor, | |
389 | * then it is assumed to be present. This works even on i830, | |
390 | * where there isn't any way to force the border color across | |
391 | * the screen | |
392 | */ | |
393 | status = detect * 4 > count * 3 ? | |
394 | connector_status_connected : | |
395 | connector_status_disconnected; | |
396 | } | |
397 | ||
398 | /* Restore previous settings */ | |
399 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
400 | ||
401 | return status; | |
402 | } | |
403 | ||
79e53945 JB |
404 | static enum drm_connector_status intel_crt_detect(struct drm_connector *connector) |
405 | { | |
406 | struct drm_device *dev = connector->dev; | |
454c1ca8 ZW |
407 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
408 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
e4a5d54f ML |
409 | struct drm_crtc *crtc; |
410 | int dpms_mode; | |
411 | enum drm_connector_status status; | |
79e53945 JB |
412 | |
413 | if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) { | |
414 | if (intel_crt_detect_hotplug(connector)) | |
415 | return connector_status_connected; | |
416 | else | |
417 | return connector_status_disconnected; | |
418 | } | |
419 | ||
454c1ca8 | 420 | if (intel_crt_detect_ddc(encoder)) |
79e53945 JB |
421 | return connector_status_connected; |
422 | ||
e4a5d54f ML |
423 | /* for pre-945g platforms use load detect */ |
424 | if (encoder->crtc && encoder->crtc->enabled) { | |
21d40d37 | 425 | status = intel_crt_load_detect(encoder->crtc, intel_encoder); |
e4a5d54f | 426 | } else { |
c1c43977 | 427 | crtc = intel_get_load_detect_pipe(intel_encoder, connector, |
e4a5d54f ML |
428 | NULL, &dpms_mode); |
429 | if (crtc) { | |
21d40d37 | 430 | status = intel_crt_load_detect(crtc, intel_encoder); |
c1c43977 ZW |
431 | intel_release_load_detect_pipe(intel_encoder, |
432 | connector, dpms_mode); | |
e4a5d54f ML |
433 | } else |
434 | status = connector_status_unknown; | |
435 | } | |
436 | ||
437 | return status; | |
79e53945 JB |
438 | } |
439 | ||
440 | static void intel_crt_destroy(struct drm_connector *connector) | |
441 | { | |
79e53945 JB |
442 | drm_sysfs_connector_remove(connector); |
443 | drm_connector_cleanup(connector); | |
444 | kfree(connector); | |
445 | } | |
446 | ||
447 | static int intel_crt_get_modes(struct drm_connector *connector) | |
448 | { | |
8e4d36b9 | 449 | int ret; |
454c1ca8 ZW |
450 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
451 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
335af9a2 | 452 | struct i2c_adapter *ddc_bus; |
8e4d36b9 | 453 | struct drm_device *dev = connector->dev; |
454 | ||
455 | ||
335af9a2 | 456 | ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); |
8e4d36b9 | 457 | if (ret || !IS_G4X(dev)) |
458 | goto end; | |
459 | ||
8e4d36b9 | 460 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
335af9a2 | 461 | ddc_bus = intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D"); |
8e4d36b9 | 462 | |
335af9a2 | 463 | if (!ddc_bus) { |
8e4d36b9 | 464 | dev_printk(KERN_ERR, &connector->dev->pdev->dev, |
465 | "DDC bus registration failed for CRTDDC_D.\n"); | |
466 | goto end; | |
467 | } | |
468 | /* Try to get modes by GPIOD port */ | |
335af9a2 ZW |
469 | ret = intel_ddc_get_modes(connector, ddc_bus); |
470 | intel_i2c_destroy(ddc_bus); | |
8e4d36b9 | 471 | |
472 | end: | |
473 | return ret; | |
474 | ||
79e53945 JB |
475 | } |
476 | ||
477 | static int intel_crt_set_property(struct drm_connector *connector, | |
478 | struct drm_property *property, | |
479 | uint64_t value) | |
480 | { | |
79e53945 JB |
481 | return 0; |
482 | } | |
483 | ||
484 | /* | |
485 | * Routines for controlling stuff on the analog port | |
486 | */ | |
487 | ||
488 | static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = { | |
489 | .dpms = intel_crt_dpms, | |
490 | .mode_fixup = intel_crt_mode_fixup, | |
491 | .prepare = intel_encoder_prepare, | |
492 | .commit = intel_encoder_commit, | |
493 | .mode_set = intel_crt_mode_set, | |
494 | }; | |
495 | ||
496 | static const struct drm_connector_funcs intel_crt_connector_funcs = { | |
c9fb15f6 | 497 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
498 | .detect = intel_crt_detect, |
499 | .fill_modes = drm_helper_probe_single_connector_modes, | |
500 | .destroy = intel_crt_destroy, | |
501 | .set_property = intel_crt_set_property, | |
502 | }; | |
503 | ||
504 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
505 | .mode_valid = intel_crt_mode_valid, | |
506 | .get_modes = intel_crt_get_modes, | |
454c1ca8 | 507 | .best_encoder = intel_attached_encoder, |
79e53945 JB |
508 | }; |
509 | ||
b358d0a6 | 510 | static void intel_crt_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 511 | { |
454c1ca8 ZW |
512 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
513 | ||
514 | intel_i2c_destroy(intel_encoder->ddc_bus); | |
79e53945 | 515 | drm_encoder_cleanup(encoder); |
454c1ca8 | 516 | kfree(intel_encoder); |
79e53945 JB |
517 | } |
518 | ||
519 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { | |
520 | .destroy = intel_crt_enc_destroy, | |
521 | }; | |
522 | ||
523 | void intel_crt_init(struct drm_device *dev) | |
524 | { | |
525 | struct drm_connector *connector; | |
21d40d37 | 526 | struct intel_encoder *intel_encoder; |
454c1ca8 | 527 | struct intel_connector *intel_connector; |
db545019 | 528 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 529 | u32 i2c_reg; |
79e53945 | 530 | |
21d40d37 EA |
531 | intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL); |
532 | if (!intel_encoder) | |
79e53945 JB |
533 | return; |
534 | ||
454c1ca8 ZW |
535 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
536 | if (!intel_connector) { | |
537 | kfree(intel_encoder); | |
538 | return; | |
539 | } | |
540 | ||
541 | connector = &intel_connector->base; | |
542 | drm_connector_init(dev, &intel_connector->base, | |
79e53945 JB |
543 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
544 | ||
21d40d37 | 545 | drm_encoder_init(dev, &intel_encoder->enc, &intel_crt_enc_funcs, |
79e53945 JB |
546 | DRM_MODE_ENCODER_DAC); |
547 | ||
454c1ca8 | 548 | drm_mode_connector_attach_encoder(&intel_connector->base, |
21d40d37 | 549 | &intel_encoder->enc); |
79e53945 JB |
550 | |
551 | /* Set up the DDC bus. */ | |
bad720ff | 552 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 553 | i2c_reg = PCH_GPIOA; |
db545019 | 554 | else { |
2c07245f | 555 | i2c_reg = GPIOA; |
db545019 | 556 | /* Use VBT information for CRT DDC if available */ |
29874f44 | 557 | if (dev_priv->crt_ddc_bus != 0) |
db545019 DMEA |
558 | i2c_reg = dev_priv->crt_ddc_bus; |
559 | } | |
21d40d37 EA |
560 | intel_encoder->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); |
561 | if (!intel_encoder->ddc_bus) { | |
79e53945 JB |
562 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " |
563 | "failed.\n"); | |
564 | return; | |
565 | } | |
566 | ||
21d40d37 EA |
567 | intel_encoder->type = INTEL_OUTPUT_ANALOG; |
568 | intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | | |
f8aed700 ML |
569 | (1 << INTEL_ANALOG_CLONE_BIT) | |
570 | (1 << INTEL_SDVO_LVDS_CLONE_BIT); | |
21d40d37 | 571 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
79e53945 JB |
572 | connector->interlace_allowed = 0; |
573 | connector->doublescan_allowed = 0; | |
574 | ||
21d40d37 | 575 | drm_encoder_helper_add(&intel_encoder->enc, &intel_crt_helper_funcs); |
79e53945 JB |
576 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
577 | ||
578 | drm_sysfs_connector_add(connector); | |
b01f2c3a JB |
579 | |
580 | dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS; | |
79e53945 | 581 | } |