Commit | Line | Data |
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b46a33e2 | 1 | /* |
058a9b43 | 2 | * SPDX-License-Identifier: MIT |
b46a33e2 | 3 | * |
058a9b43 | 4 | * Copyright © 2017-2018 Intel Corporation |
b46a33e2 | 5 | */ |
058a9b43 | 6 | |
b46a33e2 TU |
7 | #ifndef __I915_PMU_H__ |
8 | #define __I915_PMU_H__ | |
9 | ||
058a9b43 MW |
10 | #include <linux/hrtimer.h> |
11 | #include <linux/perf_event.h> | |
12 | #include <linux/spinlock_types.h> | |
83d2bdb6 | 13 | #include <uapi/drm/i915_drm.h> |
058a9b43 MW |
14 | |
15 | struct drm_i915_private; | |
da5d5167 | 16 | struct intel_gt; |
058a9b43 | 17 | |
7bc30374 | 18 | /* |
348fb0cb TU |
19 | * Non-engine events that we need to track enabled-disabled transition and |
20 | * current state. | |
21 | */ | |
22 | enum i915_pmu_tracked_events { | |
23 | __I915_PMU_ACTUAL_FREQUENCY_ENABLED = 0, | |
24 | __I915_PMU_REQUESTED_FREQUENCY_ENABLED, | |
25 | __I915_PMU_RC6_RESIDENCY_ENABLED, | |
26 | __I915_PMU_TRACKED_EVENT_COUNT, /* count marker */ | |
27 | }; | |
28 | ||
7bc30374 | 29 | /* |
348fb0cb TU |
30 | * Slots used from the sampling timer (non-engine events) with some extras for |
31 | * convenience. | |
32 | */ | |
b46a33e2 TU |
33 | enum { |
34 | __I915_SAMPLE_FREQ_ACT = 0, | |
35 | __I915_SAMPLE_FREQ_REQ, | |
1fe699e3 | 36 | __I915_SAMPLE_RC6, |
df6a4205 | 37 | __I915_SAMPLE_RC6_LAST_REPORTED, |
b46a33e2 TU |
38 | __I915_NUM_PMU_SAMPLERS |
39 | }; | |
40 | ||
419491ea | 41 | #define I915_PMU_MAX_GT 2 |
bc4be0a3 | 42 | |
7bc30374 | 43 | /* |
b46a33e2 TU |
44 | * How many different events we track in the global PMU mask. |
45 | * | |
46 | * It is also used to know to needed number of event reference counters. | |
47 | */ | |
48 | #define I915_PMU_MASK_BITS \ | |
bc4be0a3 | 49 | (I915_ENGINE_SAMPLE_COUNT + \ |
419491ea | 50 | I915_PMU_MAX_GT * __I915_PMU_TRACKED_EVENT_COUNT) |
b46a33e2 | 51 | |
d8b879bb TU |
52 | #define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1) |
53 | ||
b46a33e2 TU |
54 | struct i915_pmu_sample { |
55 | u64 cur; | |
b46a33e2 TU |
56 | }; |
57 | ||
58 | struct i915_pmu { | |
59 | /** | |
f5a179d4 | 60 | * @cpuhp: Struct used for CPU hotplug handling. |
b46a33e2 | 61 | */ |
f5a179d4 MW |
62 | struct { |
63 | struct hlist_node node; | |
537f9c84 | 64 | unsigned int cpu; |
f5a179d4 | 65 | } cpuhp; |
b46a33e2 TU |
66 | /** |
67 | * @base: PMU base. | |
68 | */ | |
69 | struct pmu base; | |
b00bccb3 TU |
70 | /** |
71 | * @closed: i915 is unregistering. | |
72 | */ | |
73 | bool closed; | |
05488673 TU |
74 | /** |
75 | * @name: Name as registered with perf core. | |
76 | */ | |
77 | const char *name; | |
b46a33e2 TU |
78 | /** |
79 | * @lock: Lock protecting enable mask and ref count handling. | |
80 | */ | |
81 | spinlock_t lock; | |
b319cc59 TU |
82 | /** |
83 | * @unparked: GT unparked mask. | |
84 | */ | |
85 | unsigned int unparked; | |
b46a33e2 TU |
86 | /** |
87 | * @timer: Timer for internal i915 PMU sampling. | |
88 | */ | |
89 | struct hrtimer timer; | |
90 | /** | |
348fb0cb TU |
91 | * @enable: Bitmask of specific enabled events. |
92 | * | |
93 | * For some events we need to track their state and do some internal | |
94 | * house keeping. | |
b46a33e2 | 95 | * |
348fb0cb TU |
96 | * Each engine event sampler type and event listed in enum |
97 | * i915_pmu_tracked_events gets a bit in this field. | |
b46a33e2 | 98 | * |
348fb0cb | 99 | * Low bits are engine samplers and other events continue from there. |
b46a33e2 | 100 | */ |
348fb0cb | 101 | u32 enable; |
9f473ecf TU |
102 | |
103 | /** | |
104 | * @timer_last: | |
105 | * | |
106 | * Timestmap of the previous timer invocation. | |
107 | */ | |
108 | ktime_t timer_last; | |
109 | ||
b46a33e2 TU |
110 | /** |
111 | * @enable_count: Reference counts for the enabled events. | |
112 | * | |
113 | * Array indices are mapped in the same way as bits in the @enable field | |
114 | * and they are used to control sampling on/off when multiple clients | |
115 | * are using the PMU API. | |
116 | */ | |
117 | unsigned int enable_count[I915_PMU_MASK_BITS]; | |
feff0dc6 TU |
118 | /** |
119 | * @timer_enabled: Should the internal sampling timer be running. | |
120 | */ | |
121 | bool timer_enabled; | |
b46a33e2 TU |
122 | /** |
123 | * @sample: Current and previous (raw) counters for sampling events. | |
124 | * | |
125 | * These counters are updated from the i915 PMU sampling timer. | |
126 | * | |
127 | * Only global counters are held here, while the per-engine ones are in | |
128 | * struct intel_engine_cs. | |
129 | */ | |
419491ea | 130 | struct i915_pmu_sample sample[I915_PMU_MAX_GT][__I915_NUM_PMU_SAMPLERS]; |
1fe699e3 | 131 | /** |
16ffe73c | 132 | * @sleep_last: Last time GT parked for RC6 estimation. |
1fe699e3 | 133 | */ |
419491ea | 134 | ktime_t sleep_last[I915_PMU_MAX_GT]; |
9c6508b9 TG |
135 | /** |
136 | * @irq_count: Number of interrupts | |
137 | * | |
138 | * Intentionally unsigned long to avoid atomics or heuristics on 32bit. | |
139 | * 4e9 interrupts are a lot and postprocessing can really deal with an | |
140 | * occasional wraparound easily. It's 32bit after all. | |
141 | */ | |
142 | unsigned long irq_count; | |
46129dc1 MW |
143 | /** |
144 | * @events_attr_group: Device events attribute group. | |
145 | */ | |
146 | struct attribute_group events_attr_group; | |
109ec558 TU |
147 | /** |
148 | * @i915_attr: Memory block holding device attributes. | |
149 | */ | |
150 | void *i915_attr; | |
151 | /** | |
152 | * @pmu_attr: Memory block holding device attributes. | |
153 | */ | |
154 | void *pmu_attr; | |
b46a33e2 TU |
155 | }; |
156 | ||
157 | #ifdef CONFIG_PERF_EVENTS | |
a04ea6ae | 158 | int i915_pmu_init(void); |
537f9c84 | 159 | void i915_pmu_exit(void); |
b46a33e2 TU |
160 | void i915_pmu_register(struct drm_i915_private *i915); |
161 | void i915_pmu_unregister(struct drm_i915_private *i915); | |
da5d5167 TU |
162 | void i915_pmu_gt_parked(struct intel_gt *gt); |
163 | void i915_pmu_gt_unparked(struct intel_gt *gt); | |
b46a33e2 | 164 | #else |
a04ea6ae | 165 | static inline int i915_pmu_init(void) { return 0; } |
537f9c84 | 166 | static inline void i915_pmu_exit(void) {} |
b46a33e2 TU |
167 | static inline void i915_pmu_register(struct drm_i915_private *i915) {} |
168 | static inline void i915_pmu_unregister(struct drm_i915_private *i915) {} | |
da5d5167 TU |
169 | static inline void i915_pmu_gt_parked(struct intel_gt *gt) {} |
170 | static inline void i915_pmu_gt_unparked(struct intel_gt *gt) {} | |
b46a33e2 TU |
171 | #endif |
172 | ||
173 | #endif |