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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
CommitLineData
84734a04
MK		 1/*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30#include <generated/utsrelease.h>
31#include "i915_drv.h"
32
84734a04
MK		 33static const char *ring_str(int ring)
34{
35 switch (ring) {
36 case RCS: return "render";
37 case VCS: return "bsd";
38 case BCS: return "blt";
39 case VECS: return "vebox";
845f74a7 40 case VCS2: return "bsd2";
84734a04
MK		 41 default: return "";
42 }
43}
44
45static const char *pin_flag(int pinned)
46{
47 if (pinned > 0)
48 return " P";
49 else if (pinned < 0)
50 return " p";
51 else
52 return "";
53}
54
55static const char *tiling_flag(int tiling)
56{
57 switch (tiling) {
58 default:
59 case I915_TILING_NONE: return "";
60 case I915_TILING_X: return " X";
61 case I915_TILING_Y: return " Y";
62 }
63}
64
65static const char *dirty_flag(int dirty)
66{
67 return dirty ? " dirty" : "";
68}
69
70static const char *purgeable_flag(int purgeable)
71{
72 return purgeable ? " purgeable" : "";
73}
74
75static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
76{
77
78 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
79 e->err = -ENOSPC;
80 return false;
81 }
82
83 if (e->bytes == e->size - 1 || e->err)
84 return false;
85
86 return true;
87}
88
89static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
90 unsigned len)
91{
92 if (e->pos + len <= e->start) {
93 e->pos += len;
94 return false;
95 }
96
97 /* First vsnprintf needs to fit in its entirety for memmove */
98 if (len >= e->size) {
99 e->err = -EIO;
100 return false;
101 }
102
103 return true;
104}
105
106static void __i915_error_advance(struct drm_i915_error_state_buf *e,
107 unsigned len)
108{
109 /* If this is first printf in this window, adjust it so that
110 * start position matches start of the buffer
111 */
112
113 if (e->pos < e->start) {
114 const size_t off = e->start - e->pos;
115
116 /* Should not happen but be paranoid */
117 if (off > len || e->bytes) {
118 e->err = -EIO;
119 return;
120 }
121
122 memmove(e->buf, e->buf + off, len - off);
123 e->bytes = len - off;
124 e->pos = e->start;
125 return;
126 }
127
128 e->bytes += len;
129 e->pos += len;
130}
131
132static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
133 const char *f, va_list args)
134{
135 unsigned len;
136
137 if (!__i915_error_ok(e))
138 return;
139
140 /* Seek the first printf which is hits start position */
141 if (e->pos < e->start) {
e29bb4eb
CW		 142 va_list tmp;
143
144 va_copy(tmp, args);
1d2cb9a5
MK		 145 len = vsnprintf(NULL, 0, f, tmp);
146 va_end(tmp);
147
148 if (!__i915_error_seek(e, len))
84734a04
MK		 149 return;
150 }
151
152 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
153 if (len >= e->size - e->bytes)
154 len = e->size - e->bytes - 1;
155
156 __i915_error_advance(e, len);
157}
158
159static void i915_error_puts(struct drm_i915_error_state_buf *e,
160 const char *str)
161{
162 unsigned len;
163
164 if (!__i915_error_ok(e))
165 return;
166
167 len = strlen(str);
168
169 /* Seek the first printf which is hits start position */
170 if (e->pos < e->start) {
171 if (!__i915_error_seek(e, len))
172 return;
173 }
174
175 if (len >= e->size - e->bytes)
176 len = e->size - e->bytes - 1;
177 memcpy(e->buf + e->bytes, str, len);
178
179 __i915_error_advance(e, len);
180}
181
182#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
183#define err_puts(e, s) i915_error_puts(e, s)
184
185static void print_error_buffers(struct drm_i915_error_state_buf *m,
186 const char *name,
187 struct drm_i915_error_buffer *err,
188 int count)
189{
b4716185
CW		 190 int i;
191
3a448734 192 err_printf(m, " %s [%d]:\n", name, count);
84734a04
MK		 193
194 while (count--) {
e1f12325
MT		 195 err_printf(m, " %08x_%08x %8u %02x %02x [ ",
196 upper_32_bits(err->gtt_offset),
197 lower_32_bits(err->gtt_offset),
84734a04
MK		 198 err->size,
199 err->read_domains,
b4716185
CW		 200 err->write_domain);
201 for (i = 0; i < I915_NUM_RINGS; i++)
202 err_printf(m, "%02x ", err->rseqno[i]);
203
204 err_printf(m, "] %02x", err->wseqno);
84734a04
MK		 205 err_puts(m, pin_flag(err->pinned));
206 err_puts(m, tiling_flag(err->tiling));
207 err_puts(m, dirty_flag(err->dirty));
208 err_puts(m, purgeable_flag(err->purgeable));
5cc9ed4b 209 err_puts(m, err->userptr ? " userptr" : "");
84734a04
MK		 210 err_puts(m, err->ring != -1 ? " " : "");
211 err_puts(m, ring_str(err->ring));
0a4cd7c8 212 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
84734a04
MK		 213
214 if (err->name)
215 err_printf(m, " (name: %d)", err->name);
216 if (err->fence_reg != I915_FENCE_REG_NONE)
217 err_printf(m, " (fence: %d)", err->fence_reg);
218
219 err_puts(m, "\n");
220 err++;
221 }
222}
223
da661464
MK		 224static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
225{
226 switch (a) {
227 case HANGCHECK_IDLE:
228 return "idle";
229 case HANGCHECK_WAIT:
230 return "wait";
231 case HANGCHECK_ACTIVE:
232 return "active";
f260fe7b
MK		 233 case HANGCHECK_ACTIVE_LOOP:
234 return "active (loop)";
da661464
MK		 235 case HANGCHECK_KICK:
236 return "kick";
237 case HANGCHECK_HUNG:
238 return "hung";
239 }
240
241 return "unknown";
242}
243
84734a04
MK		 244static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
245 struct drm_device *dev,
77c1aa84
DV		 246 struct drm_i915_error_state *error,
247 int ring_idx)
84734a04 248{
77c1aa84
DV		 249 struct drm_i915_error_ring *ring = &error->ring[ring_idx];
250
362b8af7 251 if (!ring->valid)
372fbb8e
CW		 252 return;
253
77c1aa84 254 err_printf(m, "%s command stream:\n", ring_str(ring_idx));
94f8cf10
CW		 255 err_printf(m, " START: 0x%08x\n", ring->start);
256 err_printf(m, " HEAD: 0x%08x\n", ring->head);
257 err_printf(m, " TAIL: 0x%08x\n", ring->tail);
258 err_printf(m, " CTL: 0x%08x\n", ring->ctl);
259 err_printf(m, " HWS: 0x%08x\n", ring->hws);
e3243d16 260 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
362b8af7
BW		 261 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
262 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
263 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
3dda20a9 264 if (INTEL_INFO(dev)->gen >= 4) {
e3243d16 265 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
362b8af7
BW		 266 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
267 err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
3dda20a9 268 }
362b8af7 269 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
13ffadd1
BW		 270 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
271 lower_32_bits(ring->faddr));
84734a04 272 if (INTEL_INFO(dev)->gen >= 6) {
362b8af7
BW		 273 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
274 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
84734a04 275 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 276 ring->semaphore_mboxes[0],
277 ring->semaphore_seqno[0]);
84734a04 278 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 279 ring->semaphore_mboxes[1],
280 ring->semaphore_seqno[1]);
4e5aabfd
BW		 281 if (HAS_VEBOX(dev)) {
282 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
362b8af7
BW		 283 ring->semaphore_mboxes[2],
284 ring->semaphore_seqno[2]);
4e5aabfd 285 }
84734a04 286 }
6c7a01ec
BW		 287 if (USES_PPGTT(dev)) {
288 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
289
290 if (INTEL_INFO(dev)->gen >= 8) {
291 int i;
292 for (i = 0; i < 4; i++)
293 err_printf(m, " PDP%d: 0x%016llx\n",
294 i, ring->vm_info.pdp[i]);
295 } else {
296 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
297 ring->vm_info.pp_dir_base);
298 }
299 }
362b8af7
BW		 300 err_printf(m, " seqno: 0x%08x\n", ring->seqno);
301 err_printf(m, " waiting: %s\n", yesno(ring->waiting));
302 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
303 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
da661464 304 err_printf(m, " hangcheck: %s [%d]\n",
362b8af7
BW		 305 hangcheck_action_to_str(ring->hangcheck_action),
306 ring->hangcheck_score);
84734a04
MK		 307}
308
309void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
310{
311 va_list args;
312
313 va_start(args, f);
314 i915_error_vprintf(e, f, args);
315 va_end(args);
316}
317
ab0e7ff9
CW		 318static void print_error_obj(struct drm_i915_error_state_buf *m,
319 struct drm_i915_error_object *obj)
320{
321 int page, offset, elt;
322
323 for (page = offset = 0; page < obj->page_count; page++) {
324 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
325 err_printf(m, "%08x : %08x\n", offset,
326 obj->pages[page][elt]);
327 offset += 4;
328 }
329 }
330}
331
84734a04
MK		 332int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
333 const struct i915_error_state_file_priv *error_priv)
334{
335 struct drm_device *dev = error_priv->dev;
50227e1c 336 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04 337 struct drm_i915_error_state *error = error_priv->error;
0ca36d78 338 struct drm_i915_error_object *obj;
ab0e7ff9
CW		 339 int i, j, offset, elt;
340 int max_hangcheck_score;
84734a04
MK		 341
342 if (!error) {
343 err_printf(m, "no error state collected\n");
344 goto out;
345 }
346
cb383002 347 err_printf(m, "%s\n", error->error_msg);
84734a04
MK		 348 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
349 error->time.tv_usec);
350 err_printf(m, "Kernel: " UTS_RELEASE "\n");
ab0e7ff9
CW		 351 max_hangcheck_score = 0;
352 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
353 if (error->ring[i].hangcheck_score > max_hangcheck_score)
354 max_hangcheck_score = error->ring[i].hangcheck_score;
355 }
356 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
357 if (error->ring[i].hangcheck_score == max_hangcheck_score &&
358 error->ring[i].pid != -1) {
359 err_printf(m, "Active process (on ring %s): %s [%d]\n",
360 ring_str(i),
361 error->ring[i].comm,
362 error->ring[i].pid);
363 }
364 }
48b031e3 365 err_printf(m, "Reset count: %u\n", error->reset_count);
62d5d69b 366 err_printf(m, "Suspend count: %u\n", error->suspend_count);
ffbab09b 367 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
06e6ff8f
AS		 368 err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
369 err_printf(m, "PCI Subsystem: %04x:%04x\n",
370 dev->pdev->subsystem_vendor,
371 dev->pdev->subsystem_device);
eb5be9d0 372 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
0ac7655c
MK		 373
374 if (HAS_CSR(dev)) {
375 struct intel_csr *csr = &dev_priv->csr;
376
377 err_printf(m, "DMC loaded: %s\n",
378 yesno(csr->dmc_payload != NULL));
379 err_printf(m, "DMC fw version: %d.%d\n",
380 CSR_VERSION_MAJOR(csr->version),
381 CSR_VERSION_MINOR(csr->version));
382 }
383
84734a04
MK		 384 err_printf(m, "EIR: 0x%08x\n", error->eir);
385 err_printf(m, "IER: 0x%08x\n", error->ier);
885ea5a8
RV		 386 if (INTEL_INFO(dev)->gen >= 8) {
387 for (i = 0; i < 4; i++)
388 err_printf(m, "GTIER gt %d: 0x%08x\n", i,
389 error->gtier[i]);
390 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
391 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
84734a04
MK		 392 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
393 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
394 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
395 err_printf(m, "CCID: 0x%08x\n", error->ccid);
094f9a54 396 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
84734a04
MK		 397
398 for (i = 0; i < dev_priv->num_fence_regs; i++)
399 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
400
401 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
402 err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
403 error->extra_instdone[i]);
404
405 if (INTEL_INFO(dev)->gen >= 6) {
406 err_printf(m, "ERROR: 0x%08x\n", error->error);
6c826f34
MK		 407
408 if (INTEL_INFO(dev)->gen >= 8)
409 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
410 error->fault_data1, error->fault_data0);
411
84734a04
MK		 412 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
413 }
414
415 if (INTEL_INFO(dev)->gen == 7)
416 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
417
77c1aa84
DV		 418 for (i = 0; i < ARRAY_SIZE(error->ring); i++)
419 i915_ring_error_state(m, dev, error, i);
84734a04 420
3a448734
CW		 421 for (i = 0; i < error->vm_count; i++) {
422 err_printf(m, "vm[%d]\n", i);
423
84734a04 424 print_error_buffers(m, "Active",
3a448734
CW		 425 error->active_bo[i],
426 error->active_bo_count[i]);
84734a04 427
84734a04 428 print_error_buffers(m, "Pinned",
3a448734
CW		 429 error->pinned_bo[i],
430 error->pinned_bo_count[i]);
431 }
84734a04
MK		 432
433 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
ab0e7ff9
CW		 434 obj = error->ring[i].batchbuffer;
435 if (obj) {
436 err_puts(m, dev_priv->ring[i].name);
437 if (error->ring[i].pid != -1)
438 err_printf(m, " (submitted by %s [%d])",
439 error->ring[i].comm,
440 error->ring[i].pid);
e1f12325
MT		 441 err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
442 upper_32_bits(obj->gtt_offset),
443 lower_32_bits(obj->gtt_offset));
ab0e7ff9
CW		 444 print_error_obj(m, obj);
445 }
446
447 obj = error->ring[i].wa_batchbuffer;
448 if (obj) {
449 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
e1f12325
MT		 450 dev_priv->ring[i].name,
451 lower_32_bits(obj->gtt_offset));
ab0e7ff9 452 print_error_obj(m, obj);
84734a04
MK		 453 }
454
455 if (error->ring[i].num_requests) {
456 err_printf(m, "%s --- %d requests\n",
457 dev_priv->ring[i].name,
458 error->ring[i].num_requests);
459 for (j = 0; j < error->ring[i].num_requests; j++) {
460 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
461 error->ring[i].requests[j].seqno,
462 error->ring[i].requests[j].jiffies,
463 error->ring[i].requests[j].tail);
464 }
465 }
466
467 if ((obj = error->ring[i].ringbuffer)) {
468 err_printf(m, "%s --- ringbuffer = 0x%08x\n",
469 dev_priv->ring[i].name,
e1f12325 470 lower_32_bits(obj->gtt_offset));
ab0e7ff9 471 print_error_obj(m, obj);
84734a04
MK		 472 }
473
362b8af7 474 if ((obj = error->ring[i].hws_page)) {
3a5a0393
JB		 475 u64 hws_offset = obj->gtt_offset;
476 u32 *hws_page = &obj->pages[0][0];
477
478 if (i915.enable_execlists) {
479 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
480 hws_page = &obj->pages[LRC_PPHWSP_PN][0];
481 }
d1675198 482 err_printf(m, "%s --- HW Status = 0x%08llx\n",
3a5a0393 483 dev_priv->ring[i].name, hws_offset);
f3ce3821
CW		 484 offset = 0;
485 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
486 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
487 offset,
3a5a0393
JB		 488 hws_page[elt],
489 hws_page[elt+1],
490 hws_page[elt+2],
491 hws_page[elt+3]);
f3ce3821
CW		 492 offset += 16;
493 }
494 }
495
372fbb8e 496 if ((obj = error->ring[i].ctx)) {
84734a04
MK		 497 err_printf(m, "%s --- HW Context = 0x%08x\n",
498 dev_priv->ring[i].name,
e1f12325 499 lower_32_bits(obj->gtt_offset));
17d36749 500 print_error_obj(m, obj);
84734a04
MK		 501 }
502 }
503
0ca36d78 504 if ((obj = error->semaphore_obj)) {
e1f12325
MT		 505 err_printf(m, "Semaphore page = 0x%08x\n",
506 lower_32_bits(obj->gtt_offset));
0ca36d78
BW		 507 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
508 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
509 elt * 4,
510 obj->pages[0][elt],
511 obj->pages[0][elt+1],
512 obj->pages[0][elt+2],
513 obj->pages[0][elt+3]);
514 }
515 }
516
84734a04
MK		 517 if (error->overlay)
518 intel_overlay_print_error_state(m, error->overlay);
519
520 if (error->display)
521 intel_display_print_error_state(m, dev, error->display);
522
523out:
524 if (m->bytes == 0 && m->err)
525 return m->err;
526
527 return 0;
528}
529
530int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
0a4cd7c8 531 struct drm_i915_private *i915,
84734a04
MK		 532 size_t count, loff_t pos)
533{
534 memset(ebuf, 0, sizeof(*ebuf));
0a4cd7c8 535 ebuf->i915 = i915;
84734a04
MK		 536
537 /* We need to have enough room to store any i915_error_state printf
538 * so that we can move it to start position.
539 */
540 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
541 ebuf->buf = kmalloc(ebuf->size,
542 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
543
544 if (ebuf->buf == NULL) {
545 ebuf->size = PAGE_SIZE;
546 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
547 }
548
549 if (ebuf->buf == NULL) {
550 ebuf->size = 128;
551 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
552 }
553
554 if (ebuf->buf == NULL)
555 return -ENOMEM;
556
557 ebuf->start = pos;
558
559 return 0;
560}
561
562static void i915_error_object_free(struct drm_i915_error_object *obj)
563{
564 int page;
565
566 if (obj == NULL)
567 return;
568
569 for (page = 0; page < obj->page_count; page++)
570 kfree(obj->pages[page]);
571
572 kfree(obj);
573}
574
575static void i915_error_state_free(struct kref *error_ref)
576{
577 struct drm_i915_error_state *error = container_of(error_ref,
578 typeof(*error), ref);
579 int i;
580
581 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
582 i915_error_object_free(error->ring[i].batchbuffer);
b3da4a62 583 i915_error_object_free(error->ring[i].wa_batchbuffer);
84734a04 584 i915_error_object_free(error->ring[i].ringbuffer);
362b8af7 585 i915_error_object_free(error->ring[i].hws_page);
84734a04
MK		 586 i915_error_object_free(error->ring[i].ctx);
587 kfree(error->ring[i].requests);
588 }
589
0ca36d78 590 i915_error_object_free(error->semaphore_obj);
0b37a9a9
MT		 591
592 for (i = 0; i < error->vm_count; i++)
593 kfree(error->active_bo[i]);
594
84734a04 595 kfree(error->active_bo);
0b37a9a9
MT		 596 kfree(error->active_bo_count);
597 kfree(error->pinned_bo);
598 kfree(error->pinned_bo_count);
84734a04
MK		 599 kfree(error->overlay);
600 kfree(error->display);
601 kfree(error);
602}
603
604static struct drm_i915_error_object *
8ae62dc6
CW		 605i915_error_object_create(struct drm_i915_private *dev_priv,
606 struct drm_i915_gem_object *src,
607 struct i915_address_space *vm)
84734a04
MK		 608{
609 struct drm_i915_error_object *dst;
aff43766 610 struct i915_vma *vma = NULL;
8ae62dc6 611 int num_pages;
b3c3f5e6
CW		 612 bool use_ggtt;
613 int i = 0;
e1f12325 614 u64 reloc_offset;
84734a04
MK		 615
616 if (src == NULL || src->pages == NULL)
617 return NULL;
618
8ae62dc6
CW		 619 num_pages = src->base.size >> PAGE_SHIFT;
620
84734a04
MK		 621 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
622 if (dst == NULL)
623 return NULL;
624
87a01e82
CW		 625 if (i915_gem_obj_bound(src, vm))
626 dst->gtt_offset = i915_gem_obj_offset(src, vm);
627 else
628 dst->gtt_offset = -1;
b3c3f5e6
CW		 629
630 reloc_offset = dst->gtt_offset;
aff43766
TU		 631 if (i915_is_ggtt(vm))
632 vma = i915_gem_obj_to_ggtt(src);
b3c3f5e6 633 use_ggtt = (src->cache_level == I915_CACHE_NONE &&
aff43766
TU		 634 vma && (vma->bound & GLOBAL_BIND) &&
635 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
b3c3f5e6
CW		 636
637 /* Cannot access stolen address directly, try to use the aperture */
638 if (src->stolen) {
639 use_ggtt = true;
640
aff43766 641 if (!(vma && vma->bound & GLOBAL_BIND))
b3c3f5e6
CW		 642 goto unwind;
643
644 reloc_offset = i915_gem_obj_ggtt_offset(src);
645 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
646 goto unwind;
647 }
648
649 /* Cannot access snooped pages through the aperture */
650 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
651 goto unwind;
652
653 dst->page_count = num_pages;
654 while (num_pages--) {
84734a04
MK		 655 unsigned long flags;
656 void *d;
657
658 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
659 if (d == NULL)
660 goto unwind;
661
662 local_irq_save(flags);
b3c3f5e6 663 if (use_ggtt) {
84734a04
MK		 664 void __iomem *s;
665
666 /* Simply ignore tiling or any overlapping fence.
667 * It's part of the error state, and this hopefully
668 * captures what the GPU read.
669 */
670
671 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
672 reloc_offset);
673 memcpy_fromio(d, s, PAGE_SIZE);
674 io_mapping_unmap_atomic(s);
84734a04
MK		 675 } else {
676 struct page *page;
677 void *s;
678
679 page = i915_gem_object_get_page(src, i);
680
681 drm_clflush_pages(&page, 1);
682
683 s = kmap_atomic(page);
684 memcpy(d, s, PAGE_SIZE);
685 kunmap_atomic(s);
686
687 drm_clflush_pages(&page, 1);
688 }
689 local_irq_restore(flags);
690
b3c3f5e6 691 dst->pages[i++] = d;
84734a04
MK		 692 reloc_offset += PAGE_SIZE;
693 }
84734a04
MK		 694
695 return dst;
696
697unwind:
698 while (i--)
699 kfree(dst->pages[i]);
700 kfree(dst);
701 return NULL;
702}
a7b91078 703#define i915_error_ggtt_object_create(dev_priv, src) \
8ae62dc6 704 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
84734a04
MK		 705
706static void capture_bo(struct drm_i915_error_buffer *err,
3a448734 707 struct i915_vma *vma)
84734a04 708{
3a448734 709 struct drm_i915_gem_object *obj = vma->obj;
b4716185 710 int i;
3a448734 711
84734a04
MK		 712 err->size = obj->base.size;
713 err->name = obj->base.name;
b4716185
CW		 714 for (i = 0; i < I915_NUM_RINGS; i++)
715 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
97b2a6a1 716 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
3a448734 717 err->gtt_offset = vma->node.start;
84734a04
MK		 718 err->read_domains = obj->base.read_domains;
719 err->write_domain = obj->base.write_domain;
720 err->fence_reg = obj->fence_reg;
721 err->pinned = 0;
d7f46fc4 722 if (i915_gem_obj_is_pinned(obj))
84734a04 723 err->pinned = 1;
84734a04
MK		 724 err->tiling = obj->tiling_mode;
725 err->dirty = obj->dirty;
726 err->purgeable = obj->madv != I915_MADV_WILLNEED;
5cc9ed4b 727 err->userptr = obj->userptr.mm != NULL;
b4716185
CW		 728 err->ring = obj->last_write_req ?
729 i915_gem_request_get_ring(obj->last_write_req)->id : -1;
84734a04
MK		 730 err->cache_level = obj->cache_level;
731}
732
733static u32 capture_active_bo(struct drm_i915_error_buffer *err,
734 int count, struct list_head *head)
735{
ca191b13 736 struct i915_vma *vma;
84734a04
MK		 737 int i = 0;
738
1c7f4bca 739 list_for_each_entry(vma, head, vm_link) {
3a448734 740 capture_bo(err++, vma);
84734a04
MK		 741 if (++i == count)
742 break;
743 }
744
745 return i;
746}
747
748static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
3a448734
CW		 749 int count, struct list_head *head,
750 struct i915_address_space *vm)
84734a04
MK		 751{
752 struct drm_i915_gem_object *obj;
3a448734
CW		 753 struct drm_i915_error_buffer * const first = err;
754 struct drm_i915_error_buffer * const last = err + count;
84734a04
MK		 755
756 list_for_each_entry(obj, head, global_list) {
3a448734 757 struct i915_vma *vma;
84734a04 758
3a448734 759 if (err == last)
84734a04 760 break;
3a448734 761
1c7f4bca 762 list_for_each_entry(vma, &obj->vma_list, obj_link)
fe14d5f4 763 if (vma->vm == vm && vma->pin_count > 0)
3a448734 764 capture_bo(err++, vma);
84734a04
MK		 765 }
766
3a448734 767 return err - first;
84734a04
MK		 768}
769
011cf577
BW		 770/* Generate a semi-unique error code. The code is not meant to have meaning, The
771 * code's only purpose is to try to prevent false duplicated bug reports by
772 * grossly estimating a GPU error state.
773 *
774 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
775 * the hang if we could strip the GTT offset information from it.
776 *
777 * It's only a small step better than a random number in its current form.
778 */
779static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
cb383002
MK		 780 struct drm_i915_error_state *error,
781 int *ring_id)
011cf577
BW		 782{
783 uint32_t error_code = 0;
784 int i;
785
786 /* IPEHR would be an ideal way to detect errors, as it's the gross
787 * measure of "the command that hung." However, has some very common
788 * synchronization commands which almost always appear in the case
789 * strictly a client bug. Use instdone to differentiate those some.
790 */
cb383002
MK		 791 for (i = 0; i < I915_NUM_RINGS; i++) {
792 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
793 if (ring_id)
794 *ring_id = i;
795
011cf577 796 return error->ring[i].ipehr ^ error->ring[i].instdone;
cb383002
MK		 797 }
798 }
011cf577
BW		 799
800 return error_code;
801}
802
84734a04
MK		 803static void i915_gem_record_fences(struct drm_device *dev,
804 struct drm_i915_error_state *error)
805{
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 int i;
808
ce38ab05 809 if (IS_GEN3(dev) || IS_GEN2(dev)) {
ce38ab05 810 for (i = 0; i < dev_priv->num_fence_regs; i++)
eecf613a
VS		 811 error->fence[i] = I915_READ(FENCE_REG(i));
812 } else if (IS_GEN5(dev) || IS_GEN4(dev)) {
813 for (i = 0; i < dev_priv->num_fence_regs; i++)
814 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
815 } else if (INTEL_INFO(dev)->gen >= 6) {
816 for (i = 0; i < dev_priv->num_fence_regs; i++)
817 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
818 }
84734a04
MK		 819}
820
87f85ebc 821
0ca36d78
BW		 822static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
823 struct drm_i915_error_state *error,
824 struct intel_engine_cs *ring,
825 struct drm_i915_error_ring *ering)
826{
b4558b46 827 struct intel_engine_cs *to;
0ca36d78
BW		 828 int i;
829
830 if (!i915_semaphore_is_enabled(dev_priv->dev))
831 return;
832
833 if (!error->semaphore_obj)
834 error->semaphore_obj =
cc1df8a3
DV		 835 i915_error_ggtt_object_create(dev_priv,
836 dev_priv->semaphore_obj);
0ca36d78 837
b4558b46
RV		 838 for_each_ring(to, dev_priv, i) {
839 int idx;
840 u16 signal_offset;
841 u32 *tmp;
0ca36d78 842
b4558b46
RV		 843 if (ring == to)
844 continue;
845
864c6181
RV		 846 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
847 / 4;
b4558b46
RV		 848 tmp = error->semaphore_obj->pages[0];
849 idx = intel_ring_sync_index(ring, to);
850
851 ering->semaphore_mboxes[idx] = tmp[signal_offset];
852 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
0ca36d78
BW		 853 }
854}
855
87f85ebc
BW		 856static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
857 struct intel_engine_cs *ring,
858 struct drm_i915_error_ring *ering)
859{
860 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
861 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
862 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
863 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
864
865 if (HAS_VEBOX(dev_priv->dev)) {
866 ering->semaphore_mboxes[2] =
867 I915_READ(RING_SYNC_2(ring->mmio_base));
868 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
869 }
870}
871
84734a04 872static void i915_record_ring_state(struct drm_device *dev,
0ca36d78 873 struct drm_i915_error_state *error,
a4872ba6 874 struct intel_engine_cs *ring,
362b8af7 875 struct drm_i915_error_ring *ering)
84734a04
MK		 876{
877 struct drm_i915_private *dev_priv = dev->dev_private;
878
879 if (INTEL_INFO(dev)->gen >= 6) {
3613cf1d 880 ering->rc_psmi = I915_READ(RING_PSMI_CTL(ring->mmio_base));
362b8af7 881 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
0ca36d78
BW		 882 if (INTEL_INFO(dev)->gen >= 8)
883 gen8_record_semaphore_state(dev_priv, error, ring, ering);
884 else
885 gen6_record_semaphore_state(dev_priv, ring, ering);
4e5aabfd
BW		 886 }
887
84734a04 888 if (INTEL_INFO(dev)->gen >= 4) {
362b8af7
BW		 889 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
890 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
891 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
892 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
893 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
894 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
13ffadd1
BW		 895 if (INTEL_INFO(dev)->gen >= 8) {
896 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
362b8af7 897 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
13ffadd1 898 }
362b8af7 899 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
84734a04 900 } else {
362b8af7
BW		 901 ering->faddr = I915_READ(DMA_FADD_I8XX);
902 ering->ipeir = I915_READ(IPEIR);
903 ering->ipehr = I915_READ(IPEHR);
bd93a50e 904 ering->instdone = I915_READ(GEN2_INSTDONE);
84734a04
MK		 905 }
906
362b8af7
BW		 907 ering->waiting = waitqueue_active(&ring->irq_queue);
908 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
909 ering->seqno = ring->get_seqno(ring, false);
910 ering->acthd = intel_ring_get_active_head(ring);
94f8cf10 911 ering->start = I915_READ_START(ring);
362b8af7
BW		 912 ering->head = I915_READ_HEAD(ring);
913 ering->tail = I915_READ_TAIL(ring);
914 ering->ctl = I915_READ_CTL(ring);
84734a04 915
f3ce3821 916 if (I915_NEED_GFX_HWS(dev)) {
f0f59a00 917 i915_reg_t mmio;
f3ce3821
CW		 918
919 if (IS_GEN7(dev)) {
920 switch (ring->id) {
921 default:
922 case RCS:
923 mmio = RENDER_HWS_PGA_GEN7;
924 break;
925 case BCS:
926 mmio = BLT_HWS_PGA_GEN7;
927 break;
928 case VCS:
929 mmio = BSD_HWS_PGA_GEN7;
930 break;
931 case VECS:
932 mmio = VEBOX_HWS_PGA_GEN7;
933 break;
934 }
935 } else if (IS_GEN6(ring->dev)) {
936 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
937 } else {
938 /* XXX: gen8 returns to sanity */
939 mmio = RING_HWS_PGA(ring->mmio_base);
940 }
941
362b8af7 942 ering->hws = I915_READ(mmio);
f3ce3821
CW		 943 }
944
362b8af7
BW		 945 ering->hangcheck_score = ring->hangcheck.score;
946 ering->hangcheck_action = ring->hangcheck.action;
6c7a01ec
BW		 947
948 if (USES_PPGTT(dev)) {
949 int i;
950
951 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
952
74745b09
RV		 953 if (IS_GEN6(dev))
954 ering->vm_info.pp_dir_base =
955 I915_READ(RING_PP_DIR_BASE_READ(ring));
956 else if (IS_GEN7(dev))
957 ering->vm_info.pp_dir_base =
958 I915_READ(RING_PP_DIR_BASE(ring));
959 else if (INTEL_INFO(dev)->gen >= 8)
6c7a01ec
BW		 960 for (i = 0; i < 4; i++) {
961 ering->vm_info.pdp[i] =
962 I915_READ(GEN8_RING_PDP_UDW(ring, i));
963 ering->vm_info.pdp[i] <<= 32;
964 ering->vm_info.pdp[i] |=
965 I915_READ(GEN8_RING_PDP_LDW(ring, i));
966 }
6c7a01ec 967 }
84734a04
MK		 968}
969
970
a4872ba6 971static void i915_gem_record_active_context(struct intel_engine_cs *ring,
84734a04
MK		 972 struct drm_i915_error_state *error,
973 struct drm_i915_error_ring *ering)
974{
975 struct drm_i915_private *dev_priv = ring->dev->dev_private;
976 struct drm_i915_gem_object *obj;
977
978 /* Currently render ring is the only HW context user */
979 if (ring->id != RCS || !error->ccid)
980 return;
981
982 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
36362ad3
BW		 983 if (!i915_gem_obj_ggtt_bound(obj))
984 continue;
985
84734a04 986 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
17d36749 987 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
84734a04
MK		 988 break;
989 }
990 }
991}
992
993static void i915_gem_record_rings(struct drm_device *dev,
994 struct drm_i915_error_state *error)
995{
996 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04
MK		 997 struct drm_i915_gem_request *request;
998 int i, count;
999
372fbb8e 1000 for (i = 0; i < I915_NUM_RINGS; i++) {
a4872ba6 1001 struct intel_engine_cs *ring = &dev_priv->ring[i];
9075e52f 1002 struct intel_ringbuffer *rbuf;
372fbb8e 1003
eee73b46
CW		 1004 error->ring[i].pid = -1;
1005
372fbb8e
CW		 1006 if (ring->dev == NULL)
1007 continue;
1008
1009 error->ring[i].valid = true;
1010
0ca36d78 1011 i915_record_ring_state(dev, error, ring, &error->ring[i]);
84734a04 1012
ab0e7ff9
CW		 1013 request = i915_gem_find_active_request(ring);
1014 if (request) {
ae6c4806
DV		 1015 struct i915_address_space *vm;
1016
1017 vm = request->ctx && request->ctx->ppgtt ?
1018 &request->ctx->ppgtt->base :
1019 &dev_priv->gtt.base;
1020
ab0e7ff9
CW		 1021 /* We need to copy these to an anonymous buffer
1022 * as the simplest method to avoid being overwritten
1023 * by userspace.
1024 */
1025 error->ring[i].batchbuffer =
1026 i915_error_object_create(dev_priv,
1027 request->batch_obj,
ae6c4806 1028 vm);
ab0e7ff9 1029
8ae62dc6 1030 if (HAS_BROKEN_CS_TLB(dev_priv->dev))
ab0e7ff9
CW		 1031 error->ring[i].wa_batchbuffer =
1032 i915_error_ggtt_object_create(dev_priv,
1033 ring->scratch.obj);
1034
071c92de 1035 if (request->pid) {
ab0e7ff9
CW		 1036 struct task_struct *task;
1037
1038 rcu_read_lock();
071c92de 1039 task = pid_task(request->pid, PIDTYPE_PID);
ab0e7ff9
CW		 1040 if (task) {
1041 strcpy(error->ring[i].comm, task->comm);
1042 error->ring[i].pid = task->pid;
1043 }
1044 rcu_read_unlock();
1045 }
1046 }
84734a04 1047
9075e52f
OM		 1048 if (i915.enable_execlists) {
1049 /* TODO: This is only a small fix to keep basic error
1050 * capture working, but we need to add more information
1051 * for it to be useful (e.g. dump the context being
1052 * executed).
1053 */
1054 if (request)
1055 rbuf = request->ctx->engine[ring->id].ringbuf;
1056 else
ed54c1a1 1057 rbuf = dev_priv->kernel_context->engine[ring->id].ringbuf;
9075e52f
OM		 1058 } else
1059 rbuf = ring->buffer;
1060
1061 error->ring[i].cpu_ring_head = rbuf->head;
1062 error->ring[i].cpu_ring_tail = rbuf->tail;
1063
84734a04 1064 error->ring[i].ringbuffer =
9075e52f 1065 i915_error_ggtt_object_create(dev_priv, rbuf->obj);
84734a04 1066
8ae62dc6
CW		 1067 error->ring[i].hws_page =
1068 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
84734a04
MK		 1069
1070 i915_gem_record_active_context(ring, error, &error->ring[i]);
1071
1072 count = 0;
1073 list_for_each_entry(request, &ring->request_list, list)
1074 count++;
1075
1076 error->ring[i].num_requests = count;
1077 error->ring[i].requests =
a1e22653 1078 kcalloc(count, sizeof(*error->ring[i].requests),
84734a04
MK		 1079 GFP_ATOMIC);
1080 if (error->ring[i].requests == NULL) {
1081 error->ring[i].num_requests = 0;
1082 continue;
1083 }
1084
1085 count = 0;
1086 list_for_each_entry(request, &ring->request_list, list) {
1087 struct drm_i915_error_request *erq;
1088
9c8e1bdb
TE		 1089 if (count >= error->ring[i].num_requests) {
1090 /*
1091 * If the ring request list was changed in
1092 * between the point where the error request
1093 * list was created and dimensioned and this
1094 * point then just exit early to avoid crashes.
1095 *
1096 * We don't need to communicate that the
1097 * request list changed state during error
1098 * state capture and that the error state is
1099 * slightly incorrect as a consequence since we
1100 * are typically only interested in the request
1101 * list state at the point of error state
1102 * capture, not in any changes happening during
1103 * the capture.
1104 */
1105 break;
1106 }
1107
84734a04
MK		 1108 erq = &error->ring[i].requests[count++];
1109 erq->seqno = request->seqno;
1110 erq->jiffies = request->emitted_jiffies;
72f95afa 1111 erq->tail = request->postfix;
84734a04
MK		 1112 }
1113 }
1114}
1115
95f5301d
BW		 1116/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1117 * VM.
1118 */
1119static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1120 struct drm_i915_error_state *error,
1121 struct i915_address_space *vm,
1122 const int ndx)
84734a04 1123{
95f5301d 1124 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
84734a04 1125 struct drm_i915_gem_object *obj;
95f5301d 1126 struct i915_vma *vma;
84734a04
MK		 1127 int i;
1128
1129 i = 0;
1c7f4bca 1130 list_for_each_entry(vma, &vm->active_list, vm_link)
84734a04 1131 i++;
95f5301d 1132 error->active_bo_count[ndx] = i;
3a448734
CW		 1133
1134 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1c7f4bca 1135 list_for_each_entry(vma, &obj->vma_list, obj_link)
fe14d5f4 1136 if (vma->vm == vm && vma->pin_count > 0)
3a448734 1137 i++;
3a448734 1138 }
95f5301d 1139 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
84734a04
MK		 1140
1141 if (i) {
a1e22653 1142 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
95f5301d
BW		 1143 if (active_bo)
1144 pinned_bo = active_bo + error->active_bo_count[ndx];
84734a04
MK		 1145 }
1146
95f5301d
BW		 1147 if (active_bo)
1148 error->active_bo_count[ndx] =
1149 capture_active_bo(active_bo,
1150 error->active_bo_count[ndx],
5cef07e1 1151 &vm->active_list);
84734a04 1152
95f5301d
BW		 1153 if (pinned_bo)
1154 error->pinned_bo_count[ndx] =
1155 capture_pinned_bo(pinned_bo,
1156 error->pinned_bo_count[ndx],
3a448734 1157 &dev_priv->mm.bound_list, vm);
95f5301d
BW		 1158 error->active_bo[ndx] = active_bo;
1159 error->pinned_bo[ndx] = pinned_bo;
1160}
1161
1162static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1163 struct drm_i915_error_state *error)
1164{
1165 struct i915_address_space *vm;
1166 int cnt = 0, i = 0;
1167
1168 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1169 cnt++;
1170
95f5301d
BW		 1171 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1172 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1173 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1174 GFP_ATOMIC);
1175 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1176 GFP_ATOMIC);
1177
3a448734
CW		 1178 if (error->active_bo == NULL ||
1179 error->pinned_bo == NULL ||
1180 error->active_bo_count == NULL ||
1181 error->pinned_bo_count == NULL) {
1182 kfree(error->active_bo);
1183 kfree(error->active_bo_count);
1184 kfree(error->pinned_bo);
1185 kfree(error->pinned_bo_count);
1186
1187 error->active_bo = NULL;
1188 error->active_bo_count = NULL;
1189 error->pinned_bo = NULL;
1190 error->pinned_bo_count = NULL;
1191 } else {
1192 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1193 i915_gem_capture_vm(dev_priv, error, vm, i++);
1194
1195 error->vm_count = cnt;
1196 }
84734a04
MK		 1197}
1198
1d762aad
BW		 1199/* Capture all registers which don't fit into another category. */
1200static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1201 struct drm_i915_error_state *error)
84734a04 1202{
1d762aad 1203 struct drm_device *dev = dev_priv->dev;
885ea5a8 1204 int i;
84734a04 1205
654c90c6
BW		 1206 /* General organization
1207 * 1. Registers specific to a single generation
1208 * 2. Registers which belong to multiple generations
1209 * 3. Feature specific registers.
1210 * 4. Everything else
1211 * Please try to follow the order.
1212 */
84734a04 1213
654c90c6
BW		 1214 /* 1: Registers specific to a single generation */
1215 if (IS_VALLEYVIEW(dev)) {
885ea5a8 1216 error->gtier[0] = I915_READ(GTIER);
843db716 1217 error->ier = I915_READ(VLV_IER);
40181697 1218 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
654c90c6 1219 }
84734a04 1220
654c90c6
BW		 1221 if (IS_GEN7(dev))
1222 error->err_int = I915_READ(GEN7_ERR_INT);
84734a04 1223
6c826f34
MK		 1224 if (INTEL_INFO(dev)->gen >= 8) {
1225 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1226 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1227 }
1228
91ec5d11 1229 if (IS_GEN6(dev)) {
40181697 1230 error->forcewake = I915_READ_FW(FORCEWAKE);
91ec5d11
BW		 1231 error->gab_ctl = I915_READ(GAB_CTL);
1232 error->gfx_mode = I915_READ(GFX_MODE);
1233 }
84734a04 1234
654c90c6
BW		 1235 /* 2: Registers which belong to multiple generations */
1236 if (INTEL_INFO(dev)->gen >= 7)
40181697 1237 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
84734a04
MK		 1238
1239 if (INTEL_INFO(dev)->gen >= 6) {
654c90c6 1240 error->derrmr = I915_READ(DERRMR);
84734a04
MK		 1241 error->error = I915_READ(ERROR_GEN6);
1242 error->done_reg = I915_READ(DONE_REG);
1243 }
1244
654c90c6 1245 /* 3: Feature specific registers */
91ec5d11
BW		 1246 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1247 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1248 error->gac_eco = I915_READ(GAC_ECO_BITS);
1249 }
1250
1251 /* 4: Everything else */
654c90c6
BW		 1252 if (HAS_HW_CONTEXTS(dev))
1253 error->ccid = I915_READ(CCID);
1254
885ea5a8
RV		 1255 if (INTEL_INFO(dev)->gen >= 8) {
1256 error->ier = I915_READ(GEN8_DE_MISC_IER);
1257 for (i = 0; i < 4; i++)
1258 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1259 } else if (HAS_PCH_SPLIT(dev)) {
843db716 1260 error->ier = I915_READ(DEIER);
885ea5a8 1261 error->gtier[0] = I915_READ(GTIER);
843db716
RV		 1262 } else if (IS_GEN2(dev)) {
1263 error->ier = I915_READ16(IER);
1264 } else if (!IS_VALLEYVIEW(dev)) {
1265 error->ier = I915_READ(IER);
654c90c6 1266 }
654c90c6
BW		 1267 error->eir = I915_READ(EIR);
1268 error->pgtbl_er = I915_READ(PGTBL_ER);
84734a04
MK		 1269
1270 i915_get_extra_instdone(dev, error->extra_instdone);
1d762aad
BW		 1271}
1272
cb383002 1273static void i915_error_capture_msg(struct drm_device *dev,
58174462
MK		 1274 struct drm_i915_error_state *error,
1275 bool wedged,
1276 const char *error_msg)
cb383002
MK		 1277{
1278 struct drm_i915_private *dev_priv = dev->dev_private;
1279 u32 ecode;
58174462 1280 int ring_id = -1, len;
cb383002
MK		 1281
1282 ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1283
58174462 1284 len = scnprintf(error->error_msg, sizeof(error->error_msg),
0b5492d6
MK		 1285 "GPU HANG: ecode %d:%d:0x%08x",
1286 INTEL_INFO(dev)->gen, ring_id, ecode);
58174462
MK		 1287
1288 if (ring_id != -1 && error->ring[ring_id].pid != -1)
1289 len += scnprintf(error->error_msg + len,
1290 sizeof(error->error_msg) - len,
1291 ", in %s [%d]",
1292 error->ring[ring_id].comm,
1293 error->ring[ring_id].pid);
1294
1295 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1296 ", reason: %s, action: %s",
1297 error_msg,
1298 wedged ? "reset" : "continue");
cb383002
MK		 1299}
1300
48b031e3
MK		 1301static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1302 struct drm_i915_error_state *error)
1303{
eb5be9d0
CW		 1304 error->iommu = -1;
1305#ifdef CONFIG_INTEL_IOMMU
1306 error->iommu = intel_iommu_gfx_mapped;
1307#endif
48b031e3 1308 error->reset_count = i915_reset_count(&dev_priv->gpu_error);
62d5d69b 1309 error->suspend_count = dev_priv->suspend_count;
48b031e3
MK		 1310}
1311
1d762aad
BW		 1312/**
1313 * i915_capture_error_state - capture an error record for later analysis
1314 * @dev: drm device
1315 *
1316 * Should be called when an error is detected (either a hang or an error
1317 * interrupt) to capture error state from the time of the error. Fills
1318 * out a structure which becomes available in debugfs for user level tools
1319 * to pick up.
1320 */
58174462
MK		 1321void i915_capture_error_state(struct drm_device *dev, bool wedged,
1322 const char *error_msg)
1d762aad 1323{
53a4c6b2 1324 static bool warned;
1d762aad
BW		 1325 struct drm_i915_private *dev_priv = dev->dev_private;
1326 struct drm_i915_error_state *error;
1327 unsigned long flags;
1d762aad
BW		 1328
1329 /* Account for pipe specific data like PIPE*STAT */
1330 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1331 if (!error) {
1332 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1333 return;
1334 }
1335
011cf577
BW		 1336 kref_init(&error->ref);
1337
48b031e3 1338 i915_capture_gen_state(dev_priv, error);
011cf577
BW		 1339 i915_capture_reg_state(dev_priv, error);
1340 i915_gem_capture_buffers(dev_priv, error);
1341 i915_gem_record_fences(dev, error);
1342 i915_gem_record_rings(dev, error);
1d762aad 1343
84734a04
MK		 1344 do_gettimeofday(&error->time);
1345
1346 error->overlay = intel_overlay_capture_error_state(dev);
1347 error->display = intel_display_capture_error_state(dev);
1348
58174462 1349 i915_error_capture_msg(dev, error, wedged, error_msg);
cb383002
MK		 1350 DRM_INFO("%s\n", error->error_msg);
1351
84734a04
MK		 1352 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1353 if (dev_priv->gpu_error.first_error == NULL) {
1354 dev_priv->gpu_error.first_error = error;
1355 error = NULL;
1356 }
1357 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1358
cb383002 1359 if (error) {
84734a04 1360 i915_error_state_free(&error->ref);
cb383002
MK		 1361 return;
1362 }
1363
1364 if (!warned) {
1365 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1366 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1367 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1368 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1369 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1370 warned = true;
1371 }
84734a04
MK		 1372}
1373
1374void i915_error_state_get(struct drm_device *dev,
1375 struct i915_error_state_file_priv *error_priv)
1376{
1377 struct drm_i915_private *dev_priv = dev->dev_private;
84734a04 1378
5b254c59 1379 spin_lock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1380 error_priv->error = dev_priv->gpu_error.first_error;
1381 if (error_priv->error)
1382 kref_get(&error_priv->error->ref);
5b254c59 1383 spin_unlock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1384
1385}
1386
1387void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1388{
1389 if (error_priv->error)
1390 kref_put(&error_priv->error->ref, i915_error_state_free);
1391}
1392
1393void i915_destroy_error_state(struct drm_device *dev)
1394{
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_i915_error_state *error;
84734a04 1397
5b254c59 1398 spin_lock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1399 error = dev_priv->gpu_error.first_error;
1400 dev_priv->gpu_error.first_error = NULL;
5b254c59 1401 spin_unlock_irq(&dev_priv->gpu_error.lock);
84734a04
MK		 1402
1403 if (error)
1404 kref_put(&error->ref, i915_error_state_free);
1405}
1406
0a4cd7c8 1407const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
84734a04
MK		 1408{
1409 switch (type) {
1410 case I915_CACHE_NONE: return " uncached";
0a4cd7c8 1411 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
350ec881 1412 case I915_CACHE_L3_LLC: return " L3+LLC";
f56383cb 1413 case I915_CACHE_WT: return " WT";
84734a04
MK		 1414 default: return "";
1415 }
1416}
1417
1418/* NB: please notice the memset */
1419void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1420{
1421 struct drm_i915_private *dev_priv = dev->dev_private;
1422 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1423
563f94f6 1424 if (IS_GEN2(dev) || IS_GEN3(dev))
bd93a50e 1425 instdone[0] = I915_READ(GEN2_INSTDONE);
563f94f6 1426 else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
f1d54348 1427 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
13d70b81 1428 instdone[1] = I915_READ(GEN4_INSTDONE1);
563f94f6 1429 } else if (INTEL_INFO(dev)->gen >= 7) {
f1d54348 1430 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
84734a04
MK		 1431 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1432 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1433 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
84734a04
MK		 1434 }
1435}
Linux 6.x block layer and io_uring tree(s)