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drm/i915: Engage the DP scramble reset for pipe C on CHV
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
fb1ae911 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 142 list_for_each_entry(vma, &obj->vma_list, vma_link)
143 if (vma->pin_count > 0)
144 pin_count++;
145 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 146 if (obj->pin_display)
147 seq_printf(m, " (display)");
37811fcc
CW		 148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
155 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
156 vma->node.start, vma->node.size);
157 }
c1ad11fc
CW		 158 if (obj->stolen)
159 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 160 if (obj->pin_mappable || obj->fault_mappable) {
161 char s[3], *t = s;
162 if (obj->pin_mappable)
163 *t++ = 'p';
164 if (obj->fault_mappable)
165 *t++ = 'f';
166 *t = '\0';
167 seq_printf(m, " (%s mappable)", s);
168 }
41c52415
JH		 169 if (obj->last_read_req != NULL)
170 seq_printf(m, " (%s)",
171 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 172 if (obj->frontbuffer_bits)
173 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 174}
175
273497e5 176static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 177{
ea0c76f8 178 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 179 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
180 seq_putc(m, ' ');
181}
182
433e12f7 183static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 184{
9f25d007 185 struct drm_info_node *node = m->private;
433e12f7
BG		 186 uintptr_t list = (uintptr_t) node->info_ent->data;
187 struct list_head *head;
2017263e 188 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 189 struct drm_i915_private *dev_priv = dev->dev_private;
190 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 191 struct i915_vma *vma;
8f2480fb
CW		 192 size_t total_obj_size, total_gtt_size;
193 int count, ret;
de227ef0
CW		 194
195 ret = mutex_lock_interruptible(&dev->struct_mutex);
196 if (ret)
197 return ret;
2017263e 198
ca191b13 199 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 200 switch (list) {
201 case ACTIVE_LIST:
267f0c90 202 seq_puts(m, "Active:\n");
5cef07e1 203 head = &vm->active_list;
433e12f7
BG		 204 break;
205 case INACTIVE_LIST:
267f0c90 206 seq_puts(m, "Inactive:\n");
5cef07e1 207 head = &vm->inactive_list;
433e12f7 208 break;
433e12f7 209 default:
de227ef0
CW		 210 mutex_unlock(&dev->struct_mutex);
211 return -EINVAL;
2017263e 212 }
2017263e 213
8f2480fb 214 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 215 list_for_each_entry(vma, head, mm_list) {
216 seq_printf(m, " ");
217 describe_obj(m, vma->obj);
218 seq_printf(m, "\n");
219 total_obj_size += vma->obj->base.size;
220 total_gtt_size += vma->node.size;
8f2480fb 221 count++;
2017263e 222 }
de227ef0 223 mutex_unlock(&dev->struct_mutex);
5e118f41 224
8f2480fb
CW		 225 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
226 count, total_obj_size, total_gtt_size);
2017263e
BG		 227 return 0;
228}
229
6d2b8885
CW		 230static int obj_rank_by_stolen(void *priv,
231 struct list_head *A, struct list_head *B)
232{
233 struct drm_i915_gem_object *a =
b25cb2f8 234 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 235 struct drm_i915_gem_object *b =
b25cb2f8 236 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 237
238 return a->stolen->start - b->stolen->start;
239}
240
241static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
242{
9f25d007 243 struct drm_info_node *node = m->private;
6d2b8885
CW		 244 struct drm_device *dev = node->minor->dev;
245 struct drm_i915_private *dev_priv = dev->dev_private;
246 struct drm_i915_gem_object *obj;
247 size_t total_obj_size, total_gtt_size;
248 LIST_HEAD(stolen);
249 int count, ret;
250
251 ret = mutex_lock_interruptible(&dev->struct_mutex);
252 if (ret)
253 return ret;
254
255 total_obj_size = total_gtt_size = count = 0;
256 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
257 if (obj->stolen == NULL)
258 continue;
259
b25cb2f8 260 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 261
262 total_obj_size += obj->base.size;
263 total_gtt_size += i915_gem_obj_ggtt_size(obj);
264 count++;
265 }
266 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
267 if (obj->stolen == NULL)
268 continue;
269
b25cb2f8 270 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 271
272 total_obj_size += obj->base.size;
273 count++;
274 }
275 list_sort(NULL, &stolen, obj_rank_by_stolen);
276 seq_puts(m, "Stolen:\n");
277 while (!list_empty(&stolen)) {
b25cb2f8 278 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 279 seq_puts(m, " ");
280 describe_obj(m, obj);
281 seq_putc(m, '\n');
b25cb2f8 282 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 283 }
284 mutex_unlock(&dev->struct_mutex);
285
286 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
287 count, total_obj_size, total_gtt_size);
288 return 0;
289}
290
6299f992
CW		 291#define count_objects(list, member) do { \
292 list_for_each_entry(obj, list, member) { \
f343c5f6 293 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 294 ++count; \
295 if (obj->map_and_fenceable) { \
f343c5f6 296 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 297 ++mappable_count; \
298 } \
299 } \
0206e353 300} while (0)
6299f992 301
2db8e9d6 302struct file_stats {
6313c204 303 struct drm_i915_file_private *file_priv;
2db8e9d6 304 int count;
c67a17e9
CW		 305 size_t total, unbound;
306 size_t global, shared;
307 size_t active, inactive;
2db8e9d6
CW		 308};
309
310static int per_file_stats(int id, void *ptr, void *data)
311{
312 struct drm_i915_gem_object *obj = ptr;
313 struct file_stats *stats = data;
6313c204 314 struct i915_vma *vma;
2db8e9d6
CW		 315
316 stats->count++;
317 stats->total += obj->base.size;
318
c67a17e9
CW		 319 if (obj->base.name || obj->base.dma_buf)
320 stats->shared += obj->base.size;
321
6313c204
CW		 322 if (USES_FULL_PPGTT(obj->base.dev)) {
323 list_for_each_entry(vma, &obj->vma_list, vma_link) {
324 struct i915_hw_ppgtt *ppgtt;
325
326 if (!drm_mm_node_allocated(&vma->node))
327 continue;
328
329 if (i915_is_ggtt(vma->vm)) {
330 stats->global += obj->base.size;
331 continue;
332 }
333
334 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 335 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 336 continue;
337
41c52415 338 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 339 stats->active += obj->base.size;
340 else
341 stats->inactive += obj->base.size;
342
343 return 0;
344 }
2db8e9d6 345 } else {
6313c204
CW		 346 if (i915_gem_obj_ggtt_bound(obj)) {
347 stats->global += obj->base.size;
41c52415 348 if (obj->active)
6313c204
CW		 349 stats->active += obj->base.size;
350 else
351 stats->inactive += obj->base.size;
352 return 0;
353 }
2db8e9d6
CW		 354 }
355
6313c204
CW		 356 if (!list_empty(&obj->global_list))
357 stats->unbound += obj->base.size;
358
2db8e9d6
CW		 359 return 0;
360}
361
ca191b13
BW		 362#define count_vmas(list, member) do { \
363 list_for_each_entry(vma, list, member) { \
364 size += i915_gem_obj_ggtt_size(vma->obj); \
365 ++count; \
366 if (vma->obj->map_and_fenceable) { \
367 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
368 ++mappable_count; \
369 } \
370 } \
371} while (0)
372
373static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 374{
9f25d007 375 struct drm_info_node *node = m->private;
73aa808f
CW		 376 struct drm_device *dev = node->minor->dev;
377 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 378 u32 count, mappable_count, purgeable_count;
379 size_t size, mappable_size, purgeable_size;
6299f992 380 struct drm_i915_gem_object *obj;
5cef07e1 381 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 382 struct drm_file *file;
ca191b13 383 struct i915_vma *vma;
73aa808f
CW		 384 int ret;
385
386 ret = mutex_lock_interruptible(&dev->struct_mutex);
387 if (ret)
388 return ret;
389
6299f992
CW		 390 seq_printf(m, "%u objects, %zu bytes\n",
391 dev_priv->mm.object_count,
392 dev_priv->mm.object_memory);
393
394 size = count = mappable_size = mappable_count = 0;
35c20a60 395 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 396 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
397 count, mappable_count, size, mappable_size);
398
399 size = count = mappable_size = mappable_count = 0;
ca191b13 400 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 401 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
402 count, mappable_count, size, mappable_size);
403
6299f992 404 size = count = mappable_size = mappable_count = 0;
ca191b13 405 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 406 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
407 count, mappable_count, size, mappable_size);
408
b7abb714 409 size = count = purgeable_size = purgeable_count = 0;
35c20a60 410 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 411 size += obj->base.size, ++count;
b7abb714
CW		 412 if (obj->madv == I915_MADV_DONTNEED)
413 purgeable_size += obj->base.size, ++purgeable_count;
414 }
6c085a72
CW		 415 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
416
6299f992 417 size = count = mappable_size = mappable_count = 0;
35c20a60 418 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 419 if (obj->fault_mappable) {
f343c5f6 420 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 421 ++count;
422 }
423 if (obj->pin_mappable) {
f343c5f6 424 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 425 ++mappable_count;
426 }
b7abb714
CW		 427 if (obj->madv == I915_MADV_DONTNEED) {
428 purgeable_size += obj->base.size;
429 ++purgeable_count;
430 }
6299f992 431 }
b7abb714
CW		 432 seq_printf(m, "%u purgeable objects, %zu bytes\n",
433 purgeable_count, purgeable_size);
6299f992
CW		 434 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
435 mappable_count, mappable_size);
436 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
437 count, size);
438
93d18799 439 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 440 dev_priv->gtt.base.total,
441 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 442
267f0c90 443 seq_putc(m, '\n');
2db8e9d6
CW		 444 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
445 struct file_stats stats;
3ec2f427 446 struct task_struct *task;
2db8e9d6
CW		 447
448 memset(&stats, 0, sizeof(stats));
6313c204 449 stats.file_priv = file->driver_priv;
5b5ffff0 450 spin_lock(&file->table_lock);
2db8e9d6 451 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 452 spin_unlock(&file->table_lock);
3ec2f427
TH		 453 /*
454 * Although we have a valid reference on file->pid, that does
455 * not guarantee that the task_struct who called get_pid() is
456 * still alive (e.g. get_pid(current) => fork() => exit()).
457 * Therefore, we need to protect this ->comm access using RCU.
458 */
459 rcu_read_lock();
460 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 461 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 462 task ? task->comm : "<unknown>",
2db8e9d6
CW		 463 stats.count,
464 stats.total,
465 stats.active,
466 stats.inactive,
6313c204 467 stats.global,
c67a17e9 468 stats.shared,
2db8e9d6 469 stats.unbound);
3ec2f427 470 rcu_read_unlock();
2db8e9d6
CW		 471 }
472
73aa808f
CW		 473 mutex_unlock(&dev->struct_mutex);
474
475 return 0;
476}
477
aee56cff 478static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 479{
9f25d007 480 struct drm_info_node *node = m->private;
08c18323 481 struct drm_device *dev = node->minor->dev;
1b50247a 482 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 483 struct drm_i915_private *dev_priv = dev->dev_private;
484 struct drm_i915_gem_object *obj;
485 size_t total_obj_size, total_gtt_size;
486 int count, ret;
487
488 ret = mutex_lock_interruptible(&dev->struct_mutex);
489 if (ret)
490 return ret;
491
492 total_obj_size = total_gtt_size = count = 0;
35c20a60 493 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 494 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 495 continue;
496
267f0c90 497 seq_puts(m, " ");
08c18323 498 describe_obj(m, obj);
267f0c90 499 seq_putc(m, '\n');
08c18323 500 total_obj_size += obj->base.size;
f343c5f6 501 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 502 count++;
503 }
504
505 mutex_unlock(&dev->struct_mutex);
506
507 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
508 count, total_obj_size, total_gtt_size);
509
510 return 0;
511}
512
4e5359cd
SF		 513static int i915_gem_pageflip_info(struct seq_file *m, void *data)
514{
9f25d007 515 struct drm_info_node *node = m->private;
4e5359cd 516 struct drm_device *dev = node->minor->dev;
d6bbafa1 517 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 518 struct intel_crtc *crtc;
8a270ebf
DV		 519 int ret;
520
521 ret = mutex_lock_interruptible(&dev->struct_mutex);
522 if (ret)
523 return ret;
4e5359cd 524
d3fcc808 525 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 526 const char pipe = pipe_name(crtc->pipe);
527 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 528 struct intel_unpin_work *work;
529
5e2d7afc 530 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 531 work = crtc->unpin_work;
532 if (work == NULL) {
9db4a9c7 533 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 534 pipe, plane);
535 } else {
d6bbafa1
CW		 536 u32 addr;
537
e7d841ca 538 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 539 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 540 pipe, plane);
541 } else {
9db4a9c7 542 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 543 pipe, plane);
544 }
3a8a946e
DV		 545 if (work->flip_queued_req) {
546 struct intel_engine_cs *ring =
547 i915_gem_request_get_ring(work->flip_queued_req);
548
d6bbafa1 549 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
3a8a946e 550 ring->name,
f06cc1b9 551 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 552 dev_priv->next_seqno,
3a8a946e 553 ring->get_seqno(ring, true),
1b5a433a 554 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 555 } else
556 seq_printf(m, "Flip not associated with any ring\n");
557 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
558 work->flip_queued_vblank,
559 work->flip_ready_vblank,
560 drm_vblank_count(dev, crtc->pipe));
4e5359cd 561 if (work->enable_stall_check)
267f0c90 562 seq_puts(m, "Stall check enabled, ");
4e5359cd 563 else
267f0c90 564 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 565 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 566
d6bbafa1
CW		 567 if (INTEL_INFO(dev)->gen >= 4)
568 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
569 else
570 addr = I915_READ(DSPADDR(crtc->plane));
571 seq_printf(m, "Current scanout address 0x%08x\n", addr);
572
4e5359cd 573 if (work->pending_flip_obj) {
d6bbafa1
CW		 574 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
575 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 576 }
577 }
5e2d7afc 578 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 579 }
580
8a270ebf
DV		 581 mutex_unlock(&dev->struct_mutex);
582
4e5359cd
SF		 583 return 0;
584}
585
2017263e
BG		 586static int i915_gem_request_info(struct seq_file *m, void *data)
587{
9f25d007 588 struct drm_info_node *node = m->private;
2017263e 589 struct drm_device *dev = node->minor->dev;
e277a1f8 590 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 591 struct intel_engine_cs *ring;
2017263e 592 struct drm_i915_gem_request *gem_request;
a2c7f6fd 593 int ret, count, i;
de227ef0
CW		 594
595 ret = mutex_lock_interruptible(&dev->struct_mutex);
596 if (ret)
597 return ret;
2017263e 598
c2c347a9 599 count = 0;
a2c7f6fd
CW		 600 for_each_ring(ring, dev_priv, i) {
601 if (list_empty(&ring->request_list))
602 continue;
603
604 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 605 list_for_each_entry(gem_request,
a2c7f6fd 606 &ring->request_list,
c2c347a9
CW		 607 list) {
608 seq_printf(m, " %d @ %d\n",
609 gem_request->seqno,
610 (int) (jiffies - gem_request->emitted_jiffies));
611 }
612 count++;
2017263e 613 }
de227ef0
CW		 614 mutex_unlock(&dev->struct_mutex);
615
c2c347a9 616 if (count == 0)
267f0c90 617 seq_puts(m, "No requests\n");
c2c347a9 618
2017263e
BG		 619 return 0;
620}
621
b2223497 622static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 623 struct intel_engine_cs *ring)
b2223497
CW		 624{
625 if (ring->get_seqno) {
43a7b924 626 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 627 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 628 }
629}
630
2017263e
BG		 631static int i915_gem_seqno_info(struct seq_file *m, void *data)
632{
9f25d007 633 struct drm_info_node *node = m->private;
2017263e 634 struct drm_device *dev = node->minor->dev;
e277a1f8 635 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 636 struct intel_engine_cs *ring;
1ec14ad3 637 int ret, i;
de227ef0
CW		 638
639 ret = mutex_lock_interruptible(&dev->struct_mutex);
640 if (ret)
641 return ret;
c8c8fb33 642 intel_runtime_pm_get(dev_priv);
2017263e 643
a2c7f6fd
CW		 644 for_each_ring(ring, dev_priv, i)
645 i915_ring_seqno_info(m, ring);
de227ef0 646
c8c8fb33 647 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 648 mutex_unlock(&dev->struct_mutex);
649
2017263e
BG		 650 return 0;
651}
652
653
654static int i915_interrupt_info(struct seq_file *m, void *data)
655{
9f25d007 656 struct drm_info_node *node = m->private;
2017263e 657 struct drm_device *dev = node->minor->dev;
e277a1f8 658 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 659 struct intel_engine_cs *ring;
9db4a9c7 660 int ret, i, pipe;
de227ef0
CW		 661
662 ret = mutex_lock_interruptible(&dev->struct_mutex);
663 if (ret)
664 return ret;
c8c8fb33 665 intel_runtime_pm_get(dev_priv);
2017263e 666
74e1ca8c 667 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 668 seq_printf(m, "Master Interrupt Control:\t%08x\n",
669 I915_READ(GEN8_MASTER_IRQ));
670
671 seq_printf(m, "Display IER:\t%08x\n",
672 I915_READ(VLV_IER));
673 seq_printf(m, "Display IIR:\t%08x\n",
674 I915_READ(VLV_IIR));
675 seq_printf(m, "Display IIR_RW:\t%08x\n",
676 I915_READ(VLV_IIR_RW));
677 seq_printf(m, "Display IMR:\t%08x\n",
678 I915_READ(VLV_IMR));
055e393f 679 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 680 seq_printf(m, "Pipe %c stat:\t%08x\n",
681 pipe_name(pipe),
682 I915_READ(PIPESTAT(pipe)));
683
684 seq_printf(m, "Port hotplug:\t%08x\n",
685 I915_READ(PORT_HOTPLUG_EN));
686 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
687 I915_READ(VLV_DPFLIPSTAT));
688 seq_printf(m, "DPINVGTT:\t%08x\n",
689 I915_READ(DPINVGTT));
690
691 for (i = 0; i < 4; i++) {
692 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
693 i, I915_READ(GEN8_GT_IMR(i)));
694 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
695 i, I915_READ(GEN8_GT_IIR(i)));
696 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
697 i, I915_READ(GEN8_GT_IER(i)));
698 }
699
700 seq_printf(m, "PCU interrupt mask:\t%08x\n",
701 I915_READ(GEN8_PCU_IMR));
702 seq_printf(m, "PCU interrupt identity:\t%08x\n",
703 I915_READ(GEN8_PCU_IIR));
704 seq_printf(m, "PCU interrupt enable:\t%08x\n",
705 I915_READ(GEN8_PCU_IER));
706 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 707 seq_printf(m, "Master Interrupt Control:\t%08x\n",
708 I915_READ(GEN8_MASTER_IRQ));
709
710 for (i = 0; i < 4; i++) {
711 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
712 i, I915_READ(GEN8_GT_IMR(i)));
713 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
714 i, I915_READ(GEN8_GT_IIR(i)));
715 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
716 i, I915_READ(GEN8_GT_IER(i)));
717 }
718
055e393f 719 for_each_pipe(dev_priv, pipe) {
f458ebbc 720 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 721 POWER_DOMAIN_PIPE(pipe))) {
722 seq_printf(m, "Pipe %c power disabled\n",
723 pipe_name(pipe));
724 continue;
725 }
a123f157 726 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 727 pipe_name(pipe),
728 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 729 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 730 pipe_name(pipe),
731 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 732 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 733 pipe_name(pipe),
734 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 735 }
736
737 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
738 I915_READ(GEN8_DE_PORT_IMR));
739 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
740 I915_READ(GEN8_DE_PORT_IIR));
741 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
742 I915_READ(GEN8_DE_PORT_IER));
743
744 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
745 I915_READ(GEN8_DE_MISC_IMR));
746 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
747 I915_READ(GEN8_DE_MISC_IIR));
748 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
749 I915_READ(GEN8_DE_MISC_IER));
750
751 seq_printf(m, "PCU interrupt mask:\t%08x\n",
752 I915_READ(GEN8_PCU_IMR));
753 seq_printf(m, "PCU interrupt identity:\t%08x\n",
754 I915_READ(GEN8_PCU_IIR));
755 seq_printf(m, "PCU interrupt enable:\t%08x\n",
756 I915_READ(GEN8_PCU_IER));
757 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 758 seq_printf(m, "Display IER:\t%08x\n",
759 I915_READ(VLV_IER));
760 seq_printf(m, "Display IIR:\t%08x\n",
761 I915_READ(VLV_IIR));
762 seq_printf(m, "Display IIR_RW:\t%08x\n",
763 I915_READ(VLV_IIR_RW));
764 seq_printf(m, "Display IMR:\t%08x\n",
765 I915_READ(VLV_IMR));
055e393f 766 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 767 seq_printf(m, "Pipe %c stat:\t%08x\n",
768 pipe_name(pipe),
769 I915_READ(PIPESTAT(pipe)));
770
771 seq_printf(m, "Master IER:\t%08x\n",
772 I915_READ(VLV_MASTER_IER));
773
774 seq_printf(m, "Render IER:\t%08x\n",
775 I915_READ(GTIER));
776 seq_printf(m, "Render IIR:\t%08x\n",
777 I915_READ(GTIIR));
778 seq_printf(m, "Render IMR:\t%08x\n",
779 I915_READ(GTIMR));
780
781 seq_printf(m, "PM IER:\t\t%08x\n",
782 I915_READ(GEN6_PMIER));
783 seq_printf(m, "PM IIR:\t\t%08x\n",
784 I915_READ(GEN6_PMIIR));
785 seq_printf(m, "PM IMR:\t\t%08x\n",
786 I915_READ(GEN6_PMIMR));
787
788 seq_printf(m, "Port hotplug:\t%08x\n",
789 I915_READ(PORT_HOTPLUG_EN));
790 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
791 I915_READ(VLV_DPFLIPSTAT));
792 seq_printf(m, "DPINVGTT:\t%08x\n",
793 I915_READ(DPINVGTT));
794
795 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 796 seq_printf(m, "Interrupt enable: %08x\n",
797 I915_READ(IER));
798 seq_printf(m, "Interrupt identity: %08x\n",
799 I915_READ(IIR));
800 seq_printf(m, "Interrupt mask: %08x\n",
801 I915_READ(IMR));
055e393f 802 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 803 seq_printf(m, "Pipe %c stat: %08x\n",
804 pipe_name(pipe),
805 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 806 } else {
807 seq_printf(m, "North Display Interrupt enable: %08x\n",
808 I915_READ(DEIER));
809 seq_printf(m, "North Display Interrupt identity: %08x\n",
810 I915_READ(DEIIR));
811 seq_printf(m, "North Display Interrupt mask: %08x\n",
812 I915_READ(DEIMR));
813 seq_printf(m, "South Display Interrupt enable: %08x\n",
814 I915_READ(SDEIER));
815 seq_printf(m, "South Display Interrupt identity: %08x\n",
816 I915_READ(SDEIIR));
817 seq_printf(m, "South Display Interrupt mask: %08x\n",
818 I915_READ(SDEIMR));
819 seq_printf(m, "Graphics Interrupt enable: %08x\n",
820 I915_READ(GTIER));
821 seq_printf(m, "Graphics Interrupt identity: %08x\n",
822 I915_READ(GTIIR));
823 seq_printf(m, "Graphics Interrupt mask: %08x\n",
824 I915_READ(GTIMR));
825 }
a2c7f6fd 826 for_each_ring(ring, dev_priv, i) {
a123f157 827 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 828 seq_printf(m,
829 "Graphics Interrupt mask (%s): %08x\n",
830 ring->name, I915_READ_IMR(ring));
9862e600 831 }
a2c7f6fd 832 i915_ring_seqno_info(m, ring);
9862e600 833 }
c8c8fb33 834 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 835 mutex_unlock(&dev->struct_mutex);
836
2017263e
BG		 837 return 0;
838}
839
a6172a80
CW		 840static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
841{
9f25d007 842 struct drm_info_node *node = m->private;
a6172a80 843 struct drm_device *dev = node->minor->dev;
e277a1f8 844 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 845 int i, ret;
846
847 ret = mutex_lock_interruptible(&dev->struct_mutex);
848 if (ret)
849 return ret;
a6172a80
CW		 850
851 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
852 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
853 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 854 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 855
6c085a72
CW		 856 seq_printf(m, "Fence %d, pin count = %d, object = ",
857 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 858 if (obj == NULL)
267f0c90 859 seq_puts(m, "unused");
c2c347a9 860 else
05394f39 861 describe_obj(m, obj);
267f0c90 862 seq_putc(m, '\n');
a6172a80
CW		 863 }
864
05394f39 865 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 866 return 0;
867}
868
2017263e
BG		 869static int i915_hws_info(struct seq_file *m, void *data)
870{
9f25d007 871 struct drm_info_node *node = m->private;
2017263e 872 struct drm_device *dev = node->minor->dev;
e277a1f8 873 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 874 struct intel_engine_cs *ring;
1a240d4d 875 const u32 *hws;
4066c0ae
CW		 876 int i;
877
1ec14ad3 878 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 879 hws = ring->status_page.page_addr;
2017263e
BG		 880 if (hws == NULL)
881 return 0;
882
883 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
884 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
885 i * 4,
886 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
887 }
888 return 0;
889}
890
d5442303
DV		 891static ssize_t
892i915_error_state_write(struct file *filp,
893 const char __user *ubuf,
894 size_t cnt,
895 loff_t *ppos)
896{
edc3d884 897 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 898 struct drm_device *dev = error_priv->dev;
22bcfc6a 899 int ret;
d5442303
DV		 900
901 DRM_DEBUG_DRIVER("Resetting error state\n");
902
22bcfc6a
DV		 903 ret = mutex_lock_interruptible(&dev->struct_mutex);
904 if (ret)
905 return ret;
906
d5442303
DV		 907 i915_destroy_error_state(dev);
908 mutex_unlock(&dev->struct_mutex);
909
910 return cnt;
911}
912
913static int i915_error_state_open(struct inode *inode, struct file *file)
914{
915 struct drm_device *dev = inode->i_private;
d5442303 916 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 917
918 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
919 if (!error_priv)
920 return -ENOMEM;
921
922 error_priv->dev = dev;
923
95d5bfb3 924 i915_error_state_get(dev, error_priv);
d5442303 925
edc3d884
MK		 926 file->private_data = error_priv;
927
928 return 0;
d5442303
DV		 929}
930
931static int i915_error_state_release(struct inode *inode, struct file *file)
932{
edc3d884 933 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 934
95d5bfb3 935 i915_error_state_put(error_priv);
d5442303
DV		 936 kfree(error_priv);
937
edc3d884
MK		 938 return 0;
939}
940
4dc955f7
MK		 941static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
942 size_t count, loff_t *pos)
943{
944 struct i915_error_state_file_priv *error_priv = file->private_data;
945 struct drm_i915_error_state_buf error_str;
946 loff_t tmp_pos = 0;
947 ssize_t ret_count = 0;
948 int ret;
949
0a4cd7c8 950 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 951 if (ret)
952 return ret;
edc3d884 953
fc16b48b 954 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 955 if (ret)
956 goto out;
957
edc3d884
MK		 958 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
959 error_str.buf,
960 error_str.bytes);
961
962 if (ret_count < 0)
963 ret = ret_count;
964 else
965 *pos = error_str.start + ret_count;
966out:
4dc955f7 967 i915_error_state_buf_release(&error_str);
edc3d884 968 return ret ?: ret_count;
d5442303
DV		 969}
970
971static const struct file_operations i915_error_state_fops = {
972 .owner = THIS_MODULE,
973 .open = i915_error_state_open,
edc3d884 974 .read = i915_error_state_read,
d5442303
DV		 975 .write = i915_error_state_write,
976 .llseek = default_llseek,
977 .release = i915_error_state_release,
978};
979
647416f9
KC		 980static int
981i915_next_seqno_get(void *data, u64 *val)
40633219 982{
647416f9 983 struct drm_device *dev = data;
e277a1f8 984 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 985 int ret;
986
987 ret = mutex_lock_interruptible(&dev->struct_mutex);
988 if (ret)
989 return ret;
990
647416f9 991 *val = dev_priv->next_seqno;
40633219
MK		 992 mutex_unlock(&dev->struct_mutex);
993
647416f9 994 return 0;
40633219
MK		 995}
996
647416f9
KC		 997static int
998i915_next_seqno_set(void *data, u64 val)
999{
1000 struct drm_device *dev = data;
40633219
MK		 1001 int ret;
1002
40633219
MK		 1003 ret = mutex_lock_interruptible(&dev->struct_mutex);
1004 if (ret)
1005 return ret;
1006
e94fbaa8 1007 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1008 mutex_unlock(&dev->struct_mutex);
1009
647416f9 1010 return ret;
40633219
MK		 1011}
1012
647416f9
KC		 1013DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1014 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1015 "0x%llx\n");
40633219 1016
adb4bd12 1017static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1018{
9f25d007 1019 struct drm_info_node *node = m->private;
f97108d1 1020 struct drm_device *dev = node->minor->dev;
e277a1f8 1021 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1022 int ret = 0;
1023
1024 intel_runtime_pm_get(dev_priv);
3b8d8d91 1025
5c9669ce
TR		 1026 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1027
3b8d8d91
JB		 1028 if (IS_GEN5(dev)) {
1029 u16 rgvswctl = I915_READ16(MEMSWCTL);
1030 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1031
1032 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1033 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1034 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1035 MEMSTAT_VID_SHIFT);
1036 seq_printf(m, "Current P-state: %d\n",
1037 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1038 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1039 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1040 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1041 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1042 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1043 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1044 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1045 u32 rpupei, rpcurup, rpprevup;
1046 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1047 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1048 int max_freq;
1049
1050 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1051 ret = mutex_lock_interruptible(&dev->struct_mutex);
1052 if (ret)
c8c8fb33 1053 goto out;
d1ebd816 1054
c8d9a590 1055 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1056
8e8c06cd
CW		 1057 reqf = I915_READ(GEN6_RPNSWREQ);
1058 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1059 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1060 reqf >>= 24;
1061 else
1062 reqf >>= 25;
1063 reqf *= GT_FREQUENCY_MULTIPLIER;
1064
0d8f9491
CW		 1065 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1066 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1067 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1068
ccab5c82
JB		 1069 rpstat = I915_READ(GEN6_RPSTAT1);
1070 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1071 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1072 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1073 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1074 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1075 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1076 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1077 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1078 else
1079 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1080 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1081
c8d9a590 1082 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1083 mutex_unlock(&dev->struct_mutex);
1084
9dd3c605
PZ		 1085 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1086 pm_ier = I915_READ(GEN6_PMIER);
1087 pm_imr = I915_READ(GEN6_PMIMR);
1088 pm_isr = I915_READ(GEN6_PMISR);
1089 pm_iir = I915_READ(GEN6_PMIIR);
1090 pm_mask = I915_READ(GEN6_PMINTRMSK);
1091 } else {
1092 pm_ier = I915_READ(GEN8_GT_IER(2));
1093 pm_imr = I915_READ(GEN8_GT_IMR(2));
1094 pm_isr = I915_READ(GEN8_GT_ISR(2));
1095 pm_iir = I915_READ(GEN8_GT_IIR(2));
1096 pm_mask = I915_READ(GEN6_PMINTRMSK);
1097 }
0d8f9491 1098 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1099 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1100 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1101 seq_printf(m, "Render p-state ratio: %d\n",
1102 (gt_perf_status & 0xff00) >> 8);
1103 seq_printf(m, "Render p-state VID: %d\n",
1104 gt_perf_status & 0xff);
1105 seq_printf(m, "Render p-state limit: %d\n",
1106 rp_state_limits & 0xff);
0d8f9491
CW		 1107 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1108 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1109 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1110 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1111 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1112 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1113 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1114 GEN6_CURICONT_MASK);
1115 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1116 GEN6_CURBSYTAVG_MASK);
1117 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1118 GEN6_CURBSYTAVG_MASK);
1119 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1120 GEN6_CURIAVG_MASK);
1121 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1122 GEN6_CURBSYTAVG_MASK);
1123 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1124 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1125
1126 max_freq = (rp_state_cap & 0xff0000) >> 16;
1127 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1128 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1129
1130 max_freq = (rp_state_cap & 0xff00) >> 8;
1131 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1132 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1133
1134 max_freq = rp_state_cap & 0xff;
1135 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1136 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1137
1138 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1139 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84 1140 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1141 u32 freq_sts;
0a073b84 1142
259bd5d4 1143 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1144 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1145 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1146 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1147
0a073b84 1148 seq_printf(m, "max GPU freq: %d MHz\n",
b2435c94 1149 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1150
0a073b84 1151 seq_printf(m, "min GPU freq: %d MHz\n",
b2435c94 1152 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045
VS		 1153
1154 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
b2435c94 1155 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1156
1157 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1158 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1159 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1160 } else {
267f0c90 1161 seq_puts(m, "no P-state info available\n");
3b8d8d91 1162 }
f97108d1 1163
c8c8fb33
PZ		 1164out:
1165 intel_runtime_pm_put(dev_priv);
1166 return ret;
f97108d1
JB		 1167}
1168
4d85529d 1169static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1170{
9f25d007 1171 struct drm_info_node *node = m->private;
f97108d1 1172 struct drm_device *dev = node->minor->dev;
e277a1f8 1173 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1174 u32 rgvmodectl, rstdbyctl;
1175 u16 crstandvid;
1176 int ret;
1177
1178 ret = mutex_lock_interruptible(&dev->struct_mutex);
1179 if (ret)
1180 return ret;
c8c8fb33 1181 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1182
1183 rgvmodectl = I915_READ(MEMMODECTL);
1184 rstdbyctl = I915_READ(RSTDBYCTL);
1185 crstandvid = I915_READ16(CRSTANDVID);
1186
c8c8fb33 1187 intel_runtime_pm_put(dev_priv);
616fdb5a 1188 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1189
1190 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1191 "yes" : "no");
1192 seq_printf(m, "Boost freq: %d\n",
1193 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1194 MEMMODE_BOOST_FREQ_SHIFT);
1195 seq_printf(m, "HW control enabled: %s\n",
1196 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1197 seq_printf(m, "SW control enabled: %s\n",
1198 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1199 seq_printf(m, "Gated voltage change: %s\n",
1200 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1201 seq_printf(m, "Starting frequency: P%d\n",
1202 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1203 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1204 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1205 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1206 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1207 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1208 seq_printf(m, "Render standby enabled: %s\n",
1209 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1210 seq_puts(m, "Current RS state: ");
88271da3
JB		 1211 switch (rstdbyctl & RSX_STATUS_MASK) {
1212 case RSX_STATUS_ON:
267f0c90 1213 seq_puts(m, "on\n");
88271da3
JB		 1214 break;
1215 case RSX_STATUS_RC1:
267f0c90 1216 seq_puts(m, "RC1\n");
88271da3
JB		 1217 break;
1218 case RSX_STATUS_RC1E:
267f0c90 1219 seq_puts(m, "RC1E\n");
88271da3
JB		 1220 break;
1221 case RSX_STATUS_RS1:
267f0c90 1222 seq_puts(m, "RS1\n");
88271da3
JB		 1223 break;
1224 case RSX_STATUS_RS2:
267f0c90 1225 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1226 break;
1227 case RSX_STATUS_RS3:
267f0c90 1228 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1229 break;
1230 default:
267f0c90 1231 seq_puts(m, "unknown\n");
88271da3
JB		 1232 break;
1233 }
f97108d1
JB		 1234
1235 return 0;
1236}
1237
669ab5aa
D		 1238static int vlv_drpc_info(struct seq_file *m)
1239{
1240
9f25d007 1241 struct drm_info_node *node = m->private;
669ab5aa
D		 1242 struct drm_device *dev = node->minor->dev;
1243 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1244 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa
D		 1245 unsigned fw_rendercount = 0, fw_mediacount = 0;
1246
d46c0517
ID		 1247 intel_runtime_pm_get(dev_priv);
1248
6b312cd3 1249 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1250 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1251 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1252
d46c0517
ID		 1253 intel_runtime_pm_put(dev_priv);
1254
669ab5aa
D		 1255 seq_printf(m, "Video Turbo Mode: %s\n",
1256 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1257 seq_printf(m, "Turbo enabled: %s\n",
1258 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1259 seq_printf(m, "HW control enabled: %s\n",
1260 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1261 seq_printf(m, "SW control enabled: %s\n",
1262 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1263 GEN6_RP_MEDIA_SW_MODE));
1264 seq_printf(m, "RC6 Enabled: %s\n",
1265 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1266 GEN6_RC_CTL_EI_MODE(1))));
1267 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1268 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1269 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1270 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1271
9cc19be5
ID		 1272 seq_printf(m, "Render RC6 residency since boot: %u\n",
1273 I915_READ(VLV_GT_RENDER_RC6));
1274 seq_printf(m, "Media RC6 residency since boot: %u\n",
1275 I915_READ(VLV_GT_MEDIA_RC6));
1276
669ab5aa
D		 1277 spin_lock_irq(&dev_priv->uncore.lock);
1278 fw_rendercount = dev_priv->uncore.fw_rendercount;
1279 fw_mediacount = dev_priv->uncore.fw_mediacount;
1280 spin_unlock_irq(&dev_priv->uncore.lock);
1281
1282 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1283 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1284
1285
1286 return 0;
1287}
1288
1289
4d85529d
BW		 1290static int gen6_drpc_info(struct seq_file *m)
1291{
1292
9f25d007 1293 struct drm_info_node *node = m->private;
4d85529d
BW		 1294 struct drm_device *dev = node->minor->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1296 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1297 unsigned forcewake_count;
aee56cff 1298 int count = 0, ret;
4d85529d
BW		 1299
1300 ret = mutex_lock_interruptible(&dev->struct_mutex);
1301 if (ret)
1302 return ret;
c8c8fb33 1303 intel_runtime_pm_get(dev_priv);
4d85529d 1304
907b28c5
CW		 1305 spin_lock_irq(&dev_priv->uncore.lock);
1306 forcewake_count = dev_priv->uncore.forcewake_count;
1307 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1308
1309 if (forcewake_count) {
267f0c90
DL		 1310 seq_puts(m, "RC information inaccurate because somebody "
1311 "holds a forcewake reference \n");
4d85529d
BW		 1312 } else {
1313 /* NB: we cannot use forcewake, else we read the wrong values */
1314 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1315 udelay(10);
1316 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1317 }
1318
1319 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1320 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1321
1322 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1323 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1324 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1325 mutex_lock(&dev_priv->rps.hw_lock);
1326 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1327 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1328
c8c8fb33
PZ		 1329 intel_runtime_pm_put(dev_priv);
1330
4d85529d
BW		 1331 seq_printf(m, "Video Turbo Mode: %s\n",
1332 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1333 seq_printf(m, "HW control enabled: %s\n",
1334 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1335 seq_printf(m, "SW control enabled: %s\n",
1336 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1337 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1338 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1339 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1340 seq_printf(m, "RC6 Enabled: %s\n",
1341 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1342 seq_printf(m, "Deep RC6 Enabled: %s\n",
1343 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1344 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1345 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1346 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1347 switch (gt_core_status & GEN6_RCn_MASK) {
1348 case GEN6_RC0:
1349 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1350 seq_puts(m, "Core Power Down\n");
4d85529d 1351 else
267f0c90 1352 seq_puts(m, "on\n");
4d85529d
BW		 1353 break;
1354 case GEN6_RC3:
267f0c90 1355 seq_puts(m, "RC3\n");
4d85529d
BW		 1356 break;
1357 case GEN6_RC6:
267f0c90 1358 seq_puts(m, "RC6\n");
4d85529d
BW		 1359 break;
1360 case GEN6_RC7:
267f0c90 1361 seq_puts(m, "RC7\n");
4d85529d
BW		 1362 break;
1363 default:
267f0c90 1364 seq_puts(m, "Unknown\n");
4d85529d
BW		 1365 break;
1366 }
1367
1368 seq_printf(m, "Core Power Down: %s\n",
1369 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1370
1371 /* Not exactly sure what this is */
1372 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1373 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1374 seq_printf(m, "RC6 residency since boot: %u\n",
1375 I915_READ(GEN6_GT_GFX_RC6));
1376 seq_printf(m, "RC6+ residency since boot: %u\n",
1377 I915_READ(GEN6_GT_GFX_RC6p));
1378 seq_printf(m, "RC6++ residency since boot: %u\n",
1379 I915_READ(GEN6_GT_GFX_RC6pp));
1380
ecd8faea
BW		 1381 seq_printf(m, "RC6 voltage: %dmV\n",
1382 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1383 seq_printf(m, "RC6+ voltage: %dmV\n",
1384 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1385 seq_printf(m, "RC6++ voltage: %dmV\n",
1386 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1387 return 0;
1388}
1389
1390static int i915_drpc_info(struct seq_file *m, void *unused)
1391{
9f25d007 1392 struct drm_info_node *node = m->private;
4d85529d
BW		 1393 struct drm_device *dev = node->minor->dev;
1394
669ab5aa
D		 1395 if (IS_VALLEYVIEW(dev))
1396 return vlv_drpc_info(m);
ac66cf4b 1397 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1398 return gen6_drpc_info(m);
1399 else
1400 return ironlake_drpc_info(m);
1401}
1402
b5e50c3f
JB		 1403static int i915_fbc_status(struct seq_file *m, void *unused)
1404{
9f25d007 1405 struct drm_info_node *node = m->private;
b5e50c3f 1406 struct drm_device *dev = node->minor->dev;
e277a1f8 1407 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1408
3a77c4c4 1409 if (!HAS_FBC(dev)) {
267f0c90 1410 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1411 return 0;
1412 }
1413
36623ef8
PZ		 1414 intel_runtime_pm_get(dev_priv);
1415
ee5382ae 1416 if (intel_fbc_enabled(dev)) {
267f0c90 1417 seq_puts(m, "FBC enabled\n");
b5e50c3f 1418 } else {
267f0c90 1419 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1420 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1421 case FBC_OK:
1422 seq_puts(m, "FBC actived, but currently disabled in hardware");
1423 break;
1424 case FBC_UNSUPPORTED:
1425 seq_puts(m, "unsupported by this chipset");
1426 break;
bed4a673 1427 case FBC_NO_OUTPUT:
267f0c90 1428 seq_puts(m, "no outputs");
bed4a673 1429 break;
b5e50c3f 1430 case FBC_STOLEN_TOO_SMALL:
267f0c90 1431 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1432 break;
1433 case FBC_UNSUPPORTED_MODE:
267f0c90 1434 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1435 break;
1436 case FBC_MODE_TOO_LARGE:
267f0c90 1437 seq_puts(m, "mode too large");
b5e50c3f
JB		 1438 break;
1439 case FBC_BAD_PLANE:
267f0c90 1440 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1441 break;
1442 case FBC_NOT_TILED:
267f0c90 1443 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1444 break;
9c928d16 1445 case FBC_MULTIPLE_PIPES:
267f0c90 1446 seq_puts(m, "multiple pipes are enabled");
9c928d16 1447 break;
c1a9f047 1448 case FBC_MODULE_PARAM:
267f0c90 1449 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1450 break;
8a5729a3 1451 case FBC_CHIP_DEFAULT:
267f0c90 1452 seq_puts(m, "disabled per chip default");
8a5729a3 1453 break;
b5e50c3f 1454 default:
267f0c90 1455 seq_puts(m, "unknown reason");
b5e50c3f 1456 }
267f0c90 1457 seq_putc(m, '\n');
b5e50c3f 1458 }
36623ef8
PZ		 1459
1460 intel_runtime_pm_put(dev_priv);
1461
b5e50c3f
JB		 1462 return 0;
1463}
1464
da46f936
RV		 1465static int i915_fbc_fc_get(void *data, u64 *val)
1466{
1467 struct drm_device *dev = data;
1468 struct drm_i915_private *dev_priv = dev->dev_private;
1469
1470 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1471 return -ENODEV;
1472
1473 drm_modeset_lock_all(dev);
1474 *val = dev_priv->fbc.false_color;
1475 drm_modeset_unlock_all(dev);
1476
1477 return 0;
1478}
1479
1480static int i915_fbc_fc_set(void *data, u64 val)
1481{
1482 struct drm_device *dev = data;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 u32 reg;
1485
1486 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1487 return -ENODEV;
1488
1489 drm_modeset_lock_all(dev);
1490
1491 reg = I915_READ(ILK_DPFC_CONTROL);
1492 dev_priv->fbc.false_color = val;
1493
1494 I915_WRITE(ILK_DPFC_CONTROL, val ?
1495 (reg | FBC_CTL_FALSE_COLOR) :
1496 (reg & ~FBC_CTL_FALSE_COLOR));
1497
1498 drm_modeset_unlock_all(dev);
1499 return 0;
1500}
1501
1502DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1503 i915_fbc_fc_get, i915_fbc_fc_set,
1504 "%llu\n");
1505
92d44621
PZ		 1506static int i915_ips_status(struct seq_file *m, void *unused)
1507{
9f25d007 1508 struct drm_info_node *node = m->private;
92d44621
PZ		 1509 struct drm_device *dev = node->minor->dev;
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511
f5adf94e 1512 if (!HAS_IPS(dev)) {
92d44621
PZ		 1513 seq_puts(m, "not supported\n");
1514 return 0;
1515 }
1516
36623ef8
PZ		 1517 intel_runtime_pm_get(dev_priv);
1518
0eaa53f0
RV		 1519 seq_printf(m, "Enabled by kernel parameter: %s\n",
1520 yesno(i915.enable_ips));
1521
1522 if (INTEL_INFO(dev)->gen >= 8) {
1523 seq_puts(m, "Currently: unknown\n");
1524 } else {
1525 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1526 seq_puts(m, "Currently: enabled\n");
1527 else
1528 seq_puts(m, "Currently: disabled\n");
1529 }
92d44621 1530
36623ef8
PZ		 1531 intel_runtime_pm_put(dev_priv);
1532
92d44621
PZ		 1533 return 0;
1534}
1535
4a9bef37
JB		 1536static int i915_sr_status(struct seq_file *m, void *unused)
1537{
9f25d007 1538 struct drm_info_node *node = m->private;
4a9bef37 1539 struct drm_device *dev = node->minor->dev;
e277a1f8 1540 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1541 bool sr_enabled = false;
1542
36623ef8
PZ		 1543 intel_runtime_pm_get(dev_priv);
1544
1398261a 1545 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1546 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1547 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1548 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1549 else if (IS_I915GM(dev))
1550 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1551 else if (IS_PINEVIEW(dev))
1552 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1553
36623ef8
PZ		 1554 intel_runtime_pm_put(dev_priv);
1555
5ba2aaaa
CW		 1556 seq_printf(m, "self-refresh: %s\n",
1557 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1558
1559 return 0;
1560}
1561
7648fa99
JB		 1562static int i915_emon_status(struct seq_file *m, void *unused)
1563{
9f25d007 1564 struct drm_info_node *node = m->private;
7648fa99 1565 struct drm_device *dev = node->minor->dev;
e277a1f8 1566 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1567 unsigned long temp, chipset, gfx;
de227ef0
CW		 1568 int ret;
1569
582be6b4
CW		 1570 if (!IS_GEN5(dev))
1571 return -ENODEV;
1572
de227ef0
CW		 1573 ret = mutex_lock_interruptible(&dev->struct_mutex);
1574 if (ret)
1575 return ret;
7648fa99
JB		 1576
1577 temp = i915_mch_val(dev_priv);
1578 chipset = i915_chipset_val(dev_priv);
1579 gfx = i915_gfx_val(dev_priv);
de227ef0 1580 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1581
1582 seq_printf(m, "GMCH temp: %ld\n", temp);
1583 seq_printf(m, "Chipset power: %ld\n", chipset);
1584 seq_printf(m, "GFX power: %ld\n", gfx);
1585 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1586
1587 return 0;
1588}
1589
23b2f8bb
JB		 1590static int i915_ring_freq_table(struct seq_file *m, void *unused)
1591{
9f25d007 1592 struct drm_info_node *node = m->private;
23b2f8bb 1593 struct drm_device *dev = node->minor->dev;
e277a1f8 1594 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1595 int ret = 0;
23b2f8bb
JB		 1596 int gpu_freq, ia_freq;
1597
1c70c0ce 1598 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1599 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1600 return 0;
1601 }
1602
5bfa0199
PZ		 1603 intel_runtime_pm_get(dev_priv);
1604
5c9669ce
TR		 1605 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1606
4fc688ce 1607 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1608 if (ret)
5bfa0199 1609 goto out;
23b2f8bb 1610
267f0c90 1611 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1612
b39fb297
BW		 1613 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1614 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1615 gpu_freq++) {
42c0526c
BW		 1616 ia_freq = gpu_freq;
1617 sandybridge_pcode_read(dev_priv,
1618 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1619 &ia_freq);
3ebecd07
CW		 1620 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1621 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1622 ((ia_freq >> 0) & 0xff) * 100,
1623 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1624 }
1625
4fc688ce 1626 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1627
5bfa0199
PZ		 1628out:
1629 intel_runtime_pm_put(dev_priv);
1630 return ret;
23b2f8bb
JB		 1631}
1632
44834a67
CW		 1633static int i915_opregion(struct seq_file *m, void *unused)
1634{
9f25d007 1635 struct drm_info_node *node = m->private;
44834a67 1636 struct drm_device *dev = node->minor->dev;
e277a1f8 1637 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1638 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1639 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1640 int ret;
1641
0d38f009
DV		 1642 if (data == NULL)
1643 return -ENOMEM;
1644
44834a67
CW		 1645 ret = mutex_lock_interruptible(&dev->struct_mutex);
1646 if (ret)
0d38f009 1647 goto out;
44834a67 1648
0d38f009
DV		 1649 if (opregion->header) {
1650 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1651 seq_write(m, data, OPREGION_SIZE);
1652 }
44834a67
CW		 1653
1654 mutex_unlock(&dev->struct_mutex);
1655
0d38f009
DV		 1656out:
1657 kfree(data);
44834a67
CW		 1658 return 0;
1659}
1660
37811fcc
CW		 1661static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1662{
9f25d007 1663 struct drm_info_node *node = m->private;
37811fcc 1664 struct drm_device *dev = node->minor->dev;
4520f53a 1665 struct intel_fbdev *ifbdev = NULL;
37811fcc 1666 struct intel_framebuffer *fb;
37811fcc 1667
4520f53a
DV		 1668#ifdef CONFIG_DRM_I915_FBDEV
1669 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1670
1671 ifbdev = dev_priv->fbdev;
1672 fb = to_intel_framebuffer(ifbdev->helper.fb);
1673
623f9783 1674 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1675 fb->base.width,
1676 fb->base.height,
1677 fb->base.depth,
623f9783
DV		 1678 fb->base.bits_per_pixel,
1679 atomic_read(&fb->base.refcount.refcount));
05394f39 1680 describe_obj(m, fb->obj);
267f0c90 1681 seq_putc(m, '\n');
4520f53a 1682#endif
37811fcc 1683
4b096ac1 1684 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1685 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1686 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1687 continue;
1688
623f9783 1689 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1690 fb->base.width,
1691 fb->base.height,
1692 fb->base.depth,
623f9783
DV		 1693 fb->base.bits_per_pixel,
1694 atomic_read(&fb->base.refcount.refcount));
05394f39 1695 describe_obj(m, fb->obj);
267f0c90 1696 seq_putc(m, '\n');
37811fcc 1697 }
4b096ac1 1698 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1699
1700 return 0;
1701}
1702
c9fe99bd
OM		 1703static void describe_ctx_ringbuf(struct seq_file *m,
1704 struct intel_ringbuffer *ringbuf)
1705{
1706 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1707 ringbuf->space, ringbuf->head, ringbuf->tail,
1708 ringbuf->last_retired_head);
1709}
1710
e76d3630
BW		 1711static int i915_context_status(struct seq_file *m, void *unused)
1712{
9f25d007 1713 struct drm_info_node *node = m->private;
e76d3630 1714 struct drm_device *dev = node->minor->dev;
e277a1f8 1715 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1716 struct intel_engine_cs *ring;
273497e5 1717 struct intel_context *ctx;
a168c293 1718 int ret, i;
e76d3630 1719
f3d28878 1720 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1721 if (ret)
1722 return ret;
1723
3e373948 1724 if (dev_priv->ips.pwrctx) {
267f0c90 1725 seq_puts(m, "power context ");
3e373948 1726 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1727 seq_putc(m, '\n');
dc501fbc 1728 }
e76d3630 1729
3e373948 1730 if (dev_priv->ips.renderctx) {
267f0c90 1731 seq_puts(m, "render context ");
3e373948 1732 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1733 seq_putc(m, '\n');
dc501fbc 1734 }
e76d3630 1735
a33afea5 1736 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1737 if (!i915.enable_execlists &&
1738 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1739 continue;
1740
a33afea5 1741 seq_puts(m, "HW context ");
3ccfd19d 1742 describe_ctx(m, ctx);
c9fe99bd 1743 for_each_ring(ring, dev_priv, i) {
a33afea5 1744 if (ring->default_context == ctx)
c9fe99bd
OM		 1745 seq_printf(m, "(default context %s) ",
1746 ring->name);
1747 }
1748
1749 if (i915.enable_execlists) {
1750 seq_putc(m, '\n');
1751 for_each_ring(ring, dev_priv, i) {
1752 struct drm_i915_gem_object *ctx_obj =
1753 ctx->engine[i].state;
1754 struct intel_ringbuffer *ringbuf =
1755 ctx->engine[i].ringbuf;
1756
1757 seq_printf(m, "%s: ", ring->name);
1758 if (ctx_obj)
1759 describe_obj(m, ctx_obj);
1760 if (ringbuf)
1761 describe_ctx_ringbuf(m, ringbuf);
1762 seq_putc(m, '\n');
1763 }
1764 } else {
1765 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1766 }
a33afea5 1767
a33afea5 1768 seq_putc(m, '\n');
a168c293
BW		 1769 }
1770
f3d28878 1771 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1772
1773 return 0;
1774}
1775
064ca1d2
TD		 1776static void i915_dump_lrc_obj(struct seq_file *m,
1777 struct intel_engine_cs *ring,
1778 struct drm_i915_gem_object *ctx_obj)
1779{
1780 struct page *page;
1781 uint32_t *reg_state;
1782 int j;
1783 unsigned long ggtt_offset = 0;
1784
1785 if (ctx_obj == NULL) {
1786 seq_printf(m, "Context on %s with no gem object\n",
1787 ring->name);
1788 return;
1789 }
1790
1791 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1792 intel_execlists_ctx_id(ctx_obj));
1793
1794 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1795 seq_puts(m, "\tNot bound in GGTT\n");
1796 else
1797 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1798
1799 if (i915_gem_object_get_pages(ctx_obj)) {
1800 seq_puts(m, "\tFailed to get pages for context object\n");
1801 return;
1802 }
1803
1804 page = i915_gem_object_get_page(ctx_obj, 1);
1805 if (!WARN_ON(page == NULL)) {
1806 reg_state = kmap_atomic(page);
1807
1808 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1809 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1810 ggtt_offset + 4096 + (j * 4),
1811 reg_state[j], reg_state[j + 1],
1812 reg_state[j + 2], reg_state[j + 3]);
1813 }
1814 kunmap_atomic(reg_state);
1815 }
1816
1817 seq_putc(m, '\n');
1818}
1819
c0ab1ae9
BW		 1820static int i915_dump_lrc(struct seq_file *m, void *unused)
1821{
1822 struct drm_info_node *node = (struct drm_info_node *) m->private;
1823 struct drm_device *dev = node->minor->dev;
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 struct intel_engine_cs *ring;
1826 struct intel_context *ctx;
1827 int ret, i;
1828
1829 if (!i915.enable_execlists) {
1830 seq_printf(m, "Logical Ring Contexts are disabled\n");
1831 return 0;
1832 }
1833
1834 ret = mutex_lock_interruptible(&dev->struct_mutex);
1835 if (ret)
1836 return ret;
1837
1838 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1839 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1840 if (ring->default_context != ctx)
1841 i915_dump_lrc_obj(m, ring,
1842 ctx->engine[i].state);
c0ab1ae9
BW		 1843 }
1844 }
1845
1846 mutex_unlock(&dev->struct_mutex);
1847
1848 return 0;
1849}
1850
4ba70e44
OM		 1851static int i915_execlists(struct seq_file *m, void *data)
1852{
1853 struct drm_info_node *node = (struct drm_info_node *)m->private;
1854 struct drm_device *dev = node->minor->dev;
1855 struct drm_i915_private *dev_priv = dev->dev_private;
1856 struct intel_engine_cs *ring;
1857 u32 status_pointer;
1858 u8 read_pointer;
1859 u8 write_pointer;
1860 u32 status;
1861 u32 ctx_id;
1862 struct list_head *cursor;
1863 int ring_id, i;
1864 int ret;
1865
1866 if (!i915.enable_execlists) {
1867 seq_puts(m, "Logical Ring Contexts are disabled\n");
1868 return 0;
1869 }
1870
1871 ret = mutex_lock_interruptible(&dev->struct_mutex);
1872 if (ret)
1873 return ret;
1874
fc0412ec
MT		 1875 intel_runtime_pm_get(dev_priv);
1876
4ba70e44
OM		 1877 for_each_ring(ring, dev_priv, ring_id) {
1878 struct intel_ctx_submit_request *head_req = NULL;
1879 int count = 0;
1880 unsigned long flags;
1881
1882 seq_printf(m, "%s\n", ring->name);
1883
1884 status = I915_READ(RING_EXECLIST_STATUS(ring));
1885 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1886 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1887 status, ctx_id);
1888
1889 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1890 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1891
1892 read_pointer = ring->next_context_status_buffer;
1893 write_pointer = status_pointer & 0x07;
1894 if (read_pointer > write_pointer)
1895 write_pointer += 6;
1896 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1897 read_pointer, write_pointer);
1898
1899 for (i = 0; i < 6; i++) {
1900 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1901 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1902
1903 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1904 i, status, ctx_id);
1905 }
1906
1907 spin_lock_irqsave(&ring->execlist_lock, flags);
1908 list_for_each(cursor, &ring->execlist_queue)
1909 count++;
1910 head_req = list_first_entry_or_null(&ring->execlist_queue,
1911 struct intel_ctx_submit_request, execlist_link);
1912 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1913
1914 seq_printf(m, "\t%d requests in queue\n", count);
1915 if (head_req) {
1916 struct drm_i915_gem_object *ctx_obj;
1917
1918 ctx_obj = head_req->ctx->engine[ring_id].state;
1919 seq_printf(m, "\tHead request id: %u\n",
1920 intel_execlists_ctx_id(ctx_obj));
1921 seq_printf(m, "\tHead request tail: %u\n",
1922 head_req->tail);
1923 }
1924
1925 seq_putc(m, '\n');
1926 }
1927
fc0412ec 1928 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 1929 mutex_unlock(&dev->struct_mutex);
1930
1931 return 0;
1932}
1933
6d794d42
BW		 1934static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1935{
9f25d007 1936 struct drm_info_node *node = m->private;
6d794d42
BW		 1937 struct drm_device *dev = node->minor->dev;
1938 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1939 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1940
907b28c5 1941 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1942 if (IS_VALLEYVIEW(dev)) {
1943 fw_rendercount = dev_priv->uncore.fw_rendercount;
1944 fw_mediacount = dev_priv->uncore.fw_mediacount;
1945 } else
1946 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1947 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1948
43709ba0
D		 1949 if (IS_VALLEYVIEW(dev)) {
1950 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1951 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1952 } else
1953 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1954
1955 return 0;
1956}
1957
ea16a3cd
DV		 1958static const char *swizzle_string(unsigned swizzle)
1959{
aee56cff 1960 switch (swizzle) {
ea16a3cd
DV		 1961 case I915_BIT_6_SWIZZLE_NONE:
1962 return "none";
1963 case I915_BIT_6_SWIZZLE_9:
1964 return "bit9";
1965 case I915_BIT_6_SWIZZLE_9_10:
1966 return "bit9/bit10";
1967 case I915_BIT_6_SWIZZLE_9_11:
1968 return "bit9/bit11";
1969 case I915_BIT_6_SWIZZLE_9_10_11:
1970 return "bit9/bit10/bit11";
1971 case I915_BIT_6_SWIZZLE_9_17:
1972 return "bit9/bit17";
1973 case I915_BIT_6_SWIZZLE_9_10_17:
1974 return "bit9/bit10/bit17";
1975 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1976 return "unknown";
ea16a3cd
DV		 1977 }
1978
1979 return "bug";
1980}
1981
1982static int i915_swizzle_info(struct seq_file *m, void *data)
1983{
9f25d007 1984 struct drm_info_node *node = m->private;
ea16a3cd
DV		 1985 struct drm_device *dev = node->minor->dev;
1986 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1987 int ret;
1988
1989 ret = mutex_lock_interruptible(&dev->struct_mutex);
1990 if (ret)
1991 return ret;
c8c8fb33 1992 intel_runtime_pm_get(dev_priv);
ea16a3cd 1993
ea16a3cd
DV		 1994 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1995 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1996 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1997 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1998
1999 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2000 seq_printf(m, "DDC = 0x%08x\n",
2001 I915_READ(DCC));
656bfa3a
DV		 2002 seq_printf(m, "DDC2 = 0x%08x\n",
2003 I915_READ(DCC2));
ea16a3cd
DV		 2004 seq_printf(m, "C0DRB3 = 0x%04x\n",
2005 I915_READ16(C0DRB3));
2006 seq_printf(m, "C1DRB3 = 0x%04x\n",
2007 I915_READ16(C1DRB3));
9d3203e1 2008 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2009 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2010 I915_READ(MAD_DIMM_C0));
2011 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2012 I915_READ(MAD_DIMM_C1));
2013 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2014 I915_READ(MAD_DIMM_C2));
2015 seq_printf(m, "TILECTL = 0x%08x\n",
2016 I915_READ(TILECTL));
5907f5fb 2017 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2018 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2019 I915_READ(GAMTARBMODE));
2020 else
2021 seq_printf(m, "ARB_MODE = 0x%08x\n",
2022 I915_READ(ARB_MODE));
3fa7d235
DV		 2023 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2024 I915_READ(DISP_ARB_CTL));
ea16a3cd 2025 }
656bfa3a
DV		 2026
2027 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2028 seq_puts(m, "L-shaped memory detected\n");
2029
c8c8fb33 2030 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2031 mutex_unlock(&dev->struct_mutex);
2032
2033 return 0;
2034}
2035
1c60fef5
BW		 2036static int per_file_ctx(int id, void *ptr, void *data)
2037{
273497e5 2038 struct intel_context *ctx = ptr;
1c60fef5 2039 struct seq_file *m = data;
ae6c4806
DV		 2040 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2041
2042 if (!ppgtt) {
2043 seq_printf(m, " no ppgtt for context %d\n",
2044 ctx->user_handle);
2045 return 0;
2046 }
1c60fef5 2047
f83d6518
OM		 2048 if (i915_gem_context_is_default(ctx))
2049 seq_puts(m, " default context:\n");
2050 else
821d66dd 2051 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2052 ppgtt->debug_dump(ppgtt, m);
2053
2054 return 0;
2055}
2056
77df6772 2057static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2058{
3cf17fc5 2059 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2060 struct intel_engine_cs *ring;
77df6772
BW		 2061 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2062 int unused, i;
3cf17fc5 2063
77df6772
BW		 2064 if (!ppgtt)
2065 return;
2066
2067 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2068 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2069 for_each_ring(ring, dev_priv, unused) {
2070 seq_printf(m, "%s\n", ring->name);
2071 for (i = 0; i < 4; i++) {
2072 u32 offset = 0x270 + i * 8;
2073 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2074 pdp <<= 32;
2075 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2076 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2077 }
2078 }
2079}
2080
2081static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2082{
2083 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2084 struct intel_engine_cs *ring;
1c60fef5 2085 struct drm_file *file;
77df6772 2086 int i;
3cf17fc5 2087
3cf17fc5
DV		 2088 if (INTEL_INFO(dev)->gen == 6)
2089 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2090
a2c7f6fd 2091 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2092 seq_printf(m, "%s\n", ring->name);
2093 if (INTEL_INFO(dev)->gen == 7)
2094 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2095 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2096 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2097 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2098 }
2099 if (dev_priv->mm.aliasing_ppgtt) {
2100 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2101
267f0c90 2102 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 2103 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 2104
87d60b63 2105 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2106 }
1c60fef5
BW		 2107
2108 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2109 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2110
1c60fef5
BW		 2111 seq_printf(m, "proc: %s\n",
2112 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2113 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2114 }
2115 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2116}
2117
2118static int i915_ppgtt_info(struct seq_file *m, void *data)
2119{
9f25d007 2120 struct drm_info_node *node = m->private;
77df6772 2121 struct drm_device *dev = node->minor->dev;
c8c8fb33 2122 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2123
2124 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2125 if (ret)
2126 return ret;
c8c8fb33 2127 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2128
2129 if (INTEL_INFO(dev)->gen >= 8)
2130 gen8_ppgtt_info(m, dev);
2131 else if (INTEL_INFO(dev)->gen >= 6)
2132 gen6_ppgtt_info(m, dev);
2133
c8c8fb33 2134 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2135 mutex_unlock(&dev->struct_mutex);
2136
2137 return 0;
2138}
2139
63573eb7
BW		 2140static int i915_llc(struct seq_file *m, void *data)
2141{
9f25d007 2142 struct drm_info_node *node = m->private;
63573eb7
BW		 2143 struct drm_device *dev = node->minor->dev;
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2145
2146 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2147 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2148 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2149
2150 return 0;
2151}
2152
e91fd8c6
RV		 2153static int i915_edp_psr_status(struct seq_file *m, void *data)
2154{
2155 struct drm_info_node *node = m->private;
2156 struct drm_device *dev = node->minor->dev;
2157 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2158 u32 psrperf = 0;
a6cbdb8e
RV		 2159 u32 stat[3];
2160 enum pipe pipe;
a031d709 2161 bool enabled = false;
e91fd8c6 2162
c8c8fb33
PZ		 2163 intel_runtime_pm_get(dev_priv);
2164
fa128fa6 2165 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2166 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2167 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2168 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2169 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2170 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2171 dev_priv->psr.busy_frontbuffer_bits);
2172 seq_printf(m, "Re-enable work scheduled: %s\n",
2173 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2174
a6cbdb8e
RV		 2175 if (HAS_PSR(dev)) {
2176 if (HAS_DDI(dev))
2177 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2178 else {
2179 for_each_pipe(dev_priv, pipe) {
2180 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2181 VLV_EDP_PSR_CURR_STATE_MASK;
2182 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2183 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2184 enabled = true;
2185 }
2186 }
2187 }
2188 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2189
2190 if (!HAS_DDI(dev))
2191 for_each_pipe(dev_priv, pipe) {
2192 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2193 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2194 seq_printf(m, " pipe %c", pipe_name(pipe));
2195 }
2196 seq_puts(m, "\n");
e91fd8c6 2197
a6cbdb8e
RV		 2198 /* CHV PSR has no kind of performance counter */
2199 if (HAS_PSR(dev) && HAS_DDI(dev)) {
a031d709
RV		 2200 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2201 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2202
2203 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2204 }
fa128fa6 2205 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2206
c8c8fb33 2207 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2208 return 0;
2209}
2210
d2e216d0
RV		 2211static int i915_sink_crc(struct seq_file *m, void *data)
2212{
2213 struct drm_info_node *node = m->private;
2214 struct drm_device *dev = node->minor->dev;
2215 struct intel_encoder *encoder;
2216 struct intel_connector *connector;
2217 struct intel_dp *intel_dp = NULL;
2218 int ret;
2219 u8 crc[6];
2220
2221 drm_modeset_lock_all(dev);
2222 list_for_each_entry(connector, &dev->mode_config.connector_list,
2223 base.head) {
2224
2225 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2226 continue;
2227
b6ae3c7c
PZ		 2228 if (!connector->base.encoder)
2229 continue;
2230
d2e216d0
RV		 2231 encoder = to_intel_encoder(connector->base.encoder);
2232 if (encoder->type != INTEL_OUTPUT_EDP)
2233 continue;
2234
2235 intel_dp = enc_to_intel_dp(&encoder->base);
2236
2237 ret = intel_dp_sink_crc(intel_dp, crc);
2238 if (ret)
2239 goto out;
2240
2241 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2242 crc[0], crc[1], crc[2],
2243 crc[3], crc[4], crc[5]);
2244 goto out;
2245 }
2246 ret = -ENODEV;
2247out:
2248 drm_modeset_unlock_all(dev);
2249 return ret;
2250}
2251
ec013e7f
JB		 2252static int i915_energy_uJ(struct seq_file *m, void *data)
2253{
2254 struct drm_info_node *node = m->private;
2255 struct drm_device *dev = node->minor->dev;
2256 struct drm_i915_private *dev_priv = dev->dev_private;
2257 u64 power;
2258 u32 units;
2259
2260 if (INTEL_INFO(dev)->gen < 6)
2261 return -ENODEV;
2262
36623ef8
PZ		 2263 intel_runtime_pm_get(dev_priv);
2264
ec013e7f
JB		 2265 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2266 power = (power & 0x1f00) >> 8;
2267 units = 1000000 / (1 << power); /* convert to uJ */
2268 power = I915_READ(MCH_SECP_NRG_STTS);
2269 power *= units;
2270
36623ef8
PZ		 2271 intel_runtime_pm_put(dev_priv);
2272
ec013e7f 2273 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2274
2275 return 0;
2276}
2277
2278static int i915_pc8_status(struct seq_file *m, void *unused)
2279{
9f25d007 2280 struct drm_info_node *node = m->private;
371db66a
PZ		 2281 struct drm_device *dev = node->minor->dev;
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283
85b8d5c2 2284 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2285 seq_puts(m, "not supported\n");
2286 return 0;
2287 }
2288
86c4ec0d 2289 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2290 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2291 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2292
ec013e7f
JB		 2293 return 0;
2294}
2295
1da51581
ID		 2296static const char *power_domain_str(enum intel_display_power_domain domain)
2297{
2298 switch (domain) {
2299 case POWER_DOMAIN_PIPE_A:
2300 return "PIPE_A";
2301 case POWER_DOMAIN_PIPE_B:
2302 return "PIPE_B";
2303 case POWER_DOMAIN_PIPE_C:
2304 return "PIPE_C";
2305 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2306 return "PIPE_A_PANEL_FITTER";
2307 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2308 return "PIPE_B_PANEL_FITTER";
2309 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2310 return "PIPE_C_PANEL_FITTER";
2311 case POWER_DOMAIN_TRANSCODER_A:
2312 return "TRANSCODER_A";
2313 case POWER_DOMAIN_TRANSCODER_B:
2314 return "TRANSCODER_B";
2315 case POWER_DOMAIN_TRANSCODER_C:
2316 return "TRANSCODER_C";
2317 case POWER_DOMAIN_TRANSCODER_EDP:
2318 return "TRANSCODER_EDP";
319be8ae
ID		 2319 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2320 return "PORT_DDI_A_2_LANES";
2321 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2322 return "PORT_DDI_A_4_LANES";
2323 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2324 return "PORT_DDI_B_2_LANES";
2325 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2326 return "PORT_DDI_B_4_LANES";
2327 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2328 return "PORT_DDI_C_2_LANES";
2329 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2330 return "PORT_DDI_C_4_LANES";
2331 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2332 return "PORT_DDI_D_2_LANES";
2333 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2334 return "PORT_DDI_D_4_LANES";
2335 case POWER_DOMAIN_PORT_DSI:
2336 return "PORT_DSI";
2337 case POWER_DOMAIN_PORT_CRT:
2338 return "PORT_CRT";
2339 case POWER_DOMAIN_PORT_OTHER:
2340 return "PORT_OTHER";
1da51581
ID		 2341 case POWER_DOMAIN_VGA:
2342 return "VGA";
2343 case POWER_DOMAIN_AUDIO:
2344 return "AUDIO";
bd2bb1b9
PZ		 2345 case POWER_DOMAIN_PLLS:
2346 return "PLLS";
1da51581
ID		 2347 case POWER_DOMAIN_INIT:
2348 return "INIT";
2349 default:
2350 WARN_ON(1);
2351 return "?";
2352 }
2353}
2354
2355static int i915_power_domain_info(struct seq_file *m, void *unused)
2356{
9f25d007 2357 struct drm_info_node *node = m->private;
1da51581
ID		 2358 struct drm_device *dev = node->minor->dev;
2359 struct drm_i915_private *dev_priv = dev->dev_private;
2360 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2361 int i;
2362
2363 mutex_lock(&power_domains->lock);
2364
2365 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2366 for (i = 0; i < power_domains->power_well_count; i++) {
2367 struct i915_power_well *power_well;
2368 enum intel_display_power_domain power_domain;
2369
2370 power_well = &power_domains->power_wells[i];
2371 seq_printf(m, "%-25s %d\n", power_well->name,
2372 power_well->count);
2373
2374 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2375 power_domain++) {
2376 if (!(BIT(power_domain) & power_well->domains))
2377 continue;
2378
2379 seq_printf(m, " %-23s %d\n",
2380 power_domain_str(power_domain),
2381 power_domains->domain_use_count[power_domain]);
2382 }
2383 }
2384
2385 mutex_unlock(&power_domains->lock);
2386
2387 return 0;
2388}
2389
53f5e3ca
JB		 2390static void intel_seq_print_mode(struct seq_file *m, int tabs,
2391 struct drm_display_mode *mode)
2392{
2393 int i;
2394
2395 for (i = 0; i < tabs; i++)
2396 seq_putc(m, '\t');
2397
2398 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2399 mode->base.id, mode->name,
2400 mode->vrefresh, mode->clock,
2401 mode->hdisplay, mode->hsync_start,
2402 mode->hsync_end, mode->htotal,
2403 mode->vdisplay, mode->vsync_start,
2404 mode->vsync_end, mode->vtotal,
2405 mode->type, mode->flags);
2406}
2407
2408static void intel_encoder_info(struct seq_file *m,
2409 struct intel_crtc *intel_crtc,
2410 struct intel_encoder *intel_encoder)
2411{
9f25d007 2412 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2413 struct drm_device *dev = node->minor->dev;
2414 struct drm_crtc *crtc = &intel_crtc->base;
2415 struct intel_connector *intel_connector;
2416 struct drm_encoder *encoder;
2417
2418 encoder = &intel_encoder->base;
2419 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2420 encoder->base.id, encoder->name);
53f5e3ca
JB		 2421 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2422 struct drm_connector *connector = &intel_connector->base;
2423 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2424 connector->base.id,
c23cc417 2425 connector->name,
53f5e3ca
JB		 2426 drm_get_connector_status_name(connector->status));
2427 if (connector->status == connector_status_connected) {
2428 struct drm_display_mode *mode = &crtc->mode;
2429 seq_printf(m, ", mode:\n");
2430 intel_seq_print_mode(m, 2, mode);
2431 } else {
2432 seq_putc(m, '\n');
2433 }
2434 }
2435}
2436
2437static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2438{
9f25d007 2439 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2440 struct drm_device *dev = node->minor->dev;
2441 struct drm_crtc *crtc = &intel_crtc->base;
2442 struct intel_encoder *intel_encoder;
2443
5aa8a937
MR		 2444 if (crtc->primary->fb)
2445 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2446 crtc->primary->fb->base.id, crtc->x, crtc->y,
2447 crtc->primary->fb->width, crtc->primary->fb->height);
2448 else
2449 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2450 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2451 intel_encoder_info(m, intel_crtc, intel_encoder);
2452}
2453
2454static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2455{
2456 struct drm_display_mode *mode = panel->fixed_mode;
2457
2458 seq_printf(m, "\tfixed mode:\n");
2459 intel_seq_print_mode(m, 2, mode);
2460}
2461
2462static void intel_dp_info(struct seq_file *m,
2463 struct intel_connector *intel_connector)
2464{
2465 struct intel_encoder *intel_encoder = intel_connector->encoder;
2466 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2467
2468 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2469 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2470 "no");
2471 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2472 intel_panel_info(m, &intel_connector->panel);
2473}
2474
2475static void intel_hdmi_info(struct seq_file *m,
2476 struct intel_connector *intel_connector)
2477{
2478 struct intel_encoder *intel_encoder = intel_connector->encoder;
2479 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2480
2481 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2482 "no");
2483}
2484
2485static void intel_lvds_info(struct seq_file *m,
2486 struct intel_connector *intel_connector)
2487{
2488 intel_panel_info(m, &intel_connector->panel);
2489}
2490
2491static void intel_connector_info(struct seq_file *m,
2492 struct drm_connector *connector)
2493{
2494 struct intel_connector *intel_connector = to_intel_connector(connector);
2495 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2496 struct drm_display_mode *mode;
53f5e3ca
JB		 2497
2498 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2499 connector->base.id, connector->name,
53f5e3ca
JB		 2500 drm_get_connector_status_name(connector->status));
2501 if (connector->status == connector_status_connected) {
2502 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2503 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2504 connector->display_info.width_mm,
2505 connector->display_info.height_mm);
2506 seq_printf(m, "\tsubpixel order: %s\n",
2507 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2508 seq_printf(m, "\tCEA rev: %d\n",
2509 connector->display_info.cea_rev);
2510 }
36cd7444
DA		 2511 if (intel_encoder) {
2512 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2513 intel_encoder->type == INTEL_OUTPUT_EDP)
2514 intel_dp_info(m, intel_connector);
2515 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2516 intel_hdmi_info(m, intel_connector);
2517 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2518 intel_lvds_info(m, intel_connector);
2519 }
53f5e3ca 2520
f103fc7d
JB		 2521 seq_printf(m, "\tmodes:\n");
2522 list_for_each_entry(mode, &connector->modes, head)
2523 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2524}
2525
065f2ec2
CW		 2526static bool cursor_active(struct drm_device *dev, int pipe)
2527{
2528 struct drm_i915_private *dev_priv = dev->dev_private;
2529 u32 state;
2530
2531 if (IS_845G(dev) || IS_I865G(dev))
2532 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2533 else
5efb3e28 2534 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2535
2536 return state;
2537}
2538
2539static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2540{
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542 u32 pos;
2543
5efb3e28 2544 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2545
2546 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2547 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2548 *x = -*x;
2549
2550 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2551 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2552 *y = -*y;
2553
2554 return cursor_active(dev, pipe);
2555}
2556
53f5e3ca
JB		 2557static int i915_display_info(struct seq_file *m, void *unused)
2558{
9f25d007 2559 struct drm_info_node *node = m->private;
53f5e3ca 2560 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2561 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2562 struct intel_crtc *crtc;
53f5e3ca
JB		 2563 struct drm_connector *connector;
2564
b0e5ddf3 2565 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2566 drm_modeset_lock_all(dev);
2567 seq_printf(m, "CRTC info\n");
2568 seq_printf(m, "---------\n");
d3fcc808 2569 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2570 bool active;
2571 int x, y;
53f5e3ca 2572
57127efa 2573 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2574 crtc->base.base.id, pipe_name(crtc->pipe),
57127efa 2575 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
a23dc658 2576 if (crtc->active) {
065f2ec2
CW		 2577 intel_crtc_info(m, crtc);
2578
a23dc658 2579 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2580 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2581 yesno(crtc->cursor_base),
57127efa
CW		 2582 x, y, crtc->cursor_width, crtc->cursor_height,
2583 crtc->cursor_addr, yesno(active));
a23dc658 2584 }
cace841c
DV		 2585
2586 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2587 yesno(!crtc->cpu_fifo_underrun_disabled),
2588 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2589 }
2590
2591 seq_printf(m, "\n");
2592 seq_printf(m, "Connector info\n");
2593 seq_printf(m, "--------------\n");
2594 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2595 intel_connector_info(m, connector);
2596 }
2597 drm_modeset_unlock_all(dev);
b0e5ddf3 2598 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2599
2600 return 0;
2601}
2602
e04934cf
BW		 2603static int i915_semaphore_status(struct seq_file *m, void *unused)
2604{
2605 struct drm_info_node *node = (struct drm_info_node *) m->private;
2606 struct drm_device *dev = node->minor->dev;
2607 struct drm_i915_private *dev_priv = dev->dev_private;
2608 struct intel_engine_cs *ring;
2609 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2610 int i, j, ret;
2611
2612 if (!i915_semaphore_is_enabled(dev)) {
2613 seq_puts(m, "Semaphores are disabled\n");
2614 return 0;
2615 }
2616
2617 ret = mutex_lock_interruptible(&dev->struct_mutex);
2618 if (ret)
2619 return ret;
03872064 2620 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2621
2622 if (IS_BROADWELL(dev)) {
2623 struct page *page;
2624 uint64_t *seqno;
2625
2626 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2627
2628 seqno = (uint64_t *)kmap_atomic(page);
2629 for_each_ring(ring, dev_priv, i) {
2630 uint64_t offset;
2631
2632 seq_printf(m, "%s\n", ring->name);
2633
2634 seq_puts(m, " Last signal:");
2635 for (j = 0; j < num_rings; j++) {
2636 offset = i * I915_NUM_RINGS + j;
2637 seq_printf(m, "0x%08llx (0x%02llx) ",
2638 seqno[offset], offset * 8);
2639 }
2640 seq_putc(m, '\n');
2641
2642 seq_puts(m, " Last wait: ");
2643 for (j = 0; j < num_rings; j++) {
2644 offset = i + (j * I915_NUM_RINGS);
2645 seq_printf(m, "0x%08llx (0x%02llx) ",
2646 seqno[offset], offset * 8);
2647 }
2648 seq_putc(m, '\n');
2649
2650 }
2651 kunmap_atomic(seqno);
2652 } else {
2653 seq_puts(m, " Last signal:");
2654 for_each_ring(ring, dev_priv, i)
2655 for (j = 0; j < num_rings; j++)
2656 seq_printf(m, "0x%08x\n",
2657 I915_READ(ring->semaphore.mbox.signal[j]));
2658 seq_putc(m, '\n');
2659 }
2660
2661 seq_puts(m, "\nSync seqno:\n");
2662 for_each_ring(ring, dev_priv, i) {
2663 for (j = 0; j < num_rings; j++) {
2664 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2665 }
2666 seq_putc(m, '\n');
2667 }
2668 seq_putc(m, '\n');
2669
03872064 2670 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2671 mutex_unlock(&dev->struct_mutex);
2672 return 0;
2673}
2674
728e29d7
DV		 2675static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2676{
2677 struct drm_info_node *node = (struct drm_info_node *) m->private;
2678 struct drm_device *dev = node->minor->dev;
2679 struct drm_i915_private *dev_priv = dev->dev_private;
2680 int i;
2681
2682 drm_modeset_lock_all(dev);
2683 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2684 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2685
2686 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2687 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2688 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2689 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2690 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2691 seq_printf(m, " dpll_md: 0x%08x\n",
2692 pll->config.hw_state.dpll_md);
2693 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2694 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2695 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2696 }
2697 drm_modeset_unlock_all(dev);
2698
2699 return 0;
2700}
2701
1ed1ef9d 2702static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2703{
2704 int i;
2705 int ret;
2706 struct drm_info_node *node = (struct drm_info_node *) m->private;
2707 struct drm_device *dev = node->minor->dev;
2708 struct drm_i915_private *dev_priv = dev->dev_private;
2709
888b5995
AS		 2710 ret = mutex_lock_interruptible(&dev->struct_mutex);
2711 if (ret)
2712 return ret;
2713
2714 intel_runtime_pm_get(dev_priv);
2715
7225342a
MK		 2716 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2717 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2718 u32 addr, mask, value, read;
2719 bool ok;
888b5995 2720
7225342a
MK		 2721 addr = dev_priv->workarounds.reg[i].addr;
2722 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2723 value = dev_priv->workarounds.reg[i].value;
2724 read = I915_READ(addr);
2725 ok = (value & mask) == (read & mask);
2726 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2727 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2728 }
2729
2730 intel_runtime_pm_put(dev_priv);
2731 mutex_unlock(&dev->struct_mutex);
2732
2733 return 0;
2734}
2735
c5511e44
DL		 2736static int i915_ddb_info(struct seq_file *m, void *unused)
2737{
2738 struct drm_info_node *node = m->private;
2739 struct drm_device *dev = node->minor->dev;
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 struct skl_ddb_allocation *ddb;
2742 struct skl_ddb_entry *entry;
2743 enum pipe pipe;
2744 int plane;
2745
2fcffe19
DL		 2746 if (INTEL_INFO(dev)->gen < 9)
2747 return 0;
2748
c5511e44
DL		 2749 drm_modeset_lock_all(dev);
2750
2751 ddb = &dev_priv->wm.skl_hw.ddb;
2752
2753 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2754
2755 for_each_pipe(dev_priv, pipe) {
2756 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2757
2758 for_each_plane(pipe, plane) {
2759 entry = &ddb->plane[pipe][plane];
2760 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2761 entry->start, entry->end,
2762 skl_ddb_entry_size(entry));
2763 }
2764
2765 entry = &ddb->cursor[pipe];
2766 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2767 entry->end, skl_ddb_entry_size(entry));
2768 }
2769
2770 drm_modeset_unlock_all(dev);
2771
2772 return 0;
2773}
2774
07144428
DL		 2775struct pipe_crc_info {
2776 const char *name;
2777 struct drm_device *dev;
2778 enum pipe pipe;
2779};
2780
11bed958
DA		 2781static int i915_dp_mst_info(struct seq_file *m, void *unused)
2782{
2783 struct drm_info_node *node = (struct drm_info_node *) m->private;
2784 struct drm_device *dev = node->minor->dev;
2785 struct drm_encoder *encoder;
2786 struct intel_encoder *intel_encoder;
2787 struct intel_digital_port *intel_dig_port;
2788 drm_modeset_lock_all(dev);
2789 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2790 intel_encoder = to_intel_encoder(encoder);
2791 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2792 continue;
2793 intel_dig_port = enc_to_dig_port(encoder);
2794 if (!intel_dig_port->dp.can_mst)
2795 continue;
2796
2797 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2798 }
2799 drm_modeset_unlock_all(dev);
2800 return 0;
2801}
2802
07144428
DL		 2803static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2804{
be5c7a90
DL		 2805 struct pipe_crc_info *info = inode->i_private;
2806 struct drm_i915_private *dev_priv = info->dev->dev_private;
2807 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2808
7eb1c496
DV		 2809 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2810 return -ENODEV;
2811
d538bbdf
DL		 2812 spin_lock_irq(&pipe_crc->lock);
2813
2814 if (pipe_crc->opened) {
2815 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2816 return -EBUSY; /* already open */
2817 }
2818
d538bbdf 2819 pipe_crc->opened = true;
07144428
DL		 2820 filep->private_data = inode->i_private;
2821
d538bbdf
DL		 2822 spin_unlock_irq(&pipe_crc->lock);
2823
07144428
DL		 2824 return 0;
2825}
2826
2827static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2828{
be5c7a90
DL		 2829 struct pipe_crc_info *info = inode->i_private;
2830 struct drm_i915_private *dev_priv = info->dev->dev_private;
2831 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2832
d538bbdf
DL		 2833 spin_lock_irq(&pipe_crc->lock);
2834 pipe_crc->opened = false;
2835 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2836
07144428
DL		 2837 return 0;
2838}
2839
2840/* (6 fields, 8 chars each, space separated (5) + '\n') */
2841#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2842/* account for \'0' */
2843#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2844
2845static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2846{
d538bbdf
DL		 2847 assert_spin_locked(&pipe_crc->lock);
2848 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2849 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2850}
2851
2852static ssize_t
2853i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2854 loff_t *pos)
2855{
2856 struct pipe_crc_info *info = filep->private_data;
2857 struct drm_device *dev = info->dev;
2858 struct drm_i915_private *dev_priv = dev->dev_private;
2859 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2860 char buf[PIPE_CRC_BUFFER_LEN];
2861 int head, tail, n_entries, n;
2862 ssize_t bytes_read;
2863
2864 /*
2865 * Don't allow user space to provide buffers not big enough to hold
2866 * a line of data.
2867 */
2868 if (count < PIPE_CRC_LINE_LEN)
2869 return -EINVAL;
2870
2871 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2872 return 0;
07144428
DL		 2873
2874 /* nothing to read */
d538bbdf 2875 spin_lock_irq(&pipe_crc->lock);
07144428 2876 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2877 int ret;
2878
2879 if (filep->f_flags & O_NONBLOCK) {
2880 spin_unlock_irq(&pipe_crc->lock);
07144428 2881 return -EAGAIN;
d538bbdf 2882 }
07144428 2883
d538bbdf
DL		 2884 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2885 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2886 if (ret) {
2887 spin_unlock_irq(&pipe_crc->lock);
2888 return ret;
2889 }
8bf1e9f1
SH		 2890 }
2891
07144428 2892 /* We now have one or more entries to read */
d538bbdf
DL		 2893 head = pipe_crc->head;
2894 tail = pipe_crc->tail;
07144428
DL		 2895 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2896 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2897 spin_unlock_irq(&pipe_crc->lock);
2898
07144428
DL		 2899 bytes_read = 0;
2900 n = 0;
2901 do {
b2c88f5b 2902 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2903 int ret;
8bf1e9f1 2904
07144428
DL		 2905 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2906 "%8u %8x %8x %8x %8x %8x\n",
2907 entry->frame, entry->crc[0],
2908 entry->crc[1], entry->crc[2],
2909 entry->crc[3], entry->crc[4]);
2910
2911 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2912 buf, PIPE_CRC_LINE_LEN);
2913 if (ret == PIPE_CRC_LINE_LEN)
2914 return -EFAULT;
b2c88f5b
DL		 2915
2916 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2917 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2918 n++;
2919 } while (--n_entries);
8bf1e9f1 2920
d538bbdf
DL		 2921 spin_lock_irq(&pipe_crc->lock);
2922 pipe_crc->tail = tail;
2923 spin_unlock_irq(&pipe_crc->lock);
2924
07144428
DL		 2925 return bytes_read;
2926}
2927
2928static const struct file_operations i915_pipe_crc_fops = {
2929 .owner = THIS_MODULE,
2930 .open = i915_pipe_crc_open,
2931 .read = i915_pipe_crc_read,
2932 .release = i915_pipe_crc_release,
2933};
2934
2935static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2936 {
2937 .name = "i915_pipe_A_crc",
2938 .pipe = PIPE_A,
2939 },
2940 {
2941 .name = "i915_pipe_B_crc",
2942 .pipe = PIPE_B,
2943 },
2944 {
2945 .name = "i915_pipe_C_crc",
2946 .pipe = PIPE_C,
2947 },
2948};
2949
2950static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2951 enum pipe pipe)
2952{
2953 struct drm_device *dev = minor->dev;
2954 struct dentry *ent;
2955 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2956
2957 info->dev = dev;
2958 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2959 &i915_pipe_crc_fops);
f3c5fe97
WY		 2960 if (!ent)
2961 return -ENOMEM;
07144428
DL		 2962
2963 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2964}
2965
e8dfcf78 2966static const char * const pipe_crc_sources[] = {
926321d5
DV		 2967 "none",
2968 "plane1",
2969 "plane2",
2970 "pf",
5b3a856b 2971 "pipe",
3d099a05
DV		 2972 "TV",
2973 "DP-B",
2974 "DP-C",
2975 "DP-D",
46a19188 2976 "auto",
926321d5
DV		 2977};
2978
2979static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2980{
2981 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2982 return pipe_crc_sources[source];
2983}
2984
bd9db02f 2985static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2986{
2987 struct drm_device *dev = m->private;
2988 struct drm_i915_private *dev_priv = dev->dev_private;
2989 int i;
2990
2991 for (i = 0; i < I915_MAX_PIPES; i++)
2992 seq_printf(m, "%c %s\n", pipe_name(i),
2993 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2994
2995 return 0;
2996}
2997
bd9db02f 2998static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2999{
3000 struct drm_device *dev = inode->i_private;
3001
bd9db02f 3002 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3003}
3004
46a19188 3005static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3006 uint32_t *val)
3007{
46a19188
DV		 3008 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3009 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3010
3011 switch (*source) {
52f843f6
DV		 3012 case INTEL_PIPE_CRC_SOURCE_PIPE:
3013 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3014 break;
3015 case INTEL_PIPE_CRC_SOURCE_NONE:
3016 *val = 0;
3017 break;
3018 default:
3019 return -EINVAL;
3020 }
3021
3022 return 0;
3023}
3024
46a19188
DV		 3025static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3026 enum intel_pipe_crc_source *source)
3027{
3028 struct intel_encoder *encoder;
3029 struct intel_crtc *crtc;
26756809 3030 struct intel_digital_port *dig_port;
46a19188
DV		 3031 int ret = 0;
3032
3033 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3034
6e9f798d 3035 drm_modeset_lock_all(dev);
b2784e15 3036 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3037 if (!encoder->base.crtc)
3038 continue;
3039
3040 crtc = to_intel_crtc(encoder->base.crtc);
3041
3042 if (crtc->pipe != pipe)
3043 continue;
3044
3045 switch (encoder->type) {
3046 case INTEL_OUTPUT_TVOUT:
3047 *source = INTEL_PIPE_CRC_SOURCE_TV;
3048 break;
3049 case INTEL_OUTPUT_DISPLAYPORT:
3050 case INTEL_OUTPUT_EDP:
26756809
DV		 3051 dig_port = enc_to_dig_port(&encoder->base);
3052 switch (dig_port->port) {
3053 case PORT_B:
3054 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3055 break;
3056 case PORT_C:
3057 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3058 break;
3059 case PORT_D:
3060 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3061 break;
3062 default:
3063 WARN(1, "nonexisting DP port %c\n",
3064 port_name(dig_port->port));
3065 break;
3066 }
46a19188 3067 break;
6847d71b
PZ		 3068 default:
3069 break;
46a19188
DV		 3070 }
3071 }
6e9f798d 3072 drm_modeset_unlock_all(dev);
46a19188
DV		 3073
3074 return ret;
3075}
3076
3077static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3078 enum pipe pipe,
3079 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3080 uint32_t *val)
3081{
8d2f24ca
DV		 3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 bool need_stable_symbols = false;
3084
46a19188
DV		 3085 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3086 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3087 if (ret)
3088 return ret;
3089 }
3090
3091 switch (*source) {
7ac0129b
DV		 3092 case INTEL_PIPE_CRC_SOURCE_PIPE:
3093 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3094 break;
3095 case INTEL_PIPE_CRC_SOURCE_DP_B:
3096 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3097 need_stable_symbols = true;
7ac0129b
DV		 3098 break;
3099 case INTEL_PIPE_CRC_SOURCE_DP_C:
3100 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3101 need_stable_symbols = true;
7ac0129b
DV		 3102 break;
3103 case INTEL_PIPE_CRC_SOURCE_NONE:
3104 *val = 0;
3105 break;
3106 default:
3107 return -EINVAL;
3108 }
3109
8d2f24ca
DV		 3110 /*
3111 * When the pipe CRC tap point is after the transcoders we need
3112 * to tweak symbol-level features to produce a deterministic series of
3113 * symbols for a given frame. We need to reset those features only once
3114 * a frame (instead of every nth symbol):
3115 * - DC-balance: used to ensure a better clock recovery from the data
3116 * link (SDVO)
3117 * - DisplayPort scrambling: used for EMI reduction
3118 */
3119 if (need_stable_symbols) {
3120 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3121
8d2f24ca 3122 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3123 switch (pipe) {
3124 case PIPE_A:
8d2f24ca 3125 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3126 break;
3127 case PIPE_B:
8d2f24ca 3128 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3129 break;
3130 case PIPE_C:
3131 tmp |= PIPE_C_SCRAMBLE_RESET;
3132 break;
3133 default:
3134 return -EINVAL;
3135 }
8d2f24ca
DV		 3136 I915_WRITE(PORT_DFT2_G4X, tmp);
3137 }
3138
7ac0129b
DV		 3139 return 0;
3140}
3141
4b79ebf7 3142static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3143 enum pipe pipe,
3144 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3145 uint32_t *val)
3146{
84093603
DV		 3147 struct drm_i915_private *dev_priv = dev->dev_private;
3148 bool need_stable_symbols = false;
3149
46a19188
DV		 3150 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3151 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3152 if (ret)
3153 return ret;
3154 }
3155
3156 switch (*source) {
4b79ebf7
DV		 3157 case INTEL_PIPE_CRC_SOURCE_PIPE:
3158 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3159 break;
3160 case INTEL_PIPE_CRC_SOURCE_TV:
3161 if (!SUPPORTS_TV(dev))
3162 return -EINVAL;
3163 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3164 break;
3165 case INTEL_PIPE_CRC_SOURCE_DP_B:
3166 if (!IS_G4X(dev))
3167 return -EINVAL;
3168 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3169 need_stable_symbols = true;
4b79ebf7
DV		 3170 break;
3171 case INTEL_PIPE_CRC_SOURCE_DP_C:
3172 if (!IS_G4X(dev))
3173 return -EINVAL;
3174 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3175 need_stable_symbols = true;
4b79ebf7
DV		 3176 break;
3177 case INTEL_PIPE_CRC_SOURCE_DP_D:
3178 if (!IS_G4X(dev))
3179 return -EINVAL;
3180 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3181 need_stable_symbols = true;
4b79ebf7
DV		 3182 break;
3183 case INTEL_PIPE_CRC_SOURCE_NONE:
3184 *val = 0;
3185 break;
3186 default:
3187 return -EINVAL;
3188 }
3189
84093603
DV		 3190 /*
3191 * When the pipe CRC tap point is after the transcoders we need
3192 * to tweak symbol-level features to produce a deterministic series of
3193 * symbols for a given frame. We need to reset those features only once
3194 * a frame (instead of every nth symbol):
3195 * - DC-balance: used to ensure a better clock recovery from the data
3196 * link (SDVO)
3197 * - DisplayPort scrambling: used for EMI reduction
3198 */
3199 if (need_stable_symbols) {
3200 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3201
3202 WARN_ON(!IS_G4X(dev));
3203
3204 I915_WRITE(PORT_DFT_I9XX,
3205 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3206
3207 if (pipe == PIPE_A)
3208 tmp |= PIPE_A_SCRAMBLE_RESET;
3209 else
3210 tmp |= PIPE_B_SCRAMBLE_RESET;
3211
3212 I915_WRITE(PORT_DFT2_G4X, tmp);
3213 }
3214
4b79ebf7
DV		 3215 return 0;
3216}
3217
8d2f24ca
DV		 3218static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3219 enum pipe pipe)
3220{
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3222 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3223
eb736679
VS		 3224 switch (pipe) {
3225 case PIPE_A:
8d2f24ca 3226 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3227 break;
3228 case PIPE_B:
8d2f24ca 3229 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3230 break;
3231 case PIPE_C:
3232 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3233 break;
3234 default:
3235 return;
3236 }
8d2f24ca
DV		 3237 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3238 tmp &= ~DC_BALANCE_RESET_VLV;
3239 I915_WRITE(PORT_DFT2_G4X, tmp);
3240
3241}
3242
84093603
DV		 3243static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3244 enum pipe pipe)
3245{
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3248
3249 if (pipe == PIPE_A)
3250 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3251 else
3252 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3253 I915_WRITE(PORT_DFT2_G4X, tmp);
3254
3255 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3256 I915_WRITE(PORT_DFT_I9XX,
3257 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3258 }
3259}
3260
46a19188 3261static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3262 uint32_t *val)
3263{
46a19188
DV		 3264 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3265 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3266
3267 switch (*source) {
5b3a856b
DV		 3268 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3269 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3270 break;
3271 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3272 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3273 break;
5b3a856b
DV		 3274 case INTEL_PIPE_CRC_SOURCE_PIPE:
3275 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3276 break;
3d099a05 3277 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3278 *val = 0;
3279 break;
3d099a05
DV		 3280 default:
3281 return -EINVAL;
5b3a856b
DV		 3282 }
3283
3284 return 0;
3285}
3286
fabf6e51
DV		 3287static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3288{
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *crtc =
3291 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3292
3293 drm_modeset_lock_all(dev);
3294 /*
3295 * If we use the eDP transcoder we need to make sure that we don't
3296 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3297 * relevant on hsw with pipe A when using the always-on power well
3298 * routing.
3299 */
3300 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3301 !crtc->config.pch_pfit.enabled) {
3302 crtc->config.pch_pfit.force_thru = true;
3303
3304 intel_display_power_get(dev_priv,
3305 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3306
3307 dev_priv->display.crtc_disable(&crtc->base);
3308 dev_priv->display.crtc_enable(&crtc->base);
3309 }
3310 drm_modeset_unlock_all(dev);
3311}
3312
3313static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3314{
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 struct intel_crtc *crtc =
3317 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3318
3319 drm_modeset_lock_all(dev);
3320 /*
3321 * If we use the eDP transcoder we need to make sure that we don't
3322 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3323 * relevant on hsw with pipe A when using the always-on power well
3324 * routing.
3325 */
3326 if (crtc->config.pch_pfit.force_thru) {
3327 crtc->config.pch_pfit.force_thru = false;
3328
3329 dev_priv->display.crtc_disable(&crtc->base);
3330 dev_priv->display.crtc_enable(&crtc->base);
3331
3332 intel_display_power_put(dev_priv,
3333 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3334 }
3335 drm_modeset_unlock_all(dev);
3336}
3337
3338static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3339 enum pipe pipe,
3340 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3341 uint32_t *val)
3342{
46a19188
DV		 3343 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3344 *source = INTEL_PIPE_CRC_SOURCE_PF;
3345
3346 switch (*source) {
5b3a856b
DV		 3347 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3348 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3349 break;
3350 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3351 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3352 break;
3353 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3354 if (IS_HASWELL(dev) && pipe == PIPE_A)
3355 hsw_trans_edp_pipe_A_crc_wa(dev);
3356
5b3a856b
DV		 3357 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3358 break;
3d099a05 3359 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3360 *val = 0;
3361 break;
3d099a05
DV		 3362 default:
3363 return -EINVAL;
5b3a856b
DV		 3364 }
3365
3366 return 0;
3367}
3368
926321d5
DV		 3369static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3370 enum intel_pipe_crc_source source)
3371{
3372 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3373 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3374 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3375 pipe));
432f3342 3376 u32 val = 0; /* shut up gcc */
5b3a856b 3377 int ret;
926321d5 3378
cc3da175
DL		 3379 if (pipe_crc->source == source)
3380 return 0;
3381
ae676fcd
DL		 3382 /* forbid changing the source without going back to 'none' */
3383 if (pipe_crc->source && source)
3384 return -EINVAL;
3385
9d8b0588
DV		 3386 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3387 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3388 return -EIO;
3389 }
3390
52f843f6 3391 if (IS_GEN2(dev))
46a19188 3392 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3393 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3394 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3395 else if (IS_VALLEYVIEW(dev))
fabf6e51 3396 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3397 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3398 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3399 else
fabf6e51 3400 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3401
3402 if (ret != 0)
3403 return ret;
3404
4b584369
DL		 3405 /* none -> real source transition */
3406 if (source) {
7cd6ccff
DL		 3407 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3408 pipe_name(pipe), pipe_crc_source_name(source));
3409
e5f75aca
DL		 3410 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
3411 INTEL_PIPE_CRC_ENTRIES_NR,
3412 GFP_KERNEL);
3413 if (!pipe_crc->entries)
3414 return -ENOMEM;
3415
8c740dce
PZ		 3416 /*
3417 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3418 * enabled and disabled dynamically based on package C states,
3419 * user space can't make reliable use of the CRCs, so let's just
3420 * completely disable it.
3421 */
3422 hsw_disable_ips(crtc);
3423
d538bbdf
DL		 3424 spin_lock_irq(&pipe_crc->lock);
3425 pipe_crc->head = 0;
3426 pipe_crc->tail = 0;
3427 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3428 }
3429
cc3da175 3430 pipe_crc->source = source;
926321d5 3431
926321d5
DV		 3432 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3433 POSTING_READ(PIPE_CRC_CTL(pipe));
3434
e5f75aca
DL		 3435 /* real source -> none transition */
3436 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3437 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3438 struct intel_crtc *crtc =
3439 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3440
7cd6ccff
DL		 3441 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3442 pipe_name(pipe));
3443
a33d7105
DV		 3444 drm_modeset_lock(&crtc->base.mutex, NULL);
3445 if (crtc->active)
3446 intel_wait_for_vblank(dev, pipe);
3447 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3448
d538bbdf
DL		 3449 spin_lock_irq(&pipe_crc->lock);
3450 entries = pipe_crc->entries;
e5f75aca 3451 pipe_crc->entries = NULL;
d538bbdf
DL		 3452 spin_unlock_irq(&pipe_crc->lock);
3453
3454 kfree(entries);
84093603
DV		 3455
3456 if (IS_G4X(dev))
3457 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3458 else if (IS_VALLEYVIEW(dev))
3459 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3460 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3461 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3462
3463 hsw_enable_ips(crtc);
e5f75aca
DL		 3464 }
3465
926321d5
DV		 3466 return 0;
3467}
3468
3469/*
3470 * Parse pipe CRC command strings:
b94dec87
DL		 3471 * command: wsp* object wsp+ name wsp+ source wsp*
3472 * object: 'pipe'
3473 * name: (A | B | C)
926321d5
DV		 3474 * source: (none | plane1 | plane2 | pf)
3475 * wsp: (#0x20 | #0x9 | #0xA)+
3476 *
3477 * eg.:
b94dec87
DL		 3478 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3479 * "pipe A none" -> Stop CRC
926321d5 3480 */
bd9db02f 3481static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3482{
3483 int n_words = 0;
3484
3485 while (*buf) {
3486 char *end;
3487
3488 /* skip leading white space */
3489 buf = skip_spaces(buf);
3490 if (!*buf)
3491 break; /* end of buffer */
3492
3493 /* find end of word */
3494 for (end = buf; *end && !isspace(*end); end++)
3495 ;
3496
3497 if (n_words == max_words) {
3498 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3499 max_words);
3500 return -EINVAL; /* ran out of words[] before bytes */
3501 }
3502
3503 if (*end)
3504 *end++ = '\0';
3505 words[n_words++] = buf;
3506 buf = end;
3507 }
3508
3509 return n_words;
3510}
3511
b94dec87
DL		 3512enum intel_pipe_crc_object {
3513 PIPE_CRC_OBJECT_PIPE,
3514};
3515
e8dfcf78 3516static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3517 "pipe",
3518};
3519
3520static int
bd9db02f 3521display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3522{
3523 int i;
3524
3525 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3526 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3527 *o = i;
b94dec87
DL		 3528 return 0;
3529 }
3530
3531 return -EINVAL;
3532}
3533
bd9db02f 3534static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3535{
3536 const char name = buf[0];
3537
3538 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3539 return -EINVAL;
3540
3541 *pipe = name - 'A';
3542
3543 return 0;
3544}
3545
3546static int
bd9db02f 3547display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3548{
3549 int i;
3550
3551 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3552 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3553 *s = i;
926321d5
DV		 3554 return 0;
3555 }
3556
3557 return -EINVAL;
3558}
3559
bd9db02f 3560static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3561{
b94dec87 3562#define N_WORDS 3
926321d5 3563 int n_words;
b94dec87 3564 char *words[N_WORDS];
926321d5 3565 enum pipe pipe;
b94dec87 3566 enum intel_pipe_crc_object object;
926321d5
DV		 3567 enum intel_pipe_crc_source source;
3568
bd9db02f 3569 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3570 if (n_words != N_WORDS) {
3571 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3572 N_WORDS);
3573 return -EINVAL;
3574 }
3575
bd9db02f 3576 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3577 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3578 return -EINVAL;
3579 }
3580
bd9db02f 3581 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3582 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3583 return -EINVAL;
3584 }
3585
bd9db02f 3586 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3587 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3588 return -EINVAL;
3589 }
3590
3591 return pipe_crc_set_source(dev, pipe, source);
3592}
3593
bd9db02f
DL		 3594static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3595 size_t len, loff_t *offp)
926321d5
DV		 3596{
3597 struct seq_file *m = file->private_data;
3598 struct drm_device *dev = m->private;
3599 char *tmpbuf;
3600 int ret;
3601
3602 if (len == 0)
3603 return 0;
3604
3605 if (len > PAGE_SIZE - 1) {
3606 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3607 PAGE_SIZE);
3608 return -E2BIG;
3609 }
3610
3611 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3612 if (!tmpbuf)
3613 return -ENOMEM;
3614
3615 if (copy_from_user(tmpbuf, ubuf, len)) {
3616 ret = -EFAULT;
3617 goto out;
3618 }
3619 tmpbuf[len] = '\0';
3620
bd9db02f 3621 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3622
3623out:
3624 kfree(tmpbuf);
3625 if (ret < 0)
3626 return ret;
3627
3628 *offp += len;
3629 return len;
3630}
3631
bd9db02f 3632static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3633 .owner = THIS_MODULE,
bd9db02f 3634 .open = display_crc_ctl_open,
926321d5
DV		 3635 .read = seq_read,
3636 .llseek = seq_lseek,
3637 .release = single_release,
bd9db02f 3638 .write = display_crc_ctl_write
926321d5
DV		 3639};
3640
97e94b22 3641static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3642{
3643 struct drm_device *dev = m->private;
546c81fd 3644 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3645 int level;
3646
3647 drm_modeset_lock_all(dev);
3648
3649 for (level = 0; level < num_levels; level++) {
3650 unsigned int latency = wm[level];
3651
97e94b22
DL		 3652 /*
3653 * - WM1+ latency values in 0.5us units
3654 * - latencies are in us on gen9
3655 */
3656 if (INTEL_INFO(dev)->gen >= 9)
3657 latency *= 10;
3658 else if (level > 0)
369a1342
VS		 3659 latency *= 5;
3660
3661 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3662 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3663 }
3664
3665 drm_modeset_unlock_all(dev);
3666}
3667
3668static int pri_wm_latency_show(struct seq_file *m, void *data)
3669{
3670 struct drm_device *dev = m->private;
97e94b22
DL		 3671 struct drm_i915_private *dev_priv = dev->dev_private;
3672 const uint16_t *latencies;
3673
3674 if (INTEL_INFO(dev)->gen >= 9)
3675 latencies = dev_priv->wm.skl_latency;
3676 else
3677 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3678
97e94b22 3679 wm_latency_show(m, latencies);
369a1342
VS		 3680
3681 return 0;
3682}
3683
3684static int spr_wm_latency_show(struct seq_file *m, void *data)
3685{
3686 struct drm_device *dev = m->private;
97e94b22
DL		 3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 const uint16_t *latencies;
3689
3690 if (INTEL_INFO(dev)->gen >= 9)
3691 latencies = dev_priv->wm.skl_latency;
3692 else
3693 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3694
97e94b22 3695 wm_latency_show(m, latencies);
369a1342
VS		 3696
3697 return 0;
3698}
3699
3700static int cur_wm_latency_show(struct seq_file *m, void *data)
3701{
3702 struct drm_device *dev = m->private;
97e94b22
DL		 3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 const uint16_t *latencies;
3705
3706 if (INTEL_INFO(dev)->gen >= 9)
3707 latencies = dev_priv->wm.skl_latency;
3708 else
3709 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3710
97e94b22 3711 wm_latency_show(m, latencies);
369a1342
VS		 3712
3713 return 0;
3714}
3715
3716static int pri_wm_latency_open(struct inode *inode, struct file *file)
3717{
3718 struct drm_device *dev = inode->i_private;
3719
9ad0257c 3720 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3721 return -ENODEV;
3722
3723 return single_open(file, pri_wm_latency_show, dev);
3724}
3725
3726static int spr_wm_latency_open(struct inode *inode, struct file *file)
3727{
3728 struct drm_device *dev = inode->i_private;
3729
9ad0257c 3730 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3731 return -ENODEV;
3732
3733 return single_open(file, spr_wm_latency_show, dev);
3734}
3735
3736static int cur_wm_latency_open(struct inode *inode, struct file *file)
3737{
3738 struct drm_device *dev = inode->i_private;
3739
9ad0257c 3740 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3741 return -ENODEV;
3742
3743 return single_open(file, cur_wm_latency_show, dev);
3744}
3745
3746static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3747 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3748{
3749 struct seq_file *m = file->private_data;
3750 struct drm_device *dev = m->private;
97e94b22 3751 uint16_t new[8] = { 0 };
546c81fd 3752 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3753 int level;
3754 int ret;
3755 char tmp[32];
3756
3757 if (len >= sizeof(tmp))
3758 return -EINVAL;
3759
3760 if (copy_from_user(tmp, ubuf, len))
3761 return -EFAULT;
3762
3763 tmp[len] = '\0';
3764
97e94b22
DL		 3765 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3766 &new[0], &new[1], &new[2], &new[3],
3767 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 3768 if (ret != num_levels)
3769 return -EINVAL;
3770
3771 drm_modeset_lock_all(dev);
3772
3773 for (level = 0; level < num_levels; level++)
3774 wm[level] = new[level];
3775
3776 drm_modeset_unlock_all(dev);
3777
3778 return len;
3779}
3780
3781
3782static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3783 size_t len, loff_t *offp)
3784{
3785 struct seq_file *m = file->private_data;
3786 struct drm_device *dev = m->private;
97e94b22
DL		 3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 uint16_t *latencies;
369a1342 3789
97e94b22
DL		 3790 if (INTEL_INFO(dev)->gen >= 9)
3791 latencies = dev_priv->wm.skl_latency;
3792 else
3793 latencies = to_i915(dev)->wm.pri_latency;
3794
3795 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3796}
3797
3798static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3799 size_t len, loff_t *offp)
3800{
3801 struct seq_file *m = file->private_data;
3802 struct drm_device *dev = m->private;
97e94b22
DL		 3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 uint16_t *latencies;
369a1342 3805
97e94b22
DL		 3806 if (INTEL_INFO(dev)->gen >= 9)
3807 latencies = dev_priv->wm.skl_latency;
3808 else
3809 latencies = to_i915(dev)->wm.spr_latency;
3810
3811 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3812}
3813
3814static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3815 size_t len, loff_t *offp)
3816{
3817 struct seq_file *m = file->private_data;
3818 struct drm_device *dev = m->private;
97e94b22
DL		 3819 struct drm_i915_private *dev_priv = dev->dev_private;
3820 uint16_t *latencies;
3821
3822 if (INTEL_INFO(dev)->gen >= 9)
3823 latencies = dev_priv->wm.skl_latency;
3824 else
3825 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3826
97e94b22 3827 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3828}
3829
3830static const struct file_operations i915_pri_wm_latency_fops = {
3831 .owner = THIS_MODULE,
3832 .open = pri_wm_latency_open,
3833 .read = seq_read,
3834 .llseek = seq_lseek,
3835 .release = single_release,
3836 .write = pri_wm_latency_write
3837};
3838
3839static const struct file_operations i915_spr_wm_latency_fops = {
3840 .owner = THIS_MODULE,
3841 .open = spr_wm_latency_open,
3842 .read = seq_read,
3843 .llseek = seq_lseek,
3844 .release = single_release,
3845 .write = spr_wm_latency_write
3846};
3847
3848static const struct file_operations i915_cur_wm_latency_fops = {
3849 .owner = THIS_MODULE,
3850 .open = cur_wm_latency_open,
3851 .read = seq_read,
3852 .llseek = seq_lseek,
3853 .release = single_release,
3854 .write = cur_wm_latency_write
3855};
3856
647416f9
KC		 3857static int
3858i915_wedged_get(void *data, u64 *val)
f3cd474b 3859{
647416f9 3860 struct drm_device *dev = data;
e277a1f8 3861 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3862
647416f9 3863 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3864
647416f9 3865 return 0;
f3cd474b
CW		 3866}
3867
647416f9
KC		 3868static int
3869i915_wedged_set(void *data, u64 val)
f3cd474b 3870{
647416f9 3871 struct drm_device *dev = data;
d46c0517
ID		 3872 struct drm_i915_private *dev_priv = dev->dev_private;
3873
3874 intel_runtime_pm_get(dev_priv);
f3cd474b 3875
58174462
MK		 3876 i915_handle_error(dev, val,
3877 "Manually setting wedged to %llu", val);
d46c0517
ID		 3878
3879 intel_runtime_pm_put(dev_priv);
3880
647416f9 3881 return 0;
f3cd474b
CW		 3882}
3883
647416f9
KC		 3884DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3885 i915_wedged_get, i915_wedged_set,
3a3b4f98 3886 "%llu\n");
f3cd474b 3887
647416f9
KC		 3888static int
3889i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3890{
647416f9 3891 struct drm_device *dev = data;
e277a1f8 3892 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3893
647416f9 3894 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3895
647416f9 3896 return 0;
e5eb3d63
DV		 3897}
3898
647416f9
KC		 3899static int
3900i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3901{
647416f9 3902 struct drm_device *dev = data;
e5eb3d63 3903 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3904 int ret;
e5eb3d63 3905
647416f9 3906 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3907
22bcfc6a
DV		 3908 ret = mutex_lock_interruptible(&dev->struct_mutex);
3909 if (ret)
3910 return ret;
3911
99584db3 3912 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3913 mutex_unlock(&dev->struct_mutex);
3914
647416f9 3915 return 0;
e5eb3d63
DV		 3916}
3917
647416f9
KC		 3918DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3919 i915_ring_stop_get, i915_ring_stop_set,
3920 "0x%08llx\n");
d5442303 3921
094f9a54
CW		 3922static int
3923i915_ring_missed_irq_get(void *data, u64 *val)
3924{
3925 struct drm_device *dev = data;
3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927
3928 *val = dev_priv->gpu_error.missed_irq_rings;
3929 return 0;
3930}
3931
3932static int
3933i915_ring_missed_irq_set(void *data, u64 val)
3934{
3935 struct drm_device *dev = data;
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937 int ret;
3938
3939 /* Lock against concurrent debugfs callers */
3940 ret = mutex_lock_interruptible(&dev->struct_mutex);
3941 if (ret)
3942 return ret;
3943 dev_priv->gpu_error.missed_irq_rings = val;
3944 mutex_unlock(&dev->struct_mutex);
3945
3946 return 0;
3947}
3948
3949DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3950 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3951 "0x%08llx\n");
3952
3953static int
3954i915_ring_test_irq_get(void *data, u64 *val)
3955{
3956 struct drm_device *dev = data;
3957 struct drm_i915_private *dev_priv = dev->dev_private;
3958
3959 *val = dev_priv->gpu_error.test_irq_rings;
3960
3961 return 0;
3962}
3963
3964static int
3965i915_ring_test_irq_set(void *data, u64 val)
3966{
3967 struct drm_device *dev = data;
3968 struct drm_i915_private *dev_priv = dev->dev_private;
3969 int ret;
3970
3971 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3972
3973 /* Lock against concurrent debugfs callers */
3974 ret = mutex_lock_interruptible(&dev->struct_mutex);
3975 if (ret)
3976 return ret;
3977
3978 dev_priv->gpu_error.test_irq_rings = val;
3979 mutex_unlock(&dev->struct_mutex);
3980
3981 return 0;
3982}
3983
3984DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3985 i915_ring_test_irq_get, i915_ring_test_irq_set,
3986 "0x%08llx\n");
3987
dd624afd
CW		 3988#define DROP_UNBOUND 0x1
3989#define DROP_BOUND 0x2
3990#define DROP_RETIRE 0x4
3991#define DROP_ACTIVE 0x8
3992#define DROP_ALL (DROP_UNBOUND | \
3993 DROP_BOUND | \
3994 DROP_RETIRE | \
3995 DROP_ACTIVE)
647416f9
KC		 3996static int
3997i915_drop_caches_get(void *data, u64 *val)
dd624afd 3998{
647416f9 3999 *val = DROP_ALL;
dd624afd 4000
647416f9 4001 return 0;
dd624afd
CW		 4002}
4003
647416f9
KC		 4004static int
4005i915_drop_caches_set(void *data, u64 val)
dd624afd 4006{
647416f9 4007 struct drm_device *dev = data;
dd624afd 4008 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4009 int ret;
dd624afd 4010
2f9fe5ff 4011 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4012
4013 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4014 * on ioctls on -EAGAIN. */
4015 ret = mutex_lock_interruptible(&dev->struct_mutex);
4016 if (ret)
4017 return ret;
4018
4019 if (val & DROP_ACTIVE) {
4020 ret = i915_gpu_idle(dev);
4021 if (ret)
4022 goto unlock;
4023 }
4024
4025 if (val & (DROP_RETIRE | DROP_ACTIVE))
4026 i915_gem_retire_requests(dev);
4027
21ab4e74
CW		 4028 if (val & DROP_BOUND)
4029 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4030
21ab4e74
CW		 4031 if (val & DROP_UNBOUND)
4032 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4033
4034unlock:
4035 mutex_unlock(&dev->struct_mutex);
4036
647416f9 4037 return ret;
dd624afd
CW		 4038}
4039
647416f9
KC		 4040DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4041 i915_drop_caches_get, i915_drop_caches_set,
4042 "0x%08llx\n");
dd624afd 4043
647416f9
KC		 4044static int
4045i915_max_freq_get(void *data, u64 *val)
358733e9 4046{
647416f9 4047 struct drm_device *dev = data;
e277a1f8 4048 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4049 int ret;
004777cb 4050
daa3afb2 4051 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4052 return -ENODEV;
4053
5c9669ce
TR		 4054 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4055
4fc688ce 4056 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4057 if (ret)
4058 return ret;
358733e9 4059
0a073b84 4060 if (IS_VALLEYVIEW(dev))
b39fb297 4061 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 4062 else
b39fb297 4063 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 4064 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4065
647416f9 4066 return 0;
358733e9
JB		 4067}
4068
647416f9
KC		 4069static int
4070i915_max_freq_set(void *data, u64 val)
358733e9 4071{
647416f9 4072 struct drm_device *dev = data;
358733e9 4073 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4074 u32 rp_state_cap, hw_max, hw_min;
647416f9 4075 int ret;
004777cb 4076
daa3afb2 4077 if (INTEL_INFO(dev)->gen < 6)
004777cb 4078 return -ENODEV;
358733e9 4079
5c9669ce
TR		 4080 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4081
647416f9 4082 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4083
4fc688ce 4084 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4085 if (ret)
4086 return ret;
4087
358733e9
JB		 4088 /*
4089 * Turbo will still be enabled, but won't go above the set value.
4090 */
0a073b84 4091 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4092 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4093
03af2045
VS		 4094 hw_max = dev_priv->rps.max_freq;
4095 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4096 } else {
4097 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4098
4099 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4100 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4101 hw_min = (rp_state_cap >> 16) & 0xff;
4102 }
4103
b39fb297 4104 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4105 mutex_unlock(&dev_priv->rps.hw_lock);
4106 return -EINVAL;
0a073b84
JB		 4107 }
4108
b39fb297 4109 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 4110
4111 if (IS_VALLEYVIEW(dev))
4112 valleyview_set_rps(dev, val);
4113 else
4114 gen6_set_rps(dev, val);
4115
4fc688ce 4116 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4117
647416f9 4118 return 0;
358733e9
JB		 4119}
4120
647416f9
KC		 4121DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4122 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4123 "%llu\n");
358733e9 4124
647416f9
KC		 4125static int
4126i915_min_freq_get(void *data, u64 *val)
1523c310 4127{
647416f9 4128 struct drm_device *dev = data;
e277a1f8 4129 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4130 int ret;
004777cb 4131
daa3afb2 4132 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4133 return -ENODEV;
4134
5c9669ce
TR		 4135 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4136
4fc688ce 4137 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4138 if (ret)
4139 return ret;
1523c310 4140
0a073b84 4141 if (IS_VALLEYVIEW(dev))
b39fb297 4142 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 4143 else
b39fb297 4144 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 4145 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4146
647416f9 4147 return 0;
1523c310
JB		 4148}
4149
647416f9
KC		 4150static int
4151i915_min_freq_set(void *data, u64 val)
1523c310 4152{
647416f9 4153 struct drm_device *dev = data;
1523c310 4154 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4155 u32 rp_state_cap, hw_max, hw_min;
647416f9 4156 int ret;
004777cb 4157
daa3afb2 4158 if (INTEL_INFO(dev)->gen < 6)
004777cb 4159 return -ENODEV;
1523c310 4160
5c9669ce
TR		 4161 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4162
647416f9 4163 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4164
4fc688ce 4165 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4166 if (ret)
4167 return ret;
4168
1523c310
JB		 4169 /*
4170 * Turbo will still be enabled, but won't go below the set value.
4171 */
0a073b84 4172 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4173 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4174
03af2045
VS		 4175 hw_max = dev_priv->rps.max_freq;
4176 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4177 } else {
4178 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4179
4180 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4181 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4182 hw_min = (rp_state_cap >> 16) & 0xff;
4183 }
4184
b39fb297 4185 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4186 mutex_unlock(&dev_priv->rps.hw_lock);
4187 return -EINVAL;
0a073b84 4188 }
dd0a1aa1 4189
b39fb297 4190 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 4191
4192 if (IS_VALLEYVIEW(dev))
4193 valleyview_set_rps(dev, val);
4194 else
4195 gen6_set_rps(dev, val);
4196
4fc688ce 4197 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4198
647416f9 4199 return 0;
1523c310
JB		 4200}
4201
647416f9
KC		 4202DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4203 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4204 "%llu\n");
1523c310 4205
647416f9
KC		 4206static int
4207i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4208{
647416f9 4209 struct drm_device *dev = data;
e277a1f8 4210 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4211 u32 snpcr;
647416f9 4212 int ret;
07b7ddd9 4213
004777cb
DV		 4214 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4215 return -ENODEV;
4216
22bcfc6a
DV		 4217 ret = mutex_lock_interruptible(&dev->struct_mutex);
4218 if (ret)
4219 return ret;
c8c8fb33 4220 intel_runtime_pm_get(dev_priv);
22bcfc6a 4221
07b7ddd9 4222 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4223
4224 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4225 mutex_unlock(&dev_priv->dev->struct_mutex);
4226
647416f9 4227 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4228
647416f9 4229 return 0;
07b7ddd9
JB		 4230}
4231
647416f9
KC		 4232static int
4233i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4234{
647416f9 4235 struct drm_device *dev = data;
07b7ddd9 4236 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4237 u32 snpcr;
07b7ddd9 4238
004777cb
DV		 4239 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4240 return -ENODEV;
4241
647416f9 4242 if (val > 3)
07b7ddd9
JB		 4243 return -EINVAL;
4244
c8c8fb33 4245 intel_runtime_pm_get(dev_priv);
647416f9 4246 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4247
4248 /* Update the cache sharing policy here as well */
4249 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4250 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4251 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4252 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4253
c8c8fb33 4254 intel_runtime_pm_put(dev_priv);
647416f9 4255 return 0;
07b7ddd9
JB		 4256}
4257
647416f9
KC		 4258DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4259 i915_cache_sharing_get, i915_cache_sharing_set,
4260 "%llu\n");
07b7ddd9 4261
6d794d42
BW		 4262static int i915_forcewake_open(struct inode *inode, struct file *file)
4263{
4264 struct drm_device *dev = inode->i_private;
4265 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4266
075edca4 4267 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4268 return 0;
4269
c8d9a590 4270 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4271
4272 return 0;
4273}
4274
c43b5634 4275static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4276{
4277 struct drm_device *dev = inode->i_private;
4278 struct drm_i915_private *dev_priv = dev->dev_private;
4279
075edca4 4280 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4281 return 0;
4282
c8d9a590 4283 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4284
4285 return 0;
4286}
4287
4288static const struct file_operations i915_forcewake_fops = {
4289 .owner = THIS_MODULE,
4290 .open = i915_forcewake_open,
4291 .release = i915_forcewake_release,
4292};
4293
4294static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4295{
4296 struct drm_device *dev = minor->dev;
4297 struct dentry *ent;
4298
4299 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4300 S_IRUSR,
6d794d42
BW		 4301 root, dev,
4302 &i915_forcewake_fops);
f3c5fe97
WY		 4303 if (!ent)
4304 return -ENOMEM;
6d794d42 4305
8eb57294 4306 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4307}
4308
6a9c308d
DV		 4309static int i915_debugfs_create(struct dentry *root,
4310 struct drm_minor *minor,
4311 const char *name,
4312 const struct file_operations *fops)
07b7ddd9
JB		 4313{
4314 struct drm_device *dev = minor->dev;
4315 struct dentry *ent;
4316
6a9c308d 4317 ent = debugfs_create_file(name,
07b7ddd9
JB		 4318 S_IRUGO | S_IWUSR,
4319 root, dev,
6a9c308d 4320 fops);
f3c5fe97
WY		 4321 if (!ent)
4322 return -ENOMEM;
07b7ddd9 4323
6a9c308d 4324 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4325}
4326
06c5bf8c 4327static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4328 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4329 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4330 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4331 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4332 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4333 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4334 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4335 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4336 {"i915_gem_request", i915_gem_request_info, 0},
4337 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4338 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4339 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4340 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4341 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4342 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4343 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
adb4bd12 4344 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 4345 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4346 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4347 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4348 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4349 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4350 {"i915_sr_status", i915_sr_status, 0},
44834a67 4351 {"i915_opregion", i915_opregion, 0},
37811fcc 4352 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4353 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4354 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4355 {"i915_execlists", i915_execlists, 0},
6d794d42 4356 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 4357 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4358 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4359 {"i915_llc", i915_llc, 0},
e91fd8c6 4360 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4361 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4362 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4363 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4364 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4365 {"i915_display_info", i915_display_info, 0},
e04934cf 4366 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4367 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4368 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4369 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4370 {"i915_ddb_info", i915_ddb_info, 0},
2017263e 4371};
27c202ad 4372#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4373
06c5bf8c 4374static const struct i915_debugfs_files {
34b9674c
DV		 4375 const char *name;
4376 const struct file_operations *fops;
4377} i915_debugfs_files[] = {
4378 {"i915_wedged", &i915_wedged_fops},
4379 {"i915_max_freq", &i915_max_freq_fops},
4380 {"i915_min_freq", &i915_min_freq_fops},
4381 {"i915_cache_sharing", &i915_cache_sharing_fops},
4382 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4383 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4384 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4385 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4386 {"i915_error_state", &i915_error_state_fops},
4387 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4388 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4389 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4390 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4391 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4392 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4393};
4394
07144428
DL		 4395void intel_display_crc_init(struct drm_device *dev)
4396{
4397 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4398 enum pipe pipe;
07144428 4399
055e393f 4400 for_each_pipe(dev_priv, pipe) {
b378360e 4401 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4402
d538bbdf
DL		 4403 pipe_crc->opened = false;
4404 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4405 init_waitqueue_head(&pipe_crc->wq);
4406 }
4407}
4408
27c202ad 4409int i915_debugfs_init(struct drm_minor *minor)
2017263e 4410{
34b9674c 4411 int ret, i;
f3cd474b 4412
6d794d42 4413 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4414 if (ret)
4415 return ret;
6a9c308d 4416
07144428
DL		 4417 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4418 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4419 if (ret)
4420 return ret;
4421 }
4422
34b9674c
DV		 4423 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4424 ret = i915_debugfs_create(minor->debugfs_root, minor,
4425 i915_debugfs_files[i].name,
4426 i915_debugfs_files[i].fops);
4427 if (ret)
4428 return ret;
4429 }
40633219 4430
27c202ad
BG		 4431 return drm_debugfs_create_files(i915_debugfs_list,
4432 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4433 minor->debugfs_root, minor);
4434}
4435
27c202ad 4436void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4437{
34b9674c
DV		 4438 int i;
4439
27c202ad
BG		 4440 drm_debugfs_remove_files(i915_debugfs_list,
4441 I915_DEBUGFS_ENTRIES, minor);
07144428 4442
6d794d42
BW		 4443 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4444 1, minor);
07144428 4445
e309a997 4446 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4447 struct drm_info_list *info_list =
4448 (struct drm_info_list *)&i915_pipe_crc_data[i];
4449
4450 drm_debugfs_remove_files(info_list, 1, minor);
4451 }
4452
34b9674c
DV		 4453 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4454 struct drm_info_list *info_list =
4455 (struct drm_info_list *) i915_debugfs_files[i].fops;
4456
4457 drm_debugfs_remove_files(info_list, 1, minor);
4458 }
2017263e 4459}
Linux 6.x block layer and io_uring tree(s)