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drm/i915: Cleaning up DDI translation tables
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
05394f39 92static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
baaa5cfb 94 if (obj->pin_display)
a6172a80
CW		 95 return "p";
96 else
97 return " ";
98}
99
05394f39 100static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 101{
0206e353
AJ		 102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
a6172a80
CW		 108}
109
1d693bcc
BW		 110static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111{
aff43766 112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 113}
114
ca1543be
TU		 115static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116{
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, vma_link) {
121 if (i915_is_ggtt(vma->vm) &&
122 drm_mm_node_allocated(&vma->node))
123 size += vma->node.size;
124 }
125
126 return size;
127}
128
37811fcc
CW		 129static void
130describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131{
b4716185
CW		 132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
133 struct intel_engine_cs *ring;
1d693bcc 134 struct i915_vma *vma;
d7f46fc4 135 int pin_count = 0;
b4716185 136 int i;
d7f46fc4 137
b4716185 138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 139 &obj->base,
481a3d43 140 obj->active ? "*" : " ",
37811fcc
CW		 141 get_pin_flag(obj),
142 get_tiling_flag(obj),
1d693bcc 143 get_global_flag(obj),
a05a5862 144 obj->base.size / 1024,
37811fcc 145 obj->base.read_domains,
b4716185
CW		 146 obj->base.write_domain);
147 for_each_ring(ring, dev_priv, i)
148 seq_printf(m, "%x ",
149 i915_gem_request_get_seqno(obj->last_read_req[i]));
150 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 151 i915_gem_request_get_seqno(obj->last_write_req),
152 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 154 obj->dirty ? " dirty" : "",
155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 if (obj->base.name)
157 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 159 if (vma->pin_count > 0)
160 pin_count++;
ba0635ff
DC		 161 }
162 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 163 if (obj->pin_display)
164 seq_printf(m, " (display)");
37811fcc
CW		 165 if (obj->fence_reg != I915_FENCE_REG_NONE)
166 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc 167 list_for_each_entry(vma, &obj->vma_list, vma_link) {
8d2fdc3f
TU		 168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma->vm) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_is_ggtt(vma->vm))
172 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
1d693bcc 173 else
8d2fdc3f 174 seq_puts(m, ")");
1d693bcc 175 }
c1ad11fc 176 if (obj->stolen)
440fd528 177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 178 if (obj->pin_display || obj->fault_mappable) {
6299f992 179 char s[3], *t = s;
30154650 180 if (obj->pin_display)
6299f992
CW		 181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
b4716185 187 if (obj->last_write_req != NULL)
41c52415 188 seq_printf(m, " (%s)",
b4716185 189 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 192}
193
273497e5 194static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 195{
ea0c76f8 196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199}
200
433e12f7 201static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 202{
9f25d007 203 struct drm_info_node *node = m->private;
433e12f7
BG		 204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
2017263e 206 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 207 struct drm_i915_private *dev_priv = dev->dev_private;
208 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 209 struct i915_vma *vma;
c44ef60e 210 u64 total_obj_size, total_gtt_size;
8f2480fb 211 int count, ret;
de227ef0
CW		 212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
2017263e 216
ca191b13 217 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 218 switch (list) {
219 case ACTIVE_LIST:
267f0c90 220 seq_puts(m, "Active:\n");
5cef07e1 221 head = &vm->active_list;
433e12f7
BG		 222 break;
223 case INACTIVE_LIST:
267f0c90 224 seq_puts(m, "Inactive:\n");
5cef07e1 225 head = &vm->inactive_list;
433e12f7 226 break;
433e12f7 227 default:
de227ef0
CW		 228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
2017263e 230 }
2017263e 231
8f2480fb 232 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 233 list_for_each_entry(vma, head, mm_list) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
8f2480fb 239 count++;
2017263e 240 }
de227ef0 241 mutex_unlock(&dev->struct_mutex);
5e118f41 242
c44ef60e 243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 244 count, total_obj_size, total_gtt_size);
2017263e
BG		 245 return 0;
246}
247
6d2b8885
CW		 248static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250{
251 struct drm_i915_gem_object *a =
b25cb2f8 252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 253 struct drm_i915_gem_object *b =
b25cb2f8 254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 255
2d05fa16
RV		 256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
6d2b8885
CW		 261}
262
263static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264{
9f25d007 265 struct drm_info_node *node = m->private;
6d2b8885
CW		 266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
c44ef60e 269 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
b25cb2f8 282 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 283
284 total_obj_size += obj->base.size;
ca1543be 285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
b25cb2f8 292 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
b25cb2f8 300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
b25cb2f8 304 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 305 }
306 mutex_unlock(&dev->struct_mutex);
307
c44ef60e 308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 309 count, total_obj_size, total_gtt_size);
310 return 0;
311}
312
6299f992
CW		 313#define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
ca1543be 315 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 316 ++count; \
317 if (obj->map_and_fenceable) { \
f343c5f6 318 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 319 ++mappable_count; \
320 } \
321 } \
0206e353 322} while (0)
6299f992 323
2db8e9d6 324struct file_stats {
6313c204 325 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
2db8e9d6
CW		 330};
331
332static int per_file_stats(int id, void *ptr, void *data)
333{
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
6313c204 336 struct i915_vma *vma;
2db8e9d6
CW		 337
338 stats->count++;
339 stats->total += obj->base.size;
340
c67a17e9
CW		 341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
6313c204
CW		 344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, vma_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (i915_is_ggtt(vma->vm)) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 357 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 358 continue;
359
41c52415 360 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
2db8e9d6 367 } else {
6313c204
CW		 368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
41c52415 370 if (obj->active)
6313c204
CW		 371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
2db8e9d6
CW		 376 }
377
6313c204
CW		 378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
2db8e9d6
CW		 381 return 0;
382}
383
b0da1b79
CW		 384#define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
c44ef60e 386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395} while (0)
493018dc
BV		 396
397static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399{
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
06fbca71 402 struct intel_engine_cs *ring;
8d9d5744 403 int i, j;
493018dc
BV		 404
405 memset(&stats, 0, sizeof(stats));
406
06fbca71 407 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 408 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &ring->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
06fbca71 414 }
493018dc 415
b0da1b79 416 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 417}
418
ca191b13
BW		 419#define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
ca1543be 421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428} while (0)
429
430static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 431{
9f25d007 432 struct drm_info_node *node = m->private;
73aa808f
CW		 433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714 435 u32 count, mappable_count, purgeable_count;
c44ef60e 436 u64 size, mappable_size, purgeable_size;
6299f992 437 struct drm_i915_gem_object *obj;
5cef07e1 438 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 439 struct drm_file *file;
ca191b13 440 struct i915_vma *vma;
73aa808f
CW		 441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
6299f992
CW		 447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
35c20a60 452 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
ca191b13 457 count_vmas(&vm->active_list, mm_list);
c44ef60e 458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 459 count, mappable_count, size, mappable_size);
460
6299f992 461 size = count = mappable_size = mappable_count = 0;
ca191b13 462 count_vmas(&vm->inactive_list, mm_list);
c44ef60e 463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 464 count, mappable_count, size, mappable_size);
465
b7abb714 466 size = count = purgeable_size = purgeable_count = 0;
35c20a60 467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 468 size += obj->base.size, ++count;
b7abb714
CW		 469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
c44ef60e 472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 473
6299f992 474 size = count = mappable_size = mappable_count = 0;
35c20a60 475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 476 if (obj->fault_mappable) {
f343c5f6 477 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 478 ++count;
479 }
30154650 480 if (obj->pin_display) {
f343c5f6 481 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 482 ++mappable_count;
483 }
b7abb714
CW		 484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
6299f992 488 }
c44ef60e 489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 490 purgeable_count, purgeable_size);
c44ef60e 491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 492 mappable_count, mappable_size);
c44ef60e 493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 494 count, size);
495
c44ef60e 496 seq_printf(m, "%llu [%llu] gtt total\n",
853ba5d2 497 dev_priv->gtt.base.total,
c44ef60e 498 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 499
493018dc
BV		 500 seq_putc(m, '\n');
501 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 502 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
503 struct file_stats stats;
3ec2f427 504 struct task_struct *task;
2db8e9d6
CW		 505
506 memset(&stats, 0, sizeof(stats));
6313c204 507 stats.file_priv = file->driver_priv;
5b5ffff0 508 spin_lock(&file->table_lock);
2db8e9d6 509 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 510 spin_unlock(&file->table_lock);
3ec2f427
TH		 511 /*
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
516 */
517 rcu_read_lock();
518 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 519 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 520 rcu_read_unlock();
2db8e9d6
CW		 521 }
522
73aa808f
CW		 523 mutex_unlock(&dev->struct_mutex);
524
525 return 0;
526}
527
aee56cff 528static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 529{
9f25d007 530 struct drm_info_node *node = m->private;
08c18323 531 struct drm_device *dev = node->minor->dev;
1b50247a 532 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 533 struct drm_i915_private *dev_priv = dev->dev_private;
534 struct drm_i915_gem_object *obj;
c44ef60e 535 u64 total_obj_size, total_gtt_size;
08c18323
CW		 536 int count, ret;
537
538 ret = mutex_lock_interruptible(&dev->struct_mutex);
539 if (ret)
540 return ret;
541
542 total_obj_size = total_gtt_size = count = 0;
35c20a60 543 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 544 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 545 continue;
546
267f0c90 547 seq_puts(m, " ");
08c18323 548 describe_obj(m, obj);
267f0c90 549 seq_putc(m, '\n');
08c18323 550 total_obj_size += obj->base.size;
ca1543be 551 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 552 count++;
553 }
554
555 mutex_unlock(&dev->struct_mutex);
556
c44ef60e 557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 558 count, total_obj_size, total_gtt_size);
559
560 return 0;
561}
562
4e5359cd
SF		 563static int i915_gem_pageflip_info(struct seq_file *m, void *data)
564{
9f25d007 565 struct drm_info_node *node = m->private;
4e5359cd 566 struct drm_device *dev = node->minor->dev;
d6bbafa1 567 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 568 struct intel_crtc *crtc;
8a270ebf
DV		 569 int ret;
570
571 ret = mutex_lock_interruptible(&dev->struct_mutex);
572 if (ret)
573 return ret;
4e5359cd 574
d3fcc808 575 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 576 const char pipe = pipe_name(crtc->pipe);
577 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 578 struct intel_unpin_work *work;
579
5e2d7afc 580 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 581 work = crtc->unpin_work;
582 if (work == NULL) {
9db4a9c7 583 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 584 pipe, plane);
585 } else {
d6bbafa1
CW		 586 u32 addr;
587
e7d841ca 588 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 589 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 590 pipe, plane);
591 } else {
9db4a9c7 592 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 593 pipe, plane);
594 }
3a8a946e
DV		 595 if (work->flip_queued_req) {
596 struct intel_engine_cs *ring =
597 i915_gem_request_get_ring(work->flip_queued_req);
598
20e28fba 599 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 600 ring->name,
f06cc1b9 601 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 602 dev_priv->next_seqno,
3a8a946e 603 ring->get_seqno(ring, true),
1b5a433a 604 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 605 } else
606 seq_printf(m, "Flip not associated with any ring\n");
607 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work->flip_queued_vblank,
609 work->flip_ready_vblank,
1e3feefd 610 drm_crtc_vblank_count(&crtc->base));
4e5359cd 611 if (work->enable_stall_check)
267f0c90 612 seq_puts(m, "Stall check enabled, ");
4e5359cd 613 else
267f0c90 614 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 615 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 616
d6bbafa1
CW		 617 if (INTEL_INFO(dev)->gen >= 4)
618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
619 else
620 addr = I915_READ(DSPADDR(crtc->plane));
621 seq_printf(m, "Current scanout address 0x%08x\n", addr);
622
4e5359cd 623 if (work->pending_flip_obj) {
d6bbafa1
CW		 624 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
625 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 626 }
627 }
5e2d7afc 628 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 629 }
630
8a270ebf
DV		 631 mutex_unlock(&dev->struct_mutex);
632
4e5359cd
SF		 633 return 0;
634}
635
493018dc
BV		 636static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
637{
638 struct drm_info_node *node = m->private;
639 struct drm_device *dev = node->minor->dev;
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 struct drm_i915_gem_object *obj;
06fbca71 642 struct intel_engine_cs *ring;
8d9d5744
CW		 643 int total = 0;
644 int ret, i, j;
493018dc
BV		 645
646 ret = mutex_lock_interruptible(&dev->struct_mutex);
647 if (ret)
648 return ret;
649
06fbca71 650 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 651 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
652 int count;
653
654 count = 0;
655 list_for_each_entry(obj,
656 &ring->batch_pool.cache_list[j],
657 batch_pool_link)
658 count++;
659 seq_printf(m, "%s cache[%d]: %d objects\n",
660 ring->name, j, count);
661
662 list_for_each_entry(obj,
663 &ring->batch_pool.cache_list[j],
664 batch_pool_link) {
665 seq_puts(m, " ");
666 describe_obj(m, obj);
667 seq_putc(m, '\n');
668 }
669
670 total += count;
06fbca71 671 }
493018dc
BV		 672 }
673
8d9d5744 674 seq_printf(m, "total: %d\n", total);
493018dc
BV		 675
676 mutex_unlock(&dev->struct_mutex);
677
678 return 0;
679}
680
2017263e
BG		 681static int i915_gem_request_info(struct seq_file *m, void *data)
682{
9f25d007 683 struct drm_info_node *node = m->private;
2017263e 684 struct drm_device *dev = node->minor->dev;
e277a1f8 685 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 686 struct intel_engine_cs *ring;
eed29a5b 687 struct drm_i915_gem_request *req;
2d1070b2 688 int ret, any, i;
de227ef0
CW		 689
690 ret = mutex_lock_interruptible(&dev->struct_mutex);
691 if (ret)
692 return ret;
2017263e 693
2d1070b2 694 any = 0;
a2c7f6fd 695 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 696 int count;
697
698 count = 0;
eed29a5b 699 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 700 count++;
701 if (count == 0)
a2c7f6fd
CW		 702 continue;
703
2d1070b2 704 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 705 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 706 struct task_struct *task;
707
708 rcu_read_lock();
709 task = NULL;
eed29a5b
DV		 710 if (req->pid)
711 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 712 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 713 req->seqno,
714 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 715 task ? task->comm : "<unknown>",
716 task ? task->pid : -1);
717 rcu_read_unlock();
c2c347a9 718 }
2d1070b2
CW		 719
720 any++;
2017263e 721 }
de227ef0
CW		 722 mutex_unlock(&dev->struct_mutex);
723
2d1070b2 724 if (any == 0)
267f0c90 725 seq_puts(m, "No requests\n");
c2c347a9 726
2017263e
BG		 727 return 0;
728}
729
b2223497 730static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 731 struct intel_engine_cs *ring)
b2223497
CW		 732{
733 if (ring->get_seqno) {
20e28fba 734 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 735 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 736 }
737}
738
2017263e
BG		 739static int i915_gem_seqno_info(struct seq_file *m, void *data)
740{
9f25d007 741 struct drm_info_node *node = m->private;
2017263e 742 struct drm_device *dev = node->minor->dev;
e277a1f8 743 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 744 struct intel_engine_cs *ring;
1ec14ad3 745 int ret, i;
de227ef0
CW		 746
747 ret = mutex_lock_interruptible(&dev->struct_mutex);
748 if (ret)
749 return ret;
c8c8fb33 750 intel_runtime_pm_get(dev_priv);
2017263e 751
a2c7f6fd
CW		 752 for_each_ring(ring, dev_priv, i)
753 i915_ring_seqno_info(m, ring);
de227ef0 754
c8c8fb33 755 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 756 mutex_unlock(&dev->struct_mutex);
757
2017263e
BG		 758 return 0;
759}
760
761
762static int i915_interrupt_info(struct seq_file *m, void *data)
763{
9f25d007 764 struct drm_info_node *node = m->private;
2017263e 765 struct drm_device *dev = node->minor->dev;
e277a1f8 766 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 767 struct intel_engine_cs *ring;
9db4a9c7 768 int ret, i, pipe;
de227ef0
CW		 769
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 if (ret)
772 return ret;
c8c8fb33 773 intel_runtime_pm_get(dev_priv);
2017263e 774
74e1ca8c 775 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 776 seq_printf(m, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ));
778
779 seq_printf(m, "Display IER:\t%08x\n",
780 I915_READ(VLV_IER));
781 seq_printf(m, "Display IIR:\t%08x\n",
782 I915_READ(VLV_IIR));
783 seq_printf(m, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW));
785 seq_printf(m, "Display IMR:\t%08x\n",
786 I915_READ(VLV_IMR));
055e393f 787 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 788 seq_printf(m, "Pipe %c stat:\t%08x\n",
789 pipe_name(pipe),
790 I915_READ(PIPESTAT(pipe)));
791
792 seq_printf(m, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN));
794 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT));
796 seq_printf(m, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
808 seq_printf(m, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR));
810 seq_printf(m, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR));
812 seq_printf(m, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER));
814 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 815 seq_printf(m, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ));
817
818 for (i = 0; i < 4; i++) {
819 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IMR(i)));
821 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IIR(i)));
823 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
824 i, I915_READ(GEN8_GT_IER(i)));
825 }
826
055e393f 827 for_each_pipe(dev_priv, pipe) {
f458ebbc 828 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 829 POWER_DOMAIN_PIPE(pipe))) {
830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
a123f157 834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 840 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 843 }
844
845 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR));
847 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR));
849 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER));
851
852 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR));
854 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR));
856 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER));
858
859 seq_printf(m, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR));
861 seq_printf(m, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR));
863 seq_printf(m, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER));
865 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 866 seq_printf(m, "Display IER:\t%08x\n",
867 I915_READ(VLV_IER));
868 seq_printf(m, "Display IIR:\t%08x\n",
869 I915_READ(VLV_IIR));
870 seq_printf(m, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW));
872 seq_printf(m, "Display IMR:\t%08x\n",
873 I915_READ(VLV_IMR));
055e393f 874 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 875 seq_printf(m, "Pipe %c stat:\t%08x\n",
876 pipe_name(pipe),
877 I915_READ(PIPESTAT(pipe)));
878
879 seq_printf(m, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER));
881
882 seq_printf(m, "Render IER:\t%08x\n",
883 I915_READ(GTIER));
884 seq_printf(m, "Render IIR:\t%08x\n",
885 I915_READ(GTIIR));
886 seq_printf(m, "Render IMR:\t%08x\n",
887 I915_READ(GTIMR));
888
889 seq_printf(m, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER));
891 seq_printf(m, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR));
893 seq_printf(m, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR));
895
896 seq_printf(m, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN));
898 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT));
900 seq_printf(m, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT));
902
903 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 904 seq_printf(m, "Interrupt enable: %08x\n",
905 I915_READ(IER));
906 seq_printf(m, "Interrupt identity: %08x\n",
907 I915_READ(IIR));
908 seq_printf(m, "Interrupt mask: %08x\n",
909 I915_READ(IMR));
055e393f 910 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 911 seq_printf(m, "Pipe %c stat: %08x\n",
912 pipe_name(pipe),
913 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 914 } else {
915 seq_printf(m, "North Display Interrupt enable: %08x\n",
916 I915_READ(DEIER));
917 seq_printf(m, "North Display Interrupt identity: %08x\n",
918 I915_READ(DEIIR));
919 seq_printf(m, "North Display Interrupt mask: %08x\n",
920 I915_READ(DEIMR));
921 seq_printf(m, "South Display Interrupt enable: %08x\n",
922 I915_READ(SDEIER));
923 seq_printf(m, "South Display Interrupt identity: %08x\n",
924 I915_READ(SDEIIR));
925 seq_printf(m, "South Display Interrupt mask: %08x\n",
926 I915_READ(SDEIMR));
927 seq_printf(m, "Graphics Interrupt enable: %08x\n",
928 I915_READ(GTIER));
929 seq_printf(m, "Graphics Interrupt identity: %08x\n",
930 I915_READ(GTIIR));
931 seq_printf(m, "Graphics Interrupt mask: %08x\n",
932 I915_READ(GTIMR));
933 }
a2c7f6fd 934 for_each_ring(ring, dev_priv, i) {
a123f157 935 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 936 seq_printf(m,
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring->name, I915_READ_IMR(ring));
9862e600 939 }
a2c7f6fd 940 i915_ring_seqno_info(m, ring);
9862e600 941 }
c8c8fb33 942 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 943 mutex_unlock(&dev->struct_mutex);
944
2017263e
BG		 945 return 0;
946}
947
a6172a80
CW		 948static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
949{
9f25d007 950 struct drm_info_node *node = m->private;
a6172a80 951 struct drm_device *dev = node->minor->dev;
e277a1f8 952 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 953 int i, ret;
954
955 ret = mutex_lock_interruptible(&dev->struct_mutex);
956 if (ret)
957 return ret;
a6172a80 958
a6172a80
CW		 959 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
960 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 961 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 962
6c085a72
CW		 963 seq_printf(m, "Fence %d, pin count = %d, object = ",
964 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 965 if (obj == NULL)
267f0c90 966 seq_puts(m, "unused");
c2c347a9 967 else
05394f39 968 describe_obj(m, obj);
267f0c90 969 seq_putc(m, '\n');
a6172a80
CW		 970 }
971
05394f39 972 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 973 return 0;
974}
975
2017263e
BG		 976static int i915_hws_info(struct seq_file *m, void *data)
977{
9f25d007 978 struct drm_info_node *node = m->private;
2017263e 979 struct drm_device *dev = node->minor->dev;
e277a1f8 980 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 981 struct intel_engine_cs *ring;
1a240d4d 982 const u32 *hws;
4066c0ae
CW		 983 int i;
984
1ec14ad3 985 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 986 hws = ring->status_page.page_addr;
2017263e
BG		 987 if (hws == NULL)
988 return 0;
989
990 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
991 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
992 i * 4,
993 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
994 }
995 return 0;
996}
997
d5442303
DV		 998static ssize_t
999i915_error_state_write(struct file *filp,
1000 const char __user *ubuf,
1001 size_t cnt,
1002 loff_t *ppos)
1003{
edc3d884 1004 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1005 struct drm_device *dev = error_priv->dev;
22bcfc6a 1006 int ret;
d5442303
DV		 1007
1008 DRM_DEBUG_DRIVER("Resetting error state\n");
1009
22bcfc6a
DV		 1010 ret = mutex_lock_interruptible(&dev->struct_mutex);
1011 if (ret)
1012 return ret;
1013
d5442303
DV		 1014 i915_destroy_error_state(dev);
1015 mutex_unlock(&dev->struct_mutex);
1016
1017 return cnt;
1018}
1019
1020static int i915_error_state_open(struct inode *inode, struct file *file)
1021{
1022 struct drm_device *dev = inode->i_private;
d5442303 1023 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1024
1025 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1026 if (!error_priv)
1027 return -ENOMEM;
1028
1029 error_priv->dev = dev;
1030
95d5bfb3 1031 i915_error_state_get(dev, error_priv);
d5442303 1032
edc3d884
MK		 1033 file->private_data = error_priv;
1034
1035 return 0;
d5442303
DV		 1036}
1037
1038static int i915_error_state_release(struct inode *inode, struct file *file)
1039{
edc3d884 1040 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1041
95d5bfb3 1042 i915_error_state_put(error_priv);
d5442303
DV		 1043 kfree(error_priv);
1044
edc3d884
MK		 1045 return 0;
1046}
1047
4dc955f7
MK		 1048static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1049 size_t count, loff_t *pos)
1050{
1051 struct i915_error_state_file_priv *error_priv = file->private_data;
1052 struct drm_i915_error_state_buf error_str;
1053 loff_t tmp_pos = 0;
1054 ssize_t ret_count = 0;
1055 int ret;
1056
0a4cd7c8 1057 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1058 if (ret)
1059 return ret;
edc3d884 1060
fc16b48b 1061 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1062 if (ret)
1063 goto out;
1064
edc3d884
MK		 1065 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1066 error_str.buf,
1067 error_str.bytes);
1068
1069 if (ret_count < 0)
1070 ret = ret_count;
1071 else
1072 *pos = error_str.start + ret_count;
1073out:
4dc955f7 1074 i915_error_state_buf_release(&error_str);
edc3d884 1075 return ret ?: ret_count;
d5442303
DV		 1076}
1077
1078static const struct file_operations i915_error_state_fops = {
1079 .owner = THIS_MODULE,
1080 .open = i915_error_state_open,
edc3d884 1081 .read = i915_error_state_read,
d5442303
DV		 1082 .write = i915_error_state_write,
1083 .llseek = default_llseek,
1084 .release = i915_error_state_release,
1085};
1086
647416f9
KC		 1087static int
1088i915_next_seqno_get(void *data, u64 *val)
40633219 1089{
647416f9 1090 struct drm_device *dev = data;
e277a1f8 1091 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1092 int ret;
1093
1094 ret = mutex_lock_interruptible(&dev->struct_mutex);
1095 if (ret)
1096 return ret;
1097
647416f9 1098 *val = dev_priv->next_seqno;
40633219
MK		 1099 mutex_unlock(&dev->struct_mutex);
1100
647416f9 1101 return 0;
40633219
MK		 1102}
1103
647416f9
KC		 1104static int
1105i915_next_seqno_set(void *data, u64 val)
1106{
1107 struct drm_device *dev = data;
40633219
MK		 1108 int ret;
1109
40633219
MK		 1110 ret = mutex_lock_interruptible(&dev->struct_mutex);
1111 if (ret)
1112 return ret;
1113
e94fbaa8 1114 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1115 mutex_unlock(&dev->struct_mutex);
1116
647416f9 1117 return ret;
40633219
MK		 1118}
1119
647416f9
KC		 1120DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1121 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1122 "0x%llx\n");
40633219 1123
adb4bd12 1124static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1125{
9f25d007 1126 struct drm_info_node *node = m->private;
f97108d1 1127 struct drm_device *dev = node->minor->dev;
e277a1f8 1128 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1129 int ret = 0;
1130
1131 intel_runtime_pm_get(dev_priv);
3b8d8d91 1132
5c9669ce
TR		 1133 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1134
3b8d8d91
JB		 1135 if (IS_GEN5(dev)) {
1136 u16 rgvswctl = I915_READ16(MEMSWCTL);
1137 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1138
1139 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1140 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1141 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1142 MEMSTAT_VID_SHIFT);
1143 seq_printf(m, "Current P-state: %d\n",
1144 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
666a4537
WB		 1145 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1146 u32 freq_sts;
1147
1148 mutex_lock(&dev_priv->rps.hw_lock);
1149 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1150 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1151 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1152
1153 seq_printf(m, "actual GPU freq: %d MHz\n",
1154 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1155
1156 seq_printf(m, "current GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1158
1159 seq_printf(m, "max GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1161
1162 seq_printf(m, "min GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1164
1165 seq_printf(m, "idle GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1167
1168 seq_printf(m,
1169 "efficient (RPe) frequency: %d MHz\n",
1170 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1171 mutex_unlock(&dev_priv->rps.hw_lock);
1172 } else if (INTEL_INFO(dev)->gen >= 6) {
35040562
BP		 1173 u32 rp_state_limits;
1174 u32 gt_perf_status;
1175 u32 rp_state_cap;
0d8f9491 1176 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1177 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1178 u32 rpupei, rpcurup, rpprevup;
1179 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1180 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1181 int max_freq;
1182
35040562
BP		 1183 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1184 if (IS_BROXTON(dev)) {
1185 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1186 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1187 } else {
1188 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1189 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1190 }
1191
3b8d8d91 1192 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1193 ret = mutex_lock_interruptible(&dev->struct_mutex);
1194 if (ret)
c8c8fb33 1195 goto out;
d1ebd816 1196
59bad947 1197 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1198
8e8c06cd 1199 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1200 if (IS_GEN9(dev))
1201 reqf >>= 23;
1202 else {
1203 reqf &= ~GEN6_TURBO_DISABLE;
1204 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1205 reqf >>= 24;
1206 else
1207 reqf >>= 25;
1208 }
7c59a9c1 1209 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1210
0d8f9491
CW		 1211 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1212 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1213 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1214
ccab5c82
JB		 1215 rpstat = I915_READ(GEN6_RPSTAT1);
1216 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1217 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1218 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1219 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1220 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1221 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1222 if (IS_GEN9(dev))
1223 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1224 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1225 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1226 else
1227 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1228 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1229
59bad947 1230 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1231 mutex_unlock(&dev->struct_mutex);
1232
9dd3c605
PZ		 1233 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1234 pm_ier = I915_READ(GEN6_PMIER);
1235 pm_imr = I915_READ(GEN6_PMIMR);
1236 pm_isr = I915_READ(GEN6_PMISR);
1237 pm_iir = I915_READ(GEN6_PMIIR);
1238 pm_mask = I915_READ(GEN6_PMINTRMSK);
1239 } else {
1240 pm_ier = I915_READ(GEN8_GT_IER(2));
1241 pm_imr = I915_READ(GEN8_GT_IMR(2));
1242 pm_isr = I915_READ(GEN8_GT_ISR(2));
1243 pm_iir = I915_READ(GEN8_GT_IIR(2));
1244 pm_mask = I915_READ(GEN6_PMINTRMSK);
1245 }
0d8f9491 1246 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1247 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1248 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1249 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1250 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1251 seq_printf(m, "Render p-state VID: %d\n",
1252 gt_perf_status & 0xff);
1253 seq_printf(m, "Render p-state limit: %d\n",
1254 rp_state_limits & 0xff);
0d8f9491
CW		 1255 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1256 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1257 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1258 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1259 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1260 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1261 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1262 GEN6_CURICONT_MASK);
1263 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1264 GEN6_CURBSYTAVG_MASK);
1265 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1266 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1267 seq_printf(m, "Up threshold: %d%%\n",
1268 dev_priv->rps.up_threshold);
1269
ccab5c82
JB		 1270 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1271 GEN6_CURIAVG_MASK);
1272 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1273 GEN6_CURBSYTAVG_MASK);
1274 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1275 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1276 seq_printf(m, "Down threshold: %d%%\n",
1277 dev_priv->rps.down_threshold);
3b8d8d91 1278
35040562
BP		 1279 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1280 rp_state_cap >> 16) & 0xff;
ef11bdb3
RV		 1281 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1282 GEN9_FREQ_SCALER : 1);
3b8d8d91 1283 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1284 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1285
1286 max_freq = (rp_state_cap & 0xff00) >> 8;
ef11bdb3
RV		 1287 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1288 GEN9_FREQ_SCALER : 1);
3b8d8d91 1289 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1290 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1291
35040562
BP		 1292 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1293 rp_state_cap >> 0) & 0xff;
ef11bdb3
RV		 1294 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1295 GEN9_FREQ_SCALER : 1);
3b8d8d91 1296 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1297 intel_gpu_freq(dev_priv, max_freq));
31c77388 1298 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1299 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1300
d86ed34a
CW		 1301 seq_printf(m, "Current freq: %d MHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1303 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1304 seq_printf(m, "Idle freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1306 seq_printf(m, "Min freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1308 seq_printf(m, "Max freq: %d MHz\n",
1309 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1310 seq_printf(m,
1311 "efficient (RPe) frequency: %d MHz\n",
1312 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
3b8d8d91 1313 } else {
267f0c90 1314 seq_puts(m, "no P-state info available\n");
3b8d8d91 1315 }
f97108d1 1316
1170f28c
MK		 1317 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1318 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1319 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1320
c8c8fb33
PZ		 1321out:
1322 intel_runtime_pm_put(dev_priv);
1323 return ret;
f97108d1
JB		 1324}
1325
f654449a
CW		 1326static int i915_hangcheck_info(struct seq_file *m, void *unused)
1327{
1328 struct drm_info_node *node = m->private;
ebbc7546
MK		 1329 struct drm_device *dev = node->minor->dev;
1330 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1331 struct intel_engine_cs *ring;
ebbc7546
MK		 1332 u64 acthd[I915_NUM_RINGS];
1333 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1334 int i;
1335
1336 if (!i915.enable_hangcheck) {
1337 seq_printf(m, "Hangcheck disabled\n");
1338 return 0;
1339 }
1340
ebbc7546
MK		 1341 intel_runtime_pm_get(dev_priv);
1342
1343 for_each_ring(ring, dev_priv, i) {
1344 seqno[i] = ring->get_seqno(ring, false);
1345 acthd[i] = intel_ring_get_active_head(ring);
1346 }
1347
1348 intel_runtime_pm_put(dev_priv);
1349
f654449a
CW		 1350 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1351 seq_printf(m, "Hangcheck active, fires in %dms\n",
1352 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1353 jiffies));
1354 } else
1355 seq_printf(m, "Hangcheck inactive\n");
1356
1357 for_each_ring(ring, dev_priv, i) {
1358 seq_printf(m, "%s:\n", ring->name);
1359 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1360 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1361 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1362 (long long)ring->hangcheck.acthd,
ebbc7546 1363 (long long)acthd[i]);
f654449a
CW		 1364 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1365 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1366 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1367 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1368 }
1369
1370 return 0;
1371}
1372
4d85529d 1373static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1374{
9f25d007 1375 struct drm_info_node *node = m->private;
f97108d1 1376 struct drm_device *dev = node->minor->dev;
e277a1f8 1377 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1378 u32 rgvmodectl, rstdbyctl;
1379 u16 crstandvid;
1380 int ret;
1381
1382 ret = mutex_lock_interruptible(&dev->struct_mutex);
1383 if (ret)
1384 return ret;
c8c8fb33 1385 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1386
1387 rgvmodectl = I915_READ(MEMMODECTL);
1388 rstdbyctl = I915_READ(RSTDBYCTL);
1389 crstandvid = I915_READ16(CRSTANDVID);
1390
c8c8fb33 1391 intel_runtime_pm_put(dev_priv);
616fdb5a 1392 mutex_unlock(&dev->struct_mutex);
f97108d1 1393
742f491d 1394 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1395 seq_printf(m, "Boost freq: %d\n",
1396 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1397 MEMMODE_BOOST_FREQ_SHIFT);
1398 seq_printf(m, "HW control enabled: %s\n",
742f491d 1399 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1400 seq_printf(m, "SW control enabled: %s\n",
742f491d 1401 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1402 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1403 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1404 seq_printf(m, "Starting frequency: P%d\n",
1405 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1406 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1407 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1408 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1409 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1410 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1411 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1412 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1413 seq_puts(m, "Current RS state: ");
88271da3
JB		 1414 switch (rstdbyctl & RSX_STATUS_MASK) {
1415 case RSX_STATUS_ON:
267f0c90 1416 seq_puts(m, "on\n");
88271da3
JB		 1417 break;
1418 case RSX_STATUS_RC1:
267f0c90 1419 seq_puts(m, "RC1\n");
88271da3
JB		 1420 break;
1421 case RSX_STATUS_RC1E:
267f0c90 1422 seq_puts(m, "RC1E\n");
88271da3
JB		 1423 break;
1424 case RSX_STATUS_RS1:
267f0c90 1425 seq_puts(m, "RS1\n");
88271da3
JB		 1426 break;
1427 case RSX_STATUS_RS2:
267f0c90 1428 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1429 break;
1430 case RSX_STATUS_RS3:
267f0c90 1431 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1432 break;
1433 default:
267f0c90 1434 seq_puts(m, "unknown\n");
88271da3
JB		 1435 break;
1436 }
f97108d1
JB		 1437
1438 return 0;
1439}
1440
f65367b5 1441static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1442{
b2cff0db
CW		 1443 struct drm_info_node *node = m->private;
1444 struct drm_device *dev = node->minor->dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1447 int i;
1448
1449 spin_lock_irq(&dev_priv->uncore.lock);
1450 for_each_fw_domain(fw_domain, dev_priv, i) {
1451 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1452 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1453 fw_domain->wake_count);
1454 }
1455 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1456
b2cff0db
CW		 1457 return 0;
1458}
1459
1460static int vlv_drpc_info(struct seq_file *m)
1461{
9f25d007 1462 struct drm_info_node *node = m->private;
669ab5aa
D		 1463 struct drm_device *dev = node->minor->dev;
1464 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1465 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1466
d46c0517
ID		 1467 intel_runtime_pm_get(dev_priv);
1468
6b312cd3 1469 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1470 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1471 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1472
d46c0517
ID		 1473 intel_runtime_pm_put(dev_priv);
1474
669ab5aa
D		 1475 seq_printf(m, "Video Turbo Mode: %s\n",
1476 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1477 seq_printf(m, "Turbo enabled: %s\n",
1478 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1479 seq_printf(m, "HW control enabled: %s\n",
1480 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1481 seq_printf(m, "SW control enabled: %s\n",
1482 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1483 GEN6_RP_MEDIA_SW_MODE));
1484 seq_printf(m, "RC6 Enabled: %s\n",
1485 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1486 GEN6_RC_CTL_EI_MODE(1))));
1487 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1488 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1489 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1490 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1491
9cc19be5
ID		 1492 seq_printf(m, "Render RC6 residency since boot: %u\n",
1493 I915_READ(VLV_GT_RENDER_RC6));
1494 seq_printf(m, "Media RC6 residency since boot: %u\n",
1495 I915_READ(VLV_GT_MEDIA_RC6));
1496
f65367b5 1497 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1498}
1499
4d85529d
BW		 1500static int gen6_drpc_info(struct seq_file *m)
1501{
9f25d007 1502 struct drm_info_node *node = m->private;
4d85529d
BW		 1503 struct drm_device *dev = node->minor->dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1505 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1506 unsigned forcewake_count;
aee56cff 1507 int count = 0, ret;
4d85529d
BW		 1508
1509 ret = mutex_lock_interruptible(&dev->struct_mutex);
1510 if (ret)
1511 return ret;
c8c8fb33 1512 intel_runtime_pm_get(dev_priv);
4d85529d 1513
907b28c5 1514 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1515 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1516 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1517
1518 if (forcewake_count) {
267f0c90
DL		 1519 seq_puts(m, "RC information inaccurate because somebody "
1520 "holds a forcewake reference \n");
4d85529d
BW		 1521 } else {
1522 /* NB: we cannot use forcewake, else we read the wrong values */
1523 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1524 udelay(10);
1525 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1526 }
1527
75aa3f63 1528 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1529 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1530
1531 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1532 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1533 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1534 mutex_lock(&dev_priv->rps.hw_lock);
1535 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1536 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1537
c8c8fb33
PZ		 1538 intel_runtime_pm_put(dev_priv);
1539
4d85529d
BW		 1540 seq_printf(m, "Video Turbo Mode: %s\n",
1541 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1542 seq_printf(m, "HW control enabled: %s\n",
1543 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1544 seq_printf(m, "SW control enabled: %s\n",
1545 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1546 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1547 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1548 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1549 seq_printf(m, "RC6 Enabled: %s\n",
1550 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1551 seq_printf(m, "Deep RC6 Enabled: %s\n",
1552 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1553 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1554 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1555 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1556 switch (gt_core_status & GEN6_RCn_MASK) {
1557 case GEN6_RC0:
1558 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1559 seq_puts(m, "Core Power Down\n");
4d85529d 1560 else
267f0c90 1561 seq_puts(m, "on\n");
4d85529d
BW		 1562 break;
1563 case GEN6_RC3:
267f0c90 1564 seq_puts(m, "RC3\n");
4d85529d
BW		 1565 break;
1566 case GEN6_RC6:
267f0c90 1567 seq_puts(m, "RC6\n");
4d85529d
BW		 1568 break;
1569 case GEN6_RC7:
267f0c90 1570 seq_puts(m, "RC7\n");
4d85529d
BW		 1571 break;
1572 default:
267f0c90 1573 seq_puts(m, "Unknown\n");
4d85529d
BW		 1574 break;
1575 }
1576
1577 seq_printf(m, "Core Power Down: %s\n",
1578 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1579
1580 /* Not exactly sure what this is */
1581 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1582 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1583 seq_printf(m, "RC6 residency since boot: %u\n",
1584 I915_READ(GEN6_GT_GFX_RC6));
1585 seq_printf(m, "RC6+ residency since boot: %u\n",
1586 I915_READ(GEN6_GT_GFX_RC6p));
1587 seq_printf(m, "RC6++ residency since boot: %u\n",
1588 I915_READ(GEN6_GT_GFX_RC6pp));
1589
ecd8faea
BW		 1590 seq_printf(m, "RC6 voltage: %dmV\n",
1591 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1592 seq_printf(m, "RC6+ voltage: %dmV\n",
1593 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1594 seq_printf(m, "RC6++ voltage: %dmV\n",
1595 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1596 return 0;
1597}
1598
1599static int i915_drpc_info(struct seq_file *m, void *unused)
1600{
9f25d007 1601 struct drm_info_node *node = m->private;
4d85529d
BW		 1602 struct drm_device *dev = node->minor->dev;
1603
666a4537 1604 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
669ab5aa 1605 return vlv_drpc_info(m);
ac66cf4b 1606 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1607 return gen6_drpc_info(m);
1608 else
1609 return ironlake_drpc_info(m);
1610}
1611
9a851789
DV		 1612static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1613{
1614 struct drm_info_node *node = m->private;
1615 struct drm_device *dev = node->minor->dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617
1618 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1619 dev_priv->fb_tracking.busy_bits);
1620
1621 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1622 dev_priv->fb_tracking.flip_bits);
1623
1624 return 0;
1625}
1626
b5e50c3f
JB		 1627static int i915_fbc_status(struct seq_file *m, void *unused)
1628{
9f25d007 1629 struct drm_info_node *node = m->private;
b5e50c3f 1630 struct drm_device *dev = node->minor->dev;
e277a1f8 1631 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1632
3a77c4c4 1633 if (!HAS_FBC(dev)) {
267f0c90 1634 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1635 return 0;
1636 }
1637
36623ef8 1638 intel_runtime_pm_get(dev_priv);
25ad93fd 1639 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1640
0e631adc 1641 if (intel_fbc_is_active(dev_priv))
267f0c90 1642 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1643 else
1644 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1645 dev_priv->fbc.no_fbc_reason);
36623ef8 1646
31b9df10
PZ		 1647 if (INTEL_INFO(dev_priv)->gen >= 7)
1648 seq_printf(m, "Compressing: %s\n",
1649 yesno(I915_READ(FBC_STATUS2) &
1650 FBC_COMPRESSION_MASK));
1651
25ad93fd 1652 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1653 intel_runtime_pm_put(dev_priv);
1654
b5e50c3f
JB		 1655 return 0;
1656}
1657
da46f936
RV		 1658static int i915_fbc_fc_get(void *data, u64 *val)
1659{
1660 struct drm_device *dev = data;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662
1663 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1664 return -ENODEV;
1665
da46f936 1666 *val = dev_priv->fbc.false_color;
da46f936
RV		 1667
1668 return 0;
1669}
1670
1671static int i915_fbc_fc_set(void *data, u64 val)
1672{
1673 struct drm_device *dev = data;
1674 struct drm_i915_private *dev_priv = dev->dev_private;
1675 u32 reg;
1676
1677 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1678 return -ENODEV;
1679
25ad93fd 1680 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1681
1682 reg = I915_READ(ILK_DPFC_CONTROL);
1683 dev_priv->fbc.false_color = val;
1684
1685 I915_WRITE(ILK_DPFC_CONTROL, val ?
1686 (reg | FBC_CTL_FALSE_COLOR) :
1687 (reg & ~FBC_CTL_FALSE_COLOR));
1688
25ad93fd 1689 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1690 return 0;
1691}
1692
1693DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1694 i915_fbc_fc_get, i915_fbc_fc_set,
1695 "%llu\n");
1696
92d44621
PZ		 1697static int i915_ips_status(struct seq_file *m, void *unused)
1698{
9f25d007 1699 struct drm_info_node *node = m->private;
92d44621
PZ		 1700 struct drm_device *dev = node->minor->dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702
f5adf94e 1703 if (!HAS_IPS(dev)) {
92d44621
PZ		 1704 seq_puts(m, "not supported\n");
1705 return 0;
1706 }
1707
36623ef8
PZ		 1708 intel_runtime_pm_get(dev_priv);
1709
0eaa53f0
RV		 1710 seq_printf(m, "Enabled by kernel parameter: %s\n",
1711 yesno(i915.enable_ips));
1712
1713 if (INTEL_INFO(dev)->gen >= 8) {
1714 seq_puts(m, "Currently: unknown\n");
1715 } else {
1716 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1717 seq_puts(m, "Currently: enabled\n");
1718 else
1719 seq_puts(m, "Currently: disabled\n");
1720 }
92d44621 1721
36623ef8
PZ		 1722 intel_runtime_pm_put(dev_priv);
1723
92d44621
PZ		 1724 return 0;
1725}
1726
4a9bef37
JB		 1727static int i915_sr_status(struct seq_file *m, void *unused)
1728{
9f25d007 1729 struct drm_info_node *node = m->private;
4a9bef37 1730 struct drm_device *dev = node->minor->dev;
e277a1f8 1731 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1732 bool sr_enabled = false;
1733
36623ef8
PZ		 1734 intel_runtime_pm_get(dev_priv);
1735
1398261a 1736 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1737 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1738 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1739 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1740 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1741 else if (IS_I915GM(dev))
1742 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1743 else if (IS_PINEVIEW(dev))
1744 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
666a4537 1745 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
77b64555 1746 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1747
36623ef8
PZ		 1748 intel_runtime_pm_put(dev_priv);
1749
5ba2aaaa
CW		 1750 seq_printf(m, "self-refresh: %s\n",
1751 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1752
1753 return 0;
1754}
1755
7648fa99
JB		 1756static int i915_emon_status(struct seq_file *m, void *unused)
1757{
9f25d007 1758 struct drm_info_node *node = m->private;
7648fa99 1759 struct drm_device *dev = node->minor->dev;
e277a1f8 1760 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1761 unsigned long temp, chipset, gfx;
de227ef0
CW		 1762 int ret;
1763
582be6b4
CW		 1764 if (!IS_GEN5(dev))
1765 return -ENODEV;
1766
de227ef0
CW		 1767 ret = mutex_lock_interruptible(&dev->struct_mutex);
1768 if (ret)
1769 return ret;
7648fa99
JB		 1770
1771 temp = i915_mch_val(dev_priv);
1772 chipset = i915_chipset_val(dev_priv);
1773 gfx = i915_gfx_val(dev_priv);
de227ef0 1774 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1775
1776 seq_printf(m, "GMCH temp: %ld\n", temp);
1777 seq_printf(m, "Chipset power: %ld\n", chipset);
1778 seq_printf(m, "GFX power: %ld\n", gfx);
1779 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1780
1781 return 0;
1782}
1783
23b2f8bb
JB		 1784static int i915_ring_freq_table(struct seq_file *m, void *unused)
1785{
9f25d007 1786 struct drm_info_node *node = m->private;
23b2f8bb 1787 struct drm_device *dev = node->minor->dev;
e277a1f8 1788 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1789 int ret = 0;
23b2f8bb 1790 int gpu_freq, ia_freq;
f936ec34 1791 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1792
97d3308a 1793 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1794 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1795 return 0;
1796 }
1797
5bfa0199
PZ		 1798 intel_runtime_pm_get(dev_priv);
1799
5c9669ce
TR		 1800 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1801
4fc688ce 1802 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1803 if (ret)
5bfa0199 1804 goto out;
23b2f8bb 1805
ef11bdb3 1806 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
f936ec34
AG		 1807 /* Convert GT frequency to 50 HZ units */
1808 min_gpu_freq =
1809 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1810 max_gpu_freq =
1811 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1812 } else {
1813 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1814 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1815 }
1816
267f0c90 1817 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1818
f936ec34 1819 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1820 ia_freq = gpu_freq;
1821 sandybridge_pcode_read(dev_priv,
1822 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1823 &ia_freq);
3ebecd07 1824 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1825 intel_gpu_freq(dev_priv, (gpu_freq *
ef11bdb3
RV		 1826 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1827 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1828 ((ia_freq >> 0) & 0xff) * 100,
1829 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1830 }
1831
4fc688ce 1832 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1833
5bfa0199
PZ		 1834out:
1835 intel_runtime_pm_put(dev_priv);
1836 return ret;
23b2f8bb
JB		 1837}
1838
44834a67
CW		 1839static int i915_opregion(struct seq_file *m, void *unused)
1840{
9f25d007 1841 struct drm_info_node *node = m->private;
44834a67 1842 struct drm_device *dev = node->minor->dev;
e277a1f8 1843 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67
CW		 1844 struct intel_opregion *opregion = &dev_priv->opregion;
1845 int ret;
1846
1847 ret = mutex_lock_interruptible(&dev->struct_mutex);
1848 if (ret)
0d38f009 1849 goto out;
44834a67 1850
2455a8e4
JN		 1851 if (opregion->header)
1852 seq_write(m, opregion->header, OPREGION_SIZE);
44834a67
CW		 1853
1854 mutex_unlock(&dev->struct_mutex);
1855
0d38f009 1856out:
44834a67
CW		 1857 return 0;
1858}
1859
ada8f955
JN		 1860static int i915_vbt(struct seq_file *m, void *unused)
1861{
1862 struct drm_info_node *node = m->private;
1863 struct drm_device *dev = node->minor->dev;
1864 struct drm_i915_private *dev_priv = dev->dev_private;
1865 struct intel_opregion *opregion = &dev_priv->opregion;
1866
1867 if (opregion->vbt)
1868 seq_write(m, opregion->vbt, opregion->vbt_size);
1869
1870 return 0;
1871}
1872
37811fcc
CW		 1873static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1874{
9f25d007 1875 struct drm_info_node *node = m->private;
37811fcc 1876 struct drm_device *dev = node->minor->dev;
b13b8402 1877 struct intel_framebuffer *fbdev_fb = NULL;
3a58ee10 1878 struct drm_framebuffer *drm_fb;
37811fcc 1879
0695726e 1880#ifdef CONFIG_DRM_FBDEV_EMULATION
b13b8402
NS		 1881 if (to_i915(dev)->fbdev) {
1882 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1883
1884 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1885 fbdev_fb->base.width,
1886 fbdev_fb->base.height,
1887 fbdev_fb->base.depth,
1888 fbdev_fb->base.bits_per_pixel,
1889 fbdev_fb->base.modifier[0],
1890 atomic_read(&fbdev_fb->base.refcount.refcount));
1891 describe_obj(m, fbdev_fb->obj);
1892 seq_putc(m, '\n');
1893 }
4520f53a 1894#endif
37811fcc 1895
4b096ac1 1896 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10 1897 drm_for_each_fb(drm_fb, dev) {
b13b8402
NS		 1898 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1899 if (fb == fbdev_fb)
37811fcc
CW		 1900 continue;
1901
c1ca506d 1902 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1903 fb->base.width,
1904 fb->base.height,
1905 fb->base.depth,
623f9783 1906 fb->base.bits_per_pixel,
c1ca506d 1907 fb->base.modifier[0],
623f9783 1908 atomic_read(&fb->base.refcount.refcount));
05394f39 1909 describe_obj(m, fb->obj);
267f0c90 1910 seq_putc(m, '\n');
37811fcc 1911 }
4b096ac1 1912 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1913
1914 return 0;
1915}
1916
c9fe99bd
OM		 1917static void describe_ctx_ringbuf(struct seq_file *m,
1918 struct intel_ringbuffer *ringbuf)
1919{
1920 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1921 ringbuf->space, ringbuf->head, ringbuf->tail,
1922 ringbuf->last_retired_head);
1923}
1924
e76d3630
BW		 1925static int i915_context_status(struct seq_file *m, void *unused)
1926{
9f25d007 1927 struct drm_info_node *node = m->private;
e76d3630 1928 struct drm_device *dev = node->minor->dev;
e277a1f8 1929 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1930 struct intel_engine_cs *ring;
273497e5 1931 struct intel_context *ctx;
a168c293 1932 int ret, i;
e76d3630 1933
f3d28878 1934 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1935 if (ret)
1936 return ret;
1937
a33afea5 1938 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1939 if (!i915.enable_execlists &&
1940 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1941 continue;
1942
a33afea5 1943 seq_puts(m, "HW context ");
3ccfd19d 1944 describe_ctx(m, ctx);
c9fe99bd 1945 for_each_ring(ring, dev_priv, i) {
a33afea5 1946 if (ring->default_context == ctx)
c9fe99bd
OM		 1947 seq_printf(m, "(default context %s) ",
1948 ring->name);
1949 }
1950
1951 if (i915.enable_execlists) {
1952 seq_putc(m, '\n');
1953 for_each_ring(ring, dev_priv, i) {
1954 struct drm_i915_gem_object *ctx_obj =
1955 ctx->engine[i].state;
1956 struct intel_ringbuffer *ringbuf =
1957 ctx->engine[i].ringbuf;
1958
1959 seq_printf(m, "%s: ", ring->name);
1960 if (ctx_obj)
1961 describe_obj(m, ctx_obj);
1962 if (ringbuf)
1963 describe_ctx_ringbuf(m, ringbuf);
1964 seq_putc(m, '\n');
1965 }
1966 } else {
1967 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1968 }
a33afea5 1969
a33afea5 1970 seq_putc(m, '\n');
a168c293
BW		 1971 }
1972
f3d28878 1973 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1974
1975 return 0;
1976}
1977
064ca1d2
TD		 1978static void i915_dump_lrc_obj(struct seq_file *m,
1979 struct intel_engine_cs *ring,
1980 struct drm_i915_gem_object *ctx_obj)
1981{
1982 struct page *page;
1983 uint32_t *reg_state;
1984 int j;
1985 unsigned long ggtt_offset = 0;
1986
1987 if (ctx_obj == NULL) {
1988 seq_printf(m, "Context on %s with no gem object\n",
1989 ring->name);
1990 return;
1991 }
1992
1993 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1994 intel_execlists_ctx_id(ctx_obj));
1995
1996 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1997 seq_puts(m, "\tNot bound in GGTT\n");
1998 else
1999 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2000
2001 if (i915_gem_object_get_pages(ctx_obj)) {
2002 seq_puts(m, "\tFailed to get pages for context object\n");
2003 return;
2004 }
2005
d1675198 2006 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 2007 if (!WARN_ON(page == NULL)) {
2008 reg_state = kmap_atomic(page);
2009
2010 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2011 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2012 ggtt_offset + 4096 + (j * 4),
2013 reg_state[j], reg_state[j + 1],
2014 reg_state[j + 2], reg_state[j + 3]);
2015 }
2016 kunmap_atomic(reg_state);
2017 }
2018
2019 seq_putc(m, '\n');
2020}
2021
c0ab1ae9
BW		 2022static int i915_dump_lrc(struct seq_file *m, void *unused)
2023{
2024 struct drm_info_node *node = (struct drm_info_node *) m->private;
2025 struct drm_device *dev = node->minor->dev;
2026 struct drm_i915_private *dev_priv = dev->dev_private;
2027 struct intel_engine_cs *ring;
2028 struct intel_context *ctx;
2029 int ret, i;
2030
2031 if (!i915.enable_execlists) {
2032 seq_printf(m, "Logical Ring Contexts are disabled\n");
2033 return 0;
2034 }
2035
2036 ret = mutex_lock_interruptible(&dev->struct_mutex);
2037 if (ret)
2038 return ret;
2039
2040 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2041 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 2042 if (ring->default_context != ctx)
2043 i915_dump_lrc_obj(m, ring,
2044 ctx->engine[i].state);
c0ab1ae9
BW		 2045 }
2046 }
2047
2048 mutex_unlock(&dev->struct_mutex);
2049
2050 return 0;
2051}
2052
4ba70e44
OM		 2053static int i915_execlists(struct seq_file *m, void *data)
2054{
2055 struct drm_info_node *node = (struct drm_info_node *)m->private;
2056 struct drm_device *dev = node->minor->dev;
2057 struct drm_i915_private *dev_priv = dev->dev_private;
2058 struct intel_engine_cs *ring;
2059 u32 status_pointer;
2060 u8 read_pointer;
2061 u8 write_pointer;
2062 u32 status;
2063 u32 ctx_id;
2064 struct list_head *cursor;
2065 int ring_id, i;
2066 int ret;
2067
2068 if (!i915.enable_execlists) {
2069 seq_puts(m, "Logical Ring Contexts are disabled\n");
2070 return 0;
2071 }
2072
2073 ret = mutex_lock_interruptible(&dev->struct_mutex);
2074 if (ret)
2075 return ret;
2076
fc0412ec
MT		 2077 intel_runtime_pm_get(dev_priv);
2078
4ba70e44 2079 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2080 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2081 int count = 0;
2082 unsigned long flags;
2083
2084 seq_printf(m, "%s\n", ring->name);
2085
83843d84
VS		 2086 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2087 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
4ba70e44
OM		 2088 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2089 status, ctx_id);
2090
2091 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2092 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2093
2094 read_pointer = ring->next_context_status_buffer;
5590a5f0 2095 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
4ba70e44 2096 if (read_pointer > write_pointer)
5590a5f0 2097 write_pointer += GEN8_CSB_ENTRIES;
4ba70e44
OM		 2098 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2099 read_pointer, write_pointer);
2100
5590a5f0 2101 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
83843d84
VS		 2102 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2103 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
4ba70e44
OM		 2104
2105 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2106 i, status, ctx_id);
2107 }
2108
2109 spin_lock_irqsave(&ring->execlist_lock, flags);
2110 list_for_each(cursor, &ring->execlist_queue)
2111 count++;
2112 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2113 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2114 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2115
2116 seq_printf(m, "\t%d requests in queue\n", count);
2117 if (head_req) {
2118 struct drm_i915_gem_object *ctx_obj;
2119
6d3d8274 2120 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2121 seq_printf(m, "\tHead request id: %u\n",
2122 intel_execlists_ctx_id(ctx_obj));
2123 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2124 head_req->tail);
4ba70e44
OM		 2125 }
2126
2127 seq_putc(m, '\n');
2128 }
2129
fc0412ec 2130 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2131 mutex_unlock(&dev->struct_mutex);
2132
2133 return 0;
2134}
2135
ea16a3cd
DV		 2136static const char *swizzle_string(unsigned swizzle)
2137{
aee56cff 2138 switch (swizzle) {
ea16a3cd
DV		 2139 case I915_BIT_6_SWIZZLE_NONE:
2140 return "none";
2141 case I915_BIT_6_SWIZZLE_9:
2142 return "bit9";
2143 case I915_BIT_6_SWIZZLE_9_10:
2144 return "bit9/bit10";
2145 case I915_BIT_6_SWIZZLE_9_11:
2146 return "bit9/bit11";
2147 case I915_BIT_6_SWIZZLE_9_10_11:
2148 return "bit9/bit10/bit11";
2149 case I915_BIT_6_SWIZZLE_9_17:
2150 return "bit9/bit17";
2151 case I915_BIT_6_SWIZZLE_9_10_17:
2152 return "bit9/bit10/bit17";
2153 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2154 return "unknown";
ea16a3cd
DV		 2155 }
2156
2157 return "bug";
2158}
2159
2160static int i915_swizzle_info(struct seq_file *m, void *data)
2161{
9f25d007 2162 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2163 struct drm_device *dev = node->minor->dev;
2164 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2165 int ret;
2166
2167 ret = mutex_lock_interruptible(&dev->struct_mutex);
2168 if (ret)
2169 return ret;
c8c8fb33 2170 intel_runtime_pm_get(dev_priv);
ea16a3cd 2171
ea16a3cd
DV		 2172 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2173 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2174 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2175 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2176
2177 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2178 seq_printf(m, "DDC = 0x%08x\n",
2179 I915_READ(DCC));
656bfa3a
DV		 2180 seq_printf(m, "DDC2 = 0x%08x\n",
2181 I915_READ(DCC2));
ea16a3cd
DV		 2182 seq_printf(m, "C0DRB3 = 0x%04x\n",
2183 I915_READ16(C0DRB3));
2184 seq_printf(m, "C1DRB3 = 0x%04x\n",
2185 I915_READ16(C1DRB3));
9d3203e1 2186 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2187 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2188 I915_READ(MAD_DIMM_C0));
2189 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2190 I915_READ(MAD_DIMM_C1));
2191 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2192 I915_READ(MAD_DIMM_C2));
2193 seq_printf(m, "TILECTL = 0x%08x\n",
2194 I915_READ(TILECTL));
5907f5fb 2195 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2196 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2197 I915_READ(GAMTARBMODE));
2198 else
2199 seq_printf(m, "ARB_MODE = 0x%08x\n",
2200 I915_READ(ARB_MODE));
3fa7d235
DV		 2201 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2202 I915_READ(DISP_ARB_CTL));
ea16a3cd 2203 }
656bfa3a
DV		 2204
2205 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2206 seq_puts(m, "L-shaped memory detected\n");
2207
c8c8fb33 2208 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2209 mutex_unlock(&dev->struct_mutex);
2210
2211 return 0;
2212}
2213
1c60fef5
BW		 2214static int per_file_ctx(int id, void *ptr, void *data)
2215{
273497e5 2216 struct intel_context *ctx = ptr;
1c60fef5 2217 struct seq_file *m = data;
ae6c4806
DV		 2218 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2219
2220 if (!ppgtt) {
2221 seq_printf(m, " no ppgtt for context %d\n",
2222 ctx->user_handle);
2223 return 0;
2224 }
1c60fef5 2225
f83d6518
OM		 2226 if (i915_gem_context_is_default(ctx))
2227 seq_puts(m, " default context:\n");
2228 else
821d66dd 2229 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2230 ppgtt->debug_dump(ppgtt, m);
2231
2232 return 0;
2233}
2234
77df6772 2235static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2236{
3cf17fc5 2237 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2238 struct intel_engine_cs *ring;
77df6772
BW		 2239 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2240 int unused, i;
3cf17fc5 2241
77df6772
BW		 2242 if (!ppgtt)
2243 return;
2244
77df6772
BW		 2245 for_each_ring(ring, dev_priv, unused) {
2246 seq_printf(m, "%s\n", ring->name);
2247 for (i = 0; i < 4; i++) {
d3a93cbe 2248 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
77df6772 2249 pdp <<= 32;
d3a93cbe 2250 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
a2a5b15c 2251 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2252 }
2253 }
2254}
2255
2256static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2257{
2258 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2259 struct intel_engine_cs *ring;
77df6772 2260 int i;
3cf17fc5 2261
3cf17fc5
DV		 2262 if (INTEL_INFO(dev)->gen == 6)
2263 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2264
a2c7f6fd 2265 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2266 seq_printf(m, "%s\n", ring->name);
2267 if (INTEL_INFO(dev)->gen == 7)
2268 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2269 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2270 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2271 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2272 }
2273 if (dev_priv->mm.aliasing_ppgtt) {
2274 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2275
267f0c90 2276 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2277 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2278
87d60b63 2279 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2280 }
1c60fef5 2281
3cf17fc5 2282 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2283}
2284
2285static int i915_ppgtt_info(struct seq_file *m, void *data)
2286{
9f25d007 2287 struct drm_info_node *node = m->private;
77df6772 2288 struct drm_device *dev = node->minor->dev;
c8c8fb33 2289 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2290 struct drm_file *file;
77df6772
BW		 2291
2292 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2293 if (ret)
2294 return ret;
c8c8fb33 2295 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2296
2297 if (INTEL_INFO(dev)->gen >= 8)
2298 gen8_ppgtt_info(m, dev);
2299 else if (INTEL_INFO(dev)->gen >= 6)
2300 gen6_ppgtt_info(m, dev);
2301
ea91e401
MT		 2302 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2303 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2304 struct task_struct *task;
ea91e401 2305
7cb5dff8 2306 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2307 if (!task) {
2308 ret = -ESRCH;
2309 goto out_put;
2310 }
7cb5dff8
GT		 2311 seq_printf(m, "\nproc: %s\n", task->comm);
2312 put_task_struct(task);
ea91e401
MT		 2313 idr_for_each(&file_priv->context_idr, per_file_ctx,
2314 (void *)(unsigned long)m);
2315 }
2316
06812760 2317out_put:
c8c8fb33 2318 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2319 mutex_unlock(&dev->struct_mutex);
2320
06812760 2321 return ret;
3cf17fc5
DV		 2322}
2323
f5a4c67d
CW		 2324static int count_irq_waiters(struct drm_i915_private *i915)
2325{
2326 struct intel_engine_cs *ring;
2327 int count = 0;
2328 int i;
2329
2330 for_each_ring(ring, i915, i)
2331 count += ring->irq_refcount;
2332
2333 return count;
2334}
2335
1854d5ca
CW		 2336static int i915_rps_boost_info(struct seq_file *m, void *data)
2337{
2338 struct drm_info_node *node = m->private;
2339 struct drm_device *dev = node->minor->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct drm_file *file;
1854d5ca 2342
f5a4c67d
CW		 2343 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2344 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2345 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2346 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2347 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2348 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2349 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2350 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2351 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2352 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2353 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2354 struct drm_i915_file_private *file_priv = file->driver_priv;
2355 struct task_struct *task;
2356
2357 rcu_read_lock();
2358 task = pid_task(file->pid, PIDTYPE_PID);
2359 seq_printf(m, "%s [%d]: %d boosts%s\n",
2360 task ? task->comm : "<unknown>",
2361 task ? task->pid : -1,
2e1b8730
CW		 2362 file_priv->rps.boosts,
2363 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2364 rcu_read_unlock();
2365 }
2e1b8730
CW		 2366 seq_printf(m, "Semaphore boosts: %d%s\n",
2367 dev_priv->rps.semaphores.boosts,
2368 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2369 seq_printf(m, "MMIO flip boosts: %d%s\n",
2370 dev_priv->rps.mmioflips.boosts,
2371 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2372 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2373 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2374
8d3afd7d 2375 return 0;
1854d5ca
CW		 2376}
2377
63573eb7
BW		 2378static int i915_llc(struct seq_file *m, void *data)
2379{
9f25d007 2380 struct drm_info_node *node = m->private;
63573eb7
BW		 2381 struct drm_device *dev = node->minor->dev;
2382 struct drm_i915_private *dev_priv = dev->dev_private;
2383
2384 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2385 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2386 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2387
2388 return 0;
2389}
2390
fdf5d357
AD		 2391static int i915_guc_load_status_info(struct seq_file *m, void *data)
2392{
2393 struct drm_info_node *node = m->private;
2394 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2395 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2396 u32 tmp, i;
2397
2398 if (!HAS_GUC_UCODE(dev_priv->dev))
2399 return 0;
2400
2401 seq_printf(m, "GuC firmware status:\n");
2402 seq_printf(m, "\tpath: %s\n",
2403 guc_fw->guc_fw_path);
2404 seq_printf(m, "\tfetch: %s\n",
2405 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2406 seq_printf(m, "\tload: %s\n",
2407 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2408 seq_printf(m, "\tversion wanted: %d.%d\n",
2409 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2410 seq_printf(m, "\tversion found: %d.%d\n",
2411 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2412 seq_printf(m, "\theader: offset is %d; size = %d\n",
2413 guc_fw->header_offset, guc_fw->header_size);
2414 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2415 guc_fw->ucode_offset, guc_fw->ucode_size);
2416 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2417 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2418
2419 tmp = I915_READ(GUC_STATUS);
2420
2421 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2422 seq_printf(m, "\tBootrom status = 0x%x\n",
2423 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2424 seq_printf(m, "\tuKernel status = 0x%x\n",
2425 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2426 seq_printf(m, "\tMIA Core status = 0x%x\n",
2427 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2428 seq_puts(m, "\nScratch registers:\n");
2429 for (i = 0; i < 16; i++)
2430 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2431
2432 return 0;
2433}
2434
8b417c26
DG		 2435static void i915_guc_client_info(struct seq_file *m,
2436 struct drm_i915_private *dev_priv,
2437 struct i915_guc_client *client)
2438{
2439 struct intel_engine_cs *ring;
2440 uint64_t tot = 0;
2441 uint32_t i;
2442
2443 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2444 client->priority, client->ctx_index, client->proc_desc_offset);
2445 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2446 client->doorbell_id, client->doorbell_offset, client->cookie);
2447 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2448 client->wq_size, client->wq_offset, client->wq_tail);
2449
2450 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2451 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2452 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2453
2454 for_each_ring(ring, dev_priv, i) {
2455 seq_printf(m, "\tSubmissions: %llu %s\n",
2456 client->submissions[i],
2457 ring->name);
2458 tot += client->submissions[i];
2459 }
2460 seq_printf(m, "\tTotal: %llu\n", tot);
2461}
2462
2463static int i915_guc_info(struct seq_file *m, void *data)
2464{
2465 struct drm_info_node *node = m->private;
2466 struct drm_device *dev = node->minor->dev;
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 struct intel_guc guc;
0a0b457f 2469 struct i915_guc_client client = {};
8b417c26
DG		 2470 struct intel_engine_cs *ring;
2471 enum intel_ring_id i;
2472 u64 total = 0;
2473
2474 if (!HAS_GUC_SCHED(dev_priv->dev))
2475 return 0;
2476
5a843307
AD		 2477 if (mutex_lock_interruptible(&dev->struct_mutex))
2478 return 0;
2479
8b417c26 2480 /* Take a local copy of the GuC data, so we can dump it at leisure */
8b417c26 2481 guc = dev_priv->guc;
5a843307 2482 if (guc.execbuf_client)
8b417c26 2483 client = *guc.execbuf_client;
5a843307
AD		 2484
2485 mutex_unlock(&dev->struct_mutex);
8b417c26
DG		 2486
2487 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2488 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2489 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2490 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2491 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2492
2493 seq_printf(m, "\nGuC submissions:\n");
2494 for_each_ring(ring, dev_priv, i) {
2495 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2496 ring->name, guc.submissions[i],
2497 guc.last_seqno[i], guc.last_seqno[i]);
2498 total += guc.submissions[i];
2499 }
2500 seq_printf(m, "\t%s: %llu\n", "Total", total);
2501
2502 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2503 i915_guc_client_info(m, dev_priv, &client);
2504
2505 /* Add more as required ... */
2506
2507 return 0;
2508}
2509
4c7e77fc
AD		 2510static int i915_guc_log_dump(struct seq_file *m, void *data)
2511{
2512 struct drm_info_node *node = m->private;
2513 struct drm_device *dev = node->minor->dev;
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2516 u32 *log;
2517 int i = 0, pg;
2518
2519 if (!log_obj)
2520 return 0;
2521
2522 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2523 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2524
2525 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2526 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2527 *(log + i), *(log + i + 1),
2528 *(log + i + 2), *(log + i + 3));
2529
2530 kunmap_atomic(log);
2531 }
2532
2533 seq_putc(m, '\n');
2534
2535 return 0;
2536}
2537
e91fd8c6
RV		 2538static int i915_edp_psr_status(struct seq_file *m, void *data)
2539{
2540 struct drm_info_node *node = m->private;
2541 struct drm_device *dev = node->minor->dev;
2542 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2543 u32 psrperf = 0;
a6cbdb8e
RV		 2544 u32 stat[3];
2545 enum pipe pipe;
a031d709 2546 bool enabled = false;
e91fd8c6 2547
3553a8ea
DL		 2548 if (!HAS_PSR(dev)) {
2549 seq_puts(m, "PSR not supported\n");
2550 return 0;
2551 }
2552
c8c8fb33
PZ		 2553 intel_runtime_pm_get(dev_priv);
2554
fa128fa6 2555 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2556 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2557 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2558 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2559 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2560 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2561 dev_priv->psr.busy_frontbuffer_bits);
2562 seq_printf(m, "Re-enable work scheduled: %s\n",
2563 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2564
3553a8ea 2565 if (HAS_DDI(dev))
443a389f 2566 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
3553a8ea
DL		 2567 else {
2568 for_each_pipe(dev_priv, pipe) {
2569 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2570 VLV_EDP_PSR_CURR_STATE_MASK;
2571 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2572 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2573 enabled = true;
a6cbdb8e
RV		 2574 }
2575 }
2576 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2577
2578 if (!HAS_DDI(dev))
2579 for_each_pipe(dev_priv, pipe) {
2580 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2581 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2582 seq_printf(m, " pipe %c", pipe_name(pipe));
2583 }
2584 seq_puts(m, "\n");
e91fd8c6 2585
05eec3c2
RV		 2586 /*
2587 * VLV/CHV PSR has no kind of performance counter
2588 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2589 */
2590 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443a389f 2591 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
a031d709 2592 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2593
2594 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2595 }
fa128fa6 2596 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2597
c8c8fb33 2598 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2599 return 0;
2600}
2601
d2e216d0
RV		 2602static int i915_sink_crc(struct seq_file *m, void *data)
2603{
2604 struct drm_info_node *node = m->private;
2605 struct drm_device *dev = node->minor->dev;
2606 struct intel_encoder *encoder;
2607 struct intel_connector *connector;
2608 struct intel_dp *intel_dp = NULL;
2609 int ret;
2610 u8 crc[6];
2611
2612 drm_modeset_lock_all(dev);
aca5e361 2613 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2614
2615 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2616 continue;
2617
b6ae3c7c
PZ		 2618 if (!connector->base.encoder)
2619 continue;
2620
d2e216d0
RV		 2621 encoder = to_intel_encoder(connector->base.encoder);
2622 if (encoder->type != INTEL_OUTPUT_EDP)
2623 continue;
2624
2625 intel_dp = enc_to_intel_dp(&encoder->base);
2626
2627 ret = intel_dp_sink_crc(intel_dp, crc);
2628 if (ret)
2629 goto out;
2630
2631 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2632 crc[0], crc[1], crc[2],
2633 crc[3], crc[4], crc[5]);
2634 goto out;
2635 }
2636 ret = -ENODEV;
2637out:
2638 drm_modeset_unlock_all(dev);
2639 return ret;
2640}
2641
ec013e7f
JB		 2642static int i915_energy_uJ(struct seq_file *m, void *data)
2643{
2644 struct drm_info_node *node = m->private;
2645 struct drm_device *dev = node->minor->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 u64 power;
2648 u32 units;
2649
2650 if (INTEL_INFO(dev)->gen < 6)
2651 return -ENODEV;
2652
36623ef8
PZ		 2653 intel_runtime_pm_get(dev_priv);
2654
ec013e7f
JB		 2655 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2656 power = (power & 0x1f00) >> 8;
2657 units = 1000000 / (1 << power); /* convert to uJ */
2658 power = I915_READ(MCH_SECP_NRG_STTS);
2659 power *= units;
2660
36623ef8
PZ		 2661 intel_runtime_pm_put(dev_priv);
2662
ec013e7f 2663 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2664
2665 return 0;
2666}
2667
6455c870 2668static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2669{
9f25d007 2670 struct drm_info_node *node = m->private;
371db66a
PZ		 2671 struct drm_device *dev = node->minor->dev;
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673
6455c870 2674 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2675 seq_puts(m, "not supported\n");
2676 return 0;
2677 }
2678
86c4ec0d 2679 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2680 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2681 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2682#ifdef CONFIG_PM
a6aaec8b
DL		 2683 seq_printf(m, "Usage count: %d\n",
2684 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2685#else
2686 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2687#endif
371db66a 2688
ec013e7f
JB		 2689 return 0;
2690}
2691
1da51581
ID		 2692static int i915_power_domain_info(struct seq_file *m, void *unused)
2693{
9f25d007 2694 struct drm_info_node *node = m->private;
1da51581
ID		 2695 struct drm_device *dev = node->minor->dev;
2696 struct drm_i915_private *dev_priv = dev->dev_private;
2697 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2698 int i;
2699
2700 mutex_lock(&power_domains->lock);
2701
2702 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2703 for (i = 0; i < power_domains->power_well_count; i++) {
2704 struct i915_power_well *power_well;
2705 enum intel_display_power_domain power_domain;
2706
2707 power_well = &power_domains->power_wells[i];
2708 seq_printf(m, "%-25s %d\n", power_well->name,
2709 power_well->count);
2710
2711 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2712 power_domain++) {
2713 if (!(BIT(power_domain) & power_well->domains))
2714 continue;
2715
2716 seq_printf(m, " %-23s %d\n",
9895ad03 2717 intel_display_power_domain_str(power_domain),
1da51581
ID		 2718 power_domains->domain_use_count[power_domain]);
2719 }
2720 }
2721
2722 mutex_unlock(&power_domains->lock);
2723
2724 return 0;
2725}
2726
b7cec66d
DL		 2727static int i915_dmc_info(struct seq_file *m, void *unused)
2728{
2729 struct drm_info_node *node = m->private;
2730 struct drm_device *dev = node->minor->dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 struct intel_csr *csr;
2733
2734 if (!HAS_CSR(dev)) {
2735 seq_puts(m, "not supported\n");
2736 return 0;
2737 }
2738
2739 csr = &dev_priv->csr;
2740
6fb403de
MK		 2741 intel_runtime_pm_get(dev_priv);
2742
b7cec66d
DL		 2743 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2744 seq_printf(m, "path: %s\n", csr->fw_path);
2745
2746 if (!csr->dmc_payload)
6fb403de 2747 goto out;
b7cec66d
DL		 2748
2749 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2750 CSR_VERSION_MINOR(csr->version));
2751
8337206d
DL		 2752 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2753 seq_printf(m, "DC3 -> DC5 count: %d\n",
2754 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2755 seq_printf(m, "DC5 -> DC6 count: %d\n",
2756 I915_READ(SKL_CSR_DC5_DC6_COUNT));
16e11b99
MK		 2757 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2758 seq_printf(m, "DC3 -> DC5 count: %d\n",
2759 I915_READ(BXT_CSR_DC3_DC5_COUNT));
8337206d
DL		 2760 }
2761
6fb403de
MK		 2762out:
2763 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2764 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2765 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2766
8337206d
DL		 2767 intel_runtime_pm_put(dev_priv);
2768
b7cec66d
DL		 2769 return 0;
2770}
2771
53f5e3ca
JB		 2772static void intel_seq_print_mode(struct seq_file *m, int tabs,
2773 struct drm_display_mode *mode)
2774{
2775 int i;
2776
2777 for (i = 0; i < tabs; i++)
2778 seq_putc(m, '\t');
2779
2780 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2781 mode->base.id, mode->name,
2782 mode->vrefresh, mode->clock,
2783 mode->hdisplay, mode->hsync_start,
2784 mode->hsync_end, mode->htotal,
2785 mode->vdisplay, mode->vsync_start,
2786 mode->vsync_end, mode->vtotal,
2787 mode->type, mode->flags);
2788}
2789
2790static void intel_encoder_info(struct seq_file *m,
2791 struct intel_crtc *intel_crtc,
2792 struct intel_encoder *intel_encoder)
2793{
9f25d007 2794 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2795 struct drm_device *dev = node->minor->dev;
2796 struct drm_crtc *crtc = &intel_crtc->base;
2797 struct intel_connector *intel_connector;
2798 struct drm_encoder *encoder;
2799
2800 encoder = &intel_encoder->base;
2801 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2802 encoder->base.id, encoder->name);
53f5e3ca
JB		 2803 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2804 struct drm_connector *connector = &intel_connector->base;
2805 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2806 connector->base.id,
c23cc417 2807 connector->name,
53f5e3ca
JB		 2808 drm_get_connector_status_name(connector->status));
2809 if (connector->status == connector_status_connected) {
2810 struct drm_display_mode *mode = &crtc->mode;
2811 seq_printf(m, ", mode:\n");
2812 intel_seq_print_mode(m, 2, mode);
2813 } else {
2814 seq_putc(m, '\n');
2815 }
2816 }
2817}
2818
2819static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2820{
9f25d007 2821 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2822 struct drm_device *dev = node->minor->dev;
2823 struct drm_crtc *crtc = &intel_crtc->base;
2824 struct intel_encoder *intel_encoder;
23a48d53
ML		 2825 struct drm_plane_state *plane_state = crtc->primary->state;
2826 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2827
23a48d53 2828 if (fb)
5aa8a937 2829 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2830 fb->base.id, plane_state->src_x >> 16,
2831 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2832 else
2833 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2834 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2835 intel_encoder_info(m, intel_crtc, intel_encoder);
2836}
2837
2838static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2839{
2840 struct drm_display_mode *mode = panel->fixed_mode;
2841
2842 seq_printf(m, "\tfixed mode:\n");
2843 intel_seq_print_mode(m, 2, mode);
2844}
2845
2846static void intel_dp_info(struct seq_file *m,
2847 struct intel_connector *intel_connector)
2848{
2849 struct intel_encoder *intel_encoder = intel_connector->encoder;
2850 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2851
2852 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2853 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
53f5e3ca
JB		 2854 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2855 intel_panel_info(m, &intel_connector->panel);
2856}
2857
3d52ccf5
LY		 2858static void intel_dp_mst_info(struct seq_file *m,
2859 struct intel_connector *intel_connector)
2860{
2861 struct intel_encoder *intel_encoder = intel_connector->encoder;
2862 struct intel_dp_mst_encoder *intel_mst =
2863 enc_to_mst(&intel_encoder->base);
2864 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2865 struct intel_dp *intel_dp = &intel_dig_port->dp;
2866 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2867 intel_connector->port);
2868
2869 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2870}
2871
53f5e3ca
JB		 2872static void intel_hdmi_info(struct seq_file *m,
2873 struct intel_connector *intel_connector)
2874{
2875 struct intel_encoder *intel_encoder = intel_connector->encoder;
2876 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2877
742f491d 2878 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2879}
2880
2881static void intel_lvds_info(struct seq_file *m,
2882 struct intel_connector *intel_connector)
2883{
2884 intel_panel_info(m, &intel_connector->panel);
2885}
2886
2887static void intel_connector_info(struct seq_file *m,
2888 struct drm_connector *connector)
2889{
2890 struct intel_connector *intel_connector = to_intel_connector(connector);
2891 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2892 struct drm_display_mode *mode;
53f5e3ca
JB		 2893
2894 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2895 connector->base.id, connector->name,
53f5e3ca
JB		 2896 drm_get_connector_status_name(connector->status));
2897 if (connector->status == connector_status_connected) {
2898 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2899 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2900 connector->display_info.width_mm,
2901 connector->display_info.height_mm);
2902 seq_printf(m, "\tsubpixel order: %s\n",
2903 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2904 seq_printf(m, "\tCEA rev: %d\n",
2905 connector->display_info.cea_rev);
2906 }
36cd7444
DA		 2907 if (intel_encoder) {
2908 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2909 intel_encoder->type == INTEL_OUTPUT_EDP)
2910 intel_dp_info(m, intel_connector);
2911 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2912 intel_hdmi_info(m, intel_connector);
2913 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2914 intel_lvds_info(m, intel_connector);
3d52ccf5
LY		 2915 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2916 intel_dp_mst_info(m, intel_connector);
36cd7444 2917 }
53f5e3ca 2918
f103fc7d
JB		 2919 seq_printf(m, "\tmodes:\n");
2920 list_for_each_entry(mode, &connector->modes, head)
2921 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2922}
2923
065f2ec2
CW		 2924static bool cursor_active(struct drm_device *dev, int pipe)
2925{
2926 struct drm_i915_private *dev_priv = dev->dev_private;
2927 u32 state;
2928
2929 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 2930 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2931 else
5efb3e28 2932 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2933
2934 return state;
2935}
2936
2937static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2938{
2939 struct drm_i915_private *dev_priv = dev->dev_private;
2940 u32 pos;
2941
5efb3e28 2942 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2943
2944 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2945 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2946 *x = -*x;
2947
2948 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2949 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2950 *y = -*y;
2951
2952 return cursor_active(dev, pipe);
2953}
2954
3abc4e09
RF		 2955static const char *plane_type(enum drm_plane_type type)
2956{
2957 switch (type) {
2958 case DRM_PLANE_TYPE_OVERLAY:
2959 return "OVL";
2960 case DRM_PLANE_TYPE_PRIMARY:
2961 return "PRI";
2962 case DRM_PLANE_TYPE_CURSOR:
2963 return "CUR";
2964 /*
2965 * Deliberately omitting default: to generate compiler warnings
2966 * when a new drm_plane_type gets added.
2967 */
2968 }
2969
2970 return "unknown";
2971}
2972
2973static const char *plane_rotation(unsigned int rotation)
2974{
2975 static char buf[48];
2976 /*
2977 * According to doc only one DRM_ROTATE_ is allowed but this
2978 * will print them all to visualize if the values are misused
2979 */
2980 snprintf(buf, sizeof(buf),
2981 "%s%s%s%s%s%s(0x%08x)",
2982 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
2983 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
2984 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
2985 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
2986 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
2987 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
2988 rotation);
2989
2990 return buf;
2991}
2992
2993static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2994{
2995 struct drm_info_node *node = m->private;
2996 struct drm_device *dev = node->minor->dev;
2997 struct intel_plane *intel_plane;
2998
2999 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3000 struct drm_plane_state *state;
3001 struct drm_plane *plane = &intel_plane->base;
3002
3003 if (!plane->state) {
3004 seq_puts(m, "plane->state is NULL!\n");
3005 continue;
3006 }
3007
3008 state = plane->state;
3009
3010 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3011 plane->base.id,
3012 plane_type(intel_plane->base.type),
3013 state->crtc_x, state->crtc_y,
3014 state->crtc_w, state->crtc_h,
3015 (state->src_x >> 16),
3016 ((state->src_x & 0xffff) * 15625) >> 10,
3017 (state->src_y >> 16),
3018 ((state->src_y & 0xffff) * 15625) >> 10,
3019 (state->src_w >> 16),
3020 ((state->src_w & 0xffff) * 15625) >> 10,
3021 (state->src_h >> 16),
3022 ((state->src_h & 0xffff) * 15625) >> 10,
3023 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3024 plane_rotation(state->rotation));
3025 }
3026}
3027
3028static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3029{
3030 struct intel_crtc_state *pipe_config;
3031 int num_scalers = intel_crtc->num_scalers;
3032 int i;
3033
3034 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3035
3036 /* Not all platformas have a scaler */
3037 if (num_scalers) {
3038 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3039 num_scalers,
3040 pipe_config->scaler_state.scaler_users,
3041 pipe_config->scaler_state.scaler_id);
3042
3043 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3044 struct intel_scaler *sc =
3045 &pipe_config->scaler_state.scalers[i];
3046
3047 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3048 i, yesno(sc->in_use), sc->mode);
3049 }
3050 seq_puts(m, "\n");
3051 } else {
3052 seq_puts(m, "\tNo scalers available on this platform\n");
3053 }
3054}
3055
53f5e3ca
JB		 3056static int i915_display_info(struct seq_file *m, void *unused)
3057{
9f25d007 3058 struct drm_info_node *node = m->private;
53f5e3ca 3059 struct drm_device *dev = node->minor->dev;
b0e5ddf3 3060 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 3061 struct intel_crtc *crtc;
53f5e3ca
JB		 3062 struct drm_connector *connector;
3063
b0e5ddf3 3064 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3065 drm_modeset_lock_all(dev);
3066 seq_printf(m, "CRTC info\n");
3067 seq_printf(m, "---------\n");
d3fcc808 3068 for_each_intel_crtc(dev, crtc) {
065f2ec2 3069 bool active;
f77076c9 3070 struct intel_crtc_state *pipe_config;
065f2ec2 3071 int x, y;
53f5e3ca 3072
f77076c9
ML		 3073 pipe_config = to_intel_crtc_state(crtc->base.state);
3074
3abc4e09 3075 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3076 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3077 yesno(pipe_config->base.active),
3abc4e09
RF		 3078 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3079 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3080
f77076c9 3081 if (pipe_config->base.active) {
065f2ec2
CW		 3082 intel_crtc_info(m, crtc);
3083
a23dc658 3084 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 3085 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3086 yesno(crtc->cursor_base),
3dd512fb
MR		 3087 x, y, crtc->base.cursor->state->crtc_w,
3088 crtc->base.cursor->state->crtc_h,
57127efa 3089 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3090 intel_scaler_info(m, crtc);
3091 intel_plane_info(m, crtc);
a23dc658 3092 }
cace841c
DV		 3093
3094 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3095 yesno(!crtc->cpu_fifo_underrun_disabled),
3096 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3097 }
3098
3099 seq_printf(m, "\n");
3100 seq_printf(m, "Connector info\n");
3101 seq_printf(m, "--------------\n");
3102 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3103 intel_connector_info(m, connector);
3104 }
3105 drm_modeset_unlock_all(dev);
b0e5ddf3 3106 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3107
3108 return 0;
3109}
3110
e04934cf
BW		 3111static int i915_semaphore_status(struct seq_file *m, void *unused)
3112{
3113 struct drm_info_node *node = (struct drm_info_node *) m->private;
3114 struct drm_device *dev = node->minor->dev;
3115 struct drm_i915_private *dev_priv = dev->dev_private;
3116 struct intel_engine_cs *ring;
3117 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3118 int i, j, ret;
3119
3120 if (!i915_semaphore_is_enabled(dev)) {
3121 seq_puts(m, "Semaphores are disabled\n");
3122 return 0;
3123 }
3124
3125 ret = mutex_lock_interruptible(&dev->struct_mutex);
3126 if (ret)
3127 return ret;
03872064 3128 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3129
3130 if (IS_BROADWELL(dev)) {
3131 struct page *page;
3132 uint64_t *seqno;
3133
3134 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3135
3136 seqno = (uint64_t *)kmap_atomic(page);
3137 for_each_ring(ring, dev_priv, i) {
3138 uint64_t offset;
3139
3140 seq_printf(m, "%s\n", ring->name);
3141
3142 seq_puts(m, " Last signal:");
3143 for (j = 0; j < num_rings; j++) {
3144 offset = i * I915_NUM_RINGS + j;
3145 seq_printf(m, "0x%08llx (0x%02llx) ",
3146 seqno[offset], offset * 8);
3147 }
3148 seq_putc(m, '\n');
3149
3150 seq_puts(m, " Last wait: ");
3151 for (j = 0; j < num_rings; j++) {
3152 offset = i + (j * I915_NUM_RINGS);
3153 seq_printf(m, "0x%08llx (0x%02llx) ",
3154 seqno[offset], offset * 8);
3155 }
3156 seq_putc(m, '\n');
3157
3158 }
3159 kunmap_atomic(seqno);
3160 } else {
3161 seq_puts(m, " Last signal:");
3162 for_each_ring(ring, dev_priv, i)
3163 for (j = 0; j < num_rings; j++)
3164 seq_printf(m, "0x%08x\n",
3165 I915_READ(ring->semaphore.mbox.signal[j]));
3166 seq_putc(m, '\n');
3167 }
3168
3169 seq_puts(m, "\nSync seqno:\n");
3170 for_each_ring(ring, dev_priv, i) {
3171 for (j = 0; j < num_rings; j++) {
3172 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3173 }
3174 seq_putc(m, '\n');
3175 }
3176 seq_putc(m, '\n');
3177
03872064 3178 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3179 mutex_unlock(&dev->struct_mutex);
3180 return 0;
3181}
3182
728e29d7
DV		 3183static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3184{
3185 struct drm_info_node *node = (struct drm_info_node *) m->private;
3186 struct drm_device *dev = node->minor->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 int i;
3189
3190 drm_modeset_lock_all(dev);
3191 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3192 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3193
3194 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 3195 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 3196 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 3197 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3198 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3199 seq_printf(m, " dpll_md: 0x%08x\n",
3200 pll->config.hw_state.dpll_md);
3201 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3202 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3203 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3204 }
3205 drm_modeset_unlock_all(dev);
3206
3207 return 0;
3208}
3209
1ed1ef9d 3210static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3211{
3212 int i;
3213 int ret;
3214 struct drm_info_node *node = (struct drm_info_node *) m->private;
3215 struct drm_device *dev = node->minor->dev;
3216 struct drm_i915_private *dev_priv = dev->dev_private;
3217
888b5995
AS		 3218 ret = mutex_lock_interruptible(&dev->struct_mutex);
3219 if (ret)
3220 return ret;
3221
3222 intel_runtime_pm_get(dev_priv);
3223
7225342a
MK		 3224 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3225 for (i = 0; i < dev_priv->workarounds.count; ++i) {
f0f59a00
VS		 3226 i915_reg_t addr;
3227 u32 mask, value, read;
2fa60f6d 3228 bool ok;
888b5995 3229
7225342a
MK		 3230 addr = dev_priv->workarounds.reg[i].addr;
3231 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 3232 value = dev_priv->workarounds.reg[i].value;
3233 read = I915_READ(addr);
3234 ok = (value & mask) == (read & mask);
3235 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
f0f59a00 3236 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3237 }
3238
3239 intel_runtime_pm_put(dev_priv);
3240 mutex_unlock(&dev->struct_mutex);
3241
3242 return 0;
3243}
3244
c5511e44
DL		 3245static int i915_ddb_info(struct seq_file *m, void *unused)
3246{
3247 struct drm_info_node *node = m->private;
3248 struct drm_device *dev = node->minor->dev;
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 struct skl_ddb_allocation *ddb;
3251 struct skl_ddb_entry *entry;
3252 enum pipe pipe;
3253 int plane;
3254
2fcffe19
DL		 3255 if (INTEL_INFO(dev)->gen < 9)
3256 return 0;
3257
c5511e44
DL		 3258 drm_modeset_lock_all(dev);
3259
3260 ddb = &dev_priv->wm.skl_hw.ddb;
3261
3262 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3263
3264 for_each_pipe(dev_priv, pipe) {
3265 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3266
dd740780 3267 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3268 entry = &ddb->plane[pipe][plane];
3269 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3270 entry->start, entry->end,
3271 skl_ddb_entry_size(entry));
3272 }
3273
4969d33e 3274 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3275 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3276 entry->end, skl_ddb_entry_size(entry));
3277 }
3278
3279 drm_modeset_unlock_all(dev);
3280
3281 return 0;
3282}
3283
a54746e3
VK		 3284static void drrs_status_per_crtc(struct seq_file *m,
3285 struct drm_device *dev, struct intel_crtc *intel_crtc)
3286{
3287 struct intel_encoder *intel_encoder;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct i915_drrs *drrs = &dev_priv->drrs;
3290 int vrefresh = 0;
3291
3292 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3293 /* Encoder connected on this CRTC */
3294 switch (intel_encoder->type) {
3295 case INTEL_OUTPUT_EDP:
3296 seq_puts(m, "eDP:\n");
3297 break;
3298 case INTEL_OUTPUT_DSI:
3299 seq_puts(m, "DSI:\n");
3300 break;
3301 case INTEL_OUTPUT_HDMI:
3302 seq_puts(m, "HDMI:\n");
3303 break;
3304 case INTEL_OUTPUT_DISPLAYPORT:
3305 seq_puts(m, "DP:\n");
3306 break;
3307 default:
3308 seq_printf(m, "Other encoder (id=%d).\n",
3309 intel_encoder->type);
3310 return;
3311 }
3312 }
3313
3314 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3315 seq_puts(m, "\tVBT: DRRS_type: Static");
3316 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3317 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3318 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3319 seq_puts(m, "\tVBT: DRRS_type: None");
3320 else
3321 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3322
3323 seq_puts(m, "\n\n");
3324
f77076c9 3325 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3326 struct intel_panel *panel;
3327
3328 mutex_lock(&drrs->mutex);
3329 /* DRRS Supported */
3330 seq_puts(m, "\tDRRS Supported: Yes\n");
3331
3332 /* disable_drrs() will make drrs->dp NULL */
3333 if (!drrs->dp) {
3334 seq_puts(m, "Idleness DRRS: Disabled");
3335 mutex_unlock(&drrs->mutex);
3336 return;
3337 }
3338
3339 panel = &drrs->dp->attached_connector->panel;
3340 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3341 drrs->busy_frontbuffer_bits);
3342
3343 seq_puts(m, "\n\t\t");
3344 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3345 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3346 vrefresh = panel->fixed_mode->vrefresh;
3347 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3348 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3349 vrefresh = panel->downclock_mode->vrefresh;
3350 } else {
3351 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3352 drrs->refresh_rate_type);
3353 mutex_unlock(&drrs->mutex);
3354 return;
3355 }
3356 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3357
3358 seq_puts(m, "\n\t\t");
3359 mutex_unlock(&drrs->mutex);
3360 } else {
3361 /* DRRS not supported. Print the VBT parameter*/
3362 seq_puts(m, "\tDRRS Supported : No");
3363 }
3364 seq_puts(m, "\n");
3365}
3366
3367static int i915_drrs_status(struct seq_file *m, void *unused)
3368{
3369 struct drm_info_node *node = m->private;
3370 struct drm_device *dev = node->minor->dev;
3371 struct intel_crtc *intel_crtc;
3372 int active_crtc_cnt = 0;
3373
3374 for_each_intel_crtc(dev, intel_crtc) {
3375 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3376
f77076c9 3377 if (intel_crtc->base.state->active) {
a54746e3
VK		 3378 active_crtc_cnt++;
3379 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3380
3381 drrs_status_per_crtc(m, dev, intel_crtc);
3382 }
3383
3384 drm_modeset_unlock(&intel_crtc->base.mutex);
3385 }
3386
3387 if (!active_crtc_cnt)
3388 seq_puts(m, "No active crtc found\n");
3389
3390 return 0;
3391}
3392
07144428
DL		 3393struct pipe_crc_info {
3394 const char *name;
3395 struct drm_device *dev;
3396 enum pipe pipe;
3397};
3398
11bed958
DA		 3399static int i915_dp_mst_info(struct seq_file *m, void *unused)
3400{
3401 struct drm_info_node *node = (struct drm_info_node *) m->private;
3402 struct drm_device *dev = node->minor->dev;
3403 struct drm_encoder *encoder;
3404 struct intel_encoder *intel_encoder;
3405 struct intel_digital_port *intel_dig_port;
3406 drm_modeset_lock_all(dev);
3407 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3408 intel_encoder = to_intel_encoder(encoder);
3409 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3410 continue;
3411 intel_dig_port = enc_to_dig_port(encoder);
3412 if (!intel_dig_port->dp.can_mst)
3413 continue;
3414
3415 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3416 }
3417 drm_modeset_unlock_all(dev);
3418 return 0;
3419}
3420
07144428
DL		 3421static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3422{
be5c7a90
DL		 3423 struct pipe_crc_info *info = inode->i_private;
3424 struct drm_i915_private *dev_priv = info->dev->dev_private;
3425 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3426
7eb1c496
DV		 3427 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3428 return -ENODEV;
3429
d538bbdf
DL		 3430 spin_lock_irq(&pipe_crc->lock);
3431
3432 if (pipe_crc->opened) {
3433 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3434 return -EBUSY; /* already open */
3435 }
3436
d538bbdf 3437 pipe_crc->opened = true;
07144428
DL		 3438 filep->private_data = inode->i_private;
3439
d538bbdf
DL		 3440 spin_unlock_irq(&pipe_crc->lock);
3441
07144428
DL		 3442 return 0;
3443}
3444
3445static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3446{
be5c7a90
DL		 3447 struct pipe_crc_info *info = inode->i_private;
3448 struct drm_i915_private *dev_priv = info->dev->dev_private;
3449 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3450
d538bbdf
DL		 3451 spin_lock_irq(&pipe_crc->lock);
3452 pipe_crc->opened = false;
3453 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3454
07144428
DL		 3455 return 0;
3456}
3457
3458/* (6 fields, 8 chars each, space separated (5) + '\n') */
3459#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3460/* account for \'0' */
3461#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3462
3463static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3464{
d538bbdf
DL		 3465 assert_spin_locked(&pipe_crc->lock);
3466 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3467 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3468}
3469
3470static ssize_t
3471i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3472 loff_t *pos)
3473{
3474 struct pipe_crc_info *info = filep->private_data;
3475 struct drm_device *dev = info->dev;
3476 struct drm_i915_private *dev_priv = dev->dev_private;
3477 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3478 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3479 int n_entries;
07144428
DL		 3480 ssize_t bytes_read;
3481
3482 /*
3483 * Don't allow user space to provide buffers not big enough to hold
3484 * a line of data.
3485 */
3486 if (count < PIPE_CRC_LINE_LEN)
3487 return -EINVAL;
3488
3489 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3490 return 0;
07144428
DL		 3491
3492 /* nothing to read */
d538bbdf 3493 spin_lock_irq(&pipe_crc->lock);
07144428 3494 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3495 int ret;
3496
3497 if (filep->f_flags & O_NONBLOCK) {
3498 spin_unlock_irq(&pipe_crc->lock);
07144428 3499 return -EAGAIN;
d538bbdf 3500 }
07144428 3501
d538bbdf
DL		 3502 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3503 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3504 if (ret) {
3505 spin_unlock_irq(&pipe_crc->lock);
3506 return ret;
3507 }
8bf1e9f1
SH		 3508 }
3509
07144428 3510 /* We now have one or more entries to read */
9ad6d99f 3511 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3512
07144428 3513 bytes_read = 0;
9ad6d99f
VS		 3514 while (n_entries > 0) {
3515 struct intel_pipe_crc_entry *entry =
3516 &pipe_crc->entries[pipe_crc->tail];
07144428 3517 int ret;
8bf1e9f1 3518
9ad6d99f
VS		 3519 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3520 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3521 break;
3522
3523 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3524 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3525
07144428
DL		 3526 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3527 "%8u %8x %8x %8x %8x %8x\n",
3528 entry->frame, entry->crc[0],
3529 entry->crc[1], entry->crc[2],
3530 entry->crc[3], entry->crc[4]);
3531
9ad6d99f
VS		 3532 spin_unlock_irq(&pipe_crc->lock);
3533
3534 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3535 if (ret == PIPE_CRC_LINE_LEN)
3536 return -EFAULT;
b2c88f5b 3537
9ad6d99f
VS		 3538 user_buf += PIPE_CRC_LINE_LEN;
3539 n_entries--;
3540
3541 spin_lock_irq(&pipe_crc->lock);
3542 }
8bf1e9f1 3543
d538bbdf
DL		 3544 spin_unlock_irq(&pipe_crc->lock);
3545
07144428
DL		 3546 return bytes_read;
3547}
3548
3549static const struct file_operations i915_pipe_crc_fops = {
3550 .owner = THIS_MODULE,
3551 .open = i915_pipe_crc_open,
3552 .read = i915_pipe_crc_read,
3553 .release = i915_pipe_crc_release,
3554};
3555
3556static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3557 {
3558 .name = "i915_pipe_A_crc",
3559 .pipe = PIPE_A,
3560 },
3561 {
3562 .name = "i915_pipe_B_crc",
3563 .pipe = PIPE_B,
3564 },
3565 {
3566 .name = "i915_pipe_C_crc",
3567 .pipe = PIPE_C,
3568 },
3569};
3570
3571static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3572 enum pipe pipe)
3573{
3574 struct drm_device *dev = minor->dev;
3575 struct dentry *ent;
3576 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3577
3578 info->dev = dev;
3579 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3580 &i915_pipe_crc_fops);
f3c5fe97
WY		 3581 if (!ent)
3582 return -ENOMEM;
07144428
DL		 3583
3584 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3585}
3586
e8dfcf78 3587static const char * const pipe_crc_sources[] = {
926321d5
DV		 3588 "none",
3589 "plane1",
3590 "plane2",
3591 "pf",
5b3a856b 3592 "pipe",
3d099a05
DV		 3593 "TV",
3594 "DP-B",
3595 "DP-C",
3596 "DP-D",
46a19188 3597 "auto",
926321d5
DV		 3598};
3599
3600static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3601{
3602 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3603 return pipe_crc_sources[source];
3604}
3605
bd9db02f 3606static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3607{
3608 struct drm_device *dev = m->private;
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 int i;
3611
3612 for (i = 0; i < I915_MAX_PIPES; i++)
3613 seq_printf(m, "%c %s\n", pipe_name(i),
3614 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3615
3616 return 0;
3617}
3618
bd9db02f 3619static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3620{
3621 struct drm_device *dev = inode->i_private;
3622
bd9db02f 3623 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3624}
3625
46a19188 3626static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3627 uint32_t *val)
3628{
46a19188
DV		 3629 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3630 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3631
3632 switch (*source) {
52f843f6
DV		 3633 case INTEL_PIPE_CRC_SOURCE_PIPE:
3634 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3635 break;
3636 case INTEL_PIPE_CRC_SOURCE_NONE:
3637 *val = 0;
3638 break;
3639 default:
3640 return -EINVAL;
3641 }
3642
3643 return 0;
3644}
3645
46a19188
DV		 3646static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3647 enum intel_pipe_crc_source *source)
3648{
3649 struct intel_encoder *encoder;
3650 struct intel_crtc *crtc;
26756809 3651 struct intel_digital_port *dig_port;
46a19188
DV		 3652 int ret = 0;
3653
3654 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3655
6e9f798d 3656 drm_modeset_lock_all(dev);
b2784e15 3657 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3658 if (!encoder->base.crtc)
3659 continue;
3660
3661 crtc = to_intel_crtc(encoder->base.crtc);
3662
3663 if (crtc->pipe != pipe)
3664 continue;
3665
3666 switch (encoder->type) {
3667 case INTEL_OUTPUT_TVOUT:
3668 *source = INTEL_PIPE_CRC_SOURCE_TV;
3669 break;
3670 case INTEL_OUTPUT_DISPLAYPORT:
3671 case INTEL_OUTPUT_EDP:
26756809
DV		 3672 dig_port = enc_to_dig_port(&encoder->base);
3673 switch (dig_port->port) {
3674 case PORT_B:
3675 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3676 break;
3677 case PORT_C:
3678 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3679 break;
3680 case PORT_D:
3681 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3682 break;
3683 default:
3684 WARN(1, "nonexisting DP port %c\n",
3685 port_name(dig_port->port));
3686 break;
3687 }
46a19188 3688 break;
6847d71b
PZ		 3689 default:
3690 break;
46a19188
DV		 3691 }
3692 }
6e9f798d 3693 drm_modeset_unlock_all(dev);
46a19188
DV		 3694
3695 return ret;
3696}
3697
3698static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3699 enum pipe pipe,
3700 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3701 uint32_t *val)
3702{
8d2f24ca
DV		 3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 bool need_stable_symbols = false;
3705
46a19188
DV		 3706 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3707 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3708 if (ret)
3709 return ret;
3710 }
3711
3712 switch (*source) {
7ac0129b
DV		 3713 case INTEL_PIPE_CRC_SOURCE_PIPE:
3714 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3715 break;
3716 case INTEL_PIPE_CRC_SOURCE_DP_B:
3717 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3718 need_stable_symbols = true;
7ac0129b
DV		 3719 break;
3720 case INTEL_PIPE_CRC_SOURCE_DP_C:
3721 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3722 need_stable_symbols = true;
7ac0129b 3723 break;
2be57922
VS		 3724 case INTEL_PIPE_CRC_SOURCE_DP_D:
3725 if (!IS_CHERRYVIEW(dev))
3726 return -EINVAL;
3727 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3728 need_stable_symbols = true;
3729 break;
7ac0129b
DV		 3730 case INTEL_PIPE_CRC_SOURCE_NONE:
3731 *val = 0;
3732 break;
3733 default:
3734 return -EINVAL;
3735 }
3736
8d2f24ca
DV		 3737 /*
3738 * When the pipe CRC tap point is after the transcoders we need
3739 * to tweak symbol-level features to produce a deterministic series of
3740 * symbols for a given frame. We need to reset those features only once
3741 * a frame (instead of every nth symbol):
3742 * - DC-balance: used to ensure a better clock recovery from the data
3743 * link (SDVO)
3744 * - DisplayPort scrambling: used for EMI reduction
3745 */
3746 if (need_stable_symbols) {
3747 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3748
8d2f24ca 3749 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3750 switch (pipe) {
3751 case PIPE_A:
8d2f24ca 3752 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3753 break;
3754 case PIPE_B:
8d2f24ca 3755 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3756 break;
3757 case PIPE_C:
3758 tmp |= PIPE_C_SCRAMBLE_RESET;
3759 break;
3760 default:
3761 return -EINVAL;
3762 }
8d2f24ca
DV		 3763 I915_WRITE(PORT_DFT2_G4X, tmp);
3764 }
3765
7ac0129b
DV		 3766 return 0;
3767}
3768
4b79ebf7 3769static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3770 enum pipe pipe,
3771 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3772 uint32_t *val)
3773{
84093603
DV		 3774 struct drm_i915_private *dev_priv = dev->dev_private;
3775 bool need_stable_symbols = false;
3776
46a19188
DV		 3777 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3778 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3779 if (ret)
3780 return ret;
3781 }
3782
3783 switch (*source) {
4b79ebf7
DV		 3784 case INTEL_PIPE_CRC_SOURCE_PIPE:
3785 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3786 break;
3787 case INTEL_PIPE_CRC_SOURCE_TV:
3788 if (!SUPPORTS_TV(dev))
3789 return -EINVAL;
3790 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3791 break;
3792 case INTEL_PIPE_CRC_SOURCE_DP_B:
3793 if (!IS_G4X(dev))
3794 return -EINVAL;
3795 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3796 need_stable_symbols = true;
4b79ebf7
DV		 3797 break;
3798 case INTEL_PIPE_CRC_SOURCE_DP_C:
3799 if (!IS_G4X(dev))
3800 return -EINVAL;
3801 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3802 need_stable_symbols = true;
4b79ebf7
DV		 3803 break;
3804 case INTEL_PIPE_CRC_SOURCE_DP_D:
3805 if (!IS_G4X(dev))
3806 return -EINVAL;
3807 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3808 need_stable_symbols = true;
4b79ebf7
DV		 3809 break;
3810 case INTEL_PIPE_CRC_SOURCE_NONE:
3811 *val = 0;
3812 break;
3813 default:
3814 return -EINVAL;
3815 }
3816
84093603
DV		 3817 /*
3818 * When the pipe CRC tap point is after the transcoders we need
3819 * to tweak symbol-level features to produce a deterministic series of
3820 * symbols for a given frame. We need to reset those features only once
3821 * a frame (instead of every nth symbol):
3822 * - DC-balance: used to ensure a better clock recovery from the data
3823 * link (SDVO)
3824 * - DisplayPort scrambling: used for EMI reduction
3825 */
3826 if (need_stable_symbols) {
3827 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3828
3829 WARN_ON(!IS_G4X(dev));
3830
3831 I915_WRITE(PORT_DFT_I9XX,
3832 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3833
3834 if (pipe == PIPE_A)
3835 tmp |= PIPE_A_SCRAMBLE_RESET;
3836 else
3837 tmp |= PIPE_B_SCRAMBLE_RESET;
3838
3839 I915_WRITE(PORT_DFT2_G4X, tmp);
3840 }
3841
4b79ebf7
DV		 3842 return 0;
3843}
3844
8d2f24ca
DV		 3845static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3846 enum pipe pipe)
3847{
3848 struct drm_i915_private *dev_priv = dev->dev_private;
3849 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3850
eb736679
VS		 3851 switch (pipe) {
3852 case PIPE_A:
8d2f24ca 3853 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3854 break;
3855 case PIPE_B:
8d2f24ca 3856 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3857 break;
3858 case PIPE_C:
3859 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3860 break;
3861 default:
3862 return;
3863 }
8d2f24ca
DV		 3864 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3865 tmp &= ~DC_BALANCE_RESET_VLV;
3866 I915_WRITE(PORT_DFT2_G4X, tmp);
3867
3868}
3869
84093603
DV		 3870static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3871 enum pipe pipe)
3872{
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3875
3876 if (pipe == PIPE_A)
3877 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3878 else
3879 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3880 I915_WRITE(PORT_DFT2_G4X, tmp);
3881
3882 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3883 I915_WRITE(PORT_DFT_I9XX,
3884 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3885 }
3886}
3887
46a19188 3888static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3889 uint32_t *val)
3890{
46a19188
DV		 3891 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3892 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3893
3894 switch (*source) {
5b3a856b
DV		 3895 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3896 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3897 break;
3898 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3899 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3900 break;
5b3a856b
DV		 3901 case INTEL_PIPE_CRC_SOURCE_PIPE:
3902 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3903 break;
3d099a05 3904 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3905 *val = 0;
3906 break;
3d099a05
DV		 3907 default:
3908 return -EINVAL;
5b3a856b
DV		 3909 }
3910
3911 return 0;
3912}
3913
c4e2d043 3914static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3915{
3916 struct drm_i915_private *dev_priv = dev->dev_private;
3917 struct intel_crtc *crtc =
3918 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3919 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3920 struct drm_atomic_state *state;
3921 int ret = 0;
fabf6e51
DV		 3922
3923 drm_modeset_lock_all(dev);
c4e2d043
ML		 3924 state = drm_atomic_state_alloc(dev);
3925 if (!state) {
3926 ret = -ENOMEM;
3927 goto out;
fabf6e51 3928 }
fabf6e51 3929
c4e2d043
ML		 3930 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3931 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3932 if (IS_ERR(pipe_config)) {
3933 ret = PTR_ERR(pipe_config);
3934 goto out;
3935 }
fabf6e51 3936
c4e2d043
ML		 3937 pipe_config->pch_pfit.force_thru = enable;
3938 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3939 pipe_config->pch_pfit.enabled != enable)
3940 pipe_config->base.connectors_changed = true;
1b509259 3941
c4e2d043
ML		 3942 ret = drm_atomic_commit(state);
3943out:
fabf6e51 3944 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3945 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3946 if (ret)
3947 drm_atomic_state_free(state);
fabf6e51
DV		 3948}
3949
3950static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3951 enum pipe pipe,
3952 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3953 uint32_t *val)
3954{
46a19188
DV		 3955 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3956 *source = INTEL_PIPE_CRC_SOURCE_PF;
3957
3958 switch (*source) {
5b3a856b
DV		 3959 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3960 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3961 break;
3962 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3963 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3964 break;
3965 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 3966 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3967 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 3968
5b3a856b
DV		 3969 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3970 break;
3d099a05 3971 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3972 *val = 0;
3973 break;
3d099a05
DV		 3974 default:
3975 return -EINVAL;
5b3a856b
DV		 3976 }
3977
3978 return 0;
3979}
3980
926321d5
DV		 3981static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3982 enum intel_pipe_crc_source source)
3983{
3984 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3985 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3986 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3987 pipe));
432f3342 3988 u32 val = 0; /* shut up gcc */
5b3a856b 3989 int ret;
926321d5 3990
cc3da175
DL		 3991 if (pipe_crc->source == source)
3992 return 0;
3993
ae676fcd
DL		 3994 /* forbid changing the source without going back to 'none' */
3995 if (pipe_crc->source && source)
3996 return -EINVAL;
3997
9d8b0588
DV		 3998 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3999 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4000 return -EIO;
4001 }
4002
52f843f6 4003 if (IS_GEN2(dev))
46a19188 4004 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 4005 else if (INTEL_INFO(dev)->gen < 5)
46a19188 4006 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
666a4537 4007 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
fabf6e51 4008 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 4009 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 4010 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 4011 else
fabf6e51 4012 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 4013
4014 if (ret != 0)
4015 return ret;
4016
4b584369
DL		 4017 /* none -> real source transition */
4018 if (source) {
4252fbc3
VS		 4019 struct intel_pipe_crc_entry *entries;
4020
7cd6ccff
DL		 4021 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4022 pipe_name(pipe), pipe_crc_source_name(source));
4023
3cf54b34
VS		 4024 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4025 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 4026 GFP_KERNEL);
4027 if (!entries)
e5f75aca
DL		 4028 return -ENOMEM;
4029
8c740dce
PZ		 4030 /*
4031 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4032 * enabled and disabled dynamically based on package C states,
4033 * user space can't make reliable use of the CRCs, so let's just
4034 * completely disable it.
4035 */
4036 hsw_disable_ips(crtc);
4037
d538bbdf 4038 spin_lock_irq(&pipe_crc->lock);
64387b61 4039 kfree(pipe_crc->entries);
4252fbc3 4040 pipe_crc->entries = entries;
d538bbdf
DL		 4041 pipe_crc->head = 0;
4042 pipe_crc->tail = 0;
4043 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4044 }
4045
cc3da175 4046 pipe_crc->source = source;
926321d5 4047
926321d5
DV		 4048 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4049 POSTING_READ(PIPE_CRC_CTL(pipe));
4050
e5f75aca
DL		 4051 /* real source -> none transition */
4052 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4053 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4054 struct intel_crtc *crtc =
4055 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4056
7cd6ccff
DL		 4057 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4058 pipe_name(pipe));
4059
a33d7105 4060 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4061 if (crtc->base.state->active)
a33d7105
DV		 4062 intel_wait_for_vblank(dev, pipe);
4063 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4064
d538bbdf
DL		 4065 spin_lock_irq(&pipe_crc->lock);
4066 entries = pipe_crc->entries;
e5f75aca 4067 pipe_crc->entries = NULL;
9ad6d99f
VS		 4068 pipe_crc->head = 0;
4069 pipe_crc->tail = 0;
d538bbdf
DL		 4070 spin_unlock_irq(&pipe_crc->lock);
4071
4072 kfree(entries);
84093603
DV		 4073
4074 if (IS_G4X(dev))
4075 g4x_undo_pipe_scramble_reset(dev, pipe);
666a4537 4076 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
8d2f24ca 4077 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 4078 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4079 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 4080
4081 hsw_enable_ips(crtc);
e5f75aca
DL		 4082 }
4083
926321d5
DV		 4084 return 0;
4085}
4086
4087/*
4088 * Parse pipe CRC command strings:
b94dec87
DL		 4089 * command: wsp* object wsp+ name wsp+ source wsp*
4090 * object: 'pipe'
4091 * name: (A | B | C)
926321d5
DV		 4092 * source: (none | plane1 | plane2 | pf)
4093 * wsp: (#0x20 | #0x9 | #0xA)+
4094 *
4095 * eg.:
b94dec87
DL		 4096 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4097 * "pipe A none" -> Stop CRC
926321d5 4098 */
bd9db02f 4099static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4100{
4101 int n_words = 0;
4102
4103 while (*buf) {
4104 char *end;
4105
4106 /* skip leading white space */
4107 buf = skip_spaces(buf);
4108 if (!*buf)
4109 break; /* end of buffer */
4110
4111 /* find end of word */
4112 for (end = buf; *end && !isspace(*end); end++)
4113 ;
4114
4115 if (n_words == max_words) {
4116 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4117 max_words);
4118 return -EINVAL; /* ran out of words[] before bytes */
4119 }
4120
4121 if (*end)
4122 *end++ = '\0';
4123 words[n_words++] = buf;
4124 buf = end;
4125 }
4126
4127 return n_words;
4128}
4129
b94dec87
DL		 4130enum intel_pipe_crc_object {
4131 PIPE_CRC_OBJECT_PIPE,
4132};
4133
e8dfcf78 4134static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4135 "pipe",
4136};
4137
4138static int
bd9db02f 4139display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4140{
4141 int i;
4142
4143 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4144 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4145 *o = i;
b94dec87
DL		 4146 return 0;
4147 }
4148
4149 return -EINVAL;
4150}
4151
bd9db02f 4152static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4153{
4154 const char name = buf[0];
4155
4156 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4157 return -EINVAL;
4158
4159 *pipe = name - 'A';
4160
4161 return 0;
4162}
4163
4164static int
bd9db02f 4165display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4166{
4167 int i;
4168
4169 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4170 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4171 *s = i;
926321d5
DV		 4172 return 0;
4173 }
4174
4175 return -EINVAL;
4176}
4177
bd9db02f 4178static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4179{
b94dec87 4180#define N_WORDS 3
926321d5 4181 int n_words;
b94dec87 4182 char *words[N_WORDS];
926321d5 4183 enum pipe pipe;
b94dec87 4184 enum intel_pipe_crc_object object;
926321d5
DV		 4185 enum intel_pipe_crc_source source;
4186
bd9db02f 4187 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4188 if (n_words != N_WORDS) {
4189 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4190 N_WORDS);
4191 return -EINVAL;
4192 }
4193
bd9db02f 4194 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4195 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4196 return -EINVAL;
4197 }
4198
bd9db02f 4199 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4200 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4201 return -EINVAL;
4202 }
4203
bd9db02f 4204 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4205 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4206 return -EINVAL;
4207 }
4208
4209 return pipe_crc_set_source(dev, pipe, source);
4210}
4211
bd9db02f
DL		 4212static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4213 size_t len, loff_t *offp)
926321d5
DV		 4214{
4215 struct seq_file *m = file->private_data;
4216 struct drm_device *dev = m->private;
4217 char *tmpbuf;
4218 int ret;
4219
4220 if (len == 0)
4221 return 0;
4222
4223 if (len > PAGE_SIZE - 1) {
4224 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4225 PAGE_SIZE);
4226 return -E2BIG;
4227 }
4228
4229 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4230 if (!tmpbuf)
4231 return -ENOMEM;
4232
4233 if (copy_from_user(tmpbuf, ubuf, len)) {
4234 ret = -EFAULT;
4235 goto out;
4236 }
4237 tmpbuf[len] = '\0';
4238
bd9db02f 4239 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4240
4241out:
4242 kfree(tmpbuf);
4243 if (ret < 0)
4244 return ret;
4245
4246 *offp += len;
4247 return len;
4248}
4249
bd9db02f 4250static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4251 .owner = THIS_MODULE,
bd9db02f 4252 .open = display_crc_ctl_open,
926321d5
DV		 4253 .read = seq_read,
4254 .llseek = seq_lseek,
4255 .release = single_release,
bd9db02f 4256 .write = display_crc_ctl_write
926321d5
DV		 4257};
4258
eb3394fa
TP		 4259static ssize_t i915_displayport_test_active_write(struct file *file,
4260 const char __user *ubuf,
4261 size_t len, loff_t *offp)
4262{
4263 char *input_buffer;
4264 int status = 0;
eb3394fa
TP		 4265 struct drm_device *dev;
4266 struct drm_connector *connector;
4267 struct list_head *connector_list;
4268 struct intel_dp *intel_dp;
4269 int val = 0;
4270
9aaffa34 4271 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4272
eb3394fa
TP		 4273 connector_list = &dev->mode_config.connector_list;
4274
4275 if (len == 0)
4276 return 0;
4277
4278 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4279 if (!input_buffer)
4280 return -ENOMEM;
4281
4282 if (copy_from_user(input_buffer, ubuf, len)) {
4283 status = -EFAULT;
4284 goto out;
4285 }
4286
4287 input_buffer[len] = '\0';
4288 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4289
4290 list_for_each_entry(connector, connector_list, head) {
4291
4292 if (connector->connector_type !=
4293 DRM_MODE_CONNECTOR_DisplayPort)
4294 continue;
4295
b8bb08ec 4296 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4297 connector->encoder != NULL) {
4298 intel_dp = enc_to_intel_dp(connector->encoder);
4299 status = kstrtoint(input_buffer, 10, &val);
4300 if (status < 0)
4301 goto out;
4302 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4303 /* To prevent erroneous activation of the compliance
4304 * testing code, only accept an actual value of 1 here
4305 */
4306 if (val == 1)
4307 intel_dp->compliance_test_active = 1;
4308 else
4309 intel_dp->compliance_test_active = 0;
4310 }
4311 }
4312out:
4313 kfree(input_buffer);
4314 if (status < 0)
4315 return status;
4316
4317 *offp += len;
4318 return len;
4319}
4320
4321static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4322{
4323 struct drm_device *dev = m->private;
4324 struct drm_connector *connector;
4325 struct list_head *connector_list = &dev->mode_config.connector_list;
4326 struct intel_dp *intel_dp;
4327
eb3394fa
TP		 4328 list_for_each_entry(connector, connector_list, head) {
4329
4330 if (connector->connector_type !=
4331 DRM_MODE_CONNECTOR_DisplayPort)
4332 continue;
4333
4334 if (connector->status == connector_status_connected &&
4335 connector->encoder != NULL) {
4336 intel_dp = enc_to_intel_dp(connector->encoder);
4337 if (intel_dp->compliance_test_active)
4338 seq_puts(m, "1");
4339 else
4340 seq_puts(m, "0");
4341 } else
4342 seq_puts(m, "0");
4343 }
4344
4345 return 0;
4346}
4347
4348static int i915_displayport_test_active_open(struct inode *inode,
4349 struct file *file)
4350{
4351 struct drm_device *dev = inode->i_private;
4352
4353 return single_open(file, i915_displayport_test_active_show, dev);
4354}
4355
4356static const struct file_operations i915_displayport_test_active_fops = {
4357 .owner = THIS_MODULE,
4358 .open = i915_displayport_test_active_open,
4359 .read = seq_read,
4360 .llseek = seq_lseek,
4361 .release = single_release,
4362 .write = i915_displayport_test_active_write
4363};
4364
4365static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4366{
4367 struct drm_device *dev = m->private;
4368 struct drm_connector *connector;
4369 struct list_head *connector_list = &dev->mode_config.connector_list;
4370 struct intel_dp *intel_dp;
4371
eb3394fa
TP		 4372 list_for_each_entry(connector, connector_list, head) {
4373
4374 if (connector->connector_type !=
4375 DRM_MODE_CONNECTOR_DisplayPort)
4376 continue;
4377
4378 if (connector->status == connector_status_connected &&
4379 connector->encoder != NULL) {
4380 intel_dp = enc_to_intel_dp(connector->encoder);
4381 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4382 } else
4383 seq_puts(m, "0");
4384 }
4385
4386 return 0;
4387}
4388static int i915_displayport_test_data_open(struct inode *inode,
4389 struct file *file)
4390{
4391 struct drm_device *dev = inode->i_private;
4392
4393 return single_open(file, i915_displayport_test_data_show, dev);
4394}
4395
4396static const struct file_operations i915_displayport_test_data_fops = {
4397 .owner = THIS_MODULE,
4398 .open = i915_displayport_test_data_open,
4399 .read = seq_read,
4400 .llseek = seq_lseek,
4401 .release = single_release
4402};
4403
4404static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4405{
4406 struct drm_device *dev = m->private;
4407 struct drm_connector *connector;
4408 struct list_head *connector_list = &dev->mode_config.connector_list;
4409 struct intel_dp *intel_dp;
4410
eb3394fa
TP		 4411 list_for_each_entry(connector, connector_list, head) {
4412
4413 if (connector->connector_type !=
4414 DRM_MODE_CONNECTOR_DisplayPort)
4415 continue;
4416
4417 if (connector->status == connector_status_connected &&
4418 connector->encoder != NULL) {
4419 intel_dp = enc_to_intel_dp(connector->encoder);
4420 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4421 } else
4422 seq_puts(m, "0");
4423 }
4424
4425 return 0;
4426}
4427
4428static int i915_displayport_test_type_open(struct inode *inode,
4429 struct file *file)
4430{
4431 struct drm_device *dev = inode->i_private;
4432
4433 return single_open(file, i915_displayport_test_type_show, dev);
4434}
4435
4436static const struct file_operations i915_displayport_test_type_fops = {
4437 .owner = THIS_MODULE,
4438 .open = i915_displayport_test_type_open,
4439 .read = seq_read,
4440 .llseek = seq_lseek,
4441 .release = single_release
4442};
4443
97e94b22 4444static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4445{
4446 struct drm_device *dev = m->private;
369a1342 4447 int level;
de38b95c
VS		 4448 int num_levels;
4449
4450 if (IS_CHERRYVIEW(dev))
4451 num_levels = 3;
4452 else if (IS_VALLEYVIEW(dev))
4453 num_levels = 1;
4454 else
4455 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4456
4457 drm_modeset_lock_all(dev);
4458
4459 for (level = 0; level < num_levels; level++) {
4460 unsigned int latency = wm[level];
4461
97e94b22
DL		 4462 /*
4463 * - WM1+ latency values in 0.5us units
de38b95c 4464 * - latencies are in us on gen9/vlv/chv
97e94b22 4465 */
666a4537
WB		 4466 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4467 IS_CHERRYVIEW(dev))
97e94b22
DL		 4468 latency *= 10;
4469 else if (level > 0)
369a1342
VS		 4470 latency *= 5;
4471
4472 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4473 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4474 }
4475
4476 drm_modeset_unlock_all(dev);
4477}
4478
4479static int pri_wm_latency_show(struct seq_file *m, void *data)
4480{
4481 struct drm_device *dev = m->private;
97e94b22
DL		 4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483 const uint16_t *latencies;
4484
4485 if (INTEL_INFO(dev)->gen >= 9)
4486 latencies = dev_priv->wm.skl_latency;
4487 else
4488 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4489
97e94b22 4490 wm_latency_show(m, latencies);
369a1342
VS		 4491
4492 return 0;
4493}
4494
4495static int spr_wm_latency_show(struct seq_file *m, void *data)
4496{
4497 struct drm_device *dev = m->private;
97e94b22
DL		 4498 struct drm_i915_private *dev_priv = dev->dev_private;
4499 const uint16_t *latencies;
4500
4501 if (INTEL_INFO(dev)->gen >= 9)
4502 latencies = dev_priv->wm.skl_latency;
4503 else
4504 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4505
97e94b22 4506 wm_latency_show(m, latencies);
369a1342
VS		 4507
4508 return 0;
4509}
4510
4511static int cur_wm_latency_show(struct seq_file *m, void *data)
4512{
4513 struct drm_device *dev = m->private;
97e94b22
DL		 4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 const uint16_t *latencies;
4516
4517 if (INTEL_INFO(dev)->gen >= 9)
4518 latencies = dev_priv->wm.skl_latency;
4519 else
4520 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4521
97e94b22 4522 wm_latency_show(m, latencies);
369a1342
VS		 4523
4524 return 0;
4525}
4526
4527static int pri_wm_latency_open(struct inode *inode, struct file *file)
4528{
4529 struct drm_device *dev = inode->i_private;
4530
de38b95c 4531 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4532 return -ENODEV;
4533
4534 return single_open(file, pri_wm_latency_show, dev);
4535}
4536
4537static int spr_wm_latency_open(struct inode *inode, struct file *file)
4538{
4539 struct drm_device *dev = inode->i_private;
4540
9ad0257c 4541 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4542 return -ENODEV;
4543
4544 return single_open(file, spr_wm_latency_show, dev);
4545}
4546
4547static int cur_wm_latency_open(struct inode *inode, struct file *file)
4548{
4549 struct drm_device *dev = inode->i_private;
4550
9ad0257c 4551 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4552 return -ENODEV;
4553
4554 return single_open(file, cur_wm_latency_show, dev);
4555}
4556
4557static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4558 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4559{
4560 struct seq_file *m = file->private_data;
4561 struct drm_device *dev = m->private;
97e94b22 4562 uint16_t new[8] = { 0 };
de38b95c 4563 int num_levels;
369a1342
VS		 4564 int level;
4565 int ret;
4566 char tmp[32];
4567
de38b95c
VS		 4568 if (IS_CHERRYVIEW(dev))
4569 num_levels = 3;
4570 else if (IS_VALLEYVIEW(dev))
4571 num_levels = 1;
4572 else
4573 num_levels = ilk_wm_max_level(dev) + 1;
4574
369a1342
VS		 4575 if (len >= sizeof(tmp))
4576 return -EINVAL;
4577
4578 if (copy_from_user(tmp, ubuf, len))
4579 return -EFAULT;
4580
4581 tmp[len] = '\0';
4582
97e94b22
DL		 4583 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4584 &new[0], &new[1], &new[2], &new[3],
4585 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4586 if (ret != num_levels)
4587 return -EINVAL;
4588
4589 drm_modeset_lock_all(dev);
4590
4591 for (level = 0; level < num_levels; level++)
4592 wm[level] = new[level];
4593
4594 drm_modeset_unlock_all(dev);
4595
4596 return len;
4597}
4598
4599
4600static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4601 size_t len, loff_t *offp)
4602{
4603 struct seq_file *m = file->private_data;
4604 struct drm_device *dev = m->private;
97e94b22
DL		 4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 uint16_t *latencies;
369a1342 4607
97e94b22
DL		 4608 if (INTEL_INFO(dev)->gen >= 9)
4609 latencies = dev_priv->wm.skl_latency;
4610 else
4611 latencies = to_i915(dev)->wm.pri_latency;
4612
4613 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4614}
4615
4616static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4617 size_t len, loff_t *offp)
4618{
4619 struct seq_file *m = file->private_data;
4620 struct drm_device *dev = m->private;
97e94b22
DL		 4621 struct drm_i915_private *dev_priv = dev->dev_private;
4622 uint16_t *latencies;
369a1342 4623
97e94b22
DL		 4624 if (INTEL_INFO(dev)->gen >= 9)
4625 latencies = dev_priv->wm.skl_latency;
4626 else
4627 latencies = to_i915(dev)->wm.spr_latency;
4628
4629 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4630}
4631
4632static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4633 size_t len, loff_t *offp)
4634{
4635 struct seq_file *m = file->private_data;
4636 struct drm_device *dev = m->private;
97e94b22
DL		 4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638 uint16_t *latencies;
4639
4640 if (INTEL_INFO(dev)->gen >= 9)
4641 latencies = dev_priv->wm.skl_latency;
4642 else
4643 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4644
97e94b22 4645 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4646}
4647
4648static const struct file_operations i915_pri_wm_latency_fops = {
4649 .owner = THIS_MODULE,
4650 .open = pri_wm_latency_open,
4651 .read = seq_read,
4652 .llseek = seq_lseek,
4653 .release = single_release,
4654 .write = pri_wm_latency_write
4655};
4656
4657static const struct file_operations i915_spr_wm_latency_fops = {
4658 .owner = THIS_MODULE,
4659 .open = spr_wm_latency_open,
4660 .read = seq_read,
4661 .llseek = seq_lseek,
4662 .release = single_release,
4663 .write = spr_wm_latency_write
4664};
4665
4666static const struct file_operations i915_cur_wm_latency_fops = {
4667 .owner = THIS_MODULE,
4668 .open = cur_wm_latency_open,
4669 .read = seq_read,
4670 .llseek = seq_lseek,
4671 .release = single_release,
4672 .write = cur_wm_latency_write
4673};
4674
647416f9
KC		 4675static int
4676i915_wedged_get(void *data, u64 *val)
f3cd474b 4677{
647416f9 4678 struct drm_device *dev = data;
e277a1f8 4679 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4680
647416f9 4681 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4682
647416f9 4683 return 0;
f3cd474b
CW		 4684}
4685
647416f9
KC		 4686static int
4687i915_wedged_set(void *data, u64 val)
f3cd474b 4688{
647416f9 4689 struct drm_device *dev = data;
d46c0517
ID		 4690 struct drm_i915_private *dev_priv = dev->dev_private;
4691
b8d24a06
MK		 4692 /*
4693 * There is no safeguard against this debugfs entry colliding
4694 * with the hangcheck calling same i915_handle_error() in
4695 * parallel, causing an explosion. For now we assume that the
4696 * test harness is responsible enough not to inject gpu hangs
4697 * while it is writing to 'i915_wedged'
4698 */
4699
4700 if (i915_reset_in_progress(&dev_priv->gpu_error))
4701 return -EAGAIN;
4702
d46c0517 4703 intel_runtime_pm_get(dev_priv);
f3cd474b 4704
58174462
MK		 4705 i915_handle_error(dev, val,
4706 "Manually setting wedged to %llu", val);
d46c0517
ID		 4707
4708 intel_runtime_pm_put(dev_priv);
4709
647416f9 4710 return 0;
f3cd474b
CW		 4711}
4712
647416f9
KC		 4713DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4714 i915_wedged_get, i915_wedged_set,
3a3b4f98 4715 "%llu\n");
f3cd474b 4716
647416f9
KC		 4717static int
4718i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4719{
647416f9 4720 struct drm_device *dev = data;
e277a1f8 4721 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4722
647416f9 4723 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4724
647416f9 4725 return 0;
e5eb3d63
DV		 4726}
4727
647416f9
KC		 4728static int
4729i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4730{
647416f9 4731 struct drm_device *dev = data;
e5eb3d63 4732 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4733 int ret;
e5eb3d63 4734
647416f9 4735 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4736
22bcfc6a
DV		 4737 ret = mutex_lock_interruptible(&dev->struct_mutex);
4738 if (ret)
4739 return ret;
4740
99584db3 4741 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4742 mutex_unlock(&dev->struct_mutex);
4743
647416f9 4744 return 0;
e5eb3d63
DV		 4745}
4746
647416f9
KC		 4747DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4748 i915_ring_stop_get, i915_ring_stop_set,
4749 "0x%08llx\n");
d5442303 4750
094f9a54
CW		 4751static int
4752i915_ring_missed_irq_get(void *data, u64 *val)
4753{
4754 struct drm_device *dev = data;
4755 struct drm_i915_private *dev_priv = dev->dev_private;
4756
4757 *val = dev_priv->gpu_error.missed_irq_rings;
4758 return 0;
4759}
4760
4761static int
4762i915_ring_missed_irq_set(void *data, u64 val)
4763{
4764 struct drm_device *dev = data;
4765 struct drm_i915_private *dev_priv = dev->dev_private;
4766 int ret;
4767
4768 /* Lock against concurrent debugfs callers */
4769 ret = mutex_lock_interruptible(&dev->struct_mutex);
4770 if (ret)
4771 return ret;
4772 dev_priv->gpu_error.missed_irq_rings = val;
4773 mutex_unlock(&dev->struct_mutex);
4774
4775 return 0;
4776}
4777
4778DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4779 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4780 "0x%08llx\n");
4781
4782static int
4783i915_ring_test_irq_get(void *data, u64 *val)
4784{
4785 struct drm_device *dev = data;
4786 struct drm_i915_private *dev_priv = dev->dev_private;
4787
4788 *val = dev_priv->gpu_error.test_irq_rings;
4789
4790 return 0;
4791}
4792
4793static int
4794i915_ring_test_irq_set(void *data, u64 val)
4795{
4796 struct drm_device *dev = data;
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 int ret;
4799
4800 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4801
4802 /* Lock against concurrent debugfs callers */
4803 ret = mutex_lock_interruptible(&dev->struct_mutex);
4804 if (ret)
4805 return ret;
4806
4807 dev_priv->gpu_error.test_irq_rings = val;
4808 mutex_unlock(&dev->struct_mutex);
4809
4810 return 0;
4811}
4812
4813DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4814 i915_ring_test_irq_get, i915_ring_test_irq_set,
4815 "0x%08llx\n");
4816
dd624afd
CW		 4817#define DROP_UNBOUND 0x1
4818#define DROP_BOUND 0x2
4819#define DROP_RETIRE 0x4
4820#define DROP_ACTIVE 0x8
4821#define DROP_ALL (DROP_UNBOUND | \
4822 DROP_BOUND | \
4823 DROP_RETIRE | \
4824 DROP_ACTIVE)
647416f9
KC		 4825static int
4826i915_drop_caches_get(void *data, u64 *val)
dd624afd 4827{
647416f9 4828 *val = DROP_ALL;
dd624afd 4829
647416f9 4830 return 0;
dd624afd
CW		 4831}
4832
647416f9
KC		 4833static int
4834i915_drop_caches_set(void *data, u64 val)
dd624afd 4835{
647416f9 4836 struct drm_device *dev = data;
dd624afd 4837 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4838 int ret;
dd624afd 4839
2f9fe5ff 4840 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4841
4842 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4843 * on ioctls on -EAGAIN. */
4844 ret = mutex_lock_interruptible(&dev->struct_mutex);
4845 if (ret)
4846 return ret;
4847
4848 if (val & DROP_ACTIVE) {
4849 ret = i915_gpu_idle(dev);
4850 if (ret)
4851 goto unlock;
4852 }
4853
4854 if (val & (DROP_RETIRE | DROP_ACTIVE))
4855 i915_gem_retire_requests(dev);
4856
21ab4e74
CW		 4857 if (val & DROP_BOUND)
4858 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4859
21ab4e74
CW		 4860 if (val & DROP_UNBOUND)
4861 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4862
4863unlock:
4864 mutex_unlock(&dev->struct_mutex);
4865
647416f9 4866 return ret;
dd624afd
CW		 4867}
4868
647416f9
KC		 4869DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4870 i915_drop_caches_get, i915_drop_caches_set,
4871 "0x%08llx\n");
dd624afd 4872
647416f9
KC		 4873static int
4874i915_max_freq_get(void *data, u64 *val)
358733e9 4875{
647416f9 4876 struct drm_device *dev = data;
e277a1f8 4877 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4878 int ret;
004777cb 4879
daa3afb2 4880 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4881 return -ENODEV;
4882
5c9669ce
TR		 4883 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4884
4fc688ce 4885 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4886 if (ret)
4887 return ret;
358733e9 4888
7c59a9c1 4889 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4890 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4891
647416f9 4892 return 0;
358733e9
JB		 4893}
4894
647416f9
KC		 4895static int
4896i915_max_freq_set(void *data, u64 val)
358733e9 4897{
647416f9 4898 struct drm_device *dev = data;
358733e9 4899 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4900 u32 hw_max, hw_min;
647416f9 4901 int ret;
004777cb 4902
daa3afb2 4903 if (INTEL_INFO(dev)->gen < 6)
004777cb 4904 return -ENODEV;
358733e9 4905
5c9669ce
TR		 4906 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4907
647416f9 4908 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4909
4fc688ce 4910 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4911 if (ret)
4912 return ret;
4913
358733e9
JB		 4914 /*
4915 * Turbo will still be enabled, but won't go above the set value.
4916 */
bc4d91f6 4917 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4918
bc4d91f6
AG		 4919 hw_max = dev_priv->rps.max_freq;
4920 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4921
b39fb297 4922 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4923 mutex_unlock(&dev_priv->rps.hw_lock);
4924 return -EINVAL;
0a073b84
JB		 4925 }
4926
b39fb297 4927 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4928
ffe02b40 4929 intel_set_rps(dev, val);
dd0a1aa1 4930
4fc688ce 4931 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4932
647416f9 4933 return 0;
358733e9
JB		 4934}
4935
647416f9
KC		 4936DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4937 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4938 "%llu\n");
358733e9 4939
647416f9
KC		 4940static int
4941i915_min_freq_get(void *data, u64 *val)
1523c310 4942{
647416f9 4943 struct drm_device *dev = data;
e277a1f8 4944 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4945 int ret;
004777cb 4946
daa3afb2 4947 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4948 return -ENODEV;
4949
5c9669ce
TR		 4950 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4951
4fc688ce 4952 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4953 if (ret)
4954 return ret;
1523c310 4955
7c59a9c1 4956 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4957 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4958
647416f9 4959 return 0;
1523c310
JB		 4960}
4961
647416f9
KC		 4962static int
4963i915_min_freq_set(void *data, u64 val)
1523c310 4964{
647416f9 4965 struct drm_device *dev = data;
1523c310 4966 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4967 u32 hw_max, hw_min;
647416f9 4968 int ret;
004777cb 4969
daa3afb2 4970 if (INTEL_INFO(dev)->gen < 6)
004777cb 4971 return -ENODEV;
1523c310 4972
5c9669ce
TR		 4973 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4974
647416f9 4975 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4976
4fc688ce 4977 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4978 if (ret)
4979 return ret;
4980
1523c310
JB		 4981 /*
4982 * Turbo will still be enabled, but won't go below the set value.
4983 */
bc4d91f6 4984 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4985
bc4d91f6
AG		 4986 hw_max = dev_priv->rps.max_freq;
4987 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4988
b39fb297 4989 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4990 mutex_unlock(&dev_priv->rps.hw_lock);
4991 return -EINVAL;
0a073b84 4992 }
dd0a1aa1 4993
b39fb297 4994 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4995
ffe02b40 4996 intel_set_rps(dev, val);
dd0a1aa1 4997
4fc688ce 4998 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4999
647416f9 5000 return 0;
1523c310
JB		 5001}
5002
647416f9
KC		 5003DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5004 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 5005 "%llu\n");
1523c310 5006
647416f9
KC		 5007static int
5008i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 5009{
647416f9 5010 struct drm_device *dev = data;
e277a1f8 5011 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5012 u32 snpcr;
647416f9 5013 int ret;
07b7ddd9 5014
004777cb
DV		 5015 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5016 return -ENODEV;
5017
22bcfc6a
DV		 5018 ret = mutex_lock_interruptible(&dev->struct_mutex);
5019 if (ret)
5020 return ret;
c8c8fb33 5021 intel_runtime_pm_get(dev_priv);
22bcfc6a 5022
07b7ddd9 5023 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 5024
5025 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 5026 mutex_unlock(&dev_priv->dev->struct_mutex);
5027
647416f9 5028 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 5029
647416f9 5030 return 0;
07b7ddd9
JB		 5031}
5032
647416f9
KC		 5033static int
5034i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 5035{
647416f9 5036 struct drm_device *dev = data;
07b7ddd9 5037 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5038 u32 snpcr;
07b7ddd9 5039
004777cb
DV		 5040 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5041 return -ENODEV;
5042
647416f9 5043 if (val > 3)
07b7ddd9
JB		 5044 return -EINVAL;
5045
c8c8fb33 5046 intel_runtime_pm_get(dev_priv);
647416f9 5047 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 5048
5049 /* Update the cache sharing policy here as well */
5050 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5051 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5052 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5053 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5054
c8c8fb33 5055 intel_runtime_pm_put(dev_priv);
647416f9 5056 return 0;
07b7ddd9
JB		 5057}
5058
647416f9
KC		 5059DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5060 i915_cache_sharing_get, i915_cache_sharing_set,
5061 "%llu\n");
07b7ddd9 5062
5d39525a
JM		 5063struct sseu_dev_status {
5064 unsigned int slice_total;
5065 unsigned int subslice_total;
5066 unsigned int subslice_per_slice;
5067 unsigned int eu_total;
5068 unsigned int eu_per_subslice;
5069};
5070
5071static void cherryview_sseu_device_status(struct drm_device *dev,
5072 struct sseu_dev_status *stat)
5073{
5074 struct drm_i915_private *dev_priv = dev->dev_private;
0a0b457f 5075 int ss_max = 2;
5d39525a
JM		 5076 int ss;
5077 u32 sig1[ss_max], sig2[ss_max];
5078
5079 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5080 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5081 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5082 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5083
5084 for (ss = 0; ss < ss_max; ss++) {
5085 unsigned int eu_cnt;
5086
5087 if (sig1[ss] & CHV_SS_PG_ENABLE)
5088 /* skip disabled subslice */
5089 continue;
5090
5091 stat->slice_total = 1;
5092 stat->subslice_per_slice++;
5093 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5094 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5095 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5096 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5097 stat->eu_total += eu_cnt;
5098 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5099 }
5100 stat->subslice_total = stat->subslice_per_slice;
5101}
5102
5103static void gen9_sseu_device_status(struct drm_device *dev,
5104 struct sseu_dev_status *stat)
5105{
5106 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 5107 int s_max = 3, ss_max = 4;
5d39525a
JM		 5108 int s, ss;
5109 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5110
1c046bc1
JM		 5111 /* BXT has a single slice and at most 3 subslices. */
5112 if (IS_BROXTON(dev)) {
5113 s_max = 1;
5114 ss_max = 3;
5115 }
5116
5117 for (s = 0; s < s_max; s++) {
5118 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5119 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5120 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5121 }
5122
5d39525a
JM		 5123 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5124 GEN9_PGCTL_SSA_EU19_ACK |
5125 GEN9_PGCTL_SSA_EU210_ACK |
5126 GEN9_PGCTL_SSA_EU311_ACK;
5127 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5128 GEN9_PGCTL_SSB_EU19_ACK |
5129 GEN9_PGCTL_SSB_EU210_ACK |
5130 GEN9_PGCTL_SSB_EU311_ACK;
5131
5132 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5133 unsigned int ss_cnt = 0;
5134
5d39525a
JM		 5135 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5136 /* skip disabled slice */
5137 continue;
5138
5139 stat->slice_total++;
1c046bc1 5140
ef11bdb3 5141 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1c046bc1
JM		 5142 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5143
5d39525a
JM		 5144 for (ss = 0; ss < ss_max; ss++) {
5145 unsigned int eu_cnt;
5146
1c046bc1
JM		 5147 if (IS_BROXTON(dev) &&
5148 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5149 /* skip disabled subslice */
5150 continue;
5151
5152 if (IS_BROXTON(dev))
5153 ss_cnt++;
5154
5d39525a
JM		 5155 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5156 eu_mask[ss%2]);
5157 stat->eu_total += eu_cnt;
5158 stat->eu_per_subslice = max(stat->eu_per_subslice,
5159 eu_cnt);
5160 }
1c046bc1
JM		 5161
5162 stat->subslice_total += ss_cnt;
5163 stat->subslice_per_slice = max(stat->subslice_per_slice,
5164 ss_cnt);
5d39525a
JM		 5165 }
5166}
5167
91bedd34
ŁD		 5168static void broadwell_sseu_device_status(struct drm_device *dev,
5169 struct sseu_dev_status *stat)
5170{
5171 struct drm_i915_private *dev_priv = dev->dev_private;
5172 int s;
5173 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5174
5175 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5176
5177 if (stat->slice_total) {
5178 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5179 stat->subslice_total = stat->slice_total *
5180 stat->subslice_per_slice;
5181 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5182 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5183
5184 /* subtract fused off EU(s) from enabled slice(s) */
5185 for (s = 0; s < stat->slice_total; s++) {
5186 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5187
5188 stat->eu_total -= hweight8(subslice_7eu);
5189 }
5190 }
5191}
5192
3873218f
JM		 5193static int i915_sseu_status(struct seq_file *m, void *unused)
5194{
5195 struct drm_info_node *node = (struct drm_info_node *) m->private;
5196 struct drm_device *dev = node->minor->dev;
5d39525a 5197 struct sseu_dev_status stat;
3873218f 5198
91bedd34 5199 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5200 return -ENODEV;
5201
5202 seq_puts(m, "SSEU Device Info\n");
5203 seq_printf(m, " Available Slice Total: %u\n",
5204 INTEL_INFO(dev)->slice_total);
5205 seq_printf(m, " Available Subslice Total: %u\n",
5206 INTEL_INFO(dev)->subslice_total);
5207 seq_printf(m, " Available Subslice Per Slice: %u\n",
5208 INTEL_INFO(dev)->subslice_per_slice);
5209 seq_printf(m, " Available EU Total: %u\n",
5210 INTEL_INFO(dev)->eu_total);
5211 seq_printf(m, " Available EU Per Subslice: %u\n",
5212 INTEL_INFO(dev)->eu_per_subslice);
5213 seq_printf(m, " Has Slice Power Gating: %s\n",
5214 yesno(INTEL_INFO(dev)->has_slice_pg));
5215 seq_printf(m, " Has Subslice Power Gating: %s\n",
5216 yesno(INTEL_INFO(dev)->has_subslice_pg));
5217 seq_printf(m, " Has EU Power Gating: %s\n",
5218 yesno(INTEL_INFO(dev)->has_eu_pg));
5219
7f992aba 5220 seq_puts(m, "SSEU Device Status\n");
5d39525a 5221 memset(&stat, 0, sizeof(stat));
5575f03a 5222 if (IS_CHERRYVIEW(dev)) {
5d39525a 5223 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5224 } else if (IS_BROADWELL(dev)) {
5225 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5226 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5227 gen9_sseu_device_status(dev, &stat);
7f992aba 5228 }
5d39525a
JM		 5229 seq_printf(m, " Enabled Slice Total: %u\n",
5230 stat.slice_total);
5231 seq_printf(m, " Enabled Subslice Total: %u\n",
5232 stat.subslice_total);
5233 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5234 stat.subslice_per_slice);
5235 seq_printf(m, " Enabled EU Total: %u\n",
5236 stat.eu_total);
5237 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5238 stat.eu_per_subslice);
7f992aba 5239
3873218f
JM		 5240 return 0;
5241}
5242
6d794d42
BW		 5243static int i915_forcewake_open(struct inode *inode, struct file *file)
5244{
5245 struct drm_device *dev = inode->i_private;
5246 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5247
075edca4 5248 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5249 return 0;
5250
6daccb0b 5251 intel_runtime_pm_get(dev_priv);
59bad947 5252 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5253
5254 return 0;
5255}
5256
c43b5634 5257static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5258{
5259 struct drm_device *dev = inode->i_private;
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261
075edca4 5262 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5263 return 0;
5264
59bad947 5265 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5266 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5267
5268 return 0;
5269}
5270
5271static const struct file_operations i915_forcewake_fops = {
5272 .owner = THIS_MODULE,
5273 .open = i915_forcewake_open,
5274 .release = i915_forcewake_release,
5275};
5276
5277static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5278{
5279 struct drm_device *dev = minor->dev;
5280 struct dentry *ent;
5281
5282 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5283 S_IRUSR,
6d794d42
BW		 5284 root, dev,
5285 &i915_forcewake_fops);
f3c5fe97
WY		 5286 if (!ent)
5287 return -ENOMEM;
6d794d42 5288
8eb57294 5289 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5290}
5291
6a9c308d
DV		 5292static int i915_debugfs_create(struct dentry *root,
5293 struct drm_minor *minor,
5294 const char *name,
5295 const struct file_operations *fops)
07b7ddd9
JB		 5296{
5297 struct drm_device *dev = minor->dev;
5298 struct dentry *ent;
5299
6a9c308d 5300 ent = debugfs_create_file(name,
07b7ddd9
JB		 5301 S_IRUGO | S_IWUSR,
5302 root, dev,
6a9c308d 5303 fops);
f3c5fe97
WY		 5304 if (!ent)
5305 return -ENOMEM;
07b7ddd9 5306
6a9c308d 5307 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5308}
5309
06c5bf8c 5310static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5311 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5312 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5313 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5314 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5315 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5316 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5317 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5318 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5319 {"i915_gem_request", i915_gem_request_info, 0},
5320 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5321 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5322 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5323 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5324 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5325 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5326 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5327 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5328 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5329 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5330 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5331 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5332 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5333 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5334 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5335 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5336 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5337 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5338 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5339 {"i915_sr_status", i915_sr_status, 0},
44834a67 5340 {"i915_opregion", i915_opregion, 0},
ada8f955 5341 {"i915_vbt", i915_vbt, 0},
37811fcc 5342 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5343 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5344 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5345 {"i915_execlists", i915_execlists, 0},
f65367b5 5346 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5347 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5348 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5349 {"i915_llc", i915_llc, 0},
e91fd8c6 5350 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5351 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5352 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5353 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5354 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5355 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5356 {"i915_display_info", i915_display_info, 0},
e04934cf 5357 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5358 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5359 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5360 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5361 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5362 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5363 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5364 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5365};
27c202ad 5366#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5367
06c5bf8c 5368static const struct i915_debugfs_files {
34b9674c
DV		 5369 const char *name;
5370 const struct file_operations *fops;
5371} i915_debugfs_files[] = {
5372 {"i915_wedged", &i915_wedged_fops},
5373 {"i915_max_freq", &i915_max_freq_fops},
5374 {"i915_min_freq", &i915_min_freq_fops},
5375 {"i915_cache_sharing", &i915_cache_sharing_fops},
5376 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5377 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5378 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5379 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5380 {"i915_error_state", &i915_error_state_fops},
5381 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5382 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5383 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5384 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5385 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5386 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5387 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5388 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5389 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5390};
5391
07144428
DL		 5392void intel_display_crc_init(struct drm_device *dev)
5393{
5394 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5395 enum pipe pipe;
07144428 5396
055e393f 5397 for_each_pipe(dev_priv, pipe) {
b378360e 5398 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5399
d538bbdf
DL		 5400 pipe_crc->opened = false;
5401 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5402 init_waitqueue_head(&pipe_crc->wq);
5403 }
5404}
5405
27c202ad 5406int i915_debugfs_init(struct drm_minor *minor)
2017263e 5407{
34b9674c 5408 int ret, i;
f3cd474b 5409
6d794d42 5410 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5411 if (ret)
5412 return ret;
6a9c308d 5413
07144428
DL		 5414 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5415 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5416 if (ret)
5417 return ret;
5418 }
5419
34b9674c
DV		 5420 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5421 ret = i915_debugfs_create(minor->debugfs_root, minor,
5422 i915_debugfs_files[i].name,
5423 i915_debugfs_files[i].fops);
5424 if (ret)
5425 return ret;
5426 }
40633219 5427
27c202ad
BG		 5428 return drm_debugfs_create_files(i915_debugfs_list,
5429 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5430 minor->debugfs_root, minor);
5431}
5432
27c202ad 5433void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5434{
34b9674c
DV		 5435 int i;
5436
27c202ad
BG		 5437 drm_debugfs_remove_files(i915_debugfs_list,
5438 I915_DEBUGFS_ENTRIES, minor);
07144428 5439
6d794d42
BW		 5440 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5441 1, minor);
07144428 5442
e309a997 5443 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5444 struct drm_info_list *info_list =
5445 (struct drm_info_list *)&i915_pipe_crc_data[i];
5446
5447 drm_debugfs_remove_files(info_list, 1, minor);
5448 }
5449
34b9674c
DV		 5450 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5451 struct drm_info_list *info_list =
5452 (struct drm_info_list *) i915_debugfs_files[i].fops;
5453
5454 drm_debugfs_remove_files(info_list, 1, minor);
5455 }
2017263e 5456}
aa7471d2
JN		 5457
5458struct dpcd_block {
5459 /* DPCD dump start address. */
5460 unsigned int offset;
5461 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5462 unsigned int end;
5463 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5464 size_t size;
5465 /* Only valid for eDP. */
5466 bool edp;
5467};
5468
5469static const struct dpcd_block i915_dpcd_debug[] = {
5470 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5471 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5472 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5473 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5474 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5475 { .offset = DP_SET_POWER },
5476 { .offset = DP_EDP_DPCD_REV },
5477 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5478 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5479 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5480};
5481
5482static int i915_dpcd_show(struct seq_file *m, void *data)
5483{
5484 struct drm_connector *connector = m->private;
5485 struct intel_dp *intel_dp =
5486 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5487 uint8_t buf[16];
5488 ssize_t err;
5489 int i;
5490
5c1a8875
MK		 5491 if (connector->status != connector_status_connected)
5492 return -ENODEV;
5493
aa7471d2
JN		 5494 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5495 const struct dpcd_block *b = &i915_dpcd_debug[i];
5496 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5497
5498 if (b->edp &&
5499 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5500 continue;
5501
5502 /* low tech for now */
5503 if (WARN_ON(size > sizeof(buf)))
5504 continue;
5505
5506 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5507 if (err <= 0) {
5508 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5509 size, b->offset, err);
5510 continue;
5511 }
5512
5513 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5514 }
aa7471d2
JN		 5515
5516 return 0;
5517}
5518
5519static int i915_dpcd_open(struct inode *inode, struct file *file)
5520{
5521 return single_open(file, i915_dpcd_show, inode->i_private);
5522}
5523
5524static const struct file_operations i915_dpcd_fops = {
5525 .owner = THIS_MODULE,
5526 .open = i915_dpcd_open,
5527 .read = seq_read,
5528 .llseek = seq_lseek,
5529 .release = single_release,
5530};
5531
5532/**
5533 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5534 * @connector: pointer to a registered drm_connector
5535 *
5536 * Cleanup will be done by drm_connector_unregister() through a call to
5537 * drm_debugfs_connector_remove().
5538 *
5539 * Returns 0 on success, negative error codes on error.
5540 */
5541int i915_debugfs_connector_add(struct drm_connector *connector)
5542{
5543 struct dentry *root = connector->debugfs_entry;
5544
5545 /* The connector must have been registered beforehands. */
5546 if (!root)
5547 return -ENODEV;
5548
5549 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5550 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5551 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5552 &i915_dpcd_fops);
5553
5554 return 0;
5555}
Linux 6.x block layer and io_uring tree(s)