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drm/i915/chv: Determine CHV slice/subslice/EU info
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
20e28fba 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 142 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 143 if (vma->pin_count > 0)
144 pin_count++;
ba0635ff
DC		 145 }
146 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 147 if (obj->pin_display)
148 seq_printf(m, " (display)");
37811fcc
CW		 149 if (obj->fence_reg != I915_FENCE_REG_NONE)
150 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 151 list_for_each_entry(vma, &obj->vma_list, vma_link) {
152 if (!i915_is_ggtt(vma->vm))
153 seq_puts(m, " (pp");
154 else
155 seq_puts(m, " (g");
440fd528 156 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
fe14d5f4
TU		 157 vma->node.start, vma->node.size,
158 vma->ggtt_view.type);
1d693bcc 159 }
c1ad11fc 160 if (obj->stolen)
440fd528 161 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
41c52415
JH		 171 if (obj->last_read_req != NULL)
172 seq_printf(m, " (%s)",
173 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 174 if (obj->frontbuffer_bits)
175 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 176}
177
273497e5 178static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 179{
ea0c76f8 180 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 181 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
182 seq_putc(m, ' ');
183}
184
433e12f7 185static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 186{
9f25d007 187 struct drm_info_node *node = m->private;
433e12f7
BG		 188 uintptr_t list = (uintptr_t) node->info_ent->data;
189 struct list_head *head;
2017263e 190 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 193 struct i915_vma *vma;
8f2480fb
CW		 194 size_t total_obj_size, total_gtt_size;
195 int count, ret;
de227ef0
CW		 196
197 ret = mutex_lock_interruptible(&dev->struct_mutex);
198 if (ret)
199 return ret;
2017263e 200
ca191b13 201 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 202 switch (list) {
203 case ACTIVE_LIST:
267f0c90 204 seq_puts(m, "Active:\n");
5cef07e1 205 head = &vm->active_list;
433e12f7
BG		 206 break;
207 case INACTIVE_LIST:
267f0c90 208 seq_puts(m, "Inactive:\n");
5cef07e1 209 head = &vm->inactive_list;
433e12f7 210 break;
433e12f7 211 default:
de227ef0
CW		 212 mutex_unlock(&dev->struct_mutex);
213 return -EINVAL;
2017263e 214 }
2017263e 215
8f2480fb 216 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 217 list_for_each_entry(vma, head, mm_list) {
218 seq_printf(m, " ");
219 describe_obj(m, vma->obj);
220 seq_printf(m, "\n");
221 total_obj_size += vma->obj->base.size;
222 total_gtt_size += vma->node.size;
8f2480fb 223 count++;
2017263e 224 }
de227ef0 225 mutex_unlock(&dev->struct_mutex);
5e118f41 226
8f2480fb
CW		 227 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
228 count, total_obj_size, total_gtt_size);
2017263e
BG		 229 return 0;
230}
231
6d2b8885
CW		 232static int obj_rank_by_stolen(void *priv,
233 struct list_head *A, struct list_head *B)
234{
235 struct drm_i915_gem_object *a =
b25cb2f8 236 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 237 struct drm_i915_gem_object *b =
b25cb2f8 238 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 239
240 return a->stolen->start - b->stolen->start;
241}
242
243static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
244{
9f25d007 245 struct drm_info_node *node = m->private;
6d2b8885
CW		 246 struct drm_device *dev = node->minor->dev;
247 struct drm_i915_private *dev_priv = dev->dev_private;
248 struct drm_i915_gem_object *obj;
249 size_t total_obj_size, total_gtt_size;
250 LIST_HEAD(stolen);
251 int count, ret;
252
253 ret = mutex_lock_interruptible(&dev->struct_mutex);
254 if (ret)
255 return ret;
256
257 total_obj_size = total_gtt_size = count = 0;
258 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
259 if (obj->stolen == NULL)
260 continue;
261
b25cb2f8 262 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 263
264 total_obj_size += obj->base.size;
265 total_gtt_size += i915_gem_obj_ggtt_size(obj);
266 count++;
267 }
268 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
269 if (obj->stolen == NULL)
270 continue;
271
b25cb2f8 272 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 273
274 total_obj_size += obj->base.size;
275 count++;
276 }
277 list_sort(NULL, &stolen, obj_rank_by_stolen);
278 seq_puts(m, "Stolen:\n");
279 while (!list_empty(&stolen)) {
b25cb2f8 280 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 281 seq_puts(m, " ");
282 describe_obj(m, obj);
283 seq_putc(m, '\n');
b25cb2f8 284 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 285 }
286 mutex_unlock(&dev->struct_mutex);
287
288 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
289 count, total_obj_size, total_gtt_size);
290 return 0;
291}
292
6299f992
CW		 293#define count_objects(list, member) do { \
294 list_for_each_entry(obj, list, member) { \
f343c5f6 295 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 296 ++count; \
297 if (obj->map_and_fenceable) { \
f343c5f6 298 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 299 ++mappable_count; \
300 } \
301 } \
0206e353 302} while (0)
6299f992 303
2db8e9d6 304struct file_stats {
6313c204 305 struct drm_i915_file_private *file_priv;
2db8e9d6 306 int count;
c67a17e9
CW		 307 size_t total, unbound;
308 size_t global, shared;
309 size_t active, inactive;
2db8e9d6
CW		 310};
311
312static int per_file_stats(int id, void *ptr, void *data)
313{
314 struct drm_i915_gem_object *obj = ptr;
315 struct file_stats *stats = data;
6313c204 316 struct i915_vma *vma;
2db8e9d6
CW		 317
318 stats->count++;
319 stats->total += obj->base.size;
320
c67a17e9
CW		 321 if (obj->base.name || obj->base.dma_buf)
322 stats->shared += obj->base.size;
323
6313c204
CW		 324 if (USES_FULL_PPGTT(obj->base.dev)) {
325 list_for_each_entry(vma, &obj->vma_list, vma_link) {
326 struct i915_hw_ppgtt *ppgtt;
327
328 if (!drm_mm_node_allocated(&vma->node))
329 continue;
330
331 if (i915_is_ggtt(vma->vm)) {
332 stats->global += obj->base.size;
333 continue;
334 }
335
336 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 337 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 338 continue;
339
41c52415 340 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 341 stats->active += obj->base.size;
342 else
343 stats->inactive += obj->base.size;
344
345 return 0;
346 }
2db8e9d6 347 } else {
6313c204
CW		 348 if (i915_gem_obj_ggtt_bound(obj)) {
349 stats->global += obj->base.size;
41c52415 350 if (obj->active)
6313c204
CW		 351 stats->active += obj->base.size;
352 else
353 stats->inactive += obj->base.size;
354 return 0;
355 }
2db8e9d6
CW		 356 }
357
6313c204
CW		 358 if (!list_empty(&obj->global_list))
359 stats->unbound += obj->base.size;
360
2db8e9d6
CW		 361 return 0;
362}
363
493018dc
BV		 364#define print_file_stats(m, name, stats) \
365 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
366 name, \
367 stats.count, \
368 stats.total, \
369 stats.active, \
370 stats.inactive, \
371 stats.global, \
372 stats.shared, \
373 stats.unbound)
374
375static void print_batch_pool_stats(struct seq_file *m,
376 struct drm_i915_private *dev_priv)
377{
378 struct drm_i915_gem_object *obj;
379 struct file_stats stats;
380
381 memset(&stats, 0, sizeof(stats));
382
383 list_for_each_entry(obj,
384 &dev_priv->mm.batch_pool.cache_list,
385 batch_pool_list)
386 per_file_stats(0, obj, &stats);
387
388 print_file_stats(m, "batch pool", stats);
389}
390
ca191b13
BW		 391#define count_vmas(list, member) do { \
392 list_for_each_entry(vma, list, member) { \
393 size += i915_gem_obj_ggtt_size(vma->obj); \
394 ++count; \
395 if (vma->obj->map_and_fenceable) { \
396 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
397 ++mappable_count; \
398 } \
399 } \
400} while (0)
401
402static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 403{
9f25d007 404 struct drm_info_node *node = m->private;
73aa808f
CW		 405 struct drm_device *dev = node->minor->dev;
406 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 407 u32 count, mappable_count, purgeable_count;
408 size_t size, mappable_size, purgeable_size;
6299f992 409 struct drm_i915_gem_object *obj;
5cef07e1 410 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 411 struct drm_file *file;
ca191b13 412 struct i915_vma *vma;
73aa808f
CW		 413 int ret;
414
415 ret = mutex_lock_interruptible(&dev->struct_mutex);
416 if (ret)
417 return ret;
418
6299f992
CW		 419 seq_printf(m, "%u objects, %zu bytes\n",
420 dev_priv->mm.object_count,
421 dev_priv->mm.object_memory);
422
423 size = count = mappable_size = mappable_count = 0;
35c20a60 424 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 425 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
426 count, mappable_count, size, mappable_size);
427
428 size = count = mappable_size = mappable_count = 0;
ca191b13 429 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 430 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
431 count, mappable_count, size, mappable_size);
432
6299f992 433 size = count = mappable_size = mappable_count = 0;
ca191b13 434 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 435 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
436 count, mappable_count, size, mappable_size);
437
b7abb714 438 size = count = purgeable_size = purgeable_count = 0;
35c20a60 439 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 440 size += obj->base.size, ++count;
b7abb714
CW		 441 if (obj->madv == I915_MADV_DONTNEED)
442 purgeable_size += obj->base.size, ++purgeable_count;
443 }
6c085a72
CW		 444 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
445
6299f992 446 size = count = mappable_size = mappable_count = 0;
35c20a60 447 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 448 if (obj->fault_mappable) {
f343c5f6 449 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 450 ++count;
451 }
452 if (obj->pin_mappable) {
f343c5f6 453 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 454 ++mappable_count;
455 }
b7abb714
CW		 456 if (obj->madv == I915_MADV_DONTNEED) {
457 purgeable_size += obj->base.size;
458 ++purgeable_count;
459 }
6299f992 460 }
b7abb714
CW		 461 seq_printf(m, "%u purgeable objects, %zu bytes\n",
462 purgeable_count, purgeable_size);
6299f992
CW		 463 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
464 mappable_count, mappable_size);
465 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
466 count, size);
467
93d18799 468 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 469 dev_priv->gtt.base.total,
470 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 471
493018dc
BV		 472 seq_putc(m, '\n');
473 print_batch_pool_stats(m, dev_priv);
474
267f0c90 475 seq_putc(m, '\n');
2db8e9d6
CW		 476 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
477 struct file_stats stats;
3ec2f427 478 struct task_struct *task;
2db8e9d6
CW		 479
480 memset(&stats, 0, sizeof(stats));
6313c204 481 stats.file_priv = file->driver_priv;
5b5ffff0 482 spin_lock(&file->table_lock);
2db8e9d6 483 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 484 spin_unlock(&file->table_lock);
3ec2f427
TH		 485 /*
486 * Although we have a valid reference on file->pid, that does
487 * not guarantee that the task_struct who called get_pid() is
488 * still alive (e.g. get_pid(current) => fork() => exit()).
489 * Therefore, we need to protect this ->comm access using RCU.
490 */
491 rcu_read_lock();
492 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 493 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 494 rcu_read_unlock();
2db8e9d6
CW		 495 }
496
73aa808f
CW		 497 mutex_unlock(&dev->struct_mutex);
498
499 return 0;
500}
501
aee56cff 502static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 503{
9f25d007 504 struct drm_info_node *node = m->private;
08c18323 505 struct drm_device *dev = node->minor->dev;
1b50247a 506 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 507 struct drm_i915_private *dev_priv = dev->dev_private;
508 struct drm_i915_gem_object *obj;
509 size_t total_obj_size, total_gtt_size;
510 int count, ret;
511
512 ret = mutex_lock_interruptible(&dev->struct_mutex);
513 if (ret)
514 return ret;
515
516 total_obj_size = total_gtt_size = count = 0;
35c20a60 517 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 518 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 519 continue;
520
267f0c90 521 seq_puts(m, " ");
08c18323 522 describe_obj(m, obj);
267f0c90 523 seq_putc(m, '\n');
08c18323 524 total_obj_size += obj->base.size;
f343c5f6 525 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 526 count++;
527 }
528
529 mutex_unlock(&dev->struct_mutex);
530
531 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
532 count, total_obj_size, total_gtt_size);
533
534 return 0;
535}
536
4e5359cd
SF		 537static int i915_gem_pageflip_info(struct seq_file *m, void *data)
538{
9f25d007 539 struct drm_info_node *node = m->private;
4e5359cd 540 struct drm_device *dev = node->minor->dev;
d6bbafa1 541 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 542 struct intel_crtc *crtc;
8a270ebf
DV		 543 int ret;
544
545 ret = mutex_lock_interruptible(&dev->struct_mutex);
546 if (ret)
547 return ret;
4e5359cd 548
d3fcc808 549 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 550 const char pipe = pipe_name(crtc->pipe);
551 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 552 struct intel_unpin_work *work;
553
5e2d7afc 554 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 555 work = crtc->unpin_work;
556 if (work == NULL) {
9db4a9c7 557 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 558 pipe, plane);
559 } else {
d6bbafa1
CW		 560 u32 addr;
561
e7d841ca 562 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 563 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 564 pipe, plane);
565 } else {
9db4a9c7 566 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 567 pipe, plane);
568 }
3a8a946e
DV		 569 if (work->flip_queued_req) {
570 struct intel_engine_cs *ring =
571 i915_gem_request_get_ring(work->flip_queued_req);
572
20e28fba 573 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 574 ring->name,
f06cc1b9 575 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 576 dev_priv->next_seqno,
3a8a946e 577 ring->get_seqno(ring, true),
1b5a433a 578 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 579 } else
580 seq_printf(m, "Flip not associated with any ring\n");
581 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
582 work->flip_queued_vblank,
583 work->flip_ready_vblank,
1e3feefd 584 drm_crtc_vblank_count(&crtc->base));
4e5359cd 585 if (work->enable_stall_check)
267f0c90 586 seq_puts(m, "Stall check enabled, ");
4e5359cd 587 else
267f0c90 588 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 589 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 590
d6bbafa1
CW		 591 if (INTEL_INFO(dev)->gen >= 4)
592 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
593 else
594 addr = I915_READ(DSPADDR(crtc->plane));
595 seq_printf(m, "Current scanout address 0x%08x\n", addr);
596
4e5359cd 597 if (work->pending_flip_obj) {
d6bbafa1
CW		 598 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
599 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 600 }
601 }
5e2d7afc 602 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 603 }
604
8a270ebf
DV		 605 mutex_unlock(&dev->struct_mutex);
606
4e5359cd
SF		 607 return 0;
608}
609
493018dc
BV		 610static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
611{
612 struct drm_info_node *node = m->private;
613 struct drm_device *dev = node->minor->dev;
614 struct drm_i915_private *dev_priv = dev->dev_private;
615 struct drm_i915_gem_object *obj;
616 int count = 0;
617 int ret;
618
619 ret = mutex_lock_interruptible(&dev->struct_mutex);
620 if (ret)
621 return ret;
622
623 seq_puts(m, "cache:\n");
624 list_for_each_entry(obj,
625 &dev_priv->mm.batch_pool.cache_list,
626 batch_pool_list) {
627 seq_puts(m, " ");
628 describe_obj(m, obj);
629 seq_putc(m, '\n');
630 count++;
631 }
632
633 seq_printf(m, "total: %d\n", count);
634
635 mutex_unlock(&dev->struct_mutex);
636
637 return 0;
638}
639
2017263e
BG		 640static int i915_gem_request_info(struct seq_file *m, void *data)
641{
9f25d007 642 struct drm_info_node *node = m->private;
2017263e 643 struct drm_device *dev = node->minor->dev;
e277a1f8 644 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 645 struct intel_engine_cs *ring;
2017263e 646 struct drm_i915_gem_request *gem_request;
a2c7f6fd 647 int ret, count, i;
de227ef0
CW		 648
649 ret = mutex_lock_interruptible(&dev->struct_mutex);
650 if (ret)
651 return ret;
2017263e 652
c2c347a9 653 count = 0;
a2c7f6fd
CW		 654 for_each_ring(ring, dev_priv, i) {
655 if (list_empty(&ring->request_list))
656 continue;
657
658 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 659 list_for_each_entry(gem_request,
a2c7f6fd 660 &ring->request_list,
c2c347a9 661 list) {
20e28fba 662 seq_printf(m, " %x @ %d\n",
c2c347a9
CW		 663 gem_request->seqno,
664 (int) (jiffies - gem_request->emitted_jiffies));
665 }
666 count++;
2017263e 667 }
de227ef0
CW		 668 mutex_unlock(&dev->struct_mutex);
669
c2c347a9 670 if (count == 0)
267f0c90 671 seq_puts(m, "No requests\n");
c2c347a9 672
2017263e
BG		 673 return 0;
674}
675
b2223497 676static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 677 struct intel_engine_cs *ring)
b2223497
CW		 678{
679 if (ring->get_seqno) {
20e28fba 680 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 681 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 682 }
683}
684
2017263e
BG		 685static int i915_gem_seqno_info(struct seq_file *m, void *data)
686{
9f25d007 687 struct drm_info_node *node = m->private;
2017263e 688 struct drm_device *dev = node->minor->dev;
e277a1f8 689 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 690 struct intel_engine_cs *ring;
1ec14ad3 691 int ret, i;
de227ef0
CW		 692
693 ret = mutex_lock_interruptible(&dev->struct_mutex);
694 if (ret)
695 return ret;
c8c8fb33 696 intel_runtime_pm_get(dev_priv);
2017263e 697
a2c7f6fd
CW		 698 for_each_ring(ring, dev_priv, i)
699 i915_ring_seqno_info(m, ring);
de227ef0 700
c8c8fb33 701 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 702 mutex_unlock(&dev->struct_mutex);
703
2017263e
BG		 704 return 0;
705}
706
707
708static int i915_interrupt_info(struct seq_file *m, void *data)
709{
9f25d007 710 struct drm_info_node *node = m->private;
2017263e 711 struct drm_device *dev = node->minor->dev;
e277a1f8 712 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 713 struct intel_engine_cs *ring;
9db4a9c7 714 int ret, i, pipe;
de227ef0
CW		 715
716 ret = mutex_lock_interruptible(&dev->struct_mutex);
717 if (ret)
718 return ret;
c8c8fb33 719 intel_runtime_pm_get(dev_priv);
2017263e 720
74e1ca8c 721 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 722 seq_printf(m, "Master Interrupt Control:\t%08x\n",
723 I915_READ(GEN8_MASTER_IRQ));
724
725 seq_printf(m, "Display IER:\t%08x\n",
726 I915_READ(VLV_IER));
727 seq_printf(m, "Display IIR:\t%08x\n",
728 I915_READ(VLV_IIR));
729 seq_printf(m, "Display IIR_RW:\t%08x\n",
730 I915_READ(VLV_IIR_RW));
731 seq_printf(m, "Display IMR:\t%08x\n",
732 I915_READ(VLV_IMR));
055e393f 733 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 734 seq_printf(m, "Pipe %c stat:\t%08x\n",
735 pipe_name(pipe),
736 I915_READ(PIPESTAT(pipe)));
737
738 seq_printf(m, "Port hotplug:\t%08x\n",
739 I915_READ(PORT_HOTPLUG_EN));
740 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
741 I915_READ(VLV_DPFLIPSTAT));
742 seq_printf(m, "DPINVGTT:\t%08x\n",
743 I915_READ(DPINVGTT));
744
745 for (i = 0; i < 4; i++) {
746 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
747 i, I915_READ(GEN8_GT_IMR(i)));
748 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
749 i, I915_READ(GEN8_GT_IIR(i)));
750 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
751 i, I915_READ(GEN8_GT_IER(i)));
752 }
753
754 seq_printf(m, "PCU interrupt mask:\t%08x\n",
755 I915_READ(GEN8_PCU_IMR));
756 seq_printf(m, "PCU interrupt identity:\t%08x\n",
757 I915_READ(GEN8_PCU_IIR));
758 seq_printf(m, "PCU interrupt enable:\t%08x\n",
759 I915_READ(GEN8_PCU_IER));
760 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 761 seq_printf(m, "Master Interrupt Control:\t%08x\n",
762 I915_READ(GEN8_MASTER_IRQ));
763
764 for (i = 0; i < 4; i++) {
765 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
766 i, I915_READ(GEN8_GT_IMR(i)));
767 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
768 i, I915_READ(GEN8_GT_IIR(i)));
769 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
770 i, I915_READ(GEN8_GT_IER(i)));
771 }
772
055e393f 773 for_each_pipe(dev_priv, pipe) {
f458ebbc 774 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 775 POWER_DOMAIN_PIPE(pipe))) {
776 seq_printf(m, "Pipe %c power disabled\n",
777 pipe_name(pipe));
778 continue;
779 }
a123f157 780 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 781 pipe_name(pipe),
782 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 783 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 784 pipe_name(pipe),
785 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 786 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 787 pipe_name(pipe),
788 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 789 }
790
791 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
792 I915_READ(GEN8_DE_PORT_IMR));
793 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
794 I915_READ(GEN8_DE_PORT_IIR));
795 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
796 I915_READ(GEN8_DE_PORT_IER));
797
798 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
799 I915_READ(GEN8_DE_MISC_IMR));
800 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
801 I915_READ(GEN8_DE_MISC_IIR));
802 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
803 I915_READ(GEN8_DE_MISC_IER));
804
805 seq_printf(m, "PCU interrupt mask:\t%08x\n",
806 I915_READ(GEN8_PCU_IMR));
807 seq_printf(m, "PCU interrupt identity:\t%08x\n",
808 I915_READ(GEN8_PCU_IIR));
809 seq_printf(m, "PCU interrupt enable:\t%08x\n",
810 I915_READ(GEN8_PCU_IER));
811 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 812 seq_printf(m, "Display IER:\t%08x\n",
813 I915_READ(VLV_IER));
814 seq_printf(m, "Display IIR:\t%08x\n",
815 I915_READ(VLV_IIR));
816 seq_printf(m, "Display IIR_RW:\t%08x\n",
817 I915_READ(VLV_IIR_RW));
818 seq_printf(m, "Display IMR:\t%08x\n",
819 I915_READ(VLV_IMR));
055e393f 820 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 821 seq_printf(m, "Pipe %c stat:\t%08x\n",
822 pipe_name(pipe),
823 I915_READ(PIPESTAT(pipe)));
824
825 seq_printf(m, "Master IER:\t%08x\n",
826 I915_READ(VLV_MASTER_IER));
827
828 seq_printf(m, "Render IER:\t%08x\n",
829 I915_READ(GTIER));
830 seq_printf(m, "Render IIR:\t%08x\n",
831 I915_READ(GTIIR));
832 seq_printf(m, "Render IMR:\t%08x\n",
833 I915_READ(GTIMR));
834
835 seq_printf(m, "PM IER:\t\t%08x\n",
836 I915_READ(GEN6_PMIER));
837 seq_printf(m, "PM IIR:\t\t%08x\n",
838 I915_READ(GEN6_PMIIR));
839 seq_printf(m, "PM IMR:\t\t%08x\n",
840 I915_READ(GEN6_PMIMR));
841
842 seq_printf(m, "Port hotplug:\t%08x\n",
843 I915_READ(PORT_HOTPLUG_EN));
844 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
845 I915_READ(VLV_DPFLIPSTAT));
846 seq_printf(m, "DPINVGTT:\t%08x\n",
847 I915_READ(DPINVGTT));
848
849 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 850 seq_printf(m, "Interrupt enable: %08x\n",
851 I915_READ(IER));
852 seq_printf(m, "Interrupt identity: %08x\n",
853 I915_READ(IIR));
854 seq_printf(m, "Interrupt mask: %08x\n",
855 I915_READ(IMR));
055e393f 856 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 857 seq_printf(m, "Pipe %c stat: %08x\n",
858 pipe_name(pipe),
859 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 860 } else {
861 seq_printf(m, "North Display Interrupt enable: %08x\n",
862 I915_READ(DEIER));
863 seq_printf(m, "North Display Interrupt identity: %08x\n",
864 I915_READ(DEIIR));
865 seq_printf(m, "North Display Interrupt mask: %08x\n",
866 I915_READ(DEIMR));
867 seq_printf(m, "South Display Interrupt enable: %08x\n",
868 I915_READ(SDEIER));
869 seq_printf(m, "South Display Interrupt identity: %08x\n",
870 I915_READ(SDEIIR));
871 seq_printf(m, "South Display Interrupt mask: %08x\n",
872 I915_READ(SDEIMR));
873 seq_printf(m, "Graphics Interrupt enable: %08x\n",
874 I915_READ(GTIER));
875 seq_printf(m, "Graphics Interrupt identity: %08x\n",
876 I915_READ(GTIIR));
877 seq_printf(m, "Graphics Interrupt mask: %08x\n",
878 I915_READ(GTIMR));
879 }
a2c7f6fd 880 for_each_ring(ring, dev_priv, i) {
a123f157 881 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 882 seq_printf(m,
883 "Graphics Interrupt mask (%s): %08x\n",
884 ring->name, I915_READ_IMR(ring));
9862e600 885 }
a2c7f6fd 886 i915_ring_seqno_info(m, ring);
9862e600 887 }
c8c8fb33 888 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 889 mutex_unlock(&dev->struct_mutex);
890
2017263e
BG		 891 return 0;
892}
893
a6172a80
CW		 894static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
895{
9f25d007 896 struct drm_info_node *node = m->private;
a6172a80 897 struct drm_device *dev = node->minor->dev;
e277a1f8 898 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 899 int i, ret;
900
901 ret = mutex_lock_interruptible(&dev->struct_mutex);
902 if (ret)
903 return ret;
a6172a80
CW		 904
905 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
906 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
907 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 908 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 909
6c085a72
CW		 910 seq_printf(m, "Fence %d, pin count = %d, object = ",
911 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 912 if (obj == NULL)
267f0c90 913 seq_puts(m, "unused");
c2c347a9 914 else
05394f39 915 describe_obj(m, obj);
267f0c90 916 seq_putc(m, '\n');
a6172a80
CW		 917 }
918
05394f39 919 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 920 return 0;
921}
922
2017263e
BG		 923static int i915_hws_info(struct seq_file *m, void *data)
924{
9f25d007 925 struct drm_info_node *node = m->private;
2017263e 926 struct drm_device *dev = node->minor->dev;
e277a1f8 927 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 928 struct intel_engine_cs *ring;
1a240d4d 929 const u32 *hws;
4066c0ae
CW		 930 int i;
931
1ec14ad3 932 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 933 hws = ring->status_page.page_addr;
2017263e
BG		 934 if (hws == NULL)
935 return 0;
936
937 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
938 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
939 i * 4,
940 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
941 }
942 return 0;
943}
944
d5442303
DV		 945static ssize_t
946i915_error_state_write(struct file *filp,
947 const char __user *ubuf,
948 size_t cnt,
949 loff_t *ppos)
950{
edc3d884 951 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 952 struct drm_device *dev = error_priv->dev;
22bcfc6a 953 int ret;
d5442303
DV		 954
955 DRM_DEBUG_DRIVER("Resetting error state\n");
956
22bcfc6a
DV		 957 ret = mutex_lock_interruptible(&dev->struct_mutex);
958 if (ret)
959 return ret;
960
d5442303
DV		 961 i915_destroy_error_state(dev);
962 mutex_unlock(&dev->struct_mutex);
963
964 return cnt;
965}
966
967static int i915_error_state_open(struct inode *inode, struct file *file)
968{
969 struct drm_device *dev = inode->i_private;
d5442303 970 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 971
972 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
973 if (!error_priv)
974 return -ENOMEM;
975
976 error_priv->dev = dev;
977
95d5bfb3 978 i915_error_state_get(dev, error_priv);
d5442303 979
edc3d884
MK		 980 file->private_data = error_priv;
981
982 return 0;
d5442303
DV		 983}
984
985static int i915_error_state_release(struct inode *inode, struct file *file)
986{
edc3d884 987 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 988
95d5bfb3 989 i915_error_state_put(error_priv);
d5442303
DV		 990 kfree(error_priv);
991
edc3d884
MK		 992 return 0;
993}
994
4dc955f7
MK		 995static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
996 size_t count, loff_t *pos)
997{
998 struct i915_error_state_file_priv *error_priv = file->private_data;
999 struct drm_i915_error_state_buf error_str;
1000 loff_t tmp_pos = 0;
1001 ssize_t ret_count = 0;
1002 int ret;
1003
0a4cd7c8 1004 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1005 if (ret)
1006 return ret;
edc3d884 1007
fc16b48b 1008 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1009 if (ret)
1010 goto out;
1011
edc3d884
MK		 1012 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1013 error_str.buf,
1014 error_str.bytes);
1015
1016 if (ret_count < 0)
1017 ret = ret_count;
1018 else
1019 *pos = error_str.start + ret_count;
1020out:
4dc955f7 1021 i915_error_state_buf_release(&error_str);
edc3d884 1022 return ret ?: ret_count;
d5442303
DV		 1023}
1024
1025static const struct file_operations i915_error_state_fops = {
1026 .owner = THIS_MODULE,
1027 .open = i915_error_state_open,
edc3d884 1028 .read = i915_error_state_read,
d5442303
DV		 1029 .write = i915_error_state_write,
1030 .llseek = default_llseek,
1031 .release = i915_error_state_release,
1032};
1033
647416f9
KC		 1034static int
1035i915_next_seqno_get(void *data, u64 *val)
40633219 1036{
647416f9 1037 struct drm_device *dev = data;
e277a1f8 1038 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1039 int ret;
1040
1041 ret = mutex_lock_interruptible(&dev->struct_mutex);
1042 if (ret)
1043 return ret;
1044
647416f9 1045 *val = dev_priv->next_seqno;
40633219
MK		 1046 mutex_unlock(&dev->struct_mutex);
1047
647416f9 1048 return 0;
40633219
MK		 1049}
1050
647416f9
KC		 1051static int
1052i915_next_seqno_set(void *data, u64 val)
1053{
1054 struct drm_device *dev = data;
40633219
MK		 1055 int ret;
1056
40633219
MK		 1057 ret = mutex_lock_interruptible(&dev->struct_mutex);
1058 if (ret)
1059 return ret;
1060
e94fbaa8 1061 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1062 mutex_unlock(&dev->struct_mutex);
1063
647416f9 1064 return ret;
40633219
MK		 1065}
1066
647416f9
KC		 1067DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1068 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1069 "0x%llx\n");
40633219 1070
adb4bd12 1071static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1072{
9f25d007 1073 struct drm_info_node *node = m->private;
f97108d1 1074 struct drm_device *dev = node->minor->dev;
e277a1f8 1075 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1076 int ret = 0;
1077
1078 intel_runtime_pm_get(dev_priv);
3b8d8d91 1079
5c9669ce
TR		 1080 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1081
3b8d8d91
JB		 1082 if (IS_GEN5(dev)) {
1083 u16 rgvswctl = I915_READ16(MEMSWCTL);
1084 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1085
1086 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1087 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1088 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1089 MEMSTAT_VID_SHIFT);
1090 seq_printf(m, "Current P-state: %d\n",
1091 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1092 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1093 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1094 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1095 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1096 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1097 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1098 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1099 u32 rpupei, rpcurup, rpprevup;
1100 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1101 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1102 int max_freq;
1103
1104 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1105 ret = mutex_lock_interruptible(&dev->struct_mutex);
1106 if (ret)
c8c8fb33 1107 goto out;
d1ebd816 1108
59bad947 1109 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1110
8e8c06cd
CW		 1111 reqf = I915_READ(GEN6_RPNSWREQ);
1112 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1113 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1114 reqf >>= 24;
1115 else
1116 reqf >>= 25;
7c59a9c1 1117 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1118
0d8f9491
CW		 1119 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1120 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1121 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1122
ccab5c82
JB		 1123 rpstat = I915_READ(GEN6_RPSTAT1);
1124 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1125 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1126 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1127 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1128 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1129 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1130 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1131 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1132 else
1133 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1134 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1135
59bad947 1136 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1137 mutex_unlock(&dev->struct_mutex);
1138
9dd3c605
PZ		 1139 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1140 pm_ier = I915_READ(GEN6_PMIER);
1141 pm_imr = I915_READ(GEN6_PMIMR);
1142 pm_isr = I915_READ(GEN6_PMISR);
1143 pm_iir = I915_READ(GEN6_PMIIR);
1144 pm_mask = I915_READ(GEN6_PMINTRMSK);
1145 } else {
1146 pm_ier = I915_READ(GEN8_GT_IER(2));
1147 pm_imr = I915_READ(GEN8_GT_IMR(2));
1148 pm_isr = I915_READ(GEN8_GT_ISR(2));
1149 pm_iir = I915_READ(GEN8_GT_IIR(2));
1150 pm_mask = I915_READ(GEN6_PMINTRMSK);
1151 }
0d8f9491 1152 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1153 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1154 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1155 seq_printf(m, "Render p-state ratio: %d\n",
1156 (gt_perf_status & 0xff00) >> 8);
1157 seq_printf(m, "Render p-state VID: %d\n",
1158 gt_perf_status & 0xff);
1159 seq_printf(m, "Render p-state limit: %d\n",
1160 rp_state_limits & 0xff);
0d8f9491
CW		 1161 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1162 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1163 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1164 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1165 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1166 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1167 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1168 GEN6_CURICONT_MASK);
1169 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1170 GEN6_CURBSYTAVG_MASK);
1171 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1172 GEN6_CURBSYTAVG_MASK);
1173 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1174 GEN6_CURIAVG_MASK);
1175 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1176 GEN6_CURBSYTAVG_MASK);
1177 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1178 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1179
1180 max_freq = (rp_state_cap & 0xff0000) >> 16;
1181 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1182 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1183
1184 max_freq = (rp_state_cap & 0xff00) >> 8;
1185 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1186 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1187
1188 max_freq = rp_state_cap & 0xff;
1189 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1190 intel_gpu_freq(dev_priv, max_freq));
31c77388
BW		 1191
1192 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1193 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1194 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1195 u32 freq_sts;
0a073b84 1196
259bd5d4 1197 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1198 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1199 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1200 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1201
0a073b84 1202 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1203 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1204
0a073b84 1205 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1206 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1207
7c59a9c1
VS		 1208 seq_printf(m,
1209 "efficient (RPe) frequency: %d MHz\n",
1210 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1211
1212 seq_printf(m, "current GPU freq: %d MHz\n",
7c59a9c1 1213 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1214 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1215 } else {
267f0c90 1216 seq_puts(m, "no P-state info available\n");
3b8d8d91 1217 }
f97108d1 1218
c8c8fb33
PZ		 1219out:
1220 intel_runtime_pm_put(dev_priv);
1221 return ret;
f97108d1
JB		 1222}
1223
f654449a
CW		 1224static int i915_hangcheck_info(struct seq_file *m, void *unused)
1225{
1226 struct drm_info_node *node = m->private;
ebbc7546
MK		 1227 struct drm_device *dev = node->minor->dev;
1228 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1229 struct intel_engine_cs *ring;
ebbc7546
MK		 1230 u64 acthd[I915_NUM_RINGS];
1231 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1232 int i;
1233
1234 if (!i915.enable_hangcheck) {
1235 seq_printf(m, "Hangcheck disabled\n");
1236 return 0;
1237 }
1238
ebbc7546
MK		 1239 intel_runtime_pm_get(dev_priv);
1240
1241 for_each_ring(ring, dev_priv, i) {
1242 seqno[i] = ring->get_seqno(ring, false);
1243 acthd[i] = intel_ring_get_active_head(ring);
1244 }
1245
1246 intel_runtime_pm_put(dev_priv);
1247
f654449a
CW		 1248 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1249 seq_printf(m, "Hangcheck active, fires in %dms\n",
1250 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1251 jiffies));
1252 } else
1253 seq_printf(m, "Hangcheck inactive\n");
1254
1255 for_each_ring(ring, dev_priv, i) {
1256 seq_printf(m, "%s:\n", ring->name);
1257 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1258 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1259 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1260 (long long)ring->hangcheck.acthd,
ebbc7546 1261 (long long)acthd[i]);
f654449a
CW		 1262 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1263 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1264 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1265 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1266 }
1267
1268 return 0;
1269}
1270
4d85529d 1271static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1272{
9f25d007 1273 struct drm_info_node *node = m->private;
f97108d1 1274 struct drm_device *dev = node->minor->dev;
e277a1f8 1275 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1276 u32 rgvmodectl, rstdbyctl;
1277 u16 crstandvid;
1278 int ret;
1279
1280 ret = mutex_lock_interruptible(&dev->struct_mutex);
1281 if (ret)
1282 return ret;
c8c8fb33 1283 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1284
1285 rgvmodectl = I915_READ(MEMMODECTL);
1286 rstdbyctl = I915_READ(RSTDBYCTL);
1287 crstandvid = I915_READ16(CRSTANDVID);
1288
c8c8fb33 1289 intel_runtime_pm_put(dev_priv);
616fdb5a 1290 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1291
1292 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1293 "yes" : "no");
1294 seq_printf(m, "Boost freq: %d\n",
1295 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1296 MEMMODE_BOOST_FREQ_SHIFT);
1297 seq_printf(m, "HW control enabled: %s\n",
1298 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1299 seq_printf(m, "SW control enabled: %s\n",
1300 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1301 seq_printf(m, "Gated voltage change: %s\n",
1302 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1303 seq_printf(m, "Starting frequency: P%d\n",
1304 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1305 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1306 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1307 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1308 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1309 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1310 seq_printf(m, "Render standby enabled: %s\n",
1311 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1312 seq_puts(m, "Current RS state: ");
88271da3
JB		 1313 switch (rstdbyctl & RSX_STATUS_MASK) {
1314 case RSX_STATUS_ON:
267f0c90 1315 seq_puts(m, "on\n");
88271da3
JB		 1316 break;
1317 case RSX_STATUS_RC1:
267f0c90 1318 seq_puts(m, "RC1\n");
88271da3
JB		 1319 break;
1320 case RSX_STATUS_RC1E:
267f0c90 1321 seq_puts(m, "RC1E\n");
88271da3
JB		 1322 break;
1323 case RSX_STATUS_RS1:
267f0c90 1324 seq_puts(m, "RS1\n");
88271da3
JB		 1325 break;
1326 case RSX_STATUS_RS2:
267f0c90 1327 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1328 break;
1329 case RSX_STATUS_RS3:
267f0c90 1330 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1331 break;
1332 default:
267f0c90 1333 seq_puts(m, "unknown\n");
88271da3
JB		 1334 break;
1335 }
f97108d1
JB		 1336
1337 return 0;
1338}
1339
f65367b5 1340static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1341{
b2cff0db
CW		 1342 struct drm_info_node *node = m->private;
1343 struct drm_device *dev = node->minor->dev;
1344 struct drm_i915_private *dev_priv = dev->dev_private;
1345 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1346 int i;
1347
1348 spin_lock_irq(&dev_priv->uncore.lock);
1349 for_each_fw_domain(fw_domain, dev_priv, i) {
1350 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1351 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1352 fw_domain->wake_count);
1353 }
1354 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1355
b2cff0db
CW		 1356 return 0;
1357}
1358
1359static int vlv_drpc_info(struct seq_file *m)
1360{
9f25d007 1361 struct drm_info_node *node = m->private;
669ab5aa
D		 1362 struct drm_device *dev = node->minor->dev;
1363 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1364 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1365
d46c0517
ID		 1366 intel_runtime_pm_get(dev_priv);
1367
6b312cd3 1368 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1369 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1370 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1371
d46c0517
ID		 1372 intel_runtime_pm_put(dev_priv);
1373
669ab5aa
D		 1374 seq_printf(m, "Video Turbo Mode: %s\n",
1375 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1376 seq_printf(m, "Turbo enabled: %s\n",
1377 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1378 seq_printf(m, "HW control enabled: %s\n",
1379 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1380 seq_printf(m, "SW control enabled: %s\n",
1381 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1382 GEN6_RP_MEDIA_SW_MODE));
1383 seq_printf(m, "RC6 Enabled: %s\n",
1384 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1385 GEN6_RC_CTL_EI_MODE(1))));
1386 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1387 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1388 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1389 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1390
9cc19be5
ID		 1391 seq_printf(m, "Render RC6 residency since boot: %u\n",
1392 I915_READ(VLV_GT_RENDER_RC6));
1393 seq_printf(m, "Media RC6 residency since boot: %u\n",
1394 I915_READ(VLV_GT_MEDIA_RC6));
1395
f65367b5 1396 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1397}
1398
4d85529d
BW		 1399static int gen6_drpc_info(struct seq_file *m)
1400{
9f25d007 1401 struct drm_info_node *node = m->private;
4d85529d
BW		 1402 struct drm_device *dev = node->minor->dev;
1403 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1404 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1405 unsigned forcewake_count;
aee56cff 1406 int count = 0, ret;
4d85529d
BW		 1407
1408 ret = mutex_lock_interruptible(&dev->struct_mutex);
1409 if (ret)
1410 return ret;
c8c8fb33 1411 intel_runtime_pm_get(dev_priv);
4d85529d 1412
907b28c5 1413 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1414 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1415 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1416
1417 if (forcewake_count) {
267f0c90
DL		 1418 seq_puts(m, "RC information inaccurate because somebody "
1419 "holds a forcewake reference \n");
4d85529d
BW		 1420 } else {
1421 /* NB: we cannot use forcewake, else we read the wrong values */
1422 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1423 udelay(10);
1424 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1425 }
1426
1427 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1428 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1429
1430 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1431 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1432 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1433 mutex_lock(&dev_priv->rps.hw_lock);
1434 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1435 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1436
c8c8fb33
PZ		 1437 intel_runtime_pm_put(dev_priv);
1438
4d85529d
BW		 1439 seq_printf(m, "Video Turbo Mode: %s\n",
1440 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1441 seq_printf(m, "HW control enabled: %s\n",
1442 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1443 seq_printf(m, "SW control enabled: %s\n",
1444 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1445 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1446 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1447 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1448 seq_printf(m, "RC6 Enabled: %s\n",
1449 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1450 seq_printf(m, "Deep RC6 Enabled: %s\n",
1451 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1452 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1453 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1454 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1455 switch (gt_core_status & GEN6_RCn_MASK) {
1456 case GEN6_RC0:
1457 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1458 seq_puts(m, "Core Power Down\n");
4d85529d 1459 else
267f0c90 1460 seq_puts(m, "on\n");
4d85529d
BW		 1461 break;
1462 case GEN6_RC3:
267f0c90 1463 seq_puts(m, "RC3\n");
4d85529d
BW		 1464 break;
1465 case GEN6_RC6:
267f0c90 1466 seq_puts(m, "RC6\n");
4d85529d
BW		 1467 break;
1468 case GEN6_RC7:
267f0c90 1469 seq_puts(m, "RC7\n");
4d85529d
BW		 1470 break;
1471 default:
267f0c90 1472 seq_puts(m, "Unknown\n");
4d85529d
BW		 1473 break;
1474 }
1475
1476 seq_printf(m, "Core Power Down: %s\n",
1477 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1478
1479 /* Not exactly sure what this is */
1480 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1481 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1482 seq_printf(m, "RC6 residency since boot: %u\n",
1483 I915_READ(GEN6_GT_GFX_RC6));
1484 seq_printf(m, "RC6+ residency since boot: %u\n",
1485 I915_READ(GEN6_GT_GFX_RC6p));
1486 seq_printf(m, "RC6++ residency since boot: %u\n",
1487 I915_READ(GEN6_GT_GFX_RC6pp));
1488
ecd8faea
BW		 1489 seq_printf(m, "RC6 voltage: %dmV\n",
1490 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1491 seq_printf(m, "RC6+ voltage: %dmV\n",
1492 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1493 seq_printf(m, "RC6++ voltage: %dmV\n",
1494 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1495 return 0;
1496}
1497
1498static int i915_drpc_info(struct seq_file *m, void *unused)
1499{
9f25d007 1500 struct drm_info_node *node = m->private;
4d85529d
BW		 1501 struct drm_device *dev = node->minor->dev;
1502
669ab5aa
D		 1503 if (IS_VALLEYVIEW(dev))
1504 return vlv_drpc_info(m);
ac66cf4b 1505 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1506 return gen6_drpc_info(m);
1507 else
1508 return ironlake_drpc_info(m);
1509}
1510
b5e50c3f
JB		 1511static int i915_fbc_status(struct seq_file *m, void *unused)
1512{
9f25d007 1513 struct drm_info_node *node = m->private;
b5e50c3f 1514 struct drm_device *dev = node->minor->dev;
e277a1f8 1515 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1516
3a77c4c4 1517 if (!HAS_FBC(dev)) {
267f0c90 1518 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1519 return 0;
1520 }
1521
36623ef8
PZ		 1522 intel_runtime_pm_get(dev_priv);
1523
ee5382ae 1524 if (intel_fbc_enabled(dev)) {
267f0c90 1525 seq_puts(m, "FBC enabled\n");
b5e50c3f 1526 } else {
267f0c90 1527 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1528 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1529 case FBC_OK:
1530 seq_puts(m, "FBC actived, but currently disabled in hardware");
1531 break;
1532 case FBC_UNSUPPORTED:
1533 seq_puts(m, "unsupported by this chipset");
1534 break;
bed4a673 1535 case FBC_NO_OUTPUT:
267f0c90 1536 seq_puts(m, "no outputs");
bed4a673 1537 break;
b5e50c3f 1538 case FBC_STOLEN_TOO_SMALL:
267f0c90 1539 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1540 break;
1541 case FBC_UNSUPPORTED_MODE:
267f0c90 1542 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1543 break;
1544 case FBC_MODE_TOO_LARGE:
267f0c90 1545 seq_puts(m, "mode too large");
b5e50c3f
JB		 1546 break;
1547 case FBC_BAD_PLANE:
267f0c90 1548 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1549 break;
1550 case FBC_NOT_TILED:
267f0c90 1551 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1552 break;
9c928d16 1553 case FBC_MULTIPLE_PIPES:
267f0c90 1554 seq_puts(m, "multiple pipes are enabled");
9c928d16 1555 break;
c1a9f047 1556 case FBC_MODULE_PARAM:
267f0c90 1557 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1558 break;
8a5729a3 1559 case FBC_CHIP_DEFAULT:
267f0c90 1560 seq_puts(m, "disabled per chip default");
8a5729a3 1561 break;
b5e50c3f 1562 default:
267f0c90 1563 seq_puts(m, "unknown reason");
b5e50c3f 1564 }
267f0c90 1565 seq_putc(m, '\n');
b5e50c3f 1566 }
36623ef8
PZ		 1567
1568 intel_runtime_pm_put(dev_priv);
1569
b5e50c3f
JB		 1570 return 0;
1571}
1572
da46f936
RV		 1573static int i915_fbc_fc_get(void *data, u64 *val)
1574{
1575 struct drm_device *dev = data;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577
1578 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1579 return -ENODEV;
1580
1581 drm_modeset_lock_all(dev);
1582 *val = dev_priv->fbc.false_color;
1583 drm_modeset_unlock_all(dev);
1584
1585 return 0;
1586}
1587
1588static int i915_fbc_fc_set(void *data, u64 val)
1589{
1590 struct drm_device *dev = data;
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592 u32 reg;
1593
1594 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1595 return -ENODEV;
1596
1597 drm_modeset_lock_all(dev);
1598
1599 reg = I915_READ(ILK_DPFC_CONTROL);
1600 dev_priv->fbc.false_color = val;
1601
1602 I915_WRITE(ILK_DPFC_CONTROL, val ?
1603 (reg | FBC_CTL_FALSE_COLOR) :
1604 (reg & ~FBC_CTL_FALSE_COLOR));
1605
1606 drm_modeset_unlock_all(dev);
1607 return 0;
1608}
1609
1610DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1611 i915_fbc_fc_get, i915_fbc_fc_set,
1612 "%llu\n");
1613
92d44621
PZ		 1614static int i915_ips_status(struct seq_file *m, void *unused)
1615{
9f25d007 1616 struct drm_info_node *node = m->private;
92d44621
PZ		 1617 struct drm_device *dev = node->minor->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619
f5adf94e 1620 if (!HAS_IPS(dev)) {
92d44621
PZ		 1621 seq_puts(m, "not supported\n");
1622 return 0;
1623 }
1624
36623ef8
PZ		 1625 intel_runtime_pm_get(dev_priv);
1626
0eaa53f0
RV		 1627 seq_printf(m, "Enabled by kernel parameter: %s\n",
1628 yesno(i915.enable_ips));
1629
1630 if (INTEL_INFO(dev)->gen >= 8) {
1631 seq_puts(m, "Currently: unknown\n");
1632 } else {
1633 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1634 seq_puts(m, "Currently: enabled\n");
1635 else
1636 seq_puts(m, "Currently: disabled\n");
1637 }
92d44621 1638
36623ef8
PZ		 1639 intel_runtime_pm_put(dev_priv);
1640
92d44621
PZ		 1641 return 0;
1642}
1643
4a9bef37
JB		 1644static int i915_sr_status(struct seq_file *m, void *unused)
1645{
9f25d007 1646 struct drm_info_node *node = m->private;
4a9bef37 1647 struct drm_device *dev = node->minor->dev;
e277a1f8 1648 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1649 bool sr_enabled = false;
1650
36623ef8
PZ		 1651 intel_runtime_pm_get(dev_priv);
1652
1398261a 1653 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1654 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1655 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1656 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1657 else if (IS_I915GM(dev))
1658 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1659 else if (IS_PINEVIEW(dev))
1660 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1661
36623ef8
PZ		 1662 intel_runtime_pm_put(dev_priv);
1663
5ba2aaaa
CW		 1664 seq_printf(m, "self-refresh: %s\n",
1665 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1666
1667 return 0;
1668}
1669
7648fa99
JB		 1670static int i915_emon_status(struct seq_file *m, void *unused)
1671{
9f25d007 1672 struct drm_info_node *node = m->private;
7648fa99 1673 struct drm_device *dev = node->minor->dev;
e277a1f8 1674 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1675 unsigned long temp, chipset, gfx;
de227ef0
CW		 1676 int ret;
1677
582be6b4
CW		 1678 if (!IS_GEN5(dev))
1679 return -ENODEV;
1680
de227ef0
CW		 1681 ret = mutex_lock_interruptible(&dev->struct_mutex);
1682 if (ret)
1683 return ret;
7648fa99
JB		 1684
1685 temp = i915_mch_val(dev_priv);
1686 chipset = i915_chipset_val(dev_priv);
1687 gfx = i915_gfx_val(dev_priv);
de227ef0 1688 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1689
1690 seq_printf(m, "GMCH temp: %ld\n", temp);
1691 seq_printf(m, "Chipset power: %ld\n", chipset);
1692 seq_printf(m, "GFX power: %ld\n", gfx);
1693 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1694
1695 return 0;
1696}
1697
23b2f8bb
JB		 1698static int i915_ring_freq_table(struct seq_file *m, void *unused)
1699{
9f25d007 1700 struct drm_info_node *node = m->private;
23b2f8bb 1701 struct drm_device *dev = node->minor->dev;
e277a1f8 1702 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1703 int ret = 0;
23b2f8bb
JB		 1704 int gpu_freq, ia_freq;
1705
1c70c0ce 1706 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1707 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1708 return 0;
1709 }
1710
5bfa0199
PZ		 1711 intel_runtime_pm_get(dev_priv);
1712
5c9669ce
TR		 1713 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1714
4fc688ce 1715 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1716 if (ret)
5bfa0199 1717 goto out;
23b2f8bb 1718
267f0c90 1719 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1720
b39fb297
BW		 1721 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1722 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1723 gpu_freq++) {
42c0526c
BW		 1724 ia_freq = gpu_freq;
1725 sandybridge_pcode_read(dev_priv,
1726 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1727 &ia_freq);
3ebecd07 1728 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1729 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1730 ((ia_freq >> 0) & 0xff) * 100,
1731 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1732 }
1733
4fc688ce 1734 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1735
5bfa0199
PZ		 1736out:
1737 intel_runtime_pm_put(dev_priv);
1738 return ret;
23b2f8bb
JB		 1739}
1740
44834a67
CW		 1741static int i915_opregion(struct seq_file *m, void *unused)
1742{
9f25d007 1743 struct drm_info_node *node = m->private;
44834a67 1744 struct drm_device *dev = node->minor->dev;
e277a1f8 1745 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1746 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1747 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1748 int ret;
1749
0d38f009
DV		 1750 if (data == NULL)
1751 return -ENOMEM;
1752
44834a67
CW		 1753 ret = mutex_lock_interruptible(&dev->struct_mutex);
1754 if (ret)
0d38f009 1755 goto out;
44834a67 1756
0d38f009
DV		 1757 if (opregion->header) {
1758 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1759 seq_write(m, data, OPREGION_SIZE);
1760 }
44834a67
CW		 1761
1762 mutex_unlock(&dev->struct_mutex);
1763
0d38f009
DV		 1764out:
1765 kfree(data);
44834a67
CW		 1766 return 0;
1767}
1768
37811fcc
CW		 1769static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1770{
9f25d007 1771 struct drm_info_node *node = m->private;
37811fcc 1772 struct drm_device *dev = node->minor->dev;
4520f53a 1773 struct intel_fbdev *ifbdev = NULL;
37811fcc 1774 struct intel_framebuffer *fb;
37811fcc 1775
4520f53a
DV		 1776#ifdef CONFIG_DRM_I915_FBDEV
1777 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1778
1779 ifbdev = dev_priv->fbdev;
1780 fb = to_intel_framebuffer(ifbdev->helper.fb);
1781
c1ca506d 1782 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1783 fb->base.width,
1784 fb->base.height,
1785 fb->base.depth,
623f9783 1786 fb->base.bits_per_pixel,
c1ca506d 1787 fb->base.modifier[0],
623f9783 1788 atomic_read(&fb->base.refcount.refcount));
05394f39 1789 describe_obj(m, fb->obj);
267f0c90 1790 seq_putc(m, '\n');
4520f53a 1791#endif
37811fcc 1792
4b096ac1 1793 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1794 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1795 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1796 continue;
1797
c1ca506d 1798 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1799 fb->base.width,
1800 fb->base.height,
1801 fb->base.depth,
623f9783 1802 fb->base.bits_per_pixel,
c1ca506d 1803 fb->base.modifier[0],
623f9783 1804 atomic_read(&fb->base.refcount.refcount));
05394f39 1805 describe_obj(m, fb->obj);
267f0c90 1806 seq_putc(m, '\n');
37811fcc 1807 }
4b096ac1 1808 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1809
1810 return 0;
1811}
1812
c9fe99bd
OM		 1813static void describe_ctx_ringbuf(struct seq_file *m,
1814 struct intel_ringbuffer *ringbuf)
1815{
1816 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1817 ringbuf->space, ringbuf->head, ringbuf->tail,
1818 ringbuf->last_retired_head);
1819}
1820
e76d3630
BW		 1821static int i915_context_status(struct seq_file *m, void *unused)
1822{
9f25d007 1823 struct drm_info_node *node = m->private;
e76d3630 1824 struct drm_device *dev = node->minor->dev;
e277a1f8 1825 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1826 struct intel_engine_cs *ring;
273497e5 1827 struct intel_context *ctx;
a168c293 1828 int ret, i;
e76d3630 1829
f3d28878 1830 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1831 if (ret)
1832 return ret;
1833
a33afea5 1834 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1835 if (!i915.enable_execlists &&
1836 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1837 continue;
1838
a33afea5 1839 seq_puts(m, "HW context ");
3ccfd19d 1840 describe_ctx(m, ctx);
c9fe99bd 1841 for_each_ring(ring, dev_priv, i) {
a33afea5 1842 if (ring->default_context == ctx)
c9fe99bd
OM		 1843 seq_printf(m, "(default context %s) ",
1844 ring->name);
1845 }
1846
1847 if (i915.enable_execlists) {
1848 seq_putc(m, '\n');
1849 for_each_ring(ring, dev_priv, i) {
1850 struct drm_i915_gem_object *ctx_obj =
1851 ctx->engine[i].state;
1852 struct intel_ringbuffer *ringbuf =
1853 ctx->engine[i].ringbuf;
1854
1855 seq_printf(m, "%s: ", ring->name);
1856 if (ctx_obj)
1857 describe_obj(m, ctx_obj);
1858 if (ringbuf)
1859 describe_ctx_ringbuf(m, ringbuf);
1860 seq_putc(m, '\n');
1861 }
1862 } else {
1863 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1864 }
a33afea5 1865
a33afea5 1866 seq_putc(m, '\n');
a168c293
BW		 1867 }
1868
f3d28878 1869 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1870
1871 return 0;
1872}
1873
064ca1d2
TD		 1874static void i915_dump_lrc_obj(struct seq_file *m,
1875 struct intel_engine_cs *ring,
1876 struct drm_i915_gem_object *ctx_obj)
1877{
1878 struct page *page;
1879 uint32_t *reg_state;
1880 int j;
1881 unsigned long ggtt_offset = 0;
1882
1883 if (ctx_obj == NULL) {
1884 seq_printf(m, "Context on %s with no gem object\n",
1885 ring->name);
1886 return;
1887 }
1888
1889 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1890 intel_execlists_ctx_id(ctx_obj));
1891
1892 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1893 seq_puts(m, "\tNot bound in GGTT\n");
1894 else
1895 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1896
1897 if (i915_gem_object_get_pages(ctx_obj)) {
1898 seq_puts(m, "\tFailed to get pages for context object\n");
1899 return;
1900 }
1901
1902 page = i915_gem_object_get_page(ctx_obj, 1);
1903 if (!WARN_ON(page == NULL)) {
1904 reg_state = kmap_atomic(page);
1905
1906 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1907 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1908 ggtt_offset + 4096 + (j * 4),
1909 reg_state[j], reg_state[j + 1],
1910 reg_state[j + 2], reg_state[j + 3]);
1911 }
1912 kunmap_atomic(reg_state);
1913 }
1914
1915 seq_putc(m, '\n');
1916}
1917
c0ab1ae9
BW		 1918static int i915_dump_lrc(struct seq_file *m, void *unused)
1919{
1920 struct drm_info_node *node = (struct drm_info_node *) m->private;
1921 struct drm_device *dev = node->minor->dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct intel_engine_cs *ring;
1924 struct intel_context *ctx;
1925 int ret, i;
1926
1927 if (!i915.enable_execlists) {
1928 seq_printf(m, "Logical Ring Contexts are disabled\n");
1929 return 0;
1930 }
1931
1932 ret = mutex_lock_interruptible(&dev->struct_mutex);
1933 if (ret)
1934 return ret;
1935
1936 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1937 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1938 if (ring->default_context != ctx)
1939 i915_dump_lrc_obj(m, ring,
1940 ctx->engine[i].state);
c0ab1ae9
BW		 1941 }
1942 }
1943
1944 mutex_unlock(&dev->struct_mutex);
1945
1946 return 0;
1947}
1948
4ba70e44
OM		 1949static int i915_execlists(struct seq_file *m, void *data)
1950{
1951 struct drm_info_node *node = (struct drm_info_node *)m->private;
1952 struct drm_device *dev = node->minor->dev;
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1954 struct intel_engine_cs *ring;
1955 u32 status_pointer;
1956 u8 read_pointer;
1957 u8 write_pointer;
1958 u32 status;
1959 u32 ctx_id;
1960 struct list_head *cursor;
1961 int ring_id, i;
1962 int ret;
1963
1964 if (!i915.enable_execlists) {
1965 seq_puts(m, "Logical Ring Contexts are disabled\n");
1966 return 0;
1967 }
1968
1969 ret = mutex_lock_interruptible(&dev->struct_mutex);
1970 if (ret)
1971 return ret;
1972
fc0412ec
MT		 1973 intel_runtime_pm_get(dev_priv);
1974
4ba70e44 1975 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 1976 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 1977 int count = 0;
1978 unsigned long flags;
1979
1980 seq_printf(m, "%s\n", ring->name);
1981
1982 status = I915_READ(RING_EXECLIST_STATUS(ring));
1983 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1984 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1985 status, ctx_id);
1986
1987 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1988 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1989
1990 read_pointer = ring->next_context_status_buffer;
1991 write_pointer = status_pointer & 0x07;
1992 if (read_pointer > write_pointer)
1993 write_pointer += 6;
1994 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1995 read_pointer, write_pointer);
1996
1997 for (i = 0; i < 6; i++) {
1998 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1999 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2000
2001 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2002 i, status, ctx_id);
2003 }
2004
2005 spin_lock_irqsave(&ring->execlist_lock, flags);
2006 list_for_each(cursor, &ring->execlist_queue)
2007 count++;
2008 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2009 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2010 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2011
2012 seq_printf(m, "\t%d requests in queue\n", count);
2013 if (head_req) {
2014 struct drm_i915_gem_object *ctx_obj;
2015
6d3d8274 2016 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2017 seq_printf(m, "\tHead request id: %u\n",
2018 intel_execlists_ctx_id(ctx_obj));
2019 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2020 head_req->tail);
4ba70e44
OM		 2021 }
2022
2023 seq_putc(m, '\n');
2024 }
2025
fc0412ec 2026 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2027 mutex_unlock(&dev->struct_mutex);
2028
2029 return 0;
2030}
2031
ea16a3cd
DV		 2032static const char *swizzle_string(unsigned swizzle)
2033{
aee56cff 2034 switch (swizzle) {
ea16a3cd
DV		 2035 case I915_BIT_6_SWIZZLE_NONE:
2036 return "none";
2037 case I915_BIT_6_SWIZZLE_9:
2038 return "bit9";
2039 case I915_BIT_6_SWIZZLE_9_10:
2040 return "bit9/bit10";
2041 case I915_BIT_6_SWIZZLE_9_11:
2042 return "bit9/bit11";
2043 case I915_BIT_6_SWIZZLE_9_10_11:
2044 return "bit9/bit10/bit11";
2045 case I915_BIT_6_SWIZZLE_9_17:
2046 return "bit9/bit17";
2047 case I915_BIT_6_SWIZZLE_9_10_17:
2048 return "bit9/bit10/bit17";
2049 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2050 return "unknown";
ea16a3cd
DV		 2051 }
2052
2053 return "bug";
2054}
2055
2056static int i915_swizzle_info(struct seq_file *m, void *data)
2057{
9f25d007 2058 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2059 struct drm_device *dev = node->minor->dev;
2060 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2061 int ret;
2062
2063 ret = mutex_lock_interruptible(&dev->struct_mutex);
2064 if (ret)
2065 return ret;
c8c8fb33 2066 intel_runtime_pm_get(dev_priv);
ea16a3cd 2067
ea16a3cd
DV		 2068 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2069 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2070 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2071 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2072
2073 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2074 seq_printf(m, "DDC = 0x%08x\n",
2075 I915_READ(DCC));
656bfa3a
DV		 2076 seq_printf(m, "DDC2 = 0x%08x\n",
2077 I915_READ(DCC2));
ea16a3cd
DV		 2078 seq_printf(m, "C0DRB3 = 0x%04x\n",
2079 I915_READ16(C0DRB3));
2080 seq_printf(m, "C1DRB3 = 0x%04x\n",
2081 I915_READ16(C1DRB3));
9d3203e1 2082 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2083 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2084 I915_READ(MAD_DIMM_C0));
2085 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2086 I915_READ(MAD_DIMM_C1));
2087 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2088 I915_READ(MAD_DIMM_C2));
2089 seq_printf(m, "TILECTL = 0x%08x\n",
2090 I915_READ(TILECTL));
5907f5fb 2091 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2092 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2093 I915_READ(GAMTARBMODE));
2094 else
2095 seq_printf(m, "ARB_MODE = 0x%08x\n",
2096 I915_READ(ARB_MODE));
3fa7d235
DV		 2097 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2098 I915_READ(DISP_ARB_CTL));
ea16a3cd 2099 }
656bfa3a
DV		 2100
2101 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2102 seq_puts(m, "L-shaped memory detected\n");
2103
c8c8fb33 2104 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2105 mutex_unlock(&dev->struct_mutex);
2106
2107 return 0;
2108}
2109
1c60fef5
BW		 2110static int per_file_ctx(int id, void *ptr, void *data)
2111{
273497e5 2112 struct intel_context *ctx = ptr;
1c60fef5 2113 struct seq_file *m = data;
ae6c4806
DV		 2114 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2115
2116 if (!ppgtt) {
2117 seq_printf(m, " no ppgtt for context %d\n",
2118 ctx->user_handle);
2119 return 0;
2120 }
1c60fef5 2121
f83d6518
OM		 2122 if (i915_gem_context_is_default(ctx))
2123 seq_puts(m, " default context:\n");
2124 else
821d66dd 2125 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2126 ppgtt->debug_dump(ppgtt, m);
2127
2128 return 0;
2129}
2130
77df6772 2131static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2132{
3cf17fc5 2133 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2134 struct intel_engine_cs *ring;
77df6772
BW		 2135 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2136 int unused, i;
3cf17fc5 2137
77df6772
BW		 2138 if (!ppgtt)
2139 return;
2140
2141 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2142 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2143 for_each_ring(ring, dev_priv, unused) {
2144 seq_printf(m, "%s\n", ring->name);
2145 for (i = 0; i < 4; i++) {
2146 u32 offset = 0x270 + i * 8;
2147 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2148 pdp <<= 32;
2149 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2150 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2151 }
2152 }
2153}
2154
2155static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2156{
2157 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2158 struct intel_engine_cs *ring;
1c60fef5 2159 struct drm_file *file;
77df6772 2160 int i;
3cf17fc5 2161
3cf17fc5
DV		 2162 if (INTEL_INFO(dev)->gen == 6)
2163 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2164
a2c7f6fd 2165 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2166 seq_printf(m, "%s\n", ring->name);
2167 if (INTEL_INFO(dev)->gen == 7)
2168 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2169 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2170 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2171 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2172 }
2173 if (dev_priv->mm.aliasing_ppgtt) {
2174 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2175
267f0c90 2176 seq_puts(m, "aliasing PPGTT:\n");
7324cc04 2177 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
1c60fef5 2178
87d60b63 2179 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2180 }
1c60fef5
BW		 2181
2182 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2183 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2184
1c60fef5
BW		 2185 seq_printf(m, "proc: %s\n",
2186 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2187 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2188 }
2189 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2190}
2191
2192static int i915_ppgtt_info(struct seq_file *m, void *data)
2193{
9f25d007 2194 struct drm_info_node *node = m->private;
77df6772 2195 struct drm_device *dev = node->minor->dev;
c8c8fb33 2196 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2197
2198 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2199 if (ret)
2200 return ret;
c8c8fb33 2201 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2202
2203 if (INTEL_INFO(dev)->gen >= 8)
2204 gen8_ppgtt_info(m, dev);
2205 else if (INTEL_INFO(dev)->gen >= 6)
2206 gen6_ppgtt_info(m, dev);
2207
c8c8fb33 2208 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2209 mutex_unlock(&dev->struct_mutex);
2210
2211 return 0;
2212}
2213
63573eb7
BW		 2214static int i915_llc(struct seq_file *m, void *data)
2215{
9f25d007 2216 struct drm_info_node *node = m->private;
63573eb7
BW		 2217 struct drm_device *dev = node->minor->dev;
2218 struct drm_i915_private *dev_priv = dev->dev_private;
2219
2220 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2221 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2222 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2223
2224 return 0;
2225}
2226
e91fd8c6
RV		 2227static int i915_edp_psr_status(struct seq_file *m, void *data)
2228{
2229 struct drm_info_node *node = m->private;
2230 struct drm_device *dev = node->minor->dev;
2231 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2232 u32 psrperf = 0;
a6cbdb8e
RV		 2233 u32 stat[3];
2234 enum pipe pipe;
a031d709 2235 bool enabled = false;
e91fd8c6 2236
c8c8fb33
PZ		 2237 intel_runtime_pm_get(dev_priv);
2238
fa128fa6 2239 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2240 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2241 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2242 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2243 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2244 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2245 dev_priv->psr.busy_frontbuffer_bits);
2246 seq_printf(m, "Re-enable work scheduled: %s\n",
2247 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2248
a6cbdb8e
RV		 2249 if (HAS_PSR(dev)) {
2250 if (HAS_DDI(dev))
2251 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2252 else {
2253 for_each_pipe(dev_priv, pipe) {
2254 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2255 VLV_EDP_PSR_CURR_STATE_MASK;
2256 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2257 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2258 enabled = true;
2259 }
2260 }
2261 }
2262 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2263
2264 if (!HAS_DDI(dev))
2265 for_each_pipe(dev_priv, pipe) {
2266 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2267 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2268 seq_printf(m, " pipe %c", pipe_name(pipe));
2269 }
2270 seq_puts(m, "\n");
e91fd8c6 2271
fb495814
RV		 2272 seq_printf(m, "Link standby: %s\n",
2273 yesno((bool)dev_priv->psr.link_standby));
2274
a6cbdb8e
RV		 2275 /* CHV PSR has no kind of performance counter */
2276 if (HAS_PSR(dev) && HAS_DDI(dev)) {
a031d709
RV		 2277 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2278 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2279
2280 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2281 }
fa128fa6 2282 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2283
c8c8fb33 2284 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2285 return 0;
2286}
2287
d2e216d0
RV		 2288static int i915_sink_crc(struct seq_file *m, void *data)
2289{
2290 struct drm_info_node *node = m->private;
2291 struct drm_device *dev = node->minor->dev;
2292 struct intel_encoder *encoder;
2293 struct intel_connector *connector;
2294 struct intel_dp *intel_dp = NULL;
2295 int ret;
2296 u8 crc[6];
2297
2298 drm_modeset_lock_all(dev);
3a3371ff 2299 for_each_intel_encoder(dev, connector) {
d2e216d0
RV		 2300
2301 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2302 continue;
2303
b6ae3c7c
PZ		 2304 if (!connector->base.encoder)
2305 continue;
2306
d2e216d0
RV		 2307 encoder = to_intel_encoder(connector->base.encoder);
2308 if (encoder->type != INTEL_OUTPUT_EDP)
2309 continue;
2310
2311 intel_dp = enc_to_intel_dp(&encoder->base);
2312
2313 ret = intel_dp_sink_crc(intel_dp, crc);
2314 if (ret)
2315 goto out;
2316
2317 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2318 crc[0], crc[1], crc[2],
2319 crc[3], crc[4], crc[5]);
2320 goto out;
2321 }
2322 ret = -ENODEV;
2323out:
2324 drm_modeset_unlock_all(dev);
2325 return ret;
2326}
2327
ec013e7f
JB		 2328static int i915_energy_uJ(struct seq_file *m, void *data)
2329{
2330 struct drm_info_node *node = m->private;
2331 struct drm_device *dev = node->minor->dev;
2332 struct drm_i915_private *dev_priv = dev->dev_private;
2333 u64 power;
2334 u32 units;
2335
2336 if (INTEL_INFO(dev)->gen < 6)
2337 return -ENODEV;
2338
36623ef8
PZ		 2339 intel_runtime_pm_get(dev_priv);
2340
ec013e7f
JB		 2341 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2342 power = (power & 0x1f00) >> 8;
2343 units = 1000000 / (1 << power); /* convert to uJ */
2344 power = I915_READ(MCH_SECP_NRG_STTS);
2345 power *= units;
2346
36623ef8
PZ		 2347 intel_runtime_pm_put(dev_priv);
2348
ec013e7f 2349 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2350
2351 return 0;
2352}
2353
2354static int i915_pc8_status(struct seq_file *m, void *unused)
2355{
9f25d007 2356 struct drm_info_node *node = m->private;
371db66a
PZ		 2357 struct drm_device *dev = node->minor->dev;
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359
85b8d5c2 2360 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2361 seq_puts(m, "not supported\n");
2362 return 0;
2363 }
2364
86c4ec0d 2365 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2366 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2367 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2368
ec013e7f
JB		 2369 return 0;
2370}
2371
1da51581
ID		 2372static const char *power_domain_str(enum intel_display_power_domain domain)
2373{
2374 switch (domain) {
2375 case POWER_DOMAIN_PIPE_A:
2376 return "PIPE_A";
2377 case POWER_DOMAIN_PIPE_B:
2378 return "PIPE_B";
2379 case POWER_DOMAIN_PIPE_C:
2380 return "PIPE_C";
2381 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2382 return "PIPE_A_PANEL_FITTER";
2383 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2384 return "PIPE_B_PANEL_FITTER";
2385 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2386 return "PIPE_C_PANEL_FITTER";
2387 case POWER_DOMAIN_TRANSCODER_A:
2388 return "TRANSCODER_A";
2389 case POWER_DOMAIN_TRANSCODER_B:
2390 return "TRANSCODER_B";
2391 case POWER_DOMAIN_TRANSCODER_C:
2392 return "TRANSCODER_C";
2393 case POWER_DOMAIN_TRANSCODER_EDP:
2394 return "TRANSCODER_EDP";
319be8ae
ID		 2395 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2396 return "PORT_DDI_A_2_LANES";
2397 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2398 return "PORT_DDI_A_4_LANES";
2399 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2400 return "PORT_DDI_B_2_LANES";
2401 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2402 return "PORT_DDI_B_4_LANES";
2403 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2404 return "PORT_DDI_C_2_LANES";
2405 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2406 return "PORT_DDI_C_4_LANES";
2407 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2408 return "PORT_DDI_D_2_LANES";
2409 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2410 return "PORT_DDI_D_4_LANES";
2411 case POWER_DOMAIN_PORT_DSI:
2412 return "PORT_DSI";
2413 case POWER_DOMAIN_PORT_CRT:
2414 return "PORT_CRT";
2415 case POWER_DOMAIN_PORT_OTHER:
2416 return "PORT_OTHER";
1da51581
ID		 2417 case POWER_DOMAIN_VGA:
2418 return "VGA";
2419 case POWER_DOMAIN_AUDIO:
2420 return "AUDIO";
bd2bb1b9
PZ		 2421 case POWER_DOMAIN_PLLS:
2422 return "PLLS";
1407121a
S		 2423 case POWER_DOMAIN_AUX_A:
2424 return "AUX_A";
2425 case POWER_DOMAIN_AUX_B:
2426 return "AUX_B";
2427 case POWER_DOMAIN_AUX_C:
2428 return "AUX_C";
2429 case POWER_DOMAIN_AUX_D:
2430 return "AUX_D";
1da51581
ID		 2431 case POWER_DOMAIN_INIT:
2432 return "INIT";
2433 default:
5f77eeb0 2434 MISSING_CASE(domain);
1da51581
ID		 2435 return "?";
2436 }
2437}
2438
2439static int i915_power_domain_info(struct seq_file *m, void *unused)
2440{
9f25d007 2441 struct drm_info_node *node = m->private;
1da51581
ID		 2442 struct drm_device *dev = node->minor->dev;
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2445 int i;
2446
2447 mutex_lock(&power_domains->lock);
2448
2449 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2450 for (i = 0; i < power_domains->power_well_count; i++) {
2451 struct i915_power_well *power_well;
2452 enum intel_display_power_domain power_domain;
2453
2454 power_well = &power_domains->power_wells[i];
2455 seq_printf(m, "%-25s %d\n", power_well->name,
2456 power_well->count);
2457
2458 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2459 power_domain++) {
2460 if (!(BIT(power_domain) & power_well->domains))
2461 continue;
2462
2463 seq_printf(m, " %-23s %d\n",
2464 power_domain_str(power_domain),
2465 power_domains->domain_use_count[power_domain]);
2466 }
2467 }
2468
2469 mutex_unlock(&power_domains->lock);
2470
2471 return 0;
2472}
2473
53f5e3ca
JB		 2474static void intel_seq_print_mode(struct seq_file *m, int tabs,
2475 struct drm_display_mode *mode)
2476{
2477 int i;
2478
2479 for (i = 0; i < tabs; i++)
2480 seq_putc(m, '\t');
2481
2482 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2483 mode->base.id, mode->name,
2484 mode->vrefresh, mode->clock,
2485 mode->hdisplay, mode->hsync_start,
2486 mode->hsync_end, mode->htotal,
2487 mode->vdisplay, mode->vsync_start,
2488 mode->vsync_end, mode->vtotal,
2489 mode->type, mode->flags);
2490}
2491
2492static void intel_encoder_info(struct seq_file *m,
2493 struct intel_crtc *intel_crtc,
2494 struct intel_encoder *intel_encoder)
2495{
9f25d007 2496 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2497 struct drm_device *dev = node->minor->dev;
2498 struct drm_crtc *crtc = &intel_crtc->base;
2499 struct intel_connector *intel_connector;
2500 struct drm_encoder *encoder;
2501
2502 encoder = &intel_encoder->base;
2503 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2504 encoder->base.id, encoder->name);
53f5e3ca
JB		 2505 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2506 struct drm_connector *connector = &intel_connector->base;
2507 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2508 connector->base.id,
c23cc417 2509 connector->name,
53f5e3ca
JB		 2510 drm_get_connector_status_name(connector->status));
2511 if (connector->status == connector_status_connected) {
2512 struct drm_display_mode *mode = &crtc->mode;
2513 seq_printf(m, ", mode:\n");
2514 intel_seq_print_mode(m, 2, mode);
2515 } else {
2516 seq_putc(m, '\n');
2517 }
2518 }
2519}
2520
2521static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2522{
9f25d007 2523 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2524 struct drm_device *dev = node->minor->dev;
2525 struct drm_crtc *crtc = &intel_crtc->base;
2526 struct intel_encoder *intel_encoder;
2527
5aa8a937
MR		 2528 if (crtc->primary->fb)
2529 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2530 crtc->primary->fb->base.id, crtc->x, crtc->y,
2531 crtc->primary->fb->width, crtc->primary->fb->height);
2532 else
2533 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2534 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2535 intel_encoder_info(m, intel_crtc, intel_encoder);
2536}
2537
2538static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2539{
2540 struct drm_display_mode *mode = panel->fixed_mode;
2541
2542 seq_printf(m, "\tfixed mode:\n");
2543 intel_seq_print_mode(m, 2, mode);
2544}
2545
2546static void intel_dp_info(struct seq_file *m,
2547 struct intel_connector *intel_connector)
2548{
2549 struct intel_encoder *intel_encoder = intel_connector->encoder;
2550 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2551
2552 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2553 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2554 "no");
2555 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2556 intel_panel_info(m, &intel_connector->panel);
2557}
2558
2559static void intel_hdmi_info(struct seq_file *m,
2560 struct intel_connector *intel_connector)
2561{
2562 struct intel_encoder *intel_encoder = intel_connector->encoder;
2563 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2564
2565 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2566 "no");
2567}
2568
2569static void intel_lvds_info(struct seq_file *m,
2570 struct intel_connector *intel_connector)
2571{
2572 intel_panel_info(m, &intel_connector->panel);
2573}
2574
2575static void intel_connector_info(struct seq_file *m,
2576 struct drm_connector *connector)
2577{
2578 struct intel_connector *intel_connector = to_intel_connector(connector);
2579 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2580 struct drm_display_mode *mode;
53f5e3ca
JB		 2581
2582 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2583 connector->base.id, connector->name,
53f5e3ca
JB		 2584 drm_get_connector_status_name(connector->status));
2585 if (connector->status == connector_status_connected) {
2586 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2587 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2588 connector->display_info.width_mm,
2589 connector->display_info.height_mm);
2590 seq_printf(m, "\tsubpixel order: %s\n",
2591 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2592 seq_printf(m, "\tCEA rev: %d\n",
2593 connector->display_info.cea_rev);
2594 }
36cd7444
DA		 2595 if (intel_encoder) {
2596 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2597 intel_encoder->type == INTEL_OUTPUT_EDP)
2598 intel_dp_info(m, intel_connector);
2599 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2600 intel_hdmi_info(m, intel_connector);
2601 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2602 intel_lvds_info(m, intel_connector);
2603 }
53f5e3ca 2604
f103fc7d
JB		 2605 seq_printf(m, "\tmodes:\n");
2606 list_for_each_entry(mode, &connector->modes, head)
2607 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2608}
2609
065f2ec2
CW		 2610static bool cursor_active(struct drm_device *dev, int pipe)
2611{
2612 struct drm_i915_private *dev_priv = dev->dev_private;
2613 u32 state;
2614
2615 if (IS_845G(dev) || IS_I865G(dev))
2616 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2617 else
5efb3e28 2618 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2619
2620 return state;
2621}
2622
2623static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2624{
2625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 u32 pos;
2627
5efb3e28 2628 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2629
2630 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2631 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2632 *x = -*x;
2633
2634 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2635 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2636 *y = -*y;
2637
2638 return cursor_active(dev, pipe);
2639}
2640
53f5e3ca
JB		 2641static int i915_display_info(struct seq_file *m, void *unused)
2642{
9f25d007 2643 struct drm_info_node *node = m->private;
53f5e3ca 2644 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2645 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2646 struct intel_crtc *crtc;
53f5e3ca
JB		 2647 struct drm_connector *connector;
2648
b0e5ddf3 2649 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2650 drm_modeset_lock_all(dev);
2651 seq_printf(m, "CRTC info\n");
2652 seq_printf(m, "---------\n");
d3fcc808 2653 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2654 bool active;
2655 int x, y;
53f5e3ca 2656
57127efa 2657 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2658 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2659 yesno(crtc->active), crtc->config->pipe_src_w,
2660 crtc->config->pipe_src_h);
a23dc658 2661 if (crtc->active) {
065f2ec2
CW		 2662 intel_crtc_info(m, crtc);
2663
a23dc658 2664 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2665 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2666 yesno(crtc->cursor_base),
3dd512fb
MR		 2667 x, y, crtc->base.cursor->state->crtc_w,
2668 crtc->base.cursor->state->crtc_h,
57127efa 2669 crtc->cursor_addr, yesno(active));
a23dc658 2670 }
cace841c
DV		 2671
2672 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2673 yesno(!crtc->cpu_fifo_underrun_disabled),
2674 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2675 }
2676
2677 seq_printf(m, "\n");
2678 seq_printf(m, "Connector info\n");
2679 seq_printf(m, "--------------\n");
2680 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2681 intel_connector_info(m, connector);
2682 }
2683 drm_modeset_unlock_all(dev);
b0e5ddf3 2684 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2685
2686 return 0;
2687}
2688
e04934cf
BW		 2689static int i915_semaphore_status(struct seq_file *m, void *unused)
2690{
2691 struct drm_info_node *node = (struct drm_info_node *) m->private;
2692 struct drm_device *dev = node->minor->dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694 struct intel_engine_cs *ring;
2695 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2696 int i, j, ret;
2697
2698 if (!i915_semaphore_is_enabled(dev)) {
2699 seq_puts(m, "Semaphores are disabled\n");
2700 return 0;
2701 }
2702
2703 ret = mutex_lock_interruptible(&dev->struct_mutex);
2704 if (ret)
2705 return ret;
03872064 2706 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2707
2708 if (IS_BROADWELL(dev)) {
2709 struct page *page;
2710 uint64_t *seqno;
2711
2712 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2713
2714 seqno = (uint64_t *)kmap_atomic(page);
2715 for_each_ring(ring, dev_priv, i) {
2716 uint64_t offset;
2717
2718 seq_printf(m, "%s\n", ring->name);
2719
2720 seq_puts(m, " Last signal:");
2721 for (j = 0; j < num_rings; j++) {
2722 offset = i * I915_NUM_RINGS + j;
2723 seq_printf(m, "0x%08llx (0x%02llx) ",
2724 seqno[offset], offset * 8);
2725 }
2726 seq_putc(m, '\n');
2727
2728 seq_puts(m, " Last wait: ");
2729 for (j = 0; j < num_rings; j++) {
2730 offset = i + (j * I915_NUM_RINGS);
2731 seq_printf(m, "0x%08llx (0x%02llx) ",
2732 seqno[offset], offset * 8);
2733 }
2734 seq_putc(m, '\n');
2735
2736 }
2737 kunmap_atomic(seqno);
2738 } else {
2739 seq_puts(m, " Last signal:");
2740 for_each_ring(ring, dev_priv, i)
2741 for (j = 0; j < num_rings; j++)
2742 seq_printf(m, "0x%08x\n",
2743 I915_READ(ring->semaphore.mbox.signal[j]));
2744 seq_putc(m, '\n');
2745 }
2746
2747 seq_puts(m, "\nSync seqno:\n");
2748 for_each_ring(ring, dev_priv, i) {
2749 for (j = 0; j < num_rings; j++) {
2750 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2751 }
2752 seq_putc(m, '\n');
2753 }
2754 seq_putc(m, '\n');
2755
03872064 2756 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2757 mutex_unlock(&dev->struct_mutex);
2758 return 0;
2759}
2760
728e29d7
DV		 2761static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2762{
2763 struct drm_info_node *node = (struct drm_info_node *) m->private;
2764 struct drm_device *dev = node->minor->dev;
2765 struct drm_i915_private *dev_priv = dev->dev_private;
2766 int i;
2767
2768 drm_modeset_lock_all(dev);
2769 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2770 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2771
2772 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2773 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2774 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2775 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2776 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2777 seq_printf(m, " dpll_md: 0x%08x\n",
2778 pll->config.hw_state.dpll_md);
2779 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2780 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2781 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2782 }
2783 drm_modeset_unlock_all(dev);
2784
2785 return 0;
2786}
2787
1ed1ef9d 2788static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2789{
2790 int i;
2791 int ret;
2792 struct drm_info_node *node = (struct drm_info_node *) m->private;
2793 struct drm_device *dev = node->minor->dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795
888b5995
AS		 2796 ret = mutex_lock_interruptible(&dev->struct_mutex);
2797 if (ret)
2798 return ret;
2799
2800 intel_runtime_pm_get(dev_priv);
2801
7225342a
MK		 2802 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2803 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2804 u32 addr, mask, value, read;
2805 bool ok;
888b5995 2806
7225342a
MK		 2807 addr = dev_priv->workarounds.reg[i].addr;
2808 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2809 value = dev_priv->workarounds.reg[i].value;
2810 read = I915_READ(addr);
2811 ok = (value & mask) == (read & mask);
2812 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2813 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2814 }
2815
2816 intel_runtime_pm_put(dev_priv);
2817 mutex_unlock(&dev->struct_mutex);
2818
2819 return 0;
2820}
2821
c5511e44
DL		 2822static int i915_ddb_info(struct seq_file *m, void *unused)
2823{
2824 struct drm_info_node *node = m->private;
2825 struct drm_device *dev = node->minor->dev;
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 struct skl_ddb_allocation *ddb;
2828 struct skl_ddb_entry *entry;
2829 enum pipe pipe;
2830 int plane;
2831
2fcffe19
DL		 2832 if (INTEL_INFO(dev)->gen < 9)
2833 return 0;
2834
c5511e44
DL		 2835 drm_modeset_lock_all(dev);
2836
2837 ddb = &dev_priv->wm.skl_hw.ddb;
2838
2839 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2840
2841 for_each_pipe(dev_priv, pipe) {
2842 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2843
dd740780 2844 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 2845 entry = &ddb->plane[pipe][plane];
2846 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2847 entry->start, entry->end,
2848 skl_ddb_entry_size(entry));
2849 }
2850
2851 entry = &ddb->cursor[pipe];
2852 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2853 entry->end, skl_ddb_entry_size(entry));
2854 }
2855
2856 drm_modeset_unlock_all(dev);
2857
2858 return 0;
2859}
2860
a54746e3
VK		 2861static void drrs_status_per_crtc(struct seq_file *m,
2862 struct drm_device *dev, struct intel_crtc *intel_crtc)
2863{
2864 struct intel_encoder *intel_encoder;
2865 struct drm_i915_private *dev_priv = dev->dev_private;
2866 struct i915_drrs *drrs = &dev_priv->drrs;
2867 int vrefresh = 0;
2868
2869 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
2870 /* Encoder connected on this CRTC */
2871 switch (intel_encoder->type) {
2872 case INTEL_OUTPUT_EDP:
2873 seq_puts(m, "eDP:\n");
2874 break;
2875 case INTEL_OUTPUT_DSI:
2876 seq_puts(m, "DSI:\n");
2877 break;
2878 case INTEL_OUTPUT_HDMI:
2879 seq_puts(m, "HDMI:\n");
2880 break;
2881 case INTEL_OUTPUT_DISPLAYPORT:
2882 seq_puts(m, "DP:\n");
2883 break;
2884 default:
2885 seq_printf(m, "Other encoder (id=%d).\n",
2886 intel_encoder->type);
2887 return;
2888 }
2889 }
2890
2891 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
2892 seq_puts(m, "\tVBT: DRRS_type: Static");
2893 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
2894 seq_puts(m, "\tVBT: DRRS_type: Seamless");
2895 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
2896 seq_puts(m, "\tVBT: DRRS_type: None");
2897 else
2898 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
2899
2900 seq_puts(m, "\n\n");
2901
2902 if (intel_crtc->config->has_drrs) {
2903 struct intel_panel *panel;
2904
2905 mutex_lock(&drrs->mutex);
2906 /* DRRS Supported */
2907 seq_puts(m, "\tDRRS Supported: Yes\n");
2908
2909 /* disable_drrs() will make drrs->dp NULL */
2910 if (!drrs->dp) {
2911 seq_puts(m, "Idleness DRRS: Disabled");
2912 mutex_unlock(&drrs->mutex);
2913 return;
2914 }
2915
2916 panel = &drrs->dp->attached_connector->panel;
2917 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
2918 drrs->busy_frontbuffer_bits);
2919
2920 seq_puts(m, "\n\t\t");
2921 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
2922 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
2923 vrefresh = panel->fixed_mode->vrefresh;
2924 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
2925 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
2926 vrefresh = panel->downclock_mode->vrefresh;
2927 } else {
2928 seq_printf(m, "DRRS_State: Unknown(%d)\n",
2929 drrs->refresh_rate_type);
2930 mutex_unlock(&drrs->mutex);
2931 return;
2932 }
2933 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
2934
2935 seq_puts(m, "\n\t\t");
2936 mutex_unlock(&drrs->mutex);
2937 } else {
2938 /* DRRS not supported. Print the VBT parameter*/
2939 seq_puts(m, "\tDRRS Supported : No");
2940 }
2941 seq_puts(m, "\n");
2942}
2943
2944static int i915_drrs_status(struct seq_file *m, void *unused)
2945{
2946 struct drm_info_node *node = m->private;
2947 struct drm_device *dev = node->minor->dev;
2948 struct intel_crtc *intel_crtc;
2949 int active_crtc_cnt = 0;
2950
2951 for_each_intel_crtc(dev, intel_crtc) {
2952 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
2953
2954 if (intel_crtc->active) {
2955 active_crtc_cnt++;
2956 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
2957
2958 drrs_status_per_crtc(m, dev, intel_crtc);
2959 }
2960
2961 drm_modeset_unlock(&intel_crtc->base.mutex);
2962 }
2963
2964 if (!active_crtc_cnt)
2965 seq_puts(m, "No active crtc found\n");
2966
2967 return 0;
2968}
2969
07144428
DL		 2970struct pipe_crc_info {
2971 const char *name;
2972 struct drm_device *dev;
2973 enum pipe pipe;
2974};
2975
11bed958
DA		 2976static int i915_dp_mst_info(struct seq_file *m, void *unused)
2977{
2978 struct drm_info_node *node = (struct drm_info_node *) m->private;
2979 struct drm_device *dev = node->minor->dev;
2980 struct drm_encoder *encoder;
2981 struct intel_encoder *intel_encoder;
2982 struct intel_digital_port *intel_dig_port;
2983 drm_modeset_lock_all(dev);
2984 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2985 intel_encoder = to_intel_encoder(encoder);
2986 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2987 continue;
2988 intel_dig_port = enc_to_dig_port(encoder);
2989 if (!intel_dig_port->dp.can_mst)
2990 continue;
2991
2992 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2993 }
2994 drm_modeset_unlock_all(dev);
2995 return 0;
2996}
2997
07144428
DL		 2998static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2999{
be5c7a90
DL		 3000 struct pipe_crc_info *info = inode->i_private;
3001 struct drm_i915_private *dev_priv = info->dev->dev_private;
3002 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3003
7eb1c496
DV		 3004 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3005 return -ENODEV;
3006
d538bbdf
DL		 3007 spin_lock_irq(&pipe_crc->lock);
3008
3009 if (pipe_crc->opened) {
3010 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3011 return -EBUSY; /* already open */
3012 }
3013
d538bbdf 3014 pipe_crc->opened = true;
07144428
DL		 3015 filep->private_data = inode->i_private;
3016
d538bbdf
DL		 3017 spin_unlock_irq(&pipe_crc->lock);
3018
07144428
DL		 3019 return 0;
3020}
3021
3022static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3023{
be5c7a90
DL		 3024 struct pipe_crc_info *info = inode->i_private;
3025 struct drm_i915_private *dev_priv = info->dev->dev_private;
3026 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3027
d538bbdf
DL		 3028 spin_lock_irq(&pipe_crc->lock);
3029 pipe_crc->opened = false;
3030 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3031
07144428
DL		 3032 return 0;
3033}
3034
3035/* (6 fields, 8 chars each, space separated (5) + '\n') */
3036#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3037/* account for \'0' */
3038#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3039
3040static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3041{
d538bbdf
DL		 3042 assert_spin_locked(&pipe_crc->lock);
3043 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3044 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3045}
3046
3047static ssize_t
3048i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3049 loff_t *pos)
3050{
3051 struct pipe_crc_info *info = filep->private_data;
3052 struct drm_device *dev = info->dev;
3053 struct drm_i915_private *dev_priv = dev->dev_private;
3054 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3055 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3056 int n_entries;
07144428
DL		 3057 ssize_t bytes_read;
3058
3059 /*
3060 * Don't allow user space to provide buffers not big enough to hold
3061 * a line of data.
3062 */
3063 if (count < PIPE_CRC_LINE_LEN)
3064 return -EINVAL;
3065
3066 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3067 return 0;
07144428
DL		 3068
3069 /* nothing to read */
d538bbdf 3070 spin_lock_irq(&pipe_crc->lock);
07144428 3071 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3072 int ret;
3073
3074 if (filep->f_flags & O_NONBLOCK) {
3075 spin_unlock_irq(&pipe_crc->lock);
07144428 3076 return -EAGAIN;
d538bbdf 3077 }
07144428 3078
d538bbdf
DL		 3079 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3080 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3081 if (ret) {
3082 spin_unlock_irq(&pipe_crc->lock);
3083 return ret;
3084 }
8bf1e9f1
SH		 3085 }
3086
07144428 3087 /* We now have one or more entries to read */
9ad6d99f 3088 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3089
07144428 3090 bytes_read = 0;
9ad6d99f
VS		 3091 while (n_entries > 0) {
3092 struct intel_pipe_crc_entry *entry =
3093 &pipe_crc->entries[pipe_crc->tail];
07144428 3094 int ret;
8bf1e9f1 3095
9ad6d99f
VS		 3096 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3097 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3098 break;
3099
3100 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3101 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3102
07144428
DL		 3103 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3104 "%8u %8x %8x %8x %8x %8x\n",
3105 entry->frame, entry->crc[0],
3106 entry->crc[1], entry->crc[2],
3107 entry->crc[3], entry->crc[4]);
3108
9ad6d99f
VS		 3109 spin_unlock_irq(&pipe_crc->lock);
3110
3111 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3112 if (ret == PIPE_CRC_LINE_LEN)
3113 return -EFAULT;
b2c88f5b 3114
9ad6d99f
VS		 3115 user_buf += PIPE_CRC_LINE_LEN;
3116 n_entries--;
3117
3118 spin_lock_irq(&pipe_crc->lock);
3119 }
8bf1e9f1 3120
d538bbdf
DL		 3121 spin_unlock_irq(&pipe_crc->lock);
3122
07144428
DL		 3123 return bytes_read;
3124}
3125
3126static const struct file_operations i915_pipe_crc_fops = {
3127 .owner = THIS_MODULE,
3128 .open = i915_pipe_crc_open,
3129 .read = i915_pipe_crc_read,
3130 .release = i915_pipe_crc_release,
3131};
3132
3133static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3134 {
3135 .name = "i915_pipe_A_crc",
3136 .pipe = PIPE_A,
3137 },
3138 {
3139 .name = "i915_pipe_B_crc",
3140 .pipe = PIPE_B,
3141 },
3142 {
3143 .name = "i915_pipe_C_crc",
3144 .pipe = PIPE_C,
3145 },
3146};
3147
3148static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3149 enum pipe pipe)
3150{
3151 struct drm_device *dev = minor->dev;
3152 struct dentry *ent;
3153 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3154
3155 info->dev = dev;
3156 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3157 &i915_pipe_crc_fops);
f3c5fe97
WY		 3158 if (!ent)
3159 return -ENOMEM;
07144428
DL		 3160
3161 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3162}
3163
e8dfcf78 3164static const char * const pipe_crc_sources[] = {
926321d5
DV		 3165 "none",
3166 "plane1",
3167 "plane2",
3168 "pf",
5b3a856b 3169 "pipe",
3d099a05
DV		 3170 "TV",
3171 "DP-B",
3172 "DP-C",
3173 "DP-D",
46a19188 3174 "auto",
926321d5
DV		 3175};
3176
3177static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3178{
3179 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3180 return pipe_crc_sources[source];
3181}
3182
bd9db02f 3183static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3184{
3185 struct drm_device *dev = m->private;
3186 struct drm_i915_private *dev_priv = dev->dev_private;
3187 int i;
3188
3189 for (i = 0; i < I915_MAX_PIPES; i++)
3190 seq_printf(m, "%c %s\n", pipe_name(i),
3191 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3192
3193 return 0;
3194}
3195
bd9db02f 3196static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3197{
3198 struct drm_device *dev = inode->i_private;
3199
bd9db02f 3200 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3201}
3202
46a19188 3203static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3204 uint32_t *val)
3205{
46a19188
DV		 3206 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3207 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3208
3209 switch (*source) {
52f843f6
DV		 3210 case INTEL_PIPE_CRC_SOURCE_PIPE:
3211 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3212 break;
3213 case INTEL_PIPE_CRC_SOURCE_NONE:
3214 *val = 0;
3215 break;
3216 default:
3217 return -EINVAL;
3218 }
3219
3220 return 0;
3221}
3222
46a19188
DV		 3223static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3224 enum intel_pipe_crc_source *source)
3225{
3226 struct intel_encoder *encoder;
3227 struct intel_crtc *crtc;
26756809 3228 struct intel_digital_port *dig_port;
46a19188
DV		 3229 int ret = 0;
3230
3231 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3232
6e9f798d 3233 drm_modeset_lock_all(dev);
b2784e15 3234 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3235 if (!encoder->base.crtc)
3236 continue;
3237
3238 crtc = to_intel_crtc(encoder->base.crtc);
3239
3240 if (crtc->pipe != pipe)
3241 continue;
3242
3243 switch (encoder->type) {
3244 case INTEL_OUTPUT_TVOUT:
3245 *source = INTEL_PIPE_CRC_SOURCE_TV;
3246 break;
3247 case INTEL_OUTPUT_DISPLAYPORT:
3248 case INTEL_OUTPUT_EDP:
26756809
DV		 3249 dig_port = enc_to_dig_port(&encoder->base);
3250 switch (dig_port->port) {
3251 case PORT_B:
3252 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3253 break;
3254 case PORT_C:
3255 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3256 break;
3257 case PORT_D:
3258 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3259 break;
3260 default:
3261 WARN(1, "nonexisting DP port %c\n",
3262 port_name(dig_port->port));
3263 break;
3264 }
46a19188 3265 break;
6847d71b
PZ		 3266 default:
3267 break;
46a19188
DV		 3268 }
3269 }
6e9f798d 3270 drm_modeset_unlock_all(dev);
46a19188
DV		 3271
3272 return ret;
3273}
3274
3275static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3276 enum pipe pipe,
3277 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3278 uint32_t *val)
3279{
8d2f24ca
DV		 3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 bool need_stable_symbols = false;
3282
46a19188
DV		 3283 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3284 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3285 if (ret)
3286 return ret;
3287 }
3288
3289 switch (*source) {
7ac0129b
DV		 3290 case INTEL_PIPE_CRC_SOURCE_PIPE:
3291 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3292 break;
3293 case INTEL_PIPE_CRC_SOURCE_DP_B:
3294 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3295 need_stable_symbols = true;
7ac0129b
DV		 3296 break;
3297 case INTEL_PIPE_CRC_SOURCE_DP_C:
3298 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3299 need_stable_symbols = true;
7ac0129b 3300 break;
2be57922
VS		 3301 case INTEL_PIPE_CRC_SOURCE_DP_D:
3302 if (!IS_CHERRYVIEW(dev))
3303 return -EINVAL;
3304 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3305 need_stable_symbols = true;
3306 break;
7ac0129b
DV		 3307 case INTEL_PIPE_CRC_SOURCE_NONE:
3308 *val = 0;
3309 break;
3310 default:
3311 return -EINVAL;
3312 }
3313
8d2f24ca
DV		 3314 /*
3315 * When the pipe CRC tap point is after the transcoders we need
3316 * to tweak symbol-level features to produce a deterministic series of
3317 * symbols for a given frame. We need to reset those features only once
3318 * a frame (instead of every nth symbol):
3319 * - DC-balance: used to ensure a better clock recovery from the data
3320 * link (SDVO)
3321 * - DisplayPort scrambling: used for EMI reduction
3322 */
3323 if (need_stable_symbols) {
3324 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3325
8d2f24ca 3326 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3327 switch (pipe) {
3328 case PIPE_A:
8d2f24ca 3329 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3330 break;
3331 case PIPE_B:
8d2f24ca 3332 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3333 break;
3334 case PIPE_C:
3335 tmp |= PIPE_C_SCRAMBLE_RESET;
3336 break;
3337 default:
3338 return -EINVAL;
3339 }
8d2f24ca
DV		 3340 I915_WRITE(PORT_DFT2_G4X, tmp);
3341 }
3342
7ac0129b
DV		 3343 return 0;
3344}
3345
4b79ebf7 3346static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3347 enum pipe pipe,
3348 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3349 uint32_t *val)
3350{
84093603
DV		 3351 struct drm_i915_private *dev_priv = dev->dev_private;
3352 bool need_stable_symbols = false;
3353
46a19188
DV		 3354 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3355 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3356 if (ret)
3357 return ret;
3358 }
3359
3360 switch (*source) {
4b79ebf7
DV		 3361 case INTEL_PIPE_CRC_SOURCE_PIPE:
3362 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3363 break;
3364 case INTEL_PIPE_CRC_SOURCE_TV:
3365 if (!SUPPORTS_TV(dev))
3366 return -EINVAL;
3367 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3368 break;
3369 case INTEL_PIPE_CRC_SOURCE_DP_B:
3370 if (!IS_G4X(dev))
3371 return -EINVAL;
3372 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3373 need_stable_symbols = true;
4b79ebf7
DV		 3374 break;
3375 case INTEL_PIPE_CRC_SOURCE_DP_C:
3376 if (!IS_G4X(dev))
3377 return -EINVAL;
3378 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3379 need_stable_symbols = true;
4b79ebf7
DV		 3380 break;
3381 case INTEL_PIPE_CRC_SOURCE_DP_D:
3382 if (!IS_G4X(dev))
3383 return -EINVAL;
3384 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3385 need_stable_symbols = true;
4b79ebf7
DV		 3386 break;
3387 case INTEL_PIPE_CRC_SOURCE_NONE:
3388 *val = 0;
3389 break;
3390 default:
3391 return -EINVAL;
3392 }
3393
84093603
DV		 3394 /*
3395 * When the pipe CRC tap point is after the transcoders we need
3396 * to tweak symbol-level features to produce a deterministic series of
3397 * symbols for a given frame. We need to reset those features only once
3398 * a frame (instead of every nth symbol):
3399 * - DC-balance: used to ensure a better clock recovery from the data
3400 * link (SDVO)
3401 * - DisplayPort scrambling: used for EMI reduction
3402 */
3403 if (need_stable_symbols) {
3404 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3405
3406 WARN_ON(!IS_G4X(dev));
3407
3408 I915_WRITE(PORT_DFT_I9XX,
3409 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3410
3411 if (pipe == PIPE_A)
3412 tmp |= PIPE_A_SCRAMBLE_RESET;
3413 else
3414 tmp |= PIPE_B_SCRAMBLE_RESET;
3415
3416 I915_WRITE(PORT_DFT2_G4X, tmp);
3417 }
3418
4b79ebf7
DV		 3419 return 0;
3420}
3421
8d2f24ca
DV		 3422static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3423 enum pipe pipe)
3424{
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3427
eb736679
VS		 3428 switch (pipe) {
3429 case PIPE_A:
8d2f24ca 3430 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3431 break;
3432 case PIPE_B:
8d2f24ca 3433 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3434 break;
3435 case PIPE_C:
3436 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3437 break;
3438 default:
3439 return;
3440 }
8d2f24ca
DV		 3441 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3442 tmp &= ~DC_BALANCE_RESET_VLV;
3443 I915_WRITE(PORT_DFT2_G4X, tmp);
3444
3445}
3446
84093603
DV		 3447static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3448 enum pipe pipe)
3449{
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3451 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3452
3453 if (pipe == PIPE_A)
3454 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3455 else
3456 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3457 I915_WRITE(PORT_DFT2_G4X, tmp);
3458
3459 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3460 I915_WRITE(PORT_DFT_I9XX,
3461 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3462 }
3463}
3464
46a19188 3465static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3466 uint32_t *val)
3467{
46a19188
DV		 3468 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3469 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3470
3471 switch (*source) {
5b3a856b
DV		 3472 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3473 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3474 break;
3475 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3476 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3477 break;
5b3a856b
DV		 3478 case INTEL_PIPE_CRC_SOURCE_PIPE:
3479 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3480 break;
3d099a05 3481 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3482 *val = 0;
3483 break;
3d099a05
DV		 3484 default:
3485 return -EINVAL;
5b3a856b
DV		 3486 }
3487
3488 return 0;
3489}
3490
fabf6e51
DV		 3491static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3492{
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 struct intel_crtc *crtc =
3495 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3496
3497 drm_modeset_lock_all(dev);
3498 /*
3499 * If we use the eDP transcoder we need to make sure that we don't
3500 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3501 * relevant on hsw with pipe A when using the always-on power well
3502 * routing.
3503 */
6e3c9717
ACO		 3504 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3505 !crtc->config->pch_pfit.enabled) {
3506 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3507
3508 intel_display_power_get(dev_priv,
3509 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3510
3511 dev_priv->display.crtc_disable(&crtc->base);
3512 dev_priv->display.crtc_enable(&crtc->base);
3513 }
3514 drm_modeset_unlock_all(dev);
3515}
3516
3517static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3518{
3519 struct drm_i915_private *dev_priv = dev->dev_private;
3520 struct intel_crtc *crtc =
3521 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3522
3523 drm_modeset_lock_all(dev);
3524 /*
3525 * If we use the eDP transcoder we need to make sure that we don't
3526 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3527 * relevant on hsw with pipe A when using the always-on power well
3528 * routing.
3529 */
6e3c9717
ACO		 3530 if (crtc->config->pch_pfit.force_thru) {
3531 crtc->config->pch_pfit.force_thru = false;
fabf6e51
DV		 3532
3533 dev_priv->display.crtc_disable(&crtc->base);
3534 dev_priv->display.crtc_enable(&crtc->base);
3535
3536 intel_display_power_put(dev_priv,
3537 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3538 }
3539 drm_modeset_unlock_all(dev);
3540}
3541
3542static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3543 enum pipe pipe,
3544 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3545 uint32_t *val)
3546{
46a19188
DV		 3547 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3548 *source = INTEL_PIPE_CRC_SOURCE_PF;
3549
3550 switch (*source) {
5b3a856b
DV		 3551 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3552 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3553 break;
3554 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3555 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3556 break;
3557 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3558 if (IS_HASWELL(dev) && pipe == PIPE_A)
3559 hsw_trans_edp_pipe_A_crc_wa(dev);
3560
5b3a856b
DV		 3561 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3562 break;
3d099a05 3563 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3564 *val = 0;
3565 break;
3d099a05
DV		 3566 default:
3567 return -EINVAL;
5b3a856b
DV		 3568 }
3569
3570 return 0;
3571}
3572
926321d5
DV		 3573static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3574 enum intel_pipe_crc_source source)
3575{
3576 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3577 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3578 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3579 pipe));
432f3342 3580 u32 val = 0; /* shut up gcc */
5b3a856b 3581 int ret;
926321d5 3582
cc3da175
DL		 3583 if (pipe_crc->source == source)
3584 return 0;
3585
ae676fcd
DL		 3586 /* forbid changing the source without going back to 'none' */
3587 if (pipe_crc->source && source)
3588 return -EINVAL;
3589
9d8b0588
DV		 3590 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3591 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3592 return -EIO;
3593 }
3594
52f843f6 3595 if (IS_GEN2(dev))
46a19188 3596 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3597 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3598 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3599 else if (IS_VALLEYVIEW(dev))
fabf6e51 3600 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3601 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3602 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3603 else
fabf6e51 3604 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3605
3606 if (ret != 0)
3607 return ret;
3608
4b584369
DL		 3609 /* none -> real source transition */
3610 if (source) {
4252fbc3
VS		 3611 struct intel_pipe_crc_entry *entries;
3612
7cd6ccff
DL		 3613 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3614 pipe_name(pipe), pipe_crc_source_name(source));
3615
3cf54b34
VS		 3616 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3617 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3618 GFP_KERNEL);
3619 if (!entries)
e5f75aca
DL		 3620 return -ENOMEM;
3621
8c740dce
PZ		 3622 /*
3623 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3624 * enabled and disabled dynamically based on package C states,
3625 * user space can't make reliable use of the CRCs, so let's just
3626 * completely disable it.
3627 */
3628 hsw_disable_ips(crtc);
3629
d538bbdf 3630 spin_lock_irq(&pipe_crc->lock);
64387b61 3631 kfree(pipe_crc->entries);
4252fbc3 3632 pipe_crc->entries = entries;
d538bbdf
DL		 3633 pipe_crc->head = 0;
3634 pipe_crc->tail = 0;
3635 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3636 }
3637
cc3da175 3638 pipe_crc->source = source;
926321d5 3639
926321d5
DV		 3640 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3641 POSTING_READ(PIPE_CRC_CTL(pipe));
3642
e5f75aca
DL		 3643 /* real source -> none transition */
3644 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3645 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3646 struct intel_crtc *crtc =
3647 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3648
7cd6ccff
DL		 3649 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3650 pipe_name(pipe));
3651
a33d7105
DV		 3652 drm_modeset_lock(&crtc->base.mutex, NULL);
3653 if (crtc->active)
3654 intel_wait_for_vblank(dev, pipe);
3655 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3656
d538bbdf
DL		 3657 spin_lock_irq(&pipe_crc->lock);
3658 entries = pipe_crc->entries;
e5f75aca 3659 pipe_crc->entries = NULL;
9ad6d99f
VS		 3660 pipe_crc->head = 0;
3661 pipe_crc->tail = 0;
d538bbdf
DL		 3662 spin_unlock_irq(&pipe_crc->lock);
3663
3664 kfree(entries);
84093603
DV		 3665
3666 if (IS_G4X(dev))
3667 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3668 else if (IS_VALLEYVIEW(dev))
3669 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3670 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3671 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3672
3673 hsw_enable_ips(crtc);
e5f75aca
DL		 3674 }
3675
926321d5
DV		 3676 return 0;
3677}
3678
3679/*
3680 * Parse pipe CRC command strings:
b94dec87
DL		 3681 * command: wsp* object wsp+ name wsp+ source wsp*
3682 * object: 'pipe'
3683 * name: (A | B | C)
926321d5
DV		 3684 * source: (none | plane1 | plane2 | pf)
3685 * wsp: (#0x20 | #0x9 | #0xA)+
3686 *
3687 * eg.:
b94dec87
DL		 3688 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3689 * "pipe A none" -> Stop CRC
926321d5 3690 */
bd9db02f 3691static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3692{
3693 int n_words = 0;
3694
3695 while (*buf) {
3696 char *end;
3697
3698 /* skip leading white space */
3699 buf = skip_spaces(buf);
3700 if (!*buf)
3701 break; /* end of buffer */
3702
3703 /* find end of word */
3704 for (end = buf; *end && !isspace(*end); end++)
3705 ;
3706
3707 if (n_words == max_words) {
3708 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3709 max_words);
3710 return -EINVAL; /* ran out of words[] before bytes */
3711 }
3712
3713 if (*end)
3714 *end++ = '\0';
3715 words[n_words++] = buf;
3716 buf = end;
3717 }
3718
3719 return n_words;
3720}
3721
b94dec87
DL		 3722enum intel_pipe_crc_object {
3723 PIPE_CRC_OBJECT_PIPE,
3724};
3725
e8dfcf78 3726static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3727 "pipe",
3728};
3729
3730static int
bd9db02f 3731display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3732{
3733 int i;
3734
3735 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3736 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3737 *o = i;
b94dec87
DL		 3738 return 0;
3739 }
3740
3741 return -EINVAL;
3742}
3743
bd9db02f 3744static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3745{
3746 const char name = buf[0];
3747
3748 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3749 return -EINVAL;
3750
3751 *pipe = name - 'A';
3752
3753 return 0;
3754}
3755
3756static int
bd9db02f 3757display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3758{
3759 int i;
3760
3761 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3762 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3763 *s = i;
926321d5
DV		 3764 return 0;
3765 }
3766
3767 return -EINVAL;
3768}
3769
bd9db02f 3770static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3771{
b94dec87 3772#define N_WORDS 3
926321d5 3773 int n_words;
b94dec87 3774 char *words[N_WORDS];
926321d5 3775 enum pipe pipe;
b94dec87 3776 enum intel_pipe_crc_object object;
926321d5
DV		 3777 enum intel_pipe_crc_source source;
3778
bd9db02f 3779 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3780 if (n_words != N_WORDS) {
3781 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3782 N_WORDS);
3783 return -EINVAL;
3784 }
3785
bd9db02f 3786 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3787 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3788 return -EINVAL;
3789 }
3790
bd9db02f 3791 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3792 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3793 return -EINVAL;
3794 }
3795
bd9db02f 3796 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3797 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3798 return -EINVAL;
3799 }
3800
3801 return pipe_crc_set_source(dev, pipe, source);
3802}
3803
bd9db02f
DL		 3804static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3805 size_t len, loff_t *offp)
926321d5
DV		 3806{
3807 struct seq_file *m = file->private_data;
3808 struct drm_device *dev = m->private;
3809 char *tmpbuf;
3810 int ret;
3811
3812 if (len == 0)
3813 return 0;
3814
3815 if (len > PAGE_SIZE - 1) {
3816 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3817 PAGE_SIZE);
3818 return -E2BIG;
3819 }
3820
3821 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3822 if (!tmpbuf)
3823 return -ENOMEM;
3824
3825 if (copy_from_user(tmpbuf, ubuf, len)) {
3826 ret = -EFAULT;
3827 goto out;
3828 }
3829 tmpbuf[len] = '\0';
3830
bd9db02f 3831 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3832
3833out:
3834 kfree(tmpbuf);
3835 if (ret < 0)
3836 return ret;
3837
3838 *offp += len;
3839 return len;
3840}
3841
bd9db02f 3842static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3843 .owner = THIS_MODULE,
bd9db02f 3844 .open = display_crc_ctl_open,
926321d5
DV		 3845 .read = seq_read,
3846 .llseek = seq_lseek,
3847 .release = single_release,
bd9db02f 3848 .write = display_crc_ctl_write
926321d5
DV		 3849};
3850
97e94b22 3851static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3852{
3853 struct drm_device *dev = m->private;
546c81fd 3854 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3855 int level;
3856
3857 drm_modeset_lock_all(dev);
3858
3859 for (level = 0; level < num_levels; level++) {
3860 unsigned int latency = wm[level];
3861
97e94b22
DL		 3862 /*
3863 * - WM1+ latency values in 0.5us units
3864 * - latencies are in us on gen9
3865 */
3866 if (INTEL_INFO(dev)->gen >= 9)
3867 latency *= 10;
3868 else if (level > 0)
369a1342
VS		 3869 latency *= 5;
3870
3871 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3872 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3873 }
3874
3875 drm_modeset_unlock_all(dev);
3876}
3877
3878static int pri_wm_latency_show(struct seq_file *m, void *data)
3879{
3880 struct drm_device *dev = m->private;
97e94b22
DL		 3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 const uint16_t *latencies;
3883
3884 if (INTEL_INFO(dev)->gen >= 9)
3885 latencies = dev_priv->wm.skl_latency;
3886 else
3887 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3888
97e94b22 3889 wm_latency_show(m, latencies);
369a1342
VS		 3890
3891 return 0;
3892}
3893
3894static int spr_wm_latency_show(struct seq_file *m, void *data)
3895{
3896 struct drm_device *dev = m->private;
97e94b22
DL		 3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898 const uint16_t *latencies;
3899
3900 if (INTEL_INFO(dev)->gen >= 9)
3901 latencies = dev_priv->wm.skl_latency;
3902 else
3903 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3904
97e94b22 3905 wm_latency_show(m, latencies);
369a1342
VS		 3906
3907 return 0;
3908}
3909
3910static int cur_wm_latency_show(struct seq_file *m, void *data)
3911{
3912 struct drm_device *dev = m->private;
97e94b22
DL		 3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 const uint16_t *latencies;
3915
3916 if (INTEL_INFO(dev)->gen >= 9)
3917 latencies = dev_priv->wm.skl_latency;
3918 else
3919 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3920
97e94b22 3921 wm_latency_show(m, latencies);
369a1342
VS		 3922
3923 return 0;
3924}
3925
3926static int pri_wm_latency_open(struct inode *inode, struct file *file)
3927{
3928 struct drm_device *dev = inode->i_private;
3929
9ad0257c 3930 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3931 return -ENODEV;
3932
3933 return single_open(file, pri_wm_latency_show, dev);
3934}
3935
3936static int spr_wm_latency_open(struct inode *inode, struct file *file)
3937{
3938 struct drm_device *dev = inode->i_private;
3939
9ad0257c 3940 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3941 return -ENODEV;
3942
3943 return single_open(file, spr_wm_latency_show, dev);
3944}
3945
3946static int cur_wm_latency_open(struct inode *inode, struct file *file)
3947{
3948 struct drm_device *dev = inode->i_private;
3949
9ad0257c 3950 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3951 return -ENODEV;
3952
3953 return single_open(file, cur_wm_latency_show, dev);
3954}
3955
3956static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3957 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3958{
3959 struct seq_file *m = file->private_data;
3960 struct drm_device *dev = m->private;
97e94b22 3961 uint16_t new[8] = { 0 };
546c81fd 3962 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3963 int level;
3964 int ret;
3965 char tmp[32];
3966
3967 if (len >= sizeof(tmp))
3968 return -EINVAL;
3969
3970 if (copy_from_user(tmp, ubuf, len))
3971 return -EFAULT;
3972
3973 tmp[len] = '\0';
3974
97e94b22
DL		 3975 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3976 &new[0], &new[1], &new[2], &new[3],
3977 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 3978 if (ret != num_levels)
3979 return -EINVAL;
3980
3981 drm_modeset_lock_all(dev);
3982
3983 for (level = 0; level < num_levels; level++)
3984 wm[level] = new[level];
3985
3986 drm_modeset_unlock_all(dev);
3987
3988 return len;
3989}
3990
3991
3992static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3993 size_t len, loff_t *offp)
3994{
3995 struct seq_file *m = file->private_data;
3996 struct drm_device *dev = m->private;
97e94b22
DL		 3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 uint16_t *latencies;
369a1342 3999
97e94b22
DL		 4000 if (INTEL_INFO(dev)->gen >= 9)
4001 latencies = dev_priv->wm.skl_latency;
4002 else
4003 latencies = to_i915(dev)->wm.pri_latency;
4004
4005 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4006}
4007
4008static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4009 size_t len, loff_t *offp)
4010{
4011 struct seq_file *m = file->private_data;
4012 struct drm_device *dev = m->private;
97e94b22
DL		 4013 struct drm_i915_private *dev_priv = dev->dev_private;
4014 uint16_t *latencies;
369a1342 4015
97e94b22
DL		 4016 if (INTEL_INFO(dev)->gen >= 9)
4017 latencies = dev_priv->wm.skl_latency;
4018 else
4019 latencies = to_i915(dev)->wm.spr_latency;
4020
4021 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4022}
4023
4024static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4025 size_t len, loff_t *offp)
4026{
4027 struct seq_file *m = file->private_data;
4028 struct drm_device *dev = m->private;
97e94b22
DL		 4029 struct drm_i915_private *dev_priv = dev->dev_private;
4030 uint16_t *latencies;
4031
4032 if (INTEL_INFO(dev)->gen >= 9)
4033 latencies = dev_priv->wm.skl_latency;
4034 else
4035 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4036
97e94b22 4037 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4038}
4039
4040static const struct file_operations i915_pri_wm_latency_fops = {
4041 .owner = THIS_MODULE,
4042 .open = pri_wm_latency_open,
4043 .read = seq_read,
4044 .llseek = seq_lseek,
4045 .release = single_release,
4046 .write = pri_wm_latency_write
4047};
4048
4049static const struct file_operations i915_spr_wm_latency_fops = {
4050 .owner = THIS_MODULE,
4051 .open = spr_wm_latency_open,
4052 .read = seq_read,
4053 .llseek = seq_lseek,
4054 .release = single_release,
4055 .write = spr_wm_latency_write
4056};
4057
4058static const struct file_operations i915_cur_wm_latency_fops = {
4059 .owner = THIS_MODULE,
4060 .open = cur_wm_latency_open,
4061 .read = seq_read,
4062 .llseek = seq_lseek,
4063 .release = single_release,
4064 .write = cur_wm_latency_write
4065};
4066
647416f9
KC		 4067static int
4068i915_wedged_get(void *data, u64 *val)
f3cd474b 4069{
647416f9 4070 struct drm_device *dev = data;
e277a1f8 4071 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4072
647416f9 4073 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4074
647416f9 4075 return 0;
f3cd474b
CW		 4076}
4077
647416f9
KC		 4078static int
4079i915_wedged_set(void *data, u64 val)
f3cd474b 4080{
647416f9 4081 struct drm_device *dev = data;
d46c0517
ID		 4082 struct drm_i915_private *dev_priv = dev->dev_private;
4083
b8d24a06
MK		 4084 /*
4085 * There is no safeguard against this debugfs entry colliding
4086 * with the hangcheck calling same i915_handle_error() in
4087 * parallel, causing an explosion. For now we assume that the
4088 * test harness is responsible enough not to inject gpu hangs
4089 * while it is writing to 'i915_wedged'
4090 */
4091
4092 if (i915_reset_in_progress(&dev_priv->gpu_error))
4093 return -EAGAIN;
4094
d46c0517 4095 intel_runtime_pm_get(dev_priv);
f3cd474b 4096
58174462
MK		 4097 i915_handle_error(dev, val,
4098 "Manually setting wedged to %llu", val);
d46c0517
ID		 4099
4100 intel_runtime_pm_put(dev_priv);
4101
647416f9 4102 return 0;
f3cd474b
CW		 4103}
4104
647416f9
KC		 4105DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4106 i915_wedged_get, i915_wedged_set,
3a3b4f98 4107 "%llu\n");
f3cd474b 4108
647416f9
KC		 4109static int
4110i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4111{
647416f9 4112 struct drm_device *dev = data;
e277a1f8 4113 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4114
647416f9 4115 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4116
647416f9 4117 return 0;
e5eb3d63
DV		 4118}
4119
647416f9
KC		 4120static int
4121i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4122{
647416f9 4123 struct drm_device *dev = data;
e5eb3d63 4124 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4125 int ret;
e5eb3d63 4126
647416f9 4127 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4128
22bcfc6a
DV		 4129 ret = mutex_lock_interruptible(&dev->struct_mutex);
4130 if (ret)
4131 return ret;
4132
99584db3 4133 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4134 mutex_unlock(&dev->struct_mutex);
4135
647416f9 4136 return 0;
e5eb3d63
DV		 4137}
4138
647416f9
KC		 4139DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4140 i915_ring_stop_get, i915_ring_stop_set,
4141 "0x%08llx\n");
d5442303 4142
094f9a54
CW		 4143static int
4144i915_ring_missed_irq_get(void *data, u64 *val)
4145{
4146 struct drm_device *dev = data;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148
4149 *val = dev_priv->gpu_error.missed_irq_rings;
4150 return 0;
4151}
4152
4153static int
4154i915_ring_missed_irq_set(void *data, u64 val)
4155{
4156 struct drm_device *dev = data;
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 int ret;
4159
4160 /* Lock against concurrent debugfs callers */
4161 ret = mutex_lock_interruptible(&dev->struct_mutex);
4162 if (ret)
4163 return ret;
4164 dev_priv->gpu_error.missed_irq_rings = val;
4165 mutex_unlock(&dev->struct_mutex);
4166
4167 return 0;
4168}
4169
4170DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4171 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4172 "0x%08llx\n");
4173
4174static int
4175i915_ring_test_irq_get(void *data, u64 *val)
4176{
4177 struct drm_device *dev = data;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179
4180 *val = dev_priv->gpu_error.test_irq_rings;
4181
4182 return 0;
4183}
4184
4185static int
4186i915_ring_test_irq_set(void *data, u64 val)
4187{
4188 struct drm_device *dev = data;
4189 struct drm_i915_private *dev_priv = dev->dev_private;
4190 int ret;
4191
4192 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4193
4194 /* Lock against concurrent debugfs callers */
4195 ret = mutex_lock_interruptible(&dev->struct_mutex);
4196 if (ret)
4197 return ret;
4198
4199 dev_priv->gpu_error.test_irq_rings = val;
4200 mutex_unlock(&dev->struct_mutex);
4201
4202 return 0;
4203}
4204
4205DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4206 i915_ring_test_irq_get, i915_ring_test_irq_set,
4207 "0x%08llx\n");
4208
dd624afd
CW		 4209#define DROP_UNBOUND 0x1
4210#define DROP_BOUND 0x2
4211#define DROP_RETIRE 0x4
4212#define DROP_ACTIVE 0x8
4213#define DROP_ALL (DROP_UNBOUND | \
4214 DROP_BOUND | \
4215 DROP_RETIRE | \
4216 DROP_ACTIVE)
647416f9
KC		 4217static int
4218i915_drop_caches_get(void *data, u64 *val)
dd624afd 4219{
647416f9 4220 *val = DROP_ALL;
dd624afd 4221
647416f9 4222 return 0;
dd624afd
CW		 4223}
4224
647416f9
KC		 4225static int
4226i915_drop_caches_set(void *data, u64 val)
dd624afd 4227{
647416f9 4228 struct drm_device *dev = data;
dd624afd 4229 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4230 int ret;
dd624afd 4231
2f9fe5ff 4232 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4233
4234 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4235 * on ioctls on -EAGAIN. */
4236 ret = mutex_lock_interruptible(&dev->struct_mutex);
4237 if (ret)
4238 return ret;
4239
4240 if (val & DROP_ACTIVE) {
4241 ret = i915_gpu_idle(dev);
4242 if (ret)
4243 goto unlock;
4244 }
4245
4246 if (val & (DROP_RETIRE | DROP_ACTIVE))
4247 i915_gem_retire_requests(dev);
4248
21ab4e74
CW		 4249 if (val & DROP_BOUND)
4250 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4251
21ab4e74
CW		 4252 if (val & DROP_UNBOUND)
4253 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4254
4255unlock:
4256 mutex_unlock(&dev->struct_mutex);
4257
647416f9 4258 return ret;
dd624afd
CW		 4259}
4260
647416f9
KC		 4261DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4262 i915_drop_caches_get, i915_drop_caches_set,
4263 "0x%08llx\n");
dd624afd 4264
647416f9
KC		 4265static int
4266i915_max_freq_get(void *data, u64 *val)
358733e9 4267{
647416f9 4268 struct drm_device *dev = data;
e277a1f8 4269 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4270 int ret;
004777cb 4271
daa3afb2 4272 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4273 return -ENODEV;
4274
5c9669ce
TR		 4275 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4276
4fc688ce 4277 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4278 if (ret)
4279 return ret;
358733e9 4280
7c59a9c1 4281 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4282 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4283
647416f9 4284 return 0;
358733e9
JB		 4285}
4286
647416f9
KC		 4287static int
4288i915_max_freq_set(void *data, u64 val)
358733e9 4289{
647416f9 4290 struct drm_device *dev = data;
358733e9 4291 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4292 u32 hw_max, hw_min;
647416f9 4293 int ret;
004777cb 4294
daa3afb2 4295 if (INTEL_INFO(dev)->gen < 6)
004777cb 4296 return -ENODEV;
358733e9 4297
5c9669ce
TR		 4298 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4299
647416f9 4300 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4301
4fc688ce 4302 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4303 if (ret)
4304 return ret;
4305
358733e9
JB		 4306 /*
4307 * Turbo will still be enabled, but won't go above the set value.
4308 */
bc4d91f6 4309 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4310
bc4d91f6
AG		 4311 hw_max = dev_priv->rps.max_freq;
4312 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4313
b39fb297 4314 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4315 mutex_unlock(&dev_priv->rps.hw_lock);
4316 return -EINVAL;
0a073b84
JB		 4317 }
4318
b39fb297 4319 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4320
ffe02b40 4321 intel_set_rps(dev, val);
dd0a1aa1 4322
4fc688ce 4323 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4324
647416f9 4325 return 0;
358733e9
JB		 4326}
4327
647416f9
KC		 4328DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4329 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4330 "%llu\n");
358733e9 4331
647416f9
KC		 4332static int
4333i915_min_freq_get(void *data, u64 *val)
1523c310 4334{
647416f9 4335 struct drm_device *dev = data;
e277a1f8 4336 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4337 int ret;
004777cb 4338
daa3afb2 4339 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4340 return -ENODEV;
4341
5c9669ce
TR		 4342 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4343
4fc688ce 4344 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4345 if (ret)
4346 return ret;
1523c310 4347
7c59a9c1 4348 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4349 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4350
647416f9 4351 return 0;
1523c310
JB		 4352}
4353
647416f9
KC		 4354static int
4355i915_min_freq_set(void *data, u64 val)
1523c310 4356{
647416f9 4357 struct drm_device *dev = data;
1523c310 4358 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4359 u32 hw_max, hw_min;
647416f9 4360 int ret;
004777cb 4361
daa3afb2 4362 if (INTEL_INFO(dev)->gen < 6)
004777cb 4363 return -ENODEV;
1523c310 4364
5c9669ce
TR		 4365 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4366
647416f9 4367 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4368
4fc688ce 4369 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4370 if (ret)
4371 return ret;
4372
1523c310
JB		 4373 /*
4374 * Turbo will still be enabled, but won't go below the set value.
4375 */
bc4d91f6 4376 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4377
bc4d91f6
AG		 4378 hw_max = dev_priv->rps.max_freq;
4379 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4380
b39fb297 4381 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4382 mutex_unlock(&dev_priv->rps.hw_lock);
4383 return -EINVAL;
0a073b84 4384 }
dd0a1aa1 4385
b39fb297 4386 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4387
ffe02b40 4388 intel_set_rps(dev, val);
dd0a1aa1 4389
4fc688ce 4390 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4391
647416f9 4392 return 0;
1523c310
JB		 4393}
4394
647416f9
KC		 4395DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4396 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4397 "%llu\n");
1523c310 4398
647416f9
KC		 4399static int
4400i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4401{
647416f9 4402 struct drm_device *dev = data;
e277a1f8 4403 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4404 u32 snpcr;
647416f9 4405 int ret;
07b7ddd9 4406
004777cb
DV		 4407 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4408 return -ENODEV;
4409
22bcfc6a
DV		 4410 ret = mutex_lock_interruptible(&dev->struct_mutex);
4411 if (ret)
4412 return ret;
c8c8fb33 4413 intel_runtime_pm_get(dev_priv);
22bcfc6a 4414
07b7ddd9 4415 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4416
4417 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4418 mutex_unlock(&dev_priv->dev->struct_mutex);
4419
647416f9 4420 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4421
647416f9 4422 return 0;
07b7ddd9
JB		 4423}
4424
647416f9
KC		 4425static int
4426i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4427{
647416f9 4428 struct drm_device *dev = data;
07b7ddd9 4429 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4430 u32 snpcr;
07b7ddd9 4431
004777cb
DV		 4432 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4433 return -ENODEV;
4434
647416f9 4435 if (val > 3)
07b7ddd9
JB		 4436 return -EINVAL;
4437
c8c8fb33 4438 intel_runtime_pm_get(dev_priv);
647416f9 4439 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4440
4441 /* Update the cache sharing policy here as well */
4442 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4443 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4444 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4445 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4446
c8c8fb33 4447 intel_runtime_pm_put(dev_priv);
647416f9 4448 return 0;
07b7ddd9
JB		 4449}
4450
647416f9
KC		 4451DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4452 i915_cache_sharing_get, i915_cache_sharing_set,
4453 "%llu\n");
07b7ddd9 4454
3873218f
JM		 4455static int i915_sseu_status(struct seq_file *m, void *unused)
4456{
4457 struct drm_info_node *node = (struct drm_info_node *) m->private;
4458 struct drm_device *dev = node->minor->dev;
7f992aba
JM		 4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
3873218f
JM		 4461
4462 if (INTEL_INFO(dev)->gen < 9)
4463 return -ENODEV;
4464
4465 seq_puts(m, "SSEU Device Info\n");
4466 seq_printf(m, " Available Slice Total: %u\n",
4467 INTEL_INFO(dev)->slice_total);
4468 seq_printf(m, " Available Subslice Total: %u\n",
4469 INTEL_INFO(dev)->subslice_total);
4470 seq_printf(m, " Available Subslice Per Slice: %u\n",
4471 INTEL_INFO(dev)->subslice_per_slice);
4472 seq_printf(m, " Available EU Total: %u\n",
4473 INTEL_INFO(dev)->eu_total);
4474 seq_printf(m, " Available EU Per Subslice: %u\n",
4475 INTEL_INFO(dev)->eu_per_subslice);
4476 seq_printf(m, " Has Slice Power Gating: %s\n",
4477 yesno(INTEL_INFO(dev)->has_slice_pg));
4478 seq_printf(m, " Has Subslice Power Gating: %s\n",
4479 yesno(INTEL_INFO(dev)->has_subslice_pg));
4480 seq_printf(m, " Has EU Power Gating: %s\n",
4481 yesno(INTEL_INFO(dev)->has_eu_pg));
4482
7f992aba
JM		 4483 seq_puts(m, "SSEU Device Status\n");
4484 if (IS_SKYLAKE(dev)) {
4485 const int s_max = 3, ss_max = 4;
4486 int s, ss;
4487 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4488
4489 s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
4490 s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
4491 s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
4492 eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
4493 eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
4494 eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
4495 eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
4496 eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
4497 eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
4498 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4499 GEN9_PGCTL_SSA_EU19_ACK |
4500 GEN9_PGCTL_SSA_EU210_ACK |
4501 GEN9_PGCTL_SSA_EU311_ACK;
4502 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4503 GEN9_PGCTL_SSB_EU19_ACK |
4504 GEN9_PGCTL_SSB_EU210_ACK |
4505 GEN9_PGCTL_SSB_EU311_ACK;
4506
4507 for (s = 0; s < s_max; s++) {
4508 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4509 /* skip disabled slice */
4510 continue;
4511
4512 s_tot++;
4513 ss_per = INTEL_INFO(dev)->subslice_per_slice;
4514 ss_tot += ss_per;
4515 for (ss = 0; ss < ss_max; ss++) {
4516 unsigned int eu_cnt;
4517
4518 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4519 eu_mask[ss%2]);
4520 eu_tot += eu_cnt;
4521 eu_per = max(eu_per, eu_cnt);
4522 }
4523 }
4524 }
4525 seq_printf(m, " Enabled Slice Total: %u\n", s_tot);
4526 seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot);
4527 seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per);
4528 seq_printf(m, " Enabled EU Total: %u\n", eu_tot);
4529 seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per);
4530
3873218f
JM		 4531 return 0;
4532}
4533
6d794d42
BW		 4534static int i915_forcewake_open(struct inode *inode, struct file *file)
4535{
4536 struct drm_device *dev = inode->i_private;
4537 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4538
075edca4 4539 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4540 return 0;
4541
6daccb0b 4542 intel_runtime_pm_get(dev_priv);
59bad947 4543 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4544
4545 return 0;
4546}
4547
c43b5634 4548static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4549{
4550 struct drm_device *dev = inode->i_private;
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552
075edca4 4553 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4554 return 0;
4555
59bad947 4556 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4557 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4558
4559 return 0;
4560}
4561
4562static const struct file_operations i915_forcewake_fops = {
4563 .owner = THIS_MODULE,
4564 .open = i915_forcewake_open,
4565 .release = i915_forcewake_release,
4566};
4567
4568static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4569{
4570 struct drm_device *dev = minor->dev;
4571 struct dentry *ent;
4572
4573 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4574 S_IRUSR,
6d794d42
BW		 4575 root, dev,
4576 &i915_forcewake_fops);
f3c5fe97
WY		 4577 if (!ent)
4578 return -ENOMEM;
6d794d42 4579
8eb57294 4580 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4581}
4582
6a9c308d
DV		 4583static int i915_debugfs_create(struct dentry *root,
4584 struct drm_minor *minor,
4585 const char *name,
4586 const struct file_operations *fops)
07b7ddd9
JB		 4587{
4588 struct drm_device *dev = minor->dev;
4589 struct dentry *ent;
4590
6a9c308d 4591 ent = debugfs_create_file(name,
07b7ddd9
JB		 4592 S_IRUGO | S_IWUSR,
4593 root, dev,
6a9c308d 4594 fops);
f3c5fe97
WY		 4595 if (!ent)
4596 return -ENOMEM;
07b7ddd9 4597
6a9c308d 4598 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4599}
4600
06c5bf8c 4601static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4602 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4603 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4604 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4605 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4606 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4607 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4608 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4609 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4610 {"i915_gem_request", i915_gem_request_info, 0},
4611 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4612 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4613 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4614 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4615 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4616 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4617 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4618 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 4619 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 4620 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 4621 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4622 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4623 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4624 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4625 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4626 {"i915_sr_status", i915_sr_status, 0},
44834a67 4627 {"i915_opregion", i915_opregion, 0},
37811fcc 4628 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4629 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4630 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4631 {"i915_execlists", i915_execlists, 0},
f65367b5 4632 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 4633 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4634 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4635 {"i915_llc", i915_llc, 0},
e91fd8c6 4636 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4637 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4638 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4639 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4640 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4641 {"i915_display_info", i915_display_info, 0},
e04934cf 4642 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4643 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4644 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4645 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4646 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 4647 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 4648 {"i915_drrs_status", i915_drrs_status, 0},
2017263e 4649};
27c202ad 4650#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4651
06c5bf8c 4652static const struct i915_debugfs_files {
34b9674c
DV		 4653 const char *name;
4654 const struct file_operations *fops;
4655} i915_debugfs_files[] = {
4656 {"i915_wedged", &i915_wedged_fops},
4657 {"i915_max_freq", &i915_max_freq_fops},
4658 {"i915_min_freq", &i915_min_freq_fops},
4659 {"i915_cache_sharing", &i915_cache_sharing_fops},
4660 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4661 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4662 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4663 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4664 {"i915_error_state", &i915_error_state_fops},
4665 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4666 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4667 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4668 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4669 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4670 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4671};
4672
07144428
DL		 4673void intel_display_crc_init(struct drm_device *dev)
4674{
4675 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4676 enum pipe pipe;
07144428 4677
055e393f 4678 for_each_pipe(dev_priv, pipe) {
b378360e 4679 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4680
d538bbdf
DL		 4681 pipe_crc->opened = false;
4682 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4683 init_waitqueue_head(&pipe_crc->wq);
4684 }
4685}
4686
27c202ad 4687int i915_debugfs_init(struct drm_minor *minor)
2017263e 4688{
34b9674c 4689 int ret, i;
f3cd474b 4690
6d794d42 4691 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4692 if (ret)
4693 return ret;
6a9c308d 4694
07144428
DL		 4695 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4696 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4697 if (ret)
4698 return ret;
4699 }
4700
34b9674c
DV		 4701 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4702 ret = i915_debugfs_create(minor->debugfs_root, minor,
4703 i915_debugfs_files[i].name,
4704 i915_debugfs_files[i].fops);
4705 if (ret)
4706 return ret;
4707 }
40633219 4708
27c202ad
BG		 4709 return drm_debugfs_create_files(i915_debugfs_list,
4710 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4711 minor->debugfs_root, minor);
4712}
4713
27c202ad 4714void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4715{
34b9674c
DV		 4716 int i;
4717
27c202ad
BG		 4718 drm_debugfs_remove_files(i915_debugfs_list,
4719 I915_DEBUGFS_ENTRIES, minor);
07144428 4720
6d794d42
BW		 4721 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4722 1, minor);
07144428 4723
e309a997 4724 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4725 struct drm_info_list *info_list =
4726 (struct drm_info_list *)&i915_pipe_crc_data[i];
4727
4728 drm_debugfs_remove_files(info_list, 1, minor);
4729 }
4730
34b9674c
DV		 4731 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4732 struct drm_info_list *info_list =
4733 (struct drm_info_list *) i915_debugfs_files[i].fops;
4734
4735 drm_debugfs_remove_files(info_list, 1, minor);
4736 }
2017263e 4737}
Linux 6.x block layer and io_uring tree(s)