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drm/i915: Add intel_get_crtc_scanline()
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 173}
174
3ccfd19d
BW		 175static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
176{
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
179 seq_putc(m, ' ');
180}
181
433e12f7 182static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 183{
184 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
2017263e 187 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 190 struct i915_vma *vma;
8f2480fb
CW		 191 size_t total_obj_size, total_gtt_size;
192 int count, ret;
de227ef0
CW		 193
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
195 if (ret)
196 return ret;
2017263e 197
ca191b13 198 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 199 switch (list) {
200 case ACTIVE_LIST:
267f0c90 201 seq_puts(m, "Active:\n");
5cef07e1 202 head = &vm->active_list;
433e12f7
BG		 203 break;
204 case INACTIVE_LIST:
267f0c90 205 seq_puts(m, "Inactive:\n");
5cef07e1 206 head = &vm->inactive_list;
433e12f7 207 break;
433e12f7 208 default:
de227ef0
CW		 209 mutex_unlock(&dev->struct_mutex);
210 return -EINVAL;
2017263e 211 }
2017263e 212
8f2480fb 213 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 214 list_for_each_entry(vma, head, mm_list) {
215 seq_printf(m, " ");
216 describe_obj(m, vma->obj);
217 seq_printf(m, "\n");
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
8f2480fb 220 count++;
2017263e 221 }
de227ef0 222 mutex_unlock(&dev->struct_mutex);
5e118f41 223
8f2480fb
CW		 224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
2017263e
BG		 226 return 0;
227}
228
6d2b8885
CW		 229static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
231{
232 struct drm_i915_gem_object *a =
b25cb2f8 233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 234 struct drm_i915_gem_object *b =
b25cb2f8 235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 236
237 return a->stolen->start - b->stolen->start;
238}
239
240static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
241{
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
247 LIST_HEAD(stolen);
248 int count, ret;
249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
252 return ret;
253
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
257 continue;
258
b25cb2f8 259 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 260
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
263 count++;
264 }
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
b25cb2f8 269 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 270
271 total_obj_size += obj->base.size;
272 count++;
273 }
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
b25cb2f8 277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 278 seq_puts(m, " ");
279 describe_obj(m, obj);
280 seq_putc(m, '\n');
b25cb2f8 281 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 282 }
283 mutex_unlock(&dev->struct_mutex);
284
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
287 return 0;
288}
289
6299f992
CW		 290#define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
f343c5f6 292 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 293 ++count; \
294 if (obj->map_and_fenceable) { \
f343c5f6 295 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 296 ++mappable_count; \
297 } \
298 } \
0206e353 299} while (0)
6299f992 300
2db8e9d6 301struct file_stats {
6313c204 302 struct drm_i915_file_private *file_priv;
2db8e9d6 303 int count;
c67a17e9
CW		 304 size_t total, unbound;
305 size_t global, shared;
306 size_t active, inactive;
2db8e9d6
CW		 307};
308
309static int per_file_stats(int id, void *ptr, void *data)
310{
311 struct drm_i915_gem_object *obj = ptr;
312 struct file_stats *stats = data;
6313c204 313 struct i915_vma *vma;
2db8e9d6
CW		 314
315 stats->count++;
316 stats->total += obj->base.size;
317
c67a17e9
CW		 318 if (obj->base.name || obj->base.dma_buf)
319 stats->shared += obj->base.size;
320
6313c204
CW		 321 if (USES_FULL_PPGTT(obj->base.dev)) {
322 list_for_each_entry(vma, &obj->vma_list, vma_link) {
323 struct i915_hw_ppgtt *ppgtt;
324
325 if (!drm_mm_node_allocated(&vma->node))
326 continue;
327
328 if (i915_is_ggtt(vma->vm)) {
329 stats->global += obj->base.size;
330 continue;
331 }
332
333 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
334 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
335 continue;
336
337 if (obj->ring) /* XXX per-vma statistic */
338 stats->active += obj->base.size;
339 else
340 stats->inactive += obj->base.size;
341
342 return 0;
343 }
2db8e9d6 344 } else {
6313c204
CW		 345 if (i915_gem_obj_ggtt_bound(obj)) {
346 stats->global += obj->base.size;
347 if (obj->ring)
348 stats->active += obj->base.size;
349 else
350 stats->inactive += obj->base.size;
351 return 0;
352 }
2db8e9d6
CW		 353 }
354
6313c204
CW		 355 if (!list_empty(&obj->global_list))
356 stats->unbound += obj->base.size;
357
2db8e9d6
CW		 358 return 0;
359}
360
ca191b13
BW		 361#define count_vmas(list, member) do { \
362 list_for_each_entry(vma, list, member) { \
363 size += i915_gem_obj_ggtt_size(vma->obj); \
364 ++count; \
365 if (vma->obj->map_and_fenceable) { \
366 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
367 ++mappable_count; \
368 } \
369 } \
370} while (0)
371
372static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 373{
374 struct drm_info_node *node = (struct drm_info_node *) m->private;
375 struct drm_device *dev = node->minor->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 377 u32 count, mappable_count, purgeable_count;
378 size_t size, mappable_size, purgeable_size;
6299f992 379 struct drm_i915_gem_object *obj;
5cef07e1 380 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 381 struct drm_file *file;
ca191b13 382 struct i915_vma *vma;
73aa808f
CW		 383 int ret;
384
385 ret = mutex_lock_interruptible(&dev->struct_mutex);
386 if (ret)
387 return ret;
388
6299f992
CW		 389 seq_printf(m, "%u objects, %zu bytes\n",
390 dev_priv->mm.object_count,
391 dev_priv->mm.object_memory);
392
393 size = count = mappable_size = mappable_count = 0;
35c20a60 394 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 395 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
396 count, mappable_count, size, mappable_size);
397
398 size = count = mappable_size = mappable_count = 0;
ca191b13 399 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 400 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
401 count, mappable_count, size, mappable_size);
402
6299f992 403 size = count = mappable_size = mappable_count = 0;
ca191b13 404 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 405 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
406 count, mappable_count, size, mappable_size);
407
b7abb714 408 size = count = purgeable_size = purgeable_count = 0;
35c20a60 409 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 410 size += obj->base.size, ++count;
b7abb714
CW		 411 if (obj->madv == I915_MADV_DONTNEED)
412 purgeable_size += obj->base.size, ++purgeable_count;
413 }
6c085a72
CW		 414 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
415
6299f992 416 size = count = mappable_size = mappable_count = 0;
35c20a60 417 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 418 if (obj->fault_mappable) {
f343c5f6 419 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 420 ++count;
421 }
422 if (obj->pin_mappable) {
f343c5f6 423 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 424 ++mappable_count;
425 }
b7abb714
CW		 426 if (obj->madv == I915_MADV_DONTNEED) {
427 purgeable_size += obj->base.size;
428 ++purgeable_count;
429 }
6299f992 430 }
b7abb714
CW		 431 seq_printf(m, "%u purgeable objects, %zu bytes\n",
432 purgeable_count, purgeable_size);
6299f992
CW		 433 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
434 mappable_count, mappable_size);
435 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
436 count, size);
437
93d18799 438 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 439 dev_priv->gtt.base.total,
440 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 441
267f0c90 442 seq_putc(m, '\n');
2db8e9d6
CW		 443 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
444 struct file_stats stats;
3ec2f427 445 struct task_struct *task;
2db8e9d6
CW		 446
447 memset(&stats, 0, sizeof(stats));
6313c204 448 stats.file_priv = file->driver_priv;
2db8e9d6 449 idr_for_each(&file->object_idr, per_file_stats, &stats);
3ec2f427
TH		 450 /*
451 * Although we have a valid reference on file->pid, that does
452 * not guarantee that the task_struct who called get_pid() is
453 * still alive (e.g. get_pid(current) => fork() => exit()).
454 * Therefore, we need to protect this ->comm access using RCU.
455 */
456 rcu_read_lock();
457 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 458 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 459 task ? task->comm : "<unknown>",
2db8e9d6
CW		 460 stats.count,
461 stats.total,
462 stats.active,
463 stats.inactive,
6313c204 464 stats.global,
c67a17e9 465 stats.shared,
2db8e9d6 466 stats.unbound);
3ec2f427 467 rcu_read_unlock();
2db8e9d6
CW		 468 }
469
73aa808f
CW		 470 mutex_unlock(&dev->struct_mutex);
471
472 return 0;
473}
474
aee56cff 475static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 476{
477 struct drm_info_node *node = (struct drm_info_node *) m->private;
478 struct drm_device *dev = node->minor->dev;
1b50247a 479 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct drm_i915_gem_object *obj;
482 size_t total_obj_size, total_gtt_size;
483 int count, ret;
484
485 ret = mutex_lock_interruptible(&dev->struct_mutex);
486 if (ret)
487 return ret;
488
489 total_obj_size = total_gtt_size = count = 0;
35c20a60 490 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 491 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 492 continue;
493
267f0c90 494 seq_puts(m, " ");
08c18323 495 describe_obj(m, obj);
267f0c90 496 seq_putc(m, '\n');
08c18323 497 total_obj_size += obj->base.size;
f343c5f6 498 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 499 count++;
500 }
501
502 mutex_unlock(&dev->struct_mutex);
503
504 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
505 count, total_obj_size, total_gtt_size);
506
507 return 0;
508}
509
4e5359cd
SF		 510static int i915_gem_pageflip_info(struct seq_file *m, void *data)
511{
512 struct drm_info_node *node = (struct drm_info_node *) m->private;
513 struct drm_device *dev = node->minor->dev;
514 unsigned long flags;
515 struct intel_crtc *crtc;
516
517 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 518 const char pipe = pipe_name(crtc->pipe);
519 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 520 struct intel_unpin_work *work;
521
522 spin_lock_irqsave(&dev->event_lock, flags);
523 work = crtc->unpin_work;
524 if (work == NULL) {
9db4a9c7 525 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 526 pipe, plane);
527 } else {
e7d841ca 528 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 529 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 530 pipe, plane);
531 } else {
9db4a9c7 532 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 533 pipe, plane);
534 }
535 if (work->enable_stall_check)
267f0c90 536 seq_puts(m, "Stall check enabled, ");
4e5359cd 537 else
267f0c90 538 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 539 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 540
541 if (work->old_fb_obj) {
05394f39
CW		 542 struct drm_i915_gem_object *obj = work->old_fb_obj;
543 if (obj)
f343c5f6
BW		 544 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
545 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 546 }
547 if (work->pending_flip_obj) {
05394f39
CW		 548 struct drm_i915_gem_object *obj = work->pending_flip_obj;
549 if (obj)
f343c5f6
BW		 550 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
551 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 552 }
553 }
554 spin_unlock_irqrestore(&dev->event_lock, flags);
555 }
556
557 return 0;
558}
559
2017263e
BG		 560static int i915_gem_request_info(struct seq_file *m, void *data)
561{
562 struct drm_info_node *node = (struct drm_info_node *) m->private;
563 struct drm_device *dev = node->minor->dev;
e277a1f8 564 struct drm_i915_private *dev_priv = dev->dev_private;
a2c7f6fd 565 struct intel_ring_buffer *ring;
2017263e 566 struct drm_i915_gem_request *gem_request;
a2c7f6fd 567 int ret, count, i;
de227ef0
CW		 568
569 ret = mutex_lock_interruptible(&dev->struct_mutex);
570 if (ret)
571 return ret;
2017263e 572
c2c347a9 573 count = 0;
a2c7f6fd
CW		 574 for_each_ring(ring, dev_priv, i) {
575 if (list_empty(&ring->request_list))
576 continue;
577
578 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 579 list_for_each_entry(gem_request,
a2c7f6fd 580 &ring->request_list,
c2c347a9
CW		 581 list) {
582 seq_printf(m, " %d @ %d\n",
583 gem_request->seqno,
584 (int) (jiffies - gem_request->emitted_jiffies));
585 }
586 count++;
2017263e 587 }
de227ef0
CW		 588 mutex_unlock(&dev->struct_mutex);
589
c2c347a9 590 if (count == 0)
267f0c90 591 seq_puts(m, "No requests\n");
c2c347a9 592
2017263e
BG		 593 return 0;
594}
595
b2223497
CW		 596static void i915_ring_seqno_info(struct seq_file *m,
597 struct intel_ring_buffer *ring)
598{
599 if (ring->get_seqno) {
43a7b924 600 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 601 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 602 }
603}
604
2017263e
BG		 605static int i915_gem_seqno_info(struct seq_file *m, void *data)
606{
607 struct drm_info_node *node = (struct drm_info_node *) m->private;
608 struct drm_device *dev = node->minor->dev;
e277a1f8 609 struct drm_i915_private *dev_priv = dev->dev_private;
a2c7f6fd 610 struct intel_ring_buffer *ring;
1ec14ad3 611 int ret, i;
de227ef0
CW		 612
613 ret = mutex_lock_interruptible(&dev->struct_mutex);
614 if (ret)
615 return ret;
c8c8fb33 616 intel_runtime_pm_get(dev_priv);
2017263e 617
a2c7f6fd
CW		 618 for_each_ring(ring, dev_priv, i)
619 i915_ring_seqno_info(m, ring);
de227ef0 620
c8c8fb33 621 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 622 mutex_unlock(&dev->struct_mutex);
623
2017263e
BG		 624 return 0;
625}
626
627
628static int i915_interrupt_info(struct seq_file *m, void *data)
629{
630 struct drm_info_node *node = (struct drm_info_node *) m->private;
631 struct drm_device *dev = node->minor->dev;
e277a1f8 632 struct drm_i915_private *dev_priv = dev->dev_private;
a2c7f6fd 633 struct intel_ring_buffer *ring;
9db4a9c7 634 int ret, i, pipe;
de227ef0
CW		 635
636 ret = mutex_lock_interruptible(&dev->struct_mutex);
637 if (ret)
638 return ret;
c8c8fb33 639 intel_runtime_pm_get(dev_priv);
2017263e 640
a123f157 641 if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 642 seq_printf(m, "Master Interrupt Control:\t%08x\n",
643 I915_READ(GEN8_MASTER_IRQ));
644
645 for (i = 0; i < 4; i++) {
646 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
647 i, I915_READ(GEN8_GT_IMR(i)));
648 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
649 i, I915_READ(GEN8_GT_IIR(i)));
650 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
651 i, I915_READ(GEN8_GT_IER(i)));
652 }
653
07d27e20 654 for_each_pipe(pipe) {
a123f157 655 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 656 pipe_name(pipe),
657 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 658 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 659 pipe_name(pipe),
660 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 661 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 662 pipe_name(pipe),
663 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 664 }
665
666 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
667 I915_READ(GEN8_DE_PORT_IMR));
668 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
669 I915_READ(GEN8_DE_PORT_IIR));
670 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
671 I915_READ(GEN8_DE_PORT_IER));
672
673 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
674 I915_READ(GEN8_DE_MISC_IMR));
675 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
676 I915_READ(GEN8_DE_MISC_IIR));
677 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
678 I915_READ(GEN8_DE_MISC_IER));
679
680 seq_printf(m, "PCU interrupt mask:\t%08x\n",
681 I915_READ(GEN8_PCU_IMR));
682 seq_printf(m, "PCU interrupt identity:\t%08x\n",
683 I915_READ(GEN8_PCU_IIR));
684 seq_printf(m, "PCU interrupt enable:\t%08x\n",
685 I915_READ(GEN8_PCU_IER));
686 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 687 seq_printf(m, "Display IER:\t%08x\n",
688 I915_READ(VLV_IER));
689 seq_printf(m, "Display IIR:\t%08x\n",
690 I915_READ(VLV_IIR));
691 seq_printf(m, "Display IIR_RW:\t%08x\n",
692 I915_READ(VLV_IIR_RW));
693 seq_printf(m, "Display IMR:\t%08x\n",
694 I915_READ(VLV_IMR));
695 for_each_pipe(pipe)
696 seq_printf(m, "Pipe %c stat:\t%08x\n",
697 pipe_name(pipe),
698 I915_READ(PIPESTAT(pipe)));
699
700 seq_printf(m, "Master IER:\t%08x\n",
701 I915_READ(VLV_MASTER_IER));
702
703 seq_printf(m, "Render IER:\t%08x\n",
704 I915_READ(GTIER));
705 seq_printf(m, "Render IIR:\t%08x\n",
706 I915_READ(GTIIR));
707 seq_printf(m, "Render IMR:\t%08x\n",
708 I915_READ(GTIMR));
709
710 seq_printf(m, "PM IER:\t\t%08x\n",
711 I915_READ(GEN6_PMIER));
712 seq_printf(m, "PM IIR:\t\t%08x\n",
713 I915_READ(GEN6_PMIIR));
714 seq_printf(m, "PM IMR:\t\t%08x\n",
715 I915_READ(GEN6_PMIMR));
716
717 seq_printf(m, "Port hotplug:\t%08x\n",
718 I915_READ(PORT_HOTPLUG_EN));
719 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
720 I915_READ(VLV_DPFLIPSTAT));
721 seq_printf(m, "DPINVGTT:\t%08x\n",
722 I915_READ(DPINVGTT));
723
724 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 725 seq_printf(m, "Interrupt enable: %08x\n",
726 I915_READ(IER));
727 seq_printf(m, "Interrupt identity: %08x\n",
728 I915_READ(IIR));
729 seq_printf(m, "Interrupt mask: %08x\n",
730 I915_READ(IMR));
9db4a9c7
JB		 731 for_each_pipe(pipe)
732 seq_printf(m, "Pipe %c stat: %08x\n",
733 pipe_name(pipe),
734 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 735 } else {
736 seq_printf(m, "North Display Interrupt enable: %08x\n",
737 I915_READ(DEIER));
738 seq_printf(m, "North Display Interrupt identity: %08x\n",
739 I915_READ(DEIIR));
740 seq_printf(m, "North Display Interrupt mask: %08x\n",
741 I915_READ(DEIMR));
742 seq_printf(m, "South Display Interrupt enable: %08x\n",
743 I915_READ(SDEIER));
744 seq_printf(m, "South Display Interrupt identity: %08x\n",
745 I915_READ(SDEIIR));
746 seq_printf(m, "South Display Interrupt mask: %08x\n",
747 I915_READ(SDEIMR));
748 seq_printf(m, "Graphics Interrupt enable: %08x\n",
749 I915_READ(GTIER));
750 seq_printf(m, "Graphics Interrupt identity: %08x\n",
751 I915_READ(GTIIR));
752 seq_printf(m, "Graphics Interrupt mask: %08x\n",
753 I915_READ(GTIMR));
754 }
a2c7f6fd 755 for_each_ring(ring, dev_priv, i) {
a123f157 756 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 757 seq_printf(m,
758 "Graphics Interrupt mask (%s): %08x\n",
759 ring->name, I915_READ_IMR(ring));
9862e600 760 }
a2c7f6fd 761 i915_ring_seqno_info(m, ring);
9862e600 762 }
c8c8fb33 763 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 764 mutex_unlock(&dev->struct_mutex);
765
2017263e
BG		 766 return 0;
767}
768
a6172a80
CW		 769static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
770{
771 struct drm_info_node *node = (struct drm_info_node *) m->private;
772 struct drm_device *dev = node->minor->dev;
e277a1f8 773 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 774 int i, ret;
775
776 ret = mutex_lock_interruptible(&dev->struct_mutex);
777 if (ret)
778 return ret;
a6172a80
CW		 779
780 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
781 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
782 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 783 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 784
6c085a72
CW		 785 seq_printf(m, "Fence %d, pin count = %d, object = ",
786 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 787 if (obj == NULL)
267f0c90 788 seq_puts(m, "unused");
c2c347a9 789 else
05394f39 790 describe_obj(m, obj);
267f0c90 791 seq_putc(m, '\n');
a6172a80
CW		 792 }
793
05394f39 794 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 795 return 0;
796}
797
2017263e
BG		 798static int i915_hws_info(struct seq_file *m, void *data)
799{
800 struct drm_info_node *node = (struct drm_info_node *) m->private;
801 struct drm_device *dev = node->minor->dev;
e277a1f8 802 struct drm_i915_private *dev_priv = dev->dev_private;
4066c0ae 803 struct intel_ring_buffer *ring;
1a240d4d 804 const u32 *hws;
4066c0ae
CW		 805 int i;
806
1ec14ad3 807 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 808 hws = ring->status_page.page_addr;
2017263e
BG		 809 if (hws == NULL)
810 return 0;
811
812 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
813 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
814 i * 4,
815 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
816 }
817 return 0;
818}
819
d5442303
DV		 820static ssize_t
821i915_error_state_write(struct file *filp,
822 const char __user *ubuf,
823 size_t cnt,
824 loff_t *ppos)
825{
edc3d884 826 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 827 struct drm_device *dev = error_priv->dev;
22bcfc6a 828 int ret;
d5442303
DV		 829
830 DRM_DEBUG_DRIVER("Resetting error state\n");
831
22bcfc6a
DV		 832 ret = mutex_lock_interruptible(&dev->struct_mutex);
833 if (ret)
834 return ret;
835
d5442303
DV		 836 i915_destroy_error_state(dev);
837 mutex_unlock(&dev->struct_mutex);
838
839 return cnt;
840}
841
842static int i915_error_state_open(struct inode *inode, struct file *file)
843{
844 struct drm_device *dev = inode->i_private;
d5442303 845 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 846
847 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
848 if (!error_priv)
849 return -ENOMEM;
850
851 error_priv->dev = dev;
852
95d5bfb3 853 i915_error_state_get(dev, error_priv);
d5442303 854
edc3d884
MK		 855 file->private_data = error_priv;
856
857 return 0;
d5442303
DV		 858}
859
860static int i915_error_state_release(struct inode *inode, struct file *file)
861{
edc3d884 862 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 863
95d5bfb3 864 i915_error_state_put(error_priv);
d5442303
DV		 865 kfree(error_priv);
866
edc3d884
MK		 867 return 0;
868}
869
4dc955f7
MK		 870static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
871 size_t count, loff_t *pos)
872{
873 struct i915_error_state_file_priv *error_priv = file->private_data;
874 struct drm_i915_error_state_buf error_str;
875 loff_t tmp_pos = 0;
876 ssize_t ret_count = 0;
877 int ret;
878
879 ret = i915_error_state_buf_init(&error_str, count, *pos);
880 if (ret)
881 return ret;
edc3d884 882
fc16b48b 883 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 884 if (ret)
885 goto out;
886
edc3d884
MK		 887 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
888 error_str.buf,
889 error_str.bytes);
890
891 if (ret_count < 0)
892 ret = ret_count;
893 else
894 *pos = error_str.start + ret_count;
895out:
4dc955f7 896 i915_error_state_buf_release(&error_str);
edc3d884 897 return ret ?: ret_count;
d5442303
DV		 898}
899
900static const struct file_operations i915_error_state_fops = {
901 .owner = THIS_MODULE,
902 .open = i915_error_state_open,
edc3d884 903 .read = i915_error_state_read,
d5442303
DV		 904 .write = i915_error_state_write,
905 .llseek = default_llseek,
906 .release = i915_error_state_release,
907};
908
647416f9
KC		 909static int
910i915_next_seqno_get(void *data, u64 *val)
40633219 911{
647416f9 912 struct drm_device *dev = data;
e277a1f8 913 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 914 int ret;
915
916 ret = mutex_lock_interruptible(&dev->struct_mutex);
917 if (ret)
918 return ret;
919
647416f9 920 *val = dev_priv->next_seqno;
40633219
MK		 921 mutex_unlock(&dev->struct_mutex);
922
647416f9 923 return 0;
40633219
MK		 924}
925
647416f9
KC		 926static int
927i915_next_seqno_set(void *data, u64 val)
928{
929 struct drm_device *dev = data;
40633219
MK		 930 int ret;
931
40633219
MK		 932 ret = mutex_lock_interruptible(&dev->struct_mutex);
933 if (ret)
934 return ret;
935
e94fbaa8 936 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 937 mutex_unlock(&dev->struct_mutex);
938
647416f9 939 return ret;
40633219
MK		 940}
941
647416f9
KC		 942DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
943 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 944 "0x%llx\n");
40633219 945
f97108d1
JB		 946static int i915_rstdby_delays(struct seq_file *m, void *unused)
947{
948 struct drm_info_node *node = (struct drm_info_node *) m->private;
949 struct drm_device *dev = node->minor->dev;
e277a1f8 950 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 951 u16 crstanddelay;
952 int ret;
953
954 ret = mutex_lock_interruptible(&dev->struct_mutex);
955 if (ret)
956 return ret;
c8c8fb33 957 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 958
959 crstanddelay = I915_READ16(CRSTANDVID);
960
c8c8fb33 961 intel_runtime_pm_put(dev_priv);
616fdb5a 962 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 963
964 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
965
966 return 0;
967}
968
adb4bd12 969static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1
JB		 970{
971 struct drm_info_node *node = (struct drm_info_node *) m->private;
972 struct drm_device *dev = node->minor->dev;
e277a1f8 973 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 974 int ret = 0;
975
976 intel_runtime_pm_get(dev_priv);
3b8d8d91 977
5c9669ce
TR		 978 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
979
3b8d8d91
JB		 980 if (IS_GEN5(dev)) {
981 u16 rgvswctl = I915_READ16(MEMSWCTL);
982 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
983
984 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
985 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
986 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
987 MEMSTAT_VID_SHIFT);
988 seq_printf(m, "Current P-state: %d\n",
989 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 990 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 991 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
992 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
993 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 994 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 995 u32 rpstat, cagf, reqf;
ccab5c82
JB		 996 u32 rpupei, rpcurup, rpprevup;
997 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 998 int max_freq;
999
1000 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1001 ret = mutex_lock_interruptible(&dev->struct_mutex);
1002 if (ret)
c8c8fb33 1003 goto out;
d1ebd816 1004
c8d9a590 1005 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1006
8e8c06cd
CW		 1007 reqf = I915_READ(GEN6_RPNSWREQ);
1008 reqf &= ~GEN6_TURBO_DISABLE;
1009 if (IS_HASWELL(dev))
1010 reqf >>= 24;
1011 else
1012 reqf >>= 25;
1013 reqf *= GT_FREQUENCY_MULTIPLIER;
1014
0d8f9491
CW		 1015 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1016 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1017 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1018
ccab5c82
JB		 1019 rpstat = I915_READ(GEN6_RPSTAT1);
1020 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1021 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1022 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1023 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1024 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1025 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 1026 if (IS_HASWELL(dev))
1027 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1028 else
1029 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1030 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1031
c8d9a590 1032 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1033 mutex_unlock(&dev->struct_mutex);
1034
0d8f9491
CW		 1035 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1036 I915_READ(GEN6_PMIER),
1037 I915_READ(GEN6_PMIMR),
1038 I915_READ(GEN6_PMISR),
1039 I915_READ(GEN6_PMIIR),
1040 I915_READ(GEN6_PMINTRMSK));
3b8d8d91 1041 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1042 seq_printf(m, "Render p-state ratio: %d\n",
1043 (gt_perf_status & 0xff00) >> 8);
1044 seq_printf(m, "Render p-state VID: %d\n",
1045 gt_perf_status & 0xff);
1046 seq_printf(m, "Render p-state limit: %d\n",
1047 rp_state_limits & 0xff);
0d8f9491
CW		 1048 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1049 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1050 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1051 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1052 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1053 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1054 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1055 GEN6_CURICONT_MASK);
1056 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1057 GEN6_CURBSYTAVG_MASK);
1058 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1059 GEN6_CURBSYTAVG_MASK);
1060 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1061 GEN6_CURIAVG_MASK);
1062 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1063 GEN6_CURBSYTAVG_MASK);
1064 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1065 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1066
1067 max_freq = (rp_state_cap & 0xff0000) >> 16;
1068 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1069 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1070
1071 max_freq = (rp_state_cap & 0xff00) >> 8;
1072 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1073 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1074
1075 max_freq = rp_state_cap & 0xff;
1076 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1077 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1078
1079 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1080 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1081 } else if (IS_VALLEYVIEW(dev)) {
1082 u32 freq_sts, val;
1083
259bd5d4 1084 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1085 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1086 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1087 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1088
c5bd2bf6 1089 val = valleyview_rps_max_freq(dev_priv);
0a073b84 1090 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 1091 vlv_gpu_freq(dev_priv, val));
0a073b84 1092
c5bd2bf6 1093 val = valleyview_rps_min_freq(dev_priv);
0a073b84 1094 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 1095 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 1096
1097 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1098 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1099 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1100 } else {
267f0c90 1101 seq_puts(m, "no P-state info available\n");
3b8d8d91 1102 }
f97108d1 1103
c8c8fb33
PZ		 1104out:
1105 intel_runtime_pm_put(dev_priv);
1106 return ret;
f97108d1
JB		 1107}
1108
1109static int i915_delayfreq_table(struct seq_file *m, void *unused)
1110{
1111 struct drm_info_node *node = (struct drm_info_node *) m->private;
1112 struct drm_device *dev = node->minor->dev;
e277a1f8 1113 struct drm_i915_private *dev_priv = dev->dev_private;
f97108d1 1114 u32 delayfreq;
616fdb5a
BW		 1115 int ret, i;
1116
1117 ret = mutex_lock_interruptible(&dev->struct_mutex);
1118 if (ret)
1119 return ret;
c8c8fb33 1120 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1121
1122 for (i = 0; i < 16; i++) {
1123 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1124 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1125 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1126 }
1127
c8c8fb33
PZ		 1128 intel_runtime_pm_put(dev_priv);
1129
616fdb5a
BW		 1130 mutex_unlock(&dev->struct_mutex);
1131
f97108d1
JB		 1132 return 0;
1133}
1134
1135static inline int MAP_TO_MV(int map)
1136{
1137 return 1250 - (map * 25);
1138}
1139
1140static int i915_inttoext_table(struct seq_file *m, void *unused)
1141{
1142 struct drm_info_node *node = (struct drm_info_node *) m->private;
1143 struct drm_device *dev = node->minor->dev;
e277a1f8 1144 struct drm_i915_private *dev_priv = dev->dev_private;
f97108d1 1145 u32 inttoext;
616fdb5a
BW		 1146 int ret, i;
1147
1148 ret = mutex_lock_interruptible(&dev->struct_mutex);
1149 if (ret)
1150 return ret;
c8c8fb33 1151 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1152
1153 for (i = 1; i <= 32; i++) {
1154 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1155 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1156 }
1157
c8c8fb33 1158 intel_runtime_pm_put(dev_priv);
616fdb5a
BW		 1159 mutex_unlock(&dev->struct_mutex);
1160
f97108d1
JB		 1161 return 0;
1162}
1163
4d85529d 1164static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1165{
1166 struct drm_info_node *node = (struct drm_info_node *) m->private;
1167 struct drm_device *dev = node->minor->dev;
e277a1f8 1168 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1169 u32 rgvmodectl, rstdbyctl;
1170 u16 crstandvid;
1171 int ret;
1172
1173 ret = mutex_lock_interruptible(&dev->struct_mutex);
1174 if (ret)
1175 return ret;
c8c8fb33 1176 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1177
1178 rgvmodectl = I915_READ(MEMMODECTL);
1179 rstdbyctl = I915_READ(RSTDBYCTL);
1180 crstandvid = I915_READ16(CRSTANDVID);
1181
c8c8fb33 1182 intel_runtime_pm_put(dev_priv);
616fdb5a 1183 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1184
1185 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1186 "yes" : "no");
1187 seq_printf(m, "Boost freq: %d\n",
1188 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1189 MEMMODE_BOOST_FREQ_SHIFT);
1190 seq_printf(m, "HW control enabled: %s\n",
1191 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1192 seq_printf(m, "SW control enabled: %s\n",
1193 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1194 seq_printf(m, "Gated voltage change: %s\n",
1195 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1196 seq_printf(m, "Starting frequency: P%d\n",
1197 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1198 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1199 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1200 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1201 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1202 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1203 seq_printf(m, "Render standby enabled: %s\n",
1204 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1205 seq_puts(m, "Current RS state: ");
88271da3
JB		 1206 switch (rstdbyctl & RSX_STATUS_MASK) {
1207 case RSX_STATUS_ON:
267f0c90 1208 seq_puts(m, "on\n");
88271da3
JB		 1209 break;
1210 case RSX_STATUS_RC1:
267f0c90 1211 seq_puts(m, "RC1\n");
88271da3
JB		 1212 break;
1213 case RSX_STATUS_RC1E:
267f0c90 1214 seq_puts(m, "RC1E\n");
88271da3
JB		 1215 break;
1216 case RSX_STATUS_RS1:
267f0c90 1217 seq_puts(m, "RS1\n");
88271da3
JB		 1218 break;
1219 case RSX_STATUS_RS2:
267f0c90 1220 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1221 break;
1222 case RSX_STATUS_RS3:
267f0c90 1223 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1224 break;
1225 default:
267f0c90 1226 seq_puts(m, "unknown\n");
88271da3
JB		 1227 break;
1228 }
f97108d1
JB		 1229
1230 return 0;
1231}
1232
669ab5aa
D		 1233static int vlv_drpc_info(struct seq_file *m)
1234{
1235
1236 struct drm_info_node *node = (struct drm_info_node *) m->private;
1237 struct drm_device *dev = node->minor->dev;
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239 u32 rpmodectl1, rcctl1;
1240 unsigned fw_rendercount = 0, fw_mediacount = 0;
1241
d46c0517
ID		 1242 intel_runtime_pm_get(dev_priv);
1243
669ab5aa
D		 1244 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1245 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1246
d46c0517
ID		 1247 intel_runtime_pm_put(dev_priv);
1248
669ab5aa
D		 1249 seq_printf(m, "Video Turbo Mode: %s\n",
1250 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1251 seq_printf(m, "Turbo enabled: %s\n",
1252 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1253 seq_printf(m, "HW control enabled: %s\n",
1254 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1255 seq_printf(m, "SW control enabled: %s\n",
1256 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1257 GEN6_RP_MEDIA_SW_MODE));
1258 seq_printf(m, "RC6 Enabled: %s\n",
1259 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1260 GEN6_RC_CTL_EI_MODE(1))));
1261 seq_printf(m, "Render Power Well: %s\n",
1262 (I915_READ(VLV_GTLC_PW_STATUS) &
1263 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1264 seq_printf(m, "Media Power Well: %s\n",
1265 (I915_READ(VLV_GTLC_PW_STATUS) &
1266 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1267
9cc19be5
ID		 1268 seq_printf(m, "Render RC6 residency since boot: %u\n",
1269 I915_READ(VLV_GT_RENDER_RC6));
1270 seq_printf(m, "Media RC6 residency since boot: %u\n",
1271 I915_READ(VLV_GT_MEDIA_RC6));
1272
669ab5aa
D		 1273 spin_lock_irq(&dev_priv->uncore.lock);
1274 fw_rendercount = dev_priv->uncore.fw_rendercount;
1275 fw_mediacount = dev_priv->uncore.fw_mediacount;
1276 spin_unlock_irq(&dev_priv->uncore.lock);
1277
1278 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1279 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1280
1281
1282 return 0;
1283}
1284
1285
4d85529d
BW		 1286static int gen6_drpc_info(struct seq_file *m)
1287{
1288
1289 struct drm_info_node *node = (struct drm_info_node *) m->private;
1290 struct drm_device *dev = node->minor->dev;
1291 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1292 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1293 unsigned forcewake_count;
aee56cff 1294 int count = 0, ret;
4d85529d
BW		 1295
1296 ret = mutex_lock_interruptible(&dev->struct_mutex);
1297 if (ret)
1298 return ret;
c8c8fb33 1299 intel_runtime_pm_get(dev_priv);
4d85529d 1300
907b28c5
CW		 1301 spin_lock_irq(&dev_priv->uncore.lock);
1302 forcewake_count = dev_priv->uncore.forcewake_count;
1303 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1304
1305 if (forcewake_count) {
267f0c90
DL		 1306 seq_puts(m, "RC information inaccurate because somebody "
1307 "holds a forcewake reference \n");
4d85529d
BW		 1308 } else {
1309 /* NB: we cannot use forcewake, else we read the wrong values */
1310 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1311 udelay(10);
1312 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1313 }
1314
1315 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1316 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1317
1318 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1319 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1320 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1321 mutex_lock(&dev_priv->rps.hw_lock);
1322 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1323 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1324
c8c8fb33
PZ		 1325 intel_runtime_pm_put(dev_priv);
1326
4d85529d
BW		 1327 seq_printf(m, "Video Turbo Mode: %s\n",
1328 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1329 seq_printf(m, "HW control enabled: %s\n",
1330 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1331 seq_printf(m, "SW control enabled: %s\n",
1332 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1333 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1334 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1335 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1336 seq_printf(m, "RC6 Enabled: %s\n",
1337 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1338 seq_printf(m, "Deep RC6 Enabled: %s\n",
1339 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1340 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1341 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1342 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1343 switch (gt_core_status & GEN6_RCn_MASK) {
1344 case GEN6_RC0:
1345 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1346 seq_puts(m, "Core Power Down\n");
4d85529d 1347 else
267f0c90 1348 seq_puts(m, "on\n");
4d85529d
BW		 1349 break;
1350 case GEN6_RC3:
267f0c90 1351 seq_puts(m, "RC3\n");
4d85529d
BW		 1352 break;
1353 case GEN6_RC6:
267f0c90 1354 seq_puts(m, "RC6\n");
4d85529d
BW		 1355 break;
1356 case GEN6_RC7:
267f0c90 1357 seq_puts(m, "RC7\n");
4d85529d
BW		 1358 break;
1359 default:
267f0c90 1360 seq_puts(m, "Unknown\n");
4d85529d
BW		 1361 break;
1362 }
1363
1364 seq_printf(m, "Core Power Down: %s\n",
1365 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1366
1367 /* Not exactly sure what this is */
1368 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1369 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1370 seq_printf(m, "RC6 residency since boot: %u\n",
1371 I915_READ(GEN6_GT_GFX_RC6));
1372 seq_printf(m, "RC6+ residency since boot: %u\n",
1373 I915_READ(GEN6_GT_GFX_RC6p));
1374 seq_printf(m, "RC6++ residency since boot: %u\n",
1375 I915_READ(GEN6_GT_GFX_RC6pp));
1376
ecd8faea
BW		 1377 seq_printf(m, "RC6 voltage: %dmV\n",
1378 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1379 seq_printf(m, "RC6+ voltage: %dmV\n",
1380 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1381 seq_printf(m, "RC6++ voltage: %dmV\n",
1382 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1383 return 0;
1384}
1385
1386static int i915_drpc_info(struct seq_file *m, void *unused)
1387{
1388 struct drm_info_node *node = (struct drm_info_node *) m->private;
1389 struct drm_device *dev = node->minor->dev;
1390
669ab5aa
D		 1391 if (IS_VALLEYVIEW(dev))
1392 return vlv_drpc_info(m);
1393 else if (IS_GEN6(dev) || IS_GEN7(dev))
4d85529d
BW		 1394 return gen6_drpc_info(m);
1395 else
1396 return ironlake_drpc_info(m);
1397}
1398
b5e50c3f
JB		 1399static int i915_fbc_status(struct seq_file *m, void *unused)
1400{
1401 struct drm_info_node *node = (struct drm_info_node *) m->private;
1402 struct drm_device *dev = node->minor->dev;
e277a1f8 1403 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1404
3a77c4c4 1405 if (!HAS_FBC(dev)) {
267f0c90 1406 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1407 return 0;
1408 }
1409
36623ef8
PZ		 1410 intel_runtime_pm_get(dev_priv);
1411
ee5382ae 1412 if (intel_fbc_enabled(dev)) {
267f0c90 1413 seq_puts(m, "FBC enabled\n");
b5e50c3f 1414 } else {
267f0c90 1415 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1416 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1417 case FBC_OK:
1418 seq_puts(m, "FBC actived, but currently disabled in hardware");
1419 break;
1420 case FBC_UNSUPPORTED:
1421 seq_puts(m, "unsupported by this chipset");
1422 break;
bed4a673 1423 case FBC_NO_OUTPUT:
267f0c90 1424 seq_puts(m, "no outputs");
bed4a673 1425 break;
b5e50c3f 1426 case FBC_STOLEN_TOO_SMALL:
267f0c90 1427 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1428 break;
1429 case FBC_UNSUPPORTED_MODE:
267f0c90 1430 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1431 break;
1432 case FBC_MODE_TOO_LARGE:
267f0c90 1433 seq_puts(m, "mode too large");
b5e50c3f
JB		 1434 break;
1435 case FBC_BAD_PLANE:
267f0c90 1436 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1437 break;
1438 case FBC_NOT_TILED:
267f0c90 1439 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1440 break;
9c928d16 1441 case FBC_MULTIPLE_PIPES:
267f0c90 1442 seq_puts(m, "multiple pipes are enabled");
9c928d16 1443 break;
c1a9f047 1444 case FBC_MODULE_PARAM:
267f0c90 1445 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1446 break;
8a5729a3 1447 case FBC_CHIP_DEFAULT:
267f0c90 1448 seq_puts(m, "disabled per chip default");
8a5729a3 1449 break;
b5e50c3f 1450 default:
267f0c90 1451 seq_puts(m, "unknown reason");
b5e50c3f 1452 }
267f0c90 1453 seq_putc(m, '\n');
b5e50c3f 1454 }
36623ef8
PZ		 1455
1456 intel_runtime_pm_put(dev_priv);
1457
b5e50c3f
JB		 1458 return 0;
1459}
1460
92d44621
PZ		 1461static int i915_ips_status(struct seq_file *m, void *unused)
1462{
1463 struct drm_info_node *node = (struct drm_info_node *) m->private;
1464 struct drm_device *dev = node->minor->dev;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1466
f5adf94e 1467 if (!HAS_IPS(dev)) {
92d44621
PZ		 1468 seq_puts(m, "not supported\n");
1469 return 0;
1470 }
1471
36623ef8
PZ		 1472 intel_runtime_pm_get(dev_priv);
1473
e59150dc 1474 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
92d44621
PZ		 1475 seq_puts(m, "enabled\n");
1476 else
1477 seq_puts(m, "disabled\n");
1478
36623ef8
PZ		 1479 intel_runtime_pm_put(dev_priv);
1480
92d44621
PZ		 1481 return 0;
1482}
1483
4a9bef37
JB		 1484static int i915_sr_status(struct seq_file *m, void *unused)
1485{
1486 struct drm_info_node *node = (struct drm_info_node *) m->private;
1487 struct drm_device *dev = node->minor->dev;
e277a1f8 1488 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1489 bool sr_enabled = false;
1490
36623ef8
PZ		 1491 intel_runtime_pm_get(dev_priv);
1492
1398261a 1493 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1494 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1495 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1496 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1497 else if (IS_I915GM(dev))
1498 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1499 else if (IS_PINEVIEW(dev))
1500 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1501
36623ef8
PZ		 1502 intel_runtime_pm_put(dev_priv);
1503
5ba2aaaa
CW		 1504 seq_printf(m, "self-refresh: %s\n",
1505 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1506
1507 return 0;
1508}
1509
7648fa99
JB		 1510static int i915_emon_status(struct seq_file *m, void *unused)
1511{
1512 struct drm_info_node *node = (struct drm_info_node *) m->private;
1513 struct drm_device *dev = node->minor->dev;
e277a1f8 1514 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1515 unsigned long temp, chipset, gfx;
de227ef0
CW		 1516 int ret;
1517
582be6b4
CW		 1518 if (!IS_GEN5(dev))
1519 return -ENODEV;
1520
de227ef0
CW		 1521 ret = mutex_lock_interruptible(&dev->struct_mutex);
1522 if (ret)
1523 return ret;
7648fa99
JB		 1524
1525 temp = i915_mch_val(dev_priv);
1526 chipset = i915_chipset_val(dev_priv);
1527 gfx = i915_gfx_val(dev_priv);
de227ef0 1528 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1529
1530 seq_printf(m, "GMCH temp: %ld\n", temp);
1531 seq_printf(m, "Chipset power: %ld\n", chipset);
1532 seq_printf(m, "GFX power: %ld\n", gfx);
1533 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1534
1535 return 0;
1536}
1537
23b2f8bb
JB		 1538static int i915_ring_freq_table(struct seq_file *m, void *unused)
1539{
1540 struct drm_info_node *node = (struct drm_info_node *) m->private;
1541 struct drm_device *dev = node->minor->dev;
e277a1f8 1542 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1543 int ret = 0;
23b2f8bb
JB		 1544 int gpu_freq, ia_freq;
1545
1c70c0ce 1546 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1547 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1548 return 0;
1549 }
1550
5bfa0199
PZ		 1551 intel_runtime_pm_get(dev_priv);
1552
5c9669ce
TR		 1553 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1554
4fc688ce 1555 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1556 if (ret)
5bfa0199 1557 goto out;
23b2f8bb 1558
267f0c90 1559 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1560
b39fb297
BW		 1561 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1562 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1563 gpu_freq++) {
42c0526c
BW		 1564 ia_freq = gpu_freq;
1565 sandybridge_pcode_read(dev_priv,
1566 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1567 &ia_freq);
3ebecd07
CW		 1568 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1569 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1570 ((ia_freq >> 0) & 0xff) * 100,
1571 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1572 }
1573
4fc688ce 1574 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1575
5bfa0199
PZ		 1576out:
1577 intel_runtime_pm_put(dev_priv);
1578 return ret;
23b2f8bb
JB		 1579}
1580
7648fa99
JB		 1581static int i915_gfxec(struct seq_file *m, void *unused)
1582{
1583 struct drm_info_node *node = (struct drm_info_node *) m->private;
1584 struct drm_device *dev = node->minor->dev;
e277a1f8 1585 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1586 int ret;
1587
1588 ret = mutex_lock_interruptible(&dev->struct_mutex);
1589 if (ret)
1590 return ret;
c8c8fb33 1591 intel_runtime_pm_get(dev_priv);
7648fa99
JB		 1592
1593 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
c8c8fb33 1594 intel_runtime_pm_put(dev_priv);
7648fa99 1595
616fdb5a
BW		 1596 mutex_unlock(&dev->struct_mutex);
1597
7648fa99
JB		 1598 return 0;
1599}
1600
44834a67
CW		 1601static int i915_opregion(struct seq_file *m, void *unused)
1602{
1603 struct drm_info_node *node = (struct drm_info_node *) m->private;
1604 struct drm_device *dev = node->minor->dev;
e277a1f8 1605 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1606 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1607 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1608 int ret;
1609
0d38f009
DV		 1610 if (data == NULL)
1611 return -ENOMEM;
1612
44834a67
CW		 1613 ret = mutex_lock_interruptible(&dev->struct_mutex);
1614 if (ret)
0d38f009 1615 goto out;
44834a67 1616
0d38f009
DV		 1617 if (opregion->header) {
1618 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1619 seq_write(m, data, OPREGION_SIZE);
1620 }
44834a67
CW		 1621
1622 mutex_unlock(&dev->struct_mutex);
1623
0d38f009
DV		 1624out:
1625 kfree(data);
44834a67
CW		 1626 return 0;
1627}
1628
37811fcc
CW		 1629static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1630{
1631 struct drm_info_node *node = (struct drm_info_node *) m->private;
1632 struct drm_device *dev = node->minor->dev;
4520f53a 1633 struct intel_fbdev *ifbdev = NULL;
37811fcc 1634 struct intel_framebuffer *fb;
37811fcc 1635
4520f53a
DV		 1636#ifdef CONFIG_DRM_I915_FBDEV
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1639 if (ret)
1640 return ret;
1641
1642 ifbdev = dev_priv->fbdev;
1643 fb = to_intel_framebuffer(ifbdev->helper.fb);
1644
623f9783 1645 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1646 fb->base.width,
1647 fb->base.height,
1648 fb->base.depth,
623f9783
DV		 1649 fb->base.bits_per_pixel,
1650 atomic_read(&fb->base.refcount.refcount));
05394f39 1651 describe_obj(m, fb->obj);
267f0c90 1652 seq_putc(m, '\n');
4b096ac1 1653 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1654#endif
37811fcc 1655
4b096ac1 1656 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1657 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1658 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1659 continue;
1660
623f9783 1661 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1662 fb->base.width,
1663 fb->base.height,
1664 fb->base.depth,
623f9783
DV		 1665 fb->base.bits_per_pixel,
1666 atomic_read(&fb->base.refcount.refcount));
05394f39 1667 describe_obj(m, fb->obj);
267f0c90 1668 seq_putc(m, '\n');
37811fcc 1669 }
4b096ac1 1670 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1671
1672 return 0;
1673}
1674
e76d3630
BW		 1675static int i915_context_status(struct seq_file *m, void *unused)
1676{
1677 struct drm_info_node *node = (struct drm_info_node *) m->private;
1678 struct drm_device *dev = node->minor->dev;
e277a1f8 1679 struct drm_i915_private *dev_priv = dev->dev_private;
a168c293 1680 struct intel_ring_buffer *ring;
a33afea5 1681 struct i915_hw_context *ctx;
a168c293 1682 int ret, i;
e76d3630
BW		 1683
1684 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1685 if (ret)
1686 return ret;
1687
3e373948 1688 if (dev_priv->ips.pwrctx) {
267f0c90 1689 seq_puts(m, "power context ");
3e373948 1690 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1691 seq_putc(m, '\n');
dc501fbc 1692 }
e76d3630 1693
3e373948 1694 if (dev_priv->ips.renderctx) {
267f0c90 1695 seq_puts(m, "render context ");
3e373948 1696 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1697 seq_putc(m, '\n');
dc501fbc 1698 }
e76d3630 1699
a33afea5
BW		 1700 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1701 seq_puts(m, "HW context ");
3ccfd19d 1702 describe_ctx(m, ctx);
a33afea5
BW		 1703 for_each_ring(ring, dev_priv, i)
1704 if (ring->default_context == ctx)
1705 seq_printf(m, "(default context %s) ", ring->name);
1706
1707 describe_obj(m, ctx->obj);
1708 seq_putc(m, '\n');
a168c293
BW		 1709 }
1710
e76d3630
BW		 1711 mutex_unlock(&dev->mode_config.mutex);
1712
1713 return 0;
1714}
1715
6d794d42
BW		 1716static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1717{
1718 struct drm_info_node *node = (struct drm_info_node *) m->private;
1719 struct drm_device *dev = node->minor->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1721 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1722
907b28c5 1723 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1724 if (IS_VALLEYVIEW(dev)) {
1725 fw_rendercount = dev_priv->uncore.fw_rendercount;
1726 fw_mediacount = dev_priv->uncore.fw_mediacount;
1727 } else
1728 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1729 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1730
43709ba0
D		 1731 if (IS_VALLEYVIEW(dev)) {
1732 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1733 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1734 } else
1735 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1736
1737 return 0;
1738}
1739
ea16a3cd
DV		 1740static const char *swizzle_string(unsigned swizzle)
1741{
aee56cff 1742 switch (swizzle) {
ea16a3cd
DV		 1743 case I915_BIT_6_SWIZZLE_NONE:
1744 return "none";
1745 case I915_BIT_6_SWIZZLE_9:
1746 return "bit9";
1747 case I915_BIT_6_SWIZZLE_9_10:
1748 return "bit9/bit10";
1749 case I915_BIT_6_SWIZZLE_9_11:
1750 return "bit9/bit11";
1751 case I915_BIT_6_SWIZZLE_9_10_11:
1752 return "bit9/bit10/bit11";
1753 case I915_BIT_6_SWIZZLE_9_17:
1754 return "bit9/bit17";
1755 case I915_BIT_6_SWIZZLE_9_10_17:
1756 return "bit9/bit10/bit17";
1757 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1758 return "unknown";
ea16a3cd
DV		 1759 }
1760
1761 return "bug";
1762}
1763
1764static int i915_swizzle_info(struct seq_file *m, void *data)
1765{
1766 struct drm_info_node *node = (struct drm_info_node *) m->private;
1767 struct drm_device *dev = node->minor->dev;
1768 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1769 int ret;
1770
1771 ret = mutex_lock_interruptible(&dev->struct_mutex);
1772 if (ret)
1773 return ret;
c8c8fb33 1774 intel_runtime_pm_get(dev_priv);
ea16a3cd 1775
ea16a3cd
DV		 1776 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1777 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1778 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1779 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1780
1781 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1782 seq_printf(m, "DDC = 0x%08x\n",
1783 I915_READ(DCC));
1784 seq_printf(m, "C0DRB3 = 0x%04x\n",
1785 I915_READ16(C0DRB3));
1786 seq_printf(m, "C1DRB3 = 0x%04x\n",
1787 I915_READ16(C1DRB3));
9d3203e1 1788 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1789 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1790 I915_READ(MAD_DIMM_C0));
1791 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1792 I915_READ(MAD_DIMM_C1));
1793 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1794 I915_READ(MAD_DIMM_C2));
1795 seq_printf(m, "TILECTL = 0x%08x\n",
1796 I915_READ(TILECTL));
9d3203e1
BW		 1797 if (IS_GEN8(dev))
1798 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1799 I915_READ(GAMTARBMODE));
1800 else
1801 seq_printf(m, "ARB_MODE = 0x%08x\n",
1802 I915_READ(ARB_MODE));
3fa7d235
DV		 1803 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1804 I915_READ(DISP_ARB_CTL));
ea16a3cd 1805 }
c8c8fb33 1806 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1807 mutex_unlock(&dev->struct_mutex);
1808
1809 return 0;
1810}
1811
1c60fef5
BW		 1812static int per_file_ctx(int id, void *ptr, void *data)
1813{
1814 struct i915_hw_context *ctx = ptr;
1815 struct seq_file *m = data;
1816 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1817
1818 ppgtt->debug_dump(ppgtt, m);
1819
1820 return 0;
1821}
1822
77df6772 1823static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1824{
3cf17fc5
DV		 1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826 struct intel_ring_buffer *ring;
77df6772
BW		 1827 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1828 int unused, i;
3cf17fc5 1829
77df6772
BW		 1830 if (!ppgtt)
1831 return;
1832
1833 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 1834 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 1835 for_each_ring(ring, dev_priv, unused) {
1836 seq_printf(m, "%s\n", ring->name);
1837 for (i = 0; i < 4; i++) {
1838 u32 offset = 0x270 + i * 8;
1839 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1840 pdp <<= 32;
1841 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 1842 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 1843 }
1844 }
1845}
1846
1847static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1848{
1849 struct drm_i915_private *dev_priv = dev->dev_private;
1850 struct intel_ring_buffer *ring;
1c60fef5 1851 struct drm_file *file;
77df6772 1852 int i;
3cf17fc5 1853
3cf17fc5
DV		 1854 if (INTEL_INFO(dev)->gen == 6)
1855 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1856
a2c7f6fd 1857 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1858 seq_printf(m, "%s\n", ring->name);
1859 if (INTEL_INFO(dev)->gen == 7)
1860 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1861 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1862 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1863 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1864 }
1865 if (dev_priv->mm.aliasing_ppgtt) {
1866 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1867
267f0c90 1868 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 1869 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 1870
87d60b63 1871 ppgtt->debug_dump(ppgtt, m);
1c60fef5
BW		 1872 } else
1873 return;
1874
1875 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1876 struct drm_i915_file_private *file_priv = file->driver_priv;
1877 struct i915_hw_ppgtt *pvt_ppgtt;
1878
1879 pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);
1880 seq_printf(m, "proc: %s\n",
1881 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1882 seq_puts(m, " default context:\n");
1883 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 1884 }
1885 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1886}
1887
1888static int i915_ppgtt_info(struct seq_file *m, void *data)
1889{
1890 struct drm_info_node *node = (struct drm_info_node *) m->private;
1891 struct drm_device *dev = node->minor->dev;
c8c8fb33 1892 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 1893
1894 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1895 if (ret)
1896 return ret;
c8c8fb33 1897 intel_runtime_pm_get(dev_priv);
77df6772
BW		 1898
1899 if (INTEL_INFO(dev)->gen >= 8)
1900 gen8_ppgtt_info(m, dev);
1901 else if (INTEL_INFO(dev)->gen >= 6)
1902 gen6_ppgtt_info(m, dev);
1903
c8c8fb33 1904 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 1905 mutex_unlock(&dev->struct_mutex);
1906
1907 return 0;
1908}
1909
63573eb7
BW		 1910static int i915_llc(struct seq_file *m, void *data)
1911{
1912 struct drm_info_node *node = (struct drm_info_node *) m->private;
1913 struct drm_device *dev = node->minor->dev;
1914 struct drm_i915_private *dev_priv = dev->dev_private;
1915
1916 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1917 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1918 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1919
1920 return 0;
1921}
1922
e91fd8c6
RV		 1923static int i915_edp_psr_status(struct seq_file *m, void *data)
1924{
1925 struct drm_info_node *node = m->private;
1926 struct drm_device *dev = node->minor->dev;
1927 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1928 u32 psrperf = 0;
1929 bool enabled = false;
e91fd8c6 1930
c8c8fb33
PZ		 1931 intel_runtime_pm_get(dev_priv);
1932
a031d709
RV		 1933 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1934 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1935
a031d709
RV		 1936 enabled = HAS_PSR(dev) &&
1937 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1938 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1939
a031d709
RV		 1940 if (HAS_PSR(dev))
1941 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1942 EDP_PSR_PERF_CNT_MASK;
1943 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6 1944
c8c8fb33 1945 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 1946 return 0;
1947}
1948
d2e216d0
RV		 1949static int i915_sink_crc(struct seq_file *m, void *data)
1950{
1951 struct drm_info_node *node = m->private;
1952 struct drm_device *dev = node->minor->dev;
1953 struct intel_encoder *encoder;
1954 struct intel_connector *connector;
1955 struct intel_dp *intel_dp = NULL;
1956 int ret;
1957 u8 crc[6];
1958
1959 drm_modeset_lock_all(dev);
1960 list_for_each_entry(connector, &dev->mode_config.connector_list,
1961 base.head) {
1962
1963 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1964 continue;
1965
b6ae3c7c
PZ		 1966 if (!connector->base.encoder)
1967 continue;
1968
d2e216d0
RV		 1969 encoder = to_intel_encoder(connector->base.encoder);
1970 if (encoder->type != INTEL_OUTPUT_EDP)
1971 continue;
1972
1973 intel_dp = enc_to_intel_dp(&encoder->base);
1974
1975 ret = intel_dp_sink_crc(intel_dp, crc);
1976 if (ret)
1977 goto out;
1978
1979 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1980 crc[0], crc[1], crc[2],
1981 crc[3], crc[4], crc[5]);
1982 goto out;
1983 }
1984 ret = -ENODEV;
1985out:
1986 drm_modeset_unlock_all(dev);
1987 return ret;
1988}
1989
ec013e7f
JB		 1990static int i915_energy_uJ(struct seq_file *m, void *data)
1991{
1992 struct drm_info_node *node = m->private;
1993 struct drm_device *dev = node->minor->dev;
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 u64 power;
1996 u32 units;
1997
1998 if (INTEL_INFO(dev)->gen < 6)
1999 return -ENODEV;
2000
36623ef8
PZ		 2001 intel_runtime_pm_get(dev_priv);
2002
ec013e7f
JB		 2003 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2004 power = (power & 0x1f00) >> 8;
2005 units = 1000000 / (1 << power); /* convert to uJ */
2006 power = I915_READ(MCH_SECP_NRG_STTS);
2007 power *= units;
2008
36623ef8
PZ		 2009 intel_runtime_pm_put(dev_priv);
2010
ec013e7f 2011 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2012
2013 return 0;
2014}
2015
2016static int i915_pc8_status(struct seq_file *m, void *unused)
2017{
2018 struct drm_info_node *node = (struct drm_info_node *) m->private;
2019 struct drm_device *dev = node->minor->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021
85b8d5c2 2022 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2023 seq_puts(m, "not supported\n");
2024 return 0;
2025 }
2026
86c4ec0d 2027 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2028 seq_printf(m, "IRQs disabled: %s\n",
5d584b2e 2029 yesno(dev_priv->pm.irqs_disabled));
371db66a 2030
ec013e7f
JB		 2031 return 0;
2032}
2033
1da51581
ID		 2034static const char *power_domain_str(enum intel_display_power_domain domain)
2035{
2036 switch (domain) {
2037 case POWER_DOMAIN_PIPE_A:
2038 return "PIPE_A";
2039 case POWER_DOMAIN_PIPE_B:
2040 return "PIPE_B";
2041 case POWER_DOMAIN_PIPE_C:
2042 return "PIPE_C";
2043 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2044 return "PIPE_A_PANEL_FITTER";
2045 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2046 return "PIPE_B_PANEL_FITTER";
2047 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2048 return "PIPE_C_PANEL_FITTER";
2049 case POWER_DOMAIN_TRANSCODER_A:
2050 return "TRANSCODER_A";
2051 case POWER_DOMAIN_TRANSCODER_B:
2052 return "TRANSCODER_B";
2053 case POWER_DOMAIN_TRANSCODER_C:
2054 return "TRANSCODER_C";
2055 case POWER_DOMAIN_TRANSCODER_EDP:
2056 return "TRANSCODER_EDP";
319be8ae
ID		 2057 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2058 return "PORT_DDI_A_2_LANES";
2059 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2060 return "PORT_DDI_A_4_LANES";
2061 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2062 return "PORT_DDI_B_2_LANES";
2063 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2064 return "PORT_DDI_B_4_LANES";
2065 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2066 return "PORT_DDI_C_2_LANES";
2067 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2068 return "PORT_DDI_C_4_LANES";
2069 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2070 return "PORT_DDI_D_2_LANES";
2071 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2072 return "PORT_DDI_D_4_LANES";
2073 case POWER_DOMAIN_PORT_DSI:
2074 return "PORT_DSI";
2075 case POWER_DOMAIN_PORT_CRT:
2076 return "PORT_CRT";
2077 case POWER_DOMAIN_PORT_OTHER:
2078 return "PORT_OTHER";
1da51581
ID		 2079 case POWER_DOMAIN_VGA:
2080 return "VGA";
2081 case POWER_DOMAIN_AUDIO:
2082 return "AUDIO";
2083 case POWER_DOMAIN_INIT:
2084 return "INIT";
2085 default:
2086 WARN_ON(1);
2087 return "?";
2088 }
2089}
2090
2091static int i915_power_domain_info(struct seq_file *m, void *unused)
2092{
2093 struct drm_info_node *node = (struct drm_info_node *) m->private;
2094 struct drm_device *dev = node->minor->dev;
2095 struct drm_i915_private *dev_priv = dev->dev_private;
2096 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2097 int i;
2098
2099 mutex_lock(&power_domains->lock);
2100
2101 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2102 for (i = 0; i < power_domains->power_well_count; i++) {
2103 struct i915_power_well *power_well;
2104 enum intel_display_power_domain power_domain;
2105
2106 power_well = &power_domains->power_wells[i];
2107 seq_printf(m, "%-25s %d\n", power_well->name,
2108 power_well->count);
2109
2110 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2111 power_domain++) {
2112 if (!(BIT(power_domain) & power_well->domains))
2113 continue;
2114
2115 seq_printf(m, " %-23s %d\n",
2116 power_domain_str(power_domain),
2117 power_domains->domain_use_count[power_domain]);
2118 }
2119 }
2120
2121 mutex_unlock(&power_domains->lock);
2122
2123 return 0;
2124}
2125
53f5e3ca
JB		 2126static void intel_seq_print_mode(struct seq_file *m, int tabs,
2127 struct drm_display_mode *mode)
2128{
2129 int i;
2130
2131 for (i = 0; i < tabs; i++)
2132 seq_putc(m, '\t');
2133
2134 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2135 mode->base.id, mode->name,
2136 mode->vrefresh, mode->clock,
2137 mode->hdisplay, mode->hsync_start,
2138 mode->hsync_end, mode->htotal,
2139 mode->vdisplay, mode->vsync_start,
2140 mode->vsync_end, mode->vtotal,
2141 mode->type, mode->flags);
2142}
2143
2144static void intel_encoder_info(struct seq_file *m,
2145 struct intel_crtc *intel_crtc,
2146 struct intel_encoder *intel_encoder)
2147{
2148 struct drm_info_node *node = (struct drm_info_node *) m->private;
2149 struct drm_device *dev = node->minor->dev;
2150 struct drm_crtc *crtc = &intel_crtc->base;
2151 struct intel_connector *intel_connector;
2152 struct drm_encoder *encoder;
2153
2154 encoder = &intel_encoder->base;
2155 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2156 encoder->base.id, drm_get_encoder_name(encoder));
2157 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2158 struct drm_connector *connector = &intel_connector->base;
2159 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2160 connector->base.id,
2161 drm_get_connector_name(connector),
2162 drm_get_connector_status_name(connector->status));
2163 if (connector->status == connector_status_connected) {
2164 struct drm_display_mode *mode = &crtc->mode;
2165 seq_printf(m, ", mode:\n");
2166 intel_seq_print_mode(m, 2, mode);
2167 } else {
2168 seq_putc(m, '\n');
2169 }
2170 }
2171}
2172
2173static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2174{
2175 struct drm_info_node *node = (struct drm_info_node *) m->private;
2176 struct drm_device *dev = node->minor->dev;
2177 struct drm_crtc *crtc = &intel_crtc->base;
2178 struct intel_encoder *intel_encoder;
2179
2180 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
f4510a27
MR		 2181 crtc->primary->fb->base.id, crtc->x, crtc->y,
2182 crtc->primary->fb->width, crtc->primary->fb->height);
53f5e3ca
JB		 2183 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2184 intel_encoder_info(m, intel_crtc, intel_encoder);
2185}
2186
2187static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2188{
2189 struct drm_display_mode *mode = panel->fixed_mode;
2190
2191 seq_printf(m, "\tfixed mode:\n");
2192 intel_seq_print_mode(m, 2, mode);
2193}
2194
2195static void intel_dp_info(struct seq_file *m,
2196 struct intel_connector *intel_connector)
2197{
2198 struct intel_encoder *intel_encoder = intel_connector->encoder;
2199 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2200
2201 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2202 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2203 "no");
2204 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2205 intel_panel_info(m, &intel_connector->panel);
2206}
2207
2208static void intel_hdmi_info(struct seq_file *m,
2209 struct intel_connector *intel_connector)
2210{
2211 struct intel_encoder *intel_encoder = intel_connector->encoder;
2212 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2213
2214 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2215 "no");
2216}
2217
2218static void intel_lvds_info(struct seq_file *m,
2219 struct intel_connector *intel_connector)
2220{
2221 intel_panel_info(m, &intel_connector->panel);
2222}
2223
2224static void intel_connector_info(struct seq_file *m,
2225 struct drm_connector *connector)
2226{
2227 struct intel_connector *intel_connector = to_intel_connector(connector);
2228 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2229 struct drm_display_mode *mode;
53f5e3ca
JB		 2230
2231 seq_printf(m, "connector %d: type %s, status: %s\n",
2232 connector->base.id, drm_get_connector_name(connector),
2233 drm_get_connector_status_name(connector->status));
2234 if (connector->status == connector_status_connected) {
2235 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2236 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2237 connector->display_info.width_mm,
2238 connector->display_info.height_mm);
2239 seq_printf(m, "\tsubpixel order: %s\n",
2240 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2241 seq_printf(m, "\tCEA rev: %d\n",
2242 connector->display_info.cea_rev);
2243 }
2244 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2245 intel_encoder->type == INTEL_OUTPUT_EDP)
2246 intel_dp_info(m, intel_connector);
2247 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2248 intel_hdmi_info(m, intel_connector);
2249 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2250 intel_lvds_info(m, intel_connector);
2251
f103fc7d
JB		 2252 seq_printf(m, "\tmodes:\n");
2253 list_for_each_entry(mode, &connector->modes, head)
2254 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2255}
2256
065f2ec2
CW		 2257static bool cursor_active(struct drm_device *dev, int pipe)
2258{
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 u32 state;
2261
2262 if (IS_845G(dev) || IS_I865G(dev))
2263 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2264 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
2265 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2266 else
2267 state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
2268
2269 return state;
2270}
2271
2272static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2273{
2274 struct drm_i915_private *dev_priv = dev->dev_private;
2275 u32 pos;
2276
2277 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
2278 pos = I915_READ(CURPOS_IVB(pipe));
2279 else
2280 pos = I915_READ(CURPOS(pipe));
2281
2282 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2283 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2284 *x = -*x;
2285
2286 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2287 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2288 *y = -*y;
2289
2290 return cursor_active(dev, pipe);
2291}
2292
53f5e3ca
JB		 2293static int i915_display_info(struct seq_file *m, void *unused)
2294{
2295 struct drm_info_node *node = (struct drm_info_node *) m->private;
2296 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2297 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2298 struct intel_crtc *crtc;
53f5e3ca
JB		 2299 struct drm_connector *connector;
2300
b0e5ddf3 2301 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2302 drm_modeset_lock_all(dev);
2303 seq_printf(m, "CRTC info\n");
2304 seq_printf(m, "---------\n");
065f2ec2
CW		 2305 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2306 bool active;
2307 int x, y;
53f5e3ca
JB		 2308
2309 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
065f2ec2
CW		 2310 crtc->base.base.id, pipe_name(crtc->pipe),
2311 yesno(crtc->active));
a23dc658 2312 if (crtc->active) {
065f2ec2
CW		 2313 intel_crtc_info(m, crtc);
2314
a23dc658
PZ		 2315 active = cursor_position(dev, crtc->pipe, &x, &y);
2316 seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2317 yesno(crtc->cursor_visible),
2318 x, y, crtc->cursor_addr,
2319 yesno(active));
2320 }
53f5e3ca
JB		 2321 }
2322
2323 seq_printf(m, "\n");
2324 seq_printf(m, "Connector info\n");
2325 seq_printf(m, "--------------\n");
2326 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2327 intel_connector_info(m, connector);
2328 }
2329 drm_modeset_unlock_all(dev);
b0e5ddf3 2330 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2331
2332 return 0;
2333}
2334
07144428
DL		 2335struct pipe_crc_info {
2336 const char *name;
2337 struct drm_device *dev;
2338 enum pipe pipe;
2339};
2340
2341static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2342{
be5c7a90
DL		 2343 struct pipe_crc_info *info = inode->i_private;
2344 struct drm_i915_private *dev_priv = info->dev->dev_private;
2345 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2346
7eb1c496
DV		 2347 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2348 return -ENODEV;
2349
d538bbdf
DL		 2350 spin_lock_irq(&pipe_crc->lock);
2351
2352 if (pipe_crc->opened) {
2353 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2354 return -EBUSY; /* already open */
2355 }
2356
d538bbdf 2357 pipe_crc->opened = true;
07144428
DL		 2358 filep->private_data = inode->i_private;
2359
d538bbdf
DL		 2360 spin_unlock_irq(&pipe_crc->lock);
2361
07144428
DL		 2362 return 0;
2363}
2364
2365static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2366{
be5c7a90
DL		 2367 struct pipe_crc_info *info = inode->i_private;
2368 struct drm_i915_private *dev_priv = info->dev->dev_private;
2369 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2370
d538bbdf
DL		 2371 spin_lock_irq(&pipe_crc->lock);
2372 pipe_crc->opened = false;
2373 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2374
07144428
DL		 2375 return 0;
2376}
2377
2378/* (6 fields, 8 chars each, space separated (5) + '\n') */
2379#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2380/* account for \'0' */
2381#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2382
2383static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2384{
d538bbdf
DL		 2385 assert_spin_locked(&pipe_crc->lock);
2386 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2387 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2388}
2389
2390static ssize_t
2391i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2392 loff_t *pos)
2393{
2394 struct pipe_crc_info *info = filep->private_data;
2395 struct drm_device *dev = info->dev;
2396 struct drm_i915_private *dev_priv = dev->dev_private;
2397 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2398 char buf[PIPE_CRC_BUFFER_LEN];
2399 int head, tail, n_entries, n;
2400 ssize_t bytes_read;
2401
2402 /*
2403 * Don't allow user space to provide buffers not big enough to hold
2404 * a line of data.
2405 */
2406 if (count < PIPE_CRC_LINE_LEN)
2407 return -EINVAL;
2408
2409 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2410 return 0;
07144428
DL		 2411
2412 /* nothing to read */
d538bbdf 2413 spin_lock_irq(&pipe_crc->lock);
07144428 2414 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2415 int ret;
2416
2417 if (filep->f_flags & O_NONBLOCK) {
2418 spin_unlock_irq(&pipe_crc->lock);
07144428 2419 return -EAGAIN;
d538bbdf 2420 }
07144428 2421
d538bbdf
DL		 2422 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2423 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2424 if (ret) {
2425 spin_unlock_irq(&pipe_crc->lock);
2426 return ret;
2427 }
8bf1e9f1
SH		 2428 }
2429
07144428 2430 /* We now have one or more entries to read */
d538bbdf
DL		 2431 head = pipe_crc->head;
2432 tail = pipe_crc->tail;
07144428
DL		 2433 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2434 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2435 spin_unlock_irq(&pipe_crc->lock);
2436
07144428
DL		 2437 bytes_read = 0;
2438 n = 0;
2439 do {
b2c88f5b 2440 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2441 int ret;
8bf1e9f1 2442
07144428
DL		 2443 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2444 "%8u %8x %8x %8x %8x %8x\n",
2445 entry->frame, entry->crc[0],
2446 entry->crc[1], entry->crc[2],
2447 entry->crc[3], entry->crc[4]);
2448
2449 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2450 buf, PIPE_CRC_LINE_LEN);
2451 if (ret == PIPE_CRC_LINE_LEN)
2452 return -EFAULT;
b2c88f5b
DL		 2453
2454 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2455 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2456 n++;
2457 } while (--n_entries);
8bf1e9f1 2458
d538bbdf
DL		 2459 spin_lock_irq(&pipe_crc->lock);
2460 pipe_crc->tail = tail;
2461 spin_unlock_irq(&pipe_crc->lock);
2462
07144428
DL		 2463 return bytes_read;
2464}
2465
2466static const struct file_operations i915_pipe_crc_fops = {
2467 .owner = THIS_MODULE,
2468 .open = i915_pipe_crc_open,
2469 .read = i915_pipe_crc_read,
2470 .release = i915_pipe_crc_release,
2471};
2472
2473static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2474 {
2475 .name = "i915_pipe_A_crc",
2476 .pipe = PIPE_A,
2477 },
2478 {
2479 .name = "i915_pipe_B_crc",
2480 .pipe = PIPE_B,
2481 },
2482 {
2483 .name = "i915_pipe_C_crc",
2484 .pipe = PIPE_C,
2485 },
2486};
2487
2488static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2489 enum pipe pipe)
2490{
2491 struct drm_device *dev = minor->dev;
2492 struct dentry *ent;
2493 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2494
2495 info->dev = dev;
2496 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2497 &i915_pipe_crc_fops);
f3c5fe97
WY		 2498 if (!ent)
2499 return -ENOMEM;
07144428
DL		 2500
2501 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2502}
2503
e8dfcf78 2504static const char * const pipe_crc_sources[] = {
926321d5
DV		 2505 "none",
2506 "plane1",
2507 "plane2",
2508 "pf",
5b3a856b 2509 "pipe",
3d099a05
DV		 2510 "TV",
2511 "DP-B",
2512 "DP-C",
2513 "DP-D",
46a19188 2514 "auto",
926321d5
DV		 2515};
2516
2517static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2518{
2519 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2520 return pipe_crc_sources[source];
2521}
2522
bd9db02f 2523static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2524{
2525 struct drm_device *dev = m->private;
2526 struct drm_i915_private *dev_priv = dev->dev_private;
2527 int i;
2528
2529 for (i = 0; i < I915_MAX_PIPES; i++)
2530 seq_printf(m, "%c %s\n", pipe_name(i),
2531 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2532
2533 return 0;
2534}
2535
bd9db02f 2536static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2537{
2538 struct drm_device *dev = inode->i_private;
2539
bd9db02f 2540 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2541}
2542
46a19188 2543static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2544 uint32_t *val)
2545{
46a19188
DV		 2546 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2547 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2548
2549 switch (*source) {
52f843f6
DV		 2550 case INTEL_PIPE_CRC_SOURCE_PIPE:
2551 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2552 break;
2553 case INTEL_PIPE_CRC_SOURCE_NONE:
2554 *val = 0;
2555 break;
2556 default:
2557 return -EINVAL;
2558 }
2559
2560 return 0;
2561}
2562
46a19188
DV		 2563static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2564 enum intel_pipe_crc_source *source)
2565{
2566 struct intel_encoder *encoder;
2567 struct intel_crtc *crtc;
26756809 2568 struct intel_digital_port *dig_port;
46a19188
DV		 2569 int ret = 0;
2570
2571 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2572
2573 mutex_lock(&dev->mode_config.mutex);
2574 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2575 base.head) {
2576 if (!encoder->base.crtc)
2577 continue;
2578
2579 crtc = to_intel_crtc(encoder->base.crtc);
2580
2581 if (crtc->pipe != pipe)
2582 continue;
2583
2584 switch (encoder->type) {
2585 case INTEL_OUTPUT_TVOUT:
2586 *source = INTEL_PIPE_CRC_SOURCE_TV;
2587 break;
2588 case INTEL_OUTPUT_DISPLAYPORT:
2589 case INTEL_OUTPUT_EDP:
26756809
DV		 2590 dig_port = enc_to_dig_port(&encoder->base);
2591 switch (dig_port->port) {
2592 case PORT_B:
2593 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2594 break;
2595 case PORT_C:
2596 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2597 break;
2598 case PORT_D:
2599 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2600 break;
2601 default:
2602 WARN(1, "nonexisting DP port %c\n",
2603 port_name(dig_port->port));
2604 break;
2605 }
46a19188
DV		 2606 break;
2607 }
2608 }
2609 mutex_unlock(&dev->mode_config.mutex);
2610
2611 return ret;
2612}
2613
2614static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2615 enum pipe pipe,
2616 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2617 uint32_t *val)
2618{
8d2f24ca
DV		 2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620 bool need_stable_symbols = false;
2621
46a19188
DV		 2622 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2623 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2624 if (ret)
2625 return ret;
2626 }
2627
2628 switch (*source) {
7ac0129b
DV		 2629 case INTEL_PIPE_CRC_SOURCE_PIPE:
2630 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2631 break;
2632 case INTEL_PIPE_CRC_SOURCE_DP_B:
2633 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2634 need_stable_symbols = true;
7ac0129b
DV		 2635 break;
2636 case INTEL_PIPE_CRC_SOURCE_DP_C:
2637 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2638 need_stable_symbols = true;
7ac0129b
DV		 2639 break;
2640 case INTEL_PIPE_CRC_SOURCE_NONE:
2641 *val = 0;
2642 break;
2643 default:
2644 return -EINVAL;
2645 }
2646
8d2f24ca
DV		 2647 /*
2648 * When the pipe CRC tap point is after the transcoders we need
2649 * to tweak symbol-level features to produce a deterministic series of
2650 * symbols for a given frame. We need to reset those features only once
2651 * a frame (instead of every nth symbol):
2652 * - DC-balance: used to ensure a better clock recovery from the data
2653 * link (SDVO)
2654 * - DisplayPort scrambling: used for EMI reduction
2655 */
2656 if (need_stable_symbols) {
2657 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2658
8d2f24ca
DV		 2659 tmp |= DC_BALANCE_RESET_VLV;
2660 if (pipe == PIPE_A)
2661 tmp |= PIPE_A_SCRAMBLE_RESET;
2662 else
2663 tmp |= PIPE_B_SCRAMBLE_RESET;
2664
2665 I915_WRITE(PORT_DFT2_G4X, tmp);
2666 }
2667
7ac0129b
DV		 2668 return 0;
2669}
2670
4b79ebf7 2671static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2672 enum pipe pipe,
2673 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2674 uint32_t *val)
2675{
84093603
DV		 2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 bool need_stable_symbols = false;
2678
46a19188
DV		 2679 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2680 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2681 if (ret)
2682 return ret;
2683 }
2684
2685 switch (*source) {
4b79ebf7
DV		 2686 case INTEL_PIPE_CRC_SOURCE_PIPE:
2687 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2688 break;
2689 case INTEL_PIPE_CRC_SOURCE_TV:
2690 if (!SUPPORTS_TV(dev))
2691 return -EINVAL;
2692 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2693 break;
2694 case INTEL_PIPE_CRC_SOURCE_DP_B:
2695 if (!IS_G4X(dev))
2696 return -EINVAL;
2697 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2698 need_stable_symbols = true;
4b79ebf7
DV		 2699 break;
2700 case INTEL_PIPE_CRC_SOURCE_DP_C:
2701 if (!IS_G4X(dev))
2702 return -EINVAL;
2703 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2704 need_stable_symbols = true;
4b79ebf7
DV		 2705 break;
2706 case INTEL_PIPE_CRC_SOURCE_DP_D:
2707 if (!IS_G4X(dev))
2708 return -EINVAL;
2709 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2710 need_stable_symbols = true;
4b79ebf7
DV		 2711 break;
2712 case INTEL_PIPE_CRC_SOURCE_NONE:
2713 *val = 0;
2714 break;
2715 default:
2716 return -EINVAL;
2717 }
2718
84093603
DV		 2719 /*
2720 * When the pipe CRC tap point is after the transcoders we need
2721 * to tweak symbol-level features to produce a deterministic series of
2722 * symbols for a given frame. We need to reset those features only once
2723 * a frame (instead of every nth symbol):
2724 * - DC-balance: used to ensure a better clock recovery from the data
2725 * link (SDVO)
2726 * - DisplayPort scrambling: used for EMI reduction
2727 */
2728 if (need_stable_symbols) {
2729 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2730
2731 WARN_ON(!IS_G4X(dev));
2732
2733 I915_WRITE(PORT_DFT_I9XX,
2734 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2735
2736 if (pipe == PIPE_A)
2737 tmp |= PIPE_A_SCRAMBLE_RESET;
2738 else
2739 tmp |= PIPE_B_SCRAMBLE_RESET;
2740
2741 I915_WRITE(PORT_DFT2_G4X, tmp);
2742 }
2743
4b79ebf7
DV		 2744 return 0;
2745}
2746
8d2f24ca
DV		 2747static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2748 enum pipe pipe)
2749{
2750 struct drm_i915_private *dev_priv = dev->dev_private;
2751 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2752
2753 if (pipe == PIPE_A)
2754 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2755 else
2756 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2757 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2758 tmp &= ~DC_BALANCE_RESET_VLV;
2759 I915_WRITE(PORT_DFT2_G4X, tmp);
2760
2761}
2762
84093603
DV		 2763static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2764 enum pipe pipe)
2765{
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2768
2769 if (pipe == PIPE_A)
2770 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2771 else
2772 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2773 I915_WRITE(PORT_DFT2_G4X, tmp);
2774
2775 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2776 I915_WRITE(PORT_DFT_I9XX,
2777 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2778 }
2779}
2780
46a19188 2781static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2782 uint32_t *val)
2783{
46a19188
DV		 2784 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2785 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2786
2787 switch (*source) {
5b3a856b
DV		 2788 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2789 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2790 break;
2791 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2792 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2793 break;
5b3a856b
DV		 2794 case INTEL_PIPE_CRC_SOURCE_PIPE:
2795 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2796 break;
3d099a05 2797 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2798 *val = 0;
2799 break;
3d099a05
DV		 2800 default:
2801 return -EINVAL;
5b3a856b
DV		 2802 }
2803
2804 return 0;
2805}
2806
46a19188 2807static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2808 uint32_t *val)
2809{
46a19188
DV		 2810 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2811 *source = INTEL_PIPE_CRC_SOURCE_PF;
2812
2813 switch (*source) {
5b3a856b
DV		 2814 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2815 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2816 break;
2817 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2818 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2819 break;
2820 case INTEL_PIPE_CRC_SOURCE_PF:
2821 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2822 break;
3d099a05 2823 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2824 *val = 0;
2825 break;
3d099a05
DV		 2826 default:
2827 return -EINVAL;
5b3a856b
DV		 2828 }
2829
2830 return 0;
2831}
2832
926321d5
DV		 2833static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2834 enum intel_pipe_crc_source source)
2835{
2836 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2837 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2838 u32 val = 0; /* shut up gcc */
5b3a856b 2839 int ret;
926321d5 2840
cc3da175
DL		 2841 if (pipe_crc->source == source)
2842 return 0;
2843
ae676fcd
DL		 2844 /* forbid changing the source without going back to 'none' */
2845 if (pipe_crc->source && source)
2846 return -EINVAL;
2847
52f843f6 2848 if (IS_GEN2(dev))
46a19188 2849 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2850 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2851 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2852 else if (IS_VALLEYVIEW(dev))
46a19188 2853 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2854 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2855 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2856 else
46a19188 2857 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2858
2859 if (ret != 0)
2860 return ret;
2861
4b584369
DL		 2862 /* none -> real source transition */
2863 if (source) {
7cd6ccff
DL		 2864 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2865 pipe_name(pipe), pipe_crc_source_name(source));
2866
e5f75aca
DL		 2867 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2868 INTEL_PIPE_CRC_ENTRIES_NR,
2869 GFP_KERNEL);
2870 if (!pipe_crc->entries)
2871 return -ENOMEM;
2872
d538bbdf
DL		 2873 spin_lock_irq(&pipe_crc->lock);
2874 pipe_crc->head = 0;
2875 pipe_crc->tail = 0;
2876 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2877 }
2878
cc3da175 2879 pipe_crc->source = source;
926321d5 2880
926321d5
DV		 2881 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2882 POSTING_READ(PIPE_CRC_CTL(pipe));
2883
e5f75aca
DL		 2884 /* real source -> none transition */
2885 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2886 struct intel_pipe_crc_entry *entries;
2887
7cd6ccff
DL		 2888 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2889 pipe_name(pipe));
2890
bcf17ab2
DV		 2891 intel_wait_for_vblank(dev, pipe);
2892
d538bbdf
DL		 2893 spin_lock_irq(&pipe_crc->lock);
2894 entries = pipe_crc->entries;
e5f75aca 2895 pipe_crc->entries = NULL;
d538bbdf
DL		 2896 spin_unlock_irq(&pipe_crc->lock);
2897
2898 kfree(entries);
84093603
DV		 2899
2900 if (IS_G4X(dev))
2901 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2902 else if (IS_VALLEYVIEW(dev))
2903 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2904 }
2905
926321d5
DV		 2906 return 0;
2907}
2908
2909/*
2910 * Parse pipe CRC command strings:
b94dec87
DL		 2911 * command: wsp* object wsp+ name wsp+ source wsp*
2912 * object: 'pipe'
2913 * name: (A | B | C)
926321d5
DV		 2914 * source: (none | plane1 | plane2 | pf)
2915 * wsp: (#0x20 | #0x9 | #0xA)+
2916 *
2917 * eg.:
b94dec87
DL		 2918 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2919 * "pipe A none" -> Stop CRC
926321d5 2920 */
bd9db02f 2921static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2922{
2923 int n_words = 0;
2924
2925 while (*buf) {
2926 char *end;
2927
2928 /* skip leading white space */
2929 buf = skip_spaces(buf);
2930 if (!*buf)
2931 break; /* end of buffer */
2932
2933 /* find end of word */
2934 for (end = buf; *end && !isspace(*end); end++)
2935 ;
2936
2937 if (n_words == max_words) {
2938 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2939 max_words);
2940 return -EINVAL; /* ran out of words[] before bytes */
2941 }
2942
2943 if (*end)
2944 *end++ = '\0';
2945 words[n_words++] = buf;
2946 buf = end;
2947 }
2948
2949 return n_words;
2950}
2951
b94dec87
DL		 2952enum intel_pipe_crc_object {
2953 PIPE_CRC_OBJECT_PIPE,
2954};
2955
e8dfcf78 2956static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2957 "pipe",
2958};
2959
2960static int
bd9db02f 2961display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2962{
2963 int i;
2964
2965 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2966 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2967 *o = i;
b94dec87
DL		 2968 return 0;
2969 }
2970
2971 return -EINVAL;
2972}
2973
bd9db02f 2974static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2975{
2976 const char name = buf[0];
2977
2978 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2979 return -EINVAL;
2980
2981 *pipe = name - 'A';
2982
2983 return 0;
2984}
2985
2986static int
bd9db02f 2987display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 2988{
2989 int i;
2990
2991 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2992 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 2993 *s = i;
926321d5
DV		 2994 return 0;
2995 }
2996
2997 return -EINVAL;
2998}
2999
bd9db02f 3000static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3001{
b94dec87 3002#define N_WORDS 3
926321d5 3003 int n_words;
b94dec87 3004 char *words[N_WORDS];
926321d5 3005 enum pipe pipe;
b94dec87 3006 enum intel_pipe_crc_object object;
926321d5
DV		 3007 enum intel_pipe_crc_source source;
3008
bd9db02f 3009 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3010 if (n_words != N_WORDS) {
3011 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3012 N_WORDS);
3013 return -EINVAL;
3014 }
3015
bd9db02f 3016 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3017 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3018 return -EINVAL;
3019 }
3020
bd9db02f 3021 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3022 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3023 return -EINVAL;
3024 }
3025
bd9db02f 3026 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3027 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3028 return -EINVAL;
3029 }
3030
3031 return pipe_crc_set_source(dev, pipe, source);
3032}
3033
bd9db02f
DL		 3034static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3035 size_t len, loff_t *offp)
926321d5
DV		 3036{
3037 struct seq_file *m = file->private_data;
3038 struct drm_device *dev = m->private;
3039 char *tmpbuf;
3040 int ret;
3041
3042 if (len == 0)
3043 return 0;
3044
3045 if (len > PAGE_SIZE - 1) {
3046 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3047 PAGE_SIZE);
3048 return -E2BIG;
3049 }
3050
3051 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3052 if (!tmpbuf)
3053 return -ENOMEM;
3054
3055 if (copy_from_user(tmpbuf, ubuf, len)) {
3056 ret = -EFAULT;
3057 goto out;
3058 }
3059 tmpbuf[len] = '\0';
3060
bd9db02f 3061 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3062
3063out:
3064 kfree(tmpbuf);
3065 if (ret < 0)
3066 return ret;
3067
3068 *offp += len;
3069 return len;
3070}
3071
bd9db02f 3072static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3073 .owner = THIS_MODULE,
bd9db02f 3074 .open = display_crc_ctl_open,
926321d5
DV		 3075 .read = seq_read,
3076 .llseek = seq_lseek,
3077 .release = single_release,
bd9db02f 3078 .write = display_crc_ctl_write
926321d5
DV		 3079};
3080
369a1342
VS		 3081static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3082{
3083 struct drm_device *dev = m->private;
3084 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3085 int level;
3086
3087 drm_modeset_lock_all(dev);
3088
3089 for (level = 0; level < num_levels; level++) {
3090 unsigned int latency = wm[level];
3091
3092 /* WM1+ latency values in 0.5us units */
3093 if (level > 0)
3094 latency *= 5;
3095
3096 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3097 level, wm[level],
3098 latency / 10, latency % 10);
3099 }
3100
3101 drm_modeset_unlock_all(dev);
3102}
3103
3104static int pri_wm_latency_show(struct seq_file *m, void *data)
3105{
3106 struct drm_device *dev = m->private;
3107
3108 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3109
3110 return 0;
3111}
3112
3113static int spr_wm_latency_show(struct seq_file *m, void *data)
3114{
3115 struct drm_device *dev = m->private;
3116
3117 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3118
3119 return 0;
3120}
3121
3122static int cur_wm_latency_show(struct seq_file *m, void *data)
3123{
3124 struct drm_device *dev = m->private;
3125
3126 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3127
3128 return 0;
3129}
3130
3131static int pri_wm_latency_open(struct inode *inode, struct file *file)
3132{
3133 struct drm_device *dev = inode->i_private;
3134
3135 if (!HAS_PCH_SPLIT(dev))
3136 return -ENODEV;
3137
3138 return single_open(file, pri_wm_latency_show, dev);
3139}
3140
3141static int spr_wm_latency_open(struct inode *inode, struct file *file)
3142{
3143 struct drm_device *dev = inode->i_private;
3144
3145 if (!HAS_PCH_SPLIT(dev))
3146 return -ENODEV;
3147
3148 return single_open(file, spr_wm_latency_show, dev);
3149}
3150
3151static int cur_wm_latency_open(struct inode *inode, struct file *file)
3152{
3153 struct drm_device *dev = inode->i_private;
3154
3155 if (!HAS_PCH_SPLIT(dev))
3156 return -ENODEV;
3157
3158 return single_open(file, cur_wm_latency_show, dev);
3159}
3160
3161static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3162 size_t len, loff_t *offp, uint16_t wm[5])
3163{
3164 struct seq_file *m = file->private_data;
3165 struct drm_device *dev = m->private;
3166 uint16_t new[5] = { 0 };
3167 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3168 int level;
3169 int ret;
3170 char tmp[32];
3171
3172 if (len >= sizeof(tmp))
3173 return -EINVAL;
3174
3175 if (copy_from_user(tmp, ubuf, len))
3176 return -EFAULT;
3177
3178 tmp[len] = '\0';
3179
3180 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3181 if (ret != num_levels)
3182 return -EINVAL;
3183
3184 drm_modeset_lock_all(dev);
3185
3186 for (level = 0; level < num_levels; level++)
3187 wm[level] = new[level];
3188
3189 drm_modeset_unlock_all(dev);
3190
3191 return len;
3192}
3193
3194
3195static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3196 size_t len, loff_t *offp)
3197{
3198 struct seq_file *m = file->private_data;
3199 struct drm_device *dev = m->private;
3200
3201 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3202}
3203
3204static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3205 size_t len, loff_t *offp)
3206{
3207 struct seq_file *m = file->private_data;
3208 struct drm_device *dev = m->private;
3209
3210 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3211}
3212
3213static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3214 size_t len, loff_t *offp)
3215{
3216 struct seq_file *m = file->private_data;
3217 struct drm_device *dev = m->private;
3218
3219 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3220}
3221
3222static const struct file_operations i915_pri_wm_latency_fops = {
3223 .owner = THIS_MODULE,
3224 .open = pri_wm_latency_open,
3225 .read = seq_read,
3226 .llseek = seq_lseek,
3227 .release = single_release,
3228 .write = pri_wm_latency_write
3229};
3230
3231static const struct file_operations i915_spr_wm_latency_fops = {
3232 .owner = THIS_MODULE,
3233 .open = spr_wm_latency_open,
3234 .read = seq_read,
3235 .llseek = seq_lseek,
3236 .release = single_release,
3237 .write = spr_wm_latency_write
3238};
3239
3240static const struct file_operations i915_cur_wm_latency_fops = {
3241 .owner = THIS_MODULE,
3242 .open = cur_wm_latency_open,
3243 .read = seq_read,
3244 .llseek = seq_lseek,
3245 .release = single_release,
3246 .write = cur_wm_latency_write
3247};
3248
647416f9
KC		 3249static int
3250i915_wedged_get(void *data, u64 *val)
f3cd474b 3251{
647416f9 3252 struct drm_device *dev = data;
e277a1f8 3253 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3254
647416f9 3255 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3256
647416f9 3257 return 0;
f3cd474b
CW		 3258}
3259
647416f9
KC		 3260static int
3261i915_wedged_set(void *data, u64 val)
f3cd474b 3262{
647416f9 3263 struct drm_device *dev = data;
d46c0517
ID		 3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265
3266 intel_runtime_pm_get(dev_priv);
f3cd474b 3267
58174462
MK		 3268 i915_handle_error(dev, val,
3269 "Manually setting wedged to %llu", val);
d46c0517
ID		 3270
3271 intel_runtime_pm_put(dev_priv);
3272
647416f9 3273 return 0;
f3cd474b
CW		 3274}
3275
647416f9
KC		 3276DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3277 i915_wedged_get, i915_wedged_set,
3a3b4f98 3278 "%llu\n");
f3cd474b 3279
647416f9
KC		 3280static int
3281i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3282{
647416f9 3283 struct drm_device *dev = data;
e277a1f8 3284 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3285
647416f9 3286 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3287
647416f9 3288 return 0;
e5eb3d63
DV		 3289}
3290
647416f9
KC		 3291static int
3292i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3293{
647416f9 3294 struct drm_device *dev = data;
e5eb3d63 3295 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3296 int ret;
e5eb3d63 3297
647416f9 3298 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3299
22bcfc6a
DV		 3300 ret = mutex_lock_interruptible(&dev->struct_mutex);
3301 if (ret)
3302 return ret;
3303
99584db3 3304 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3305 mutex_unlock(&dev->struct_mutex);
3306
647416f9 3307 return 0;
e5eb3d63
DV		 3308}
3309
647416f9
KC		 3310DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3311 i915_ring_stop_get, i915_ring_stop_set,
3312 "0x%08llx\n");
d5442303 3313
094f9a54
CW		 3314static int
3315i915_ring_missed_irq_get(void *data, u64 *val)
3316{
3317 struct drm_device *dev = data;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319
3320 *val = dev_priv->gpu_error.missed_irq_rings;
3321 return 0;
3322}
3323
3324static int
3325i915_ring_missed_irq_set(void *data, u64 val)
3326{
3327 struct drm_device *dev = data;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 int ret;
3330
3331 /* Lock against concurrent debugfs callers */
3332 ret = mutex_lock_interruptible(&dev->struct_mutex);
3333 if (ret)
3334 return ret;
3335 dev_priv->gpu_error.missed_irq_rings = val;
3336 mutex_unlock(&dev->struct_mutex);
3337
3338 return 0;
3339}
3340
3341DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3342 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3343 "0x%08llx\n");
3344
3345static int
3346i915_ring_test_irq_get(void *data, u64 *val)
3347{
3348 struct drm_device *dev = data;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350
3351 *val = dev_priv->gpu_error.test_irq_rings;
3352
3353 return 0;
3354}
3355
3356static int
3357i915_ring_test_irq_set(void *data, u64 val)
3358{
3359 struct drm_device *dev = data;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int ret;
3362
3363 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3364
3365 /* Lock against concurrent debugfs callers */
3366 ret = mutex_lock_interruptible(&dev->struct_mutex);
3367 if (ret)
3368 return ret;
3369
3370 dev_priv->gpu_error.test_irq_rings = val;
3371 mutex_unlock(&dev->struct_mutex);
3372
3373 return 0;
3374}
3375
3376DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3377 i915_ring_test_irq_get, i915_ring_test_irq_set,
3378 "0x%08llx\n");
3379
dd624afd
CW		 3380#define DROP_UNBOUND 0x1
3381#define DROP_BOUND 0x2
3382#define DROP_RETIRE 0x4
3383#define DROP_ACTIVE 0x8
3384#define DROP_ALL (DROP_UNBOUND | \
3385 DROP_BOUND | \
3386 DROP_RETIRE | \
3387 DROP_ACTIVE)
647416f9
KC		 3388static int
3389i915_drop_caches_get(void *data, u64 *val)
dd624afd 3390{
647416f9 3391 *val = DROP_ALL;
dd624afd 3392
647416f9 3393 return 0;
dd624afd
CW		 3394}
3395
647416f9
KC		 3396static int
3397i915_drop_caches_set(void *data, u64 val)
dd624afd 3398{
647416f9 3399 struct drm_device *dev = data;
dd624afd
CW		 3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 3402 struct i915_address_space *vm;
3403 struct i915_vma *vma, *x;
647416f9 3404 int ret;
dd624afd 3405
2f9fe5ff 3406 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3407
3408 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3409 * on ioctls on -EAGAIN. */
3410 ret = mutex_lock_interruptible(&dev->struct_mutex);
3411 if (ret)
3412 return ret;
3413
3414 if (val & DROP_ACTIVE) {
3415 ret = i915_gpu_idle(dev);
3416 if (ret)
3417 goto unlock;
3418 }
3419
3420 if (val & (DROP_RETIRE | DROP_ACTIVE))
3421 i915_gem_retire_requests(dev);
3422
3423 if (val & DROP_BOUND) {
ca191b13
BW		 3424 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3425 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3426 mm_list) {
d7f46fc4 3427 if (vma->pin_count)
ca191b13
BW		 3428 continue;
3429
3430 ret = i915_vma_unbind(vma);
3431 if (ret)
3432 goto unlock;
3433 }
31a46c9c 3434 }
dd624afd
CW		 3435 }
3436
3437 if (val & DROP_UNBOUND) {
35c20a60
BW		 3438 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3439 global_list)
dd624afd
CW		 3440 if (obj->pages_pin_count == 0) {
3441 ret = i915_gem_object_put_pages(obj);
3442 if (ret)
3443 goto unlock;
3444 }
3445 }
3446
3447unlock:
3448 mutex_unlock(&dev->struct_mutex);
3449
647416f9 3450 return ret;
dd624afd
CW		 3451}
3452
647416f9
KC		 3453DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3454 i915_drop_caches_get, i915_drop_caches_set,
3455 "0x%08llx\n");
dd624afd 3456
647416f9
KC		 3457static int
3458i915_max_freq_get(void *data, u64 *val)
358733e9 3459{
647416f9 3460 struct drm_device *dev = data;
e277a1f8 3461 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3462 int ret;
004777cb
DV		 3463
3464 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3465 return -ENODEV;
3466
5c9669ce
TR		 3467 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3468
4fc688ce 3469 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3470 if (ret)
3471 return ret;
358733e9 3472
0a073b84 3473 if (IS_VALLEYVIEW(dev))
b39fb297 3474 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 3475 else
b39fb297 3476 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3477 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3478
647416f9 3479 return 0;
358733e9
JB		 3480}
3481
647416f9
KC		 3482static int
3483i915_max_freq_set(void *data, u64 val)
358733e9 3484{
647416f9 3485 struct drm_device *dev = data;
358733e9 3486 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3487 u32 rp_state_cap, hw_max, hw_min;
647416f9 3488 int ret;
004777cb
DV		 3489
3490 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3491 return -ENODEV;
358733e9 3492
5c9669ce
TR		 3493 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3494
647416f9 3495 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3496
4fc688ce 3497 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3498 if (ret)
3499 return ret;
3500
358733e9
JB		 3501 /*
3502 * Turbo will still be enabled, but won't go above the set value.
3503 */
0a073b84 3504 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3505 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3506
3507 hw_max = valleyview_rps_max_freq(dev_priv);
3508 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3509 } else {
3510 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3511
3512 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3513 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3514 hw_min = (rp_state_cap >> 16) & 0xff;
3515 }
3516
b39fb297 3517 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 3518 mutex_unlock(&dev_priv->rps.hw_lock);
3519 return -EINVAL;
0a073b84
JB		 3520 }
3521
b39fb297 3522 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 3523
3524 if (IS_VALLEYVIEW(dev))
3525 valleyview_set_rps(dev, val);
3526 else
3527 gen6_set_rps(dev, val);
3528
4fc688ce 3529 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3530
647416f9 3531 return 0;
358733e9
JB		 3532}
3533
647416f9
KC		 3534DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3535 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3536 "%llu\n");
358733e9 3537
647416f9
KC		 3538static int
3539i915_min_freq_get(void *data, u64 *val)
1523c310 3540{
647416f9 3541 struct drm_device *dev = data;
e277a1f8 3542 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3543 int ret;
004777cb
DV		 3544
3545 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3546 return -ENODEV;
3547
5c9669ce
TR		 3548 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3549
4fc688ce 3550 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3551 if (ret)
3552 return ret;
1523c310 3553
0a073b84 3554 if (IS_VALLEYVIEW(dev))
b39fb297 3555 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 3556 else
b39fb297 3557 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3558 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3559
647416f9 3560 return 0;
1523c310
JB		 3561}
3562
647416f9
KC		 3563static int
3564i915_min_freq_set(void *data, u64 val)
1523c310 3565{
647416f9 3566 struct drm_device *dev = data;
1523c310 3567 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3568 u32 rp_state_cap, hw_max, hw_min;
647416f9 3569 int ret;
004777cb
DV		 3570
3571 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3572 return -ENODEV;
1523c310 3573
5c9669ce
TR		 3574 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3575
647416f9 3576 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3577
4fc688ce 3578 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3579 if (ret)
3580 return ret;
3581
1523c310
JB		 3582 /*
3583 * Turbo will still be enabled, but won't go below the set value.
3584 */
0a073b84 3585 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3586 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3587
3588 hw_max = valleyview_rps_max_freq(dev_priv);
3589 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3590 } else {
3591 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3592
3593 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3594 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3595 hw_min = (rp_state_cap >> 16) & 0xff;
3596 }
3597
b39fb297 3598 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 3599 mutex_unlock(&dev_priv->rps.hw_lock);
3600 return -EINVAL;
0a073b84 3601 }
dd0a1aa1 3602
b39fb297 3603 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 3604
3605 if (IS_VALLEYVIEW(dev))
3606 valleyview_set_rps(dev, val);
3607 else
3608 gen6_set_rps(dev, val);
3609
4fc688ce 3610 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3611
647416f9 3612 return 0;
1523c310
JB		 3613}
3614
647416f9
KC		 3615DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3616 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3617 "%llu\n");
1523c310 3618
647416f9
KC		 3619static int
3620i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3621{
647416f9 3622 struct drm_device *dev = data;
e277a1f8 3623 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3624 u32 snpcr;
647416f9 3625 int ret;
07b7ddd9 3626
004777cb
DV		 3627 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3628 return -ENODEV;
3629
22bcfc6a
DV		 3630 ret = mutex_lock_interruptible(&dev->struct_mutex);
3631 if (ret)
3632 return ret;
c8c8fb33 3633 intel_runtime_pm_get(dev_priv);
22bcfc6a 3634
07b7ddd9 3635 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 3636
3637 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 3638 mutex_unlock(&dev_priv->dev->struct_mutex);
3639
647416f9 3640 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3641
647416f9 3642 return 0;
07b7ddd9
JB		 3643}
3644
647416f9
KC		 3645static int
3646i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3647{
647416f9 3648 struct drm_device *dev = data;
07b7ddd9 3649 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3650 u32 snpcr;
07b7ddd9 3651
004777cb
DV		 3652 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3653 return -ENODEV;
3654
647416f9 3655 if (val > 3)
07b7ddd9
JB		 3656 return -EINVAL;
3657
c8c8fb33 3658 intel_runtime_pm_get(dev_priv);
647416f9 3659 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3660
3661 /* Update the cache sharing policy here as well */
3662 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3663 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3664 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3665 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3666
c8c8fb33 3667 intel_runtime_pm_put(dev_priv);
647416f9 3668 return 0;
07b7ddd9
JB		 3669}
3670
647416f9
KC		 3671DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3672 i915_cache_sharing_get, i915_cache_sharing_set,
3673 "%llu\n");
07b7ddd9 3674
6d794d42
BW		 3675static int i915_forcewake_open(struct inode *inode, struct file *file)
3676{
3677 struct drm_device *dev = inode->i_private;
3678 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3679
075edca4 3680 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3681 return 0;
3682
c8d9a590 3683 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3684
3685 return 0;
3686}
3687
c43b5634 3688static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3689{
3690 struct drm_device *dev = inode->i_private;
3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692
075edca4 3693 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3694 return 0;
3695
c8d9a590 3696 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3697
3698 return 0;
3699}
3700
3701static const struct file_operations i915_forcewake_fops = {
3702 .owner = THIS_MODULE,
3703 .open = i915_forcewake_open,
3704 .release = i915_forcewake_release,
3705};
3706
3707static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3708{
3709 struct drm_device *dev = minor->dev;
3710 struct dentry *ent;
3711
3712 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3713 S_IRUSR,
6d794d42
BW		 3714 root, dev,
3715 &i915_forcewake_fops);
f3c5fe97
WY		 3716 if (!ent)
3717 return -ENOMEM;
6d794d42 3718
8eb57294 3719 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3720}
3721
6a9c308d
DV		 3722static int i915_debugfs_create(struct dentry *root,
3723 struct drm_minor *minor,
3724 const char *name,
3725 const struct file_operations *fops)
07b7ddd9
JB		 3726{
3727 struct drm_device *dev = minor->dev;
3728 struct dentry *ent;
3729
6a9c308d 3730 ent = debugfs_create_file(name,
07b7ddd9
JB		 3731 S_IRUGO | S_IWUSR,
3732 root, dev,
6a9c308d 3733 fops);
f3c5fe97
WY		 3734 if (!ent)
3735 return -ENOMEM;
07b7ddd9 3736
6a9c308d 3737 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3738}
3739
06c5bf8c 3740static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3741 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3742 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3743 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3744 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3745 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3746 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3747 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3748 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3749 {"i915_gem_request", i915_gem_request_info, 0},
3750 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3751 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3752 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3753 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3754 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3755 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3756 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1 3757 {"i915_rstdby_delays", i915_rstdby_delays, 0},
adb4bd12 3758 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1
JB		 3759 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3760 {"i915_inttoext_table", i915_inttoext_table, 0},
3761 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3762 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3763 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 3764 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 3765 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3766 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3767 {"i915_sr_status", i915_sr_status, 0},
44834a67 3768 {"i915_opregion", i915_opregion, 0},
37811fcc 3769 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3770 {"i915_context_status", i915_context_status, 0},
6d794d42 3771 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3772 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3773 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 3774 {"i915_llc", i915_llc, 0},
e91fd8c6 3775 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 3776 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 3777 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3778 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3779 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 3780 {"i915_display_info", i915_display_info, 0},
2017263e 3781};
27c202ad 3782#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3783
06c5bf8c 3784static const struct i915_debugfs_files {
34b9674c
DV		 3785 const char *name;
3786 const struct file_operations *fops;
3787} i915_debugfs_files[] = {
3788 {"i915_wedged", &i915_wedged_fops},
3789 {"i915_max_freq", &i915_max_freq_fops},
3790 {"i915_min_freq", &i915_min_freq_fops},
3791 {"i915_cache_sharing", &i915_cache_sharing_fops},
3792 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3793 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3794 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3795 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3796 {"i915_error_state", &i915_error_state_fops},
3797 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3798 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 3799 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3800 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3801 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
34b9674c
DV		 3802};
3803
07144428
DL		 3804void intel_display_crc_init(struct drm_device *dev)
3805{
3806 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3807 enum pipe pipe;
07144428 3808
b378360e
DV		 3809 for_each_pipe(pipe) {
3810 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3811
d538bbdf
DL		 3812 pipe_crc->opened = false;
3813 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3814 init_waitqueue_head(&pipe_crc->wq);
3815 }
3816}
3817
27c202ad 3818int i915_debugfs_init(struct drm_minor *minor)
2017263e 3819{
34b9674c 3820 int ret, i;
f3cd474b 3821
6d794d42 3822 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3823 if (ret)
3824 return ret;
6a9c308d 3825
07144428
DL		 3826 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3827 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3828 if (ret)
3829 return ret;
3830 }
3831
34b9674c
DV		 3832 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3833 ret = i915_debugfs_create(minor->debugfs_root, minor,
3834 i915_debugfs_files[i].name,
3835 i915_debugfs_files[i].fops);
3836 if (ret)
3837 return ret;
3838 }
40633219 3839
27c202ad
BG		 3840 return drm_debugfs_create_files(i915_debugfs_list,
3841 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3842 minor->debugfs_root, minor);
3843}
3844
27c202ad 3845void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3846{
34b9674c
DV		 3847 int i;
3848
27c202ad
BG		 3849 drm_debugfs_remove_files(i915_debugfs_list,
3850 I915_DEBUGFS_ENTRIES, minor);
07144428 3851
6d794d42
BW		 3852 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3853 1, minor);
07144428 3854
e309a997 3855 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3856 struct drm_info_list *info_list =
3857 (struct drm_info_list *)&i915_pipe_crc_data[i];
3858
3859 drm_debugfs_remove_files(info_list, 1, minor);
3860 }
3861
34b9674c
DV		 3862 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3863 struct drm_info_list *info_list =
3864 (struct drm_info_list *) i915_debugfs_files[i].fops;
3865
3866 drm_debugfs_remove_files(info_list, 1, minor);
3867 }
2017263e 3868}
Linux 6.x block layer and io_uring tree(s)