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drm/i915: Add PPGTT dumper
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
2017263e
BG		 43#if defined(CONFIG_DEBUG_FS)
44
f13d3f73 45enum {
69dc4987 46 ACTIVE_LIST,
f13d3f73 47 INACTIVE_LIST,
d21d5975 48 PINNED_LIST,
f13d3f73 49};
2017263e 50
70d39fe4
CW		 51static const char *yesno(int v)
52{
53 return v ? "yes" : "no";
54}
55
497666d8
DL		 56/* As the drm_debugfs_init() routines are called before dev->dev_private is
57 * allocated we need to hook into the minor for release. */
58static int
59drm_add_fake_info_node(struct drm_minor *minor,
60 struct dentry *ent,
61 const void *key)
62{
63 struct drm_info_node *node;
64
65 node = kmalloc(sizeof(*node), GFP_KERNEL);
66 if (node == NULL) {
67 debugfs_remove(ent);
68 return -ENOMEM;
69 }
70
71 node->minor = minor;
72 node->dent = ent;
73 node->info_ent = (void *) key;
74
75 mutex_lock(&minor->debugfs_lock);
76 list_add(&node->list, &minor->debugfs_list);
77 mutex_unlock(&minor->debugfs_lock);
78
79 return 0;
80}
81
70d39fe4
CW		 82static int i915_capabilities(struct seq_file *m, void *data)
83{
84 struct drm_info_node *node = (struct drm_info_node *) m->private;
85 struct drm_device *dev = node->minor->dev;
86 const struct intel_device_info *info = INTEL_INFO(dev);
87
88 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 89 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 90#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
91#define SEP_SEMICOLON ;
92 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
93#undef PRINT_FLAG
94#undef SEP_SEMICOLON
70d39fe4
CW		 95
96 return 0;
97}
2017263e 98
05394f39 99static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 100{
05394f39 101 if (obj->user_pin_count > 0)
a6172a80 102 return "P";
d7f46fc4 103 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 104 return "p";
105 else
106 return " ";
107}
108
05394f39 109static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 110{
0206e353
AJ		 111 switch (obj->tiling_mode) {
112 default:
113 case I915_TILING_NONE: return " ";
114 case I915_TILING_X: return "X";
115 case I915_TILING_Y: return "Y";
116 }
a6172a80
CW		 117}
118
1d693bcc
BW		 119static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
120{
121 return obj->has_global_gtt_mapping ? "g" : " ";
122}
123
37811fcc
CW		 124static void
125describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
126{
1d693bcc 127 struct i915_vma *vma;
d7f46fc4
BW		 128 int pin_count = 0;
129
fb1ae911 130 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 131 &obj->base,
132 get_pin_flag(obj),
133 get_tiling_flag(obj),
1d693bcc 134 get_global_flag(obj),
a05a5862 135 obj->base.size / 1024,
37811fcc
CW		 136 obj->base.read_domains,
137 obj->base.write_domain,
0201f1ec
CW		 138 obj->last_read_seqno,
139 obj->last_write_seqno,
caea7476 140 obj->last_fenced_seqno,
84734a04 141 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 142 obj->dirty ? " dirty" : "",
143 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
144 if (obj->base.name)
145 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 146 list_for_each_entry(vma, &obj->vma_list, vma_link)
147 if (vma->pin_count > 0)
148 pin_count++;
149 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 150 if (obj->pin_display)
151 seq_printf(m, " (display)");
37811fcc
CW		 152 if (obj->fence_reg != I915_FENCE_REG_NONE)
153 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 154 list_for_each_entry(vma, &obj->vma_list, vma_link) {
155 if (!i915_is_ggtt(vma->vm))
156 seq_puts(m, " (pp");
157 else
158 seq_puts(m, " (g");
159 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
160 vma->node.start, vma->node.size);
161 }
c1ad11fc
CW		 162 if (obj->stolen)
163 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 164 if (obj->pin_mappable || obj->fault_mappable) {
165 char s[3], *t = s;
166 if (obj->pin_mappable)
167 *t++ = 'p';
168 if (obj->fault_mappable)
169 *t++ = 'f';
170 *t = '\0';
171 seq_printf(m, " (%s mappable)", s);
172 }
69dc4987
CW		 173 if (obj->ring != NULL)
174 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 175}
176
3ccfd19d
BW		 177static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
178{
179 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 185{
186 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
244 struct drm_info_node *node = (struct drm_info_node *) m->private;
245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6
CW		 303struct file_stats {
304 int count;
305 size_t total, active, inactive, unbound;
306};
307
308static int per_file_stats(int id, void *ptr, void *data)
309{
310 struct drm_i915_gem_object *obj = ptr;
311 struct file_stats *stats = data;
312
313 stats->count++;
314 stats->total += obj->base.size;
315
f343c5f6 316 if (i915_gem_obj_ggtt_bound(obj)) {
2db8e9d6
CW		 317 if (!list_empty(&obj->ring_list))
318 stats->active += obj->base.size;
319 else
320 stats->inactive += obj->base.size;
321 } else {
322 if (!list_empty(&obj->global_list))
323 stats->unbound += obj->base.size;
324 }
325
326 return 0;
327}
328
ca191b13
BW		 329#define count_vmas(list, member) do { \
330 list_for_each_entry(vma, list, member) { \
331 size += i915_gem_obj_ggtt_size(vma->obj); \
332 ++count; \
333 if (vma->obj->map_and_fenceable) { \
334 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
335 ++mappable_count; \
336 } \
337 } \
338} while (0)
339
340static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 341{
342 struct drm_info_node *node = (struct drm_info_node *) m->private;
343 struct drm_device *dev = node->minor->dev;
344 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 345 u32 count, mappable_count, purgeable_count;
346 size_t size, mappable_size, purgeable_size;
6299f992 347 struct drm_i915_gem_object *obj;
5cef07e1 348 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 349 struct drm_file *file;
ca191b13 350 struct i915_vma *vma;
73aa808f
CW		 351 int ret;
352
353 ret = mutex_lock_interruptible(&dev->struct_mutex);
354 if (ret)
355 return ret;
356
6299f992
CW		 357 seq_printf(m, "%u objects, %zu bytes\n",
358 dev_priv->mm.object_count,
359 dev_priv->mm.object_memory);
360
361 size = count = mappable_size = mappable_count = 0;
35c20a60 362 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 363 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
364 count, mappable_count, size, mappable_size);
365
366 size = count = mappable_size = mappable_count = 0;
ca191b13 367 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 368 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
369 count, mappable_count, size, mappable_size);
370
6299f992 371 size = count = mappable_size = mappable_count = 0;
ca191b13 372 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 373 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
374 count, mappable_count, size, mappable_size);
375
b7abb714 376 size = count = purgeable_size = purgeable_count = 0;
35c20a60 377 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 378 size += obj->base.size, ++count;
b7abb714
CW		 379 if (obj->madv == I915_MADV_DONTNEED)
380 purgeable_size += obj->base.size, ++purgeable_count;
381 }
6c085a72
CW		 382 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
383
6299f992 384 size = count = mappable_size = mappable_count = 0;
35c20a60 385 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 386 if (obj->fault_mappable) {
f343c5f6 387 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 388 ++count;
389 }
390 if (obj->pin_mappable) {
f343c5f6 391 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 392 ++mappable_count;
393 }
b7abb714
CW		 394 if (obj->madv == I915_MADV_DONTNEED) {
395 purgeable_size += obj->base.size;
396 ++purgeable_count;
397 }
6299f992 398 }
b7abb714
CW		 399 seq_printf(m, "%u purgeable objects, %zu bytes\n",
400 purgeable_count, purgeable_size);
6299f992
CW		 401 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
402 mappable_count, mappable_size);
403 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
404 count, size);
405
93d18799 406 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 407 dev_priv->gtt.base.total,
408 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 409
267f0c90 410 seq_putc(m, '\n');
2db8e9d6
CW		 411 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
412 struct file_stats stats;
413
414 memset(&stats, 0, sizeof(stats));
415 idr_for_each(&file->object_idr, per_file_stats, &stats);
416 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
417 get_pid_task(file->pid, PIDTYPE_PID)->comm,
418 stats.count,
419 stats.total,
420 stats.active,
421 stats.inactive,
422 stats.unbound);
423 }
424
73aa808f
CW		 425 mutex_unlock(&dev->struct_mutex);
426
427 return 0;
428}
429
aee56cff 430static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 431{
432 struct drm_info_node *node = (struct drm_info_node *) m->private;
433 struct drm_device *dev = node->minor->dev;
1b50247a 434 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 435 struct drm_i915_private *dev_priv = dev->dev_private;
436 struct drm_i915_gem_object *obj;
437 size_t total_obj_size, total_gtt_size;
438 int count, ret;
439
440 ret = mutex_lock_interruptible(&dev->struct_mutex);
441 if (ret)
442 return ret;
443
444 total_obj_size = total_gtt_size = count = 0;
35c20a60 445 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 446 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 447 continue;
448
267f0c90 449 seq_puts(m, " ");
08c18323 450 describe_obj(m, obj);
267f0c90 451 seq_putc(m, '\n');
08c18323 452 total_obj_size += obj->base.size;
f343c5f6 453 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 454 count++;
455 }
456
457 mutex_unlock(&dev->struct_mutex);
458
459 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
460 count, total_obj_size, total_gtt_size);
461
462 return 0;
463}
464
4e5359cd
SF		 465static int i915_gem_pageflip_info(struct seq_file *m, void *data)
466{
467 struct drm_info_node *node = (struct drm_info_node *) m->private;
468 struct drm_device *dev = node->minor->dev;
469 unsigned long flags;
470 struct intel_crtc *crtc;
471
472 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 473 const char pipe = pipe_name(crtc->pipe);
474 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 475 struct intel_unpin_work *work;
476
477 spin_lock_irqsave(&dev->event_lock, flags);
478 work = crtc->unpin_work;
479 if (work == NULL) {
9db4a9c7 480 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 481 pipe, plane);
482 } else {
e7d841ca 483 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 484 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 485 pipe, plane);
486 } else {
9db4a9c7 487 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 488 pipe, plane);
489 }
490 if (work->enable_stall_check)
267f0c90 491 seq_puts(m, "Stall check enabled, ");
4e5359cd 492 else
267f0c90 493 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 494 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 495
496 if (work->old_fb_obj) {
05394f39
CW		 497 struct drm_i915_gem_object *obj = work->old_fb_obj;
498 if (obj)
f343c5f6
BW		 499 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
500 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 501 }
502 if (work->pending_flip_obj) {
05394f39
CW		 503 struct drm_i915_gem_object *obj = work->pending_flip_obj;
504 if (obj)
f343c5f6
BW		 505 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
506 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 507 }
508 }
509 spin_unlock_irqrestore(&dev->event_lock, flags);
510 }
511
512 return 0;
513}
514
2017263e
BG		 515static int i915_gem_request_info(struct seq_file *m, void *data)
516{
517 struct drm_info_node *node = (struct drm_info_node *) m->private;
518 struct drm_device *dev = node->minor->dev;
519 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 520 struct intel_ring_buffer *ring;
2017263e 521 struct drm_i915_gem_request *gem_request;
a2c7f6fd 522 int ret, count, i;
de227ef0
CW		 523
524 ret = mutex_lock_interruptible(&dev->struct_mutex);
525 if (ret)
526 return ret;
2017263e 527
c2c347a9 528 count = 0;
a2c7f6fd
CW		 529 for_each_ring(ring, dev_priv, i) {
530 if (list_empty(&ring->request_list))
531 continue;
532
533 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 534 list_for_each_entry(gem_request,
a2c7f6fd 535 &ring->request_list,
c2c347a9
CW		 536 list) {
537 seq_printf(m, " %d @ %d\n",
538 gem_request->seqno,
539 (int) (jiffies - gem_request->emitted_jiffies));
540 }
541 count++;
2017263e 542 }
de227ef0
CW		 543 mutex_unlock(&dev->struct_mutex);
544
c2c347a9 545 if (count == 0)
267f0c90 546 seq_puts(m, "No requests\n");
c2c347a9 547
2017263e
BG		 548 return 0;
549}
550
b2223497
CW		 551static void i915_ring_seqno_info(struct seq_file *m,
552 struct intel_ring_buffer *ring)
553{
554 if (ring->get_seqno) {
43a7b924 555 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 556 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 557 }
558}
559
2017263e
BG		 560static int i915_gem_seqno_info(struct seq_file *m, void *data)
561{
562 struct drm_info_node *node = (struct drm_info_node *) m->private;
563 struct drm_device *dev = node->minor->dev;
564 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 565 struct intel_ring_buffer *ring;
1ec14ad3 566 int ret, i;
de227ef0
CW		 567
568 ret = mutex_lock_interruptible(&dev->struct_mutex);
569 if (ret)
570 return ret;
2017263e 571
a2c7f6fd
CW		 572 for_each_ring(ring, dev_priv, i)
573 i915_ring_seqno_info(m, ring);
de227ef0
CW		 574
575 mutex_unlock(&dev->struct_mutex);
576
2017263e
BG		 577 return 0;
578}
579
580
581static int i915_interrupt_info(struct seq_file *m, void *data)
582{
583 struct drm_info_node *node = (struct drm_info_node *) m->private;
584 struct drm_device *dev = node->minor->dev;
585 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 586 struct intel_ring_buffer *ring;
9db4a9c7 587 int ret, i, pipe;
de227ef0
CW		 588
589 ret = mutex_lock_interruptible(&dev->struct_mutex);
590 if (ret)
591 return ret;
2017263e 592
a123f157
BW		 593 if (INTEL_INFO(dev)->gen >= 8) {
594 int i;
595 seq_printf(m, "Master Interrupt Control:\t%08x\n",
596 I915_READ(GEN8_MASTER_IRQ));
597
598 for (i = 0; i < 4; i++) {
599 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
600 i, I915_READ(GEN8_GT_IMR(i)));
601 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
602 i, I915_READ(GEN8_GT_IIR(i)));
603 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
604 i, I915_READ(GEN8_GT_IER(i)));
605 }
606
607 for_each_pipe(i) {
608 seq_printf(m, "Pipe %c IMR:\t%08x\n",
609 pipe_name(i),
610 I915_READ(GEN8_DE_PIPE_IMR(i)));
611 seq_printf(m, "Pipe %c IIR:\t%08x\n",
612 pipe_name(i),
613 I915_READ(GEN8_DE_PIPE_IIR(i)));
614 seq_printf(m, "Pipe %c IER:\t%08x\n",
615 pipe_name(i),
616 I915_READ(GEN8_DE_PIPE_IER(i)));
617 }
618
619 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
620 I915_READ(GEN8_DE_PORT_IMR));
621 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
622 I915_READ(GEN8_DE_PORT_IIR));
623 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
624 I915_READ(GEN8_DE_PORT_IER));
625
626 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
627 I915_READ(GEN8_DE_MISC_IMR));
628 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
629 I915_READ(GEN8_DE_MISC_IIR));
630 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
631 I915_READ(GEN8_DE_MISC_IER));
632
633 seq_printf(m, "PCU interrupt mask:\t%08x\n",
634 I915_READ(GEN8_PCU_IMR));
635 seq_printf(m, "PCU interrupt identity:\t%08x\n",
636 I915_READ(GEN8_PCU_IIR));
637 seq_printf(m, "PCU interrupt enable:\t%08x\n",
638 I915_READ(GEN8_PCU_IER));
639 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 640 seq_printf(m, "Display IER:\t%08x\n",
641 I915_READ(VLV_IER));
642 seq_printf(m, "Display IIR:\t%08x\n",
643 I915_READ(VLV_IIR));
644 seq_printf(m, "Display IIR_RW:\t%08x\n",
645 I915_READ(VLV_IIR_RW));
646 seq_printf(m, "Display IMR:\t%08x\n",
647 I915_READ(VLV_IMR));
648 for_each_pipe(pipe)
649 seq_printf(m, "Pipe %c stat:\t%08x\n",
650 pipe_name(pipe),
651 I915_READ(PIPESTAT(pipe)));
652
653 seq_printf(m, "Master IER:\t%08x\n",
654 I915_READ(VLV_MASTER_IER));
655
656 seq_printf(m, "Render IER:\t%08x\n",
657 I915_READ(GTIER));
658 seq_printf(m, "Render IIR:\t%08x\n",
659 I915_READ(GTIIR));
660 seq_printf(m, "Render IMR:\t%08x\n",
661 I915_READ(GTIMR));
662
663 seq_printf(m, "PM IER:\t\t%08x\n",
664 I915_READ(GEN6_PMIER));
665 seq_printf(m, "PM IIR:\t\t%08x\n",
666 I915_READ(GEN6_PMIIR));
667 seq_printf(m, "PM IMR:\t\t%08x\n",
668 I915_READ(GEN6_PMIMR));
669
670 seq_printf(m, "Port hotplug:\t%08x\n",
671 I915_READ(PORT_HOTPLUG_EN));
672 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
673 I915_READ(VLV_DPFLIPSTAT));
674 seq_printf(m, "DPINVGTT:\t%08x\n",
675 I915_READ(DPINVGTT));
676
677 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 678 seq_printf(m, "Interrupt enable: %08x\n",
679 I915_READ(IER));
680 seq_printf(m, "Interrupt identity: %08x\n",
681 I915_READ(IIR));
682 seq_printf(m, "Interrupt mask: %08x\n",
683 I915_READ(IMR));
9db4a9c7
JB		 684 for_each_pipe(pipe)
685 seq_printf(m, "Pipe %c stat: %08x\n",
686 pipe_name(pipe),
687 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 688 } else {
689 seq_printf(m, "North Display Interrupt enable: %08x\n",
690 I915_READ(DEIER));
691 seq_printf(m, "North Display Interrupt identity: %08x\n",
692 I915_READ(DEIIR));
693 seq_printf(m, "North Display Interrupt mask: %08x\n",
694 I915_READ(DEIMR));
695 seq_printf(m, "South Display Interrupt enable: %08x\n",
696 I915_READ(SDEIER));
697 seq_printf(m, "South Display Interrupt identity: %08x\n",
698 I915_READ(SDEIIR));
699 seq_printf(m, "South Display Interrupt mask: %08x\n",
700 I915_READ(SDEIMR));
701 seq_printf(m, "Graphics Interrupt enable: %08x\n",
702 I915_READ(GTIER));
703 seq_printf(m, "Graphics Interrupt identity: %08x\n",
704 I915_READ(GTIIR));
705 seq_printf(m, "Graphics Interrupt mask: %08x\n",
706 I915_READ(GTIMR));
707 }
2017263e
BG		 708 seq_printf(m, "Interrupts received: %d\n",
709 atomic_read(&dev_priv->irq_received));
a2c7f6fd 710 for_each_ring(ring, dev_priv, i) {
a123f157 711 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 712 seq_printf(m,
713 "Graphics Interrupt mask (%s): %08x\n",
714 ring->name, I915_READ_IMR(ring));
9862e600 715 }
a2c7f6fd 716 i915_ring_seqno_info(m, ring);
9862e600 717 }
de227ef0
CW		 718 mutex_unlock(&dev->struct_mutex);
719
2017263e
BG		 720 return 0;
721}
722
a6172a80
CW		 723static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
724{
725 struct drm_info_node *node = (struct drm_info_node *) m->private;
726 struct drm_device *dev = node->minor->dev;
727 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 728 int i, ret;
729
730 ret = mutex_lock_interruptible(&dev->struct_mutex);
731 if (ret)
732 return ret;
a6172a80
CW		 733
734 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
735 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
736 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 737 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 738
6c085a72
CW		 739 seq_printf(m, "Fence %d, pin count = %d, object = ",
740 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 741 if (obj == NULL)
267f0c90 742 seq_puts(m, "unused");
c2c347a9 743 else
05394f39 744 describe_obj(m, obj);
267f0c90 745 seq_putc(m, '\n');
a6172a80
CW		 746 }
747
05394f39 748 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 749 return 0;
750}
751
2017263e
BG		 752static int i915_hws_info(struct seq_file *m, void *data)
753{
754 struct drm_info_node *node = (struct drm_info_node *) m->private;
755 struct drm_device *dev = node->minor->dev;
756 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 757 struct intel_ring_buffer *ring;
1a240d4d 758 const u32 *hws;
4066c0ae
CW		 759 int i;
760
1ec14ad3 761 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 762 hws = ring->status_page.page_addr;
2017263e
BG		 763 if (hws == NULL)
764 return 0;
765
766 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
767 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
768 i * 4,
769 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
770 }
771 return 0;
772}
773
d5442303
DV		 774static ssize_t
775i915_error_state_write(struct file *filp,
776 const char __user *ubuf,
777 size_t cnt,
778 loff_t *ppos)
779{
edc3d884 780 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 781 struct drm_device *dev = error_priv->dev;
22bcfc6a 782 int ret;
d5442303
DV		 783
784 DRM_DEBUG_DRIVER("Resetting error state\n");
785
22bcfc6a
DV		 786 ret = mutex_lock_interruptible(&dev->struct_mutex);
787 if (ret)
788 return ret;
789
d5442303
DV		 790 i915_destroy_error_state(dev);
791 mutex_unlock(&dev->struct_mutex);
792
793 return cnt;
794}
795
796static int i915_error_state_open(struct inode *inode, struct file *file)
797{
798 struct drm_device *dev = inode->i_private;
d5442303 799 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 800
801 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
802 if (!error_priv)
803 return -ENOMEM;
804
805 error_priv->dev = dev;
806
95d5bfb3 807 i915_error_state_get(dev, error_priv);
d5442303 808
edc3d884
MK		 809 file->private_data = error_priv;
810
811 return 0;
d5442303
DV		 812}
813
814static int i915_error_state_release(struct inode *inode, struct file *file)
815{
edc3d884 816 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 817
95d5bfb3 818 i915_error_state_put(error_priv);
d5442303
DV		 819 kfree(error_priv);
820
edc3d884
MK		 821 return 0;
822}
823
4dc955f7
MK		 824static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
825 size_t count, loff_t *pos)
826{
827 struct i915_error_state_file_priv *error_priv = file->private_data;
828 struct drm_i915_error_state_buf error_str;
829 loff_t tmp_pos = 0;
830 ssize_t ret_count = 0;
831 int ret;
832
833 ret = i915_error_state_buf_init(&error_str, count, *pos);
834 if (ret)
835 return ret;
edc3d884 836
fc16b48b 837 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 838 if (ret)
839 goto out;
840
edc3d884
MK		 841 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
842 error_str.buf,
843 error_str.bytes);
844
845 if (ret_count < 0)
846 ret = ret_count;
847 else
848 *pos = error_str.start + ret_count;
849out:
4dc955f7 850 i915_error_state_buf_release(&error_str);
edc3d884 851 return ret ?: ret_count;
d5442303
DV		 852}
853
854static const struct file_operations i915_error_state_fops = {
855 .owner = THIS_MODULE,
856 .open = i915_error_state_open,
edc3d884 857 .read = i915_error_state_read,
d5442303
DV		 858 .write = i915_error_state_write,
859 .llseek = default_llseek,
860 .release = i915_error_state_release,
861};
862
647416f9
KC		 863static int
864i915_next_seqno_get(void *data, u64 *val)
40633219 865{
647416f9 866 struct drm_device *dev = data;
40633219 867 drm_i915_private_t *dev_priv = dev->dev_private;
40633219
MK		 868 int ret;
869
870 ret = mutex_lock_interruptible(&dev->struct_mutex);
871 if (ret)
872 return ret;
873
647416f9 874 *val = dev_priv->next_seqno;
40633219
MK		 875 mutex_unlock(&dev->struct_mutex);
876
647416f9 877 return 0;
40633219
MK		 878}
879
647416f9
KC		 880static int
881i915_next_seqno_set(void *data, u64 val)
882{
883 struct drm_device *dev = data;
40633219
MK		 884 int ret;
885
40633219
MK		 886 ret = mutex_lock_interruptible(&dev->struct_mutex);
887 if (ret)
888 return ret;
889
e94fbaa8 890 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 891 mutex_unlock(&dev->struct_mutex);
892
647416f9 893 return ret;
40633219
MK		 894}
895
647416f9
KC		 896DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
897 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 898 "0x%llx\n");
40633219 899
f97108d1
JB		 900static int i915_rstdby_delays(struct seq_file *m, void *unused)
901{
902 struct drm_info_node *node = (struct drm_info_node *) m->private;
903 struct drm_device *dev = node->minor->dev;
904 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 905 u16 crstanddelay;
906 int ret;
907
908 ret = mutex_lock_interruptible(&dev->struct_mutex);
909 if (ret)
910 return ret;
911
912 crstanddelay = I915_READ16(CRSTANDVID);
913
914 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 915
916 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
917
918 return 0;
919}
920
921static int i915_cur_delayinfo(struct seq_file *m, void *unused)
922{
923 struct drm_info_node *node = (struct drm_info_node *) m->private;
924 struct drm_device *dev = node->minor->dev;
925 drm_i915_private_t *dev_priv = dev->dev_private;
d1ebd816 926 int ret;
3b8d8d91 927
5c9669ce
TR		 928 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
929
3b8d8d91
JB		 930 if (IS_GEN5(dev)) {
931 u16 rgvswctl = I915_READ16(MEMSWCTL);
932 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
933
934 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
935 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
936 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
937 MEMSTAT_VID_SHIFT);
938 seq_printf(m, "Current P-state: %d\n",
939 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 940 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 941 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
942 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
943 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8e8c06cd 944 u32 rpstat, cagf, reqf;
ccab5c82
JB		 945 u32 rpupei, rpcurup, rpprevup;
946 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 947 int max_freq;
948
949 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 950 ret = mutex_lock_interruptible(&dev->struct_mutex);
951 if (ret)
952 return ret;
953
c8d9a590 954 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 955
8e8c06cd
CW		 956 reqf = I915_READ(GEN6_RPNSWREQ);
957 reqf &= ~GEN6_TURBO_DISABLE;
958 if (IS_HASWELL(dev))
959 reqf >>= 24;
960 else
961 reqf >>= 25;
962 reqf *= GT_FREQUENCY_MULTIPLIER;
963
ccab5c82
JB		 964 rpstat = I915_READ(GEN6_RPSTAT1);
965 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
966 rpcurup = I915_READ(GEN6_RP_CUR_UP);
967 rpprevup = I915_READ(GEN6_RP_PREV_UP);
968 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
969 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
970 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 971 if (IS_HASWELL(dev))
972 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
973 else
974 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
975 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 976
c8d9a590 977 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 978 mutex_unlock(&dev->struct_mutex);
979
3b8d8d91 980 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 981 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 982 seq_printf(m, "Render p-state ratio: %d\n",
983 (gt_perf_status & 0xff00) >> 8);
984 seq_printf(m, "Render p-state VID: %d\n",
985 gt_perf_status & 0xff);
986 seq_printf(m, "Render p-state limit: %d\n",
987 rp_state_limits & 0xff);
8e8c06cd 988 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 989 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 990 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
991 GEN6_CURICONT_MASK);
992 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
993 GEN6_CURBSYTAVG_MASK);
994 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
995 GEN6_CURBSYTAVG_MASK);
996 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
997 GEN6_CURIAVG_MASK);
998 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
999 GEN6_CURBSYTAVG_MASK);
1000 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1001 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1002
1003 max_freq = (rp_state_cap & 0xff0000) >> 16;
1004 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1005 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1006
1007 max_freq = (rp_state_cap & 0xff00) >> 8;
1008 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1009 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1010
1011 max_freq = rp_state_cap & 0xff;
1012 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1013 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1014
1015 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1016 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1017 } else if (IS_VALLEYVIEW(dev)) {
1018 u32 freq_sts, val;
1019
259bd5d4 1020 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1021 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1022 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1023 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1024
c5bd2bf6 1025 val = valleyview_rps_max_freq(dev_priv);
0a073b84 1026 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 1027 vlv_gpu_freq(dev_priv, val));
0a073b84 1028
c5bd2bf6 1029 val = valleyview_rps_min_freq(dev_priv);
0a073b84 1030 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 1031 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 1032
1033 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1034 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1035 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1036 } else {
267f0c90 1037 seq_puts(m, "no P-state info available\n");
3b8d8d91 1038 }
f97108d1
JB		 1039
1040 return 0;
1041}
1042
1043static int i915_delayfreq_table(struct seq_file *m, void *unused)
1044{
1045 struct drm_info_node *node = (struct drm_info_node *) m->private;
1046 struct drm_device *dev = node->minor->dev;
1047 drm_i915_private_t *dev_priv = dev->dev_private;
1048 u32 delayfreq;
616fdb5a
BW		 1049 int ret, i;
1050
1051 ret = mutex_lock_interruptible(&dev->struct_mutex);
1052 if (ret)
1053 return ret;
f97108d1
JB		 1054
1055 for (i = 0; i < 16; i++) {
1056 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1057 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1058 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1059 }
1060
616fdb5a
BW		 1061 mutex_unlock(&dev->struct_mutex);
1062
f97108d1
JB		 1063 return 0;
1064}
1065
1066static inline int MAP_TO_MV(int map)
1067{
1068 return 1250 - (map * 25);
1069}
1070
1071static int i915_inttoext_table(struct seq_file *m, void *unused)
1072{
1073 struct drm_info_node *node = (struct drm_info_node *) m->private;
1074 struct drm_device *dev = node->minor->dev;
1075 drm_i915_private_t *dev_priv = dev->dev_private;
1076 u32 inttoext;
616fdb5a
BW		 1077 int ret, i;
1078
1079 ret = mutex_lock_interruptible(&dev->struct_mutex);
1080 if (ret)
1081 return ret;
f97108d1
JB		 1082
1083 for (i = 1; i <= 32; i++) {
1084 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1085 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1086 }
1087
616fdb5a
BW		 1088 mutex_unlock(&dev->struct_mutex);
1089
f97108d1
JB		 1090 return 0;
1091}
1092
4d85529d 1093static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1094{
1095 struct drm_info_node *node = (struct drm_info_node *) m->private;
1096 struct drm_device *dev = node->minor->dev;
1097 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1098 u32 rgvmodectl, rstdbyctl;
1099 u16 crstandvid;
1100 int ret;
1101
1102 ret = mutex_lock_interruptible(&dev->struct_mutex);
1103 if (ret)
1104 return ret;
1105
1106 rgvmodectl = I915_READ(MEMMODECTL);
1107 rstdbyctl = I915_READ(RSTDBYCTL);
1108 crstandvid = I915_READ16(CRSTANDVID);
1109
1110 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1111
1112 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1113 "yes" : "no");
1114 seq_printf(m, "Boost freq: %d\n",
1115 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1116 MEMMODE_BOOST_FREQ_SHIFT);
1117 seq_printf(m, "HW control enabled: %s\n",
1118 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1119 seq_printf(m, "SW control enabled: %s\n",
1120 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1121 seq_printf(m, "Gated voltage change: %s\n",
1122 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1123 seq_printf(m, "Starting frequency: P%d\n",
1124 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1125 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1126 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1127 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1128 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1129 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1130 seq_printf(m, "Render standby enabled: %s\n",
1131 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1132 seq_puts(m, "Current RS state: ");
88271da3
JB		 1133 switch (rstdbyctl & RSX_STATUS_MASK) {
1134 case RSX_STATUS_ON:
267f0c90 1135 seq_puts(m, "on\n");
88271da3
JB		 1136 break;
1137 case RSX_STATUS_RC1:
267f0c90 1138 seq_puts(m, "RC1\n");
88271da3
JB		 1139 break;
1140 case RSX_STATUS_RC1E:
267f0c90 1141 seq_puts(m, "RC1E\n");
88271da3
JB		 1142 break;
1143 case RSX_STATUS_RS1:
267f0c90 1144 seq_puts(m, "RS1\n");
88271da3
JB		 1145 break;
1146 case RSX_STATUS_RS2:
267f0c90 1147 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1148 break;
1149 case RSX_STATUS_RS3:
267f0c90 1150 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1151 break;
1152 default:
267f0c90 1153 seq_puts(m, "unknown\n");
88271da3
JB		 1154 break;
1155 }
f97108d1
JB		 1156
1157 return 0;
1158}
1159
4d85529d
BW		 1160static int gen6_drpc_info(struct seq_file *m)
1161{
1162
1163 struct drm_info_node *node = (struct drm_info_node *) m->private;
1164 struct drm_device *dev = node->minor->dev;
1165 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1166 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1167 unsigned forcewake_count;
aee56cff 1168 int count = 0, ret;
4d85529d
BW		 1169
1170 ret = mutex_lock_interruptible(&dev->struct_mutex);
1171 if (ret)
1172 return ret;
1173
907b28c5
CW		 1174 spin_lock_irq(&dev_priv->uncore.lock);
1175 forcewake_count = dev_priv->uncore.forcewake_count;
1176 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1177
1178 if (forcewake_count) {
267f0c90
DL		 1179 seq_puts(m, "RC information inaccurate because somebody "
1180 "holds a forcewake reference \n");
4d85529d
BW		 1181 } else {
1182 /* NB: we cannot use forcewake, else we read the wrong values */
1183 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1184 udelay(10);
1185 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1186 }
1187
1188 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1189 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1190
1191 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1192 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1193 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1194 mutex_lock(&dev_priv->rps.hw_lock);
1195 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1196 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d
BW		 1197
1198 seq_printf(m, "Video Turbo Mode: %s\n",
1199 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1200 seq_printf(m, "HW control enabled: %s\n",
1201 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1202 seq_printf(m, "SW control enabled: %s\n",
1203 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1204 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1205 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1206 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1207 seq_printf(m, "RC6 Enabled: %s\n",
1208 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1209 seq_printf(m, "Deep RC6 Enabled: %s\n",
1210 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1211 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1212 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1213 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1214 switch (gt_core_status & GEN6_RCn_MASK) {
1215 case GEN6_RC0:
1216 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1217 seq_puts(m, "Core Power Down\n");
4d85529d 1218 else
267f0c90 1219 seq_puts(m, "on\n");
4d85529d
BW		 1220 break;
1221 case GEN6_RC3:
267f0c90 1222 seq_puts(m, "RC3\n");
4d85529d
BW		 1223 break;
1224 case GEN6_RC6:
267f0c90 1225 seq_puts(m, "RC6\n");
4d85529d
BW		 1226 break;
1227 case GEN6_RC7:
267f0c90 1228 seq_puts(m, "RC7\n");
4d85529d
BW		 1229 break;
1230 default:
267f0c90 1231 seq_puts(m, "Unknown\n");
4d85529d
BW		 1232 break;
1233 }
1234
1235 seq_printf(m, "Core Power Down: %s\n",
1236 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1237
1238 /* Not exactly sure what this is */
1239 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1240 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1241 seq_printf(m, "RC6 residency since boot: %u\n",
1242 I915_READ(GEN6_GT_GFX_RC6));
1243 seq_printf(m, "RC6+ residency since boot: %u\n",
1244 I915_READ(GEN6_GT_GFX_RC6p));
1245 seq_printf(m, "RC6++ residency since boot: %u\n",
1246 I915_READ(GEN6_GT_GFX_RC6pp));
1247
ecd8faea
BW		 1248 seq_printf(m, "RC6 voltage: %dmV\n",
1249 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1250 seq_printf(m, "RC6+ voltage: %dmV\n",
1251 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1252 seq_printf(m, "RC6++ voltage: %dmV\n",
1253 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1254 return 0;
1255}
1256
1257static int i915_drpc_info(struct seq_file *m, void *unused)
1258{
1259 struct drm_info_node *node = (struct drm_info_node *) m->private;
1260 struct drm_device *dev = node->minor->dev;
1261
1262 if (IS_GEN6(dev) || IS_GEN7(dev))
1263 return gen6_drpc_info(m);
1264 else
1265 return ironlake_drpc_info(m);
1266}
1267
b5e50c3f
JB		 1268static int i915_fbc_status(struct seq_file *m, void *unused)
1269{
1270 struct drm_info_node *node = (struct drm_info_node *) m->private;
1271 struct drm_device *dev = node->minor->dev;
b5e50c3f 1272 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1273
ee5382ae 1274 if (!I915_HAS_FBC(dev)) {
267f0c90 1275 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1276 return 0;
1277 }
1278
ee5382ae 1279 if (intel_fbc_enabled(dev)) {
267f0c90 1280 seq_puts(m, "FBC enabled\n");
b5e50c3f 1281 } else {
267f0c90 1282 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1283 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1284 case FBC_OK:
1285 seq_puts(m, "FBC actived, but currently disabled in hardware");
1286 break;
1287 case FBC_UNSUPPORTED:
1288 seq_puts(m, "unsupported by this chipset");
1289 break;
bed4a673 1290 case FBC_NO_OUTPUT:
267f0c90 1291 seq_puts(m, "no outputs");
bed4a673 1292 break;
b5e50c3f 1293 case FBC_STOLEN_TOO_SMALL:
267f0c90 1294 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1295 break;
1296 case FBC_UNSUPPORTED_MODE:
267f0c90 1297 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1298 break;
1299 case FBC_MODE_TOO_LARGE:
267f0c90 1300 seq_puts(m, "mode too large");
b5e50c3f
JB		 1301 break;
1302 case FBC_BAD_PLANE:
267f0c90 1303 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1304 break;
1305 case FBC_NOT_TILED:
267f0c90 1306 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1307 break;
9c928d16 1308 case FBC_MULTIPLE_PIPES:
267f0c90 1309 seq_puts(m, "multiple pipes are enabled");
9c928d16 1310 break;
c1a9f047 1311 case FBC_MODULE_PARAM:
267f0c90 1312 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1313 break;
8a5729a3 1314 case FBC_CHIP_DEFAULT:
267f0c90 1315 seq_puts(m, "disabled per chip default");
8a5729a3 1316 break;
b5e50c3f 1317 default:
267f0c90 1318 seq_puts(m, "unknown reason");
b5e50c3f 1319 }
267f0c90 1320 seq_putc(m, '\n');
b5e50c3f
JB		 1321 }
1322 return 0;
1323}
1324
92d44621
PZ		 1325static int i915_ips_status(struct seq_file *m, void *unused)
1326{
1327 struct drm_info_node *node = (struct drm_info_node *) m->private;
1328 struct drm_device *dev = node->minor->dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330
f5adf94e 1331 if (!HAS_IPS(dev)) {
92d44621
PZ		 1332 seq_puts(m, "not supported\n");
1333 return 0;
1334 }
1335
1336 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1337 seq_puts(m, "enabled\n");
1338 else
1339 seq_puts(m, "disabled\n");
1340
1341 return 0;
1342}
1343
4a9bef37
JB		 1344static int i915_sr_status(struct seq_file *m, void *unused)
1345{
1346 struct drm_info_node *node = (struct drm_info_node *) m->private;
1347 struct drm_device *dev = node->minor->dev;
1348 drm_i915_private_t *dev_priv = dev->dev_private;
1349 bool sr_enabled = false;
1350
1398261a 1351 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1352 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1353 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1354 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1355 else if (IS_I915GM(dev))
1356 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1357 else if (IS_PINEVIEW(dev))
1358 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1359
5ba2aaaa
CW		 1360 seq_printf(m, "self-refresh: %s\n",
1361 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1362
1363 return 0;
1364}
1365
7648fa99
JB		 1366static int i915_emon_status(struct seq_file *m, void *unused)
1367{
1368 struct drm_info_node *node = (struct drm_info_node *) m->private;
1369 struct drm_device *dev = node->minor->dev;
1370 drm_i915_private_t *dev_priv = dev->dev_private;
1371 unsigned long temp, chipset, gfx;
de227ef0
CW		 1372 int ret;
1373
582be6b4
CW		 1374 if (!IS_GEN5(dev))
1375 return -ENODEV;
1376
de227ef0
CW		 1377 ret = mutex_lock_interruptible(&dev->struct_mutex);
1378 if (ret)
1379 return ret;
7648fa99
JB		 1380
1381 temp = i915_mch_val(dev_priv);
1382 chipset = i915_chipset_val(dev_priv);
1383 gfx = i915_gfx_val(dev_priv);
de227ef0 1384 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1385
1386 seq_printf(m, "GMCH temp: %ld\n", temp);
1387 seq_printf(m, "Chipset power: %ld\n", chipset);
1388 seq_printf(m, "GFX power: %ld\n", gfx);
1389 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1390
1391 return 0;
1392}
1393
23b2f8bb
JB		 1394static int i915_ring_freq_table(struct seq_file *m, void *unused)
1395{
1396 struct drm_info_node *node = (struct drm_info_node *) m->private;
1397 struct drm_device *dev = node->minor->dev;
1398 drm_i915_private_t *dev_priv = dev->dev_private;
1399 int ret;
1400 int gpu_freq, ia_freq;
1401
1c70c0ce 1402 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1403 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1404 return 0;
1405 }
1406
5c9669ce
TR		 1407 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1408
4fc688ce 1409 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1410 if (ret)
1411 return ret;
1412
267f0c90 1413 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1414
c6a828d3
DV		 1415 for (gpu_freq = dev_priv->rps.min_delay;
1416 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1417 gpu_freq++) {
42c0526c
BW		 1418 ia_freq = gpu_freq;
1419 sandybridge_pcode_read(dev_priv,
1420 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1421 &ia_freq);
3ebecd07
CW		 1422 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1423 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1424 ((ia_freq >> 0) & 0xff) * 100,
1425 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1426 }
1427
4fc688ce 1428 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1429
1430 return 0;
1431}
1432
7648fa99
JB		 1433static int i915_gfxec(struct seq_file *m, void *unused)
1434{
1435 struct drm_info_node *node = (struct drm_info_node *) m->private;
1436 struct drm_device *dev = node->minor->dev;
1437 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1438 int ret;
1439
1440 ret = mutex_lock_interruptible(&dev->struct_mutex);
1441 if (ret)
1442 return ret;
7648fa99
JB		 1443
1444 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1445
616fdb5a
BW		 1446 mutex_unlock(&dev->struct_mutex);
1447
7648fa99
JB		 1448 return 0;
1449}
1450
44834a67
CW		 1451static int i915_opregion(struct seq_file *m, void *unused)
1452{
1453 struct drm_info_node *node = (struct drm_info_node *) m->private;
1454 struct drm_device *dev = node->minor->dev;
1455 drm_i915_private_t *dev_priv = dev->dev_private;
1456 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1457 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1458 int ret;
1459
0d38f009
DV		 1460 if (data == NULL)
1461 return -ENOMEM;
1462
44834a67
CW		 1463 ret = mutex_lock_interruptible(&dev->struct_mutex);
1464 if (ret)
0d38f009 1465 goto out;
44834a67 1466
0d38f009
DV		 1467 if (opregion->header) {
1468 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1469 seq_write(m, data, OPREGION_SIZE);
1470 }
44834a67
CW		 1471
1472 mutex_unlock(&dev->struct_mutex);
1473
0d38f009
DV		 1474out:
1475 kfree(data);
44834a67
CW		 1476 return 0;
1477}
1478
37811fcc
CW		 1479static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1480{
1481 struct drm_info_node *node = (struct drm_info_node *) m->private;
1482 struct drm_device *dev = node->minor->dev;
4520f53a 1483 struct intel_fbdev *ifbdev = NULL;
37811fcc 1484 struct intel_framebuffer *fb;
37811fcc 1485
4520f53a
DV		 1486#ifdef CONFIG_DRM_I915_FBDEV
1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1489 if (ret)
1490 return ret;
1491
1492 ifbdev = dev_priv->fbdev;
1493 fb = to_intel_framebuffer(ifbdev->helper.fb);
1494
623f9783 1495 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1496 fb->base.width,
1497 fb->base.height,
1498 fb->base.depth,
623f9783
DV		 1499 fb->base.bits_per_pixel,
1500 atomic_read(&fb->base.refcount.refcount));
05394f39 1501 describe_obj(m, fb->obj);
267f0c90 1502 seq_putc(m, '\n');
4b096ac1 1503 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1504#endif
37811fcc 1505
4b096ac1 1506 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1507 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1508 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1509 continue;
1510
623f9783 1511 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1512 fb->base.width,
1513 fb->base.height,
1514 fb->base.depth,
623f9783
DV		 1515 fb->base.bits_per_pixel,
1516 atomic_read(&fb->base.refcount.refcount));
05394f39 1517 describe_obj(m, fb->obj);
267f0c90 1518 seq_putc(m, '\n');
37811fcc 1519 }
4b096ac1 1520 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1521
1522 return 0;
1523}
1524
e76d3630
BW		 1525static int i915_context_status(struct seq_file *m, void *unused)
1526{
1527 struct drm_info_node *node = (struct drm_info_node *) m->private;
1528 struct drm_device *dev = node->minor->dev;
1529 drm_i915_private_t *dev_priv = dev->dev_private;
a168c293 1530 struct intel_ring_buffer *ring;
a33afea5 1531 struct i915_hw_context *ctx;
a168c293 1532 int ret, i;
e76d3630
BW		 1533
1534 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1535 if (ret)
1536 return ret;
1537
3e373948 1538 if (dev_priv->ips.pwrctx) {
267f0c90 1539 seq_puts(m, "power context ");
3e373948 1540 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1541 seq_putc(m, '\n');
dc501fbc 1542 }
e76d3630 1543
3e373948 1544 if (dev_priv->ips.renderctx) {
267f0c90 1545 seq_puts(m, "render context ");
3e373948 1546 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1547 seq_putc(m, '\n');
dc501fbc 1548 }
e76d3630 1549
a33afea5
BW		 1550 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1551 seq_puts(m, "HW context ");
3ccfd19d 1552 describe_ctx(m, ctx);
a33afea5
BW		 1553 for_each_ring(ring, dev_priv, i)
1554 if (ring->default_context == ctx)
1555 seq_printf(m, "(default context %s) ", ring->name);
1556
1557 describe_obj(m, ctx->obj);
1558 seq_putc(m, '\n');
a168c293
BW		 1559 }
1560
e76d3630
BW		 1561 mutex_unlock(&dev->mode_config.mutex);
1562
1563 return 0;
1564}
1565
6d794d42
BW		 1566static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1567{
1568 struct drm_info_node *node = (struct drm_info_node *) m->private;
1569 struct drm_device *dev = node->minor->dev;
1570 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1571 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1572
907b28c5 1573 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1574 if (IS_VALLEYVIEW(dev)) {
1575 fw_rendercount = dev_priv->uncore.fw_rendercount;
1576 fw_mediacount = dev_priv->uncore.fw_mediacount;
1577 } else
1578 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1579 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1580
43709ba0
D		 1581 if (IS_VALLEYVIEW(dev)) {
1582 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1583 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1584 } else
1585 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1586
1587 return 0;
1588}
1589
ea16a3cd
DV		 1590static const char *swizzle_string(unsigned swizzle)
1591{
aee56cff 1592 switch (swizzle) {
ea16a3cd
DV		 1593 case I915_BIT_6_SWIZZLE_NONE:
1594 return "none";
1595 case I915_BIT_6_SWIZZLE_9:
1596 return "bit9";
1597 case I915_BIT_6_SWIZZLE_9_10:
1598 return "bit9/bit10";
1599 case I915_BIT_6_SWIZZLE_9_11:
1600 return "bit9/bit11";
1601 case I915_BIT_6_SWIZZLE_9_10_11:
1602 return "bit9/bit10/bit11";
1603 case I915_BIT_6_SWIZZLE_9_17:
1604 return "bit9/bit17";
1605 case I915_BIT_6_SWIZZLE_9_10_17:
1606 return "bit9/bit10/bit17";
1607 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1608 return "unknown";
ea16a3cd
DV		 1609 }
1610
1611 return "bug";
1612}
1613
1614static int i915_swizzle_info(struct seq_file *m, void *data)
1615{
1616 struct drm_info_node *node = (struct drm_info_node *) m->private;
1617 struct drm_device *dev = node->minor->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1619 int ret;
1620
1621 ret = mutex_lock_interruptible(&dev->struct_mutex);
1622 if (ret)
1623 return ret;
ea16a3cd 1624
ea16a3cd
DV		 1625 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1626 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1627 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1628 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1629
1630 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1631 seq_printf(m, "DDC = 0x%08x\n",
1632 I915_READ(DCC));
1633 seq_printf(m, "C0DRB3 = 0x%04x\n",
1634 I915_READ16(C0DRB3));
1635 seq_printf(m, "C1DRB3 = 0x%04x\n",
1636 I915_READ16(C1DRB3));
9d3203e1 1637 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1638 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1639 I915_READ(MAD_DIMM_C0));
1640 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1641 I915_READ(MAD_DIMM_C1));
1642 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1643 I915_READ(MAD_DIMM_C2));
1644 seq_printf(m, "TILECTL = 0x%08x\n",
1645 I915_READ(TILECTL));
9d3203e1
BW		 1646 if (IS_GEN8(dev))
1647 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1648 I915_READ(GAMTARBMODE));
1649 else
1650 seq_printf(m, "ARB_MODE = 0x%08x\n",
1651 I915_READ(ARB_MODE));
3fa7d235
DV		 1652 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1653 I915_READ(DISP_ARB_CTL));
ea16a3cd
DV		 1654 }
1655 mutex_unlock(&dev->struct_mutex);
1656
1657 return 0;
1658}
1659
77df6772 1660static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1661{
3cf17fc5
DV		 1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 struct intel_ring_buffer *ring;
77df6772
BW		 1664 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1665 int unused, i;
3cf17fc5 1666
77df6772
BW		 1667 if (!ppgtt)
1668 return;
1669
1670 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1671 seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages);
1672 for_each_ring(ring, dev_priv, unused) {
1673 seq_printf(m, "%s\n", ring->name);
1674 for (i = 0; i < 4; i++) {
1675 u32 offset = 0x270 + i * 8;
1676 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1677 pdp <<= 32;
1678 pdp |= I915_READ(ring->mmio_base + offset);
1679 for (i = 0; i < 4; i++)
1680 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1681 }
1682 }
1683}
1684
1685static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1686{
1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 struct intel_ring_buffer *ring;
1689 int i;
3cf17fc5 1690
3cf17fc5
DV		 1691 if (INTEL_INFO(dev)->gen == 6)
1692 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1693
a2c7f6fd 1694 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1695 seq_printf(m, "%s\n", ring->name);
1696 if (INTEL_INFO(dev)->gen == 7)
1697 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1698 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1699 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1700 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1701 }
1702 if (dev_priv->mm.aliasing_ppgtt) {
1703 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1704
267f0c90 1705 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 1706 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
87d60b63 1707 ppgtt->debug_dump(ppgtt, m);
3cf17fc5
DV		 1708 }
1709 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1710}
1711
1712static int i915_ppgtt_info(struct seq_file *m, void *data)
1713{
1714 struct drm_info_node *node = (struct drm_info_node *) m->private;
1715 struct drm_device *dev = node->minor->dev;
1716
1717 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1718 if (ret)
1719 return ret;
1720
1721 if (INTEL_INFO(dev)->gen >= 8)
1722 gen8_ppgtt_info(m, dev);
1723 else if (INTEL_INFO(dev)->gen >= 6)
1724 gen6_ppgtt_info(m, dev);
1725
3cf17fc5
DV		 1726 mutex_unlock(&dev->struct_mutex);
1727
1728 return 0;
1729}
1730
57f350b6
JB		 1731static int i915_dpio_info(struct seq_file *m, void *data)
1732{
1733 struct drm_info_node *node = (struct drm_info_node *) m->private;
1734 struct drm_device *dev = node->minor->dev;
1735 struct drm_i915_private *dev_priv = dev->dev_private;
1736 int ret;
1737
1738
1739 if (!IS_VALLEYVIEW(dev)) {
267f0c90 1740 seq_puts(m, "unsupported\n");
57f350b6
JB		 1741 return 0;
1742 }
1743
09153000 1744 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
57f350b6
JB		 1745 if (ret)
1746 return ret;
1747
1748 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1749
ab3c759a
CML		 1750 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1751 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1752 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1753 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1754
1755 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1756 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1757 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1758 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1759
1760 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1761 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1762 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1763 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1764
1765 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1766 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1767 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1768 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
57f350b6
JB		 1769
1770 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
ab3c759a 1771 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
57f350b6 1772
09153000 1773 mutex_unlock(&dev_priv->dpio_lock);
57f350b6
JB		 1774
1775 return 0;
1776}
1777
63573eb7
BW		 1778static int i915_llc(struct seq_file *m, void *data)
1779{
1780 struct drm_info_node *node = (struct drm_info_node *) m->private;
1781 struct drm_device *dev = node->minor->dev;
1782 struct drm_i915_private *dev_priv = dev->dev_private;
1783
1784 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1785 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1786 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1787
1788 return 0;
1789}
1790
e91fd8c6
RV		 1791static int i915_edp_psr_status(struct seq_file *m, void *data)
1792{
1793 struct drm_info_node *node = m->private;
1794 struct drm_device *dev = node->minor->dev;
1795 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1796 u32 psrperf = 0;
1797 bool enabled = false;
e91fd8c6 1798
a031d709
RV		 1799 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1800 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1801
a031d709
RV		 1802 enabled = HAS_PSR(dev) &&
1803 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1804 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1805
a031d709
RV		 1806 if (HAS_PSR(dev))
1807 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1808 EDP_PSR_PERF_CNT_MASK;
1809 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6
RV		 1810
1811 return 0;
1812}
1813
ec013e7f
JB		 1814static int i915_energy_uJ(struct seq_file *m, void *data)
1815{
1816 struct drm_info_node *node = m->private;
1817 struct drm_device *dev = node->minor->dev;
1818 struct drm_i915_private *dev_priv = dev->dev_private;
1819 u64 power;
1820 u32 units;
1821
1822 if (INTEL_INFO(dev)->gen < 6)
1823 return -ENODEV;
1824
1825 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1826 power = (power & 0x1f00) >> 8;
1827 units = 1000000 / (1 << power); /* convert to uJ */
1828 power = I915_READ(MCH_SECP_NRG_STTS);
1829 power *= units;
1830
1831 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 1832
1833 return 0;
1834}
1835
1836static int i915_pc8_status(struct seq_file *m, void *unused)
1837{
1838 struct drm_info_node *node = (struct drm_info_node *) m->private;
1839 struct drm_device *dev = node->minor->dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841
1842 if (!IS_HASWELL(dev)) {
1843 seq_puts(m, "not supported\n");
1844 return 0;
1845 }
1846
1847 mutex_lock(&dev_priv->pc8.lock);
1848 seq_printf(m, "Requirements met: %s\n",
1849 yesno(dev_priv->pc8.requirements_met));
1850 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1851 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1852 seq_printf(m, "IRQs disabled: %s\n",
1853 yesno(dev_priv->pc8.irqs_disabled));
1854 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1855 mutex_unlock(&dev_priv->pc8.lock);
1856
ec013e7f
JB		 1857 return 0;
1858}
1859
1da51581
ID		 1860static const char *power_domain_str(enum intel_display_power_domain domain)
1861{
1862 switch (domain) {
1863 case POWER_DOMAIN_PIPE_A:
1864 return "PIPE_A";
1865 case POWER_DOMAIN_PIPE_B:
1866 return "PIPE_B";
1867 case POWER_DOMAIN_PIPE_C:
1868 return "PIPE_C";
1869 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
1870 return "PIPE_A_PANEL_FITTER";
1871 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
1872 return "PIPE_B_PANEL_FITTER";
1873 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
1874 return "PIPE_C_PANEL_FITTER";
1875 case POWER_DOMAIN_TRANSCODER_A:
1876 return "TRANSCODER_A";
1877 case POWER_DOMAIN_TRANSCODER_B:
1878 return "TRANSCODER_B";
1879 case POWER_DOMAIN_TRANSCODER_C:
1880 return "TRANSCODER_C";
1881 case POWER_DOMAIN_TRANSCODER_EDP:
1882 return "TRANSCODER_EDP";
1883 case POWER_DOMAIN_VGA:
1884 return "VGA";
1885 case POWER_DOMAIN_AUDIO:
1886 return "AUDIO";
1887 case POWER_DOMAIN_INIT:
1888 return "INIT";
1889 default:
1890 WARN_ON(1);
1891 return "?";
1892 }
1893}
1894
1895static int i915_power_domain_info(struct seq_file *m, void *unused)
1896{
1897 struct drm_info_node *node = (struct drm_info_node *) m->private;
1898 struct drm_device *dev = node->minor->dev;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1901 int i;
1902
1903 mutex_lock(&power_domains->lock);
1904
1905 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
1906 for (i = 0; i < power_domains->power_well_count; i++) {
1907 struct i915_power_well *power_well;
1908 enum intel_display_power_domain power_domain;
1909
1910 power_well = &power_domains->power_wells[i];
1911 seq_printf(m, "%-25s %d\n", power_well->name,
1912 power_well->count);
1913
1914 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
1915 power_domain++) {
1916 if (!(BIT(power_domain) & power_well->domains))
1917 continue;
1918
1919 seq_printf(m, " %-23s %d\n",
1920 power_domain_str(power_domain),
1921 power_domains->domain_use_count[power_domain]);
1922 }
1923 }
1924
1925 mutex_unlock(&power_domains->lock);
1926
1927 return 0;
1928}
1929
07144428
DL		 1930struct pipe_crc_info {
1931 const char *name;
1932 struct drm_device *dev;
1933 enum pipe pipe;
1934};
1935
1936static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
1937{
be5c7a90
DL		 1938 struct pipe_crc_info *info = inode->i_private;
1939 struct drm_i915_private *dev_priv = info->dev->dev_private;
1940 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1941
7eb1c496
DV		 1942 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
1943 return -ENODEV;
1944
d538bbdf
DL		 1945 spin_lock_irq(&pipe_crc->lock);
1946
1947 if (pipe_crc->opened) {
1948 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 1949 return -EBUSY; /* already open */
1950 }
1951
d538bbdf 1952 pipe_crc->opened = true;
07144428
DL		 1953 filep->private_data = inode->i_private;
1954
d538bbdf
DL		 1955 spin_unlock_irq(&pipe_crc->lock);
1956
07144428
DL		 1957 return 0;
1958}
1959
1960static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
1961{
be5c7a90
DL		 1962 struct pipe_crc_info *info = inode->i_private;
1963 struct drm_i915_private *dev_priv = info->dev->dev_private;
1964 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1965
d538bbdf
DL		 1966 spin_lock_irq(&pipe_crc->lock);
1967 pipe_crc->opened = false;
1968 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 1969
07144428
DL		 1970 return 0;
1971}
1972
1973/* (6 fields, 8 chars each, space separated (5) + '\n') */
1974#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
1975/* account for \'0' */
1976#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
1977
1978static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 1979{
d538bbdf
DL		 1980 assert_spin_locked(&pipe_crc->lock);
1981 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
1982 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 1983}
1984
1985static ssize_t
1986i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
1987 loff_t *pos)
1988{
1989 struct pipe_crc_info *info = filep->private_data;
1990 struct drm_device *dev = info->dev;
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1992 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1993 char buf[PIPE_CRC_BUFFER_LEN];
1994 int head, tail, n_entries, n;
1995 ssize_t bytes_read;
1996
1997 /*
1998 * Don't allow user space to provide buffers not big enough to hold
1999 * a line of data.
2000 */
2001 if (count < PIPE_CRC_LINE_LEN)
2002 return -EINVAL;
2003
2004 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2005 return 0;
07144428
DL		 2006
2007 /* nothing to read */
d538bbdf 2008 spin_lock_irq(&pipe_crc->lock);
07144428 2009 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2010 int ret;
2011
2012 if (filep->f_flags & O_NONBLOCK) {
2013 spin_unlock_irq(&pipe_crc->lock);
07144428 2014 return -EAGAIN;
d538bbdf 2015 }
07144428 2016
d538bbdf
DL		 2017 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2018 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2019 if (ret) {
2020 spin_unlock_irq(&pipe_crc->lock);
2021 return ret;
2022 }
8bf1e9f1
SH		 2023 }
2024
07144428 2025 /* We now have one or more entries to read */
d538bbdf
DL		 2026 head = pipe_crc->head;
2027 tail = pipe_crc->tail;
07144428
DL		 2028 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2029 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2030 spin_unlock_irq(&pipe_crc->lock);
2031
07144428
DL		 2032 bytes_read = 0;
2033 n = 0;
2034 do {
b2c88f5b 2035 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2036 int ret;
8bf1e9f1 2037
07144428
DL		 2038 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2039 "%8u %8x %8x %8x %8x %8x\n",
2040 entry->frame, entry->crc[0],
2041 entry->crc[1], entry->crc[2],
2042 entry->crc[3], entry->crc[4]);
2043
2044 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2045 buf, PIPE_CRC_LINE_LEN);
2046 if (ret == PIPE_CRC_LINE_LEN)
2047 return -EFAULT;
b2c88f5b
DL		 2048
2049 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2050 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2051 n++;
2052 } while (--n_entries);
8bf1e9f1 2053
d538bbdf
DL		 2054 spin_lock_irq(&pipe_crc->lock);
2055 pipe_crc->tail = tail;
2056 spin_unlock_irq(&pipe_crc->lock);
2057
07144428
DL		 2058 return bytes_read;
2059}
2060
2061static const struct file_operations i915_pipe_crc_fops = {
2062 .owner = THIS_MODULE,
2063 .open = i915_pipe_crc_open,
2064 .read = i915_pipe_crc_read,
2065 .release = i915_pipe_crc_release,
2066};
2067
2068static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2069 {
2070 .name = "i915_pipe_A_crc",
2071 .pipe = PIPE_A,
2072 },
2073 {
2074 .name = "i915_pipe_B_crc",
2075 .pipe = PIPE_B,
2076 },
2077 {
2078 .name = "i915_pipe_C_crc",
2079 .pipe = PIPE_C,
2080 },
2081};
2082
2083static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2084 enum pipe pipe)
2085{
2086 struct drm_device *dev = minor->dev;
2087 struct dentry *ent;
2088 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2089
2090 info->dev = dev;
2091 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2092 &i915_pipe_crc_fops);
2093 if (IS_ERR(ent))
2094 return PTR_ERR(ent);
2095
2096 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2097}
2098
e8dfcf78 2099static const char * const pipe_crc_sources[] = {
926321d5
DV		 2100 "none",
2101 "plane1",
2102 "plane2",
2103 "pf",
5b3a856b 2104 "pipe",
3d099a05
DV		 2105 "TV",
2106 "DP-B",
2107 "DP-C",
2108 "DP-D",
46a19188 2109 "auto",
926321d5
DV		 2110};
2111
2112static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2113{
2114 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2115 return pipe_crc_sources[source];
2116}
2117
bd9db02f 2118static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2119{
2120 struct drm_device *dev = m->private;
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 int i;
2123
2124 for (i = 0; i < I915_MAX_PIPES; i++)
2125 seq_printf(m, "%c %s\n", pipe_name(i),
2126 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2127
2128 return 0;
2129}
2130
bd9db02f 2131static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2132{
2133 struct drm_device *dev = inode->i_private;
2134
bd9db02f 2135 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2136}
2137
46a19188 2138static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2139 uint32_t *val)
2140{
46a19188
DV		 2141 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2142 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2143
2144 switch (*source) {
52f843f6
DV		 2145 case INTEL_PIPE_CRC_SOURCE_PIPE:
2146 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2147 break;
2148 case INTEL_PIPE_CRC_SOURCE_NONE:
2149 *val = 0;
2150 break;
2151 default:
2152 return -EINVAL;
2153 }
2154
2155 return 0;
2156}
2157
46a19188
DV		 2158static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2159 enum intel_pipe_crc_source *source)
2160{
2161 struct intel_encoder *encoder;
2162 struct intel_crtc *crtc;
26756809 2163 struct intel_digital_port *dig_port;
46a19188
DV		 2164 int ret = 0;
2165
2166 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2167
2168 mutex_lock(&dev->mode_config.mutex);
2169 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2170 base.head) {
2171 if (!encoder->base.crtc)
2172 continue;
2173
2174 crtc = to_intel_crtc(encoder->base.crtc);
2175
2176 if (crtc->pipe != pipe)
2177 continue;
2178
2179 switch (encoder->type) {
2180 case INTEL_OUTPUT_TVOUT:
2181 *source = INTEL_PIPE_CRC_SOURCE_TV;
2182 break;
2183 case INTEL_OUTPUT_DISPLAYPORT:
2184 case INTEL_OUTPUT_EDP:
26756809
DV		 2185 dig_port = enc_to_dig_port(&encoder->base);
2186 switch (dig_port->port) {
2187 case PORT_B:
2188 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2189 break;
2190 case PORT_C:
2191 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2192 break;
2193 case PORT_D:
2194 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2195 break;
2196 default:
2197 WARN(1, "nonexisting DP port %c\n",
2198 port_name(dig_port->port));
2199 break;
2200 }
46a19188
DV		 2201 break;
2202 }
2203 }
2204 mutex_unlock(&dev->mode_config.mutex);
2205
2206 return ret;
2207}
2208
2209static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2210 enum pipe pipe,
2211 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2212 uint32_t *val)
2213{
8d2f24ca
DV		 2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215 bool need_stable_symbols = false;
2216
46a19188
DV		 2217 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2218 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2219 if (ret)
2220 return ret;
2221 }
2222
2223 switch (*source) {
7ac0129b
DV		 2224 case INTEL_PIPE_CRC_SOURCE_PIPE:
2225 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2226 break;
2227 case INTEL_PIPE_CRC_SOURCE_DP_B:
2228 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2229 need_stable_symbols = true;
7ac0129b
DV		 2230 break;
2231 case INTEL_PIPE_CRC_SOURCE_DP_C:
2232 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2233 need_stable_symbols = true;
7ac0129b
DV		 2234 break;
2235 case INTEL_PIPE_CRC_SOURCE_NONE:
2236 *val = 0;
2237 break;
2238 default:
2239 return -EINVAL;
2240 }
2241
8d2f24ca
DV		 2242 /*
2243 * When the pipe CRC tap point is after the transcoders we need
2244 * to tweak symbol-level features to produce a deterministic series of
2245 * symbols for a given frame. We need to reset those features only once
2246 * a frame (instead of every nth symbol):
2247 * - DC-balance: used to ensure a better clock recovery from the data
2248 * link (SDVO)
2249 * - DisplayPort scrambling: used for EMI reduction
2250 */
2251 if (need_stable_symbols) {
2252 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2253
2254 WARN_ON(!IS_G4X(dev));
2255
2256 tmp |= DC_BALANCE_RESET_VLV;
2257 if (pipe == PIPE_A)
2258 tmp |= PIPE_A_SCRAMBLE_RESET;
2259 else
2260 tmp |= PIPE_B_SCRAMBLE_RESET;
2261
2262 I915_WRITE(PORT_DFT2_G4X, tmp);
2263 }
2264
7ac0129b
DV		 2265 return 0;
2266}
2267
4b79ebf7 2268static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2269 enum pipe pipe,
2270 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2271 uint32_t *val)
2272{
84093603
DV		 2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274 bool need_stable_symbols = false;
2275
46a19188
DV		 2276 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2277 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2278 if (ret)
2279 return ret;
2280 }
2281
2282 switch (*source) {
4b79ebf7
DV		 2283 case INTEL_PIPE_CRC_SOURCE_PIPE:
2284 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2285 break;
2286 case INTEL_PIPE_CRC_SOURCE_TV:
2287 if (!SUPPORTS_TV(dev))
2288 return -EINVAL;
2289 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2290 break;
2291 case INTEL_PIPE_CRC_SOURCE_DP_B:
2292 if (!IS_G4X(dev))
2293 return -EINVAL;
2294 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2295 need_stable_symbols = true;
4b79ebf7
DV		 2296 break;
2297 case INTEL_PIPE_CRC_SOURCE_DP_C:
2298 if (!IS_G4X(dev))
2299 return -EINVAL;
2300 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2301 need_stable_symbols = true;
4b79ebf7
DV		 2302 break;
2303 case INTEL_PIPE_CRC_SOURCE_DP_D:
2304 if (!IS_G4X(dev))
2305 return -EINVAL;
2306 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2307 need_stable_symbols = true;
4b79ebf7
DV		 2308 break;
2309 case INTEL_PIPE_CRC_SOURCE_NONE:
2310 *val = 0;
2311 break;
2312 default:
2313 return -EINVAL;
2314 }
2315
84093603
DV		 2316 /*
2317 * When the pipe CRC tap point is after the transcoders we need
2318 * to tweak symbol-level features to produce a deterministic series of
2319 * symbols for a given frame. We need to reset those features only once
2320 * a frame (instead of every nth symbol):
2321 * - DC-balance: used to ensure a better clock recovery from the data
2322 * link (SDVO)
2323 * - DisplayPort scrambling: used for EMI reduction
2324 */
2325 if (need_stable_symbols) {
2326 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2327
2328 WARN_ON(!IS_G4X(dev));
2329
2330 I915_WRITE(PORT_DFT_I9XX,
2331 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2332
2333 if (pipe == PIPE_A)
2334 tmp |= PIPE_A_SCRAMBLE_RESET;
2335 else
2336 tmp |= PIPE_B_SCRAMBLE_RESET;
2337
2338 I915_WRITE(PORT_DFT2_G4X, tmp);
2339 }
2340
4b79ebf7
DV		 2341 return 0;
2342}
2343
8d2f24ca
DV		 2344static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2345 enum pipe pipe)
2346{
2347 struct drm_i915_private *dev_priv = dev->dev_private;
2348 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2349
2350 if (pipe == PIPE_A)
2351 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2352 else
2353 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2354 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2355 tmp &= ~DC_BALANCE_RESET_VLV;
2356 I915_WRITE(PORT_DFT2_G4X, tmp);
2357
2358}
2359
84093603
DV		 2360static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2361 enum pipe pipe)
2362{
2363 struct drm_i915_private *dev_priv = dev->dev_private;
2364 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2365
2366 if (pipe == PIPE_A)
2367 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2368 else
2369 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2370 I915_WRITE(PORT_DFT2_G4X, tmp);
2371
2372 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2373 I915_WRITE(PORT_DFT_I9XX,
2374 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2375 }
2376}
2377
46a19188 2378static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2379 uint32_t *val)
2380{
46a19188
DV		 2381 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2382 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2383
2384 switch (*source) {
5b3a856b
DV		 2385 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2386 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2387 break;
2388 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2389 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2390 break;
5b3a856b
DV		 2391 case INTEL_PIPE_CRC_SOURCE_PIPE:
2392 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2393 break;
3d099a05 2394 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2395 *val = 0;
2396 break;
3d099a05
DV		 2397 default:
2398 return -EINVAL;
5b3a856b
DV		 2399 }
2400
2401 return 0;
2402}
2403
46a19188 2404static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2405 uint32_t *val)
2406{
46a19188
DV		 2407 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2408 *source = INTEL_PIPE_CRC_SOURCE_PF;
2409
2410 switch (*source) {
5b3a856b
DV		 2411 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2412 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2413 break;
2414 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2415 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2416 break;
2417 case INTEL_PIPE_CRC_SOURCE_PF:
2418 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2419 break;
3d099a05 2420 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2421 *val = 0;
2422 break;
3d099a05
DV		 2423 default:
2424 return -EINVAL;
5b3a856b
DV		 2425 }
2426
2427 return 0;
2428}
2429
926321d5
DV		 2430static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2431 enum intel_pipe_crc_source source)
2432{
2433 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2434 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2435 u32 val = 0; /* shut up gcc */
5b3a856b 2436 int ret;
926321d5 2437
cc3da175
DL		 2438 if (pipe_crc->source == source)
2439 return 0;
2440
ae676fcd
DL		 2441 /* forbid changing the source without going back to 'none' */
2442 if (pipe_crc->source && source)
2443 return -EINVAL;
2444
52f843f6 2445 if (IS_GEN2(dev))
46a19188 2446 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2447 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2448 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2449 else if (IS_VALLEYVIEW(dev))
46a19188 2450 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2451 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2452 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2453 else
46a19188 2454 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2455
2456 if (ret != 0)
2457 return ret;
2458
4b584369
DL		 2459 /* none -> real source transition */
2460 if (source) {
7cd6ccff
DL		 2461 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2462 pipe_name(pipe), pipe_crc_source_name(source));
2463
e5f75aca
DL		 2464 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2465 INTEL_PIPE_CRC_ENTRIES_NR,
2466 GFP_KERNEL);
2467 if (!pipe_crc->entries)
2468 return -ENOMEM;
2469
d538bbdf
DL		 2470 spin_lock_irq(&pipe_crc->lock);
2471 pipe_crc->head = 0;
2472 pipe_crc->tail = 0;
2473 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2474 }
2475
cc3da175 2476 pipe_crc->source = source;
926321d5 2477
926321d5
DV		 2478 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2479 POSTING_READ(PIPE_CRC_CTL(pipe));
2480
e5f75aca
DL		 2481 /* real source -> none transition */
2482 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2483 struct intel_pipe_crc_entry *entries;
2484
7cd6ccff
DL		 2485 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2486 pipe_name(pipe));
2487
bcf17ab2
DV		 2488 intel_wait_for_vblank(dev, pipe);
2489
d538bbdf
DL		 2490 spin_lock_irq(&pipe_crc->lock);
2491 entries = pipe_crc->entries;
e5f75aca 2492 pipe_crc->entries = NULL;
d538bbdf
DL		 2493 spin_unlock_irq(&pipe_crc->lock);
2494
2495 kfree(entries);
84093603
DV		 2496
2497 if (IS_G4X(dev))
2498 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2499 else if (IS_VALLEYVIEW(dev))
2500 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2501 }
2502
926321d5
DV		 2503 return 0;
2504}
2505
2506/*
2507 * Parse pipe CRC command strings:
b94dec87
DL		 2508 * command: wsp* object wsp+ name wsp+ source wsp*
2509 * object: 'pipe'
2510 * name: (A | B | C)
926321d5
DV		 2511 * source: (none | plane1 | plane2 | pf)
2512 * wsp: (#0x20 | #0x9 | #0xA)+
2513 *
2514 * eg.:
b94dec87
DL		 2515 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2516 * "pipe A none" -> Stop CRC
926321d5 2517 */
bd9db02f 2518static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2519{
2520 int n_words = 0;
2521
2522 while (*buf) {
2523 char *end;
2524
2525 /* skip leading white space */
2526 buf = skip_spaces(buf);
2527 if (!*buf)
2528 break; /* end of buffer */
2529
2530 /* find end of word */
2531 for (end = buf; *end && !isspace(*end); end++)
2532 ;
2533
2534 if (n_words == max_words) {
2535 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2536 max_words);
2537 return -EINVAL; /* ran out of words[] before bytes */
2538 }
2539
2540 if (*end)
2541 *end++ = '\0';
2542 words[n_words++] = buf;
2543 buf = end;
2544 }
2545
2546 return n_words;
2547}
2548
b94dec87
DL		 2549enum intel_pipe_crc_object {
2550 PIPE_CRC_OBJECT_PIPE,
2551};
2552
e8dfcf78 2553static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2554 "pipe",
2555};
2556
2557static int
bd9db02f 2558display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2559{
2560 int i;
2561
2562 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2563 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2564 *o = i;
b94dec87
DL		 2565 return 0;
2566 }
2567
2568 return -EINVAL;
2569}
2570
bd9db02f 2571static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2572{
2573 const char name = buf[0];
2574
2575 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2576 return -EINVAL;
2577
2578 *pipe = name - 'A';
2579
2580 return 0;
2581}
2582
2583static int
bd9db02f 2584display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 2585{
2586 int i;
2587
2588 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2589 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 2590 *s = i;
926321d5
DV		 2591 return 0;
2592 }
2593
2594 return -EINVAL;
2595}
2596
bd9db02f 2597static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 2598{
b94dec87 2599#define N_WORDS 3
926321d5 2600 int n_words;
b94dec87 2601 char *words[N_WORDS];
926321d5 2602 enum pipe pipe;
b94dec87 2603 enum intel_pipe_crc_object object;
926321d5
DV		 2604 enum intel_pipe_crc_source source;
2605
bd9db02f 2606 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 2607 if (n_words != N_WORDS) {
2608 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2609 N_WORDS);
2610 return -EINVAL;
2611 }
2612
bd9db02f 2613 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 2614 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 2615 return -EINVAL;
2616 }
2617
bd9db02f 2618 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 2619 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 2620 return -EINVAL;
2621 }
2622
bd9db02f 2623 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 2624 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 2625 return -EINVAL;
2626 }
2627
2628 return pipe_crc_set_source(dev, pipe, source);
2629}
2630
bd9db02f
DL		 2631static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2632 size_t len, loff_t *offp)
926321d5
DV		 2633{
2634 struct seq_file *m = file->private_data;
2635 struct drm_device *dev = m->private;
2636 char *tmpbuf;
2637 int ret;
2638
2639 if (len == 0)
2640 return 0;
2641
2642 if (len > PAGE_SIZE - 1) {
2643 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2644 PAGE_SIZE);
2645 return -E2BIG;
2646 }
2647
2648 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2649 if (!tmpbuf)
2650 return -ENOMEM;
2651
2652 if (copy_from_user(tmpbuf, ubuf, len)) {
2653 ret = -EFAULT;
2654 goto out;
2655 }
2656 tmpbuf[len] = '\0';
2657
bd9db02f 2658 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 2659
2660out:
2661 kfree(tmpbuf);
2662 if (ret < 0)
2663 return ret;
2664
2665 *offp += len;
2666 return len;
2667}
2668
bd9db02f 2669static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 2670 .owner = THIS_MODULE,
bd9db02f 2671 .open = display_crc_ctl_open,
926321d5
DV		 2672 .read = seq_read,
2673 .llseek = seq_lseek,
2674 .release = single_release,
bd9db02f 2675 .write = display_crc_ctl_write
926321d5
DV		 2676};
2677
647416f9
KC		 2678static int
2679i915_wedged_get(void *data, u64 *val)
f3cd474b 2680{
647416f9 2681 struct drm_device *dev = data;
f3cd474b 2682 drm_i915_private_t *dev_priv = dev->dev_private;
f3cd474b 2683
647416f9 2684 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 2685
647416f9 2686 return 0;
f3cd474b
CW		 2687}
2688
647416f9
KC		 2689static int
2690i915_wedged_set(void *data, u64 val)
f3cd474b 2691{
647416f9 2692 struct drm_device *dev = data;
f3cd474b 2693
647416f9 2694 DRM_INFO("Manually setting wedged to %llu\n", val);
527f9e90 2695 i915_handle_error(dev, val);
f3cd474b 2696
647416f9 2697 return 0;
f3cd474b
CW		 2698}
2699
647416f9
KC		 2700DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2701 i915_wedged_get, i915_wedged_set,
3a3b4f98 2702 "%llu\n");
f3cd474b 2703
647416f9
KC		 2704static int
2705i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 2706{
647416f9 2707 struct drm_device *dev = data;
e5eb3d63 2708 drm_i915_private_t *dev_priv = dev->dev_private;
e5eb3d63 2709
647416f9 2710 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 2711
647416f9 2712 return 0;
e5eb3d63
DV		 2713}
2714
647416f9
KC		 2715static int
2716i915_ring_stop_set(void *data, u64 val)
e5eb3d63 2717{
647416f9 2718 struct drm_device *dev = data;
e5eb3d63 2719 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2720 int ret;
e5eb3d63 2721
647416f9 2722 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 2723
22bcfc6a
DV		 2724 ret = mutex_lock_interruptible(&dev->struct_mutex);
2725 if (ret)
2726 return ret;
2727
99584db3 2728 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 2729 mutex_unlock(&dev->struct_mutex);
2730
647416f9 2731 return 0;
e5eb3d63
DV		 2732}
2733
647416f9
KC		 2734DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2735 i915_ring_stop_get, i915_ring_stop_set,
2736 "0x%08llx\n");
d5442303 2737
094f9a54
CW		 2738static int
2739i915_ring_missed_irq_get(void *data, u64 *val)
2740{
2741 struct drm_device *dev = data;
2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743
2744 *val = dev_priv->gpu_error.missed_irq_rings;
2745 return 0;
2746}
2747
2748static int
2749i915_ring_missed_irq_set(void *data, u64 val)
2750{
2751 struct drm_device *dev = data;
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 int ret;
2754
2755 /* Lock against concurrent debugfs callers */
2756 ret = mutex_lock_interruptible(&dev->struct_mutex);
2757 if (ret)
2758 return ret;
2759 dev_priv->gpu_error.missed_irq_rings = val;
2760 mutex_unlock(&dev->struct_mutex);
2761
2762 return 0;
2763}
2764
2765DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2766 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2767 "0x%08llx\n");
2768
2769static int
2770i915_ring_test_irq_get(void *data, u64 *val)
2771{
2772 struct drm_device *dev = data;
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774
2775 *val = dev_priv->gpu_error.test_irq_rings;
2776
2777 return 0;
2778}
2779
2780static int
2781i915_ring_test_irq_set(void *data, u64 val)
2782{
2783 struct drm_device *dev = data;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 int ret;
2786
2787 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2788
2789 /* Lock against concurrent debugfs callers */
2790 ret = mutex_lock_interruptible(&dev->struct_mutex);
2791 if (ret)
2792 return ret;
2793
2794 dev_priv->gpu_error.test_irq_rings = val;
2795 mutex_unlock(&dev->struct_mutex);
2796
2797 return 0;
2798}
2799
2800DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2801 i915_ring_test_irq_get, i915_ring_test_irq_set,
2802 "0x%08llx\n");
2803
dd624afd
CW		 2804#define DROP_UNBOUND 0x1
2805#define DROP_BOUND 0x2
2806#define DROP_RETIRE 0x4
2807#define DROP_ACTIVE 0x8
2808#define DROP_ALL (DROP_UNBOUND | \
2809 DROP_BOUND | \
2810 DROP_RETIRE | \
2811 DROP_ACTIVE)
647416f9
KC		 2812static int
2813i915_drop_caches_get(void *data, u64 *val)
dd624afd 2814{
647416f9 2815 *val = DROP_ALL;
dd624afd 2816
647416f9 2817 return 0;
dd624afd
CW		 2818}
2819
647416f9
KC		 2820static int
2821i915_drop_caches_set(void *data, u64 val)
dd624afd 2822{
647416f9 2823 struct drm_device *dev = data;
dd624afd
CW		 2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 2826 struct i915_address_space *vm;
2827 struct i915_vma *vma, *x;
647416f9 2828 int ret;
dd624afd 2829
2f9fe5ff 2830 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 2831
2832 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2833 * on ioctls on -EAGAIN. */
2834 ret = mutex_lock_interruptible(&dev->struct_mutex);
2835 if (ret)
2836 return ret;
2837
2838 if (val & DROP_ACTIVE) {
2839 ret = i915_gpu_idle(dev);
2840 if (ret)
2841 goto unlock;
2842 }
2843
2844 if (val & (DROP_RETIRE | DROP_ACTIVE))
2845 i915_gem_retire_requests(dev);
2846
2847 if (val & DROP_BOUND) {
ca191b13
BW		 2848 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2849 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2850 mm_list) {
d7f46fc4 2851 if (vma->pin_count)
ca191b13
BW		 2852 continue;
2853
2854 ret = i915_vma_unbind(vma);
2855 if (ret)
2856 goto unlock;
2857 }
31a46c9c 2858 }
dd624afd
CW		 2859 }
2860
2861 if (val & DROP_UNBOUND) {
35c20a60
BW		 2862 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2863 global_list)
dd624afd
CW		 2864 if (obj->pages_pin_count == 0) {
2865 ret = i915_gem_object_put_pages(obj);
2866 if (ret)
2867 goto unlock;
2868 }
2869 }
2870
2871unlock:
2872 mutex_unlock(&dev->struct_mutex);
2873
647416f9 2874 return ret;
dd624afd
CW		 2875}
2876
647416f9
KC		 2877DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2878 i915_drop_caches_get, i915_drop_caches_set,
2879 "0x%08llx\n");
dd624afd 2880
647416f9
KC		 2881static int
2882i915_max_freq_get(void *data, u64 *val)
358733e9 2883{
647416f9 2884 struct drm_device *dev = data;
358733e9 2885 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2886 int ret;
004777cb
DV		 2887
2888 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2889 return -ENODEV;
2890
5c9669ce
TR		 2891 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2892
4fc688ce 2893 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2894 if (ret)
2895 return ret;
358733e9 2896
0a073b84 2897 if (IS_VALLEYVIEW(dev))
2ec3815f 2898 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
0a073b84
JB		 2899 else
2900 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2901 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2902
647416f9 2903 return 0;
358733e9
JB		 2904}
2905
647416f9
KC		 2906static int
2907i915_max_freq_set(void *data, u64 val)
358733e9 2908{
647416f9 2909 struct drm_device *dev = data;
358733e9 2910 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2911 int ret;
004777cb
DV		 2912
2913 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2914 return -ENODEV;
358733e9 2915
5c9669ce
TR		 2916 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2917
647416f9 2918 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 2919
4fc688ce 2920 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2921 if (ret)
2922 return ret;
2923
358733e9
JB		 2924 /*
2925 * Turbo will still be enabled, but won't go above the set value.
2926 */
0a073b84 2927 if (IS_VALLEYVIEW(dev)) {
2ec3815f 2928 val = vlv_freq_opcode(dev_priv, val);
0a073b84 2929 dev_priv->rps.max_delay = val;
6917c7b9 2930 valleyview_set_rps(dev, val);
0a073b84
JB		 2931 } else {
2932 do_div(val, GT_FREQUENCY_MULTIPLIER);
2933 dev_priv->rps.max_delay = val;
2934 gen6_set_rps(dev, val);
2935 }
2936
4fc688ce 2937 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 2938
647416f9 2939 return 0;
358733e9
JB		 2940}
2941
647416f9
KC		 2942DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
2943 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 2944 "%llu\n");
358733e9 2945
647416f9
KC		 2946static int
2947i915_min_freq_get(void *data, u64 *val)
1523c310 2948{
647416f9 2949 struct drm_device *dev = data;
1523c310 2950 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 2951 int ret;
004777cb
DV		 2952
2953 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2954 return -ENODEV;
2955
5c9669ce
TR		 2956 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2957
4fc688ce 2958 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2959 if (ret)
2960 return ret;
1523c310 2961
0a073b84 2962 if (IS_VALLEYVIEW(dev))
2ec3815f 2963 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
0a073b84
JB		 2964 else
2965 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
4fc688ce 2966 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 2967
647416f9 2968 return 0;
1523c310
JB		 2969}
2970
647416f9
KC		 2971static int
2972i915_min_freq_set(void *data, u64 val)
1523c310 2973{
647416f9 2974 struct drm_device *dev = data;
1523c310 2975 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 2976 int ret;
004777cb
DV		 2977
2978 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2979 return -ENODEV;
1523c310 2980
5c9669ce
TR		 2981 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2982
647416f9 2983 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 2984
4fc688ce 2985 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 2986 if (ret)
2987 return ret;
2988
1523c310
JB		 2989 /*
2990 * Turbo will still be enabled, but won't go below the set value.
2991 */
0a073b84 2992 if (IS_VALLEYVIEW(dev)) {
2ec3815f 2993 val = vlv_freq_opcode(dev_priv, val);
0a073b84
JB		 2994 dev_priv->rps.min_delay = val;
2995 valleyview_set_rps(dev, val);
2996 } else {
2997 do_div(val, GT_FREQUENCY_MULTIPLIER);
2998 dev_priv->rps.min_delay = val;
2999 gen6_set_rps(dev, val);
3000 }
4fc688ce 3001 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3002
647416f9 3003 return 0;
1523c310
JB		 3004}
3005
647416f9
KC		 3006DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3007 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3008 "%llu\n");
1523c310 3009
647416f9
KC		 3010static int
3011i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3012{
647416f9 3013 struct drm_device *dev = data;
07b7ddd9 3014 drm_i915_private_t *dev_priv = dev->dev_private;
07b7ddd9 3015 u32 snpcr;
647416f9 3016 int ret;
07b7ddd9 3017
004777cb
DV		 3018 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3019 return -ENODEV;
3020
22bcfc6a
DV		 3021 ret = mutex_lock_interruptible(&dev->struct_mutex);
3022 if (ret)
3023 return ret;
3024
07b7ddd9
JB		 3025 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3026 mutex_unlock(&dev_priv->dev->struct_mutex);
3027
647416f9 3028 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3029
647416f9 3030 return 0;
07b7ddd9
JB		 3031}
3032
647416f9
KC		 3033static int
3034i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3035{
647416f9 3036 struct drm_device *dev = data;
07b7ddd9 3037 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3038 u32 snpcr;
07b7ddd9 3039
004777cb
DV		 3040 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3041 return -ENODEV;
3042
647416f9 3043 if (val > 3)
07b7ddd9
JB		 3044 return -EINVAL;
3045
647416f9 3046 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3047
3048 /* Update the cache sharing policy here as well */
3049 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3050 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3051 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3052 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3053
647416f9 3054 return 0;
07b7ddd9
JB		 3055}
3056
647416f9
KC		 3057DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3058 i915_cache_sharing_get, i915_cache_sharing_set,
3059 "%llu\n");
07b7ddd9 3060
6d794d42
BW		 3061static int i915_forcewake_open(struct inode *inode, struct file *file)
3062{
3063 struct drm_device *dev = inode->i_private;
3064 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3065
075edca4 3066 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3067 return 0;
3068
c8d9a590 3069 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3070
3071 return 0;
3072}
3073
c43b5634 3074static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3075{
3076 struct drm_device *dev = inode->i_private;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078
075edca4 3079 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3080 return 0;
3081
c8d9a590 3082 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3083
3084 return 0;
3085}
3086
3087static const struct file_operations i915_forcewake_fops = {
3088 .owner = THIS_MODULE,
3089 .open = i915_forcewake_open,
3090 .release = i915_forcewake_release,
3091};
3092
3093static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3094{
3095 struct drm_device *dev = minor->dev;
3096 struct dentry *ent;
3097
3098 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3099 S_IRUSR,
6d794d42
BW		 3100 root, dev,
3101 &i915_forcewake_fops);
3102 if (IS_ERR(ent))
3103 return PTR_ERR(ent);
3104
8eb57294 3105 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3106}
3107
6a9c308d
DV		 3108static int i915_debugfs_create(struct dentry *root,
3109 struct drm_minor *minor,
3110 const char *name,
3111 const struct file_operations *fops)
07b7ddd9
JB		 3112{
3113 struct drm_device *dev = minor->dev;
3114 struct dentry *ent;
3115
6a9c308d 3116 ent = debugfs_create_file(name,
07b7ddd9
JB		 3117 S_IRUGO | S_IWUSR,
3118 root, dev,
6a9c308d 3119 fops);
07b7ddd9
JB		 3120 if (IS_ERR(ent))
3121 return PTR_ERR(ent);
3122
6a9c308d 3123 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3124}
3125
06c5bf8c 3126static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3127 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3128 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3129 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3130 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3131 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3132 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3133 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3134 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3135 {"i915_gem_request", i915_gem_request_info, 0},
3136 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3137 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3138 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3139 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3140 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3141 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3142 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1
JB		 3143 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3144 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3145 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3146 {"i915_inttoext_table", i915_inttoext_table, 0},
3147 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3148 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3149 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 3150 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 3151 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3152 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3153 {"i915_sr_status", i915_sr_status, 0},
44834a67 3154 {"i915_opregion", i915_opregion, 0},
37811fcc 3155 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3156 {"i915_context_status", i915_context_status, 0},
6d794d42 3157 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3158 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3159 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 3160 {"i915_dpio", i915_dpio_info, 0},
63573eb7 3161 {"i915_llc", i915_llc, 0},
e91fd8c6 3162 {"i915_edp_psr_status", i915_edp_psr_status, 0},
ec013e7f 3163 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3164 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3165 {"i915_power_domain_info", i915_power_domain_info, 0},
2017263e 3166};
27c202ad 3167#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3168
06c5bf8c 3169static const struct i915_debugfs_files {
34b9674c
DV		 3170 const char *name;
3171 const struct file_operations *fops;
3172} i915_debugfs_files[] = {
3173 {"i915_wedged", &i915_wedged_fops},
3174 {"i915_max_freq", &i915_max_freq_fops},
3175 {"i915_min_freq", &i915_min_freq_fops},
3176 {"i915_cache_sharing", &i915_cache_sharing_fops},
3177 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3178 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3179 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3180 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3181 {"i915_error_state", &i915_error_state_fops},
3182 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3183 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
34b9674c
DV		 3184};
3185
07144428
DL		 3186void intel_display_crc_init(struct drm_device *dev)
3187{
3188 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3189 enum pipe pipe;
07144428 3190
b378360e
DV		 3191 for_each_pipe(pipe) {
3192 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3193
d538bbdf
DL		 3194 pipe_crc->opened = false;
3195 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3196 init_waitqueue_head(&pipe_crc->wq);
3197 }
3198}
3199
27c202ad 3200int i915_debugfs_init(struct drm_minor *minor)
2017263e 3201{
34b9674c 3202 int ret, i;
f3cd474b 3203
6d794d42 3204 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3205 if (ret)
3206 return ret;
6a9c308d 3207
07144428
DL		 3208 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3209 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3210 if (ret)
3211 return ret;
3212 }
3213
34b9674c
DV		 3214 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3215 ret = i915_debugfs_create(minor->debugfs_root, minor,
3216 i915_debugfs_files[i].name,
3217 i915_debugfs_files[i].fops);
3218 if (ret)
3219 return ret;
3220 }
40633219 3221
27c202ad
BG		 3222 return drm_debugfs_create_files(i915_debugfs_list,
3223 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3224 minor->debugfs_root, minor);
3225}
3226
27c202ad 3227void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3228{
34b9674c
DV		 3229 int i;
3230
27c202ad
BG		 3231 drm_debugfs_remove_files(i915_debugfs_list,
3232 I915_DEBUGFS_ENTRIES, minor);
07144428 3233
6d794d42
BW		 3234 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3235 1, minor);
07144428 3236
e309a997 3237 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3238 struct drm_info_list *info_list =
3239 (struct drm_info_list *)&i915_pipe_crc_data[i];
3240
3241 drm_debugfs_remove_files(info_list, 1, minor);
3242 }
3243
34b9674c
DV		 3244 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3245 struct drm_info_list *info_list =
3246 (struct drm_info_list *) i915_debugfs_files[i].fops;
3247
3248 drm_debugfs_remove_files(info_list, 1, minor);
3249 }
2017263e
BG		 3250}
3251
3252#endif /* CONFIG_DEBUG_FS */
Linux 6.x block layer and io_uring tree(s)