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drm/i915: Make vlv and chv forcewake put generic.
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
fb1ae911 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 142 list_for_each_entry(vma, &obj->vma_list, vma_link)
143 if (vma->pin_count > 0)
144 pin_count++;
145 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 146 if (obj->pin_display)
147 seq_printf(m, " (display)");
37811fcc
CW		 148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
fe14d5f4
TU		 155 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
156 vma->node.start, vma->node.size,
157 vma->ggtt_view.type);
1d693bcc 158 }
c1ad11fc
CW		 159 if (obj->stolen)
160 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 161 if (obj->pin_mappable || obj->fault_mappable) {
162 char s[3], *t = s;
163 if (obj->pin_mappable)
164 *t++ = 'p';
165 if (obj->fault_mappable)
166 *t++ = 'f';
167 *t = '\0';
168 seq_printf(m, " (%s mappable)", s);
169 }
41c52415
JH		 170 if (obj->last_read_req != NULL)
171 seq_printf(m, " (%s)",
172 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 336 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 337 continue;
338
41c52415 339 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
41c52415 349 if (obj->active)
6313c204
CW		 350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
493018dc
BV		 363#define print_file_stats(m, name, stats) \
364 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
365 name, \
366 stats.count, \
367 stats.total, \
368 stats.active, \
369 stats.inactive, \
370 stats.global, \
371 stats.shared, \
372 stats.unbound)
373
374static void print_batch_pool_stats(struct seq_file *m,
375 struct drm_i915_private *dev_priv)
376{
377 struct drm_i915_gem_object *obj;
378 struct file_stats stats;
379
380 memset(&stats, 0, sizeof(stats));
381
382 list_for_each_entry(obj,
383 &dev_priv->mm.batch_pool.cache_list,
384 batch_pool_list)
385 per_file_stats(0, obj, &stats);
386
387 print_file_stats(m, "batch pool", stats);
388}
389
ca191b13
BW		 390#define count_vmas(list, member) do { \
391 list_for_each_entry(vma, list, member) { \
392 size += i915_gem_obj_ggtt_size(vma->obj); \
393 ++count; \
394 if (vma->obj->map_and_fenceable) { \
395 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
396 ++mappable_count; \
397 } \
398 } \
399} while (0)
400
401static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 402{
9f25d007 403 struct drm_info_node *node = m->private;
73aa808f
CW		 404 struct drm_device *dev = node->minor->dev;
405 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 406 u32 count, mappable_count, purgeable_count;
407 size_t size, mappable_size, purgeable_size;
6299f992 408 struct drm_i915_gem_object *obj;
5cef07e1 409 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 410 struct drm_file *file;
ca191b13 411 struct i915_vma *vma;
73aa808f
CW		 412 int ret;
413
414 ret = mutex_lock_interruptible(&dev->struct_mutex);
415 if (ret)
416 return ret;
417
6299f992
CW		 418 seq_printf(m, "%u objects, %zu bytes\n",
419 dev_priv->mm.object_count,
420 dev_priv->mm.object_memory);
421
422 size = count = mappable_size = mappable_count = 0;
35c20a60 423 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 424 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
425 count, mappable_count, size, mappable_size);
426
427 size = count = mappable_size = mappable_count = 0;
ca191b13 428 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 429 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
430 count, mappable_count, size, mappable_size);
431
6299f992 432 size = count = mappable_size = mappable_count = 0;
ca191b13 433 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 434 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
435 count, mappable_count, size, mappable_size);
436
b7abb714 437 size = count = purgeable_size = purgeable_count = 0;
35c20a60 438 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 439 size += obj->base.size, ++count;
b7abb714
CW		 440 if (obj->madv == I915_MADV_DONTNEED)
441 purgeable_size += obj->base.size, ++purgeable_count;
442 }
6c085a72
CW		 443 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
444
6299f992 445 size = count = mappable_size = mappable_count = 0;
35c20a60 446 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 447 if (obj->fault_mappable) {
f343c5f6 448 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 449 ++count;
450 }
451 if (obj->pin_mappable) {
f343c5f6 452 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 453 ++mappable_count;
454 }
b7abb714
CW		 455 if (obj->madv == I915_MADV_DONTNEED) {
456 purgeable_size += obj->base.size;
457 ++purgeable_count;
458 }
6299f992 459 }
b7abb714
CW		 460 seq_printf(m, "%u purgeable objects, %zu bytes\n",
461 purgeable_count, purgeable_size);
6299f992
CW		 462 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
463 mappable_count, mappable_size);
464 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
465 count, size);
466
93d18799 467 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 468 dev_priv->gtt.base.total,
469 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 470
493018dc
BV		 471 seq_putc(m, '\n');
472 print_batch_pool_stats(m, dev_priv);
473
267f0c90 474 seq_putc(m, '\n');
2db8e9d6
CW		 475 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
476 struct file_stats stats;
3ec2f427 477 struct task_struct *task;
2db8e9d6
CW		 478
479 memset(&stats, 0, sizeof(stats));
6313c204 480 stats.file_priv = file->driver_priv;
5b5ffff0 481 spin_lock(&file->table_lock);
2db8e9d6 482 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 483 spin_unlock(&file->table_lock);
3ec2f427
TH		 484 /*
485 * Although we have a valid reference on file->pid, that does
486 * not guarantee that the task_struct who called get_pid() is
487 * still alive (e.g. get_pid(current) => fork() => exit()).
488 * Therefore, we need to protect this ->comm access using RCU.
489 */
490 rcu_read_lock();
491 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 492 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 493 rcu_read_unlock();
2db8e9d6
CW		 494 }
495
73aa808f
CW		 496 mutex_unlock(&dev->struct_mutex);
497
498 return 0;
499}
500
aee56cff 501static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 502{
9f25d007 503 struct drm_info_node *node = m->private;
08c18323 504 struct drm_device *dev = node->minor->dev;
1b50247a 505 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 506 struct drm_i915_private *dev_priv = dev->dev_private;
507 struct drm_i915_gem_object *obj;
508 size_t total_obj_size, total_gtt_size;
509 int count, ret;
510
511 ret = mutex_lock_interruptible(&dev->struct_mutex);
512 if (ret)
513 return ret;
514
515 total_obj_size = total_gtt_size = count = 0;
35c20a60 516 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 517 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 518 continue;
519
267f0c90 520 seq_puts(m, " ");
08c18323 521 describe_obj(m, obj);
267f0c90 522 seq_putc(m, '\n');
08c18323 523 total_obj_size += obj->base.size;
f343c5f6 524 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 525 count++;
526 }
527
528 mutex_unlock(&dev->struct_mutex);
529
530 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
531 count, total_obj_size, total_gtt_size);
532
533 return 0;
534}
535
4e5359cd
SF		 536static int i915_gem_pageflip_info(struct seq_file *m, void *data)
537{
9f25d007 538 struct drm_info_node *node = m->private;
4e5359cd 539 struct drm_device *dev = node->minor->dev;
d6bbafa1 540 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 541 struct intel_crtc *crtc;
8a270ebf
DV		 542 int ret;
543
544 ret = mutex_lock_interruptible(&dev->struct_mutex);
545 if (ret)
546 return ret;
4e5359cd 547
d3fcc808 548 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 549 const char pipe = pipe_name(crtc->pipe);
550 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 551 struct intel_unpin_work *work;
552
5e2d7afc 553 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 554 work = crtc->unpin_work;
555 if (work == NULL) {
9db4a9c7 556 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 557 pipe, plane);
558 } else {
d6bbafa1
CW		 559 u32 addr;
560
e7d841ca 561 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 562 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 563 pipe, plane);
564 } else {
9db4a9c7 565 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 566 pipe, plane);
567 }
3a8a946e
DV		 568 if (work->flip_queued_req) {
569 struct intel_engine_cs *ring =
570 i915_gem_request_get_ring(work->flip_queued_req);
571
d6bbafa1 572 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
3a8a946e 573 ring->name,
f06cc1b9 574 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 575 dev_priv->next_seqno,
3a8a946e 576 ring->get_seqno(ring, true),
1b5a433a 577 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 578 } else
579 seq_printf(m, "Flip not associated with any ring\n");
580 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
581 work->flip_queued_vblank,
582 work->flip_ready_vblank,
583 drm_vblank_count(dev, crtc->pipe));
4e5359cd 584 if (work->enable_stall_check)
267f0c90 585 seq_puts(m, "Stall check enabled, ");
4e5359cd 586 else
267f0c90 587 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 588 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 589
d6bbafa1
CW		 590 if (INTEL_INFO(dev)->gen >= 4)
591 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
592 else
593 addr = I915_READ(DSPADDR(crtc->plane));
594 seq_printf(m, "Current scanout address 0x%08x\n", addr);
595
4e5359cd 596 if (work->pending_flip_obj) {
d6bbafa1
CW		 597 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
598 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 599 }
600 }
5e2d7afc 601 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 602 }
603
8a270ebf
DV		 604 mutex_unlock(&dev->struct_mutex);
605
4e5359cd
SF		 606 return 0;
607}
608
493018dc
BV		 609static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
610{
611 struct drm_info_node *node = m->private;
612 struct drm_device *dev = node->minor->dev;
613 struct drm_i915_private *dev_priv = dev->dev_private;
614 struct drm_i915_gem_object *obj;
615 int count = 0;
616 int ret;
617
618 ret = mutex_lock_interruptible(&dev->struct_mutex);
619 if (ret)
620 return ret;
621
622 seq_puts(m, "cache:\n");
623 list_for_each_entry(obj,
624 &dev_priv->mm.batch_pool.cache_list,
625 batch_pool_list) {
626 seq_puts(m, " ");
627 describe_obj(m, obj);
628 seq_putc(m, '\n');
629 count++;
630 }
631
632 seq_printf(m, "total: %d\n", count);
633
634 mutex_unlock(&dev->struct_mutex);
635
636 return 0;
637}
638
2017263e
BG		 639static int i915_gem_request_info(struct seq_file *m, void *data)
640{
9f25d007 641 struct drm_info_node *node = m->private;
2017263e 642 struct drm_device *dev = node->minor->dev;
e277a1f8 643 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 644 struct intel_engine_cs *ring;
2017263e 645 struct drm_i915_gem_request *gem_request;
a2c7f6fd 646 int ret, count, i;
de227ef0
CW		 647
648 ret = mutex_lock_interruptible(&dev->struct_mutex);
649 if (ret)
650 return ret;
2017263e 651
c2c347a9 652 count = 0;
a2c7f6fd
CW		 653 for_each_ring(ring, dev_priv, i) {
654 if (list_empty(&ring->request_list))
655 continue;
656
657 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 658 list_for_each_entry(gem_request,
a2c7f6fd 659 &ring->request_list,
c2c347a9
CW		 660 list) {
661 seq_printf(m, " %d @ %d\n",
662 gem_request->seqno,
663 (int) (jiffies - gem_request->emitted_jiffies));
664 }
665 count++;
2017263e 666 }
de227ef0
CW		 667 mutex_unlock(&dev->struct_mutex);
668
c2c347a9 669 if (count == 0)
267f0c90 670 seq_puts(m, "No requests\n");
c2c347a9 671
2017263e
BG		 672 return 0;
673}
674
b2223497 675static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 676 struct intel_engine_cs *ring)
b2223497
CW		 677{
678 if (ring->get_seqno) {
43a7b924 679 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 680 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 681 }
682}
683
2017263e
BG		 684static int i915_gem_seqno_info(struct seq_file *m, void *data)
685{
9f25d007 686 struct drm_info_node *node = m->private;
2017263e 687 struct drm_device *dev = node->minor->dev;
e277a1f8 688 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 689 struct intel_engine_cs *ring;
1ec14ad3 690 int ret, i;
de227ef0
CW		 691
692 ret = mutex_lock_interruptible(&dev->struct_mutex);
693 if (ret)
694 return ret;
c8c8fb33 695 intel_runtime_pm_get(dev_priv);
2017263e 696
a2c7f6fd
CW		 697 for_each_ring(ring, dev_priv, i)
698 i915_ring_seqno_info(m, ring);
de227ef0 699
c8c8fb33 700 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 701 mutex_unlock(&dev->struct_mutex);
702
2017263e
BG		 703 return 0;
704}
705
706
707static int i915_interrupt_info(struct seq_file *m, void *data)
708{
9f25d007 709 struct drm_info_node *node = m->private;
2017263e 710 struct drm_device *dev = node->minor->dev;
e277a1f8 711 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 712 struct intel_engine_cs *ring;
9db4a9c7 713 int ret, i, pipe;
de227ef0
CW		 714
715 ret = mutex_lock_interruptible(&dev->struct_mutex);
716 if (ret)
717 return ret;
c8c8fb33 718 intel_runtime_pm_get(dev_priv);
2017263e 719
74e1ca8c 720 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 721 seq_printf(m, "Master Interrupt Control:\t%08x\n",
722 I915_READ(GEN8_MASTER_IRQ));
723
724 seq_printf(m, "Display IER:\t%08x\n",
725 I915_READ(VLV_IER));
726 seq_printf(m, "Display IIR:\t%08x\n",
727 I915_READ(VLV_IIR));
728 seq_printf(m, "Display IIR_RW:\t%08x\n",
729 I915_READ(VLV_IIR_RW));
730 seq_printf(m, "Display IMR:\t%08x\n",
731 I915_READ(VLV_IMR));
055e393f 732 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 733 seq_printf(m, "Pipe %c stat:\t%08x\n",
734 pipe_name(pipe),
735 I915_READ(PIPESTAT(pipe)));
736
737 seq_printf(m, "Port hotplug:\t%08x\n",
738 I915_READ(PORT_HOTPLUG_EN));
739 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
740 I915_READ(VLV_DPFLIPSTAT));
741 seq_printf(m, "DPINVGTT:\t%08x\n",
742 I915_READ(DPINVGTT));
743
744 for (i = 0; i < 4; i++) {
745 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
746 i, I915_READ(GEN8_GT_IMR(i)));
747 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
748 i, I915_READ(GEN8_GT_IIR(i)));
749 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
750 i, I915_READ(GEN8_GT_IER(i)));
751 }
752
753 seq_printf(m, "PCU interrupt mask:\t%08x\n",
754 I915_READ(GEN8_PCU_IMR));
755 seq_printf(m, "PCU interrupt identity:\t%08x\n",
756 I915_READ(GEN8_PCU_IIR));
757 seq_printf(m, "PCU interrupt enable:\t%08x\n",
758 I915_READ(GEN8_PCU_IER));
759 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 760 seq_printf(m, "Master Interrupt Control:\t%08x\n",
761 I915_READ(GEN8_MASTER_IRQ));
762
763 for (i = 0; i < 4; i++) {
764 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
765 i, I915_READ(GEN8_GT_IMR(i)));
766 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
767 i, I915_READ(GEN8_GT_IIR(i)));
768 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
769 i, I915_READ(GEN8_GT_IER(i)));
770 }
771
055e393f 772 for_each_pipe(dev_priv, pipe) {
f458ebbc 773 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 774 POWER_DOMAIN_PIPE(pipe))) {
775 seq_printf(m, "Pipe %c power disabled\n",
776 pipe_name(pipe));
777 continue;
778 }
a123f157 779 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 780 pipe_name(pipe),
781 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 782 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 783 pipe_name(pipe),
784 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 785 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 786 pipe_name(pipe),
787 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 788 }
789
790 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
791 I915_READ(GEN8_DE_PORT_IMR));
792 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
793 I915_READ(GEN8_DE_PORT_IIR));
794 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
795 I915_READ(GEN8_DE_PORT_IER));
796
797 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
798 I915_READ(GEN8_DE_MISC_IMR));
799 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
800 I915_READ(GEN8_DE_MISC_IIR));
801 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
802 I915_READ(GEN8_DE_MISC_IER));
803
804 seq_printf(m, "PCU interrupt mask:\t%08x\n",
805 I915_READ(GEN8_PCU_IMR));
806 seq_printf(m, "PCU interrupt identity:\t%08x\n",
807 I915_READ(GEN8_PCU_IIR));
808 seq_printf(m, "PCU interrupt enable:\t%08x\n",
809 I915_READ(GEN8_PCU_IER));
810 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 811 seq_printf(m, "Display IER:\t%08x\n",
812 I915_READ(VLV_IER));
813 seq_printf(m, "Display IIR:\t%08x\n",
814 I915_READ(VLV_IIR));
815 seq_printf(m, "Display IIR_RW:\t%08x\n",
816 I915_READ(VLV_IIR_RW));
817 seq_printf(m, "Display IMR:\t%08x\n",
818 I915_READ(VLV_IMR));
055e393f 819 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 820 seq_printf(m, "Pipe %c stat:\t%08x\n",
821 pipe_name(pipe),
822 I915_READ(PIPESTAT(pipe)));
823
824 seq_printf(m, "Master IER:\t%08x\n",
825 I915_READ(VLV_MASTER_IER));
826
827 seq_printf(m, "Render IER:\t%08x\n",
828 I915_READ(GTIER));
829 seq_printf(m, "Render IIR:\t%08x\n",
830 I915_READ(GTIIR));
831 seq_printf(m, "Render IMR:\t%08x\n",
832 I915_READ(GTIMR));
833
834 seq_printf(m, "PM IER:\t\t%08x\n",
835 I915_READ(GEN6_PMIER));
836 seq_printf(m, "PM IIR:\t\t%08x\n",
837 I915_READ(GEN6_PMIIR));
838 seq_printf(m, "PM IMR:\t\t%08x\n",
839 I915_READ(GEN6_PMIMR));
840
841 seq_printf(m, "Port hotplug:\t%08x\n",
842 I915_READ(PORT_HOTPLUG_EN));
843 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
844 I915_READ(VLV_DPFLIPSTAT));
845 seq_printf(m, "DPINVGTT:\t%08x\n",
846 I915_READ(DPINVGTT));
847
848 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 849 seq_printf(m, "Interrupt enable: %08x\n",
850 I915_READ(IER));
851 seq_printf(m, "Interrupt identity: %08x\n",
852 I915_READ(IIR));
853 seq_printf(m, "Interrupt mask: %08x\n",
854 I915_READ(IMR));
055e393f 855 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 856 seq_printf(m, "Pipe %c stat: %08x\n",
857 pipe_name(pipe),
858 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 859 } else {
860 seq_printf(m, "North Display Interrupt enable: %08x\n",
861 I915_READ(DEIER));
862 seq_printf(m, "North Display Interrupt identity: %08x\n",
863 I915_READ(DEIIR));
864 seq_printf(m, "North Display Interrupt mask: %08x\n",
865 I915_READ(DEIMR));
866 seq_printf(m, "South Display Interrupt enable: %08x\n",
867 I915_READ(SDEIER));
868 seq_printf(m, "South Display Interrupt identity: %08x\n",
869 I915_READ(SDEIIR));
870 seq_printf(m, "South Display Interrupt mask: %08x\n",
871 I915_READ(SDEIMR));
872 seq_printf(m, "Graphics Interrupt enable: %08x\n",
873 I915_READ(GTIER));
874 seq_printf(m, "Graphics Interrupt identity: %08x\n",
875 I915_READ(GTIIR));
876 seq_printf(m, "Graphics Interrupt mask: %08x\n",
877 I915_READ(GTIMR));
878 }
a2c7f6fd 879 for_each_ring(ring, dev_priv, i) {
a123f157 880 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 881 seq_printf(m,
882 "Graphics Interrupt mask (%s): %08x\n",
883 ring->name, I915_READ_IMR(ring));
9862e600 884 }
a2c7f6fd 885 i915_ring_seqno_info(m, ring);
9862e600 886 }
c8c8fb33 887 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 888 mutex_unlock(&dev->struct_mutex);
889
2017263e
BG		 890 return 0;
891}
892
a6172a80
CW		 893static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
894{
9f25d007 895 struct drm_info_node *node = m->private;
a6172a80 896 struct drm_device *dev = node->minor->dev;
e277a1f8 897 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 898 int i, ret;
899
900 ret = mutex_lock_interruptible(&dev->struct_mutex);
901 if (ret)
902 return ret;
a6172a80
CW		 903
904 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
905 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
906 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 907 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 908
6c085a72
CW		 909 seq_printf(m, "Fence %d, pin count = %d, object = ",
910 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 911 if (obj == NULL)
267f0c90 912 seq_puts(m, "unused");
c2c347a9 913 else
05394f39 914 describe_obj(m, obj);
267f0c90 915 seq_putc(m, '\n');
a6172a80
CW		 916 }
917
05394f39 918 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 919 return 0;
920}
921
2017263e
BG		 922static int i915_hws_info(struct seq_file *m, void *data)
923{
9f25d007 924 struct drm_info_node *node = m->private;
2017263e 925 struct drm_device *dev = node->minor->dev;
e277a1f8 926 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 927 struct intel_engine_cs *ring;
1a240d4d 928 const u32 *hws;
4066c0ae
CW		 929 int i;
930
1ec14ad3 931 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 932 hws = ring->status_page.page_addr;
2017263e
BG		 933 if (hws == NULL)
934 return 0;
935
936 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
937 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
938 i * 4,
939 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
940 }
941 return 0;
942}
943
d5442303
DV		 944static ssize_t
945i915_error_state_write(struct file *filp,
946 const char __user *ubuf,
947 size_t cnt,
948 loff_t *ppos)
949{
edc3d884 950 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 951 struct drm_device *dev = error_priv->dev;
22bcfc6a 952 int ret;
d5442303
DV		 953
954 DRM_DEBUG_DRIVER("Resetting error state\n");
955
22bcfc6a
DV		 956 ret = mutex_lock_interruptible(&dev->struct_mutex);
957 if (ret)
958 return ret;
959
d5442303
DV		 960 i915_destroy_error_state(dev);
961 mutex_unlock(&dev->struct_mutex);
962
963 return cnt;
964}
965
966static int i915_error_state_open(struct inode *inode, struct file *file)
967{
968 struct drm_device *dev = inode->i_private;
d5442303 969 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 970
971 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
972 if (!error_priv)
973 return -ENOMEM;
974
975 error_priv->dev = dev;
976
95d5bfb3 977 i915_error_state_get(dev, error_priv);
d5442303 978
edc3d884
MK		 979 file->private_data = error_priv;
980
981 return 0;
d5442303
DV		 982}
983
984static int i915_error_state_release(struct inode *inode, struct file *file)
985{
edc3d884 986 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 987
95d5bfb3 988 i915_error_state_put(error_priv);
d5442303
DV		 989 kfree(error_priv);
990
edc3d884
MK		 991 return 0;
992}
993
4dc955f7
MK		 994static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
995 size_t count, loff_t *pos)
996{
997 struct i915_error_state_file_priv *error_priv = file->private_data;
998 struct drm_i915_error_state_buf error_str;
999 loff_t tmp_pos = 0;
1000 ssize_t ret_count = 0;
1001 int ret;
1002
0a4cd7c8 1003 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1004 if (ret)
1005 return ret;
edc3d884 1006
fc16b48b 1007 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1008 if (ret)
1009 goto out;
1010
edc3d884
MK		 1011 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1012 error_str.buf,
1013 error_str.bytes);
1014
1015 if (ret_count < 0)
1016 ret = ret_count;
1017 else
1018 *pos = error_str.start + ret_count;
1019out:
4dc955f7 1020 i915_error_state_buf_release(&error_str);
edc3d884 1021 return ret ?: ret_count;
d5442303
DV		 1022}
1023
1024static const struct file_operations i915_error_state_fops = {
1025 .owner = THIS_MODULE,
1026 .open = i915_error_state_open,
edc3d884 1027 .read = i915_error_state_read,
d5442303
DV		 1028 .write = i915_error_state_write,
1029 .llseek = default_llseek,
1030 .release = i915_error_state_release,
1031};
1032
647416f9
KC		 1033static int
1034i915_next_seqno_get(void *data, u64 *val)
40633219 1035{
647416f9 1036 struct drm_device *dev = data;
e277a1f8 1037 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1038 int ret;
1039
1040 ret = mutex_lock_interruptible(&dev->struct_mutex);
1041 if (ret)
1042 return ret;
1043
647416f9 1044 *val = dev_priv->next_seqno;
40633219
MK		 1045 mutex_unlock(&dev->struct_mutex);
1046
647416f9 1047 return 0;
40633219
MK		 1048}
1049
647416f9
KC		 1050static int
1051i915_next_seqno_set(void *data, u64 val)
1052{
1053 struct drm_device *dev = data;
40633219
MK		 1054 int ret;
1055
40633219
MK		 1056 ret = mutex_lock_interruptible(&dev->struct_mutex);
1057 if (ret)
1058 return ret;
1059
e94fbaa8 1060 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1061 mutex_unlock(&dev->struct_mutex);
1062
647416f9 1063 return ret;
40633219
MK		 1064}
1065
647416f9
KC		 1066DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1067 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1068 "0x%llx\n");
40633219 1069
adb4bd12 1070static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1071{
9f25d007 1072 struct drm_info_node *node = m->private;
f97108d1 1073 struct drm_device *dev = node->minor->dev;
e277a1f8 1074 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1075 int ret = 0;
1076
1077 intel_runtime_pm_get(dev_priv);
3b8d8d91 1078
5c9669ce
TR		 1079 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1080
3b8d8d91
JB		 1081 if (IS_GEN5(dev)) {
1082 u16 rgvswctl = I915_READ16(MEMSWCTL);
1083 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1084
1085 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1086 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1087 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1088 MEMSTAT_VID_SHIFT);
1089 seq_printf(m, "Current P-state: %d\n",
1090 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1091 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1092 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1093 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1094 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1095 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1096 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1097 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1098 u32 rpupei, rpcurup, rpprevup;
1099 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1100 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1101 int max_freq;
1102
1103 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1104 ret = mutex_lock_interruptible(&dev->struct_mutex);
1105 if (ret)
c8c8fb33 1106 goto out;
d1ebd816 1107
c8d9a590 1108 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1109
8e8c06cd
CW		 1110 reqf = I915_READ(GEN6_RPNSWREQ);
1111 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1112 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1113 reqf >>= 24;
1114 else
1115 reqf >>= 25;
1116 reqf *= GT_FREQUENCY_MULTIPLIER;
1117
0d8f9491
CW		 1118 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1120 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1121
ccab5c82
JB		 1122 rpstat = I915_READ(GEN6_RPSTAT1);
1123 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1124 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1125 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1126 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1127 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1128 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1129 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1130 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131 else
1132 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1133 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1134
c8d9a590 1135 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1136 mutex_unlock(&dev->struct_mutex);
1137
9dd3c605
PZ		 1138 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1139 pm_ier = I915_READ(GEN6_PMIER);
1140 pm_imr = I915_READ(GEN6_PMIMR);
1141 pm_isr = I915_READ(GEN6_PMISR);
1142 pm_iir = I915_READ(GEN6_PMIIR);
1143 pm_mask = I915_READ(GEN6_PMINTRMSK);
1144 } else {
1145 pm_ier = I915_READ(GEN8_GT_IER(2));
1146 pm_imr = I915_READ(GEN8_GT_IMR(2));
1147 pm_isr = I915_READ(GEN8_GT_ISR(2));
1148 pm_iir = I915_READ(GEN8_GT_IIR(2));
1149 pm_mask = I915_READ(GEN6_PMINTRMSK);
1150 }
0d8f9491 1151 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1152 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1153 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1154 seq_printf(m, "Render p-state ratio: %d\n",
1155 (gt_perf_status & 0xff00) >> 8);
1156 seq_printf(m, "Render p-state VID: %d\n",
1157 gt_perf_status & 0xff);
1158 seq_printf(m, "Render p-state limit: %d\n",
1159 rp_state_limits & 0xff);
0d8f9491
CW		 1160 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1161 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1162 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1163 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1164 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1165 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1166 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1167 GEN6_CURICONT_MASK);
1168 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1169 GEN6_CURBSYTAVG_MASK);
1170 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1171 GEN6_CURBSYTAVG_MASK);
1172 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1173 GEN6_CURIAVG_MASK);
1174 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1175 GEN6_CURBSYTAVG_MASK);
1176 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1177 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1178
1179 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1181 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1182
1183 max_freq = (rp_state_cap & 0xff00) >> 8;
1184 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1185 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1186
1187 max_freq = rp_state_cap & 0xff;
1188 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1189 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1190
1191 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1192 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84 1193 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1194 u32 freq_sts;
0a073b84 1195
259bd5d4 1196 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1197 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1198 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1199 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200
0a073b84 1201 seq_printf(m, "max GPU freq: %d MHz\n",
b2435c94 1202 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1203
0a073b84 1204 seq_printf(m, "min GPU freq: %d MHz\n",
b2435c94 1205 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045
VS		 1206
1207 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
b2435c94 1208 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1209
1210 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1211 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1212 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1213 } else {
267f0c90 1214 seq_puts(m, "no P-state info available\n");
3b8d8d91 1215 }
f97108d1 1216
c8c8fb33
PZ		 1217out:
1218 intel_runtime_pm_put(dev_priv);
1219 return ret;
f97108d1
JB		 1220}
1221
4d85529d 1222static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1223{
9f25d007 1224 struct drm_info_node *node = m->private;
f97108d1 1225 struct drm_device *dev = node->minor->dev;
e277a1f8 1226 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1227 u32 rgvmodectl, rstdbyctl;
1228 u16 crstandvid;
1229 int ret;
1230
1231 ret = mutex_lock_interruptible(&dev->struct_mutex);
1232 if (ret)
1233 return ret;
c8c8fb33 1234 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1235
1236 rgvmodectl = I915_READ(MEMMODECTL);
1237 rstdbyctl = I915_READ(RSTDBYCTL);
1238 crstandvid = I915_READ16(CRSTANDVID);
1239
c8c8fb33 1240 intel_runtime_pm_put(dev_priv);
616fdb5a 1241 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1242
1243 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1244 "yes" : "no");
1245 seq_printf(m, "Boost freq: %d\n",
1246 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1247 MEMMODE_BOOST_FREQ_SHIFT);
1248 seq_printf(m, "HW control enabled: %s\n",
1249 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1250 seq_printf(m, "SW control enabled: %s\n",
1251 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1252 seq_printf(m, "Gated voltage change: %s\n",
1253 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1254 seq_printf(m, "Starting frequency: P%d\n",
1255 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1256 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1257 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1258 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1259 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1260 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1261 seq_printf(m, "Render standby enabled: %s\n",
1262 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1263 seq_puts(m, "Current RS state: ");
88271da3
JB		 1264 switch (rstdbyctl & RSX_STATUS_MASK) {
1265 case RSX_STATUS_ON:
267f0c90 1266 seq_puts(m, "on\n");
88271da3
JB		 1267 break;
1268 case RSX_STATUS_RC1:
267f0c90 1269 seq_puts(m, "RC1\n");
88271da3
JB		 1270 break;
1271 case RSX_STATUS_RC1E:
267f0c90 1272 seq_puts(m, "RC1E\n");
88271da3
JB		 1273 break;
1274 case RSX_STATUS_RS1:
267f0c90 1275 seq_puts(m, "RS1\n");
88271da3
JB		 1276 break;
1277 case RSX_STATUS_RS2:
267f0c90 1278 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1279 break;
1280 case RSX_STATUS_RS3:
267f0c90 1281 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1282 break;
1283 default:
267f0c90 1284 seq_puts(m, "unknown\n");
88271da3
JB		 1285 break;
1286 }
f97108d1
JB		 1287
1288 return 0;
1289}
1290
b2cff0db 1291static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
669ab5aa 1292{
b2cff0db
CW		 1293 struct drm_info_node *node = m->private;
1294 struct drm_device *dev = node->minor->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1297 int i;
1298
1299 spin_lock_irq(&dev_priv->uncore.lock);
1300 for_each_fw_domain(fw_domain, dev_priv, i) {
1301 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1302 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1303 fw_domain->wake_count);
1304 }
1305 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1306
b2cff0db
CW		 1307 return 0;
1308}
1309
1310static int vlv_drpc_info(struct seq_file *m)
1311{
9f25d007 1312 struct drm_info_node *node = m->private;
669ab5aa
D		 1313 struct drm_device *dev = node->minor->dev;
1314 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1315 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1316
d46c0517
ID		 1317 intel_runtime_pm_get(dev_priv);
1318
6b312cd3 1319 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1320 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1321 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1322
d46c0517
ID		 1323 intel_runtime_pm_put(dev_priv);
1324
669ab5aa
D		 1325 seq_printf(m, "Video Turbo Mode: %s\n",
1326 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1327 seq_printf(m, "Turbo enabled: %s\n",
1328 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1329 seq_printf(m, "HW control enabled: %s\n",
1330 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1331 seq_printf(m, "SW control enabled: %s\n",
1332 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1333 GEN6_RP_MEDIA_SW_MODE));
1334 seq_printf(m, "RC6 Enabled: %s\n",
1335 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1336 GEN6_RC_CTL_EI_MODE(1))));
1337 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1338 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1339 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1340 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1341
9cc19be5
ID		 1342 seq_printf(m, "Render RC6 residency since boot: %u\n",
1343 I915_READ(VLV_GT_RENDER_RC6));
1344 seq_printf(m, "Media RC6 residency since boot: %u\n",
1345 I915_READ(VLV_GT_MEDIA_RC6));
1346
b2cff0db 1347 return i915_gen6_forcewake_count_info(m, NULL);
669ab5aa
D		 1348}
1349
4d85529d
BW		 1350static int gen6_drpc_info(struct seq_file *m)
1351{
9f25d007 1352 struct drm_info_node *node = m->private;
4d85529d
BW		 1353 struct drm_device *dev = node->minor->dev;
1354 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1355 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1356 unsigned forcewake_count;
aee56cff 1357 int count = 0, ret;
4d85529d
BW		 1358
1359 ret = mutex_lock_interruptible(&dev->struct_mutex);
1360 if (ret)
1361 return ret;
c8c8fb33 1362 intel_runtime_pm_get(dev_priv);
4d85529d 1363
907b28c5 1364 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1365 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1366 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1367
1368 if (forcewake_count) {
267f0c90
DL		 1369 seq_puts(m, "RC information inaccurate because somebody "
1370 "holds a forcewake reference \n");
4d85529d
BW		 1371 } else {
1372 /* NB: we cannot use forcewake, else we read the wrong values */
1373 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1374 udelay(10);
1375 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1376 }
1377
1378 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1379 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1380
1381 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1382 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1383 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1384 mutex_lock(&dev_priv->rps.hw_lock);
1385 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1386 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1387
c8c8fb33
PZ		 1388 intel_runtime_pm_put(dev_priv);
1389
4d85529d
BW		 1390 seq_printf(m, "Video Turbo Mode: %s\n",
1391 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1392 seq_printf(m, "HW control enabled: %s\n",
1393 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1394 seq_printf(m, "SW control enabled: %s\n",
1395 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1396 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1397 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1398 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1399 seq_printf(m, "RC6 Enabled: %s\n",
1400 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1401 seq_printf(m, "Deep RC6 Enabled: %s\n",
1402 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1403 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1404 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1405 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1406 switch (gt_core_status & GEN6_RCn_MASK) {
1407 case GEN6_RC0:
1408 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1409 seq_puts(m, "Core Power Down\n");
4d85529d 1410 else
267f0c90 1411 seq_puts(m, "on\n");
4d85529d
BW		 1412 break;
1413 case GEN6_RC3:
267f0c90 1414 seq_puts(m, "RC3\n");
4d85529d
BW		 1415 break;
1416 case GEN6_RC6:
267f0c90 1417 seq_puts(m, "RC6\n");
4d85529d
BW		 1418 break;
1419 case GEN6_RC7:
267f0c90 1420 seq_puts(m, "RC7\n");
4d85529d
BW		 1421 break;
1422 default:
267f0c90 1423 seq_puts(m, "Unknown\n");
4d85529d
BW		 1424 break;
1425 }
1426
1427 seq_printf(m, "Core Power Down: %s\n",
1428 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1429
1430 /* Not exactly sure what this is */
1431 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1432 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1433 seq_printf(m, "RC6 residency since boot: %u\n",
1434 I915_READ(GEN6_GT_GFX_RC6));
1435 seq_printf(m, "RC6+ residency since boot: %u\n",
1436 I915_READ(GEN6_GT_GFX_RC6p));
1437 seq_printf(m, "RC6++ residency since boot: %u\n",
1438 I915_READ(GEN6_GT_GFX_RC6pp));
1439
ecd8faea
BW		 1440 seq_printf(m, "RC6 voltage: %dmV\n",
1441 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1442 seq_printf(m, "RC6+ voltage: %dmV\n",
1443 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1444 seq_printf(m, "RC6++ voltage: %dmV\n",
1445 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1446 return 0;
1447}
1448
1449static int i915_drpc_info(struct seq_file *m, void *unused)
1450{
9f25d007 1451 struct drm_info_node *node = m->private;
4d85529d
BW		 1452 struct drm_device *dev = node->minor->dev;
1453
669ab5aa
D		 1454 if (IS_VALLEYVIEW(dev))
1455 return vlv_drpc_info(m);
ac66cf4b 1456 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1457 return gen6_drpc_info(m);
1458 else
1459 return ironlake_drpc_info(m);
1460}
1461
b5e50c3f
JB		 1462static int i915_fbc_status(struct seq_file *m, void *unused)
1463{
9f25d007 1464 struct drm_info_node *node = m->private;
b5e50c3f 1465 struct drm_device *dev = node->minor->dev;
e277a1f8 1466 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1467
3a77c4c4 1468 if (!HAS_FBC(dev)) {
267f0c90 1469 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1470 return 0;
1471 }
1472
36623ef8
PZ		 1473 intel_runtime_pm_get(dev_priv);
1474
ee5382ae 1475 if (intel_fbc_enabled(dev)) {
267f0c90 1476 seq_puts(m, "FBC enabled\n");
b5e50c3f 1477 } else {
267f0c90 1478 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1479 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1480 case FBC_OK:
1481 seq_puts(m, "FBC actived, but currently disabled in hardware");
1482 break;
1483 case FBC_UNSUPPORTED:
1484 seq_puts(m, "unsupported by this chipset");
1485 break;
bed4a673 1486 case FBC_NO_OUTPUT:
267f0c90 1487 seq_puts(m, "no outputs");
bed4a673 1488 break;
b5e50c3f 1489 case FBC_STOLEN_TOO_SMALL:
267f0c90 1490 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1491 break;
1492 case FBC_UNSUPPORTED_MODE:
267f0c90 1493 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1494 break;
1495 case FBC_MODE_TOO_LARGE:
267f0c90 1496 seq_puts(m, "mode too large");
b5e50c3f
JB		 1497 break;
1498 case FBC_BAD_PLANE:
267f0c90 1499 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1500 break;
1501 case FBC_NOT_TILED:
267f0c90 1502 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1503 break;
9c928d16 1504 case FBC_MULTIPLE_PIPES:
267f0c90 1505 seq_puts(m, "multiple pipes are enabled");
9c928d16 1506 break;
c1a9f047 1507 case FBC_MODULE_PARAM:
267f0c90 1508 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1509 break;
8a5729a3 1510 case FBC_CHIP_DEFAULT:
267f0c90 1511 seq_puts(m, "disabled per chip default");
8a5729a3 1512 break;
b5e50c3f 1513 default:
267f0c90 1514 seq_puts(m, "unknown reason");
b5e50c3f 1515 }
267f0c90 1516 seq_putc(m, '\n');
b5e50c3f 1517 }
36623ef8
PZ		 1518
1519 intel_runtime_pm_put(dev_priv);
1520
b5e50c3f
JB		 1521 return 0;
1522}
1523
da46f936
RV		 1524static int i915_fbc_fc_get(void *data, u64 *val)
1525{
1526 struct drm_device *dev = data;
1527 struct drm_i915_private *dev_priv = dev->dev_private;
1528
1529 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1530 return -ENODEV;
1531
1532 drm_modeset_lock_all(dev);
1533 *val = dev_priv->fbc.false_color;
1534 drm_modeset_unlock_all(dev);
1535
1536 return 0;
1537}
1538
1539static int i915_fbc_fc_set(void *data, u64 val)
1540{
1541 struct drm_device *dev = data;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 u32 reg;
1544
1545 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1546 return -ENODEV;
1547
1548 drm_modeset_lock_all(dev);
1549
1550 reg = I915_READ(ILK_DPFC_CONTROL);
1551 dev_priv->fbc.false_color = val;
1552
1553 I915_WRITE(ILK_DPFC_CONTROL, val ?
1554 (reg | FBC_CTL_FALSE_COLOR) :
1555 (reg & ~FBC_CTL_FALSE_COLOR));
1556
1557 drm_modeset_unlock_all(dev);
1558 return 0;
1559}
1560
1561DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1562 i915_fbc_fc_get, i915_fbc_fc_set,
1563 "%llu\n");
1564
92d44621
PZ		 1565static int i915_ips_status(struct seq_file *m, void *unused)
1566{
9f25d007 1567 struct drm_info_node *node = m->private;
92d44621
PZ		 1568 struct drm_device *dev = node->minor->dev;
1569 struct drm_i915_private *dev_priv = dev->dev_private;
1570
f5adf94e 1571 if (!HAS_IPS(dev)) {
92d44621
PZ		 1572 seq_puts(m, "not supported\n");
1573 return 0;
1574 }
1575
36623ef8
PZ		 1576 intel_runtime_pm_get(dev_priv);
1577
0eaa53f0
RV		 1578 seq_printf(m, "Enabled by kernel parameter: %s\n",
1579 yesno(i915.enable_ips));
1580
1581 if (INTEL_INFO(dev)->gen >= 8) {
1582 seq_puts(m, "Currently: unknown\n");
1583 } else {
1584 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1585 seq_puts(m, "Currently: enabled\n");
1586 else
1587 seq_puts(m, "Currently: disabled\n");
1588 }
92d44621 1589
36623ef8
PZ		 1590 intel_runtime_pm_put(dev_priv);
1591
92d44621
PZ		 1592 return 0;
1593}
1594
4a9bef37
JB		 1595static int i915_sr_status(struct seq_file *m, void *unused)
1596{
9f25d007 1597 struct drm_info_node *node = m->private;
4a9bef37 1598 struct drm_device *dev = node->minor->dev;
e277a1f8 1599 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1600 bool sr_enabled = false;
1601
36623ef8
PZ		 1602 intel_runtime_pm_get(dev_priv);
1603
1398261a 1604 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1605 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1606 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1607 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1608 else if (IS_I915GM(dev))
1609 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1610 else if (IS_PINEVIEW(dev))
1611 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1612
36623ef8
PZ		 1613 intel_runtime_pm_put(dev_priv);
1614
5ba2aaaa
CW		 1615 seq_printf(m, "self-refresh: %s\n",
1616 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1617
1618 return 0;
1619}
1620
7648fa99
JB		 1621static int i915_emon_status(struct seq_file *m, void *unused)
1622{
9f25d007 1623 struct drm_info_node *node = m->private;
7648fa99 1624 struct drm_device *dev = node->minor->dev;
e277a1f8 1625 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1626 unsigned long temp, chipset, gfx;
de227ef0
CW		 1627 int ret;
1628
582be6b4
CW		 1629 if (!IS_GEN5(dev))
1630 return -ENODEV;
1631
de227ef0
CW		 1632 ret = mutex_lock_interruptible(&dev->struct_mutex);
1633 if (ret)
1634 return ret;
7648fa99
JB		 1635
1636 temp = i915_mch_val(dev_priv);
1637 chipset = i915_chipset_val(dev_priv);
1638 gfx = i915_gfx_val(dev_priv);
de227ef0 1639 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1640
1641 seq_printf(m, "GMCH temp: %ld\n", temp);
1642 seq_printf(m, "Chipset power: %ld\n", chipset);
1643 seq_printf(m, "GFX power: %ld\n", gfx);
1644 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1645
1646 return 0;
1647}
1648
23b2f8bb
JB		 1649static int i915_ring_freq_table(struct seq_file *m, void *unused)
1650{
9f25d007 1651 struct drm_info_node *node = m->private;
23b2f8bb 1652 struct drm_device *dev = node->minor->dev;
e277a1f8 1653 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1654 int ret = 0;
23b2f8bb
JB		 1655 int gpu_freq, ia_freq;
1656
1c70c0ce 1657 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1658 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1659 return 0;
1660 }
1661
5bfa0199
PZ		 1662 intel_runtime_pm_get(dev_priv);
1663
5c9669ce
TR		 1664 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1665
4fc688ce 1666 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1667 if (ret)
5bfa0199 1668 goto out;
23b2f8bb 1669
267f0c90 1670 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1671
b39fb297
BW		 1672 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1673 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1674 gpu_freq++) {
42c0526c
BW		 1675 ia_freq = gpu_freq;
1676 sandybridge_pcode_read(dev_priv,
1677 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1678 &ia_freq);
3ebecd07
CW		 1679 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1680 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1681 ((ia_freq >> 0) & 0xff) * 100,
1682 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1683 }
1684
4fc688ce 1685 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1686
5bfa0199
PZ		 1687out:
1688 intel_runtime_pm_put(dev_priv);
1689 return ret;
23b2f8bb
JB		 1690}
1691
44834a67
CW		 1692static int i915_opregion(struct seq_file *m, void *unused)
1693{
9f25d007 1694 struct drm_info_node *node = m->private;
44834a67 1695 struct drm_device *dev = node->minor->dev;
e277a1f8 1696 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1697 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1698 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1699 int ret;
1700
0d38f009
DV		 1701 if (data == NULL)
1702 return -ENOMEM;
1703
44834a67
CW		 1704 ret = mutex_lock_interruptible(&dev->struct_mutex);
1705 if (ret)
0d38f009 1706 goto out;
44834a67 1707
0d38f009
DV		 1708 if (opregion->header) {
1709 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1710 seq_write(m, data, OPREGION_SIZE);
1711 }
44834a67
CW		 1712
1713 mutex_unlock(&dev->struct_mutex);
1714
0d38f009
DV		 1715out:
1716 kfree(data);
44834a67
CW		 1717 return 0;
1718}
1719
37811fcc
CW		 1720static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1721{
9f25d007 1722 struct drm_info_node *node = m->private;
37811fcc 1723 struct drm_device *dev = node->minor->dev;
4520f53a 1724 struct intel_fbdev *ifbdev = NULL;
37811fcc 1725 struct intel_framebuffer *fb;
37811fcc 1726
4520f53a
DV		 1727#ifdef CONFIG_DRM_I915_FBDEV
1728 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1729
1730 ifbdev = dev_priv->fbdev;
1731 fb = to_intel_framebuffer(ifbdev->helper.fb);
1732
623f9783 1733 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1734 fb->base.width,
1735 fb->base.height,
1736 fb->base.depth,
623f9783
DV		 1737 fb->base.bits_per_pixel,
1738 atomic_read(&fb->base.refcount.refcount));
05394f39 1739 describe_obj(m, fb->obj);
267f0c90 1740 seq_putc(m, '\n');
4520f53a 1741#endif
37811fcc 1742
4b096ac1 1743 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1744 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1745 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1746 continue;
1747
623f9783 1748 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1749 fb->base.width,
1750 fb->base.height,
1751 fb->base.depth,
623f9783
DV		 1752 fb->base.bits_per_pixel,
1753 atomic_read(&fb->base.refcount.refcount));
05394f39 1754 describe_obj(m, fb->obj);
267f0c90 1755 seq_putc(m, '\n');
37811fcc 1756 }
4b096ac1 1757 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1758
1759 return 0;
1760}
1761
c9fe99bd
OM		 1762static void describe_ctx_ringbuf(struct seq_file *m,
1763 struct intel_ringbuffer *ringbuf)
1764{
1765 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1766 ringbuf->space, ringbuf->head, ringbuf->tail,
1767 ringbuf->last_retired_head);
1768}
1769
e76d3630
BW		 1770static int i915_context_status(struct seq_file *m, void *unused)
1771{
9f25d007 1772 struct drm_info_node *node = m->private;
e76d3630 1773 struct drm_device *dev = node->minor->dev;
e277a1f8 1774 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1775 struct intel_engine_cs *ring;
273497e5 1776 struct intel_context *ctx;
a168c293 1777 int ret, i;
e76d3630 1778
f3d28878 1779 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1780 if (ret)
1781 return ret;
1782
3e373948 1783 if (dev_priv->ips.pwrctx) {
267f0c90 1784 seq_puts(m, "power context ");
3e373948 1785 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1786 seq_putc(m, '\n');
dc501fbc 1787 }
e76d3630 1788
3e373948 1789 if (dev_priv->ips.renderctx) {
267f0c90 1790 seq_puts(m, "render context ");
3e373948 1791 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1792 seq_putc(m, '\n');
dc501fbc 1793 }
e76d3630 1794
a33afea5 1795 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1796 if (!i915.enable_execlists &&
1797 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1798 continue;
1799
a33afea5 1800 seq_puts(m, "HW context ");
3ccfd19d 1801 describe_ctx(m, ctx);
c9fe99bd 1802 for_each_ring(ring, dev_priv, i) {
a33afea5 1803 if (ring->default_context == ctx)
c9fe99bd
OM		 1804 seq_printf(m, "(default context %s) ",
1805 ring->name);
1806 }
1807
1808 if (i915.enable_execlists) {
1809 seq_putc(m, '\n');
1810 for_each_ring(ring, dev_priv, i) {
1811 struct drm_i915_gem_object *ctx_obj =
1812 ctx->engine[i].state;
1813 struct intel_ringbuffer *ringbuf =
1814 ctx->engine[i].ringbuf;
1815
1816 seq_printf(m, "%s: ", ring->name);
1817 if (ctx_obj)
1818 describe_obj(m, ctx_obj);
1819 if (ringbuf)
1820 describe_ctx_ringbuf(m, ringbuf);
1821 seq_putc(m, '\n');
1822 }
1823 } else {
1824 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1825 }
a33afea5 1826
a33afea5 1827 seq_putc(m, '\n');
a168c293
BW		 1828 }
1829
f3d28878 1830 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1831
1832 return 0;
1833}
1834
064ca1d2
TD		 1835static void i915_dump_lrc_obj(struct seq_file *m,
1836 struct intel_engine_cs *ring,
1837 struct drm_i915_gem_object *ctx_obj)
1838{
1839 struct page *page;
1840 uint32_t *reg_state;
1841 int j;
1842 unsigned long ggtt_offset = 0;
1843
1844 if (ctx_obj == NULL) {
1845 seq_printf(m, "Context on %s with no gem object\n",
1846 ring->name);
1847 return;
1848 }
1849
1850 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1851 intel_execlists_ctx_id(ctx_obj));
1852
1853 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1854 seq_puts(m, "\tNot bound in GGTT\n");
1855 else
1856 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1857
1858 if (i915_gem_object_get_pages(ctx_obj)) {
1859 seq_puts(m, "\tFailed to get pages for context object\n");
1860 return;
1861 }
1862
1863 page = i915_gem_object_get_page(ctx_obj, 1);
1864 if (!WARN_ON(page == NULL)) {
1865 reg_state = kmap_atomic(page);
1866
1867 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1868 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1869 ggtt_offset + 4096 + (j * 4),
1870 reg_state[j], reg_state[j + 1],
1871 reg_state[j + 2], reg_state[j + 3]);
1872 }
1873 kunmap_atomic(reg_state);
1874 }
1875
1876 seq_putc(m, '\n');
1877}
1878
c0ab1ae9
BW		 1879static int i915_dump_lrc(struct seq_file *m, void *unused)
1880{
1881 struct drm_info_node *node = (struct drm_info_node *) m->private;
1882 struct drm_device *dev = node->minor->dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_engine_cs *ring;
1885 struct intel_context *ctx;
1886 int ret, i;
1887
1888 if (!i915.enable_execlists) {
1889 seq_printf(m, "Logical Ring Contexts are disabled\n");
1890 return 0;
1891 }
1892
1893 ret = mutex_lock_interruptible(&dev->struct_mutex);
1894 if (ret)
1895 return ret;
1896
1897 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1898 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1899 if (ring->default_context != ctx)
1900 i915_dump_lrc_obj(m, ring,
1901 ctx->engine[i].state);
c0ab1ae9
BW		 1902 }
1903 }
1904
1905 mutex_unlock(&dev->struct_mutex);
1906
1907 return 0;
1908}
1909
4ba70e44
OM		 1910static int i915_execlists(struct seq_file *m, void *data)
1911{
1912 struct drm_info_node *node = (struct drm_info_node *)m->private;
1913 struct drm_device *dev = node->minor->dev;
1914 struct drm_i915_private *dev_priv = dev->dev_private;
1915 struct intel_engine_cs *ring;
1916 u32 status_pointer;
1917 u8 read_pointer;
1918 u8 write_pointer;
1919 u32 status;
1920 u32 ctx_id;
1921 struct list_head *cursor;
1922 int ring_id, i;
1923 int ret;
1924
1925 if (!i915.enable_execlists) {
1926 seq_puts(m, "Logical Ring Contexts are disabled\n");
1927 return 0;
1928 }
1929
1930 ret = mutex_lock_interruptible(&dev->struct_mutex);
1931 if (ret)
1932 return ret;
1933
fc0412ec
MT		 1934 intel_runtime_pm_get(dev_priv);
1935
4ba70e44 1936 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 1937 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 1938 int count = 0;
1939 unsigned long flags;
1940
1941 seq_printf(m, "%s\n", ring->name);
1942
1943 status = I915_READ(RING_EXECLIST_STATUS(ring));
1944 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1945 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1946 status, ctx_id);
1947
1948 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1949 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1950
1951 read_pointer = ring->next_context_status_buffer;
1952 write_pointer = status_pointer & 0x07;
1953 if (read_pointer > write_pointer)
1954 write_pointer += 6;
1955 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1956 read_pointer, write_pointer);
1957
1958 for (i = 0; i < 6; i++) {
1959 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1960 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1961
1962 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1963 i, status, ctx_id);
1964 }
1965
1966 spin_lock_irqsave(&ring->execlist_lock, flags);
1967 list_for_each(cursor, &ring->execlist_queue)
1968 count++;
1969 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 1970 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 1971 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1972
1973 seq_printf(m, "\t%d requests in queue\n", count);
1974 if (head_req) {
1975 struct drm_i915_gem_object *ctx_obj;
1976
6d3d8274 1977 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 1978 seq_printf(m, "\tHead request id: %u\n",
1979 intel_execlists_ctx_id(ctx_obj));
1980 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 1981 head_req->tail);
4ba70e44
OM		 1982 }
1983
1984 seq_putc(m, '\n');
1985 }
1986
fc0412ec 1987 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 1988 mutex_unlock(&dev->struct_mutex);
1989
1990 return 0;
1991}
1992
ea16a3cd
DV		 1993static const char *swizzle_string(unsigned swizzle)
1994{
aee56cff 1995 switch (swizzle) {
ea16a3cd
DV		 1996 case I915_BIT_6_SWIZZLE_NONE:
1997 return "none";
1998 case I915_BIT_6_SWIZZLE_9:
1999 return "bit9";
2000 case I915_BIT_6_SWIZZLE_9_10:
2001 return "bit9/bit10";
2002 case I915_BIT_6_SWIZZLE_9_11:
2003 return "bit9/bit11";
2004 case I915_BIT_6_SWIZZLE_9_10_11:
2005 return "bit9/bit10/bit11";
2006 case I915_BIT_6_SWIZZLE_9_17:
2007 return "bit9/bit17";
2008 case I915_BIT_6_SWIZZLE_9_10_17:
2009 return "bit9/bit10/bit17";
2010 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2011 return "unknown";
ea16a3cd
DV		 2012 }
2013
2014 return "bug";
2015}
2016
2017static int i915_swizzle_info(struct seq_file *m, void *data)
2018{
9f25d007 2019 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2020 struct drm_device *dev = node->minor->dev;
2021 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2022 int ret;
2023
2024 ret = mutex_lock_interruptible(&dev->struct_mutex);
2025 if (ret)
2026 return ret;
c8c8fb33 2027 intel_runtime_pm_get(dev_priv);
ea16a3cd 2028
ea16a3cd
DV		 2029 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2030 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2031 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2032 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2033
2034 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2035 seq_printf(m, "DDC = 0x%08x\n",
2036 I915_READ(DCC));
656bfa3a
DV		 2037 seq_printf(m, "DDC2 = 0x%08x\n",
2038 I915_READ(DCC2));
ea16a3cd
DV		 2039 seq_printf(m, "C0DRB3 = 0x%04x\n",
2040 I915_READ16(C0DRB3));
2041 seq_printf(m, "C1DRB3 = 0x%04x\n",
2042 I915_READ16(C1DRB3));
9d3203e1 2043 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2044 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2045 I915_READ(MAD_DIMM_C0));
2046 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2047 I915_READ(MAD_DIMM_C1));
2048 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2049 I915_READ(MAD_DIMM_C2));
2050 seq_printf(m, "TILECTL = 0x%08x\n",
2051 I915_READ(TILECTL));
5907f5fb 2052 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2053 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2054 I915_READ(GAMTARBMODE));
2055 else
2056 seq_printf(m, "ARB_MODE = 0x%08x\n",
2057 I915_READ(ARB_MODE));
3fa7d235
DV		 2058 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2059 I915_READ(DISP_ARB_CTL));
ea16a3cd 2060 }
656bfa3a
DV		 2061
2062 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2063 seq_puts(m, "L-shaped memory detected\n");
2064
c8c8fb33 2065 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2066 mutex_unlock(&dev->struct_mutex);
2067
2068 return 0;
2069}
2070
1c60fef5
BW		 2071static int per_file_ctx(int id, void *ptr, void *data)
2072{
273497e5 2073 struct intel_context *ctx = ptr;
1c60fef5 2074 struct seq_file *m = data;
ae6c4806
DV		 2075 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2076
2077 if (!ppgtt) {
2078 seq_printf(m, " no ppgtt for context %d\n",
2079 ctx->user_handle);
2080 return 0;
2081 }
1c60fef5 2082
f83d6518
OM		 2083 if (i915_gem_context_is_default(ctx))
2084 seq_puts(m, " default context:\n");
2085 else
821d66dd 2086 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2087 ppgtt->debug_dump(ppgtt, m);
2088
2089 return 0;
2090}
2091
77df6772 2092static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2093{
3cf17fc5 2094 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2095 struct intel_engine_cs *ring;
77df6772
BW		 2096 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2097 int unused, i;
3cf17fc5 2098
77df6772
BW		 2099 if (!ppgtt)
2100 return;
2101
2102 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2103 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2104 for_each_ring(ring, dev_priv, unused) {
2105 seq_printf(m, "%s\n", ring->name);
2106 for (i = 0; i < 4; i++) {
2107 u32 offset = 0x270 + i * 8;
2108 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2109 pdp <<= 32;
2110 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2111 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2112 }
2113 }
2114}
2115
2116static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2117{
2118 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2119 struct intel_engine_cs *ring;
1c60fef5 2120 struct drm_file *file;
77df6772 2121 int i;
3cf17fc5 2122
3cf17fc5
DV		 2123 if (INTEL_INFO(dev)->gen == 6)
2124 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2125
a2c7f6fd 2126 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2127 seq_printf(m, "%s\n", ring->name);
2128 if (INTEL_INFO(dev)->gen == 7)
2129 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2130 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2131 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2132 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2133 }
2134 if (dev_priv->mm.aliasing_ppgtt) {
2135 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2136
267f0c90 2137 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 2138 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 2139
87d60b63 2140 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2141 }
1c60fef5
BW		 2142
2143 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2144 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2145
1c60fef5
BW		 2146 seq_printf(m, "proc: %s\n",
2147 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2148 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2149 }
2150 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2151}
2152
2153static int i915_ppgtt_info(struct seq_file *m, void *data)
2154{
9f25d007 2155 struct drm_info_node *node = m->private;
77df6772 2156 struct drm_device *dev = node->minor->dev;
c8c8fb33 2157 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2158
2159 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2160 if (ret)
2161 return ret;
c8c8fb33 2162 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2163
2164 if (INTEL_INFO(dev)->gen >= 8)
2165 gen8_ppgtt_info(m, dev);
2166 else if (INTEL_INFO(dev)->gen >= 6)
2167 gen6_ppgtt_info(m, dev);
2168
c8c8fb33 2169 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2170 mutex_unlock(&dev->struct_mutex);
2171
2172 return 0;
2173}
2174
63573eb7
BW		 2175static int i915_llc(struct seq_file *m, void *data)
2176{
9f25d007 2177 struct drm_info_node *node = m->private;
63573eb7
BW		 2178 struct drm_device *dev = node->minor->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180
2181 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2182 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2183 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2184
2185 return 0;
2186}
2187
e91fd8c6
RV		 2188static int i915_edp_psr_status(struct seq_file *m, void *data)
2189{
2190 struct drm_info_node *node = m->private;
2191 struct drm_device *dev = node->minor->dev;
2192 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2193 u32 psrperf = 0;
a6cbdb8e
RV		 2194 u32 stat[3];
2195 enum pipe pipe;
a031d709 2196 bool enabled = false;
e91fd8c6 2197
c8c8fb33
PZ		 2198 intel_runtime_pm_get(dev_priv);
2199
fa128fa6 2200 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2201 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2202 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2203 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2204 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2205 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2206 dev_priv->psr.busy_frontbuffer_bits);
2207 seq_printf(m, "Re-enable work scheduled: %s\n",
2208 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2209
a6cbdb8e
RV		 2210 if (HAS_PSR(dev)) {
2211 if (HAS_DDI(dev))
2212 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2213 else {
2214 for_each_pipe(dev_priv, pipe) {
2215 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2216 VLV_EDP_PSR_CURR_STATE_MASK;
2217 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2218 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2219 enabled = true;
2220 }
2221 }
2222 }
2223 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2224
2225 if (!HAS_DDI(dev))
2226 for_each_pipe(dev_priv, pipe) {
2227 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2228 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2229 seq_printf(m, " pipe %c", pipe_name(pipe));
2230 }
2231 seq_puts(m, "\n");
e91fd8c6 2232
fb495814
RV		 2233 seq_printf(m, "Link standby: %s\n",
2234 yesno((bool)dev_priv->psr.link_standby));
2235
a6cbdb8e
RV		 2236 /* CHV PSR has no kind of performance counter */
2237 if (HAS_PSR(dev) && HAS_DDI(dev)) {
a031d709
RV		 2238 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2239 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2240
2241 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2242 }
fa128fa6 2243 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2244
c8c8fb33 2245 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2246 return 0;
2247}
2248
d2e216d0
RV		 2249static int i915_sink_crc(struct seq_file *m, void *data)
2250{
2251 struct drm_info_node *node = m->private;
2252 struct drm_device *dev = node->minor->dev;
2253 struct intel_encoder *encoder;
2254 struct intel_connector *connector;
2255 struct intel_dp *intel_dp = NULL;
2256 int ret;
2257 u8 crc[6];
2258
2259 drm_modeset_lock_all(dev);
2260 list_for_each_entry(connector, &dev->mode_config.connector_list,
2261 base.head) {
2262
2263 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2264 continue;
2265
b6ae3c7c
PZ		 2266 if (!connector->base.encoder)
2267 continue;
2268
d2e216d0
RV		 2269 encoder = to_intel_encoder(connector->base.encoder);
2270 if (encoder->type != INTEL_OUTPUT_EDP)
2271 continue;
2272
2273 intel_dp = enc_to_intel_dp(&encoder->base);
2274
2275 ret = intel_dp_sink_crc(intel_dp, crc);
2276 if (ret)
2277 goto out;
2278
2279 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2280 crc[0], crc[1], crc[2],
2281 crc[3], crc[4], crc[5]);
2282 goto out;
2283 }
2284 ret = -ENODEV;
2285out:
2286 drm_modeset_unlock_all(dev);
2287 return ret;
2288}
2289
ec013e7f
JB		 2290static int i915_energy_uJ(struct seq_file *m, void *data)
2291{
2292 struct drm_info_node *node = m->private;
2293 struct drm_device *dev = node->minor->dev;
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 u64 power;
2296 u32 units;
2297
2298 if (INTEL_INFO(dev)->gen < 6)
2299 return -ENODEV;
2300
36623ef8
PZ		 2301 intel_runtime_pm_get(dev_priv);
2302
ec013e7f
JB		 2303 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2304 power = (power & 0x1f00) >> 8;
2305 units = 1000000 / (1 << power); /* convert to uJ */
2306 power = I915_READ(MCH_SECP_NRG_STTS);
2307 power *= units;
2308
36623ef8
PZ		 2309 intel_runtime_pm_put(dev_priv);
2310
ec013e7f 2311 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2312
2313 return 0;
2314}
2315
2316static int i915_pc8_status(struct seq_file *m, void *unused)
2317{
9f25d007 2318 struct drm_info_node *node = m->private;
371db66a
PZ		 2319 struct drm_device *dev = node->minor->dev;
2320 struct drm_i915_private *dev_priv = dev->dev_private;
2321
85b8d5c2 2322 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2323 seq_puts(m, "not supported\n");
2324 return 0;
2325 }
2326
86c4ec0d 2327 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2328 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2329 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2330
ec013e7f
JB		 2331 return 0;
2332}
2333
1da51581
ID		 2334static const char *power_domain_str(enum intel_display_power_domain domain)
2335{
2336 switch (domain) {
2337 case POWER_DOMAIN_PIPE_A:
2338 return "PIPE_A";
2339 case POWER_DOMAIN_PIPE_B:
2340 return "PIPE_B";
2341 case POWER_DOMAIN_PIPE_C:
2342 return "PIPE_C";
2343 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2344 return "PIPE_A_PANEL_FITTER";
2345 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2346 return "PIPE_B_PANEL_FITTER";
2347 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2348 return "PIPE_C_PANEL_FITTER";
2349 case POWER_DOMAIN_TRANSCODER_A:
2350 return "TRANSCODER_A";
2351 case POWER_DOMAIN_TRANSCODER_B:
2352 return "TRANSCODER_B";
2353 case POWER_DOMAIN_TRANSCODER_C:
2354 return "TRANSCODER_C";
2355 case POWER_DOMAIN_TRANSCODER_EDP:
2356 return "TRANSCODER_EDP";
319be8ae
ID		 2357 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2358 return "PORT_DDI_A_2_LANES";
2359 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2360 return "PORT_DDI_A_4_LANES";
2361 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2362 return "PORT_DDI_B_2_LANES";
2363 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2364 return "PORT_DDI_B_4_LANES";
2365 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2366 return "PORT_DDI_C_2_LANES";
2367 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2368 return "PORT_DDI_C_4_LANES";
2369 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2370 return "PORT_DDI_D_2_LANES";
2371 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2372 return "PORT_DDI_D_4_LANES";
2373 case POWER_DOMAIN_PORT_DSI:
2374 return "PORT_DSI";
2375 case POWER_DOMAIN_PORT_CRT:
2376 return "PORT_CRT";
2377 case POWER_DOMAIN_PORT_OTHER:
2378 return "PORT_OTHER";
1da51581
ID		 2379 case POWER_DOMAIN_VGA:
2380 return "VGA";
2381 case POWER_DOMAIN_AUDIO:
2382 return "AUDIO";
bd2bb1b9
PZ		 2383 case POWER_DOMAIN_PLLS:
2384 return "PLLS";
1da51581
ID		 2385 case POWER_DOMAIN_INIT:
2386 return "INIT";
2387 default:
5f77eeb0 2388 MISSING_CASE(domain);
1da51581
ID		 2389 return "?";
2390 }
2391}
2392
2393static int i915_power_domain_info(struct seq_file *m, void *unused)
2394{
9f25d007 2395 struct drm_info_node *node = m->private;
1da51581
ID		 2396 struct drm_device *dev = node->minor->dev;
2397 struct drm_i915_private *dev_priv = dev->dev_private;
2398 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2399 int i;
2400
2401 mutex_lock(&power_domains->lock);
2402
2403 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2404 for (i = 0; i < power_domains->power_well_count; i++) {
2405 struct i915_power_well *power_well;
2406 enum intel_display_power_domain power_domain;
2407
2408 power_well = &power_domains->power_wells[i];
2409 seq_printf(m, "%-25s %d\n", power_well->name,
2410 power_well->count);
2411
2412 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2413 power_domain++) {
2414 if (!(BIT(power_domain) & power_well->domains))
2415 continue;
2416
2417 seq_printf(m, " %-23s %d\n",
2418 power_domain_str(power_domain),
2419 power_domains->domain_use_count[power_domain]);
2420 }
2421 }
2422
2423 mutex_unlock(&power_domains->lock);
2424
2425 return 0;
2426}
2427
53f5e3ca
JB		 2428static void intel_seq_print_mode(struct seq_file *m, int tabs,
2429 struct drm_display_mode *mode)
2430{
2431 int i;
2432
2433 for (i = 0; i < tabs; i++)
2434 seq_putc(m, '\t');
2435
2436 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2437 mode->base.id, mode->name,
2438 mode->vrefresh, mode->clock,
2439 mode->hdisplay, mode->hsync_start,
2440 mode->hsync_end, mode->htotal,
2441 mode->vdisplay, mode->vsync_start,
2442 mode->vsync_end, mode->vtotal,
2443 mode->type, mode->flags);
2444}
2445
2446static void intel_encoder_info(struct seq_file *m,
2447 struct intel_crtc *intel_crtc,
2448 struct intel_encoder *intel_encoder)
2449{
9f25d007 2450 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2451 struct drm_device *dev = node->minor->dev;
2452 struct drm_crtc *crtc = &intel_crtc->base;
2453 struct intel_connector *intel_connector;
2454 struct drm_encoder *encoder;
2455
2456 encoder = &intel_encoder->base;
2457 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2458 encoder->base.id, encoder->name);
53f5e3ca
JB		 2459 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2460 struct drm_connector *connector = &intel_connector->base;
2461 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2462 connector->base.id,
c23cc417 2463 connector->name,
53f5e3ca
JB		 2464 drm_get_connector_status_name(connector->status));
2465 if (connector->status == connector_status_connected) {
2466 struct drm_display_mode *mode = &crtc->mode;
2467 seq_printf(m, ", mode:\n");
2468 intel_seq_print_mode(m, 2, mode);
2469 } else {
2470 seq_putc(m, '\n');
2471 }
2472 }
2473}
2474
2475static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2476{
9f25d007 2477 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2478 struct drm_device *dev = node->minor->dev;
2479 struct drm_crtc *crtc = &intel_crtc->base;
2480 struct intel_encoder *intel_encoder;
2481
5aa8a937
MR		 2482 if (crtc->primary->fb)
2483 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2484 crtc->primary->fb->base.id, crtc->x, crtc->y,
2485 crtc->primary->fb->width, crtc->primary->fb->height);
2486 else
2487 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2488 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2489 intel_encoder_info(m, intel_crtc, intel_encoder);
2490}
2491
2492static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2493{
2494 struct drm_display_mode *mode = panel->fixed_mode;
2495
2496 seq_printf(m, "\tfixed mode:\n");
2497 intel_seq_print_mode(m, 2, mode);
2498}
2499
2500static void intel_dp_info(struct seq_file *m,
2501 struct intel_connector *intel_connector)
2502{
2503 struct intel_encoder *intel_encoder = intel_connector->encoder;
2504 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2505
2506 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2507 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2508 "no");
2509 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2510 intel_panel_info(m, &intel_connector->panel);
2511}
2512
2513static void intel_hdmi_info(struct seq_file *m,
2514 struct intel_connector *intel_connector)
2515{
2516 struct intel_encoder *intel_encoder = intel_connector->encoder;
2517 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2518
2519 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2520 "no");
2521}
2522
2523static void intel_lvds_info(struct seq_file *m,
2524 struct intel_connector *intel_connector)
2525{
2526 intel_panel_info(m, &intel_connector->panel);
2527}
2528
2529static void intel_connector_info(struct seq_file *m,
2530 struct drm_connector *connector)
2531{
2532 struct intel_connector *intel_connector = to_intel_connector(connector);
2533 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2534 struct drm_display_mode *mode;
53f5e3ca
JB		 2535
2536 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2537 connector->base.id, connector->name,
53f5e3ca
JB		 2538 drm_get_connector_status_name(connector->status));
2539 if (connector->status == connector_status_connected) {
2540 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2541 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2542 connector->display_info.width_mm,
2543 connector->display_info.height_mm);
2544 seq_printf(m, "\tsubpixel order: %s\n",
2545 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2546 seq_printf(m, "\tCEA rev: %d\n",
2547 connector->display_info.cea_rev);
2548 }
36cd7444
DA		 2549 if (intel_encoder) {
2550 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2551 intel_encoder->type == INTEL_OUTPUT_EDP)
2552 intel_dp_info(m, intel_connector);
2553 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2554 intel_hdmi_info(m, intel_connector);
2555 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2556 intel_lvds_info(m, intel_connector);
2557 }
53f5e3ca 2558
f103fc7d
JB		 2559 seq_printf(m, "\tmodes:\n");
2560 list_for_each_entry(mode, &connector->modes, head)
2561 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2562}
2563
065f2ec2
CW		 2564static bool cursor_active(struct drm_device *dev, int pipe)
2565{
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 u32 state;
2568
2569 if (IS_845G(dev) || IS_I865G(dev))
2570 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2571 else
5efb3e28 2572 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2573
2574 return state;
2575}
2576
2577static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2578{
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 u32 pos;
2581
5efb3e28 2582 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2583
2584 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2585 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2586 *x = -*x;
2587
2588 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2589 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2590 *y = -*y;
2591
2592 return cursor_active(dev, pipe);
2593}
2594
53f5e3ca
JB		 2595static int i915_display_info(struct seq_file *m, void *unused)
2596{
9f25d007 2597 struct drm_info_node *node = m->private;
53f5e3ca 2598 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2599 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2600 struct intel_crtc *crtc;
53f5e3ca
JB		 2601 struct drm_connector *connector;
2602
b0e5ddf3 2603 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2604 drm_modeset_lock_all(dev);
2605 seq_printf(m, "CRTC info\n");
2606 seq_printf(m, "---------\n");
d3fcc808 2607 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2608 bool active;
2609 int x, y;
53f5e3ca 2610
57127efa 2611 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2612 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2613 yesno(crtc->active), crtc->config->pipe_src_w,
2614 crtc->config->pipe_src_h);
a23dc658 2615 if (crtc->active) {
065f2ec2
CW		 2616 intel_crtc_info(m, crtc);
2617
a23dc658 2618 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2619 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2620 yesno(crtc->cursor_base),
57127efa
CW		 2621 x, y, crtc->cursor_width, crtc->cursor_height,
2622 crtc->cursor_addr, yesno(active));
a23dc658 2623 }
cace841c
DV		 2624
2625 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2626 yesno(!crtc->cpu_fifo_underrun_disabled),
2627 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2628 }
2629
2630 seq_printf(m, "\n");
2631 seq_printf(m, "Connector info\n");
2632 seq_printf(m, "--------------\n");
2633 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2634 intel_connector_info(m, connector);
2635 }
2636 drm_modeset_unlock_all(dev);
b0e5ddf3 2637 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2638
2639 return 0;
2640}
2641
e04934cf
BW		 2642static int i915_semaphore_status(struct seq_file *m, void *unused)
2643{
2644 struct drm_info_node *node = (struct drm_info_node *) m->private;
2645 struct drm_device *dev = node->minor->dev;
2646 struct drm_i915_private *dev_priv = dev->dev_private;
2647 struct intel_engine_cs *ring;
2648 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2649 int i, j, ret;
2650
2651 if (!i915_semaphore_is_enabled(dev)) {
2652 seq_puts(m, "Semaphores are disabled\n");
2653 return 0;
2654 }
2655
2656 ret = mutex_lock_interruptible(&dev->struct_mutex);
2657 if (ret)
2658 return ret;
03872064 2659 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2660
2661 if (IS_BROADWELL(dev)) {
2662 struct page *page;
2663 uint64_t *seqno;
2664
2665 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2666
2667 seqno = (uint64_t *)kmap_atomic(page);
2668 for_each_ring(ring, dev_priv, i) {
2669 uint64_t offset;
2670
2671 seq_printf(m, "%s\n", ring->name);
2672
2673 seq_puts(m, " Last signal:");
2674 for (j = 0; j < num_rings; j++) {
2675 offset = i * I915_NUM_RINGS + j;
2676 seq_printf(m, "0x%08llx (0x%02llx) ",
2677 seqno[offset], offset * 8);
2678 }
2679 seq_putc(m, '\n');
2680
2681 seq_puts(m, " Last wait: ");
2682 for (j = 0; j < num_rings; j++) {
2683 offset = i + (j * I915_NUM_RINGS);
2684 seq_printf(m, "0x%08llx (0x%02llx) ",
2685 seqno[offset], offset * 8);
2686 }
2687 seq_putc(m, '\n');
2688
2689 }
2690 kunmap_atomic(seqno);
2691 } else {
2692 seq_puts(m, " Last signal:");
2693 for_each_ring(ring, dev_priv, i)
2694 for (j = 0; j < num_rings; j++)
2695 seq_printf(m, "0x%08x\n",
2696 I915_READ(ring->semaphore.mbox.signal[j]));
2697 seq_putc(m, '\n');
2698 }
2699
2700 seq_puts(m, "\nSync seqno:\n");
2701 for_each_ring(ring, dev_priv, i) {
2702 for (j = 0; j < num_rings; j++) {
2703 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2704 }
2705 seq_putc(m, '\n');
2706 }
2707 seq_putc(m, '\n');
2708
03872064 2709 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2710 mutex_unlock(&dev->struct_mutex);
2711 return 0;
2712}
2713
728e29d7
DV		 2714static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2715{
2716 struct drm_info_node *node = (struct drm_info_node *) m->private;
2717 struct drm_device *dev = node->minor->dev;
2718 struct drm_i915_private *dev_priv = dev->dev_private;
2719 int i;
2720
2721 drm_modeset_lock_all(dev);
2722 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2723 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2724
2725 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2726 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2727 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2728 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2729 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2730 seq_printf(m, " dpll_md: 0x%08x\n",
2731 pll->config.hw_state.dpll_md);
2732 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2733 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2734 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2735 }
2736 drm_modeset_unlock_all(dev);
2737
2738 return 0;
2739}
2740
1ed1ef9d 2741static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2742{
2743 int i;
2744 int ret;
2745 struct drm_info_node *node = (struct drm_info_node *) m->private;
2746 struct drm_device *dev = node->minor->dev;
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748
888b5995
AS		 2749 ret = mutex_lock_interruptible(&dev->struct_mutex);
2750 if (ret)
2751 return ret;
2752
2753 intel_runtime_pm_get(dev_priv);
2754
7225342a
MK		 2755 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2756 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2757 u32 addr, mask, value, read;
2758 bool ok;
888b5995 2759
7225342a
MK		 2760 addr = dev_priv->workarounds.reg[i].addr;
2761 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2762 value = dev_priv->workarounds.reg[i].value;
2763 read = I915_READ(addr);
2764 ok = (value & mask) == (read & mask);
2765 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2766 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2767 }
2768
2769 intel_runtime_pm_put(dev_priv);
2770 mutex_unlock(&dev->struct_mutex);
2771
2772 return 0;
2773}
2774
c5511e44
DL		 2775static int i915_ddb_info(struct seq_file *m, void *unused)
2776{
2777 struct drm_info_node *node = m->private;
2778 struct drm_device *dev = node->minor->dev;
2779 struct drm_i915_private *dev_priv = dev->dev_private;
2780 struct skl_ddb_allocation *ddb;
2781 struct skl_ddb_entry *entry;
2782 enum pipe pipe;
2783 int plane;
2784
2fcffe19
DL		 2785 if (INTEL_INFO(dev)->gen < 9)
2786 return 0;
2787
c5511e44
DL		 2788 drm_modeset_lock_all(dev);
2789
2790 ddb = &dev_priv->wm.skl_hw.ddb;
2791
2792 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2793
2794 for_each_pipe(dev_priv, pipe) {
2795 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2796
2797 for_each_plane(pipe, plane) {
2798 entry = &ddb->plane[pipe][plane];
2799 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2800 entry->start, entry->end,
2801 skl_ddb_entry_size(entry));
2802 }
2803
2804 entry = &ddb->cursor[pipe];
2805 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2806 entry->end, skl_ddb_entry_size(entry));
2807 }
2808
2809 drm_modeset_unlock_all(dev);
2810
2811 return 0;
2812}
2813
07144428
DL		 2814struct pipe_crc_info {
2815 const char *name;
2816 struct drm_device *dev;
2817 enum pipe pipe;
2818};
2819
11bed958
DA		 2820static int i915_dp_mst_info(struct seq_file *m, void *unused)
2821{
2822 struct drm_info_node *node = (struct drm_info_node *) m->private;
2823 struct drm_device *dev = node->minor->dev;
2824 struct drm_encoder *encoder;
2825 struct intel_encoder *intel_encoder;
2826 struct intel_digital_port *intel_dig_port;
2827 drm_modeset_lock_all(dev);
2828 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2829 intel_encoder = to_intel_encoder(encoder);
2830 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2831 continue;
2832 intel_dig_port = enc_to_dig_port(encoder);
2833 if (!intel_dig_port->dp.can_mst)
2834 continue;
2835
2836 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2837 }
2838 drm_modeset_unlock_all(dev);
2839 return 0;
2840}
2841
07144428
DL		 2842static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2843{
be5c7a90
DL		 2844 struct pipe_crc_info *info = inode->i_private;
2845 struct drm_i915_private *dev_priv = info->dev->dev_private;
2846 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2847
7eb1c496
DV		 2848 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2849 return -ENODEV;
2850
d538bbdf
DL		 2851 spin_lock_irq(&pipe_crc->lock);
2852
2853 if (pipe_crc->opened) {
2854 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2855 return -EBUSY; /* already open */
2856 }
2857
d538bbdf 2858 pipe_crc->opened = true;
07144428
DL		 2859 filep->private_data = inode->i_private;
2860
d538bbdf
DL		 2861 spin_unlock_irq(&pipe_crc->lock);
2862
07144428
DL		 2863 return 0;
2864}
2865
2866static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2867{
be5c7a90
DL		 2868 struct pipe_crc_info *info = inode->i_private;
2869 struct drm_i915_private *dev_priv = info->dev->dev_private;
2870 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2871
d538bbdf
DL		 2872 spin_lock_irq(&pipe_crc->lock);
2873 pipe_crc->opened = false;
2874 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2875
07144428
DL		 2876 return 0;
2877}
2878
2879/* (6 fields, 8 chars each, space separated (5) + '\n') */
2880#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2881/* account for \'0' */
2882#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2883
2884static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2885{
d538bbdf
DL		 2886 assert_spin_locked(&pipe_crc->lock);
2887 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2888 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2889}
2890
2891static ssize_t
2892i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2893 loff_t *pos)
2894{
2895 struct pipe_crc_info *info = filep->private_data;
2896 struct drm_device *dev = info->dev;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2899 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 2900 int n_entries;
07144428
DL		 2901 ssize_t bytes_read;
2902
2903 /*
2904 * Don't allow user space to provide buffers not big enough to hold
2905 * a line of data.
2906 */
2907 if (count < PIPE_CRC_LINE_LEN)
2908 return -EINVAL;
2909
2910 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2911 return 0;
07144428
DL		 2912
2913 /* nothing to read */
d538bbdf 2914 spin_lock_irq(&pipe_crc->lock);
07144428 2915 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2916 int ret;
2917
2918 if (filep->f_flags & O_NONBLOCK) {
2919 spin_unlock_irq(&pipe_crc->lock);
07144428 2920 return -EAGAIN;
d538bbdf 2921 }
07144428 2922
d538bbdf
DL		 2923 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2924 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2925 if (ret) {
2926 spin_unlock_irq(&pipe_crc->lock);
2927 return ret;
2928 }
8bf1e9f1
SH		 2929 }
2930
07144428 2931 /* We now have one or more entries to read */
9ad6d99f 2932 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 2933
07144428 2934 bytes_read = 0;
9ad6d99f
VS		 2935 while (n_entries > 0) {
2936 struct intel_pipe_crc_entry *entry =
2937 &pipe_crc->entries[pipe_crc->tail];
07144428 2938 int ret;
8bf1e9f1 2939
9ad6d99f
VS		 2940 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2941 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2942 break;
2943
2944 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2945 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2946
07144428
DL		 2947 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2948 "%8u %8x %8x %8x %8x %8x\n",
2949 entry->frame, entry->crc[0],
2950 entry->crc[1], entry->crc[2],
2951 entry->crc[3], entry->crc[4]);
2952
9ad6d99f
VS		 2953 spin_unlock_irq(&pipe_crc->lock);
2954
2955 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 2956 if (ret == PIPE_CRC_LINE_LEN)
2957 return -EFAULT;
b2c88f5b 2958
9ad6d99f
VS		 2959 user_buf += PIPE_CRC_LINE_LEN;
2960 n_entries--;
2961
2962 spin_lock_irq(&pipe_crc->lock);
2963 }
8bf1e9f1 2964
d538bbdf
DL		 2965 spin_unlock_irq(&pipe_crc->lock);
2966
07144428
DL		 2967 return bytes_read;
2968}
2969
2970static const struct file_operations i915_pipe_crc_fops = {
2971 .owner = THIS_MODULE,
2972 .open = i915_pipe_crc_open,
2973 .read = i915_pipe_crc_read,
2974 .release = i915_pipe_crc_release,
2975};
2976
2977static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2978 {
2979 .name = "i915_pipe_A_crc",
2980 .pipe = PIPE_A,
2981 },
2982 {
2983 .name = "i915_pipe_B_crc",
2984 .pipe = PIPE_B,
2985 },
2986 {
2987 .name = "i915_pipe_C_crc",
2988 .pipe = PIPE_C,
2989 },
2990};
2991
2992static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2993 enum pipe pipe)
2994{
2995 struct drm_device *dev = minor->dev;
2996 struct dentry *ent;
2997 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2998
2999 info->dev = dev;
3000 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3001 &i915_pipe_crc_fops);
f3c5fe97
WY		 3002 if (!ent)
3003 return -ENOMEM;
07144428
DL		 3004
3005 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3006}
3007
e8dfcf78 3008static const char * const pipe_crc_sources[] = {
926321d5
DV		 3009 "none",
3010 "plane1",
3011 "plane2",
3012 "pf",
5b3a856b 3013 "pipe",
3d099a05
DV		 3014 "TV",
3015 "DP-B",
3016 "DP-C",
3017 "DP-D",
46a19188 3018 "auto",
926321d5
DV		 3019};
3020
3021static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3022{
3023 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3024 return pipe_crc_sources[source];
3025}
3026
bd9db02f 3027static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3028{
3029 struct drm_device *dev = m->private;
3030 struct drm_i915_private *dev_priv = dev->dev_private;
3031 int i;
3032
3033 for (i = 0; i < I915_MAX_PIPES; i++)
3034 seq_printf(m, "%c %s\n", pipe_name(i),
3035 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3036
3037 return 0;
3038}
3039
bd9db02f 3040static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3041{
3042 struct drm_device *dev = inode->i_private;
3043
bd9db02f 3044 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3045}
3046
46a19188 3047static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3048 uint32_t *val)
3049{
46a19188
DV		 3050 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3051 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3052
3053 switch (*source) {
52f843f6
DV		 3054 case INTEL_PIPE_CRC_SOURCE_PIPE:
3055 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3056 break;
3057 case INTEL_PIPE_CRC_SOURCE_NONE:
3058 *val = 0;
3059 break;
3060 default:
3061 return -EINVAL;
3062 }
3063
3064 return 0;
3065}
3066
46a19188
DV		 3067static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3068 enum intel_pipe_crc_source *source)
3069{
3070 struct intel_encoder *encoder;
3071 struct intel_crtc *crtc;
26756809 3072 struct intel_digital_port *dig_port;
46a19188
DV		 3073 int ret = 0;
3074
3075 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3076
6e9f798d 3077 drm_modeset_lock_all(dev);
b2784e15 3078 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3079 if (!encoder->base.crtc)
3080 continue;
3081
3082 crtc = to_intel_crtc(encoder->base.crtc);
3083
3084 if (crtc->pipe != pipe)
3085 continue;
3086
3087 switch (encoder->type) {
3088 case INTEL_OUTPUT_TVOUT:
3089 *source = INTEL_PIPE_CRC_SOURCE_TV;
3090 break;
3091 case INTEL_OUTPUT_DISPLAYPORT:
3092 case INTEL_OUTPUT_EDP:
26756809
DV		 3093 dig_port = enc_to_dig_port(&encoder->base);
3094 switch (dig_port->port) {
3095 case PORT_B:
3096 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3097 break;
3098 case PORT_C:
3099 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3100 break;
3101 case PORT_D:
3102 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3103 break;
3104 default:
3105 WARN(1, "nonexisting DP port %c\n",
3106 port_name(dig_port->port));
3107 break;
3108 }
46a19188 3109 break;
6847d71b
PZ		 3110 default:
3111 break;
46a19188
DV		 3112 }
3113 }
6e9f798d 3114 drm_modeset_unlock_all(dev);
46a19188
DV		 3115
3116 return ret;
3117}
3118
3119static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3120 enum pipe pipe,
3121 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3122 uint32_t *val)
3123{
8d2f24ca
DV		 3124 struct drm_i915_private *dev_priv = dev->dev_private;
3125 bool need_stable_symbols = false;
3126
46a19188
DV		 3127 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3128 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3129 if (ret)
3130 return ret;
3131 }
3132
3133 switch (*source) {
7ac0129b
DV		 3134 case INTEL_PIPE_CRC_SOURCE_PIPE:
3135 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3136 break;
3137 case INTEL_PIPE_CRC_SOURCE_DP_B:
3138 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3139 need_stable_symbols = true;
7ac0129b
DV		 3140 break;
3141 case INTEL_PIPE_CRC_SOURCE_DP_C:
3142 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3143 need_stable_symbols = true;
7ac0129b 3144 break;
2be57922
VS		 3145 case INTEL_PIPE_CRC_SOURCE_DP_D:
3146 if (!IS_CHERRYVIEW(dev))
3147 return -EINVAL;
3148 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3149 need_stable_symbols = true;
3150 break;
7ac0129b
DV		 3151 case INTEL_PIPE_CRC_SOURCE_NONE:
3152 *val = 0;
3153 break;
3154 default:
3155 return -EINVAL;
3156 }
3157
8d2f24ca
DV		 3158 /*
3159 * When the pipe CRC tap point is after the transcoders we need
3160 * to tweak symbol-level features to produce a deterministic series of
3161 * symbols for a given frame. We need to reset those features only once
3162 * a frame (instead of every nth symbol):
3163 * - DC-balance: used to ensure a better clock recovery from the data
3164 * link (SDVO)
3165 * - DisplayPort scrambling: used for EMI reduction
3166 */
3167 if (need_stable_symbols) {
3168 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3169
8d2f24ca 3170 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3171 switch (pipe) {
3172 case PIPE_A:
8d2f24ca 3173 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3174 break;
3175 case PIPE_B:
8d2f24ca 3176 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3177 break;
3178 case PIPE_C:
3179 tmp |= PIPE_C_SCRAMBLE_RESET;
3180 break;
3181 default:
3182 return -EINVAL;
3183 }
8d2f24ca
DV		 3184 I915_WRITE(PORT_DFT2_G4X, tmp);
3185 }
3186
7ac0129b
DV		 3187 return 0;
3188}
3189
4b79ebf7 3190static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3191 enum pipe pipe,
3192 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3193 uint32_t *val)
3194{
84093603
DV		 3195 struct drm_i915_private *dev_priv = dev->dev_private;
3196 bool need_stable_symbols = false;
3197
46a19188
DV		 3198 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3199 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3200 if (ret)
3201 return ret;
3202 }
3203
3204 switch (*source) {
4b79ebf7
DV		 3205 case INTEL_PIPE_CRC_SOURCE_PIPE:
3206 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3207 break;
3208 case INTEL_PIPE_CRC_SOURCE_TV:
3209 if (!SUPPORTS_TV(dev))
3210 return -EINVAL;
3211 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3212 break;
3213 case INTEL_PIPE_CRC_SOURCE_DP_B:
3214 if (!IS_G4X(dev))
3215 return -EINVAL;
3216 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3217 need_stable_symbols = true;
4b79ebf7
DV		 3218 break;
3219 case INTEL_PIPE_CRC_SOURCE_DP_C:
3220 if (!IS_G4X(dev))
3221 return -EINVAL;
3222 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3223 need_stable_symbols = true;
4b79ebf7
DV		 3224 break;
3225 case INTEL_PIPE_CRC_SOURCE_DP_D:
3226 if (!IS_G4X(dev))
3227 return -EINVAL;
3228 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3229 need_stable_symbols = true;
4b79ebf7
DV		 3230 break;
3231 case INTEL_PIPE_CRC_SOURCE_NONE:
3232 *val = 0;
3233 break;
3234 default:
3235 return -EINVAL;
3236 }
3237
84093603
DV		 3238 /*
3239 * When the pipe CRC tap point is after the transcoders we need
3240 * to tweak symbol-level features to produce a deterministic series of
3241 * symbols for a given frame. We need to reset those features only once
3242 * a frame (instead of every nth symbol):
3243 * - DC-balance: used to ensure a better clock recovery from the data
3244 * link (SDVO)
3245 * - DisplayPort scrambling: used for EMI reduction
3246 */
3247 if (need_stable_symbols) {
3248 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3249
3250 WARN_ON(!IS_G4X(dev));
3251
3252 I915_WRITE(PORT_DFT_I9XX,
3253 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3254
3255 if (pipe == PIPE_A)
3256 tmp |= PIPE_A_SCRAMBLE_RESET;
3257 else
3258 tmp |= PIPE_B_SCRAMBLE_RESET;
3259
3260 I915_WRITE(PORT_DFT2_G4X, tmp);
3261 }
3262
4b79ebf7
DV		 3263 return 0;
3264}
3265
8d2f24ca
DV		 3266static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3267 enum pipe pipe)
3268{
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3271
eb736679
VS		 3272 switch (pipe) {
3273 case PIPE_A:
8d2f24ca 3274 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3275 break;
3276 case PIPE_B:
8d2f24ca 3277 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3278 break;
3279 case PIPE_C:
3280 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3281 break;
3282 default:
3283 return;
3284 }
8d2f24ca
DV		 3285 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3286 tmp &= ~DC_BALANCE_RESET_VLV;
3287 I915_WRITE(PORT_DFT2_G4X, tmp);
3288
3289}
3290
84093603
DV		 3291static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3292 enum pipe pipe)
3293{
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3296
3297 if (pipe == PIPE_A)
3298 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3299 else
3300 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3301 I915_WRITE(PORT_DFT2_G4X, tmp);
3302
3303 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3304 I915_WRITE(PORT_DFT_I9XX,
3305 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3306 }
3307}
3308
46a19188 3309static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3310 uint32_t *val)
3311{
46a19188
DV		 3312 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3313 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3314
3315 switch (*source) {
5b3a856b
DV		 3316 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3317 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3318 break;
3319 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3320 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3321 break;
5b3a856b
DV		 3322 case INTEL_PIPE_CRC_SOURCE_PIPE:
3323 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3324 break;
3d099a05 3325 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3326 *val = 0;
3327 break;
3d099a05
DV		 3328 default:
3329 return -EINVAL;
5b3a856b
DV		 3330 }
3331
3332 return 0;
3333}
3334
fabf6e51
DV		 3335static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3336{
3337 struct drm_i915_private *dev_priv = dev->dev_private;
3338 struct intel_crtc *crtc =
3339 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3340
3341 drm_modeset_lock_all(dev);
3342 /*
3343 * If we use the eDP transcoder we need to make sure that we don't
3344 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3345 * relevant on hsw with pipe A when using the always-on power well
3346 * routing.
3347 */
6e3c9717
ACO		 3348 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3349 !crtc->config->pch_pfit.enabled) {
3350 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3351
3352 intel_display_power_get(dev_priv,
3353 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3354
3355 dev_priv->display.crtc_disable(&crtc->base);
3356 dev_priv->display.crtc_enable(&crtc->base);
3357 }
3358 drm_modeset_unlock_all(dev);
3359}
3360
3361static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3362{
3363 struct drm_i915_private *dev_priv = dev->dev_private;
3364 struct intel_crtc *crtc =
3365 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3366
3367 drm_modeset_lock_all(dev);
3368 /*
3369 * If we use the eDP transcoder we need to make sure that we don't
3370 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3371 * relevant on hsw with pipe A when using the always-on power well
3372 * routing.
3373 */
6e3c9717
ACO		 3374 if (crtc->config->pch_pfit.force_thru) {
3375 crtc->config->pch_pfit.force_thru = false;
fabf6e51
DV		 3376
3377 dev_priv->display.crtc_disable(&crtc->base);
3378 dev_priv->display.crtc_enable(&crtc->base);
3379
3380 intel_display_power_put(dev_priv,
3381 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3382 }
3383 drm_modeset_unlock_all(dev);
3384}
3385
3386static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3387 enum pipe pipe,
3388 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3389 uint32_t *val)
3390{
46a19188
DV		 3391 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3392 *source = INTEL_PIPE_CRC_SOURCE_PF;
3393
3394 switch (*source) {
5b3a856b
DV		 3395 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3396 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3397 break;
3398 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3399 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3400 break;
3401 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3402 if (IS_HASWELL(dev) && pipe == PIPE_A)
3403 hsw_trans_edp_pipe_A_crc_wa(dev);
3404
5b3a856b
DV		 3405 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3406 break;
3d099a05 3407 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3408 *val = 0;
3409 break;
3d099a05
DV		 3410 default:
3411 return -EINVAL;
5b3a856b
DV		 3412 }
3413
3414 return 0;
3415}
3416
926321d5
DV		 3417static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3418 enum intel_pipe_crc_source source)
3419{
3420 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3421 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3422 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3423 pipe));
432f3342 3424 u32 val = 0; /* shut up gcc */
5b3a856b 3425 int ret;
926321d5 3426
cc3da175
DL		 3427 if (pipe_crc->source == source)
3428 return 0;
3429
ae676fcd
DL		 3430 /* forbid changing the source without going back to 'none' */
3431 if (pipe_crc->source && source)
3432 return -EINVAL;
3433
9d8b0588
DV		 3434 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3435 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3436 return -EIO;
3437 }
3438
52f843f6 3439 if (IS_GEN2(dev))
46a19188 3440 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3441 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3442 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3443 else if (IS_VALLEYVIEW(dev))
fabf6e51 3444 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3445 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3446 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3447 else
fabf6e51 3448 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3449
3450 if (ret != 0)
3451 return ret;
3452
4b584369
DL		 3453 /* none -> real source transition */
3454 if (source) {
4252fbc3
VS		 3455 struct intel_pipe_crc_entry *entries;
3456
7cd6ccff
DL		 3457 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3458 pipe_name(pipe), pipe_crc_source_name(source));
3459
3cf54b34
VS		 3460 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3461 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3462 GFP_KERNEL);
3463 if (!entries)
e5f75aca
DL		 3464 return -ENOMEM;
3465
8c740dce
PZ		 3466 /*
3467 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3468 * enabled and disabled dynamically based on package C states,
3469 * user space can't make reliable use of the CRCs, so let's just
3470 * completely disable it.
3471 */
3472 hsw_disable_ips(crtc);
3473
d538bbdf 3474 spin_lock_irq(&pipe_crc->lock);
64387b61 3475 kfree(pipe_crc->entries);
4252fbc3 3476 pipe_crc->entries = entries;
d538bbdf
DL		 3477 pipe_crc->head = 0;
3478 pipe_crc->tail = 0;
3479 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3480 }
3481
cc3da175 3482 pipe_crc->source = source;
926321d5 3483
926321d5
DV		 3484 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3485 POSTING_READ(PIPE_CRC_CTL(pipe));
3486
e5f75aca
DL		 3487 /* real source -> none transition */
3488 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3489 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3490 struct intel_crtc *crtc =
3491 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3492
7cd6ccff
DL		 3493 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3494 pipe_name(pipe));
3495
a33d7105
DV		 3496 drm_modeset_lock(&crtc->base.mutex, NULL);
3497 if (crtc->active)
3498 intel_wait_for_vblank(dev, pipe);
3499 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3500
d538bbdf
DL		 3501 spin_lock_irq(&pipe_crc->lock);
3502 entries = pipe_crc->entries;
e5f75aca 3503 pipe_crc->entries = NULL;
9ad6d99f
VS		 3504 pipe_crc->head = 0;
3505 pipe_crc->tail = 0;
d538bbdf
DL		 3506 spin_unlock_irq(&pipe_crc->lock);
3507
3508 kfree(entries);
84093603
DV		 3509
3510 if (IS_G4X(dev))
3511 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3512 else if (IS_VALLEYVIEW(dev))
3513 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3514 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3515 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3516
3517 hsw_enable_ips(crtc);
e5f75aca
DL		 3518 }
3519
926321d5
DV		 3520 return 0;
3521}
3522
3523/*
3524 * Parse pipe CRC command strings:
b94dec87
DL		 3525 * command: wsp* object wsp+ name wsp+ source wsp*
3526 * object: 'pipe'
3527 * name: (A | B | C)
926321d5
DV		 3528 * source: (none | plane1 | plane2 | pf)
3529 * wsp: (#0x20 | #0x9 | #0xA)+
3530 *
3531 * eg.:
b94dec87
DL		 3532 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3533 * "pipe A none" -> Stop CRC
926321d5 3534 */
bd9db02f 3535static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3536{
3537 int n_words = 0;
3538
3539 while (*buf) {
3540 char *end;
3541
3542 /* skip leading white space */
3543 buf = skip_spaces(buf);
3544 if (!*buf)
3545 break; /* end of buffer */
3546
3547 /* find end of word */
3548 for (end = buf; *end && !isspace(*end); end++)
3549 ;
3550
3551 if (n_words == max_words) {
3552 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3553 max_words);
3554 return -EINVAL; /* ran out of words[] before bytes */
3555 }
3556
3557 if (*end)
3558 *end++ = '\0';
3559 words[n_words++] = buf;
3560 buf = end;
3561 }
3562
3563 return n_words;
3564}
3565
b94dec87
DL		 3566enum intel_pipe_crc_object {
3567 PIPE_CRC_OBJECT_PIPE,
3568};
3569
e8dfcf78 3570static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3571 "pipe",
3572};
3573
3574static int
bd9db02f 3575display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3576{
3577 int i;
3578
3579 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3580 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3581 *o = i;
b94dec87
DL		 3582 return 0;
3583 }
3584
3585 return -EINVAL;
3586}
3587
bd9db02f 3588static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3589{
3590 const char name = buf[0];
3591
3592 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3593 return -EINVAL;
3594
3595 *pipe = name - 'A';
3596
3597 return 0;
3598}
3599
3600static int
bd9db02f 3601display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3602{
3603 int i;
3604
3605 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3606 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3607 *s = i;
926321d5
DV		 3608 return 0;
3609 }
3610
3611 return -EINVAL;
3612}
3613
bd9db02f 3614static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3615{
b94dec87 3616#define N_WORDS 3
926321d5 3617 int n_words;
b94dec87 3618 char *words[N_WORDS];
926321d5 3619 enum pipe pipe;
b94dec87 3620 enum intel_pipe_crc_object object;
926321d5
DV		 3621 enum intel_pipe_crc_source source;
3622
bd9db02f 3623 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3624 if (n_words != N_WORDS) {
3625 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3626 N_WORDS);
3627 return -EINVAL;
3628 }
3629
bd9db02f 3630 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3631 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3632 return -EINVAL;
3633 }
3634
bd9db02f 3635 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3636 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3637 return -EINVAL;
3638 }
3639
bd9db02f 3640 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3641 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3642 return -EINVAL;
3643 }
3644
3645 return pipe_crc_set_source(dev, pipe, source);
3646}
3647
bd9db02f
DL		 3648static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3649 size_t len, loff_t *offp)
926321d5
DV		 3650{
3651 struct seq_file *m = file->private_data;
3652 struct drm_device *dev = m->private;
3653 char *tmpbuf;
3654 int ret;
3655
3656 if (len == 0)
3657 return 0;
3658
3659 if (len > PAGE_SIZE - 1) {
3660 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3661 PAGE_SIZE);
3662 return -E2BIG;
3663 }
3664
3665 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3666 if (!tmpbuf)
3667 return -ENOMEM;
3668
3669 if (copy_from_user(tmpbuf, ubuf, len)) {
3670 ret = -EFAULT;
3671 goto out;
3672 }
3673 tmpbuf[len] = '\0';
3674
bd9db02f 3675 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3676
3677out:
3678 kfree(tmpbuf);
3679 if (ret < 0)
3680 return ret;
3681
3682 *offp += len;
3683 return len;
3684}
3685
bd9db02f 3686static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3687 .owner = THIS_MODULE,
bd9db02f 3688 .open = display_crc_ctl_open,
926321d5
DV		 3689 .read = seq_read,
3690 .llseek = seq_lseek,
3691 .release = single_release,
bd9db02f 3692 .write = display_crc_ctl_write
926321d5
DV		 3693};
3694
97e94b22 3695static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3696{
3697 struct drm_device *dev = m->private;
546c81fd 3698 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3699 int level;
3700
3701 drm_modeset_lock_all(dev);
3702
3703 for (level = 0; level < num_levels; level++) {
3704 unsigned int latency = wm[level];
3705
97e94b22
DL		 3706 /*
3707 * - WM1+ latency values in 0.5us units
3708 * - latencies are in us on gen9
3709 */
3710 if (INTEL_INFO(dev)->gen >= 9)
3711 latency *= 10;
3712 else if (level > 0)
369a1342
VS		 3713 latency *= 5;
3714
3715 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3716 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3717 }
3718
3719 drm_modeset_unlock_all(dev);
3720}
3721
3722static int pri_wm_latency_show(struct seq_file *m, void *data)
3723{
3724 struct drm_device *dev = m->private;
97e94b22
DL		 3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 const uint16_t *latencies;
3727
3728 if (INTEL_INFO(dev)->gen >= 9)
3729 latencies = dev_priv->wm.skl_latency;
3730 else
3731 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3732
97e94b22 3733 wm_latency_show(m, latencies);
369a1342
VS		 3734
3735 return 0;
3736}
3737
3738static int spr_wm_latency_show(struct seq_file *m, void *data)
3739{
3740 struct drm_device *dev = m->private;
97e94b22
DL		 3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 const uint16_t *latencies;
3743
3744 if (INTEL_INFO(dev)->gen >= 9)
3745 latencies = dev_priv->wm.skl_latency;
3746 else
3747 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3748
97e94b22 3749 wm_latency_show(m, latencies);
369a1342
VS		 3750
3751 return 0;
3752}
3753
3754static int cur_wm_latency_show(struct seq_file *m, void *data)
3755{
3756 struct drm_device *dev = m->private;
97e94b22
DL		 3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 const uint16_t *latencies;
3759
3760 if (INTEL_INFO(dev)->gen >= 9)
3761 latencies = dev_priv->wm.skl_latency;
3762 else
3763 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3764
97e94b22 3765 wm_latency_show(m, latencies);
369a1342
VS		 3766
3767 return 0;
3768}
3769
3770static int pri_wm_latency_open(struct inode *inode, struct file *file)
3771{
3772 struct drm_device *dev = inode->i_private;
3773
9ad0257c 3774 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3775 return -ENODEV;
3776
3777 return single_open(file, pri_wm_latency_show, dev);
3778}
3779
3780static int spr_wm_latency_open(struct inode *inode, struct file *file)
3781{
3782 struct drm_device *dev = inode->i_private;
3783
9ad0257c 3784 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3785 return -ENODEV;
3786
3787 return single_open(file, spr_wm_latency_show, dev);
3788}
3789
3790static int cur_wm_latency_open(struct inode *inode, struct file *file)
3791{
3792 struct drm_device *dev = inode->i_private;
3793
9ad0257c 3794 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3795 return -ENODEV;
3796
3797 return single_open(file, cur_wm_latency_show, dev);
3798}
3799
3800static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3801 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3802{
3803 struct seq_file *m = file->private_data;
3804 struct drm_device *dev = m->private;
97e94b22 3805 uint16_t new[8] = { 0 };
546c81fd 3806 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3807 int level;
3808 int ret;
3809 char tmp[32];
3810
3811 if (len >= sizeof(tmp))
3812 return -EINVAL;
3813
3814 if (copy_from_user(tmp, ubuf, len))
3815 return -EFAULT;
3816
3817 tmp[len] = '\0';
3818
97e94b22
DL		 3819 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3820 &new[0], &new[1], &new[2], &new[3],
3821 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 3822 if (ret != num_levels)
3823 return -EINVAL;
3824
3825 drm_modeset_lock_all(dev);
3826
3827 for (level = 0; level < num_levels; level++)
3828 wm[level] = new[level];
3829
3830 drm_modeset_unlock_all(dev);
3831
3832 return len;
3833}
3834
3835
3836static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3837 size_t len, loff_t *offp)
3838{
3839 struct seq_file *m = file->private_data;
3840 struct drm_device *dev = m->private;
97e94b22
DL		 3841 struct drm_i915_private *dev_priv = dev->dev_private;
3842 uint16_t *latencies;
369a1342 3843
97e94b22
DL		 3844 if (INTEL_INFO(dev)->gen >= 9)
3845 latencies = dev_priv->wm.skl_latency;
3846 else
3847 latencies = to_i915(dev)->wm.pri_latency;
3848
3849 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3850}
3851
3852static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3853 size_t len, loff_t *offp)
3854{
3855 struct seq_file *m = file->private_data;
3856 struct drm_device *dev = m->private;
97e94b22
DL		 3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858 uint16_t *latencies;
369a1342 3859
97e94b22
DL		 3860 if (INTEL_INFO(dev)->gen >= 9)
3861 latencies = dev_priv->wm.skl_latency;
3862 else
3863 latencies = to_i915(dev)->wm.spr_latency;
3864
3865 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3866}
3867
3868static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3869 size_t len, loff_t *offp)
3870{
3871 struct seq_file *m = file->private_data;
3872 struct drm_device *dev = m->private;
97e94b22
DL		 3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 uint16_t *latencies;
3875
3876 if (INTEL_INFO(dev)->gen >= 9)
3877 latencies = dev_priv->wm.skl_latency;
3878 else
3879 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3880
97e94b22 3881 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3882}
3883
3884static const struct file_operations i915_pri_wm_latency_fops = {
3885 .owner = THIS_MODULE,
3886 .open = pri_wm_latency_open,
3887 .read = seq_read,
3888 .llseek = seq_lseek,
3889 .release = single_release,
3890 .write = pri_wm_latency_write
3891};
3892
3893static const struct file_operations i915_spr_wm_latency_fops = {
3894 .owner = THIS_MODULE,
3895 .open = spr_wm_latency_open,
3896 .read = seq_read,
3897 .llseek = seq_lseek,
3898 .release = single_release,
3899 .write = spr_wm_latency_write
3900};
3901
3902static const struct file_operations i915_cur_wm_latency_fops = {
3903 .owner = THIS_MODULE,
3904 .open = cur_wm_latency_open,
3905 .read = seq_read,
3906 .llseek = seq_lseek,
3907 .release = single_release,
3908 .write = cur_wm_latency_write
3909};
3910
647416f9
KC		 3911static int
3912i915_wedged_get(void *data, u64 *val)
f3cd474b 3913{
647416f9 3914 struct drm_device *dev = data;
e277a1f8 3915 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3916
647416f9 3917 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3918
647416f9 3919 return 0;
f3cd474b
CW		 3920}
3921
647416f9
KC		 3922static int
3923i915_wedged_set(void *data, u64 val)
f3cd474b 3924{
647416f9 3925 struct drm_device *dev = data;
d46c0517
ID		 3926 struct drm_i915_private *dev_priv = dev->dev_private;
3927
3928 intel_runtime_pm_get(dev_priv);
f3cd474b 3929
58174462
MK		 3930 i915_handle_error(dev, val,
3931 "Manually setting wedged to %llu", val);
d46c0517
ID		 3932
3933 intel_runtime_pm_put(dev_priv);
3934
647416f9 3935 return 0;
f3cd474b
CW		 3936}
3937
647416f9
KC		 3938DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3939 i915_wedged_get, i915_wedged_set,
3a3b4f98 3940 "%llu\n");
f3cd474b 3941
647416f9
KC		 3942static int
3943i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3944{
647416f9 3945 struct drm_device *dev = data;
e277a1f8 3946 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3947
647416f9 3948 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3949
647416f9 3950 return 0;
e5eb3d63
DV		 3951}
3952
647416f9
KC		 3953static int
3954i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3955{
647416f9 3956 struct drm_device *dev = data;
e5eb3d63 3957 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3958 int ret;
e5eb3d63 3959
647416f9 3960 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3961
22bcfc6a
DV		 3962 ret = mutex_lock_interruptible(&dev->struct_mutex);
3963 if (ret)
3964 return ret;
3965
99584db3 3966 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3967 mutex_unlock(&dev->struct_mutex);
3968
647416f9 3969 return 0;
e5eb3d63
DV		 3970}
3971
647416f9
KC		 3972DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3973 i915_ring_stop_get, i915_ring_stop_set,
3974 "0x%08llx\n");
d5442303 3975
094f9a54
CW		 3976static int
3977i915_ring_missed_irq_get(void *data, u64 *val)
3978{
3979 struct drm_device *dev = data;
3980 struct drm_i915_private *dev_priv = dev->dev_private;
3981
3982 *val = dev_priv->gpu_error.missed_irq_rings;
3983 return 0;
3984}
3985
3986static int
3987i915_ring_missed_irq_set(void *data, u64 val)
3988{
3989 struct drm_device *dev = data;
3990 struct drm_i915_private *dev_priv = dev->dev_private;
3991 int ret;
3992
3993 /* Lock against concurrent debugfs callers */
3994 ret = mutex_lock_interruptible(&dev->struct_mutex);
3995 if (ret)
3996 return ret;
3997 dev_priv->gpu_error.missed_irq_rings = val;
3998 mutex_unlock(&dev->struct_mutex);
3999
4000 return 0;
4001}
4002
4003DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4004 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4005 "0x%08llx\n");
4006
4007static int
4008i915_ring_test_irq_get(void *data, u64 *val)
4009{
4010 struct drm_device *dev = data;
4011 struct drm_i915_private *dev_priv = dev->dev_private;
4012
4013 *val = dev_priv->gpu_error.test_irq_rings;
4014
4015 return 0;
4016}
4017
4018static int
4019i915_ring_test_irq_set(void *data, u64 val)
4020{
4021 struct drm_device *dev = data;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 int ret;
4024
4025 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4026
4027 /* Lock against concurrent debugfs callers */
4028 ret = mutex_lock_interruptible(&dev->struct_mutex);
4029 if (ret)
4030 return ret;
4031
4032 dev_priv->gpu_error.test_irq_rings = val;
4033 mutex_unlock(&dev->struct_mutex);
4034
4035 return 0;
4036}
4037
4038DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4039 i915_ring_test_irq_get, i915_ring_test_irq_set,
4040 "0x%08llx\n");
4041
dd624afd
CW		 4042#define DROP_UNBOUND 0x1
4043#define DROP_BOUND 0x2
4044#define DROP_RETIRE 0x4
4045#define DROP_ACTIVE 0x8
4046#define DROP_ALL (DROP_UNBOUND | \
4047 DROP_BOUND | \
4048 DROP_RETIRE | \
4049 DROP_ACTIVE)
647416f9
KC		 4050static int
4051i915_drop_caches_get(void *data, u64 *val)
dd624afd 4052{
647416f9 4053 *val = DROP_ALL;
dd624afd 4054
647416f9 4055 return 0;
dd624afd
CW		 4056}
4057
647416f9
KC		 4058static int
4059i915_drop_caches_set(void *data, u64 val)
dd624afd 4060{
647416f9 4061 struct drm_device *dev = data;
dd624afd 4062 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4063 int ret;
dd624afd 4064
2f9fe5ff 4065 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4066
4067 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4068 * on ioctls on -EAGAIN. */
4069 ret = mutex_lock_interruptible(&dev->struct_mutex);
4070 if (ret)
4071 return ret;
4072
4073 if (val & DROP_ACTIVE) {
4074 ret = i915_gpu_idle(dev);
4075 if (ret)
4076 goto unlock;
4077 }
4078
4079 if (val & (DROP_RETIRE | DROP_ACTIVE))
4080 i915_gem_retire_requests(dev);
4081
21ab4e74
CW		 4082 if (val & DROP_BOUND)
4083 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4084
21ab4e74
CW		 4085 if (val & DROP_UNBOUND)
4086 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4087
4088unlock:
4089 mutex_unlock(&dev->struct_mutex);
4090
647416f9 4091 return ret;
dd624afd
CW		 4092}
4093
647416f9
KC		 4094DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4095 i915_drop_caches_get, i915_drop_caches_set,
4096 "0x%08llx\n");
dd624afd 4097
647416f9
KC		 4098static int
4099i915_max_freq_get(void *data, u64 *val)
358733e9 4100{
647416f9 4101 struct drm_device *dev = data;
e277a1f8 4102 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4103 int ret;
004777cb 4104
daa3afb2 4105 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4106 return -ENODEV;
4107
5c9669ce
TR		 4108 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4109
4fc688ce 4110 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4111 if (ret)
4112 return ret;
358733e9 4113
0a073b84 4114 if (IS_VALLEYVIEW(dev))
b39fb297 4115 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 4116 else
b39fb297 4117 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 4118 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4119
647416f9 4120 return 0;
358733e9
JB		 4121}
4122
647416f9
KC		 4123static int
4124i915_max_freq_set(void *data, u64 val)
358733e9 4125{
647416f9 4126 struct drm_device *dev = data;
358733e9 4127 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4128 u32 rp_state_cap, hw_max, hw_min;
647416f9 4129 int ret;
004777cb 4130
daa3afb2 4131 if (INTEL_INFO(dev)->gen < 6)
004777cb 4132 return -ENODEV;
358733e9 4133
5c9669ce
TR		 4134 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4135
647416f9 4136 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4137
4fc688ce 4138 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4139 if (ret)
4140 return ret;
4141
358733e9
JB		 4142 /*
4143 * Turbo will still be enabled, but won't go above the set value.
4144 */
0a073b84 4145 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4146 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4147
03af2045
VS		 4148 hw_max = dev_priv->rps.max_freq;
4149 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4150 } else {
4151 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4152
4153 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4154 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4155 hw_min = (rp_state_cap >> 16) & 0xff;
4156 }
4157
b39fb297 4158 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4159 mutex_unlock(&dev_priv->rps.hw_lock);
4160 return -EINVAL;
0a073b84
JB		 4161 }
4162
b39fb297 4163 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 4164
4165 if (IS_VALLEYVIEW(dev))
4166 valleyview_set_rps(dev, val);
4167 else
4168 gen6_set_rps(dev, val);
4169
4fc688ce 4170 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4171
647416f9 4172 return 0;
358733e9
JB		 4173}
4174
647416f9
KC		 4175DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4176 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4177 "%llu\n");
358733e9 4178
647416f9
KC		 4179static int
4180i915_min_freq_get(void *data, u64 *val)
1523c310 4181{
647416f9 4182 struct drm_device *dev = data;
e277a1f8 4183 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4184 int ret;
004777cb 4185
daa3afb2 4186 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4187 return -ENODEV;
4188
5c9669ce
TR		 4189 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4190
4fc688ce 4191 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4192 if (ret)
4193 return ret;
1523c310 4194
0a073b84 4195 if (IS_VALLEYVIEW(dev))
b39fb297 4196 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 4197 else
b39fb297 4198 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 4199 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4200
647416f9 4201 return 0;
1523c310
JB		 4202}
4203
647416f9
KC		 4204static int
4205i915_min_freq_set(void *data, u64 val)
1523c310 4206{
647416f9 4207 struct drm_device *dev = data;
1523c310 4208 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4209 u32 rp_state_cap, hw_max, hw_min;
647416f9 4210 int ret;
004777cb 4211
daa3afb2 4212 if (INTEL_INFO(dev)->gen < 6)
004777cb 4213 return -ENODEV;
1523c310 4214
5c9669ce
TR		 4215 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4216
647416f9 4217 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4218
4fc688ce 4219 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4220 if (ret)
4221 return ret;
4222
1523c310
JB		 4223 /*
4224 * Turbo will still be enabled, but won't go below the set value.
4225 */
0a073b84 4226 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4227 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4228
03af2045
VS		 4229 hw_max = dev_priv->rps.max_freq;
4230 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4231 } else {
4232 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4233
4234 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4235 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4236 hw_min = (rp_state_cap >> 16) & 0xff;
4237 }
4238
b39fb297 4239 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4240 mutex_unlock(&dev_priv->rps.hw_lock);
4241 return -EINVAL;
0a073b84 4242 }
dd0a1aa1 4243
b39fb297 4244 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 4245
4246 if (IS_VALLEYVIEW(dev))
4247 valleyview_set_rps(dev, val);
4248 else
4249 gen6_set_rps(dev, val);
4250
4fc688ce 4251 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4252
647416f9 4253 return 0;
1523c310
JB		 4254}
4255
647416f9
KC		 4256DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4257 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4258 "%llu\n");
1523c310 4259
647416f9
KC		 4260static int
4261i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4262{
647416f9 4263 struct drm_device *dev = data;
e277a1f8 4264 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4265 u32 snpcr;
647416f9 4266 int ret;
07b7ddd9 4267
004777cb
DV		 4268 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4269 return -ENODEV;
4270
22bcfc6a
DV		 4271 ret = mutex_lock_interruptible(&dev->struct_mutex);
4272 if (ret)
4273 return ret;
c8c8fb33 4274 intel_runtime_pm_get(dev_priv);
22bcfc6a 4275
07b7ddd9 4276 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4277
4278 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4279 mutex_unlock(&dev_priv->dev->struct_mutex);
4280
647416f9 4281 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4282
647416f9 4283 return 0;
07b7ddd9
JB		 4284}
4285
647416f9
KC		 4286static int
4287i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4288{
647416f9 4289 struct drm_device *dev = data;
07b7ddd9 4290 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4291 u32 snpcr;
07b7ddd9 4292
004777cb
DV		 4293 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4294 return -ENODEV;
4295
647416f9 4296 if (val > 3)
07b7ddd9
JB		 4297 return -EINVAL;
4298
c8c8fb33 4299 intel_runtime_pm_get(dev_priv);
647416f9 4300 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4301
4302 /* Update the cache sharing policy here as well */
4303 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4304 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4305 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4306 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4307
c8c8fb33 4308 intel_runtime_pm_put(dev_priv);
647416f9 4309 return 0;
07b7ddd9
JB		 4310}
4311
647416f9
KC		 4312DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4313 i915_cache_sharing_get, i915_cache_sharing_set,
4314 "%llu\n");
07b7ddd9 4315
6d794d42
BW		 4316static int i915_forcewake_open(struct inode *inode, struct file *file)
4317{
4318 struct drm_device *dev = inode->i_private;
4319 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4320
075edca4 4321 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4322 return 0;
4323
6daccb0b 4324 intel_runtime_pm_get(dev_priv);
c8d9a590 4325 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4326
4327 return 0;
4328}
4329
c43b5634 4330static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4331{
4332 struct drm_device *dev = inode->i_private;
4333 struct drm_i915_private *dev_priv = dev->dev_private;
4334
075edca4 4335 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4336 return 0;
4337
c8d9a590 4338 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4339 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4340
4341 return 0;
4342}
4343
4344static const struct file_operations i915_forcewake_fops = {
4345 .owner = THIS_MODULE,
4346 .open = i915_forcewake_open,
4347 .release = i915_forcewake_release,
4348};
4349
4350static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4351{
4352 struct drm_device *dev = minor->dev;
4353 struct dentry *ent;
4354
4355 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4356 S_IRUSR,
6d794d42
BW		 4357 root, dev,
4358 &i915_forcewake_fops);
f3c5fe97
WY		 4359 if (!ent)
4360 return -ENOMEM;
6d794d42 4361
8eb57294 4362 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4363}
4364
6a9c308d
DV		 4365static int i915_debugfs_create(struct dentry *root,
4366 struct drm_minor *minor,
4367 const char *name,
4368 const struct file_operations *fops)
07b7ddd9
JB		 4369{
4370 struct drm_device *dev = minor->dev;
4371 struct dentry *ent;
4372
6a9c308d 4373 ent = debugfs_create_file(name,
07b7ddd9
JB		 4374 S_IRUGO | S_IWUSR,
4375 root, dev,
6a9c308d 4376 fops);
f3c5fe97
WY		 4377 if (!ent)
4378 return -ENOMEM;
07b7ddd9 4379
6a9c308d 4380 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4381}
4382
06c5bf8c 4383static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4384 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4385 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4386 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4387 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4388 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4389 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4390 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4391 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4392 {"i915_gem_request", i915_gem_request_info, 0},
4393 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4394 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4395 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4396 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4397 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4398 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4399 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4400 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 4401 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 4402 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4403 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4404 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4405 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4406 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4407 {"i915_sr_status", i915_sr_status, 0},
44834a67 4408 {"i915_opregion", i915_opregion, 0},
37811fcc 4409 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4410 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4411 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4412 {"i915_execlists", i915_execlists, 0},
6d794d42 4413 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 4414 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4415 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4416 {"i915_llc", i915_llc, 0},
e91fd8c6 4417 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4418 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4419 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4420 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4421 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4422 {"i915_display_info", i915_display_info, 0},
e04934cf 4423 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4424 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4425 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4426 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4427 {"i915_ddb_info", i915_ddb_info, 0},
2017263e 4428};
27c202ad 4429#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4430
06c5bf8c 4431static const struct i915_debugfs_files {
34b9674c
DV		 4432 const char *name;
4433 const struct file_operations *fops;
4434} i915_debugfs_files[] = {
4435 {"i915_wedged", &i915_wedged_fops},
4436 {"i915_max_freq", &i915_max_freq_fops},
4437 {"i915_min_freq", &i915_min_freq_fops},
4438 {"i915_cache_sharing", &i915_cache_sharing_fops},
4439 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4440 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4441 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4442 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4443 {"i915_error_state", &i915_error_state_fops},
4444 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4445 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4446 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4447 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4448 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4449 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4450};
4451
07144428
DL		 4452void intel_display_crc_init(struct drm_device *dev)
4453{
4454 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4455 enum pipe pipe;
07144428 4456
055e393f 4457 for_each_pipe(dev_priv, pipe) {
b378360e 4458 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4459
d538bbdf
DL		 4460 pipe_crc->opened = false;
4461 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4462 init_waitqueue_head(&pipe_crc->wq);
4463 }
4464}
4465
27c202ad 4466int i915_debugfs_init(struct drm_minor *minor)
2017263e 4467{
34b9674c 4468 int ret, i;
f3cd474b 4469
6d794d42 4470 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4471 if (ret)
4472 return ret;
6a9c308d 4473
07144428
DL		 4474 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4475 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4476 if (ret)
4477 return ret;
4478 }
4479
34b9674c
DV		 4480 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4481 ret = i915_debugfs_create(minor->debugfs_root, minor,
4482 i915_debugfs_files[i].name,
4483 i915_debugfs_files[i].fops);
4484 if (ret)
4485 return ret;
4486 }
40633219 4487
27c202ad
BG		 4488 return drm_debugfs_create_files(i915_debugfs_list,
4489 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4490 minor->debugfs_root, minor);
4491}
4492
27c202ad 4493void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4494{
34b9674c
DV		 4495 int i;
4496
27c202ad
BG		 4497 drm_debugfs_remove_files(i915_debugfs_list,
4498 I915_DEBUGFS_ENTRIES, minor);
07144428 4499
6d794d42
BW		 4500 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4501 1, minor);
07144428 4502
e309a997 4503 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4504 struct drm_info_list *info_list =
4505 (struct drm_info_list *)&i915_pipe_crc_data[i];
4506
4507 drm_debugfs_remove_files(info_list, 1, minor);
4508 }
4509
34b9674c
DV		 4510 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4511 struct drm_info_list *info_list =
4512 (struct drm_info_list *) i915_debugfs_files[i].fops;
4513
4514 drm_debugfs_remove_files(info_list, 1, minor);
4515 }
2017263e 4516}
Linux 6.x block layer and io_uring tree(s)