projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Update ring freq for full gpu freq range
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
aff43766 119 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
0a4cd7c8 139 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 336 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 337 continue;
338
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
349 if (obj->ring)
350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
ca191b13
BW		 363#define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
366 ++count; \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
369 ++mappable_count; \
370 } \
371 } \
372} while (0)
373
374static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 375{
9f25d007 376 struct drm_info_node *node = m->private;
73aa808f
CW		 377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
6299f992 381 struct drm_i915_gem_object *obj;
5cef07e1 382 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 383 struct drm_file *file;
ca191b13 384 struct i915_vma *vma;
73aa808f
CW		 385 int ret;
386
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
388 if (ret)
389 return ret;
390
6299f992
CW		 391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
394
395 size = count = mappable_size = mappable_count = 0;
35c20a60 396 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
399
400 size = count = mappable_size = mappable_count = 0;
ca191b13 401 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
404
6299f992 405 size = count = mappable_size = mappable_count = 0;
ca191b13 406 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
409
b7abb714 410 size = count = purgeable_size = purgeable_count = 0;
35c20a60 411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 412 size += obj->base.size, ++count;
b7abb714
CW		 413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
415 }
6c085a72
CW		 416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
417
6299f992 418 size = count = mappable_size = mappable_count = 0;
35c20a60 419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 420 if (obj->fault_mappable) {
f343c5f6 421 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 422 ++count;
423 }
424 if (obj->pin_mappable) {
f343c5f6 425 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 426 ++mappable_count;
427 }
b7abb714
CW		 428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
430 ++purgeable_count;
431 }
6299f992 432 }
b7abb714
CW		 433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
6299f992
CW		 435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 count, size);
439
93d18799 440 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 443
267f0c90 444 seq_putc(m, '\n');
2db8e9d6
CW		 445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
3ec2f427 447 struct task_struct *task;
2db8e9d6
CW		 448
449 memset(&stats, 0, sizeof(stats));
6313c204 450 stats.file_priv = file->driver_priv;
5b5ffff0 451 spin_lock(&file->table_lock);
2db8e9d6 452 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 453 spin_unlock(&file->table_lock);
3ec2f427
TH		 454 /*
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
459 */
460 rcu_read_lock();
461 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 463 task ? task->comm : "<unknown>",
2db8e9d6
CW		 464 stats.count,
465 stats.total,
466 stats.active,
467 stats.inactive,
6313c204 468 stats.global,
c67a17e9 469 stats.shared,
2db8e9d6 470 stats.unbound);
3ec2f427 471 rcu_read_unlock();
2db8e9d6
CW		 472 }
473
73aa808f
CW		 474 mutex_unlock(&dev->struct_mutex);
475
476 return 0;
477}
478
aee56cff 479static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 480{
9f25d007 481 struct drm_info_node *node = m->private;
08c18323 482 struct drm_device *dev = node->minor->dev;
1b50247a 483 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
487 int count, ret;
488
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
490 if (ret)
491 return ret;
492
493 total_obj_size = total_gtt_size = count = 0;
35c20a60 494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 496 continue;
497
267f0c90 498 seq_puts(m, " ");
08c18323 499 describe_obj(m, obj);
267f0c90 500 seq_putc(m, '\n');
08c18323 501 total_obj_size += obj->base.size;
f343c5f6 502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 503 count++;
504 }
505
506 mutex_unlock(&dev->struct_mutex);
507
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
510
511 return 0;
512}
513
4e5359cd
SF		 514static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515{
9f25d007 516 struct drm_info_node *node = m->private;
4e5359cd 517 struct drm_device *dev = node->minor->dev;
d6bbafa1 518 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 519 struct intel_crtc *crtc;
8a270ebf
DV		 520 int ret;
521
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
523 if (ret)
524 return ret;
4e5359cd 525
d3fcc808 526 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 529 struct intel_unpin_work *work;
530
5e2d7afc 531 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 532 work = crtc->unpin_work;
533 if (work == NULL) {
9db4a9c7 534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 535 pipe, plane);
536 } else {
d6bbafa1
CW		 537 u32 addr;
538
e7d841ca 539 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 540 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 541 pipe, plane);
542 } else {
9db4a9c7 543 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 544 pipe, plane);
545 }
d6bbafa1
CW		 546 if (work->flip_queued_ring) {
547 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
548 work->flip_queued_ring->name,
549 work->flip_queued_seqno,
550 dev_priv->next_seqno,
551 work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
552 i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
553 work->flip_queued_seqno));
554 } else
555 seq_printf(m, "Flip not associated with any ring\n");
556 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
557 work->flip_queued_vblank,
558 work->flip_ready_vblank,
559 drm_vblank_count(dev, crtc->pipe));
4e5359cd 560 if (work->enable_stall_check)
267f0c90 561 seq_puts(m, "Stall check enabled, ");
4e5359cd 562 else
267f0c90 563 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 564 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 565
d6bbafa1
CW		 566 if (INTEL_INFO(dev)->gen >= 4)
567 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
568 else
569 addr = I915_READ(DSPADDR(crtc->plane));
570 seq_printf(m, "Current scanout address 0x%08x\n", addr);
571
4e5359cd 572 if (work->pending_flip_obj) {
d6bbafa1
CW		 573 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
574 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 575 }
576 }
5e2d7afc 577 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 578 }
579
8a270ebf
DV		 580 mutex_unlock(&dev->struct_mutex);
581
4e5359cd
SF		 582 return 0;
583}
584
2017263e
BG		 585static int i915_gem_request_info(struct seq_file *m, void *data)
586{
9f25d007 587 struct drm_info_node *node = m->private;
2017263e 588 struct drm_device *dev = node->minor->dev;
e277a1f8 589 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 590 struct intel_engine_cs *ring;
2017263e 591 struct drm_i915_gem_request *gem_request;
a2c7f6fd 592 int ret, count, i;
de227ef0
CW		 593
594 ret = mutex_lock_interruptible(&dev->struct_mutex);
595 if (ret)
596 return ret;
2017263e 597
c2c347a9 598 count = 0;
a2c7f6fd
CW		 599 for_each_ring(ring, dev_priv, i) {
600 if (list_empty(&ring->request_list))
601 continue;
602
603 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 604 list_for_each_entry(gem_request,
a2c7f6fd 605 &ring->request_list,
c2c347a9
CW		 606 list) {
607 seq_printf(m, " %d @ %d\n",
608 gem_request->seqno,
609 (int) (jiffies - gem_request->emitted_jiffies));
610 }
611 count++;
2017263e 612 }
de227ef0
CW		 613 mutex_unlock(&dev->struct_mutex);
614
c2c347a9 615 if (count == 0)
267f0c90 616 seq_puts(m, "No requests\n");
c2c347a9 617
2017263e
BG		 618 return 0;
619}
620
b2223497 621static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 622 struct intel_engine_cs *ring)
b2223497
CW		 623{
624 if (ring->get_seqno) {
43a7b924 625 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 626 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 627 }
628}
629
2017263e
BG		 630static int i915_gem_seqno_info(struct seq_file *m, void *data)
631{
9f25d007 632 struct drm_info_node *node = m->private;
2017263e 633 struct drm_device *dev = node->minor->dev;
e277a1f8 634 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 635 struct intel_engine_cs *ring;
1ec14ad3 636 int ret, i;
de227ef0
CW		 637
638 ret = mutex_lock_interruptible(&dev->struct_mutex);
639 if (ret)
640 return ret;
c8c8fb33 641 intel_runtime_pm_get(dev_priv);
2017263e 642
a2c7f6fd
CW		 643 for_each_ring(ring, dev_priv, i)
644 i915_ring_seqno_info(m, ring);
de227ef0 645
c8c8fb33 646 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 647 mutex_unlock(&dev->struct_mutex);
648
2017263e
BG		 649 return 0;
650}
651
652
653static int i915_interrupt_info(struct seq_file *m, void *data)
654{
9f25d007 655 struct drm_info_node *node = m->private;
2017263e 656 struct drm_device *dev = node->minor->dev;
e277a1f8 657 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 658 struct intel_engine_cs *ring;
9db4a9c7 659 int ret, i, pipe;
de227ef0
CW		 660
661 ret = mutex_lock_interruptible(&dev->struct_mutex);
662 if (ret)
663 return ret;
c8c8fb33 664 intel_runtime_pm_get(dev_priv);
2017263e 665
74e1ca8c 666 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 667 seq_printf(m, "Master Interrupt Control:\t%08x\n",
668 I915_READ(GEN8_MASTER_IRQ));
669
670 seq_printf(m, "Display IER:\t%08x\n",
671 I915_READ(VLV_IER));
672 seq_printf(m, "Display IIR:\t%08x\n",
673 I915_READ(VLV_IIR));
674 seq_printf(m, "Display IIR_RW:\t%08x\n",
675 I915_READ(VLV_IIR_RW));
676 seq_printf(m, "Display IMR:\t%08x\n",
677 I915_READ(VLV_IMR));
055e393f 678 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 679 seq_printf(m, "Pipe %c stat:\t%08x\n",
680 pipe_name(pipe),
681 I915_READ(PIPESTAT(pipe)));
682
683 seq_printf(m, "Port hotplug:\t%08x\n",
684 I915_READ(PORT_HOTPLUG_EN));
685 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
686 I915_READ(VLV_DPFLIPSTAT));
687 seq_printf(m, "DPINVGTT:\t%08x\n",
688 I915_READ(DPINVGTT));
689
690 for (i = 0; i < 4; i++) {
691 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
692 i, I915_READ(GEN8_GT_IMR(i)));
693 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
694 i, I915_READ(GEN8_GT_IIR(i)));
695 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
696 i, I915_READ(GEN8_GT_IER(i)));
697 }
698
699 seq_printf(m, "PCU interrupt mask:\t%08x\n",
700 I915_READ(GEN8_PCU_IMR));
701 seq_printf(m, "PCU interrupt identity:\t%08x\n",
702 I915_READ(GEN8_PCU_IIR));
703 seq_printf(m, "PCU interrupt enable:\t%08x\n",
704 I915_READ(GEN8_PCU_IER));
705 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 706 seq_printf(m, "Master Interrupt Control:\t%08x\n",
707 I915_READ(GEN8_MASTER_IRQ));
708
709 for (i = 0; i < 4; i++) {
710 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
711 i, I915_READ(GEN8_GT_IMR(i)));
712 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
713 i, I915_READ(GEN8_GT_IIR(i)));
714 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
715 i, I915_READ(GEN8_GT_IER(i)));
716 }
717
055e393f 718 for_each_pipe(dev_priv, pipe) {
f458ebbc 719 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 720 POWER_DOMAIN_PIPE(pipe))) {
721 seq_printf(m, "Pipe %c power disabled\n",
722 pipe_name(pipe));
723 continue;
724 }
a123f157 725 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 726 pipe_name(pipe),
727 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 728 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 729 pipe_name(pipe),
730 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 731 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 732 pipe_name(pipe),
733 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 734 }
735
736 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
737 I915_READ(GEN8_DE_PORT_IMR));
738 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
739 I915_READ(GEN8_DE_PORT_IIR));
740 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
741 I915_READ(GEN8_DE_PORT_IER));
742
743 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
744 I915_READ(GEN8_DE_MISC_IMR));
745 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
746 I915_READ(GEN8_DE_MISC_IIR));
747 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
748 I915_READ(GEN8_DE_MISC_IER));
749
750 seq_printf(m, "PCU interrupt mask:\t%08x\n",
751 I915_READ(GEN8_PCU_IMR));
752 seq_printf(m, "PCU interrupt identity:\t%08x\n",
753 I915_READ(GEN8_PCU_IIR));
754 seq_printf(m, "PCU interrupt enable:\t%08x\n",
755 I915_READ(GEN8_PCU_IER));
756 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 757 seq_printf(m, "Display IER:\t%08x\n",
758 I915_READ(VLV_IER));
759 seq_printf(m, "Display IIR:\t%08x\n",
760 I915_READ(VLV_IIR));
761 seq_printf(m, "Display IIR_RW:\t%08x\n",
762 I915_READ(VLV_IIR_RW));
763 seq_printf(m, "Display IMR:\t%08x\n",
764 I915_READ(VLV_IMR));
055e393f 765 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 766 seq_printf(m, "Pipe %c stat:\t%08x\n",
767 pipe_name(pipe),
768 I915_READ(PIPESTAT(pipe)));
769
770 seq_printf(m, "Master IER:\t%08x\n",
771 I915_READ(VLV_MASTER_IER));
772
773 seq_printf(m, "Render IER:\t%08x\n",
774 I915_READ(GTIER));
775 seq_printf(m, "Render IIR:\t%08x\n",
776 I915_READ(GTIIR));
777 seq_printf(m, "Render IMR:\t%08x\n",
778 I915_READ(GTIMR));
779
780 seq_printf(m, "PM IER:\t\t%08x\n",
781 I915_READ(GEN6_PMIER));
782 seq_printf(m, "PM IIR:\t\t%08x\n",
783 I915_READ(GEN6_PMIIR));
784 seq_printf(m, "PM IMR:\t\t%08x\n",
785 I915_READ(GEN6_PMIMR));
786
787 seq_printf(m, "Port hotplug:\t%08x\n",
788 I915_READ(PORT_HOTPLUG_EN));
789 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
790 I915_READ(VLV_DPFLIPSTAT));
791 seq_printf(m, "DPINVGTT:\t%08x\n",
792 I915_READ(DPINVGTT));
793
794 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 795 seq_printf(m, "Interrupt enable: %08x\n",
796 I915_READ(IER));
797 seq_printf(m, "Interrupt identity: %08x\n",
798 I915_READ(IIR));
799 seq_printf(m, "Interrupt mask: %08x\n",
800 I915_READ(IMR));
055e393f 801 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 802 seq_printf(m, "Pipe %c stat: %08x\n",
803 pipe_name(pipe),
804 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 805 } else {
806 seq_printf(m, "North Display Interrupt enable: %08x\n",
807 I915_READ(DEIER));
808 seq_printf(m, "North Display Interrupt identity: %08x\n",
809 I915_READ(DEIIR));
810 seq_printf(m, "North Display Interrupt mask: %08x\n",
811 I915_READ(DEIMR));
812 seq_printf(m, "South Display Interrupt enable: %08x\n",
813 I915_READ(SDEIER));
814 seq_printf(m, "South Display Interrupt identity: %08x\n",
815 I915_READ(SDEIIR));
816 seq_printf(m, "South Display Interrupt mask: %08x\n",
817 I915_READ(SDEIMR));
818 seq_printf(m, "Graphics Interrupt enable: %08x\n",
819 I915_READ(GTIER));
820 seq_printf(m, "Graphics Interrupt identity: %08x\n",
821 I915_READ(GTIIR));
822 seq_printf(m, "Graphics Interrupt mask: %08x\n",
823 I915_READ(GTIMR));
824 }
a2c7f6fd 825 for_each_ring(ring, dev_priv, i) {
a123f157 826 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 827 seq_printf(m,
828 "Graphics Interrupt mask (%s): %08x\n",
829 ring->name, I915_READ_IMR(ring));
9862e600 830 }
a2c7f6fd 831 i915_ring_seqno_info(m, ring);
9862e600 832 }
c8c8fb33 833 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 834 mutex_unlock(&dev->struct_mutex);
835
2017263e
BG		 836 return 0;
837}
838
a6172a80
CW		 839static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
840{
9f25d007 841 struct drm_info_node *node = m->private;
a6172a80 842 struct drm_device *dev = node->minor->dev;
e277a1f8 843 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 844 int i, ret;
845
846 ret = mutex_lock_interruptible(&dev->struct_mutex);
847 if (ret)
848 return ret;
a6172a80
CW		 849
850 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
851 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
852 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 853 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 854
6c085a72
CW		 855 seq_printf(m, "Fence %d, pin count = %d, object = ",
856 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 857 if (obj == NULL)
267f0c90 858 seq_puts(m, "unused");
c2c347a9 859 else
05394f39 860 describe_obj(m, obj);
267f0c90 861 seq_putc(m, '\n');
a6172a80
CW		 862 }
863
05394f39 864 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 865 return 0;
866}
867
2017263e
BG		 868static int i915_hws_info(struct seq_file *m, void *data)
869{
9f25d007 870 struct drm_info_node *node = m->private;
2017263e 871 struct drm_device *dev = node->minor->dev;
e277a1f8 872 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 873 struct intel_engine_cs *ring;
1a240d4d 874 const u32 *hws;
4066c0ae
CW		 875 int i;
876
1ec14ad3 877 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 878 hws = ring->status_page.page_addr;
2017263e
BG		 879 if (hws == NULL)
880 return 0;
881
882 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
883 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
884 i * 4,
885 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
886 }
887 return 0;
888}
889
d5442303
DV		 890static ssize_t
891i915_error_state_write(struct file *filp,
892 const char __user *ubuf,
893 size_t cnt,
894 loff_t *ppos)
895{
edc3d884 896 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 897 struct drm_device *dev = error_priv->dev;
22bcfc6a 898 int ret;
d5442303
DV		 899
900 DRM_DEBUG_DRIVER("Resetting error state\n");
901
22bcfc6a
DV		 902 ret = mutex_lock_interruptible(&dev->struct_mutex);
903 if (ret)
904 return ret;
905
d5442303
DV		 906 i915_destroy_error_state(dev);
907 mutex_unlock(&dev->struct_mutex);
908
909 return cnt;
910}
911
912static int i915_error_state_open(struct inode *inode, struct file *file)
913{
914 struct drm_device *dev = inode->i_private;
d5442303 915 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 916
917 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
918 if (!error_priv)
919 return -ENOMEM;
920
921 error_priv->dev = dev;
922
95d5bfb3 923 i915_error_state_get(dev, error_priv);
d5442303 924
edc3d884
MK		 925 file->private_data = error_priv;
926
927 return 0;
d5442303
DV		 928}
929
930static int i915_error_state_release(struct inode *inode, struct file *file)
931{
edc3d884 932 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 933
95d5bfb3 934 i915_error_state_put(error_priv);
d5442303
DV		 935 kfree(error_priv);
936
edc3d884
MK		 937 return 0;
938}
939
4dc955f7
MK		 940static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
941 size_t count, loff_t *pos)
942{
943 struct i915_error_state_file_priv *error_priv = file->private_data;
944 struct drm_i915_error_state_buf error_str;
945 loff_t tmp_pos = 0;
946 ssize_t ret_count = 0;
947 int ret;
948
0a4cd7c8 949 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 950 if (ret)
951 return ret;
edc3d884 952
fc16b48b 953 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 954 if (ret)
955 goto out;
956
edc3d884
MK		 957 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
958 error_str.buf,
959 error_str.bytes);
960
961 if (ret_count < 0)
962 ret = ret_count;
963 else
964 *pos = error_str.start + ret_count;
965out:
4dc955f7 966 i915_error_state_buf_release(&error_str);
edc3d884 967 return ret ?: ret_count;
d5442303
DV		 968}
969
970static const struct file_operations i915_error_state_fops = {
971 .owner = THIS_MODULE,
972 .open = i915_error_state_open,
edc3d884 973 .read = i915_error_state_read,
d5442303
DV		 974 .write = i915_error_state_write,
975 .llseek = default_llseek,
976 .release = i915_error_state_release,
977};
978
647416f9
KC		 979static int
980i915_next_seqno_get(void *data, u64 *val)
40633219 981{
647416f9 982 struct drm_device *dev = data;
e277a1f8 983 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 984 int ret;
985
986 ret = mutex_lock_interruptible(&dev->struct_mutex);
987 if (ret)
988 return ret;
989
647416f9 990 *val = dev_priv->next_seqno;
40633219
MK		 991 mutex_unlock(&dev->struct_mutex);
992
647416f9 993 return 0;
40633219
MK		 994}
995
647416f9
KC		 996static int
997i915_next_seqno_set(void *data, u64 val)
998{
999 struct drm_device *dev = data;
40633219
MK		 1000 int ret;
1001
40633219
MK		 1002 ret = mutex_lock_interruptible(&dev->struct_mutex);
1003 if (ret)
1004 return ret;
1005
e94fbaa8 1006 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1007 mutex_unlock(&dev->struct_mutex);
1008
647416f9 1009 return ret;
40633219
MK		 1010}
1011
647416f9
KC		 1012DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1013 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1014 "0x%llx\n");
40633219 1015
adb4bd12 1016static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1017{
9f25d007 1018 struct drm_info_node *node = m->private;
f97108d1 1019 struct drm_device *dev = node->minor->dev;
e277a1f8 1020 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1021 int ret = 0;
1022
1023 intel_runtime_pm_get(dev_priv);
3b8d8d91 1024
5c9669ce
TR		 1025 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1026
3b8d8d91
JB		 1027 if (IS_GEN5(dev)) {
1028 u16 rgvswctl = I915_READ16(MEMSWCTL);
1029 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1030
1031 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1032 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1033 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1034 MEMSTAT_VID_SHIFT);
1035 seq_printf(m, "Current P-state: %d\n",
1036 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1037 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1038 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1039 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1040 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1041 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1042 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1043 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1044 u32 rpupei, rpcurup, rpprevup;
1045 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1046 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1047 int max_freq;
1048
1049 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1050 ret = mutex_lock_interruptible(&dev->struct_mutex);
1051 if (ret)
c8c8fb33 1052 goto out;
d1ebd816 1053
c8d9a590 1054 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1055
8e8c06cd
CW		 1056 reqf = I915_READ(GEN6_RPNSWREQ);
1057 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1058 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1059 reqf >>= 24;
1060 else
1061 reqf >>= 25;
1062 reqf *= GT_FREQUENCY_MULTIPLIER;
1063
0d8f9491
CW		 1064 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1065 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1066 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1067
ccab5c82
JB		 1068 rpstat = I915_READ(GEN6_RPSTAT1);
1069 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1070 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1071 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1072 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1073 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1074 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1075 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1076 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1077 else
1078 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1079 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1080
c8d9a590 1081 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1082 mutex_unlock(&dev->struct_mutex);
1083
9dd3c605
PZ		 1084 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1085 pm_ier = I915_READ(GEN6_PMIER);
1086 pm_imr = I915_READ(GEN6_PMIMR);
1087 pm_isr = I915_READ(GEN6_PMISR);
1088 pm_iir = I915_READ(GEN6_PMIIR);
1089 pm_mask = I915_READ(GEN6_PMINTRMSK);
1090 } else {
1091 pm_ier = I915_READ(GEN8_GT_IER(2));
1092 pm_imr = I915_READ(GEN8_GT_IMR(2));
1093 pm_isr = I915_READ(GEN8_GT_ISR(2));
1094 pm_iir = I915_READ(GEN8_GT_IIR(2));
1095 pm_mask = I915_READ(GEN6_PMINTRMSK);
1096 }
0d8f9491 1097 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1098 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1099 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1100 seq_printf(m, "Render p-state ratio: %d\n",
1101 (gt_perf_status & 0xff00) >> 8);
1102 seq_printf(m, "Render p-state VID: %d\n",
1103 gt_perf_status & 0xff);
1104 seq_printf(m, "Render p-state limit: %d\n",
1105 rp_state_limits & 0xff);
0d8f9491
CW		 1106 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1107 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1108 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1109 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1110 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1111 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1112 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1113 GEN6_CURICONT_MASK);
1114 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1115 GEN6_CURBSYTAVG_MASK);
1116 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1117 GEN6_CURBSYTAVG_MASK);
1118 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1119 GEN6_CURIAVG_MASK);
1120 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1121 GEN6_CURBSYTAVG_MASK);
1122 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1123 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1124
1125 max_freq = (rp_state_cap & 0xff0000) >> 16;
1126 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1127 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1128
1129 max_freq = (rp_state_cap & 0xff00) >> 8;
1130 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1131 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1132
1133 max_freq = rp_state_cap & 0xff;
1134 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1135 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1136
1137 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1138 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84 1139 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1140 u32 freq_sts;
0a073b84 1141
259bd5d4 1142 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1143 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1144 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1145 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1146
0a073b84 1147 seq_printf(m, "max GPU freq: %d MHz\n",
b2435c94 1148 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1149
0a073b84 1150 seq_printf(m, "min GPU freq: %d MHz\n",
b2435c94 1151 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045
VS		 1152
1153 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
b2435c94 1154 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1155
1156 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1157 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1158 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1159 } else {
267f0c90 1160 seq_puts(m, "no P-state info available\n");
3b8d8d91 1161 }
f97108d1 1162
c8c8fb33
PZ		 1163out:
1164 intel_runtime_pm_put(dev_priv);
1165 return ret;
f97108d1
JB		 1166}
1167
4d85529d 1168static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1169{
9f25d007 1170 struct drm_info_node *node = m->private;
f97108d1 1171 struct drm_device *dev = node->minor->dev;
e277a1f8 1172 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1173 u32 rgvmodectl, rstdbyctl;
1174 u16 crstandvid;
1175 int ret;
1176
1177 ret = mutex_lock_interruptible(&dev->struct_mutex);
1178 if (ret)
1179 return ret;
c8c8fb33 1180 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1181
1182 rgvmodectl = I915_READ(MEMMODECTL);
1183 rstdbyctl = I915_READ(RSTDBYCTL);
1184 crstandvid = I915_READ16(CRSTANDVID);
1185
c8c8fb33 1186 intel_runtime_pm_put(dev_priv);
616fdb5a 1187 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1188
1189 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1190 "yes" : "no");
1191 seq_printf(m, "Boost freq: %d\n",
1192 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1193 MEMMODE_BOOST_FREQ_SHIFT);
1194 seq_printf(m, "HW control enabled: %s\n",
1195 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1196 seq_printf(m, "SW control enabled: %s\n",
1197 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1198 seq_printf(m, "Gated voltage change: %s\n",
1199 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1200 seq_printf(m, "Starting frequency: P%d\n",
1201 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1202 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1203 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1204 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1205 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1206 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1207 seq_printf(m, "Render standby enabled: %s\n",
1208 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1209 seq_puts(m, "Current RS state: ");
88271da3
JB		 1210 switch (rstdbyctl & RSX_STATUS_MASK) {
1211 case RSX_STATUS_ON:
267f0c90 1212 seq_puts(m, "on\n");
88271da3
JB		 1213 break;
1214 case RSX_STATUS_RC1:
267f0c90 1215 seq_puts(m, "RC1\n");
88271da3
JB		 1216 break;
1217 case RSX_STATUS_RC1E:
267f0c90 1218 seq_puts(m, "RC1E\n");
88271da3
JB		 1219 break;
1220 case RSX_STATUS_RS1:
267f0c90 1221 seq_puts(m, "RS1\n");
88271da3
JB		 1222 break;
1223 case RSX_STATUS_RS2:
267f0c90 1224 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1225 break;
1226 case RSX_STATUS_RS3:
267f0c90 1227 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1228 break;
1229 default:
267f0c90 1230 seq_puts(m, "unknown\n");
88271da3
JB		 1231 break;
1232 }
f97108d1
JB		 1233
1234 return 0;
1235}
1236
669ab5aa
D		 1237static int vlv_drpc_info(struct seq_file *m)
1238{
1239
9f25d007 1240 struct drm_info_node *node = m->private;
669ab5aa
D		 1241 struct drm_device *dev = node->minor->dev;
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 u32 rpmodectl1, rcctl1;
1244 unsigned fw_rendercount = 0, fw_mediacount = 0;
1245
d46c0517
ID		 1246 intel_runtime_pm_get(dev_priv);
1247
669ab5aa
D		 1248 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1249 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1250
d46c0517
ID		 1251 intel_runtime_pm_put(dev_priv);
1252
669ab5aa
D		 1253 seq_printf(m, "Video Turbo Mode: %s\n",
1254 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1255 seq_printf(m, "Turbo enabled: %s\n",
1256 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1257 seq_printf(m, "HW control enabled: %s\n",
1258 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1259 seq_printf(m, "SW control enabled: %s\n",
1260 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1261 GEN6_RP_MEDIA_SW_MODE));
1262 seq_printf(m, "RC6 Enabled: %s\n",
1263 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1264 GEN6_RC_CTL_EI_MODE(1))));
1265 seq_printf(m, "Render Power Well: %s\n",
1266 (I915_READ(VLV_GTLC_PW_STATUS) &
1267 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1268 seq_printf(m, "Media Power Well: %s\n",
1269 (I915_READ(VLV_GTLC_PW_STATUS) &
1270 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1271
9cc19be5
ID		 1272 seq_printf(m, "Render RC6 residency since boot: %u\n",
1273 I915_READ(VLV_GT_RENDER_RC6));
1274 seq_printf(m, "Media RC6 residency since boot: %u\n",
1275 I915_READ(VLV_GT_MEDIA_RC6));
1276
669ab5aa
D		 1277 spin_lock_irq(&dev_priv->uncore.lock);
1278 fw_rendercount = dev_priv->uncore.fw_rendercount;
1279 fw_mediacount = dev_priv->uncore.fw_mediacount;
1280 spin_unlock_irq(&dev_priv->uncore.lock);
1281
1282 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1283 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1284
1285
1286 return 0;
1287}
1288
1289
4d85529d
BW		 1290static int gen6_drpc_info(struct seq_file *m)
1291{
1292
9f25d007 1293 struct drm_info_node *node = m->private;
4d85529d
BW		 1294 struct drm_device *dev = node->minor->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1296 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1297 unsigned forcewake_count;
aee56cff 1298 int count = 0, ret;
4d85529d
BW		 1299
1300 ret = mutex_lock_interruptible(&dev->struct_mutex);
1301 if (ret)
1302 return ret;
c8c8fb33 1303 intel_runtime_pm_get(dev_priv);
4d85529d 1304
907b28c5
CW		 1305 spin_lock_irq(&dev_priv->uncore.lock);
1306 forcewake_count = dev_priv->uncore.forcewake_count;
1307 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1308
1309 if (forcewake_count) {
267f0c90
DL		 1310 seq_puts(m, "RC information inaccurate because somebody "
1311 "holds a forcewake reference \n");
4d85529d
BW		 1312 } else {
1313 /* NB: we cannot use forcewake, else we read the wrong values */
1314 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1315 udelay(10);
1316 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1317 }
1318
1319 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1320 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1321
1322 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1323 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1324 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1325 mutex_lock(&dev_priv->rps.hw_lock);
1326 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1327 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1328
c8c8fb33
PZ		 1329 intel_runtime_pm_put(dev_priv);
1330
4d85529d
BW		 1331 seq_printf(m, "Video Turbo Mode: %s\n",
1332 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1333 seq_printf(m, "HW control enabled: %s\n",
1334 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1335 seq_printf(m, "SW control enabled: %s\n",
1336 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1337 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1338 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1339 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1340 seq_printf(m, "RC6 Enabled: %s\n",
1341 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1342 seq_printf(m, "Deep RC6 Enabled: %s\n",
1343 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1344 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1345 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1346 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1347 switch (gt_core_status & GEN6_RCn_MASK) {
1348 case GEN6_RC0:
1349 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1350 seq_puts(m, "Core Power Down\n");
4d85529d 1351 else
267f0c90 1352 seq_puts(m, "on\n");
4d85529d
BW		 1353 break;
1354 case GEN6_RC3:
267f0c90 1355 seq_puts(m, "RC3\n");
4d85529d
BW		 1356 break;
1357 case GEN6_RC6:
267f0c90 1358 seq_puts(m, "RC6\n");
4d85529d
BW		 1359 break;
1360 case GEN6_RC7:
267f0c90 1361 seq_puts(m, "RC7\n");
4d85529d
BW		 1362 break;
1363 default:
267f0c90 1364 seq_puts(m, "Unknown\n");
4d85529d
BW		 1365 break;
1366 }
1367
1368 seq_printf(m, "Core Power Down: %s\n",
1369 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1370
1371 /* Not exactly sure what this is */
1372 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1373 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1374 seq_printf(m, "RC6 residency since boot: %u\n",
1375 I915_READ(GEN6_GT_GFX_RC6));
1376 seq_printf(m, "RC6+ residency since boot: %u\n",
1377 I915_READ(GEN6_GT_GFX_RC6p));
1378 seq_printf(m, "RC6++ residency since boot: %u\n",
1379 I915_READ(GEN6_GT_GFX_RC6pp));
1380
ecd8faea
BW		 1381 seq_printf(m, "RC6 voltage: %dmV\n",
1382 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1383 seq_printf(m, "RC6+ voltage: %dmV\n",
1384 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1385 seq_printf(m, "RC6++ voltage: %dmV\n",
1386 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1387 return 0;
1388}
1389
1390static int i915_drpc_info(struct seq_file *m, void *unused)
1391{
9f25d007 1392 struct drm_info_node *node = m->private;
4d85529d
BW		 1393 struct drm_device *dev = node->minor->dev;
1394
669ab5aa
D		 1395 if (IS_VALLEYVIEW(dev))
1396 return vlv_drpc_info(m);
ac66cf4b 1397 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1398 return gen6_drpc_info(m);
1399 else
1400 return ironlake_drpc_info(m);
1401}
1402
b5e50c3f
JB		 1403static int i915_fbc_status(struct seq_file *m, void *unused)
1404{
9f25d007 1405 struct drm_info_node *node = m->private;
b5e50c3f 1406 struct drm_device *dev = node->minor->dev;
e277a1f8 1407 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1408
3a77c4c4 1409 if (!HAS_FBC(dev)) {
267f0c90 1410 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1411 return 0;
1412 }
1413
36623ef8
PZ		 1414 intel_runtime_pm_get(dev_priv);
1415
ee5382ae 1416 if (intel_fbc_enabled(dev)) {
267f0c90 1417 seq_puts(m, "FBC enabled\n");
b5e50c3f 1418 } else {
267f0c90 1419 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1420 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1421 case FBC_OK:
1422 seq_puts(m, "FBC actived, but currently disabled in hardware");
1423 break;
1424 case FBC_UNSUPPORTED:
1425 seq_puts(m, "unsupported by this chipset");
1426 break;
bed4a673 1427 case FBC_NO_OUTPUT:
267f0c90 1428 seq_puts(m, "no outputs");
bed4a673 1429 break;
b5e50c3f 1430 case FBC_STOLEN_TOO_SMALL:
267f0c90 1431 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1432 break;
1433 case FBC_UNSUPPORTED_MODE:
267f0c90 1434 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1435 break;
1436 case FBC_MODE_TOO_LARGE:
267f0c90 1437 seq_puts(m, "mode too large");
b5e50c3f
JB		 1438 break;
1439 case FBC_BAD_PLANE:
267f0c90 1440 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1441 break;
1442 case FBC_NOT_TILED:
267f0c90 1443 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1444 break;
9c928d16 1445 case FBC_MULTIPLE_PIPES:
267f0c90 1446 seq_puts(m, "multiple pipes are enabled");
9c928d16 1447 break;
c1a9f047 1448 case FBC_MODULE_PARAM:
267f0c90 1449 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1450 break;
8a5729a3 1451 case FBC_CHIP_DEFAULT:
267f0c90 1452 seq_puts(m, "disabled per chip default");
8a5729a3 1453 break;
b5e50c3f 1454 default:
267f0c90 1455 seq_puts(m, "unknown reason");
b5e50c3f 1456 }
267f0c90 1457 seq_putc(m, '\n');
b5e50c3f 1458 }
36623ef8
PZ		 1459
1460 intel_runtime_pm_put(dev_priv);
1461
b5e50c3f
JB		 1462 return 0;
1463}
1464
da46f936
RV		 1465static int i915_fbc_fc_get(void *data, u64 *val)
1466{
1467 struct drm_device *dev = data;
1468 struct drm_i915_private *dev_priv = dev->dev_private;
1469
1470 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1471 return -ENODEV;
1472
1473 drm_modeset_lock_all(dev);
1474 *val = dev_priv->fbc.false_color;
1475 drm_modeset_unlock_all(dev);
1476
1477 return 0;
1478}
1479
1480static int i915_fbc_fc_set(void *data, u64 val)
1481{
1482 struct drm_device *dev = data;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 u32 reg;
1485
1486 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1487 return -ENODEV;
1488
1489 drm_modeset_lock_all(dev);
1490
1491 reg = I915_READ(ILK_DPFC_CONTROL);
1492 dev_priv->fbc.false_color = val;
1493
1494 I915_WRITE(ILK_DPFC_CONTROL, val ?
1495 (reg | FBC_CTL_FALSE_COLOR) :
1496 (reg & ~FBC_CTL_FALSE_COLOR));
1497
1498 drm_modeset_unlock_all(dev);
1499 return 0;
1500}
1501
1502DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1503 i915_fbc_fc_get, i915_fbc_fc_set,
1504 "%llu\n");
1505
92d44621
PZ		 1506static int i915_ips_status(struct seq_file *m, void *unused)
1507{
9f25d007 1508 struct drm_info_node *node = m->private;
92d44621
PZ		 1509 struct drm_device *dev = node->minor->dev;
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511
f5adf94e 1512 if (!HAS_IPS(dev)) {
92d44621
PZ		 1513 seq_puts(m, "not supported\n");
1514 return 0;
1515 }
1516
36623ef8
PZ		 1517 intel_runtime_pm_get(dev_priv);
1518
0eaa53f0
RV		 1519 seq_printf(m, "Enabled by kernel parameter: %s\n",
1520 yesno(i915.enable_ips));
1521
1522 if (INTEL_INFO(dev)->gen >= 8) {
1523 seq_puts(m, "Currently: unknown\n");
1524 } else {
1525 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1526 seq_puts(m, "Currently: enabled\n");
1527 else
1528 seq_puts(m, "Currently: disabled\n");
1529 }
92d44621 1530
36623ef8
PZ		 1531 intel_runtime_pm_put(dev_priv);
1532
92d44621
PZ		 1533 return 0;
1534}
1535
4a9bef37
JB		 1536static int i915_sr_status(struct seq_file *m, void *unused)
1537{
9f25d007 1538 struct drm_info_node *node = m->private;
4a9bef37 1539 struct drm_device *dev = node->minor->dev;
e277a1f8 1540 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1541 bool sr_enabled = false;
1542
36623ef8
PZ		 1543 intel_runtime_pm_get(dev_priv);
1544
1398261a 1545 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1546 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1547 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1548 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1549 else if (IS_I915GM(dev))
1550 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1551 else if (IS_PINEVIEW(dev))
1552 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1553
36623ef8
PZ		 1554 intel_runtime_pm_put(dev_priv);
1555
5ba2aaaa
CW		 1556 seq_printf(m, "self-refresh: %s\n",
1557 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1558
1559 return 0;
1560}
1561
7648fa99
JB		 1562static int i915_emon_status(struct seq_file *m, void *unused)
1563{
9f25d007 1564 struct drm_info_node *node = m->private;
7648fa99 1565 struct drm_device *dev = node->minor->dev;
e277a1f8 1566 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1567 unsigned long temp, chipset, gfx;
de227ef0
CW		 1568 int ret;
1569
582be6b4
CW		 1570 if (!IS_GEN5(dev))
1571 return -ENODEV;
1572
de227ef0
CW		 1573 ret = mutex_lock_interruptible(&dev->struct_mutex);
1574 if (ret)
1575 return ret;
7648fa99
JB		 1576
1577 temp = i915_mch_val(dev_priv);
1578 chipset = i915_chipset_val(dev_priv);
1579 gfx = i915_gfx_val(dev_priv);
de227ef0 1580 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1581
1582 seq_printf(m, "GMCH temp: %ld\n", temp);
1583 seq_printf(m, "Chipset power: %ld\n", chipset);
1584 seq_printf(m, "GFX power: %ld\n", gfx);
1585 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1586
1587 return 0;
1588}
1589
23b2f8bb
JB		 1590static int i915_ring_freq_table(struct seq_file *m, void *unused)
1591{
9f25d007 1592 struct drm_info_node *node = m->private;
23b2f8bb 1593 struct drm_device *dev = node->minor->dev;
e277a1f8 1594 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1595 int ret = 0;
23b2f8bb
JB		 1596 int gpu_freq, ia_freq;
1597
1c70c0ce 1598 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1599 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1600 return 0;
1601 }
1602
5bfa0199
PZ		 1603 intel_runtime_pm_get(dev_priv);
1604
5c9669ce
TR		 1605 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1606
4fc688ce 1607 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1608 if (ret)
5bfa0199 1609 goto out;
23b2f8bb 1610
267f0c90 1611 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1612
b39fb297
BW		 1613 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1614 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1615 gpu_freq++) {
42c0526c
BW		 1616 ia_freq = gpu_freq;
1617 sandybridge_pcode_read(dev_priv,
1618 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1619 &ia_freq);
3ebecd07
CW		 1620 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1621 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1622 ((ia_freq >> 0) & 0xff) * 100,
1623 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1624 }
1625
4fc688ce 1626 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1627
5bfa0199
PZ		 1628out:
1629 intel_runtime_pm_put(dev_priv);
1630 return ret;
23b2f8bb
JB		 1631}
1632
44834a67
CW		 1633static int i915_opregion(struct seq_file *m, void *unused)
1634{
9f25d007 1635 struct drm_info_node *node = m->private;
44834a67 1636 struct drm_device *dev = node->minor->dev;
e277a1f8 1637 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1638 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1639 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1640 int ret;
1641
0d38f009
DV		 1642 if (data == NULL)
1643 return -ENOMEM;
1644
44834a67
CW		 1645 ret = mutex_lock_interruptible(&dev->struct_mutex);
1646 if (ret)
0d38f009 1647 goto out;
44834a67 1648
0d38f009
DV		 1649 if (opregion->header) {
1650 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1651 seq_write(m, data, OPREGION_SIZE);
1652 }
44834a67
CW		 1653
1654 mutex_unlock(&dev->struct_mutex);
1655
0d38f009
DV		 1656out:
1657 kfree(data);
44834a67
CW		 1658 return 0;
1659}
1660
37811fcc
CW		 1661static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1662{
9f25d007 1663 struct drm_info_node *node = m->private;
37811fcc 1664 struct drm_device *dev = node->minor->dev;
4520f53a 1665 struct intel_fbdev *ifbdev = NULL;
37811fcc 1666 struct intel_framebuffer *fb;
37811fcc 1667
4520f53a
DV		 1668#ifdef CONFIG_DRM_I915_FBDEV
1669 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1670
1671 ifbdev = dev_priv->fbdev;
1672 fb = to_intel_framebuffer(ifbdev->helper.fb);
1673
623f9783 1674 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1675 fb->base.width,
1676 fb->base.height,
1677 fb->base.depth,
623f9783
DV		 1678 fb->base.bits_per_pixel,
1679 atomic_read(&fb->base.refcount.refcount));
05394f39 1680 describe_obj(m, fb->obj);
267f0c90 1681 seq_putc(m, '\n');
4520f53a 1682#endif
37811fcc 1683
4b096ac1 1684 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1685 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1686 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1687 continue;
1688
623f9783 1689 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1690 fb->base.width,
1691 fb->base.height,
1692 fb->base.depth,
623f9783
DV		 1693 fb->base.bits_per_pixel,
1694 atomic_read(&fb->base.refcount.refcount));
05394f39 1695 describe_obj(m, fb->obj);
267f0c90 1696 seq_putc(m, '\n');
37811fcc 1697 }
4b096ac1 1698 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1699
1700 return 0;
1701}
1702
c9fe99bd
OM		 1703static void describe_ctx_ringbuf(struct seq_file *m,
1704 struct intel_ringbuffer *ringbuf)
1705{
1706 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1707 ringbuf->space, ringbuf->head, ringbuf->tail,
1708 ringbuf->last_retired_head);
1709}
1710
e76d3630
BW		 1711static int i915_context_status(struct seq_file *m, void *unused)
1712{
9f25d007 1713 struct drm_info_node *node = m->private;
e76d3630 1714 struct drm_device *dev = node->minor->dev;
e277a1f8 1715 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1716 struct intel_engine_cs *ring;
273497e5 1717 struct intel_context *ctx;
a168c293 1718 int ret, i;
e76d3630 1719
f3d28878 1720 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1721 if (ret)
1722 return ret;
1723
3e373948 1724 if (dev_priv->ips.pwrctx) {
267f0c90 1725 seq_puts(m, "power context ");
3e373948 1726 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1727 seq_putc(m, '\n');
dc501fbc 1728 }
e76d3630 1729
3e373948 1730 if (dev_priv->ips.renderctx) {
267f0c90 1731 seq_puts(m, "render context ");
3e373948 1732 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1733 seq_putc(m, '\n');
dc501fbc 1734 }
e76d3630 1735
a33afea5 1736 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1737 if (!i915.enable_execlists &&
1738 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1739 continue;
1740
a33afea5 1741 seq_puts(m, "HW context ");
3ccfd19d 1742 describe_ctx(m, ctx);
c9fe99bd 1743 for_each_ring(ring, dev_priv, i) {
a33afea5 1744 if (ring->default_context == ctx)
c9fe99bd
OM		 1745 seq_printf(m, "(default context %s) ",
1746 ring->name);
1747 }
1748
1749 if (i915.enable_execlists) {
1750 seq_putc(m, '\n');
1751 for_each_ring(ring, dev_priv, i) {
1752 struct drm_i915_gem_object *ctx_obj =
1753 ctx->engine[i].state;
1754 struct intel_ringbuffer *ringbuf =
1755 ctx->engine[i].ringbuf;
1756
1757 seq_printf(m, "%s: ", ring->name);
1758 if (ctx_obj)
1759 describe_obj(m, ctx_obj);
1760 if (ringbuf)
1761 describe_ctx_ringbuf(m, ringbuf);
1762 seq_putc(m, '\n');
1763 }
1764 } else {
1765 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1766 }
a33afea5 1767
a33afea5 1768 seq_putc(m, '\n');
a168c293
BW		 1769 }
1770
f3d28878 1771 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1772
1773 return 0;
1774}
1775
c0ab1ae9
BW		 1776static int i915_dump_lrc(struct seq_file *m, void *unused)
1777{
1778 struct drm_info_node *node = (struct drm_info_node *) m->private;
1779 struct drm_device *dev = node->minor->dev;
1780 struct drm_i915_private *dev_priv = dev->dev_private;
1781 struct intel_engine_cs *ring;
1782 struct intel_context *ctx;
1783 int ret, i;
1784
1785 if (!i915.enable_execlists) {
1786 seq_printf(m, "Logical Ring Contexts are disabled\n");
1787 return 0;
1788 }
1789
1790 ret = mutex_lock_interruptible(&dev->struct_mutex);
1791 if (ret)
1792 return ret;
1793
1794 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1795 for_each_ring(ring, dev_priv, i) {
1796 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1797
1798 if (ring->default_context == ctx)
1799 continue;
1800
1801 if (ctx_obj) {
dcb4c12a
OM		 1802 struct page *page;
1803 uint32_t *reg_state;
c0ab1ae9
BW		 1804 int j;
1805
dcb4c12a
OM		 1806 i915_gem_obj_ggtt_pin(ctx_obj,
1807 GEN8_LR_CONTEXT_ALIGN, 0);
1808
1809 page = i915_gem_object_get_page(ctx_obj, 1);
1810 reg_state = kmap_atomic(page);
1811
c0ab1ae9
BW		 1812 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1813 intel_execlists_ctx_id(ctx_obj));
1814
1815 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1816 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1817 i915_gem_obj_ggtt_offset(ctx_obj) + 4096 + (j * 4),
1818 reg_state[j], reg_state[j + 1],
1819 reg_state[j + 2], reg_state[j + 3]);
1820 }
1821 kunmap_atomic(reg_state);
1822
dcb4c12a
OM		 1823 i915_gem_object_ggtt_unpin(ctx_obj);
1824
c0ab1ae9
BW		 1825 seq_putc(m, '\n');
1826 }
1827 }
1828 }
1829
1830 mutex_unlock(&dev->struct_mutex);
1831
1832 return 0;
1833}
1834
4ba70e44
OM		 1835static int i915_execlists(struct seq_file *m, void *data)
1836{
1837 struct drm_info_node *node = (struct drm_info_node *)m->private;
1838 struct drm_device *dev = node->minor->dev;
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840 struct intel_engine_cs *ring;
1841 u32 status_pointer;
1842 u8 read_pointer;
1843 u8 write_pointer;
1844 u32 status;
1845 u32 ctx_id;
1846 struct list_head *cursor;
1847 int ring_id, i;
1848 int ret;
1849
1850 if (!i915.enable_execlists) {
1851 seq_puts(m, "Logical Ring Contexts are disabled\n");
1852 return 0;
1853 }
1854
1855 ret = mutex_lock_interruptible(&dev->struct_mutex);
1856 if (ret)
1857 return ret;
1858
fc0412ec
MT		 1859 intel_runtime_pm_get(dev_priv);
1860
4ba70e44
OM		 1861 for_each_ring(ring, dev_priv, ring_id) {
1862 struct intel_ctx_submit_request *head_req = NULL;
1863 int count = 0;
1864 unsigned long flags;
1865
1866 seq_printf(m, "%s\n", ring->name);
1867
1868 status = I915_READ(RING_EXECLIST_STATUS(ring));
1869 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1870 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1871 status, ctx_id);
1872
1873 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1874 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1875
1876 read_pointer = ring->next_context_status_buffer;
1877 write_pointer = status_pointer & 0x07;
1878 if (read_pointer > write_pointer)
1879 write_pointer += 6;
1880 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1881 read_pointer, write_pointer);
1882
1883 for (i = 0; i < 6; i++) {
1884 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1885 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1886
1887 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1888 i, status, ctx_id);
1889 }
1890
1891 spin_lock_irqsave(&ring->execlist_lock, flags);
1892 list_for_each(cursor, &ring->execlist_queue)
1893 count++;
1894 head_req = list_first_entry_or_null(&ring->execlist_queue,
1895 struct intel_ctx_submit_request, execlist_link);
1896 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1897
1898 seq_printf(m, "\t%d requests in queue\n", count);
1899 if (head_req) {
1900 struct drm_i915_gem_object *ctx_obj;
1901
1902 ctx_obj = head_req->ctx->engine[ring_id].state;
1903 seq_printf(m, "\tHead request id: %u\n",
1904 intel_execlists_ctx_id(ctx_obj));
1905 seq_printf(m, "\tHead request tail: %u\n",
1906 head_req->tail);
1907 }
1908
1909 seq_putc(m, '\n');
1910 }
1911
fc0412ec 1912 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 1913 mutex_unlock(&dev->struct_mutex);
1914
1915 return 0;
1916}
1917
6d794d42
BW		 1918static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1919{
9f25d007 1920 struct drm_info_node *node = m->private;
6d794d42
BW		 1921 struct drm_device *dev = node->minor->dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1923 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1924
907b28c5 1925 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1926 if (IS_VALLEYVIEW(dev)) {
1927 fw_rendercount = dev_priv->uncore.fw_rendercount;
1928 fw_mediacount = dev_priv->uncore.fw_mediacount;
1929 } else
1930 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1931 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1932
43709ba0
D		 1933 if (IS_VALLEYVIEW(dev)) {
1934 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1935 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1936 } else
1937 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1938
1939 return 0;
1940}
1941
ea16a3cd
DV		 1942static const char *swizzle_string(unsigned swizzle)
1943{
aee56cff 1944 switch (swizzle) {
ea16a3cd
DV		 1945 case I915_BIT_6_SWIZZLE_NONE:
1946 return "none";
1947 case I915_BIT_6_SWIZZLE_9:
1948 return "bit9";
1949 case I915_BIT_6_SWIZZLE_9_10:
1950 return "bit9/bit10";
1951 case I915_BIT_6_SWIZZLE_9_11:
1952 return "bit9/bit11";
1953 case I915_BIT_6_SWIZZLE_9_10_11:
1954 return "bit9/bit10/bit11";
1955 case I915_BIT_6_SWIZZLE_9_17:
1956 return "bit9/bit17";
1957 case I915_BIT_6_SWIZZLE_9_10_17:
1958 return "bit9/bit10/bit17";
1959 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1960 return "unknown";
ea16a3cd
DV		 1961 }
1962
1963 return "bug";
1964}
1965
1966static int i915_swizzle_info(struct seq_file *m, void *data)
1967{
9f25d007 1968 struct drm_info_node *node = m->private;
ea16a3cd
DV		 1969 struct drm_device *dev = node->minor->dev;
1970 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1971 int ret;
1972
1973 ret = mutex_lock_interruptible(&dev->struct_mutex);
1974 if (ret)
1975 return ret;
c8c8fb33 1976 intel_runtime_pm_get(dev_priv);
ea16a3cd 1977
ea16a3cd
DV		 1978 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1979 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1980 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1981 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1982
1983 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1984 seq_printf(m, "DDC = 0x%08x\n",
1985 I915_READ(DCC));
1986 seq_printf(m, "C0DRB3 = 0x%04x\n",
1987 I915_READ16(C0DRB3));
1988 seq_printf(m, "C1DRB3 = 0x%04x\n",
1989 I915_READ16(C1DRB3));
9d3203e1 1990 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1991 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1992 I915_READ(MAD_DIMM_C0));
1993 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1994 I915_READ(MAD_DIMM_C1));
1995 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1996 I915_READ(MAD_DIMM_C2));
1997 seq_printf(m, "TILECTL = 0x%08x\n",
1998 I915_READ(TILECTL));
5907f5fb 1999 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2000 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2001 I915_READ(GAMTARBMODE));
2002 else
2003 seq_printf(m, "ARB_MODE = 0x%08x\n",
2004 I915_READ(ARB_MODE));
3fa7d235
DV		 2005 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2006 I915_READ(DISP_ARB_CTL));
ea16a3cd 2007 }
c8c8fb33 2008 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2009 mutex_unlock(&dev->struct_mutex);
2010
2011 return 0;
2012}
2013
1c60fef5
BW		 2014static int per_file_ctx(int id, void *ptr, void *data)
2015{
273497e5 2016 struct intel_context *ctx = ptr;
1c60fef5 2017 struct seq_file *m = data;
ae6c4806
DV		 2018 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2019
2020 if (!ppgtt) {
2021 seq_printf(m, " no ppgtt for context %d\n",
2022 ctx->user_handle);
2023 return 0;
2024 }
1c60fef5 2025
f83d6518
OM		 2026 if (i915_gem_context_is_default(ctx))
2027 seq_puts(m, " default context:\n");
2028 else
821d66dd 2029 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2030 ppgtt->debug_dump(ppgtt, m);
2031
2032 return 0;
2033}
2034
77df6772 2035static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2036{
3cf17fc5 2037 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2038 struct intel_engine_cs *ring;
77df6772
BW		 2039 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2040 int unused, i;
3cf17fc5 2041
77df6772
BW		 2042 if (!ppgtt)
2043 return;
2044
2045 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2046 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2047 for_each_ring(ring, dev_priv, unused) {
2048 seq_printf(m, "%s\n", ring->name);
2049 for (i = 0; i < 4; i++) {
2050 u32 offset = 0x270 + i * 8;
2051 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2052 pdp <<= 32;
2053 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2054 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2055 }
2056 }
2057}
2058
2059static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2060{
2061 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2062 struct intel_engine_cs *ring;
1c60fef5 2063 struct drm_file *file;
77df6772 2064 int i;
3cf17fc5 2065
3cf17fc5
DV		 2066 if (INTEL_INFO(dev)->gen == 6)
2067 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2068
a2c7f6fd 2069 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2070 seq_printf(m, "%s\n", ring->name);
2071 if (INTEL_INFO(dev)->gen == 7)
2072 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2073 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2074 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2075 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2076 }
2077 if (dev_priv->mm.aliasing_ppgtt) {
2078 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2079
267f0c90 2080 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 2081 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 2082
87d60b63 2083 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2084 }
1c60fef5
BW		 2085
2086 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2087 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2088
1c60fef5
BW		 2089 seq_printf(m, "proc: %s\n",
2090 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2091 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2092 }
2093 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2094}
2095
2096static int i915_ppgtt_info(struct seq_file *m, void *data)
2097{
9f25d007 2098 struct drm_info_node *node = m->private;
77df6772 2099 struct drm_device *dev = node->minor->dev;
c8c8fb33 2100 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2101
2102 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2103 if (ret)
2104 return ret;
c8c8fb33 2105 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2106
2107 if (INTEL_INFO(dev)->gen >= 8)
2108 gen8_ppgtt_info(m, dev);
2109 else if (INTEL_INFO(dev)->gen >= 6)
2110 gen6_ppgtt_info(m, dev);
2111
c8c8fb33 2112 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2113 mutex_unlock(&dev->struct_mutex);
2114
2115 return 0;
2116}
2117
63573eb7
BW		 2118static int i915_llc(struct seq_file *m, void *data)
2119{
9f25d007 2120 struct drm_info_node *node = m->private;
63573eb7
BW		 2121 struct drm_device *dev = node->minor->dev;
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123
2124 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2125 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2126 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2127
2128 return 0;
2129}
2130
e91fd8c6
RV		 2131static int i915_edp_psr_status(struct seq_file *m, void *data)
2132{
2133 struct drm_info_node *node = m->private;
2134 struct drm_device *dev = node->minor->dev;
2135 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 2136 u32 psrperf = 0;
2137 bool enabled = false;
e91fd8c6 2138
c8c8fb33
PZ		 2139 intel_runtime_pm_get(dev_priv);
2140
fa128fa6 2141 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2142 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2143 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2144 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2145 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2146 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2147 dev_priv->psr.busy_frontbuffer_bits);
2148 seq_printf(m, "Re-enable work scheduled: %s\n",
2149 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2150
a031d709
RV		 2151 enabled = HAS_PSR(dev) &&
2152 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
5755c78f 2153 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
e91fd8c6 2154
a031d709
RV		 2155 if (HAS_PSR(dev))
2156 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2157 EDP_PSR_PERF_CNT_MASK;
2158 seq_printf(m, "Performance_Counter: %u\n", psrperf);
fa128fa6 2159 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2160
c8c8fb33 2161 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2162 return 0;
2163}
2164
d2e216d0
RV		 2165static int i915_sink_crc(struct seq_file *m, void *data)
2166{
2167 struct drm_info_node *node = m->private;
2168 struct drm_device *dev = node->minor->dev;
2169 struct intel_encoder *encoder;
2170 struct intel_connector *connector;
2171 struct intel_dp *intel_dp = NULL;
2172 int ret;
2173 u8 crc[6];
2174
2175 drm_modeset_lock_all(dev);
2176 list_for_each_entry(connector, &dev->mode_config.connector_list,
2177 base.head) {
2178
2179 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2180 continue;
2181
b6ae3c7c
PZ		 2182 if (!connector->base.encoder)
2183 continue;
2184
d2e216d0
RV		 2185 encoder = to_intel_encoder(connector->base.encoder);
2186 if (encoder->type != INTEL_OUTPUT_EDP)
2187 continue;
2188
2189 intel_dp = enc_to_intel_dp(&encoder->base);
2190
2191 ret = intel_dp_sink_crc(intel_dp, crc);
2192 if (ret)
2193 goto out;
2194
2195 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2196 crc[0], crc[1], crc[2],
2197 crc[3], crc[4], crc[5]);
2198 goto out;
2199 }
2200 ret = -ENODEV;
2201out:
2202 drm_modeset_unlock_all(dev);
2203 return ret;
2204}
2205
ec013e7f
JB		 2206static int i915_energy_uJ(struct seq_file *m, void *data)
2207{
2208 struct drm_info_node *node = m->private;
2209 struct drm_device *dev = node->minor->dev;
2210 struct drm_i915_private *dev_priv = dev->dev_private;
2211 u64 power;
2212 u32 units;
2213
2214 if (INTEL_INFO(dev)->gen < 6)
2215 return -ENODEV;
2216
36623ef8
PZ		 2217 intel_runtime_pm_get(dev_priv);
2218
ec013e7f
JB		 2219 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2220 power = (power & 0x1f00) >> 8;
2221 units = 1000000 / (1 << power); /* convert to uJ */
2222 power = I915_READ(MCH_SECP_NRG_STTS);
2223 power *= units;
2224
36623ef8
PZ		 2225 intel_runtime_pm_put(dev_priv);
2226
ec013e7f 2227 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2228
2229 return 0;
2230}
2231
2232static int i915_pc8_status(struct seq_file *m, void *unused)
2233{
9f25d007 2234 struct drm_info_node *node = m->private;
371db66a
PZ		 2235 struct drm_device *dev = node->minor->dev;
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2237
85b8d5c2 2238 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2239 seq_puts(m, "not supported\n");
2240 return 0;
2241 }
2242
86c4ec0d 2243 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2244 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2245 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2246
ec013e7f
JB		 2247 return 0;
2248}
2249
1da51581
ID		 2250static const char *power_domain_str(enum intel_display_power_domain domain)
2251{
2252 switch (domain) {
2253 case POWER_DOMAIN_PIPE_A:
2254 return "PIPE_A";
2255 case POWER_DOMAIN_PIPE_B:
2256 return "PIPE_B";
2257 case POWER_DOMAIN_PIPE_C:
2258 return "PIPE_C";
2259 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2260 return "PIPE_A_PANEL_FITTER";
2261 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2262 return "PIPE_B_PANEL_FITTER";
2263 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2264 return "PIPE_C_PANEL_FITTER";
2265 case POWER_DOMAIN_TRANSCODER_A:
2266 return "TRANSCODER_A";
2267 case POWER_DOMAIN_TRANSCODER_B:
2268 return "TRANSCODER_B";
2269 case POWER_DOMAIN_TRANSCODER_C:
2270 return "TRANSCODER_C";
2271 case POWER_DOMAIN_TRANSCODER_EDP:
2272 return "TRANSCODER_EDP";
319be8ae
ID		 2273 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2274 return "PORT_DDI_A_2_LANES";
2275 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2276 return "PORT_DDI_A_4_LANES";
2277 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2278 return "PORT_DDI_B_2_LANES";
2279 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2280 return "PORT_DDI_B_4_LANES";
2281 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2282 return "PORT_DDI_C_2_LANES";
2283 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2284 return "PORT_DDI_C_4_LANES";
2285 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2286 return "PORT_DDI_D_2_LANES";
2287 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2288 return "PORT_DDI_D_4_LANES";
2289 case POWER_DOMAIN_PORT_DSI:
2290 return "PORT_DSI";
2291 case POWER_DOMAIN_PORT_CRT:
2292 return "PORT_CRT";
2293 case POWER_DOMAIN_PORT_OTHER:
2294 return "PORT_OTHER";
1da51581
ID		 2295 case POWER_DOMAIN_VGA:
2296 return "VGA";
2297 case POWER_DOMAIN_AUDIO:
2298 return "AUDIO";
bd2bb1b9
PZ		 2299 case POWER_DOMAIN_PLLS:
2300 return "PLLS";
1da51581
ID		 2301 case POWER_DOMAIN_INIT:
2302 return "INIT";
2303 default:
2304 WARN_ON(1);
2305 return "?";
2306 }
2307}
2308
2309static int i915_power_domain_info(struct seq_file *m, void *unused)
2310{
9f25d007 2311 struct drm_info_node *node = m->private;
1da51581
ID		 2312 struct drm_device *dev = node->minor->dev;
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2315 int i;
2316
2317 mutex_lock(&power_domains->lock);
2318
2319 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2320 for (i = 0; i < power_domains->power_well_count; i++) {
2321 struct i915_power_well *power_well;
2322 enum intel_display_power_domain power_domain;
2323
2324 power_well = &power_domains->power_wells[i];
2325 seq_printf(m, "%-25s %d\n", power_well->name,
2326 power_well->count);
2327
2328 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2329 power_domain++) {
2330 if (!(BIT(power_domain) & power_well->domains))
2331 continue;
2332
2333 seq_printf(m, " %-23s %d\n",
2334 power_domain_str(power_domain),
2335 power_domains->domain_use_count[power_domain]);
2336 }
2337 }
2338
2339 mutex_unlock(&power_domains->lock);
2340
2341 return 0;
2342}
2343
53f5e3ca
JB		 2344static void intel_seq_print_mode(struct seq_file *m, int tabs,
2345 struct drm_display_mode *mode)
2346{
2347 int i;
2348
2349 for (i = 0; i < tabs; i++)
2350 seq_putc(m, '\t');
2351
2352 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2353 mode->base.id, mode->name,
2354 mode->vrefresh, mode->clock,
2355 mode->hdisplay, mode->hsync_start,
2356 mode->hsync_end, mode->htotal,
2357 mode->vdisplay, mode->vsync_start,
2358 mode->vsync_end, mode->vtotal,
2359 mode->type, mode->flags);
2360}
2361
2362static void intel_encoder_info(struct seq_file *m,
2363 struct intel_crtc *intel_crtc,
2364 struct intel_encoder *intel_encoder)
2365{
9f25d007 2366 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2367 struct drm_device *dev = node->minor->dev;
2368 struct drm_crtc *crtc = &intel_crtc->base;
2369 struct intel_connector *intel_connector;
2370 struct drm_encoder *encoder;
2371
2372 encoder = &intel_encoder->base;
2373 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2374 encoder->base.id, encoder->name);
53f5e3ca
JB		 2375 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2376 struct drm_connector *connector = &intel_connector->base;
2377 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2378 connector->base.id,
c23cc417 2379 connector->name,
53f5e3ca
JB		 2380 drm_get_connector_status_name(connector->status));
2381 if (connector->status == connector_status_connected) {
2382 struct drm_display_mode *mode = &crtc->mode;
2383 seq_printf(m, ", mode:\n");
2384 intel_seq_print_mode(m, 2, mode);
2385 } else {
2386 seq_putc(m, '\n');
2387 }
2388 }
2389}
2390
2391static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2392{
9f25d007 2393 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2394 struct drm_device *dev = node->minor->dev;
2395 struct drm_crtc *crtc = &intel_crtc->base;
2396 struct intel_encoder *intel_encoder;
2397
5aa8a937
MR		 2398 if (crtc->primary->fb)
2399 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2400 crtc->primary->fb->base.id, crtc->x, crtc->y,
2401 crtc->primary->fb->width, crtc->primary->fb->height);
2402 else
2403 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2404 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2405 intel_encoder_info(m, intel_crtc, intel_encoder);
2406}
2407
2408static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2409{
2410 struct drm_display_mode *mode = panel->fixed_mode;
2411
2412 seq_printf(m, "\tfixed mode:\n");
2413 intel_seq_print_mode(m, 2, mode);
2414}
2415
2416static void intel_dp_info(struct seq_file *m,
2417 struct intel_connector *intel_connector)
2418{
2419 struct intel_encoder *intel_encoder = intel_connector->encoder;
2420 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2421
2422 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2423 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2424 "no");
2425 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2426 intel_panel_info(m, &intel_connector->panel);
2427}
2428
2429static void intel_hdmi_info(struct seq_file *m,
2430 struct intel_connector *intel_connector)
2431{
2432 struct intel_encoder *intel_encoder = intel_connector->encoder;
2433 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2434
2435 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2436 "no");
2437}
2438
2439static void intel_lvds_info(struct seq_file *m,
2440 struct intel_connector *intel_connector)
2441{
2442 intel_panel_info(m, &intel_connector->panel);
2443}
2444
2445static void intel_connector_info(struct seq_file *m,
2446 struct drm_connector *connector)
2447{
2448 struct intel_connector *intel_connector = to_intel_connector(connector);
2449 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2450 struct drm_display_mode *mode;
53f5e3ca
JB		 2451
2452 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2453 connector->base.id, connector->name,
53f5e3ca
JB		 2454 drm_get_connector_status_name(connector->status));
2455 if (connector->status == connector_status_connected) {
2456 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2457 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2458 connector->display_info.width_mm,
2459 connector->display_info.height_mm);
2460 seq_printf(m, "\tsubpixel order: %s\n",
2461 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2462 seq_printf(m, "\tCEA rev: %d\n",
2463 connector->display_info.cea_rev);
2464 }
36cd7444
DA		 2465 if (intel_encoder) {
2466 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2467 intel_encoder->type == INTEL_OUTPUT_EDP)
2468 intel_dp_info(m, intel_connector);
2469 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2470 intel_hdmi_info(m, intel_connector);
2471 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2472 intel_lvds_info(m, intel_connector);
2473 }
53f5e3ca 2474
f103fc7d
JB		 2475 seq_printf(m, "\tmodes:\n");
2476 list_for_each_entry(mode, &connector->modes, head)
2477 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2478}
2479
065f2ec2
CW		 2480static bool cursor_active(struct drm_device *dev, int pipe)
2481{
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2483 u32 state;
2484
2485 if (IS_845G(dev) || IS_I865G(dev))
2486 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2487 else
5efb3e28 2488 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2489
2490 return state;
2491}
2492
2493static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2494{
2495 struct drm_i915_private *dev_priv = dev->dev_private;
2496 u32 pos;
2497
5efb3e28 2498 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2499
2500 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2501 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2502 *x = -*x;
2503
2504 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2505 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2506 *y = -*y;
2507
2508 return cursor_active(dev, pipe);
2509}
2510
53f5e3ca
JB		 2511static int i915_display_info(struct seq_file *m, void *unused)
2512{
9f25d007 2513 struct drm_info_node *node = m->private;
53f5e3ca 2514 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2515 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2516 struct intel_crtc *crtc;
53f5e3ca
JB		 2517 struct drm_connector *connector;
2518
b0e5ddf3 2519 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2520 drm_modeset_lock_all(dev);
2521 seq_printf(m, "CRTC info\n");
2522 seq_printf(m, "---------\n");
d3fcc808 2523 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2524 bool active;
2525 int x, y;
53f5e3ca 2526
57127efa 2527 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2528 crtc->base.base.id, pipe_name(crtc->pipe),
57127efa 2529 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
a23dc658 2530 if (crtc->active) {
065f2ec2
CW		 2531 intel_crtc_info(m, crtc);
2532
a23dc658 2533 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2534 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2535 yesno(crtc->cursor_base),
57127efa
CW		 2536 x, y, crtc->cursor_width, crtc->cursor_height,
2537 crtc->cursor_addr, yesno(active));
a23dc658 2538 }
cace841c
DV		 2539
2540 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2541 yesno(!crtc->cpu_fifo_underrun_disabled),
2542 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2543 }
2544
2545 seq_printf(m, "\n");
2546 seq_printf(m, "Connector info\n");
2547 seq_printf(m, "--------------\n");
2548 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2549 intel_connector_info(m, connector);
2550 }
2551 drm_modeset_unlock_all(dev);
b0e5ddf3 2552 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2553
2554 return 0;
2555}
2556
e04934cf
BW		 2557static int i915_semaphore_status(struct seq_file *m, void *unused)
2558{
2559 struct drm_info_node *node = (struct drm_info_node *) m->private;
2560 struct drm_device *dev = node->minor->dev;
2561 struct drm_i915_private *dev_priv = dev->dev_private;
2562 struct intel_engine_cs *ring;
2563 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2564 int i, j, ret;
2565
2566 if (!i915_semaphore_is_enabled(dev)) {
2567 seq_puts(m, "Semaphores are disabled\n");
2568 return 0;
2569 }
2570
2571 ret = mutex_lock_interruptible(&dev->struct_mutex);
2572 if (ret)
2573 return ret;
03872064 2574 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2575
2576 if (IS_BROADWELL(dev)) {
2577 struct page *page;
2578 uint64_t *seqno;
2579
2580 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2581
2582 seqno = (uint64_t *)kmap_atomic(page);
2583 for_each_ring(ring, dev_priv, i) {
2584 uint64_t offset;
2585
2586 seq_printf(m, "%s\n", ring->name);
2587
2588 seq_puts(m, " Last signal:");
2589 for (j = 0; j < num_rings; j++) {
2590 offset = i * I915_NUM_RINGS + j;
2591 seq_printf(m, "0x%08llx (0x%02llx) ",
2592 seqno[offset], offset * 8);
2593 }
2594 seq_putc(m, '\n');
2595
2596 seq_puts(m, " Last wait: ");
2597 for (j = 0; j < num_rings; j++) {
2598 offset = i + (j * I915_NUM_RINGS);
2599 seq_printf(m, "0x%08llx (0x%02llx) ",
2600 seqno[offset], offset * 8);
2601 }
2602 seq_putc(m, '\n');
2603
2604 }
2605 kunmap_atomic(seqno);
2606 } else {
2607 seq_puts(m, " Last signal:");
2608 for_each_ring(ring, dev_priv, i)
2609 for (j = 0; j < num_rings; j++)
2610 seq_printf(m, "0x%08x\n",
2611 I915_READ(ring->semaphore.mbox.signal[j]));
2612 seq_putc(m, '\n');
2613 }
2614
2615 seq_puts(m, "\nSync seqno:\n");
2616 for_each_ring(ring, dev_priv, i) {
2617 for (j = 0; j < num_rings; j++) {
2618 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2619 }
2620 seq_putc(m, '\n');
2621 }
2622 seq_putc(m, '\n');
2623
03872064 2624 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2625 mutex_unlock(&dev->struct_mutex);
2626 return 0;
2627}
2628
728e29d7
DV		 2629static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2630{
2631 struct drm_info_node *node = (struct drm_info_node *) m->private;
2632 struct drm_device *dev = node->minor->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 int i;
2635
2636 drm_modeset_lock_all(dev);
2637 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2638 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2639
2640 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2641 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2642 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2643 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2644 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2645 seq_printf(m, " dpll_md: 0x%08x\n",
2646 pll->config.hw_state.dpll_md);
2647 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2648 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2649 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2650 }
2651 drm_modeset_unlock_all(dev);
2652
2653 return 0;
2654}
2655
1ed1ef9d 2656static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2657{
2658 int i;
2659 int ret;
2660 struct drm_info_node *node = (struct drm_info_node *) m->private;
2661 struct drm_device *dev = node->minor->dev;
2662 struct drm_i915_private *dev_priv = dev->dev_private;
2663
888b5995
AS		 2664 ret = mutex_lock_interruptible(&dev->struct_mutex);
2665 if (ret)
2666 return ret;
2667
2668 intel_runtime_pm_get(dev_priv);
2669
7225342a
MK		 2670 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2671 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2672 u32 addr, mask, value, read;
2673 bool ok;
888b5995 2674
7225342a
MK		 2675 addr = dev_priv->workarounds.reg[i].addr;
2676 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2677 value = dev_priv->workarounds.reg[i].value;
2678 read = I915_READ(addr);
2679 ok = (value & mask) == (read & mask);
2680 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2681 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2682 }
2683
2684 intel_runtime_pm_put(dev_priv);
2685 mutex_unlock(&dev->struct_mutex);
2686
2687 return 0;
2688}
2689
c5511e44
DL		 2690static int i915_ddb_info(struct seq_file *m, void *unused)
2691{
2692 struct drm_info_node *node = m->private;
2693 struct drm_device *dev = node->minor->dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 struct skl_ddb_allocation *ddb;
2696 struct skl_ddb_entry *entry;
2697 enum pipe pipe;
2698 int plane;
2699
2700 drm_modeset_lock_all(dev);
2701
2702 ddb = &dev_priv->wm.skl_hw.ddb;
2703
2704 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2705
2706 for_each_pipe(dev_priv, pipe) {
2707 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2708
2709 for_each_plane(pipe, plane) {
2710 entry = &ddb->plane[pipe][plane];
2711 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2712 entry->start, entry->end,
2713 skl_ddb_entry_size(entry));
2714 }
2715
2716 entry = &ddb->cursor[pipe];
2717 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2718 entry->end, skl_ddb_entry_size(entry));
2719 }
2720
2721 drm_modeset_unlock_all(dev);
2722
2723 return 0;
2724}
2725
07144428
DL		 2726struct pipe_crc_info {
2727 const char *name;
2728 struct drm_device *dev;
2729 enum pipe pipe;
2730};
2731
11bed958
DA		 2732static int i915_dp_mst_info(struct seq_file *m, void *unused)
2733{
2734 struct drm_info_node *node = (struct drm_info_node *) m->private;
2735 struct drm_device *dev = node->minor->dev;
2736 struct drm_encoder *encoder;
2737 struct intel_encoder *intel_encoder;
2738 struct intel_digital_port *intel_dig_port;
2739 drm_modeset_lock_all(dev);
2740 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2741 intel_encoder = to_intel_encoder(encoder);
2742 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2743 continue;
2744 intel_dig_port = enc_to_dig_port(encoder);
2745 if (!intel_dig_port->dp.can_mst)
2746 continue;
2747
2748 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2749 }
2750 drm_modeset_unlock_all(dev);
2751 return 0;
2752}
2753
07144428
DL		 2754static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2755{
be5c7a90
DL		 2756 struct pipe_crc_info *info = inode->i_private;
2757 struct drm_i915_private *dev_priv = info->dev->dev_private;
2758 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2759
7eb1c496
DV		 2760 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2761 return -ENODEV;
2762
d538bbdf
DL		 2763 spin_lock_irq(&pipe_crc->lock);
2764
2765 if (pipe_crc->opened) {
2766 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2767 return -EBUSY; /* already open */
2768 }
2769
d538bbdf 2770 pipe_crc->opened = true;
07144428
DL		 2771 filep->private_data = inode->i_private;
2772
d538bbdf
DL		 2773 spin_unlock_irq(&pipe_crc->lock);
2774
07144428
DL		 2775 return 0;
2776}
2777
2778static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2779{
be5c7a90
DL		 2780 struct pipe_crc_info *info = inode->i_private;
2781 struct drm_i915_private *dev_priv = info->dev->dev_private;
2782 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2783
d538bbdf
DL		 2784 spin_lock_irq(&pipe_crc->lock);
2785 pipe_crc->opened = false;
2786 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2787
07144428
DL		 2788 return 0;
2789}
2790
2791/* (6 fields, 8 chars each, space separated (5) + '\n') */
2792#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2793/* account for \'0' */
2794#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2795
2796static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2797{
d538bbdf
DL		 2798 assert_spin_locked(&pipe_crc->lock);
2799 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2800 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2801}
2802
2803static ssize_t
2804i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2805 loff_t *pos)
2806{
2807 struct pipe_crc_info *info = filep->private_data;
2808 struct drm_device *dev = info->dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2811 char buf[PIPE_CRC_BUFFER_LEN];
2812 int head, tail, n_entries, n;
2813 ssize_t bytes_read;
2814
2815 /*
2816 * Don't allow user space to provide buffers not big enough to hold
2817 * a line of data.
2818 */
2819 if (count < PIPE_CRC_LINE_LEN)
2820 return -EINVAL;
2821
2822 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2823 return 0;
07144428
DL		 2824
2825 /* nothing to read */
d538bbdf 2826 spin_lock_irq(&pipe_crc->lock);
07144428 2827 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2828 int ret;
2829
2830 if (filep->f_flags & O_NONBLOCK) {
2831 spin_unlock_irq(&pipe_crc->lock);
07144428 2832 return -EAGAIN;
d538bbdf 2833 }
07144428 2834
d538bbdf
DL		 2835 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2836 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2837 if (ret) {
2838 spin_unlock_irq(&pipe_crc->lock);
2839 return ret;
2840 }
8bf1e9f1
SH		 2841 }
2842
07144428 2843 /* We now have one or more entries to read */
d538bbdf
DL		 2844 head = pipe_crc->head;
2845 tail = pipe_crc->tail;
07144428
DL		 2846 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2847 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2848 spin_unlock_irq(&pipe_crc->lock);
2849
07144428
DL		 2850 bytes_read = 0;
2851 n = 0;
2852 do {
b2c88f5b 2853 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2854 int ret;
8bf1e9f1 2855
07144428
DL		 2856 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2857 "%8u %8x %8x %8x %8x %8x\n",
2858 entry->frame, entry->crc[0],
2859 entry->crc[1], entry->crc[2],
2860 entry->crc[3], entry->crc[4]);
2861
2862 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2863 buf, PIPE_CRC_LINE_LEN);
2864 if (ret == PIPE_CRC_LINE_LEN)
2865 return -EFAULT;
b2c88f5b
DL		 2866
2867 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2868 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2869 n++;
2870 } while (--n_entries);
8bf1e9f1 2871
d538bbdf
DL		 2872 spin_lock_irq(&pipe_crc->lock);
2873 pipe_crc->tail = tail;
2874 spin_unlock_irq(&pipe_crc->lock);
2875
07144428
DL		 2876 return bytes_read;
2877}
2878
2879static const struct file_operations i915_pipe_crc_fops = {
2880 .owner = THIS_MODULE,
2881 .open = i915_pipe_crc_open,
2882 .read = i915_pipe_crc_read,
2883 .release = i915_pipe_crc_release,
2884};
2885
2886static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2887 {
2888 .name = "i915_pipe_A_crc",
2889 .pipe = PIPE_A,
2890 },
2891 {
2892 .name = "i915_pipe_B_crc",
2893 .pipe = PIPE_B,
2894 },
2895 {
2896 .name = "i915_pipe_C_crc",
2897 .pipe = PIPE_C,
2898 },
2899};
2900
2901static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2902 enum pipe pipe)
2903{
2904 struct drm_device *dev = minor->dev;
2905 struct dentry *ent;
2906 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2907
2908 info->dev = dev;
2909 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2910 &i915_pipe_crc_fops);
f3c5fe97
WY		 2911 if (!ent)
2912 return -ENOMEM;
07144428
DL		 2913
2914 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2915}
2916
e8dfcf78 2917static const char * const pipe_crc_sources[] = {
926321d5
DV		 2918 "none",
2919 "plane1",
2920 "plane2",
2921 "pf",
5b3a856b 2922 "pipe",
3d099a05
DV		 2923 "TV",
2924 "DP-B",
2925 "DP-C",
2926 "DP-D",
46a19188 2927 "auto",
926321d5
DV		 2928};
2929
2930static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2931{
2932 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2933 return pipe_crc_sources[source];
2934}
2935
bd9db02f 2936static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2937{
2938 struct drm_device *dev = m->private;
2939 struct drm_i915_private *dev_priv = dev->dev_private;
2940 int i;
2941
2942 for (i = 0; i < I915_MAX_PIPES; i++)
2943 seq_printf(m, "%c %s\n", pipe_name(i),
2944 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2945
2946 return 0;
2947}
2948
bd9db02f 2949static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2950{
2951 struct drm_device *dev = inode->i_private;
2952
bd9db02f 2953 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2954}
2955
46a19188 2956static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2957 uint32_t *val)
2958{
46a19188
DV		 2959 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2960 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2961
2962 switch (*source) {
52f843f6
DV		 2963 case INTEL_PIPE_CRC_SOURCE_PIPE:
2964 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2965 break;
2966 case INTEL_PIPE_CRC_SOURCE_NONE:
2967 *val = 0;
2968 break;
2969 default:
2970 return -EINVAL;
2971 }
2972
2973 return 0;
2974}
2975
46a19188
DV		 2976static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2977 enum intel_pipe_crc_source *source)
2978{
2979 struct intel_encoder *encoder;
2980 struct intel_crtc *crtc;
26756809 2981 struct intel_digital_port *dig_port;
46a19188
DV		 2982 int ret = 0;
2983
2984 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2985
6e9f798d 2986 drm_modeset_lock_all(dev);
b2784e15 2987 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 2988 if (!encoder->base.crtc)
2989 continue;
2990
2991 crtc = to_intel_crtc(encoder->base.crtc);
2992
2993 if (crtc->pipe != pipe)
2994 continue;
2995
2996 switch (encoder->type) {
2997 case INTEL_OUTPUT_TVOUT:
2998 *source = INTEL_PIPE_CRC_SOURCE_TV;
2999 break;
3000 case INTEL_OUTPUT_DISPLAYPORT:
3001 case INTEL_OUTPUT_EDP:
26756809
DV		 3002 dig_port = enc_to_dig_port(&encoder->base);
3003 switch (dig_port->port) {
3004 case PORT_B:
3005 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3006 break;
3007 case PORT_C:
3008 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3009 break;
3010 case PORT_D:
3011 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3012 break;
3013 default:
3014 WARN(1, "nonexisting DP port %c\n",
3015 port_name(dig_port->port));
3016 break;
3017 }
46a19188 3018 break;
6847d71b
PZ		 3019 default:
3020 break;
46a19188
DV		 3021 }
3022 }
6e9f798d 3023 drm_modeset_unlock_all(dev);
46a19188
DV		 3024
3025 return ret;
3026}
3027
3028static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3029 enum pipe pipe,
3030 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3031 uint32_t *val)
3032{
8d2f24ca
DV		 3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 bool need_stable_symbols = false;
3035
46a19188
DV		 3036 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3037 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3038 if (ret)
3039 return ret;
3040 }
3041
3042 switch (*source) {
7ac0129b
DV		 3043 case INTEL_PIPE_CRC_SOURCE_PIPE:
3044 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3045 break;
3046 case INTEL_PIPE_CRC_SOURCE_DP_B:
3047 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3048 need_stable_symbols = true;
7ac0129b
DV		 3049 break;
3050 case INTEL_PIPE_CRC_SOURCE_DP_C:
3051 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3052 need_stable_symbols = true;
7ac0129b
DV		 3053 break;
3054 case INTEL_PIPE_CRC_SOURCE_NONE:
3055 *val = 0;
3056 break;
3057 default:
3058 return -EINVAL;
3059 }
3060
8d2f24ca
DV		 3061 /*
3062 * When the pipe CRC tap point is after the transcoders we need
3063 * to tweak symbol-level features to produce a deterministic series of
3064 * symbols for a given frame. We need to reset those features only once
3065 * a frame (instead of every nth symbol):
3066 * - DC-balance: used to ensure a better clock recovery from the data
3067 * link (SDVO)
3068 * - DisplayPort scrambling: used for EMI reduction
3069 */
3070 if (need_stable_symbols) {
3071 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3072
8d2f24ca
DV		 3073 tmp |= DC_BALANCE_RESET_VLV;
3074 if (pipe == PIPE_A)
3075 tmp |= PIPE_A_SCRAMBLE_RESET;
3076 else
3077 tmp |= PIPE_B_SCRAMBLE_RESET;
3078
3079 I915_WRITE(PORT_DFT2_G4X, tmp);
3080 }
3081
7ac0129b
DV		 3082 return 0;
3083}
3084
4b79ebf7 3085static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3086 enum pipe pipe,
3087 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3088 uint32_t *val)
3089{
84093603
DV		 3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 bool need_stable_symbols = false;
3092
46a19188
DV		 3093 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3094 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3095 if (ret)
3096 return ret;
3097 }
3098
3099 switch (*source) {
4b79ebf7
DV		 3100 case INTEL_PIPE_CRC_SOURCE_PIPE:
3101 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3102 break;
3103 case INTEL_PIPE_CRC_SOURCE_TV:
3104 if (!SUPPORTS_TV(dev))
3105 return -EINVAL;
3106 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3107 break;
3108 case INTEL_PIPE_CRC_SOURCE_DP_B:
3109 if (!IS_G4X(dev))
3110 return -EINVAL;
3111 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3112 need_stable_symbols = true;
4b79ebf7
DV		 3113 break;
3114 case INTEL_PIPE_CRC_SOURCE_DP_C:
3115 if (!IS_G4X(dev))
3116 return -EINVAL;
3117 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3118 need_stable_symbols = true;
4b79ebf7
DV		 3119 break;
3120 case INTEL_PIPE_CRC_SOURCE_DP_D:
3121 if (!IS_G4X(dev))
3122 return -EINVAL;
3123 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3124 need_stable_symbols = true;
4b79ebf7
DV		 3125 break;
3126 case INTEL_PIPE_CRC_SOURCE_NONE:
3127 *val = 0;
3128 break;
3129 default:
3130 return -EINVAL;
3131 }
3132
84093603
DV		 3133 /*
3134 * When the pipe CRC tap point is after the transcoders we need
3135 * to tweak symbol-level features to produce a deterministic series of
3136 * symbols for a given frame. We need to reset those features only once
3137 * a frame (instead of every nth symbol):
3138 * - DC-balance: used to ensure a better clock recovery from the data
3139 * link (SDVO)
3140 * - DisplayPort scrambling: used for EMI reduction
3141 */
3142 if (need_stable_symbols) {
3143 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3144
3145 WARN_ON(!IS_G4X(dev));
3146
3147 I915_WRITE(PORT_DFT_I9XX,
3148 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3149
3150 if (pipe == PIPE_A)
3151 tmp |= PIPE_A_SCRAMBLE_RESET;
3152 else
3153 tmp |= PIPE_B_SCRAMBLE_RESET;
3154
3155 I915_WRITE(PORT_DFT2_G4X, tmp);
3156 }
3157
4b79ebf7
DV		 3158 return 0;
3159}
3160
8d2f24ca
DV		 3161static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3162 enum pipe pipe)
3163{
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3166
3167 if (pipe == PIPE_A)
3168 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3169 else
3170 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3171 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3172 tmp &= ~DC_BALANCE_RESET_VLV;
3173 I915_WRITE(PORT_DFT2_G4X, tmp);
3174
3175}
3176
84093603
DV		 3177static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3178 enum pipe pipe)
3179{
3180 struct drm_i915_private *dev_priv = dev->dev_private;
3181 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3182
3183 if (pipe == PIPE_A)
3184 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3185 else
3186 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3187 I915_WRITE(PORT_DFT2_G4X, tmp);
3188
3189 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3190 I915_WRITE(PORT_DFT_I9XX,
3191 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3192 }
3193}
3194
46a19188 3195static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3196 uint32_t *val)
3197{
46a19188
DV		 3198 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3199 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3200
3201 switch (*source) {
5b3a856b
DV		 3202 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3203 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3204 break;
3205 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3206 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3207 break;
5b3a856b
DV		 3208 case INTEL_PIPE_CRC_SOURCE_PIPE:
3209 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3210 break;
3d099a05 3211 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3212 *val = 0;
3213 break;
3d099a05
DV		 3214 default:
3215 return -EINVAL;
5b3a856b
DV		 3216 }
3217
3218 return 0;
3219}
3220
fabf6e51
DV		 3221static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3222{
3223 struct drm_i915_private *dev_priv = dev->dev_private;
3224 struct intel_crtc *crtc =
3225 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3226
3227 drm_modeset_lock_all(dev);
3228 /*
3229 * If we use the eDP transcoder we need to make sure that we don't
3230 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3231 * relevant on hsw with pipe A when using the always-on power well
3232 * routing.
3233 */
3234 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3235 !crtc->config.pch_pfit.enabled) {
3236 crtc->config.pch_pfit.force_thru = true;
3237
3238 intel_display_power_get(dev_priv,
3239 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3240
3241 dev_priv->display.crtc_disable(&crtc->base);
3242 dev_priv->display.crtc_enable(&crtc->base);
3243 }
3244 drm_modeset_unlock_all(dev);
3245}
3246
3247static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3248{
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 struct intel_crtc *crtc =
3251 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3252
3253 drm_modeset_lock_all(dev);
3254 /*
3255 * If we use the eDP transcoder we need to make sure that we don't
3256 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3257 * relevant on hsw with pipe A when using the always-on power well
3258 * routing.
3259 */
3260 if (crtc->config.pch_pfit.force_thru) {
3261 crtc->config.pch_pfit.force_thru = false;
3262
3263 dev_priv->display.crtc_disable(&crtc->base);
3264 dev_priv->display.crtc_enable(&crtc->base);
3265
3266 intel_display_power_put(dev_priv,
3267 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3268 }
3269 drm_modeset_unlock_all(dev);
3270}
3271
3272static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3273 enum pipe pipe,
3274 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3275 uint32_t *val)
3276{
46a19188
DV		 3277 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3278 *source = INTEL_PIPE_CRC_SOURCE_PF;
3279
3280 switch (*source) {
5b3a856b
DV		 3281 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3282 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3283 break;
3284 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3285 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3286 break;
3287 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3288 if (IS_HASWELL(dev) && pipe == PIPE_A)
3289 hsw_trans_edp_pipe_A_crc_wa(dev);
3290
5b3a856b
DV		 3291 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3292 break;
3d099a05 3293 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3294 *val = 0;
3295 break;
3d099a05
DV		 3296 default:
3297 return -EINVAL;
5b3a856b
DV		 3298 }
3299
3300 return 0;
3301}
3302
926321d5
DV		 3303static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3304 enum intel_pipe_crc_source source)
3305{
3306 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3307 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3308 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3309 pipe));
432f3342 3310 u32 val = 0; /* shut up gcc */
5b3a856b 3311 int ret;
926321d5 3312
cc3da175
DL		 3313 if (pipe_crc->source == source)
3314 return 0;
3315
ae676fcd
DL		 3316 /* forbid changing the source without going back to 'none' */
3317 if (pipe_crc->source && source)
3318 return -EINVAL;
3319
52f843f6 3320 if (IS_GEN2(dev))
46a19188 3321 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3322 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3323 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3324 else if (IS_VALLEYVIEW(dev))
fabf6e51 3325 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3326 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3327 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3328 else
fabf6e51 3329 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3330
3331 if (ret != 0)
3332 return ret;
3333
4b584369
DL		 3334 /* none -> real source transition */
3335 if (source) {
7cd6ccff
DL		 3336 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3337 pipe_name(pipe), pipe_crc_source_name(source));
3338
e5f75aca
DL		 3339 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
3340 INTEL_PIPE_CRC_ENTRIES_NR,
3341 GFP_KERNEL);
3342 if (!pipe_crc->entries)
3343 return -ENOMEM;
3344
8c740dce
PZ		 3345 /*
3346 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3347 * enabled and disabled dynamically based on package C states,
3348 * user space can't make reliable use of the CRCs, so let's just
3349 * completely disable it.
3350 */
3351 hsw_disable_ips(crtc);
3352
d538bbdf
DL		 3353 spin_lock_irq(&pipe_crc->lock);
3354 pipe_crc->head = 0;
3355 pipe_crc->tail = 0;
3356 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3357 }
3358
cc3da175 3359 pipe_crc->source = source;
926321d5 3360
926321d5
DV		 3361 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3362 POSTING_READ(PIPE_CRC_CTL(pipe));
3363
e5f75aca
DL		 3364 /* real source -> none transition */
3365 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3366 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3367 struct intel_crtc *crtc =
3368 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3369
7cd6ccff
DL		 3370 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3371 pipe_name(pipe));
3372
a33d7105
DV		 3373 drm_modeset_lock(&crtc->base.mutex, NULL);
3374 if (crtc->active)
3375 intel_wait_for_vblank(dev, pipe);
3376 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3377
d538bbdf
DL		 3378 spin_lock_irq(&pipe_crc->lock);
3379 entries = pipe_crc->entries;
e5f75aca 3380 pipe_crc->entries = NULL;
d538bbdf
DL		 3381 spin_unlock_irq(&pipe_crc->lock);
3382
3383 kfree(entries);
84093603
DV		 3384
3385 if (IS_G4X(dev))
3386 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3387 else if (IS_VALLEYVIEW(dev))
3388 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3389 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3390 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3391
3392 hsw_enable_ips(crtc);
e5f75aca
DL		 3393 }
3394
926321d5
DV		 3395 return 0;
3396}
3397
3398/*
3399 * Parse pipe CRC command strings:
b94dec87
DL		 3400 * command: wsp* object wsp+ name wsp+ source wsp*
3401 * object: 'pipe'
3402 * name: (A | B | C)
926321d5
DV		 3403 * source: (none | plane1 | plane2 | pf)
3404 * wsp: (#0x20 | #0x9 | #0xA)+
3405 *
3406 * eg.:
b94dec87
DL		 3407 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3408 * "pipe A none" -> Stop CRC
926321d5 3409 */
bd9db02f 3410static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3411{
3412 int n_words = 0;
3413
3414 while (*buf) {
3415 char *end;
3416
3417 /* skip leading white space */
3418 buf = skip_spaces(buf);
3419 if (!*buf)
3420 break; /* end of buffer */
3421
3422 /* find end of word */
3423 for (end = buf; *end && !isspace(*end); end++)
3424 ;
3425
3426 if (n_words == max_words) {
3427 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3428 max_words);
3429 return -EINVAL; /* ran out of words[] before bytes */
3430 }
3431
3432 if (*end)
3433 *end++ = '\0';
3434 words[n_words++] = buf;
3435 buf = end;
3436 }
3437
3438 return n_words;
3439}
3440
b94dec87
DL		 3441enum intel_pipe_crc_object {
3442 PIPE_CRC_OBJECT_PIPE,
3443};
3444
e8dfcf78 3445static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3446 "pipe",
3447};
3448
3449static int
bd9db02f 3450display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3451{
3452 int i;
3453
3454 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3455 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3456 *o = i;
b94dec87
DL		 3457 return 0;
3458 }
3459
3460 return -EINVAL;
3461}
3462
bd9db02f 3463static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3464{
3465 const char name = buf[0];
3466
3467 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3468 return -EINVAL;
3469
3470 *pipe = name - 'A';
3471
3472 return 0;
3473}
3474
3475static int
bd9db02f 3476display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3477{
3478 int i;
3479
3480 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3481 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3482 *s = i;
926321d5
DV		 3483 return 0;
3484 }
3485
3486 return -EINVAL;
3487}
3488
bd9db02f 3489static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3490{
b94dec87 3491#define N_WORDS 3
926321d5 3492 int n_words;
b94dec87 3493 char *words[N_WORDS];
926321d5 3494 enum pipe pipe;
b94dec87 3495 enum intel_pipe_crc_object object;
926321d5
DV		 3496 enum intel_pipe_crc_source source;
3497
bd9db02f 3498 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3499 if (n_words != N_WORDS) {
3500 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3501 N_WORDS);
3502 return -EINVAL;
3503 }
3504
bd9db02f 3505 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3506 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3507 return -EINVAL;
3508 }
3509
bd9db02f 3510 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3511 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3512 return -EINVAL;
3513 }
3514
bd9db02f 3515 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3516 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3517 return -EINVAL;
3518 }
3519
3520 return pipe_crc_set_source(dev, pipe, source);
3521}
3522
bd9db02f
DL		 3523static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3524 size_t len, loff_t *offp)
926321d5
DV		 3525{
3526 struct seq_file *m = file->private_data;
3527 struct drm_device *dev = m->private;
3528 char *tmpbuf;
3529 int ret;
3530
3531 if (len == 0)
3532 return 0;
3533
3534 if (len > PAGE_SIZE - 1) {
3535 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3536 PAGE_SIZE);
3537 return -E2BIG;
3538 }
3539
3540 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3541 if (!tmpbuf)
3542 return -ENOMEM;
3543
3544 if (copy_from_user(tmpbuf, ubuf, len)) {
3545 ret = -EFAULT;
3546 goto out;
3547 }
3548 tmpbuf[len] = '\0';
3549
bd9db02f 3550 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3551
3552out:
3553 kfree(tmpbuf);
3554 if (ret < 0)
3555 return ret;
3556
3557 *offp += len;
3558 return len;
3559}
3560
bd9db02f 3561static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3562 .owner = THIS_MODULE,
bd9db02f 3563 .open = display_crc_ctl_open,
926321d5
DV		 3564 .read = seq_read,
3565 .llseek = seq_lseek,
3566 .release = single_release,
bd9db02f 3567 .write = display_crc_ctl_write
926321d5
DV		 3568};
3569
97e94b22 3570static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3571{
3572 struct drm_device *dev = m->private;
546c81fd 3573 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3574 int level;
3575
3576 drm_modeset_lock_all(dev);
3577
3578 for (level = 0; level < num_levels; level++) {
3579 unsigned int latency = wm[level];
3580
97e94b22
DL		 3581 /*
3582 * - WM1+ latency values in 0.5us units
3583 * - latencies are in us on gen9
3584 */
3585 if (INTEL_INFO(dev)->gen >= 9)
3586 latency *= 10;
3587 else if (level > 0)
369a1342
VS		 3588 latency *= 5;
3589
3590 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3591 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3592 }
3593
3594 drm_modeset_unlock_all(dev);
3595}
3596
3597static int pri_wm_latency_show(struct seq_file *m, void *data)
3598{
3599 struct drm_device *dev = m->private;
97e94b22
DL		 3600 struct drm_i915_private *dev_priv = dev->dev_private;
3601 const uint16_t *latencies;
3602
3603 if (INTEL_INFO(dev)->gen >= 9)
3604 latencies = dev_priv->wm.skl_latency;
3605 else
3606 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3607
97e94b22 3608 wm_latency_show(m, latencies);
369a1342
VS		 3609
3610 return 0;
3611}
3612
3613static int spr_wm_latency_show(struct seq_file *m, void *data)
3614{
3615 struct drm_device *dev = m->private;
97e94b22
DL		 3616 struct drm_i915_private *dev_priv = dev->dev_private;
3617 const uint16_t *latencies;
3618
3619 if (INTEL_INFO(dev)->gen >= 9)
3620 latencies = dev_priv->wm.skl_latency;
3621 else
3622 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3623
97e94b22 3624 wm_latency_show(m, latencies);
369a1342
VS		 3625
3626 return 0;
3627}
3628
3629static int cur_wm_latency_show(struct seq_file *m, void *data)
3630{
3631 struct drm_device *dev = m->private;
97e94b22
DL		 3632 struct drm_i915_private *dev_priv = dev->dev_private;
3633 const uint16_t *latencies;
3634
3635 if (INTEL_INFO(dev)->gen >= 9)
3636 latencies = dev_priv->wm.skl_latency;
3637 else
3638 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3639
97e94b22 3640 wm_latency_show(m, latencies);
369a1342
VS		 3641
3642 return 0;
3643}
3644
3645static int pri_wm_latency_open(struct inode *inode, struct file *file)
3646{
3647 struct drm_device *dev = inode->i_private;
3648
9ad0257c 3649 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3650 return -ENODEV;
3651
3652 return single_open(file, pri_wm_latency_show, dev);
3653}
3654
3655static int spr_wm_latency_open(struct inode *inode, struct file *file)
3656{
3657 struct drm_device *dev = inode->i_private;
3658
9ad0257c 3659 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3660 return -ENODEV;
3661
3662 return single_open(file, spr_wm_latency_show, dev);
3663}
3664
3665static int cur_wm_latency_open(struct inode *inode, struct file *file)
3666{
3667 struct drm_device *dev = inode->i_private;
3668
9ad0257c 3669 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3670 return -ENODEV;
3671
3672 return single_open(file, cur_wm_latency_show, dev);
3673}
3674
3675static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3676 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3677{
3678 struct seq_file *m = file->private_data;
3679 struct drm_device *dev = m->private;
97e94b22 3680 uint16_t new[8] = { 0 };
546c81fd 3681 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3682 int level;
3683 int ret;
3684 char tmp[32];
3685
3686 if (len >= sizeof(tmp))
3687 return -EINVAL;
3688
3689 if (copy_from_user(tmp, ubuf, len))
3690 return -EFAULT;
3691
3692 tmp[len] = '\0';
3693
97e94b22
DL		 3694 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3695 &new[0], &new[1], &new[2], &new[3],
3696 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 3697 if (ret != num_levels)
3698 return -EINVAL;
3699
3700 drm_modeset_lock_all(dev);
3701
3702 for (level = 0; level < num_levels; level++)
3703 wm[level] = new[level];
3704
3705 drm_modeset_unlock_all(dev);
3706
3707 return len;
3708}
3709
3710
3711static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3712 size_t len, loff_t *offp)
3713{
3714 struct seq_file *m = file->private_data;
3715 struct drm_device *dev = m->private;
97e94b22
DL		 3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 uint16_t *latencies;
369a1342 3718
97e94b22
DL		 3719 if (INTEL_INFO(dev)->gen >= 9)
3720 latencies = dev_priv->wm.skl_latency;
3721 else
3722 latencies = to_i915(dev)->wm.pri_latency;
3723
3724 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3725}
3726
3727static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3728 size_t len, loff_t *offp)
3729{
3730 struct seq_file *m = file->private_data;
3731 struct drm_device *dev = m->private;
97e94b22
DL		 3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 uint16_t *latencies;
369a1342 3734
97e94b22
DL		 3735 if (INTEL_INFO(dev)->gen >= 9)
3736 latencies = dev_priv->wm.skl_latency;
3737 else
3738 latencies = to_i915(dev)->wm.spr_latency;
3739
3740 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3741}
3742
3743static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3744 size_t len, loff_t *offp)
3745{
3746 struct seq_file *m = file->private_data;
3747 struct drm_device *dev = m->private;
97e94b22
DL		 3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 uint16_t *latencies;
3750
3751 if (INTEL_INFO(dev)->gen >= 9)
3752 latencies = dev_priv->wm.skl_latency;
3753 else
3754 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3755
97e94b22 3756 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3757}
3758
3759static const struct file_operations i915_pri_wm_latency_fops = {
3760 .owner = THIS_MODULE,
3761 .open = pri_wm_latency_open,
3762 .read = seq_read,
3763 .llseek = seq_lseek,
3764 .release = single_release,
3765 .write = pri_wm_latency_write
3766};
3767
3768static const struct file_operations i915_spr_wm_latency_fops = {
3769 .owner = THIS_MODULE,
3770 .open = spr_wm_latency_open,
3771 .read = seq_read,
3772 .llseek = seq_lseek,
3773 .release = single_release,
3774 .write = spr_wm_latency_write
3775};
3776
3777static const struct file_operations i915_cur_wm_latency_fops = {
3778 .owner = THIS_MODULE,
3779 .open = cur_wm_latency_open,
3780 .read = seq_read,
3781 .llseek = seq_lseek,
3782 .release = single_release,
3783 .write = cur_wm_latency_write
3784};
3785
647416f9
KC		 3786static int
3787i915_wedged_get(void *data, u64 *val)
f3cd474b 3788{
647416f9 3789 struct drm_device *dev = data;
e277a1f8 3790 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3791
647416f9 3792 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3793
647416f9 3794 return 0;
f3cd474b
CW		 3795}
3796
647416f9
KC		 3797static int
3798i915_wedged_set(void *data, u64 val)
f3cd474b 3799{
647416f9 3800 struct drm_device *dev = data;
d46c0517
ID		 3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802
3803 intel_runtime_pm_get(dev_priv);
f3cd474b 3804
58174462
MK		 3805 i915_handle_error(dev, val,
3806 "Manually setting wedged to %llu", val);
d46c0517
ID		 3807
3808 intel_runtime_pm_put(dev_priv);
3809
647416f9 3810 return 0;
f3cd474b
CW		 3811}
3812
647416f9
KC		 3813DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3814 i915_wedged_get, i915_wedged_set,
3a3b4f98 3815 "%llu\n");
f3cd474b 3816
647416f9
KC		 3817static int
3818i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3819{
647416f9 3820 struct drm_device *dev = data;
e277a1f8 3821 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3822
647416f9 3823 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3824
647416f9 3825 return 0;
e5eb3d63
DV		 3826}
3827
647416f9
KC		 3828static int
3829i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3830{
647416f9 3831 struct drm_device *dev = data;
e5eb3d63 3832 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3833 int ret;
e5eb3d63 3834
647416f9 3835 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3836
22bcfc6a
DV		 3837 ret = mutex_lock_interruptible(&dev->struct_mutex);
3838 if (ret)
3839 return ret;
3840
99584db3 3841 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3842 mutex_unlock(&dev->struct_mutex);
3843
647416f9 3844 return 0;
e5eb3d63
DV		 3845}
3846
647416f9
KC		 3847DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3848 i915_ring_stop_get, i915_ring_stop_set,
3849 "0x%08llx\n");
d5442303 3850
094f9a54
CW		 3851static int
3852i915_ring_missed_irq_get(void *data, u64 *val)
3853{
3854 struct drm_device *dev = data;
3855 struct drm_i915_private *dev_priv = dev->dev_private;
3856
3857 *val = dev_priv->gpu_error.missed_irq_rings;
3858 return 0;
3859}
3860
3861static int
3862i915_ring_missed_irq_set(void *data, u64 val)
3863{
3864 struct drm_device *dev = data;
3865 struct drm_i915_private *dev_priv = dev->dev_private;
3866 int ret;
3867
3868 /* Lock against concurrent debugfs callers */
3869 ret = mutex_lock_interruptible(&dev->struct_mutex);
3870 if (ret)
3871 return ret;
3872 dev_priv->gpu_error.missed_irq_rings = val;
3873 mutex_unlock(&dev->struct_mutex);
3874
3875 return 0;
3876}
3877
3878DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3879 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3880 "0x%08llx\n");
3881
3882static int
3883i915_ring_test_irq_get(void *data, u64 *val)
3884{
3885 struct drm_device *dev = data;
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3887
3888 *val = dev_priv->gpu_error.test_irq_rings;
3889
3890 return 0;
3891}
3892
3893static int
3894i915_ring_test_irq_set(void *data, u64 val)
3895{
3896 struct drm_device *dev = data;
3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898 int ret;
3899
3900 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3901
3902 /* Lock against concurrent debugfs callers */
3903 ret = mutex_lock_interruptible(&dev->struct_mutex);
3904 if (ret)
3905 return ret;
3906
3907 dev_priv->gpu_error.test_irq_rings = val;
3908 mutex_unlock(&dev->struct_mutex);
3909
3910 return 0;
3911}
3912
3913DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3914 i915_ring_test_irq_get, i915_ring_test_irq_set,
3915 "0x%08llx\n");
3916
dd624afd
CW		 3917#define DROP_UNBOUND 0x1
3918#define DROP_BOUND 0x2
3919#define DROP_RETIRE 0x4
3920#define DROP_ACTIVE 0x8
3921#define DROP_ALL (DROP_UNBOUND | \
3922 DROP_BOUND | \
3923 DROP_RETIRE | \
3924 DROP_ACTIVE)
647416f9
KC		 3925static int
3926i915_drop_caches_get(void *data, u64 *val)
dd624afd 3927{
647416f9 3928 *val = DROP_ALL;
dd624afd 3929
647416f9 3930 return 0;
dd624afd
CW		 3931}
3932
647416f9
KC		 3933static int
3934i915_drop_caches_set(void *data, u64 val)
dd624afd 3935{
647416f9 3936 struct drm_device *dev = data;
dd624afd 3937 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3938 int ret;
dd624afd 3939
2f9fe5ff 3940 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3941
3942 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3943 * on ioctls on -EAGAIN. */
3944 ret = mutex_lock_interruptible(&dev->struct_mutex);
3945 if (ret)
3946 return ret;
3947
3948 if (val & DROP_ACTIVE) {
3949 ret = i915_gpu_idle(dev);
3950 if (ret)
3951 goto unlock;
3952 }
3953
3954 if (val & (DROP_RETIRE | DROP_ACTIVE))
3955 i915_gem_retire_requests(dev);
3956
21ab4e74
CW		 3957 if (val & DROP_BOUND)
3958 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 3959
21ab4e74
CW		 3960 if (val & DROP_UNBOUND)
3961 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 3962
3963unlock:
3964 mutex_unlock(&dev->struct_mutex);
3965
647416f9 3966 return ret;
dd624afd
CW		 3967}
3968
647416f9
KC		 3969DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3970 i915_drop_caches_get, i915_drop_caches_set,
3971 "0x%08llx\n");
dd624afd 3972
647416f9
KC		 3973static int
3974i915_max_freq_get(void *data, u64 *val)
358733e9 3975{
647416f9 3976 struct drm_device *dev = data;
e277a1f8 3977 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3978 int ret;
004777cb 3979
daa3afb2 3980 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3981 return -ENODEV;
3982
5c9669ce
TR		 3983 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3984
4fc688ce 3985 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3986 if (ret)
3987 return ret;
358733e9 3988
0a073b84 3989 if (IS_VALLEYVIEW(dev))
b39fb297 3990 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 3991 else
b39fb297 3992 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3993 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3994
647416f9 3995 return 0;
358733e9
JB		 3996}
3997
647416f9
KC		 3998static int
3999i915_max_freq_set(void *data, u64 val)
358733e9 4000{
647416f9 4001 struct drm_device *dev = data;
358733e9 4002 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4003 u32 rp_state_cap, hw_max, hw_min;
647416f9 4004 int ret;
004777cb 4005
daa3afb2 4006 if (INTEL_INFO(dev)->gen < 6)
004777cb 4007 return -ENODEV;
358733e9 4008
5c9669ce
TR		 4009 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4010
647416f9 4011 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4012
4fc688ce 4013 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4014 if (ret)
4015 return ret;
4016
358733e9
JB		 4017 /*
4018 * Turbo will still be enabled, but won't go above the set value.
4019 */
0a073b84 4020 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4021 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4022
03af2045
VS		 4023 hw_max = dev_priv->rps.max_freq;
4024 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4025 } else {
4026 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4027
4028 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4029 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4030 hw_min = (rp_state_cap >> 16) & 0xff;
4031 }
4032
b39fb297 4033 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4034 mutex_unlock(&dev_priv->rps.hw_lock);
4035 return -EINVAL;
0a073b84
JB		 4036 }
4037
b39fb297 4038 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 4039
4040 if (IS_VALLEYVIEW(dev))
4041 valleyview_set_rps(dev, val);
4042 else
4043 gen6_set_rps(dev, val);
4044
4fc688ce 4045 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4046
647416f9 4047 return 0;
358733e9
JB		 4048}
4049
647416f9
KC		 4050DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4051 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4052 "%llu\n");
358733e9 4053
647416f9
KC		 4054static int
4055i915_min_freq_get(void *data, u64 *val)
1523c310 4056{
647416f9 4057 struct drm_device *dev = data;
e277a1f8 4058 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4059 int ret;
004777cb 4060
daa3afb2 4061 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4062 return -ENODEV;
4063
5c9669ce
TR		 4064 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4065
4fc688ce 4066 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4067 if (ret)
4068 return ret;
1523c310 4069
0a073b84 4070 if (IS_VALLEYVIEW(dev))
b39fb297 4071 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 4072 else
b39fb297 4073 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 4074 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4075
647416f9 4076 return 0;
1523c310
JB		 4077}
4078
647416f9
KC		 4079static int
4080i915_min_freq_set(void *data, u64 val)
1523c310 4081{
647416f9 4082 struct drm_device *dev = data;
1523c310 4083 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4084 u32 rp_state_cap, hw_max, hw_min;
647416f9 4085 int ret;
004777cb 4086
daa3afb2 4087 if (INTEL_INFO(dev)->gen < 6)
004777cb 4088 return -ENODEV;
1523c310 4089
5c9669ce
TR		 4090 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4091
647416f9 4092 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4093
4fc688ce 4094 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4095 if (ret)
4096 return ret;
4097
1523c310
JB		 4098 /*
4099 * Turbo will still be enabled, but won't go below the set value.
4100 */
0a073b84 4101 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4102 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4103
03af2045
VS		 4104 hw_max = dev_priv->rps.max_freq;
4105 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4106 } else {
4107 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4108
4109 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4110 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4111 hw_min = (rp_state_cap >> 16) & 0xff;
4112 }
4113
b39fb297 4114 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4115 mutex_unlock(&dev_priv->rps.hw_lock);
4116 return -EINVAL;
0a073b84 4117 }
dd0a1aa1 4118
b39fb297 4119 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 4120
4121 if (IS_VALLEYVIEW(dev))
4122 valleyview_set_rps(dev, val);
4123 else
4124 gen6_set_rps(dev, val);
4125
4fc688ce 4126 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4127
647416f9 4128 return 0;
1523c310
JB		 4129}
4130
647416f9
KC		 4131DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4132 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4133 "%llu\n");
1523c310 4134
647416f9
KC		 4135static int
4136i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4137{
647416f9 4138 struct drm_device *dev = data;
e277a1f8 4139 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4140 u32 snpcr;
647416f9 4141 int ret;
07b7ddd9 4142
004777cb
DV		 4143 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4144 return -ENODEV;
4145
22bcfc6a
DV		 4146 ret = mutex_lock_interruptible(&dev->struct_mutex);
4147 if (ret)
4148 return ret;
c8c8fb33 4149 intel_runtime_pm_get(dev_priv);
22bcfc6a 4150
07b7ddd9 4151 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4152
4153 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4154 mutex_unlock(&dev_priv->dev->struct_mutex);
4155
647416f9 4156 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4157
647416f9 4158 return 0;
07b7ddd9
JB		 4159}
4160
647416f9
KC		 4161static int
4162i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4163{
647416f9 4164 struct drm_device *dev = data;
07b7ddd9 4165 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4166 u32 snpcr;
07b7ddd9 4167
004777cb
DV		 4168 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4169 return -ENODEV;
4170
647416f9 4171 if (val > 3)
07b7ddd9
JB		 4172 return -EINVAL;
4173
c8c8fb33 4174 intel_runtime_pm_get(dev_priv);
647416f9 4175 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4176
4177 /* Update the cache sharing policy here as well */
4178 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4179 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4180 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4181 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4182
c8c8fb33 4183 intel_runtime_pm_put(dev_priv);
647416f9 4184 return 0;
07b7ddd9
JB		 4185}
4186
647416f9
KC		 4187DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4188 i915_cache_sharing_get, i915_cache_sharing_set,
4189 "%llu\n");
07b7ddd9 4190
6d794d42
BW		 4191static int i915_forcewake_open(struct inode *inode, struct file *file)
4192{
4193 struct drm_device *dev = inode->i_private;
4194 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4195
075edca4 4196 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4197 return 0;
4198
c8d9a590 4199 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4200
4201 return 0;
4202}
4203
c43b5634 4204static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4205{
4206 struct drm_device *dev = inode->i_private;
4207 struct drm_i915_private *dev_priv = dev->dev_private;
4208
075edca4 4209 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4210 return 0;
4211
c8d9a590 4212 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4213
4214 return 0;
4215}
4216
4217static const struct file_operations i915_forcewake_fops = {
4218 .owner = THIS_MODULE,
4219 .open = i915_forcewake_open,
4220 .release = i915_forcewake_release,
4221};
4222
4223static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4224{
4225 struct drm_device *dev = minor->dev;
4226 struct dentry *ent;
4227
4228 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4229 S_IRUSR,
6d794d42
BW		 4230 root, dev,
4231 &i915_forcewake_fops);
f3c5fe97
WY		 4232 if (!ent)
4233 return -ENOMEM;
6d794d42 4234
8eb57294 4235 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4236}
4237
6a9c308d
DV		 4238static int i915_debugfs_create(struct dentry *root,
4239 struct drm_minor *minor,
4240 const char *name,
4241 const struct file_operations *fops)
07b7ddd9
JB		 4242{
4243 struct drm_device *dev = minor->dev;
4244 struct dentry *ent;
4245
6a9c308d 4246 ent = debugfs_create_file(name,
07b7ddd9
JB		 4247 S_IRUGO | S_IWUSR,
4248 root, dev,
6a9c308d 4249 fops);
f3c5fe97
WY		 4250 if (!ent)
4251 return -ENOMEM;
07b7ddd9 4252
6a9c308d 4253 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4254}
4255
06c5bf8c 4256static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4257 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4258 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4259 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4260 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4261 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4262 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4263 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4264 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4265 {"i915_gem_request", i915_gem_request_info, 0},
4266 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4267 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4268 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4269 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4270 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4271 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4272 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
adb4bd12 4273 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 4274 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4275 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4276 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4277 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4278 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4279 {"i915_sr_status", i915_sr_status, 0},
44834a67 4280 {"i915_opregion", i915_opregion, 0},
37811fcc 4281 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4282 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4283 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4284 {"i915_execlists", i915_execlists, 0},
6d794d42 4285 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 4286 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4287 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4288 {"i915_llc", i915_llc, 0},
e91fd8c6 4289 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4290 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4291 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4292 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4293 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4294 {"i915_display_info", i915_display_info, 0},
e04934cf 4295 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4296 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4297 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4298 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4299 {"i915_ddb_info", i915_ddb_info, 0},
2017263e 4300};
27c202ad 4301#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4302
06c5bf8c 4303static const struct i915_debugfs_files {
34b9674c
DV		 4304 const char *name;
4305 const struct file_operations *fops;
4306} i915_debugfs_files[] = {
4307 {"i915_wedged", &i915_wedged_fops},
4308 {"i915_max_freq", &i915_max_freq_fops},
4309 {"i915_min_freq", &i915_min_freq_fops},
4310 {"i915_cache_sharing", &i915_cache_sharing_fops},
4311 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4312 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4313 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4314 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4315 {"i915_error_state", &i915_error_state_fops},
4316 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4317 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4318 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4319 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4320 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4321 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4322};
4323
07144428
DL		 4324void intel_display_crc_init(struct drm_device *dev)
4325{
4326 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4327 enum pipe pipe;
07144428 4328
055e393f 4329 for_each_pipe(dev_priv, pipe) {
b378360e 4330 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4331
d538bbdf
DL		 4332 pipe_crc->opened = false;
4333 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4334 init_waitqueue_head(&pipe_crc->wq);
4335 }
4336}
4337
27c202ad 4338int i915_debugfs_init(struct drm_minor *minor)
2017263e 4339{
34b9674c 4340 int ret, i;
f3cd474b 4341
6d794d42 4342 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4343 if (ret)
4344 return ret;
6a9c308d 4345
07144428
DL		 4346 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4347 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4348 if (ret)
4349 return ret;
4350 }
4351
34b9674c
DV		 4352 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4353 ret = i915_debugfs_create(minor->debugfs_root, minor,
4354 i915_debugfs_files[i].name,
4355 i915_debugfs_files[i].fops);
4356 if (ret)
4357 return ret;
4358 }
40633219 4359
27c202ad
BG		 4360 return drm_debugfs_create_files(i915_debugfs_list,
4361 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4362 minor->debugfs_root, minor);
4363}
4364
27c202ad 4365void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4366{
34b9674c
DV		 4367 int i;
4368
27c202ad
BG		 4369 drm_debugfs_remove_files(i915_debugfs_list,
4370 I915_DEBUGFS_ENTRIES, minor);
07144428 4371
6d794d42
BW		 4372 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4373 1, minor);
07144428 4374
e309a997 4375 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4376 struct drm_info_list *info_list =
4377 (struct drm_info_list *)&i915_pipe_crc_data[i];
4378
4379 drm_debugfs_remove_files(info_list, 1, minor);
4380 }
4381
34b9674c
DV		 4382 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4383 struct drm_info_list *info_list =
4384 (struct drm_info_list *) i915_debugfs_files[i].fops;
4385
4386 drm_debugfs_remove_files(info_list, 1, minor);
4387 }
2017263e 4388}
Linux 6.x block layer and io_uring tree(s)