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drm/i915: Unpin last_context at reset
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d
BW		 178{
179 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
336 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
337 continue;
338
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
349 if (obj->ring)
350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
ca191b13
BW		 363#define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
366 ++count; \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
369 ++mappable_count; \
370 } \
371 } \
372} while (0)
373
374static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 375{
9f25d007 376 struct drm_info_node *node = m->private;
73aa808f
CW		 377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
6299f992 381 struct drm_i915_gem_object *obj;
5cef07e1 382 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 383 struct drm_file *file;
ca191b13 384 struct i915_vma *vma;
73aa808f
CW		 385 int ret;
386
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
388 if (ret)
389 return ret;
390
6299f992
CW		 391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
394
395 size = count = mappable_size = mappable_count = 0;
35c20a60 396 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
399
400 size = count = mappable_size = mappable_count = 0;
ca191b13 401 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
404
6299f992 405 size = count = mappable_size = mappable_count = 0;
ca191b13 406 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
409
b7abb714 410 size = count = purgeable_size = purgeable_count = 0;
35c20a60 411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 412 size += obj->base.size, ++count;
b7abb714
CW		 413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
415 }
6c085a72
CW		 416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
417
6299f992 418 size = count = mappable_size = mappable_count = 0;
35c20a60 419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 420 if (obj->fault_mappable) {
f343c5f6 421 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 422 ++count;
423 }
424 if (obj->pin_mappable) {
f343c5f6 425 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 426 ++mappable_count;
427 }
b7abb714
CW		 428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
430 ++purgeable_count;
431 }
6299f992 432 }
b7abb714
CW		 433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
6299f992
CW		 435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 count, size);
439
93d18799 440 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 443
267f0c90 444 seq_putc(m, '\n');
2db8e9d6
CW		 445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
3ec2f427 447 struct task_struct *task;
2db8e9d6
CW		 448
449 memset(&stats, 0, sizeof(stats));
6313c204 450 stats.file_priv = file->driver_priv;
5b5ffff0 451 spin_lock(&file->table_lock);
2db8e9d6 452 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 453 spin_unlock(&file->table_lock);
3ec2f427
TH		 454 /*
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
459 */
460 rcu_read_lock();
461 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 463 task ? task->comm : "<unknown>",
2db8e9d6
CW		 464 stats.count,
465 stats.total,
466 stats.active,
467 stats.inactive,
6313c204 468 stats.global,
c67a17e9 469 stats.shared,
2db8e9d6 470 stats.unbound);
3ec2f427 471 rcu_read_unlock();
2db8e9d6
CW		 472 }
473
73aa808f
CW		 474 mutex_unlock(&dev->struct_mutex);
475
476 return 0;
477}
478
aee56cff 479static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 480{
9f25d007 481 struct drm_info_node *node = m->private;
08c18323 482 struct drm_device *dev = node->minor->dev;
1b50247a 483 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
487 int count, ret;
488
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
490 if (ret)
491 return ret;
492
493 total_obj_size = total_gtt_size = count = 0;
35c20a60 494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 496 continue;
497
267f0c90 498 seq_puts(m, " ");
08c18323 499 describe_obj(m, obj);
267f0c90 500 seq_putc(m, '\n');
08c18323 501 total_obj_size += obj->base.size;
f343c5f6 502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 503 count++;
504 }
505
506 mutex_unlock(&dev->struct_mutex);
507
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
510
511 return 0;
512}
513
4e5359cd
SF		 514static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515{
9f25d007 516 struct drm_info_node *node = m->private;
4e5359cd
SF		 517 struct drm_device *dev = node->minor->dev;
518 unsigned long flags;
519 struct intel_crtc *crtc;
8a270ebf
DV		 520 int ret;
521
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
523 if (ret)
524 return ret;
4e5359cd 525
d3fcc808 526 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 529 struct intel_unpin_work *work;
530
531 spin_lock_irqsave(&dev->event_lock, flags);
532 work = crtc->unpin_work;
533 if (work == NULL) {
9db4a9c7 534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 535 pipe, plane);
536 } else {
e7d841ca 537 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 538 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 539 pipe, plane);
540 } else {
9db4a9c7 541 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 542 pipe, plane);
543 }
544 if (work->enable_stall_check)
267f0c90 545 seq_puts(m, "Stall check enabled, ");
4e5359cd 546 else
267f0c90 547 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 548 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 549
550 if (work->old_fb_obj) {
05394f39
CW		 551 struct drm_i915_gem_object *obj = work->old_fb_obj;
552 if (obj)
f343c5f6
BW		 553 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
554 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 555 }
556 if (work->pending_flip_obj) {
05394f39
CW		 557 struct drm_i915_gem_object *obj = work->pending_flip_obj;
558 if (obj)
f343c5f6
BW		 559 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
560 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 561 }
562 }
563 spin_unlock_irqrestore(&dev->event_lock, flags);
564 }
565
8a270ebf
DV		 566 mutex_unlock(&dev->struct_mutex);
567
4e5359cd
SF		 568 return 0;
569}
570
2017263e
BG		 571static int i915_gem_request_info(struct seq_file *m, void *data)
572{
9f25d007 573 struct drm_info_node *node = m->private;
2017263e 574 struct drm_device *dev = node->minor->dev;
e277a1f8 575 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 576 struct intel_engine_cs *ring;
2017263e 577 struct drm_i915_gem_request *gem_request;
a2c7f6fd 578 int ret, count, i;
de227ef0
CW		 579
580 ret = mutex_lock_interruptible(&dev->struct_mutex);
581 if (ret)
582 return ret;
2017263e 583
c2c347a9 584 count = 0;
a2c7f6fd
CW		 585 for_each_ring(ring, dev_priv, i) {
586 if (list_empty(&ring->request_list))
587 continue;
588
589 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 590 list_for_each_entry(gem_request,
a2c7f6fd 591 &ring->request_list,
c2c347a9
CW		 592 list) {
593 seq_printf(m, " %d @ %d\n",
594 gem_request->seqno,
595 (int) (jiffies - gem_request->emitted_jiffies));
596 }
597 count++;
2017263e 598 }
de227ef0
CW		 599 mutex_unlock(&dev->struct_mutex);
600
c2c347a9 601 if (count == 0)
267f0c90 602 seq_puts(m, "No requests\n");
c2c347a9 603
2017263e
BG		 604 return 0;
605}
606
b2223497 607static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 608 struct intel_engine_cs *ring)
b2223497
CW		 609{
610 if (ring->get_seqno) {
43a7b924 611 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 612 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 613 }
614}
615
2017263e
BG		 616static int i915_gem_seqno_info(struct seq_file *m, void *data)
617{
9f25d007 618 struct drm_info_node *node = m->private;
2017263e 619 struct drm_device *dev = node->minor->dev;
e277a1f8 620 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 621 struct intel_engine_cs *ring;
1ec14ad3 622 int ret, i;
de227ef0
CW		 623
624 ret = mutex_lock_interruptible(&dev->struct_mutex);
625 if (ret)
626 return ret;
c8c8fb33 627 intel_runtime_pm_get(dev_priv);
2017263e 628
a2c7f6fd
CW		 629 for_each_ring(ring, dev_priv, i)
630 i915_ring_seqno_info(m, ring);
de227ef0 631
c8c8fb33 632 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 633 mutex_unlock(&dev->struct_mutex);
634
2017263e
BG		 635 return 0;
636}
637
638
639static int i915_interrupt_info(struct seq_file *m, void *data)
640{
9f25d007 641 struct drm_info_node *node = m->private;
2017263e 642 struct drm_device *dev = node->minor->dev;
e277a1f8 643 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 644 struct intel_engine_cs *ring;
9db4a9c7 645 int ret, i, pipe;
de227ef0
CW		 646
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 if (ret)
649 return ret;
c8c8fb33 650 intel_runtime_pm_get(dev_priv);
2017263e 651
74e1ca8c
VS		 652 if (IS_CHERRYVIEW(dev)) {
653 int i;
654 seq_printf(m, "Master Interrupt Control:\t%08x\n",
655 I915_READ(GEN8_MASTER_IRQ));
656
657 seq_printf(m, "Display IER:\t%08x\n",
658 I915_READ(VLV_IER));
659 seq_printf(m, "Display IIR:\t%08x\n",
660 I915_READ(VLV_IIR));
661 seq_printf(m, "Display IIR_RW:\t%08x\n",
662 I915_READ(VLV_IIR_RW));
663 seq_printf(m, "Display IMR:\t%08x\n",
664 I915_READ(VLV_IMR));
665 for_each_pipe(pipe)
666 seq_printf(m, "Pipe %c stat:\t%08x\n",
667 pipe_name(pipe),
668 I915_READ(PIPESTAT(pipe)));
669
670 seq_printf(m, "Port hotplug:\t%08x\n",
671 I915_READ(PORT_HOTPLUG_EN));
672 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
673 I915_READ(VLV_DPFLIPSTAT));
674 seq_printf(m, "DPINVGTT:\t%08x\n",
675 I915_READ(DPINVGTT));
676
677 for (i = 0; i < 4; i++) {
678 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
679 i, I915_READ(GEN8_GT_IMR(i)));
680 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
681 i, I915_READ(GEN8_GT_IIR(i)));
682 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
683 i, I915_READ(GEN8_GT_IER(i)));
684 }
685
686 seq_printf(m, "PCU interrupt mask:\t%08x\n",
687 I915_READ(GEN8_PCU_IMR));
688 seq_printf(m, "PCU interrupt identity:\t%08x\n",
689 I915_READ(GEN8_PCU_IIR));
690 seq_printf(m, "PCU interrupt enable:\t%08x\n",
691 I915_READ(GEN8_PCU_IER));
692 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 693 seq_printf(m, "Master Interrupt Control:\t%08x\n",
694 I915_READ(GEN8_MASTER_IRQ));
695
696 for (i = 0; i < 4; i++) {
697 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
698 i, I915_READ(GEN8_GT_IMR(i)));
699 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
700 i, I915_READ(GEN8_GT_IIR(i)));
701 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
702 i, I915_READ(GEN8_GT_IER(i)));
703 }
704
07d27e20 705 for_each_pipe(pipe) {
a123f157 706 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 707 pipe_name(pipe),
708 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 709 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 710 pipe_name(pipe),
711 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 712 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 713 pipe_name(pipe),
714 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 715 }
716
717 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
718 I915_READ(GEN8_DE_PORT_IMR));
719 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
720 I915_READ(GEN8_DE_PORT_IIR));
721 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
722 I915_READ(GEN8_DE_PORT_IER));
723
724 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
725 I915_READ(GEN8_DE_MISC_IMR));
726 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
727 I915_READ(GEN8_DE_MISC_IIR));
728 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
729 I915_READ(GEN8_DE_MISC_IER));
730
731 seq_printf(m, "PCU interrupt mask:\t%08x\n",
732 I915_READ(GEN8_PCU_IMR));
733 seq_printf(m, "PCU interrupt identity:\t%08x\n",
734 I915_READ(GEN8_PCU_IIR));
735 seq_printf(m, "PCU interrupt enable:\t%08x\n",
736 I915_READ(GEN8_PCU_IER));
737 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 738 seq_printf(m, "Display IER:\t%08x\n",
739 I915_READ(VLV_IER));
740 seq_printf(m, "Display IIR:\t%08x\n",
741 I915_READ(VLV_IIR));
742 seq_printf(m, "Display IIR_RW:\t%08x\n",
743 I915_READ(VLV_IIR_RW));
744 seq_printf(m, "Display IMR:\t%08x\n",
745 I915_READ(VLV_IMR));
746 for_each_pipe(pipe)
747 seq_printf(m, "Pipe %c stat:\t%08x\n",
748 pipe_name(pipe),
749 I915_READ(PIPESTAT(pipe)));
750
751 seq_printf(m, "Master IER:\t%08x\n",
752 I915_READ(VLV_MASTER_IER));
753
754 seq_printf(m, "Render IER:\t%08x\n",
755 I915_READ(GTIER));
756 seq_printf(m, "Render IIR:\t%08x\n",
757 I915_READ(GTIIR));
758 seq_printf(m, "Render IMR:\t%08x\n",
759 I915_READ(GTIMR));
760
761 seq_printf(m, "PM IER:\t\t%08x\n",
762 I915_READ(GEN6_PMIER));
763 seq_printf(m, "PM IIR:\t\t%08x\n",
764 I915_READ(GEN6_PMIIR));
765 seq_printf(m, "PM IMR:\t\t%08x\n",
766 I915_READ(GEN6_PMIMR));
767
768 seq_printf(m, "Port hotplug:\t%08x\n",
769 I915_READ(PORT_HOTPLUG_EN));
770 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
771 I915_READ(VLV_DPFLIPSTAT));
772 seq_printf(m, "DPINVGTT:\t%08x\n",
773 I915_READ(DPINVGTT));
774
775 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 776 seq_printf(m, "Interrupt enable: %08x\n",
777 I915_READ(IER));
778 seq_printf(m, "Interrupt identity: %08x\n",
779 I915_READ(IIR));
780 seq_printf(m, "Interrupt mask: %08x\n",
781 I915_READ(IMR));
9db4a9c7
JB		 782 for_each_pipe(pipe)
783 seq_printf(m, "Pipe %c stat: %08x\n",
784 pipe_name(pipe),
785 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 786 } else {
787 seq_printf(m, "North Display Interrupt enable: %08x\n",
788 I915_READ(DEIER));
789 seq_printf(m, "North Display Interrupt identity: %08x\n",
790 I915_READ(DEIIR));
791 seq_printf(m, "North Display Interrupt mask: %08x\n",
792 I915_READ(DEIMR));
793 seq_printf(m, "South Display Interrupt enable: %08x\n",
794 I915_READ(SDEIER));
795 seq_printf(m, "South Display Interrupt identity: %08x\n",
796 I915_READ(SDEIIR));
797 seq_printf(m, "South Display Interrupt mask: %08x\n",
798 I915_READ(SDEIMR));
799 seq_printf(m, "Graphics Interrupt enable: %08x\n",
800 I915_READ(GTIER));
801 seq_printf(m, "Graphics Interrupt identity: %08x\n",
802 I915_READ(GTIIR));
803 seq_printf(m, "Graphics Interrupt mask: %08x\n",
804 I915_READ(GTIMR));
805 }
a2c7f6fd 806 for_each_ring(ring, dev_priv, i) {
a123f157 807 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 808 seq_printf(m,
809 "Graphics Interrupt mask (%s): %08x\n",
810 ring->name, I915_READ_IMR(ring));
9862e600 811 }
a2c7f6fd 812 i915_ring_seqno_info(m, ring);
9862e600 813 }
c8c8fb33 814 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 815 mutex_unlock(&dev->struct_mutex);
816
2017263e
BG		 817 return 0;
818}
819
a6172a80
CW		 820static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
821{
9f25d007 822 struct drm_info_node *node = m->private;
a6172a80 823 struct drm_device *dev = node->minor->dev;
e277a1f8 824 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 825 int i, ret;
826
827 ret = mutex_lock_interruptible(&dev->struct_mutex);
828 if (ret)
829 return ret;
a6172a80
CW		 830
831 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
832 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
833 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 834 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 835
6c085a72
CW		 836 seq_printf(m, "Fence %d, pin count = %d, object = ",
837 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 838 if (obj == NULL)
267f0c90 839 seq_puts(m, "unused");
c2c347a9 840 else
05394f39 841 describe_obj(m, obj);
267f0c90 842 seq_putc(m, '\n');
a6172a80
CW		 843 }
844
05394f39 845 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 846 return 0;
847}
848
2017263e
BG		 849static int i915_hws_info(struct seq_file *m, void *data)
850{
9f25d007 851 struct drm_info_node *node = m->private;
2017263e 852 struct drm_device *dev = node->minor->dev;
e277a1f8 853 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 854 struct intel_engine_cs *ring;
1a240d4d 855 const u32 *hws;
4066c0ae
CW		 856 int i;
857
1ec14ad3 858 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 859 hws = ring->status_page.page_addr;
2017263e
BG		 860 if (hws == NULL)
861 return 0;
862
863 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
864 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
865 i * 4,
866 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
867 }
868 return 0;
869}
870
d5442303
DV		 871static ssize_t
872i915_error_state_write(struct file *filp,
873 const char __user *ubuf,
874 size_t cnt,
875 loff_t *ppos)
876{
edc3d884 877 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 878 struct drm_device *dev = error_priv->dev;
22bcfc6a 879 int ret;
d5442303
DV		 880
881 DRM_DEBUG_DRIVER("Resetting error state\n");
882
22bcfc6a
DV		 883 ret = mutex_lock_interruptible(&dev->struct_mutex);
884 if (ret)
885 return ret;
886
d5442303
DV		 887 i915_destroy_error_state(dev);
888 mutex_unlock(&dev->struct_mutex);
889
890 return cnt;
891}
892
893static int i915_error_state_open(struct inode *inode, struct file *file)
894{
895 struct drm_device *dev = inode->i_private;
d5442303 896 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 897
898 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
899 if (!error_priv)
900 return -ENOMEM;
901
902 error_priv->dev = dev;
903
95d5bfb3 904 i915_error_state_get(dev, error_priv);
d5442303 905
edc3d884
MK		 906 file->private_data = error_priv;
907
908 return 0;
d5442303
DV		 909}
910
911static int i915_error_state_release(struct inode *inode, struct file *file)
912{
edc3d884 913 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 914
95d5bfb3 915 i915_error_state_put(error_priv);
d5442303
DV		 916 kfree(error_priv);
917
edc3d884
MK		 918 return 0;
919}
920
4dc955f7
MK		 921static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
922 size_t count, loff_t *pos)
923{
924 struct i915_error_state_file_priv *error_priv = file->private_data;
925 struct drm_i915_error_state_buf error_str;
926 loff_t tmp_pos = 0;
927 ssize_t ret_count = 0;
928 int ret;
929
930 ret = i915_error_state_buf_init(&error_str, count, *pos);
931 if (ret)
932 return ret;
edc3d884 933
fc16b48b 934 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 935 if (ret)
936 goto out;
937
edc3d884
MK		 938 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
939 error_str.buf,
940 error_str.bytes);
941
942 if (ret_count < 0)
943 ret = ret_count;
944 else
945 *pos = error_str.start + ret_count;
946out:
4dc955f7 947 i915_error_state_buf_release(&error_str);
edc3d884 948 return ret ?: ret_count;
d5442303
DV		 949}
950
951static const struct file_operations i915_error_state_fops = {
952 .owner = THIS_MODULE,
953 .open = i915_error_state_open,
edc3d884 954 .read = i915_error_state_read,
d5442303
DV		 955 .write = i915_error_state_write,
956 .llseek = default_llseek,
957 .release = i915_error_state_release,
958};
959
647416f9
KC		 960static int
961i915_next_seqno_get(void *data, u64 *val)
40633219 962{
647416f9 963 struct drm_device *dev = data;
e277a1f8 964 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 965 int ret;
966
967 ret = mutex_lock_interruptible(&dev->struct_mutex);
968 if (ret)
969 return ret;
970
647416f9 971 *val = dev_priv->next_seqno;
40633219
MK		 972 mutex_unlock(&dev->struct_mutex);
973
647416f9 974 return 0;
40633219
MK		 975}
976
647416f9
KC		 977static int
978i915_next_seqno_set(void *data, u64 val)
979{
980 struct drm_device *dev = data;
40633219
MK		 981 int ret;
982
40633219
MK		 983 ret = mutex_lock_interruptible(&dev->struct_mutex);
984 if (ret)
985 return ret;
986
e94fbaa8 987 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 988 mutex_unlock(&dev->struct_mutex);
989
647416f9 990 return ret;
40633219
MK		 991}
992
647416f9
KC		 993DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
994 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 995 "0x%llx\n");
40633219 996
f97108d1
JB		 997static int i915_rstdby_delays(struct seq_file *m, void *unused)
998{
9f25d007 999 struct drm_info_node *node = m->private;
f97108d1 1000 struct drm_device *dev = node->minor->dev;
e277a1f8 1001 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1002 u16 crstanddelay;
1003 int ret;
1004
1005 ret = mutex_lock_interruptible(&dev->struct_mutex);
1006 if (ret)
1007 return ret;
c8c8fb33 1008 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1009
1010 crstanddelay = I915_READ16(CRSTANDVID);
1011
c8c8fb33 1012 intel_runtime_pm_put(dev_priv);
616fdb5a 1013 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1014
1015 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1016
1017 return 0;
1018}
1019
adb4bd12 1020static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1021{
9f25d007 1022 struct drm_info_node *node = m->private;
f97108d1 1023 struct drm_device *dev = node->minor->dev;
e277a1f8 1024 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1025 int ret = 0;
1026
1027 intel_runtime_pm_get(dev_priv);
3b8d8d91 1028
5c9669ce
TR		 1029 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1030
3b8d8d91
JB		 1031 if (IS_GEN5(dev)) {
1032 u16 rgvswctl = I915_READ16(MEMSWCTL);
1033 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1034
1035 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1036 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1037 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1038 MEMSTAT_VID_SHIFT);
1039 seq_printf(m, "Current P-state: %d\n",
1040 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1041 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1042 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1043 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1044 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1045 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1046 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1047 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1048 u32 rpupei, rpcurup, rpprevup;
1049 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 1050 int max_freq;
1051
1052 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1053 ret = mutex_lock_interruptible(&dev->struct_mutex);
1054 if (ret)
c8c8fb33 1055 goto out;
d1ebd816 1056
c8d9a590 1057 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1058
8e8c06cd
CW		 1059 reqf = I915_READ(GEN6_RPNSWREQ);
1060 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1061 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1062 reqf >>= 24;
1063 else
1064 reqf >>= 25;
1065 reqf *= GT_FREQUENCY_MULTIPLIER;
1066
0d8f9491
CW		 1067 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1068 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1069 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1070
ccab5c82
JB		 1071 rpstat = I915_READ(GEN6_RPSTAT1);
1072 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1073 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1074 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1075 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1076 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1077 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1078 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1079 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1080 else
1081 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1082 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1083
c8d9a590 1084 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1085 mutex_unlock(&dev->struct_mutex);
1086
0d8f9491
CW		 1087 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1088 I915_READ(GEN6_PMIER),
1089 I915_READ(GEN6_PMIMR),
1090 I915_READ(GEN6_PMISR),
1091 I915_READ(GEN6_PMIIR),
1092 I915_READ(GEN6_PMINTRMSK));
3b8d8d91 1093 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1094 seq_printf(m, "Render p-state ratio: %d\n",
1095 (gt_perf_status & 0xff00) >> 8);
1096 seq_printf(m, "Render p-state VID: %d\n",
1097 gt_perf_status & 0xff);
1098 seq_printf(m, "Render p-state limit: %d\n",
1099 rp_state_limits & 0xff);
0d8f9491
CW		 1100 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1101 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1102 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1103 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1104 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1105 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1106 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1107 GEN6_CURICONT_MASK);
1108 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1109 GEN6_CURBSYTAVG_MASK);
1110 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1111 GEN6_CURBSYTAVG_MASK);
1112 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1113 GEN6_CURIAVG_MASK);
1114 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1115 GEN6_CURBSYTAVG_MASK);
1116 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1117 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1118
1119 max_freq = (rp_state_cap & 0xff0000) >> 16;
1120 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1121 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1122
1123 max_freq = (rp_state_cap & 0xff00) >> 8;
1124 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1125 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1126
1127 max_freq = rp_state_cap & 0xff;
1128 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1129 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1130
1131 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1132 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1133 } else if (IS_VALLEYVIEW(dev)) {
1134 u32 freq_sts, val;
1135
259bd5d4 1136 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1137 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1138 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1139 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1140
c5bd2bf6 1141 val = valleyview_rps_max_freq(dev_priv);
0a073b84 1142 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 1143 vlv_gpu_freq(dev_priv, val));
0a073b84 1144
c5bd2bf6 1145 val = valleyview_rps_min_freq(dev_priv);
0a073b84 1146 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 1147 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 1148
1149 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1150 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1151 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1152 } else {
267f0c90 1153 seq_puts(m, "no P-state info available\n");
3b8d8d91 1154 }
f97108d1 1155
c8c8fb33
PZ		 1156out:
1157 intel_runtime_pm_put(dev_priv);
1158 return ret;
f97108d1
JB		 1159}
1160
1161static int i915_delayfreq_table(struct seq_file *m, void *unused)
1162{
9f25d007 1163 struct drm_info_node *node = m->private;
f97108d1 1164 struct drm_device *dev = node->minor->dev;
e277a1f8 1165 struct drm_i915_private *dev_priv = dev->dev_private;
f97108d1 1166 u32 delayfreq;
616fdb5a
BW		 1167 int ret, i;
1168
1169 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170 if (ret)
1171 return ret;
c8c8fb33 1172 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1173
1174 for (i = 0; i < 16; i++) {
1175 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1176 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1177 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1178 }
1179
c8c8fb33
PZ		 1180 intel_runtime_pm_put(dev_priv);
1181
616fdb5a
BW		 1182 mutex_unlock(&dev->struct_mutex);
1183
f97108d1
JB		 1184 return 0;
1185}
1186
1187static inline int MAP_TO_MV(int map)
1188{
1189 return 1250 - (map * 25);
1190}
1191
1192static int i915_inttoext_table(struct seq_file *m, void *unused)
1193{
9f25d007 1194 struct drm_info_node *node = m->private;
f97108d1 1195 struct drm_device *dev = node->minor->dev;
e277a1f8 1196 struct drm_i915_private *dev_priv = dev->dev_private;
f97108d1 1197 u32 inttoext;
616fdb5a
BW		 1198 int ret, i;
1199
1200 ret = mutex_lock_interruptible(&dev->struct_mutex);
1201 if (ret)
1202 return ret;
c8c8fb33 1203 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1204
1205 for (i = 1; i <= 32; i++) {
1206 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1207 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1208 }
1209
c8c8fb33 1210 intel_runtime_pm_put(dev_priv);
616fdb5a
BW		 1211 mutex_unlock(&dev->struct_mutex);
1212
f97108d1
JB		 1213 return 0;
1214}
1215
4d85529d 1216static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1217{
9f25d007 1218 struct drm_info_node *node = m->private;
f97108d1 1219 struct drm_device *dev = node->minor->dev;
e277a1f8 1220 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1221 u32 rgvmodectl, rstdbyctl;
1222 u16 crstandvid;
1223 int ret;
1224
1225 ret = mutex_lock_interruptible(&dev->struct_mutex);
1226 if (ret)
1227 return ret;
c8c8fb33 1228 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1229
1230 rgvmodectl = I915_READ(MEMMODECTL);
1231 rstdbyctl = I915_READ(RSTDBYCTL);
1232 crstandvid = I915_READ16(CRSTANDVID);
1233
c8c8fb33 1234 intel_runtime_pm_put(dev_priv);
616fdb5a 1235 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1236
1237 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1238 "yes" : "no");
1239 seq_printf(m, "Boost freq: %d\n",
1240 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1241 MEMMODE_BOOST_FREQ_SHIFT);
1242 seq_printf(m, "HW control enabled: %s\n",
1243 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1244 seq_printf(m, "SW control enabled: %s\n",
1245 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1246 seq_printf(m, "Gated voltage change: %s\n",
1247 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1248 seq_printf(m, "Starting frequency: P%d\n",
1249 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1250 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1251 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1252 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1253 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1254 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1255 seq_printf(m, "Render standby enabled: %s\n",
1256 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1257 seq_puts(m, "Current RS state: ");
88271da3
JB		 1258 switch (rstdbyctl & RSX_STATUS_MASK) {
1259 case RSX_STATUS_ON:
267f0c90 1260 seq_puts(m, "on\n");
88271da3
JB		 1261 break;
1262 case RSX_STATUS_RC1:
267f0c90 1263 seq_puts(m, "RC1\n");
88271da3
JB		 1264 break;
1265 case RSX_STATUS_RC1E:
267f0c90 1266 seq_puts(m, "RC1E\n");
88271da3
JB		 1267 break;
1268 case RSX_STATUS_RS1:
267f0c90 1269 seq_puts(m, "RS1\n");
88271da3
JB		 1270 break;
1271 case RSX_STATUS_RS2:
267f0c90 1272 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1273 break;
1274 case RSX_STATUS_RS3:
267f0c90 1275 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1276 break;
1277 default:
267f0c90 1278 seq_puts(m, "unknown\n");
88271da3
JB		 1279 break;
1280 }
f97108d1
JB		 1281
1282 return 0;
1283}
1284
669ab5aa
D		 1285static int vlv_drpc_info(struct seq_file *m)
1286{
1287
9f25d007 1288 struct drm_info_node *node = m->private;
669ab5aa
D		 1289 struct drm_device *dev = node->minor->dev;
1290 struct drm_i915_private *dev_priv = dev->dev_private;
1291 u32 rpmodectl1, rcctl1;
1292 unsigned fw_rendercount = 0, fw_mediacount = 0;
1293
d46c0517
ID		 1294 intel_runtime_pm_get(dev_priv);
1295
669ab5aa
D		 1296 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1297 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1298
d46c0517
ID		 1299 intel_runtime_pm_put(dev_priv);
1300
669ab5aa
D		 1301 seq_printf(m, "Video Turbo Mode: %s\n",
1302 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1303 seq_printf(m, "Turbo enabled: %s\n",
1304 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1305 seq_printf(m, "HW control enabled: %s\n",
1306 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1307 seq_printf(m, "SW control enabled: %s\n",
1308 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1309 GEN6_RP_MEDIA_SW_MODE));
1310 seq_printf(m, "RC6 Enabled: %s\n",
1311 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1312 GEN6_RC_CTL_EI_MODE(1))));
1313 seq_printf(m, "Render Power Well: %s\n",
1314 (I915_READ(VLV_GTLC_PW_STATUS) &
1315 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1316 seq_printf(m, "Media Power Well: %s\n",
1317 (I915_READ(VLV_GTLC_PW_STATUS) &
1318 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1319
9cc19be5
ID		 1320 seq_printf(m, "Render RC6 residency since boot: %u\n",
1321 I915_READ(VLV_GT_RENDER_RC6));
1322 seq_printf(m, "Media RC6 residency since boot: %u\n",
1323 I915_READ(VLV_GT_MEDIA_RC6));
1324
669ab5aa
D		 1325 spin_lock_irq(&dev_priv->uncore.lock);
1326 fw_rendercount = dev_priv->uncore.fw_rendercount;
1327 fw_mediacount = dev_priv->uncore.fw_mediacount;
1328 spin_unlock_irq(&dev_priv->uncore.lock);
1329
1330 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1331 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1332
1333
1334 return 0;
1335}
1336
1337
4d85529d
BW		 1338static int gen6_drpc_info(struct seq_file *m)
1339{
1340
9f25d007 1341 struct drm_info_node *node = m->private;
4d85529d
BW		 1342 struct drm_device *dev = node->minor->dev;
1343 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1344 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1345 unsigned forcewake_count;
aee56cff 1346 int count = 0, ret;
4d85529d
BW		 1347
1348 ret = mutex_lock_interruptible(&dev->struct_mutex);
1349 if (ret)
1350 return ret;
c8c8fb33 1351 intel_runtime_pm_get(dev_priv);
4d85529d 1352
907b28c5
CW		 1353 spin_lock_irq(&dev_priv->uncore.lock);
1354 forcewake_count = dev_priv->uncore.forcewake_count;
1355 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1356
1357 if (forcewake_count) {
267f0c90
DL		 1358 seq_puts(m, "RC information inaccurate because somebody "
1359 "holds a forcewake reference \n");
4d85529d
BW		 1360 } else {
1361 /* NB: we cannot use forcewake, else we read the wrong values */
1362 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1363 udelay(10);
1364 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1365 }
1366
1367 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1368 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1369
1370 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1371 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1372 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1373 mutex_lock(&dev_priv->rps.hw_lock);
1374 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1375 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1376
c8c8fb33
PZ		 1377 intel_runtime_pm_put(dev_priv);
1378
4d85529d
BW		 1379 seq_printf(m, "Video Turbo Mode: %s\n",
1380 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1381 seq_printf(m, "HW control enabled: %s\n",
1382 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1383 seq_printf(m, "SW control enabled: %s\n",
1384 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1385 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1386 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1387 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1388 seq_printf(m, "RC6 Enabled: %s\n",
1389 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1390 seq_printf(m, "Deep RC6 Enabled: %s\n",
1391 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1392 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1393 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1394 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1395 switch (gt_core_status & GEN6_RCn_MASK) {
1396 case GEN6_RC0:
1397 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1398 seq_puts(m, "Core Power Down\n");
4d85529d 1399 else
267f0c90 1400 seq_puts(m, "on\n");
4d85529d
BW		 1401 break;
1402 case GEN6_RC3:
267f0c90 1403 seq_puts(m, "RC3\n");
4d85529d
BW		 1404 break;
1405 case GEN6_RC6:
267f0c90 1406 seq_puts(m, "RC6\n");
4d85529d
BW		 1407 break;
1408 case GEN6_RC7:
267f0c90 1409 seq_puts(m, "RC7\n");
4d85529d
BW		 1410 break;
1411 default:
267f0c90 1412 seq_puts(m, "Unknown\n");
4d85529d
BW		 1413 break;
1414 }
1415
1416 seq_printf(m, "Core Power Down: %s\n",
1417 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1418
1419 /* Not exactly sure what this is */
1420 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1421 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1422 seq_printf(m, "RC6 residency since boot: %u\n",
1423 I915_READ(GEN6_GT_GFX_RC6));
1424 seq_printf(m, "RC6+ residency since boot: %u\n",
1425 I915_READ(GEN6_GT_GFX_RC6p));
1426 seq_printf(m, "RC6++ residency since boot: %u\n",
1427 I915_READ(GEN6_GT_GFX_RC6pp));
1428
ecd8faea
BW		 1429 seq_printf(m, "RC6 voltage: %dmV\n",
1430 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1431 seq_printf(m, "RC6+ voltage: %dmV\n",
1432 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1433 seq_printf(m, "RC6++ voltage: %dmV\n",
1434 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1435 return 0;
1436}
1437
1438static int i915_drpc_info(struct seq_file *m, void *unused)
1439{
9f25d007 1440 struct drm_info_node *node = m->private;
4d85529d
BW		 1441 struct drm_device *dev = node->minor->dev;
1442
669ab5aa
D		 1443 if (IS_VALLEYVIEW(dev))
1444 return vlv_drpc_info(m);
1445 else if (IS_GEN6(dev) || IS_GEN7(dev))
4d85529d
BW		 1446 return gen6_drpc_info(m);
1447 else
1448 return ironlake_drpc_info(m);
1449}
1450
b5e50c3f
JB		 1451static int i915_fbc_status(struct seq_file *m, void *unused)
1452{
9f25d007 1453 struct drm_info_node *node = m->private;
b5e50c3f 1454 struct drm_device *dev = node->minor->dev;
e277a1f8 1455 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1456
3a77c4c4 1457 if (!HAS_FBC(dev)) {
267f0c90 1458 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1459 return 0;
1460 }
1461
36623ef8
PZ		 1462 intel_runtime_pm_get(dev_priv);
1463
ee5382ae 1464 if (intel_fbc_enabled(dev)) {
267f0c90 1465 seq_puts(m, "FBC enabled\n");
b5e50c3f 1466 } else {
267f0c90 1467 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1468 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1469 case FBC_OK:
1470 seq_puts(m, "FBC actived, but currently disabled in hardware");
1471 break;
1472 case FBC_UNSUPPORTED:
1473 seq_puts(m, "unsupported by this chipset");
1474 break;
bed4a673 1475 case FBC_NO_OUTPUT:
267f0c90 1476 seq_puts(m, "no outputs");
bed4a673 1477 break;
b5e50c3f 1478 case FBC_STOLEN_TOO_SMALL:
267f0c90 1479 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1480 break;
1481 case FBC_UNSUPPORTED_MODE:
267f0c90 1482 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1483 break;
1484 case FBC_MODE_TOO_LARGE:
267f0c90 1485 seq_puts(m, "mode too large");
b5e50c3f
JB		 1486 break;
1487 case FBC_BAD_PLANE:
267f0c90 1488 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1489 break;
1490 case FBC_NOT_TILED:
267f0c90 1491 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1492 break;
9c928d16 1493 case FBC_MULTIPLE_PIPES:
267f0c90 1494 seq_puts(m, "multiple pipes are enabled");
9c928d16 1495 break;
c1a9f047 1496 case FBC_MODULE_PARAM:
267f0c90 1497 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1498 break;
8a5729a3 1499 case FBC_CHIP_DEFAULT:
267f0c90 1500 seq_puts(m, "disabled per chip default");
8a5729a3 1501 break;
b5e50c3f 1502 default:
267f0c90 1503 seq_puts(m, "unknown reason");
b5e50c3f 1504 }
267f0c90 1505 seq_putc(m, '\n');
b5e50c3f 1506 }
36623ef8
PZ		 1507
1508 intel_runtime_pm_put(dev_priv);
1509
b5e50c3f
JB		 1510 return 0;
1511}
1512
92d44621
PZ		 1513static int i915_ips_status(struct seq_file *m, void *unused)
1514{
9f25d007 1515 struct drm_info_node *node = m->private;
92d44621
PZ		 1516 struct drm_device *dev = node->minor->dev;
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518
f5adf94e 1519 if (!HAS_IPS(dev)) {
92d44621
PZ		 1520 seq_puts(m, "not supported\n");
1521 return 0;
1522 }
1523
36623ef8
PZ		 1524 intel_runtime_pm_get(dev_priv);
1525
e59150dc 1526 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
92d44621
PZ		 1527 seq_puts(m, "enabled\n");
1528 else
1529 seq_puts(m, "disabled\n");
1530
36623ef8
PZ		 1531 intel_runtime_pm_put(dev_priv);
1532
92d44621
PZ		 1533 return 0;
1534}
1535
4a9bef37
JB		 1536static int i915_sr_status(struct seq_file *m, void *unused)
1537{
9f25d007 1538 struct drm_info_node *node = m->private;
4a9bef37 1539 struct drm_device *dev = node->minor->dev;
e277a1f8 1540 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1541 bool sr_enabled = false;
1542
36623ef8
PZ		 1543 intel_runtime_pm_get(dev_priv);
1544
1398261a 1545 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1546 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1547 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1548 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1549 else if (IS_I915GM(dev))
1550 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1551 else if (IS_PINEVIEW(dev))
1552 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1553
36623ef8
PZ		 1554 intel_runtime_pm_put(dev_priv);
1555
5ba2aaaa
CW		 1556 seq_printf(m, "self-refresh: %s\n",
1557 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1558
1559 return 0;
1560}
1561
7648fa99
JB		 1562static int i915_emon_status(struct seq_file *m, void *unused)
1563{
9f25d007 1564 struct drm_info_node *node = m->private;
7648fa99 1565 struct drm_device *dev = node->minor->dev;
e277a1f8 1566 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1567 unsigned long temp, chipset, gfx;
de227ef0
CW		 1568 int ret;
1569
582be6b4
CW		 1570 if (!IS_GEN5(dev))
1571 return -ENODEV;
1572
de227ef0
CW		 1573 ret = mutex_lock_interruptible(&dev->struct_mutex);
1574 if (ret)
1575 return ret;
7648fa99
JB		 1576
1577 temp = i915_mch_val(dev_priv);
1578 chipset = i915_chipset_val(dev_priv);
1579 gfx = i915_gfx_val(dev_priv);
de227ef0 1580 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1581
1582 seq_printf(m, "GMCH temp: %ld\n", temp);
1583 seq_printf(m, "Chipset power: %ld\n", chipset);
1584 seq_printf(m, "GFX power: %ld\n", gfx);
1585 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1586
1587 return 0;
1588}
1589
23b2f8bb
JB		 1590static int i915_ring_freq_table(struct seq_file *m, void *unused)
1591{
9f25d007 1592 struct drm_info_node *node = m->private;
23b2f8bb 1593 struct drm_device *dev = node->minor->dev;
e277a1f8 1594 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1595 int ret = 0;
23b2f8bb
JB		 1596 int gpu_freq, ia_freq;
1597
1c70c0ce 1598 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1599 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1600 return 0;
1601 }
1602
5bfa0199
PZ		 1603 intel_runtime_pm_get(dev_priv);
1604
5c9669ce
TR		 1605 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1606
4fc688ce 1607 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1608 if (ret)
5bfa0199 1609 goto out;
23b2f8bb 1610
267f0c90 1611 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1612
b39fb297
BW		 1613 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1614 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1615 gpu_freq++) {
42c0526c
BW		 1616 ia_freq = gpu_freq;
1617 sandybridge_pcode_read(dev_priv,
1618 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1619 &ia_freq);
3ebecd07
CW		 1620 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1621 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1622 ((ia_freq >> 0) & 0xff) * 100,
1623 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1624 }
1625
4fc688ce 1626 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1627
5bfa0199
PZ		 1628out:
1629 intel_runtime_pm_put(dev_priv);
1630 return ret;
23b2f8bb
JB		 1631}
1632
7648fa99
JB		 1633static int i915_gfxec(struct seq_file *m, void *unused)
1634{
9f25d007 1635 struct drm_info_node *node = m->private;
7648fa99 1636 struct drm_device *dev = node->minor->dev;
e277a1f8 1637 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1638 int ret;
1639
1640 ret = mutex_lock_interruptible(&dev->struct_mutex);
1641 if (ret)
1642 return ret;
c8c8fb33 1643 intel_runtime_pm_get(dev_priv);
7648fa99
JB		 1644
1645 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
c8c8fb33 1646 intel_runtime_pm_put(dev_priv);
7648fa99 1647
616fdb5a
BW		 1648 mutex_unlock(&dev->struct_mutex);
1649
7648fa99
JB		 1650 return 0;
1651}
1652
44834a67
CW		 1653static int i915_opregion(struct seq_file *m, void *unused)
1654{
9f25d007 1655 struct drm_info_node *node = m->private;
44834a67 1656 struct drm_device *dev = node->minor->dev;
e277a1f8 1657 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1658 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1659 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1660 int ret;
1661
0d38f009
DV		 1662 if (data == NULL)
1663 return -ENOMEM;
1664
44834a67
CW		 1665 ret = mutex_lock_interruptible(&dev->struct_mutex);
1666 if (ret)
0d38f009 1667 goto out;
44834a67 1668
0d38f009
DV		 1669 if (opregion->header) {
1670 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1671 seq_write(m, data, OPREGION_SIZE);
1672 }
44834a67
CW		 1673
1674 mutex_unlock(&dev->struct_mutex);
1675
0d38f009
DV		 1676out:
1677 kfree(data);
44834a67
CW		 1678 return 0;
1679}
1680
37811fcc
CW		 1681static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1682{
9f25d007 1683 struct drm_info_node *node = m->private;
37811fcc 1684 struct drm_device *dev = node->minor->dev;
4520f53a 1685 struct intel_fbdev *ifbdev = NULL;
37811fcc 1686 struct intel_framebuffer *fb;
37811fcc 1687
4520f53a
DV		 1688#ifdef CONFIG_DRM_I915_FBDEV
1689 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1690
1691 ifbdev = dev_priv->fbdev;
1692 fb = to_intel_framebuffer(ifbdev->helper.fb);
1693
623f9783 1694 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1695 fb->base.width,
1696 fb->base.height,
1697 fb->base.depth,
623f9783
DV		 1698 fb->base.bits_per_pixel,
1699 atomic_read(&fb->base.refcount.refcount));
05394f39 1700 describe_obj(m, fb->obj);
267f0c90 1701 seq_putc(m, '\n');
4520f53a 1702#endif
37811fcc 1703
4b096ac1 1704 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1705 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1706 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1707 continue;
1708
623f9783 1709 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1710 fb->base.width,
1711 fb->base.height,
1712 fb->base.depth,
623f9783
DV		 1713 fb->base.bits_per_pixel,
1714 atomic_read(&fb->base.refcount.refcount));
05394f39 1715 describe_obj(m, fb->obj);
267f0c90 1716 seq_putc(m, '\n');
37811fcc 1717 }
4b096ac1 1718 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1719
1720 return 0;
1721}
1722
e76d3630
BW		 1723static int i915_context_status(struct seq_file *m, void *unused)
1724{
9f25d007 1725 struct drm_info_node *node = m->private;
e76d3630 1726 struct drm_device *dev = node->minor->dev;
e277a1f8 1727 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1728 struct intel_engine_cs *ring;
273497e5 1729 struct intel_context *ctx;
a168c293 1730 int ret, i;
e76d3630 1731
f3d28878 1732 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1733 if (ret)
1734 return ret;
1735
3e373948 1736 if (dev_priv->ips.pwrctx) {
267f0c90 1737 seq_puts(m, "power context ");
3e373948 1738 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1739 seq_putc(m, '\n');
dc501fbc 1740 }
e76d3630 1741
3e373948 1742 if (dev_priv->ips.renderctx) {
267f0c90 1743 seq_puts(m, "render context ");
3e373948 1744 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1745 seq_putc(m, '\n');
dc501fbc 1746 }
e76d3630 1747
a33afea5 1748 list_for_each_entry(ctx, &dev_priv->context_list, link) {
b77f6997
CW		 1749 if (ctx->obj == NULL)
1750 continue;
1751
a33afea5 1752 seq_puts(m, "HW context ");
3ccfd19d 1753 describe_ctx(m, ctx);
a33afea5
BW		 1754 for_each_ring(ring, dev_priv, i)
1755 if (ring->default_context == ctx)
1756 seq_printf(m, "(default context %s) ", ring->name);
1757
1758 describe_obj(m, ctx->obj);
1759 seq_putc(m, '\n');
a168c293
BW		 1760 }
1761
f3d28878 1762 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1763
1764 return 0;
1765}
1766
6d794d42
BW		 1767static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1768{
9f25d007 1769 struct drm_info_node *node = m->private;
6d794d42
BW		 1770 struct drm_device *dev = node->minor->dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1772 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1773
907b28c5 1774 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1775 if (IS_VALLEYVIEW(dev)) {
1776 fw_rendercount = dev_priv->uncore.fw_rendercount;
1777 fw_mediacount = dev_priv->uncore.fw_mediacount;
1778 } else
1779 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1780 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1781
43709ba0
D		 1782 if (IS_VALLEYVIEW(dev)) {
1783 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1784 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1785 } else
1786 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1787
1788 return 0;
1789}
1790
ea16a3cd
DV		 1791static const char *swizzle_string(unsigned swizzle)
1792{
aee56cff 1793 switch (swizzle) {
ea16a3cd
DV		 1794 case I915_BIT_6_SWIZZLE_NONE:
1795 return "none";
1796 case I915_BIT_6_SWIZZLE_9:
1797 return "bit9";
1798 case I915_BIT_6_SWIZZLE_9_10:
1799 return "bit9/bit10";
1800 case I915_BIT_6_SWIZZLE_9_11:
1801 return "bit9/bit11";
1802 case I915_BIT_6_SWIZZLE_9_10_11:
1803 return "bit9/bit10/bit11";
1804 case I915_BIT_6_SWIZZLE_9_17:
1805 return "bit9/bit17";
1806 case I915_BIT_6_SWIZZLE_9_10_17:
1807 return "bit9/bit10/bit17";
1808 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1809 return "unknown";
ea16a3cd
DV		 1810 }
1811
1812 return "bug";
1813}
1814
1815static int i915_swizzle_info(struct seq_file *m, void *data)
1816{
9f25d007 1817 struct drm_info_node *node = m->private;
ea16a3cd
DV		 1818 struct drm_device *dev = node->minor->dev;
1819 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1820 int ret;
1821
1822 ret = mutex_lock_interruptible(&dev->struct_mutex);
1823 if (ret)
1824 return ret;
c8c8fb33 1825 intel_runtime_pm_get(dev_priv);
ea16a3cd 1826
ea16a3cd
DV		 1827 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1828 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1829 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1830 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1831
1832 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1833 seq_printf(m, "DDC = 0x%08x\n",
1834 I915_READ(DCC));
1835 seq_printf(m, "C0DRB3 = 0x%04x\n",
1836 I915_READ16(C0DRB3));
1837 seq_printf(m, "C1DRB3 = 0x%04x\n",
1838 I915_READ16(C1DRB3));
9d3203e1 1839 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1840 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1841 I915_READ(MAD_DIMM_C0));
1842 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1843 I915_READ(MAD_DIMM_C1));
1844 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1845 I915_READ(MAD_DIMM_C2));
1846 seq_printf(m, "TILECTL = 0x%08x\n",
1847 I915_READ(TILECTL));
9d3203e1
BW		 1848 if (IS_GEN8(dev))
1849 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1850 I915_READ(GAMTARBMODE));
1851 else
1852 seq_printf(m, "ARB_MODE = 0x%08x\n",
1853 I915_READ(ARB_MODE));
3fa7d235
DV		 1854 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1855 I915_READ(DISP_ARB_CTL));
ea16a3cd 1856 }
c8c8fb33 1857 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1858 mutex_unlock(&dev->struct_mutex);
1859
1860 return 0;
1861}
1862
1c60fef5
BW		 1863static int per_file_ctx(int id, void *ptr, void *data)
1864{
273497e5 1865 struct intel_context *ctx = ptr;
1c60fef5
BW		 1866 struct seq_file *m = data;
1867 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1868
f83d6518
OM		 1869 if (i915_gem_context_is_default(ctx))
1870 seq_puts(m, " default context:\n");
1871 else
1872 seq_printf(m, " context %d:\n", ctx->id);
1c60fef5
BW		 1873 ppgtt->debug_dump(ppgtt, m);
1874
1875 return 0;
1876}
1877
77df6772 1878static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1879{
3cf17fc5 1880 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1881 struct intel_engine_cs *ring;
77df6772
BW		 1882 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1883 int unused, i;
3cf17fc5 1884
77df6772
BW		 1885 if (!ppgtt)
1886 return;
1887
1888 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 1889 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 1890 for_each_ring(ring, dev_priv, unused) {
1891 seq_printf(m, "%s\n", ring->name);
1892 for (i = 0; i < 4; i++) {
1893 u32 offset = 0x270 + i * 8;
1894 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1895 pdp <<= 32;
1896 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 1897 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 1898 }
1899 }
1900}
1901
1902static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1903{
1904 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1905 struct intel_engine_cs *ring;
1c60fef5 1906 struct drm_file *file;
77df6772 1907 int i;
3cf17fc5 1908
3cf17fc5
DV		 1909 if (INTEL_INFO(dev)->gen == 6)
1910 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1911
a2c7f6fd 1912 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1913 seq_printf(m, "%s\n", ring->name);
1914 if (INTEL_INFO(dev)->gen == 7)
1915 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1916 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1917 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1918 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1919 }
1920 if (dev_priv->mm.aliasing_ppgtt) {
1921 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1922
267f0c90 1923 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 1924 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 1925
87d60b63 1926 ppgtt->debug_dump(ppgtt, m);
1c60fef5
BW		 1927 } else
1928 return;
1929
1930 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1931 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 1932
1c60fef5
BW		 1933 seq_printf(m, "proc: %s\n",
1934 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 1935 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 1936 }
1937 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1938}
1939
1940static int i915_ppgtt_info(struct seq_file *m, void *data)
1941{
9f25d007 1942 struct drm_info_node *node = m->private;
77df6772 1943 struct drm_device *dev = node->minor->dev;
c8c8fb33 1944 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 1945
1946 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1947 if (ret)
1948 return ret;
c8c8fb33 1949 intel_runtime_pm_get(dev_priv);
77df6772
BW		 1950
1951 if (INTEL_INFO(dev)->gen >= 8)
1952 gen8_ppgtt_info(m, dev);
1953 else if (INTEL_INFO(dev)->gen >= 6)
1954 gen6_ppgtt_info(m, dev);
1955
c8c8fb33 1956 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 1957 mutex_unlock(&dev->struct_mutex);
1958
1959 return 0;
1960}
1961
63573eb7
BW		 1962static int i915_llc(struct seq_file *m, void *data)
1963{
9f25d007 1964 struct drm_info_node *node = m->private;
63573eb7
BW		 1965 struct drm_device *dev = node->minor->dev;
1966 struct drm_i915_private *dev_priv = dev->dev_private;
1967
1968 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1969 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1970 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1971
1972 return 0;
1973}
1974
e91fd8c6
RV		 1975static int i915_edp_psr_status(struct seq_file *m, void *data)
1976{
1977 struct drm_info_node *node = m->private;
1978 struct drm_device *dev = node->minor->dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1980 u32 psrperf = 0;
1981 bool enabled = false;
e91fd8c6 1982
c8c8fb33
PZ		 1983 intel_runtime_pm_get(dev_priv);
1984
a031d709
RV		 1985 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1986 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
5755c78f
RV		 1987 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
1988 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
e91fd8c6 1989
a031d709
RV		 1990 enabled = HAS_PSR(dev) &&
1991 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
5755c78f 1992 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
e91fd8c6 1993
a031d709
RV		 1994 if (HAS_PSR(dev))
1995 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1996 EDP_PSR_PERF_CNT_MASK;
1997 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6 1998
c8c8fb33 1999 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2000 return 0;
2001}
2002
d2e216d0
RV		 2003static int i915_sink_crc(struct seq_file *m, void *data)
2004{
2005 struct drm_info_node *node = m->private;
2006 struct drm_device *dev = node->minor->dev;
2007 struct intel_encoder *encoder;
2008 struct intel_connector *connector;
2009 struct intel_dp *intel_dp = NULL;
2010 int ret;
2011 u8 crc[6];
2012
2013 drm_modeset_lock_all(dev);
2014 list_for_each_entry(connector, &dev->mode_config.connector_list,
2015 base.head) {
2016
2017 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2018 continue;
2019
b6ae3c7c
PZ		 2020 if (!connector->base.encoder)
2021 continue;
2022
d2e216d0
RV		 2023 encoder = to_intel_encoder(connector->base.encoder);
2024 if (encoder->type != INTEL_OUTPUT_EDP)
2025 continue;
2026
2027 intel_dp = enc_to_intel_dp(&encoder->base);
2028
2029 ret = intel_dp_sink_crc(intel_dp, crc);
2030 if (ret)
2031 goto out;
2032
2033 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2034 crc[0], crc[1], crc[2],
2035 crc[3], crc[4], crc[5]);
2036 goto out;
2037 }
2038 ret = -ENODEV;
2039out:
2040 drm_modeset_unlock_all(dev);
2041 return ret;
2042}
2043
ec013e7f
JB		 2044static int i915_energy_uJ(struct seq_file *m, void *data)
2045{
2046 struct drm_info_node *node = m->private;
2047 struct drm_device *dev = node->minor->dev;
2048 struct drm_i915_private *dev_priv = dev->dev_private;
2049 u64 power;
2050 u32 units;
2051
2052 if (INTEL_INFO(dev)->gen < 6)
2053 return -ENODEV;
2054
36623ef8
PZ		 2055 intel_runtime_pm_get(dev_priv);
2056
ec013e7f
JB		 2057 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2058 power = (power & 0x1f00) >> 8;
2059 units = 1000000 / (1 << power); /* convert to uJ */
2060 power = I915_READ(MCH_SECP_NRG_STTS);
2061 power *= units;
2062
36623ef8
PZ		 2063 intel_runtime_pm_put(dev_priv);
2064
ec013e7f 2065 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2066
2067 return 0;
2068}
2069
2070static int i915_pc8_status(struct seq_file *m, void *unused)
2071{
9f25d007 2072 struct drm_info_node *node = m->private;
371db66a
PZ		 2073 struct drm_device *dev = node->minor->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075
85b8d5c2 2076 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2077 seq_puts(m, "not supported\n");
2078 return 0;
2079 }
2080
86c4ec0d 2081 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2082 seq_printf(m, "IRQs disabled: %s\n",
5d584b2e 2083 yesno(dev_priv->pm.irqs_disabled));
371db66a 2084
ec013e7f
JB		 2085 return 0;
2086}
2087
1da51581
ID		 2088static const char *power_domain_str(enum intel_display_power_domain domain)
2089{
2090 switch (domain) {
2091 case POWER_DOMAIN_PIPE_A:
2092 return "PIPE_A";
2093 case POWER_DOMAIN_PIPE_B:
2094 return "PIPE_B";
2095 case POWER_DOMAIN_PIPE_C:
2096 return "PIPE_C";
2097 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2098 return "PIPE_A_PANEL_FITTER";
2099 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2100 return "PIPE_B_PANEL_FITTER";
2101 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2102 return "PIPE_C_PANEL_FITTER";
2103 case POWER_DOMAIN_TRANSCODER_A:
2104 return "TRANSCODER_A";
2105 case POWER_DOMAIN_TRANSCODER_B:
2106 return "TRANSCODER_B";
2107 case POWER_DOMAIN_TRANSCODER_C:
2108 return "TRANSCODER_C";
2109 case POWER_DOMAIN_TRANSCODER_EDP:
2110 return "TRANSCODER_EDP";
319be8ae
ID		 2111 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2112 return "PORT_DDI_A_2_LANES";
2113 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2114 return "PORT_DDI_A_4_LANES";
2115 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2116 return "PORT_DDI_B_2_LANES";
2117 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2118 return "PORT_DDI_B_4_LANES";
2119 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2120 return "PORT_DDI_C_2_LANES";
2121 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2122 return "PORT_DDI_C_4_LANES";
2123 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2124 return "PORT_DDI_D_2_LANES";
2125 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2126 return "PORT_DDI_D_4_LANES";
2127 case POWER_DOMAIN_PORT_DSI:
2128 return "PORT_DSI";
2129 case POWER_DOMAIN_PORT_CRT:
2130 return "PORT_CRT";
2131 case POWER_DOMAIN_PORT_OTHER:
2132 return "PORT_OTHER";
1da51581
ID		 2133 case POWER_DOMAIN_VGA:
2134 return "VGA";
2135 case POWER_DOMAIN_AUDIO:
2136 return "AUDIO";
2137 case POWER_DOMAIN_INIT:
2138 return "INIT";
2139 default:
2140 WARN_ON(1);
2141 return "?";
2142 }
2143}
2144
2145static int i915_power_domain_info(struct seq_file *m, void *unused)
2146{
9f25d007 2147 struct drm_info_node *node = m->private;
1da51581
ID		 2148 struct drm_device *dev = node->minor->dev;
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2151 int i;
2152
2153 mutex_lock(&power_domains->lock);
2154
2155 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2156 for (i = 0; i < power_domains->power_well_count; i++) {
2157 struct i915_power_well *power_well;
2158 enum intel_display_power_domain power_domain;
2159
2160 power_well = &power_domains->power_wells[i];
2161 seq_printf(m, "%-25s %d\n", power_well->name,
2162 power_well->count);
2163
2164 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2165 power_domain++) {
2166 if (!(BIT(power_domain) & power_well->domains))
2167 continue;
2168
2169 seq_printf(m, " %-23s %d\n",
2170 power_domain_str(power_domain),
2171 power_domains->domain_use_count[power_domain]);
2172 }
2173 }
2174
2175 mutex_unlock(&power_domains->lock);
2176
2177 return 0;
2178}
2179
53f5e3ca
JB		 2180static void intel_seq_print_mode(struct seq_file *m, int tabs,
2181 struct drm_display_mode *mode)
2182{
2183 int i;
2184
2185 for (i = 0; i < tabs; i++)
2186 seq_putc(m, '\t');
2187
2188 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2189 mode->base.id, mode->name,
2190 mode->vrefresh, mode->clock,
2191 mode->hdisplay, mode->hsync_start,
2192 mode->hsync_end, mode->htotal,
2193 mode->vdisplay, mode->vsync_start,
2194 mode->vsync_end, mode->vtotal,
2195 mode->type, mode->flags);
2196}
2197
2198static void intel_encoder_info(struct seq_file *m,
2199 struct intel_crtc *intel_crtc,
2200 struct intel_encoder *intel_encoder)
2201{
9f25d007 2202 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2203 struct drm_device *dev = node->minor->dev;
2204 struct drm_crtc *crtc = &intel_crtc->base;
2205 struct intel_connector *intel_connector;
2206 struct drm_encoder *encoder;
2207
2208 encoder = &intel_encoder->base;
2209 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2210 encoder->base.id, encoder->name);
53f5e3ca
JB		 2211 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2212 struct drm_connector *connector = &intel_connector->base;
2213 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2214 connector->base.id,
c23cc417 2215 connector->name,
53f5e3ca
JB		 2216 drm_get_connector_status_name(connector->status));
2217 if (connector->status == connector_status_connected) {
2218 struct drm_display_mode *mode = &crtc->mode;
2219 seq_printf(m, ", mode:\n");
2220 intel_seq_print_mode(m, 2, mode);
2221 } else {
2222 seq_putc(m, '\n');
2223 }
2224 }
2225}
2226
2227static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2228{
9f25d007 2229 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2230 struct drm_device *dev = node->minor->dev;
2231 struct drm_crtc *crtc = &intel_crtc->base;
2232 struct intel_encoder *intel_encoder;
2233
5aa8a937
MR		 2234 if (crtc->primary->fb)
2235 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2236 crtc->primary->fb->base.id, crtc->x, crtc->y,
2237 crtc->primary->fb->width, crtc->primary->fb->height);
2238 else
2239 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2240 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2241 intel_encoder_info(m, intel_crtc, intel_encoder);
2242}
2243
2244static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2245{
2246 struct drm_display_mode *mode = panel->fixed_mode;
2247
2248 seq_printf(m, "\tfixed mode:\n");
2249 intel_seq_print_mode(m, 2, mode);
2250}
2251
2252static void intel_dp_info(struct seq_file *m,
2253 struct intel_connector *intel_connector)
2254{
2255 struct intel_encoder *intel_encoder = intel_connector->encoder;
2256 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2257
2258 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2259 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2260 "no");
2261 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2262 intel_panel_info(m, &intel_connector->panel);
2263}
2264
2265static void intel_hdmi_info(struct seq_file *m,
2266 struct intel_connector *intel_connector)
2267{
2268 struct intel_encoder *intel_encoder = intel_connector->encoder;
2269 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2270
2271 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2272 "no");
2273}
2274
2275static void intel_lvds_info(struct seq_file *m,
2276 struct intel_connector *intel_connector)
2277{
2278 intel_panel_info(m, &intel_connector->panel);
2279}
2280
2281static void intel_connector_info(struct seq_file *m,
2282 struct drm_connector *connector)
2283{
2284 struct intel_connector *intel_connector = to_intel_connector(connector);
2285 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2286 struct drm_display_mode *mode;
53f5e3ca
JB		 2287
2288 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2289 connector->base.id, connector->name,
53f5e3ca
JB		 2290 drm_get_connector_status_name(connector->status));
2291 if (connector->status == connector_status_connected) {
2292 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2293 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2294 connector->display_info.width_mm,
2295 connector->display_info.height_mm);
2296 seq_printf(m, "\tsubpixel order: %s\n",
2297 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2298 seq_printf(m, "\tCEA rev: %d\n",
2299 connector->display_info.cea_rev);
2300 }
2301 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2302 intel_encoder->type == INTEL_OUTPUT_EDP)
2303 intel_dp_info(m, intel_connector);
2304 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2305 intel_hdmi_info(m, intel_connector);
2306 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2307 intel_lvds_info(m, intel_connector);
2308
f103fc7d
JB		 2309 seq_printf(m, "\tmodes:\n");
2310 list_for_each_entry(mode, &connector->modes, head)
2311 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2312}
2313
065f2ec2
CW		 2314static bool cursor_active(struct drm_device *dev, int pipe)
2315{
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2317 u32 state;
2318
2319 if (IS_845G(dev) || IS_I865G(dev))
2320 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2321 else
5efb3e28 2322 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2323
2324 return state;
2325}
2326
2327static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2328{
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 u32 pos;
2331
5efb3e28 2332 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2333
2334 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2335 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2336 *x = -*x;
2337
2338 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2339 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2340 *y = -*y;
2341
2342 return cursor_active(dev, pipe);
2343}
2344
53f5e3ca
JB		 2345static int i915_display_info(struct seq_file *m, void *unused)
2346{
9f25d007 2347 struct drm_info_node *node = m->private;
53f5e3ca 2348 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2349 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2350 struct intel_crtc *crtc;
53f5e3ca
JB		 2351 struct drm_connector *connector;
2352
b0e5ddf3 2353 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2354 drm_modeset_lock_all(dev);
2355 seq_printf(m, "CRTC info\n");
2356 seq_printf(m, "---------\n");
d3fcc808 2357 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2358 bool active;
2359 int x, y;
53f5e3ca 2360
57127efa 2361 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2362 crtc->base.base.id, pipe_name(crtc->pipe),
57127efa 2363 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
a23dc658 2364 if (crtc->active) {
065f2ec2
CW		 2365 intel_crtc_info(m, crtc);
2366
a23dc658 2367 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2368 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2369 yesno(crtc->cursor_base),
57127efa
CW		 2370 x, y, crtc->cursor_width, crtc->cursor_height,
2371 crtc->cursor_addr, yesno(active));
a23dc658 2372 }
cace841c
DV		 2373
2374 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2375 yesno(!crtc->cpu_fifo_underrun_disabled),
2376 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2377 }
2378
2379 seq_printf(m, "\n");
2380 seq_printf(m, "Connector info\n");
2381 seq_printf(m, "--------------\n");
2382 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2383 intel_connector_info(m, connector);
2384 }
2385 drm_modeset_unlock_all(dev);
b0e5ddf3 2386 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2387
2388 return 0;
2389}
2390
07144428
DL		 2391struct pipe_crc_info {
2392 const char *name;
2393 struct drm_device *dev;
2394 enum pipe pipe;
2395};
2396
2397static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2398{
be5c7a90
DL		 2399 struct pipe_crc_info *info = inode->i_private;
2400 struct drm_i915_private *dev_priv = info->dev->dev_private;
2401 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2402
7eb1c496
DV		 2403 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2404 return -ENODEV;
2405
d538bbdf
DL		 2406 spin_lock_irq(&pipe_crc->lock);
2407
2408 if (pipe_crc->opened) {
2409 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2410 return -EBUSY; /* already open */
2411 }
2412
d538bbdf 2413 pipe_crc->opened = true;
07144428
DL		 2414 filep->private_data = inode->i_private;
2415
d538bbdf
DL		 2416 spin_unlock_irq(&pipe_crc->lock);
2417
07144428
DL		 2418 return 0;
2419}
2420
2421static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2422{
be5c7a90
DL		 2423 struct pipe_crc_info *info = inode->i_private;
2424 struct drm_i915_private *dev_priv = info->dev->dev_private;
2425 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2426
d538bbdf
DL		 2427 spin_lock_irq(&pipe_crc->lock);
2428 pipe_crc->opened = false;
2429 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2430
07144428
DL		 2431 return 0;
2432}
2433
2434/* (6 fields, 8 chars each, space separated (5) + '\n') */
2435#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2436/* account for \'0' */
2437#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2438
2439static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2440{
d538bbdf
DL		 2441 assert_spin_locked(&pipe_crc->lock);
2442 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2443 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2444}
2445
2446static ssize_t
2447i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2448 loff_t *pos)
2449{
2450 struct pipe_crc_info *info = filep->private_data;
2451 struct drm_device *dev = info->dev;
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2454 char buf[PIPE_CRC_BUFFER_LEN];
2455 int head, tail, n_entries, n;
2456 ssize_t bytes_read;
2457
2458 /*
2459 * Don't allow user space to provide buffers not big enough to hold
2460 * a line of data.
2461 */
2462 if (count < PIPE_CRC_LINE_LEN)
2463 return -EINVAL;
2464
2465 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2466 return 0;
07144428
DL		 2467
2468 /* nothing to read */
d538bbdf 2469 spin_lock_irq(&pipe_crc->lock);
07144428 2470 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2471 int ret;
2472
2473 if (filep->f_flags & O_NONBLOCK) {
2474 spin_unlock_irq(&pipe_crc->lock);
07144428 2475 return -EAGAIN;
d538bbdf 2476 }
07144428 2477
d538bbdf
DL		 2478 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2479 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2480 if (ret) {
2481 spin_unlock_irq(&pipe_crc->lock);
2482 return ret;
2483 }
8bf1e9f1
SH		 2484 }
2485
07144428 2486 /* We now have one or more entries to read */
d538bbdf
DL		 2487 head = pipe_crc->head;
2488 tail = pipe_crc->tail;
07144428
DL		 2489 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2490 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2491 spin_unlock_irq(&pipe_crc->lock);
2492
07144428
DL		 2493 bytes_read = 0;
2494 n = 0;
2495 do {
b2c88f5b 2496 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2497 int ret;
8bf1e9f1 2498
07144428
DL		 2499 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2500 "%8u %8x %8x %8x %8x %8x\n",
2501 entry->frame, entry->crc[0],
2502 entry->crc[1], entry->crc[2],
2503 entry->crc[3], entry->crc[4]);
2504
2505 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2506 buf, PIPE_CRC_LINE_LEN);
2507 if (ret == PIPE_CRC_LINE_LEN)
2508 return -EFAULT;
b2c88f5b
DL		 2509
2510 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2511 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2512 n++;
2513 } while (--n_entries);
8bf1e9f1 2514
d538bbdf
DL		 2515 spin_lock_irq(&pipe_crc->lock);
2516 pipe_crc->tail = tail;
2517 spin_unlock_irq(&pipe_crc->lock);
2518
07144428
DL		 2519 return bytes_read;
2520}
2521
2522static const struct file_operations i915_pipe_crc_fops = {
2523 .owner = THIS_MODULE,
2524 .open = i915_pipe_crc_open,
2525 .read = i915_pipe_crc_read,
2526 .release = i915_pipe_crc_release,
2527};
2528
2529static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2530 {
2531 .name = "i915_pipe_A_crc",
2532 .pipe = PIPE_A,
2533 },
2534 {
2535 .name = "i915_pipe_B_crc",
2536 .pipe = PIPE_B,
2537 },
2538 {
2539 .name = "i915_pipe_C_crc",
2540 .pipe = PIPE_C,
2541 },
2542};
2543
2544static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2545 enum pipe pipe)
2546{
2547 struct drm_device *dev = minor->dev;
2548 struct dentry *ent;
2549 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2550
2551 info->dev = dev;
2552 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2553 &i915_pipe_crc_fops);
f3c5fe97
WY		 2554 if (!ent)
2555 return -ENOMEM;
07144428
DL		 2556
2557 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2558}
2559
e8dfcf78 2560static const char * const pipe_crc_sources[] = {
926321d5
DV		 2561 "none",
2562 "plane1",
2563 "plane2",
2564 "pf",
5b3a856b 2565 "pipe",
3d099a05
DV		 2566 "TV",
2567 "DP-B",
2568 "DP-C",
2569 "DP-D",
46a19188 2570 "auto",
926321d5
DV		 2571};
2572
2573static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2574{
2575 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2576 return pipe_crc_sources[source];
2577}
2578
bd9db02f 2579static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2580{
2581 struct drm_device *dev = m->private;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 int i;
2584
2585 for (i = 0; i < I915_MAX_PIPES; i++)
2586 seq_printf(m, "%c %s\n", pipe_name(i),
2587 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2588
2589 return 0;
2590}
2591
bd9db02f 2592static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2593{
2594 struct drm_device *dev = inode->i_private;
2595
bd9db02f 2596 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2597}
2598
46a19188 2599static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2600 uint32_t *val)
2601{
46a19188
DV		 2602 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2603 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2604
2605 switch (*source) {
52f843f6
DV		 2606 case INTEL_PIPE_CRC_SOURCE_PIPE:
2607 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2608 break;
2609 case INTEL_PIPE_CRC_SOURCE_NONE:
2610 *val = 0;
2611 break;
2612 default:
2613 return -EINVAL;
2614 }
2615
2616 return 0;
2617}
2618
46a19188
DV		 2619static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2620 enum intel_pipe_crc_source *source)
2621{
2622 struct intel_encoder *encoder;
2623 struct intel_crtc *crtc;
26756809 2624 struct intel_digital_port *dig_port;
46a19188
DV		 2625 int ret = 0;
2626
2627 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2628
6e9f798d 2629 drm_modeset_lock_all(dev);
46a19188
DV		 2630 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2631 base.head) {
2632 if (!encoder->base.crtc)
2633 continue;
2634
2635 crtc = to_intel_crtc(encoder->base.crtc);
2636
2637 if (crtc->pipe != pipe)
2638 continue;
2639
2640 switch (encoder->type) {
2641 case INTEL_OUTPUT_TVOUT:
2642 *source = INTEL_PIPE_CRC_SOURCE_TV;
2643 break;
2644 case INTEL_OUTPUT_DISPLAYPORT:
2645 case INTEL_OUTPUT_EDP:
26756809
DV		 2646 dig_port = enc_to_dig_port(&encoder->base);
2647 switch (dig_port->port) {
2648 case PORT_B:
2649 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2650 break;
2651 case PORT_C:
2652 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2653 break;
2654 case PORT_D:
2655 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2656 break;
2657 default:
2658 WARN(1, "nonexisting DP port %c\n",
2659 port_name(dig_port->port));
2660 break;
2661 }
46a19188
DV		 2662 break;
2663 }
2664 }
6e9f798d 2665 drm_modeset_unlock_all(dev);
46a19188
DV		 2666
2667 return ret;
2668}
2669
2670static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2671 enum pipe pipe,
2672 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2673 uint32_t *val)
2674{
8d2f24ca
DV		 2675 struct drm_i915_private *dev_priv = dev->dev_private;
2676 bool need_stable_symbols = false;
2677
46a19188
DV		 2678 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2679 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2680 if (ret)
2681 return ret;
2682 }
2683
2684 switch (*source) {
7ac0129b
DV		 2685 case INTEL_PIPE_CRC_SOURCE_PIPE:
2686 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2687 break;
2688 case INTEL_PIPE_CRC_SOURCE_DP_B:
2689 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2690 need_stable_symbols = true;
7ac0129b
DV		 2691 break;
2692 case INTEL_PIPE_CRC_SOURCE_DP_C:
2693 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2694 need_stable_symbols = true;
7ac0129b
DV		 2695 break;
2696 case INTEL_PIPE_CRC_SOURCE_NONE:
2697 *val = 0;
2698 break;
2699 default:
2700 return -EINVAL;
2701 }
2702
8d2f24ca
DV		 2703 /*
2704 * When the pipe CRC tap point is after the transcoders we need
2705 * to tweak symbol-level features to produce a deterministic series of
2706 * symbols for a given frame. We need to reset those features only once
2707 * a frame (instead of every nth symbol):
2708 * - DC-balance: used to ensure a better clock recovery from the data
2709 * link (SDVO)
2710 * - DisplayPort scrambling: used for EMI reduction
2711 */
2712 if (need_stable_symbols) {
2713 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2714
8d2f24ca
DV		 2715 tmp |= DC_BALANCE_RESET_VLV;
2716 if (pipe == PIPE_A)
2717 tmp |= PIPE_A_SCRAMBLE_RESET;
2718 else
2719 tmp |= PIPE_B_SCRAMBLE_RESET;
2720
2721 I915_WRITE(PORT_DFT2_G4X, tmp);
2722 }
2723
7ac0129b
DV		 2724 return 0;
2725}
2726
4b79ebf7 2727static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2728 enum pipe pipe,
2729 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2730 uint32_t *val)
2731{
84093603
DV		 2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733 bool need_stable_symbols = false;
2734
46a19188
DV		 2735 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2736 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2737 if (ret)
2738 return ret;
2739 }
2740
2741 switch (*source) {
4b79ebf7
DV		 2742 case INTEL_PIPE_CRC_SOURCE_PIPE:
2743 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2744 break;
2745 case INTEL_PIPE_CRC_SOURCE_TV:
2746 if (!SUPPORTS_TV(dev))
2747 return -EINVAL;
2748 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2749 break;
2750 case INTEL_PIPE_CRC_SOURCE_DP_B:
2751 if (!IS_G4X(dev))
2752 return -EINVAL;
2753 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2754 need_stable_symbols = true;
4b79ebf7
DV		 2755 break;
2756 case INTEL_PIPE_CRC_SOURCE_DP_C:
2757 if (!IS_G4X(dev))
2758 return -EINVAL;
2759 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2760 need_stable_symbols = true;
4b79ebf7
DV		 2761 break;
2762 case INTEL_PIPE_CRC_SOURCE_DP_D:
2763 if (!IS_G4X(dev))
2764 return -EINVAL;
2765 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2766 need_stable_symbols = true;
4b79ebf7
DV		 2767 break;
2768 case INTEL_PIPE_CRC_SOURCE_NONE:
2769 *val = 0;
2770 break;
2771 default:
2772 return -EINVAL;
2773 }
2774
84093603
DV		 2775 /*
2776 * When the pipe CRC tap point is after the transcoders we need
2777 * to tweak symbol-level features to produce a deterministic series of
2778 * symbols for a given frame. We need to reset those features only once
2779 * a frame (instead of every nth symbol):
2780 * - DC-balance: used to ensure a better clock recovery from the data
2781 * link (SDVO)
2782 * - DisplayPort scrambling: used for EMI reduction
2783 */
2784 if (need_stable_symbols) {
2785 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2786
2787 WARN_ON(!IS_G4X(dev));
2788
2789 I915_WRITE(PORT_DFT_I9XX,
2790 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2791
2792 if (pipe == PIPE_A)
2793 tmp |= PIPE_A_SCRAMBLE_RESET;
2794 else
2795 tmp |= PIPE_B_SCRAMBLE_RESET;
2796
2797 I915_WRITE(PORT_DFT2_G4X, tmp);
2798 }
2799
4b79ebf7
DV		 2800 return 0;
2801}
2802
8d2f24ca
DV		 2803static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2804 enum pipe pipe)
2805{
2806 struct drm_i915_private *dev_priv = dev->dev_private;
2807 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2808
2809 if (pipe == PIPE_A)
2810 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2811 else
2812 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2813 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2814 tmp &= ~DC_BALANCE_RESET_VLV;
2815 I915_WRITE(PORT_DFT2_G4X, tmp);
2816
2817}
2818
84093603
DV		 2819static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2820 enum pipe pipe)
2821{
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2824
2825 if (pipe == PIPE_A)
2826 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2827 else
2828 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2829 I915_WRITE(PORT_DFT2_G4X, tmp);
2830
2831 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2832 I915_WRITE(PORT_DFT_I9XX,
2833 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2834 }
2835}
2836
46a19188 2837static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2838 uint32_t *val)
2839{
46a19188
DV		 2840 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2841 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2842
2843 switch (*source) {
5b3a856b
DV		 2844 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2845 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2846 break;
2847 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2848 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2849 break;
5b3a856b
DV		 2850 case INTEL_PIPE_CRC_SOURCE_PIPE:
2851 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2852 break;
3d099a05 2853 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2854 *val = 0;
2855 break;
3d099a05
DV		 2856 default:
2857 return -EINVAL;
5b3a856b
DV		 2858 }
2859
2860 return 0;
2861}
2862
46a19188 2863static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2864 uint32_t *val)
2865{
46a19188
DV		 2866 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2867 *source = INTEL_PIPE_CRC_SOURCE_PF;
2868
2869 switch (*source) {
5b3a856b
DV		 2870 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2871 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2872 break;
2873 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2874 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2875 break;
2876 case INTEL_PIPE_CRC_SOURCE_PF:
2877 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2878 break;
3d099a05 2879 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2880 *val = 0;
2881 break;
3d099a05
DV		 2882 default:
2883 return -EINVAL;
5b3a856b
DV		 2884 }
2885
2886 return 0;
2887}
2888
926321d5
DV		 2889static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2890 enum intel_pipe_crc_source source)
2891{
2892 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2893 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2894 u32 val = 0; /* shut up gcc */
5b3a856b 2895 int ret;
926321d5 2896
cc3da175
DL		 2897 if (pipe_crc->source == source)
2898 return 0;
2899
ae676fcd
DL		 2900 /* forbid changing the source without going back to 'none' */
2901 if (pipe_crc->source && source)
2902 return -EINVAL;
2903
52f843f6 2904 if (IS_GEN2(dev))
46a19188 2905 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2906 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2907 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2908 else if (IS_VALLEYVIEW(dev))
46a19188 2909 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2910 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2911 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2912 else
46a19188 2913 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2914
2915 if (ret != 0)
2916 return ret;
2917
4b584369
DL		 2918 /* none -> real source transition */
2919 if (source) {
7cd6ccff
DL		 2920 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2921 pipe_name(pipe), pipe_crc_source_name(source));
2922
e5f75aca
DL		 2923 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2924 INTEL_PIPE_CRC_ENTRIES_NR,
2925 GFP_KERNEL);
2926 if (!pipe_crc->entries)
2927 return -ENOMEM;
2928
d538bbdf
DL		 2929 spin_lock_irq(&pipe_crc->lock);
2930 pipe_crc->head = 0;
2931 pipe_crc->tail = 0;
2932 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2933 }
2934
cc3da175 2935 pipe_crc->source = source;
926321d5 2936
926321d5
DV		 2937 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2938 POSTING_READ(PIPE_CRC_CTL(pipe));
2939
e5f75aca
DL		 2940 /* real source -> none transition */
2941 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 2942 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 2943 struct intel_crtc *crtc =
2944 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 2945
7cd6ccff
DL		 2946 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2947 pipe_name(pipe));
2948
a33d7105
DV		 2949 drm_modeset_lock(&crtc->base.mutex, NULL);
2950 if (crtc->active)
2951 intel_wait_for_vblank(dev, pipe);
2952 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 2953
d538bbdf
DL		 2954 spin_lock_irq(&pipe_crc->lock);
2955 entries = pipe_crc->entries;
e5f75aca 2956 pipe_crc->entries = NULL;
d538bbdf
DL		 2957 spin_unlock_irq(&pipe_crc->lock);
2958
2959 kfree(entries);
84093603
DV		 2960
2961 if (IS_G4X(dev))
2962 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2963 else if (IS_VALLEYVIEW(dev))
2964 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2965 }
2966
926321d5
DV		 2967 return 0;
2968}
2969
2970/*
2971 * Parse pipe CRC command strings:
b94dec87
DL		 2972 * command: wsp* object wsp+ name wsp+ source wsp*
2973 * object: 'pipe'
2974 * name: (A | B | C)
926321d5
DV		 2975 * source: (none | plane1 | plane2 | pf)
2976 * wsp: (#0x20 | #0x9 | #0xA)+
2977 *
2978 * eg.:
b94dec87
DL		 2979 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2980 * "pipe A none" -> Stop CRC
926321d5 2981 */
bd9db02f 2982static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2983{
2984 int n_words = 0;
2985
2986 while (*buf) {
2987 char *end;
2988
2989 /* skip leading white space */
2990 buf = skip_spaces(buf);
2991 if (!*buf)
2992 break; /* end of buffer */
2993
2994 /* find end of word */
2995 for (end = buf; *end && !isspace(*end); end++)
2996 ;
2997
2998 if (n_words == max_words) {
2999 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3000 max_words);
3001 return -EINVAL; /* ran out of words[] before bytes */
3002 }
3003
3004 if (*end)
3005 *end++ = '\0';
3006 words[n_words++] = buf;
3007 buf = end;
3008 }
3009
3010 return n_words;
3011}
3012
b94dec87
DL		 3013enum intel_pipe_crc_object {
3014 PIPE_CRC_OBJECT_PIPE,
3015};
3016
e8dfcf78 3017static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3018 "pipe",
3019};
3020
3021static int
bd9db02f 3022display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3023{
3024 int i;
3025
3026 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3027 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3028 *o = i;
b94dec87
DL		 3029 return 0;
3030 }
3031
3032 return -EINVAL;
3033}
3034
bd9db02f 3035static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3036{
3037 const char name = buf[0];
3038
3039 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3040 return -EINVAL;
3041
3042 *pipe = name - 'A';
3043
3044 return 0;
3045}
3046
3047static int
bd9db02f 3048display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3049{
3050 int i;
3051
3052 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3053 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3054 *s = i;
926321d5
DV		 3055 return 0;
3056 }
3057
3058 return -EINVAL;
3059}
3060
bd9db02f 3061static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3062{
b94dec87 3063#define N_WORDS 3
926321d5 3064 int n_words;
b94dec87 3065 char *words[N_WORDS];
926321d5 3066 enum pipe pipe;
b94dec87 3067 enum intel_pipe_crc_object object;
926321d5
DV		 3068 enum intel_pipe_crc_source source;
3069
bd9db02f 3070 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3071 if (n_words != N_WORDS) {
3072 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3073 N_WORDS);
3074 return -EINVAL;
3075 }
3076
bd9db02f 3077 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3078 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3079 return -EINVAL;
3080 }
3081
bd9db02f 3082 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3083 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3084 return -EINVAL;
3085 }
3086
bd9db02f 3087 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3088 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3089 return -EINVAL;
3090 }
3091
3092 return pipe_crc_set_source(dev, pipe, source);
3093}
3094
bd9db02f
DL		 3095static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3096 size_t len, loff_t *offp)
926321d5
DV		 3097{
3098 struct seq_file *m = file->private_data;
3099 struct drm_device *dev = m->private;
3100 char *tmpbuf;
3101 int ret;
3102
3103 if (len == 0)
3104 return 0;
3105
3106 if (len > PAGE_SIZE - 1) {
3107 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3108 PAGE_SIZE);
3109 return -E2BIG;
3110 }
3111
3112 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3113 if (!tmpbuf)
3114 return -ENOMEM;
3115
3116 if (copy_from_user(tmpbuf, ubuf, len)) {
3117 ret = -EFAULT;
3118 goto out;
3119 }
3120 tmpbuf[len] = '\0';
3121
bd9db02f 3122 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3123
3124out:
3125 kfree(tmpbuf);
3126 if (ret < 0)
3127 return ret;
3128
3129 *offp += len;
3130 return len;
3131}
3132
bd9db02f 3133static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3134 .owner = THIS_MODULE,
bd9db02f 3135 .open = display_crc_ctl_open,
926321d5
DV		 3136 .read = seq_read,
3137 .llseek = seq_lseek,
3138 .release = single_release,
bd9db02f 3139 .write = display_crc_ctl_write
926321d5
DV		 3140};
3141
369a1342
VS		 3142static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3143{
3144 struct drm_device *dev = m->private;
546c81fd 3145 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3146 int level;
3147
3148 drm_modeset_lock_all(dev);
3149
3150 for (level = 0; level < num_levels; level++) {
3151 unsigned int latency = wm[level];
3152
3153 /* WM1+ latency values in 0.5us units */
3154 if (level > 0)
3155 latency *= 5;
3156
3157 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3158 level, wm[level],
3159 latency / 10, latency % 10);
3160 }
3161
3162 drm_modeset_unlock_all(dev);
3163}
3164
3165static int pri_wm_latency_show(struct seq_file *m, void *data)
3166{
3167 struct drm_device *dev = m->private;
3168
3169 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3170
3171 return 0;
3172}
3173
3174static int spr_wm_latency_show(struct seq_file *m, void *data)
3175{
3176 struct drm_device *dev = m->private;
3177
3178 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3179
3180 return 0;
3181}
3182
3183static int cur_wm_latency_show(struct seq_file *m, void *data)
3184{
3185 struct drm_device *dev = m->private;
3186
3187 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3188
3189 return 0;
3190}
3191
3192static int pri_wm_latency_open(struct inode *inode, struct file *file)
3193{
3194 struct drm_device *dev = inode->i_private;
3195
3196 if (!HAS_PCH_SPLIT(dev))
3197 return -ENODEV;
3198
3199 return single_open(file, pri_wm_latency_show, dev);
3200}
3201
3202static int spr_wm_latency_open(struct inode *inode, struct file *file)
3203{
3204 struct drm_device *dev = inode->i_private;
3205
3206 if (!HAS_PCH_SPLIT(dev))
3207 return -ENODEV;
3208
3209 return single_open(file, spr_wm_latency_show, dev);
3210}
3211
3212static int cur_wm_latency_open(struct inode *inode, struct file *file)
3213{
3214 struct drm_device *dev = inode->i_private;
3215
3216 if (!HAS_PCH_SPLIT(dev))
3217 return -ENODEV;
3218
3219 return single_open(file, cur_wm_latency_show, dev);
3220}
3221
3222static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3223 size_t len, loff_t *offp, uint16_t wm[5])
3224{
3225 struct seq_file *m = file->private_data;
3226 struct drm_device *dev = m->private;
3227 uint16_t new[5] = { 0 };
546c81fd 3228 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3229 int level;
3230 int ret;
3231 char tmp[32];
3232
3233 if (len >= sizeof(tmp))
3234 return -EINVAL;
3235
3236 if (copy_from_user(tmp, ubuf, len))
3237 return -EFAULT;
3238
3239 tmp[len] = '\0';
3240
3241 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3242 if (ret != num_levels)
3243 return -EINVAL;
3244
3245 drm_modeset_lock_all(dev);
3246
3247 for (level = 0; level < num_levels; level++)
3248 wm[level] = new[level];
3249
3250 drm_modeset_unlock_all(dev);
3251
3252 return len;
3253}
3254
3255
3256static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3257 size_t len, loff_t *offp)
3258{
3259 struct seq_file *m = file->private_data;
3260 struct drm_device *dev = m->private;
3261
3262 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3263}
3264
3265static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3266 size_t len, loff_t *offp)
3267{
3268 struct seq_file *m = file->private_data;
3269 struct drm_device *dev = m->private;
3270
3271 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3272}
3273
3274static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3275 size_t len, loff_t *offp)
3276{
3277 struct seq_file *m = file->private_data;
3278 struct drm_device *dev = m->private;
3279
3280 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3281}
3282
3283static const struct file_operations i915_pri_wm_latency_fops = {
3284 .owner = THIS_MODULE,
3285 .open = pri_wm_latency_open,
3286 .read = seq_read,
3287 .llseek = seq_lseek,
3288 .release = single_release,
3289 .write = pri_wm_latency_write
3290};
3291
3292static const struct file_operations i915_spr_wm_latency_fops = {
3293 .owner = THIS_MODULE,
3294 .open = spr_wm_latency_open,
3295 .read = seq_read,
3296 .llseek = seq_lseek,
3297 .release = single_release,
3298 .write = spr_wm_latency_write
3299};
3300
3301static const struct file_operations i915_cur_wm_latency_fops = {
3302 .owner = THIS_MODULE,
3303 .open = cur_wm_latency_open,
3304 .read = seq_read,
3305 .llseek = seq_lseek,
3306 .release = single_release,
3307 .write = cur_wm_latency_write
3308};
3309
647416f9
KC		 3310static int
3311i915_wedged_get(void *data, u64 *val)
f3cd474b 3312{
647416f9 3313 struct drm_device *dev = data;
e277a1f8 3314 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3315
647416f9 3316 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3317
647416f9 3318 return 0;
f3cd474b
CW		 3319}
3320
647416f9
KC		 3321static int
3322i915_wedged_set(void *data, u64 val)
f3cd474b 3323{
647416f9 3324 struct drm_device *dev = data;
d46c0517
ID		 3325 struct drm_i915_private *dev_priv = dev->dev_private;
3326
3327 intel_runtime_pm_get(dev_priv);
f3cd474b 3328
58174462
MK		 3329 i915_handle_error(dev, val,
3330 "Manually setting wedged to %llu", val);
d46c0517
ID		 3331
3332 intel_runtime_pm_put(dev_priv);
3333
647416f9 3334 return 0;
f3cd474b
CW		 3335}
3336
647416f9
KC		 3337DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3338 i915_wedged_get, i915_wedged_set,
3a3b4f98 3339 "%llu\n");
f3cd474b 3340
647416f9
KC		 3341static int
3342i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3343{
647416f9 3344 struct drm_device *dev = data;
e277a1f8 3345 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3346
647416f9 3347 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3348
647416f9 3349 return 0;
e5eb3d63
DV		 3350}
3351
647416f9
KC		 3352static int
3353i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3354{
647416f9 3355 struct drm_device *dev = data;
e5eb3d63 3356 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3357 int ret;
e5eb3d63 3358
647416f9 3359 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3360
22bcfc6a
DV		 3361 ret = mutex_lock_interruptible(&dev->struct_mutex);
3362 if (ret)
3363 return ret;
3364
99584db3 3365 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3366 mutex_unlock(&dev->struct_mutex);
3367
647416f9 3368 return 0;
e5eb3d63
DV		 3369}
3370
647416f9
KC		 3371DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3372 i915_ring_stop_get, i915_ring_stop_set,
3373 "0x%08llx\n");
d5442303 3374
094f9a54
CW		 3375static int
3376i915_ring_missed_irq_get(void *data, u64 *val)
3377{
3378 struct drm_device *dev = data;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380
3381 *val = dev_priv->gpu_error.missed_irq_rings;
3382 return 0;
3383}
3384
3385static int
3386i915_ring_missed_irq_set(void *data, u64 val)
3387{
3388 struct drm_device *dev = data;
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3390 int ret;
3391
3392 /* Lock against concurrent debugfs callers */
3393 ret = mutex_lock_interruptible(&dev->struct_mutex);
3394 if (ret)
3395 return ret;
3396 dev_priv->gpu_error.missed_irq_rings = val;
3397 mutex_unlock(&dev->struct_mutex);
3398
3399 return 0;
3400}
3401
3402DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3403 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3404 "0x%08llx\n");
3405
3406static int
3407i915_ring_test_irq_get(void *data, u64 *val)
3408{
3409 struct drm_device *dev = data;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411
3412 *val = dev_priv->gpu_error.test_irq_rings;
3413
3414 return 0;
3415}
3416
3417static int
3418i915_ring_test_irq_set(void *data, u64 val)
3419{
3420 struct drm_device *dev = data;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 int ret;
3423
3424 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3425
3426 /* Lock against concurrent debugfs callers */
3427 ret = mutex_lock_interruptible(&dev->struct_mutex);
3428 if (ret)
3429 return ret;
3430
3431 dev_priv->gpu_error.test_irq_rings = val;
3432 mutex_unlock(&dev->struct_mutex);
3433
3434 return 0;
3435}
3436
3437DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3438 i915_ring_test_irq_get, i915_ring_test_irq_set,
3439 "0x%08llx\n");
3440
dd624afd
CW		 3441#define DROP_UNBOUND 0x1
3442#define DROP_BOUND 0x2
3443#define DROP_RETIRE 0x4
3444#define DROP_ACTIVE 0x8
3445#define DROP_ALL (DROP_UNBOUND | \
3446 DROP_BOUND | \
3447 DROP_RETIRE | \
3448 DROP_ACTIVE)
647416f9
KC		 3449static int
3450i915_drop_caches_get(void *data, u64 *val)
dd624afd 3451{
647416f9 3452 *val = DROP_ALL;
dd624afd 3453
647416f9 3454 return 0;
dd624afd
CW		 3455}
3456
647416f9
KC		 3457static int
3458i915_drop_caches_set(void *data, u64 val)
dd624afd 3459{
647416f9 3460 struct drm_device *dev = data;
dd624afd
CW		 3461 struct drm_i915_private *dev_priv = dev->dev_private;
3462 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 3463 struct i915_address_space *vm;
3464 struct i915_vma *vma, *x;
647416f9 3465 int ret;
dd624afd 3466
2f9fe5ff 3467 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3468
3469 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3470 * on ioctls on -EAGAIN. */
3471 ret = mutex_lock_interruptible(&dev->struct_mutex);
3472 if (ret)
3473 return ret;
3474
3475 if (val & DROP_ACTIVE) {
3476 ret = i915_gpu_idle(dev);
3477 if (ret)
3478 goto unlock;
3479 }
3480
3481 if (val & (DROP_RETIRE | DROP_ACTIVE))
3482 i915_gem_retire_requests(dev);
3483
3484 if (val & DROP_BOUND) {
ca191b13
BW		 3485 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3486 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3487 mm_list) {
d7f46fc4 3488 if (vma->pin_count)
ca191b13
BW		 3489 continue;
3490
3491 ret = i915_vma_unbind(vma);
3492 if (ret)
3493 goto unlock;
3494 }
31a46c9c 3495 }
dd624afd
CW		 3496 }
3497
3498 if (val & DROP_UNBOUND) {
35c20a60
BW		 3499 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3500 global_list)
dd624afd
CW		 3501 if (obj->pages_pin_count == 0) {
3502 ret = i915_gem_object_put_pages(obj);
3503 if (ret)
3504 goto unlock;
3505 }
3506 }
3507
3508unlock:
3509 mutex_unlock(&dev->struct_mutex);
3510
647416f9 3511 return ret;
dd624afd
CW		 3512}
3513
647416f9
KC		 3514DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3515 i915_drop_caches_get, i915_drop_caches_set,
3516 "0x%08llx\n");
dd624afd 3517
647416f9
KC		 3518static int
3519i915_max_freq_get(void *data, u64 *val)
358733e9 3520{
647416f9 3521 struct drm_device *dev = data;
e277a1f8 3522 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3523 int ret;
004777cb 3524
daa3afb2 3525 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3526 return -ENODEV;
3527
5c9669ce
TR		 3528 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3529
4fc688ce 3530 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3531 if (ret)
3532 return ret;
358733e9 3533
0a073b84 3534 if (IS_VALLEYVIEW(dev))
b39fb297 3535 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 3536 else
b39fb297 3537 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3538 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3539
647416f9 3540 return 0;
358733e9
JB		 3541}
3542
647416f9
KC		 3543static int
3544i915_max_freq_set(void *data, u64 val)
358733e9 3545{
647416f9 3546 struct drm_device *dev = data;
358733e9 3547 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3548 u32 rp_state_cap, hw_max, hw_min;
647416f9 3549 int ret;
004777cb 3550
daa3afb2 3551 if (INTEL_INFO(dev)->gen < 6)
004777cb 3552 return -ENODEV;
358733e9 3553
5c9669ce
TR		 3554 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3555
647416f9 3556 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3557
4fc688ce 3558 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3559 if (ret)
3560 return ret;
3561
358733e9
JB		 3562 /*
3563 * Turbo will still be enabled, but won't go above the set value.
3564 */
0a073b84 3565 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3566 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3567
3568 hw_max = valleyview_rps_max_freq(dev_priv);
3569 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3570 } else {
3571 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3572
3573 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3574 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3575 hw_min = (rp_state_cap >> 16) & 0xff;
3576 }
3577
b39fb297 3578 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 3579 mutex_unlock(&dev_priv->rps.hw_lock);
3580 return -EINVAL;
0a073b84
JB		 3581 }
3582
b39fb297 3583 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 3584
3585 if (IS_VALLEYVIEW(dev))
3586 valleyview_set_rps(dev, val);
3587 else
3588 gen6_set_rps(dev, val);
3589
4fc688ce 3590 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3591
647416f9 3592 return 0;
358733e9
JB		 3593}
3594
647416f9
KC		 3595DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3596 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3597 "%llu\n");
358733e9 3598
647416f9
KC		 3599static int
3600i915_min_freq_get(void *data, u64 *val)
1523c310 3601{
647416f9 3602 struct drm_device *dev = data;
e277a1f8 3603 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3604 int ret;
004777cb 3605
daa3afb2 3606 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3607 return -ENODEV;
3608
5c9669ce
TR		 3609 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3610
4fc688ce 3611 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3612 if (ret)
3613 return ret;
1523c310 3614
0a073b84 3615 if (IS_VALLEYVIEW(dev))
b39fb297 3616 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 3617 else
b39fb297 3618 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3619 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3620
647416f9 3621 return 0;
1523c310
JB		 3622}
3623
647416f9
KC		 3624static int
3625i915_min_freq_set(void *data, u64 val)
1523c310 3626{
647416f9 3627 struct drm_device *dev = data;
1523c310 3628 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3629 u32 rp_state_cap, hw_max, hw_min;
647416f9 3630 int ret;
004777cb 3631
daa3afb2 3632 if (INTEL_INFO(dev)->gen < 6)
004777cb 3633 return -ENODEV;
1523c310 3634
5c9669ce
TR		 3635 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3636
647416f9 3637 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3638
4fc688ce 3639 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3640 if (ret)
3641 return ret;
3642
1523c310
JB		 3643 /*
3644 * Turbo will still be enabled, but won't go below the set value.
3645 */
0a073b84 3646 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3647 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3648
3649 hw_max = valleyview_rps_max_freq(dev_priv);
3650 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3651 } else {
3652 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3653
3654 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3655 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3656 hw_min = (rp_state_cap >> 16) & 0xff;
3657 }
3658
b39fb297 3659 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 3660 mutex_unlock(&dev_priv->rps.hw_lock);
3661 return -EINVAL;
0a073b84 3662 }
dd0a1aa1 3663
b39fb297 3664 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 3665
3666 if (IS_VALLEYVIEW(dev))
3667 valleyview_set_rps(dev, val);
3668 else
3669 gen6_set_rps(dev, val);
3670
4fc688ce 3671 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3672
647416f9 3673 return 0;
1523c310
JB		 3674}
3675
647416f9
KC		 3676DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3677 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3678 "%llu\n");
1523c310 3679
647416f9
KC		 3680static int
3681i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3682{
647416f9 3683 struct drm_device *dev = data;
e277a1f8 3684 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3685 u32 snpcr;
647416f9 3686 int ret;
07b7ddd9 3687
004777cb
DV		 3688 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3689 return -ENODEV;
3690
22bcfc6a
DV		 3691 ret = mutex_lock_interruptible(&dev->struct_mutex);
3692 if (ret)
3693 return ret;
c8c8fb33 3694 intel_runtime_pm_get(dev_priv);
22bcfc6a 3695
07b7ddd9 3696 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 3697
3698 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 3699 mutex_unlock(&dev_priv->dev->struct_mutex);
3700
647416f9 3701 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3702
647416f9 3703 return 0;
07b7ddd9
JB		 3704}
3705
647416f9
KC		 3706static int
3707i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3708{
647416f9 3709 struct drm_device *dev = data;
07b7ddd9 3710 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3711 u32 snpcr;
07b7ddd9 3712
004777cb
DV		 3713 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3714 return -ENODEV;
3715
647416f9 3716 if (val > 3)
07b7ddd9
JB		 3717 return -EINVAL;
3718
c8c8fb33 3719 intel_runtime_pm_get(dev_priv);
647416f9 3720 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3721
3722 /* Update the cache sharing policy here as well */
3723 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3724 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3725 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3726 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3727
c8c8fb33 3728 intel_runtime_pm_put(dev_priv);
647416f9 3729 return 0;
07b7ddd9
JB		 3730}
3731
647416f9
KC		 3732DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3733 i915_cache_sharing_get, i915_cache_sharing_set,
3734 "%llu\n");
07b7ddd9 3735
6d794d42
BW		 3736static int i915_forcewake_open(struct inode *inode, struct file *file)
3737{
3738 struct drm_device *dev = inode->i_private;
3739 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3740
075edca4 3741 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3742 return 0;
3743
c8d9a590 3744 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3745
3746 return 0;
3747}
3748
c43b5634 3749static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3750{
3751 struct drm_device *dev = inode->i_private;
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3753
075edca4 3754 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3755 return 0;
3756
c8d9a590 3757 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3758
3759 return 0;
3760}
3761
3762static const struct file_operations i915_forcewake_fops = {
3763 .owner = THIS_MODULE,
3764 .open = i915_forcewake_open,
3765 .release = i915_forcewake_release,
3766};
3767
3768static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3769{
3770 struct drm_device *dev = minor->dev;
3771 struct dentry *ent;
3772
3773 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3774 S_IRUSR,
6d794d42
BW		 3775 root, dev,
3776 &i915_forcewake_fops);
f3c5fe97
WY		 3777 if (!ent)
3778 return -ENOMEM;
6d794d42 3779
8eb57294 3780 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3781}
3782
6a9c308d
DV		 3783static int i915_debugfs_create(struct dentry *root,
3784 struct drm_minor *minor,
3785 const char *name,
3786 const struct file_operations *fops)
07b7ddd9
JB		 3787{
3788 struct drm_device *dev = minor->dev;
3789 struct dentry *ent;
3790
6a9c308d 3791 ent = debugfs_create_file(name,
07b7ddd9
JB		 3792 S_IRUGO | S_IWUSR,
3793 root, dev,
6a9c308d 3794 fops);
f3c5fe97
WY		 3795 if (!ent)
3796 return -ENOMEM;
07b7ddd9 3797
6a9c308d 3798 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3799}
3800
06c5bf8c 3801static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3802 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3803 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3804 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3805 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3806 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3807 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3808 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3809 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3810 {"i915_gem_request", i915_gem_request_info, 0},
3811 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3812 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3813 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3814 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3815 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3816 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3817 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1 3818 {"i915_rstdby_delays", i915_rstdby_delays, 0},
adb4bd12 3819 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1
JB		 3820 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3821 {"i915_inttoext_table", i915_inttoext_table, 0},
3822 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3823 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3824 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 3825 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 3826 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3827 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3828 {"i915_sr_status", i915_sr_status, 0},
44834a67 3829 {"i915_opregion", i915_opregion, 0},
37811fcc 3830 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3831 {"i915_context_status", i915_context_status, 0},
6d794d42 3832 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3833 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3834 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 3835 {"i915_llc", i915_llc, 0},
e91fd8c6 3836 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 3837 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 3838 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3839 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3840 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 3841 {"i915_display_info", i915_display_info, 0},
2017263e 3842};
27c202ad 3843#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3844
06c5bf8c 3845static const struct i915_debugfs_files {
34b9674c
DV		 3846 const char *name;
3847 const struct file_operations *fops;
3848} i915_debugfs_files[] = {
3849 {"i915_wedged", &i915_wedged_fops},
3850 {"i915_max_freq", &i915_max_freq_fops},
3851 {"i915_min_freq", &i915_min_freq_fops},
3852 {"i915_cache_sharing", &i915_cache_sharing_fops},
3853 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3854 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3855 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3856 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3857 {"i915_error_state", &i915_error_state_fops},
3858 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3859 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 3860 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3861 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3862 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
34b9674c
DV		 3863};
3864
07144428
DL		 3865void intel_display_crc_init(struct drm_device *dev)
3866{
3867 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3868 enum pipe pipe;
07144428 3869
b378360e
DV		 3870 for_each_pipe(pipe) {
3871 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3872
d538bbdf
DL		 3873 pipe_crc->opened = false;
3874 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3875 init_waitqueue_head(&pipe_crc->wq);
3876 }
3877}
3878
27c202ad 3879int i915_debugfs_init(struct drm_minor *minor)
2017263e 3880{
34b9674c 3881 int ret, i;
f3cd474b 3882
6d794d42 3883 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3884 if (ret)
3885 return ret;
6a9c308d 3886
07144428
DL		 3887 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3888 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3889 if (ret)
3890 return ret;
3891 }
3892
34b9674c
DV		 3893 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3894 ret = i915_debugfs_create(minor->debugfs_root, minor,
3895 i915_debugfs_files[i].name,
3896 i915_debugfs_files[i].fops);
3897 if (ret)
3898 return ret;
3899 }
40633219 3900
27c202ad
BG		 3901 return drm_debugfs_create_files(i915_debugfs_list,
3902 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3903 minor->debugfs_root, minor);
3904}
3905
27c202ad 3906void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3907{
34b9674c
DV		 3908 int i;
3909
27c202ad
BG		 3910 drm_debugfs_remove_files(i915_debugfs_list,
3911 I915_DEBUGFS_ENTRIES, minor);
07144428 3912
6d794d42
BW		 3913 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3914 1, minor);
07144428 3915
e309a997 3916 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3917 struct drm_info_list *info_list =
3918 (struct drm_info_list *)&i915_pipe_crc_data[i];
3919
3920 drm_debugfs_remove_files(info_list, 1, minor);
3921 }
3922
34b9674c
DV		 3923 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3924 struct drm_info_list *info_list =
3925 (struct drm_info_list *) i915_debugfs_files[i].fops;
3926
3927 drm_debugfs_remove_files(info_list, 1, minor);
3928 }
2017263e 3929}
Linux 6.x block layer and io_uring tree(s)