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drm/i915: remove the i915_dpio debugfs entry
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 173}
174
3ccfd19d
BW		 175static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
176{
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
179 seq_putc(m, ' ');
180}
181
433e12f7 182static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 183{
184 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
2017263e 187 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 190 struct i915_vma *vma;
8f2480fb
CW		 191 size_t total_obj_size, total_gtt_size;
192 int count, ret;
de227ef0
CW		 193
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
195 if (ret)
196 return ret;
2017263e 197
ca191b13 198 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 199 switch (list) {
200 case ACTIVE_LIST:
267f0c90 201 seq_puts(m, "Active:\n");
5cef07e1 202 head = &vm->active_list;
433e12f7
BG		 203 break;
204 case INACTIVE_LIST:
267f0c90 205 seq_puts(m, "Inactive:\n");
5cef07e1 206 head = &vm->inactive_list;
433e12f7 207 break;
433e12f7 208 default:
de227ef0
CW		 209 mutex_unlock(&dev->struct_mutex);
210 return -EINVAL;
2017263e 211 }
2017263e 212
8f2480fb 213 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 214 list_for_each_entry(vma, head, mm_list) {
215 seq_printf(m, " ");
216 describe_obj(m, vma->obj);
217 seq_printf(m, "\n");
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
8f2480fb 220 count++;
2017263e 221 }
de227ef0 222 mutex_unlock(&dev->struct_mutex);
5e118f41 223
8f2480fb
CW		 224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
2017263e
BG		 226 return 0;
227}
228
6d2b8885
CW		 229static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
231{
232 struct drm_i915_gem_object *a =
b25cb2f8 233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 234 struct drm_i915_gem_object *b =
b25cb2f8 235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 236
237 return a->stolen->start - b->stolen->start;
238}
239
240static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
241{
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
247 LIST_HEAD(stolen);
248 int count, ret;
249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
252 return ret;
253
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
257 continue;
258
b25cb2f8 259 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 260
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
263 count++;
264 }
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
b25cb2f8 269 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 270
271 total_obj_size += obj->base.size;
272 count++;
273 }
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
b25cb2f8 277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 278 seq_puts(m, " ");
279 describe_obj(m, obj);
280 seq_putc(m, '\n');
b25cb2f8 281 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 282 }
283 mutex_unlock(&dev->struct_mutex);
284
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
287 return 0;
288}
289
6299f992
CW		 290#define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
f343c5f6 292 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 293 ++count; \
294 if (obj->map_and_fenceable) { \
f343c5f6 295 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 296 ++mappable_count; \
297 } \
298 } \
0206e353 299} while (0)
6299f992 300
2db8e9d6 301struct file_stats {
6313c204 302 struct drm_i915_file_private *file_priv;
2db8e9d6 303 int count;
c67a17e9
CW		 304 size_t total, unbound;
305 size_t global, shared;
306 size_t active, inactive;
2db8e9d6
CW		 307};
308
309static int per_file_stats(int id, void *ptr, void *data)
310{
311 struct drm_i915_gem_object *obj = ptr;
312 struct file_stats *stats = data;
6313c204 313 struct i915_vma *vma;
2db8e9d6
CW		 314
315 stats->count++;
316 stats->total += obj->base.size;
317
c67a17e9
CW		 318 if (obj->base.name || obj->base.dma_buf)
319 stats->shared += obj->base.size;
320
6313c204
CW		 321 if (USES_FULL_PPGTT(obj->base.dev)) {
322 list_for_each_entry(vma, &obj->vma_list, vma_link) {
323 struct i915_hw_ppgtt *ppgtt;
324
325 if (!drm_mm_node_allocated(&vma->node))
326 continue;
327
328 if (i915_is_ggtt(vma->vm)) {
329 stats->global += obj->base.size;
330 continue;
331 }
332
333 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
334 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
335 continue;
336
337 if (obj->ring) /* XXX per-vma statistic */
338 stats->active += obj->base.size;
339 else
340 stats->inactive += obj->base.size;
341
342 return 0;
343 }
2db8e9d6 344 } else {
6313c204
CW		 345 if (i915_gem_obj_ggtt_bound(obj)) {
346 stats->global += obj->base.size;
347 if (obj->ring)
348 stats->active += obj->base.size;
349 else
350 stats->inactive += obj->base.size;
351 return 0;
352 }
2db8e9d6
CW		 353 }
354
6313c204
CW		 355 if (!list_empty(&obj->global_list))
356 stats->unbound += obj->base.size;
357
2db8e9d6
CW		 358 return 0;
359}
360
ca191b13
BW		 361#define count_vmas(list, member) do { \
362 list_for_each_entry(vma, list, member) { \
363 size += i915_gem_obj_ggtt_size(vma->obj); \
364 ++count; \
365 if (vma->obj->map_and_fenceable) { \
366 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
367 ++mappable_count; \
368 } \
369 } \
370} while (0)
371
372static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 373{
374 struct drm_info_node *node = (struct drm_info_node *) m->private;
375 struct drm_device *dev = node->minor->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 377 u32 count, mappable_count, purgeable_count;
378 size_t size, mappable_size, purgeable_size;
6299f992 379 struct drm_i915_gem_object *obj;
5cef07e1 380 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 381 struct drm_file *file;
ca191b13 382 struct i915_vma *vma;
73aa808f
CW		 383 int ret;
384
385 ret = mutex_lock_interruptible(&dev->struct_mutex);
386 if (ret)
387 return ret;
388
6299f992
CW		 389 seq_printf(m, "%u objects, %zu bytes\n",
390 dev_priv->mm.object_count,
391 dev_priv->mm.object_memory);
392
393 size = count = mappable_size = mappable_count = 0;
35c20a60 394 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 395 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
396 count, mappable_count, size, mappable_size);
397
398 size = count = mappable_size = mappable_count = 0;
ca191b13 399 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 400 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
401 count, mappable_count, size, mappable_size);
402
6299f992 403 size = count = mappable_size = mappable_count = 0;
ca191b13 404 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 405 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
406 count, mappable_count, size, mappable_size);
407
b7abb714 408 size = count = purgeable_size = purgeable_count = 0;
35c20a60 409 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 410 size += obj->base.size, ++count;
b7abb714
CW		 411 if (obj->madv == I915_MADV_DONTNEED)
412 purgeable_size += obj->base.size, ++purgeable_count;
413 }
6c085a72
CW		 414 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
415
6299f992 416 size = count = mappable_size = mappable_count = 0;
35c20a60 417 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 418 if (obj->fault_mappable) {
f343c5f6 419 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 420 ++count;
421 }
422 if (obj->pin_mappable) {
f343c5f6 423 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 424 ++mappable_count;
425 }
b7abb714
CW		 426 if (obj->madv == I915_MADV_DONTNEED) {
427 purgeable_size += obj->base.size;
428 ++purgeable_count;
429 }
6299f992 430 }
b7abb714
CW		 431 seq_printf(m, "%u purgeable objects, %zu bytes\n",
432 purgeable_count, purgeable_size);
6299f992
CW		 433 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
434 mappable_count, mappable_size);
435 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
436 count, size);
437
93d18799 438 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 439 dev_priv->gtt.base.total,
440 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 441
267f0c90 442 seq_putc(m, '\n');
2db8e9d6
CW		 443 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
444 struct file_stats stats;
3ec2f427 445 struct task_struct *task;
2db8e9d6
CW		 446
447 memset(&stats, 0, sizeof(stats));
6313c204 448 stats.file_priv = file->driver_priv;
2db8e9d6 449 idr_for_each(&file->object_idr, per_file_stats, &stats);
3ec2f427
TH		 450 /*
451 * Although we have a valid reference on file->pid, that does
452 * not guarantee that the task_struct who called get_pid() is
453 * still alive (e.g. get_pid(current) => fork() => exit()).
454 * Therefore, we need to protect this ->comm access using RCU.
455 */
456 rcu_read_lock();
457 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 458 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 459 task ? task->comm : "<unknown>",
2db8e9d6
CW		 460 stats.count,
461 stats.total,
462 stats.active,
463 stats.inactive,
6313c204 464 stats.global,
c67a17e9 465 stats.shared,
2db8e9d6 466 stats.unbound);
3ec2f427 467 rcu_read_unlock();
2db8e9d6
CW		 468 }
469
73aa808f
CW		 470 mutex_unlock(&dev->struct_mutex);
471
472 return 0;
473}
474
aee56cff 475static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 476{
477 struct drm_info_node *node = (struct drm_info_node *) m->private;
478 struct drm_device *dev = node->minor->dev;
1b50247a 479 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct drm_i915_gem_object *obj;
482 size_t total_obj_size, total_gtt_size;
483 int count, ret;
484
485 ret = mutex_lock_interruptible(&dev->struct_mutex);
486 if (ret)
487 return ret;
488
489 total_obj_size = total_gtt_size = count = 0;
35c20a60 490 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 491 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 492 continue;
493
267f0c90 494 seq_puts(m, " ");
08c18323 495 describe_obj(m, obj);
267f0c90 496 seq_putc(m, '\n');
08c18323 497 total_obj_size += obj->base.size;
f343c5f6 498 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 499 count++;
500 }
501
502 mutex_unlock(&dev->struct_mutex);
503
504 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
505 count, total_obj_size, total_gtt_size);
506
507 return 0;
508}
509
4e5359cd
SF		 510static int i915_gem_pageflip_info(struct seq_file *m, void *data)
511{
512 struct drm_info_node *node = (struct drm_info_node *) m->private;
513 struct drm_device *dev = node->minor->dev;
514 unsigned long flags;
515 struct intel_crtc *crtc;
516
517 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 518 const char pipe = pipe_name(crtc->pipe);
519 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 520 struct intel_unpin_work *work;
521
522 spin_lock_irqsave(&dev->event_lock, flags);
523 work = crtc->unpin_work;
524 if (work == NULL) {
9db4a9c7 525 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 526 pipe, plane);
527 } else {
e7d841ca 528 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 529 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 530 pipe, plane);
531 } else {
9db4a9c7 532 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 533 pipe, plane);
534 }
535 if (work->enable_stall_check)
267f0c90 536 seq_puts(m, "Stall check enabled, ");
4e5359cd 537 else
267f0c90 538 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 539 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 540
541 if (work->old_fb_obj) {
05394f39
CW		 542 struct drm_i915_gem_object *obj = work->old_fb_obj;
543 if (obj)
f343c5f6
BW		 544 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
545 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 546 }
547 if (work->pending_flip_obj) {
05394f39
CW		 548 struct drm_i915_gem_object *obj = work->pending_flip_obj;
549 if (obj)
f343c5f6
BW		 550 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
551 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 552 }
553 }
554 spin_unlock_irqrestore(&dev->event_lock, flags);
555 }
556
557 return 0;
558}
559
2017263e
BG		 560static int i915_gem_request_info(struct seq_file *m, void *data)
561{
562 struct drm_info_node *node = (struct drm_info_node *) m->private;
563 struct drm_device *dev = node->minor->dev;
e277a1f8 564 struct drm_i915_private *dev_priv = dev->dev_private;
a2c7f6fd 565 struct intel_ring_buffer *ring;
2017263e 566 struct drm_i915_gem_request *gem_request;
a2c7f6fd 567 int ret, count, i;
de227ef0
CW		 568
569 ret = mutex_lock_interruptible(&dev->struct_mutex);
570 if (ret)
571 return ret;
2017263e 572
c2c347a9 573 count = 0;
a2c7f6fd
CW		 574 for_each_ring(ring, dev_priv, i) {
575 if (list_empty(&ring->request_list))
576 continue;
577
578 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 579 list_for_each_entry(gem_request,
a2c7f6fd 580 &ring->request_list,
c2c347a9
CW		 581 list) {
582 seq_printf(m, " %d @ %d\n",
583 gem_request->seqno,
584 (int) (jiffies - gem_request->emitted_jiffies));
585 }
586 count++;
2017263e 587 }
de227ef0
CW		 588 mutex_unlock(&dev->struct_mutex);
589
c2c347a9 590 if (count == 0)
267f0c90 591 seq_puts(m, "No requests\n");
c2c347a9 592
2017263e
BG		 593 return 0;
594}
595
b2223497
CW		 596static void i915_ring_seqno_info(struct seq_file *m,
597 struct intel_ring_buffer *ring)
598{
599 if (ring->get_seqno) {
43a7b924 600 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 601 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 602 }
603}
604
2017263e
BG		 605static int i915_gem_seqno_info(struct seq_file *m, void *data)
606{
607 struct drm_info_node *node = (struct drm_info_node *) m->private;
608 struct drm_device *dev = node->minor->dev;
e277a1f8 609 struct drm_i915_private *dev_priv = dev->dev_private;
a2c7f6fd 610 struct intel_ring_buffer *ring;
1ec14ad3 611 int ret, i;
de227ef0
CW		 612
613 ret = mutex_lock_interruptible(&dev->struct_mutex);
614 if (ret)
615 return ret;
c8c8fb33 616 intel_runtime_pm_get(dev_priv);
2017263e 617
a2c7f6fd
CW		 618 for_each_ring(ring, dev_priv, i)
619 i915_ring_seqno_info(m, ring);
de227ef0 620
c8c8fb33 621 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 622 mutex_unlock(&dev->struct_mutex);
623
2017263e
BG		 624 return 0;
625}
626
627
628static int i915_interrupt_info(struct seq_file *m, void *data)
629{
630 struct drm_info_node *node = (struct drm_info_node *) m->private;
631 struct drm_device *dev = node->minor->dev;
e277a1f8 632 struct drm_i915_private *dev_priv = dev->dev_private;
a2c7f6fd 633 struct intel_ring_buffer *ring;
9db4a9c7 634 int ret, i, pipe;
de227ef0
CW		 635
636 ret = mutex_lock_interruptible(&dev->struct_mutex);
637 if (ret)
638 return ret;
c8c8fb33 639 intel_runtime_pm_get(dev_priv);
2017263e 640
a123f157 641 if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 642 seq_printf(m, "Master Interrupt Control:\t%08x\n",
643 I915_READ(GEN8_MASTER_IRQ));
644
645 for (i = 0; i < 4; i++) {
646 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
647 i, I915_READ(GEN8_GT_IMR(i)));
648 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
649 i, I915_READ(GEN8_GT_IIR(i)));
650 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
651 i, I915_READ(GEN8_GT_IER(i)));
652 }
653
07d27e20 654 for_each_pipe(pipe) {
a123f157 655 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 656 pipe_name(pipe),
657 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 658 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 659 pipe_name(pipe),
660 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 661 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 662 pipe_name(pipe),
663 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 664 }
665
666 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
667 I915_READ(GEN8_DE_PORT_IMR));
668 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
669 I915_READ(GEN8_DE_PORT_IIR));
670 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
671 I915_READ(GEN8_DE_PORT_IER));
672
673 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
674 I915_READ(GEN8_DE_MISC_IMR));
675 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
676 I915_READ(GEN8_DE_MISC_IIR));
677 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
678 I915_READ(GEN8_DE_MISC_IER));
679
680 seq_printf(m, "PCU interrupt mask:\t%08x\n",
681 I915_READ(GEN8_PCU_IMR));
682 seq_printf(m, "PCU interrupt identity:\t%08x\n",
683 I915_READ(GEN8_PCU_IIR));
684 seq_printf(m, "PCU interrupt enable:\t%08x\n",
685 I915_READ(GEN8_PCU_IER));
686 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 687 seq_printf(m, "Display IER:\t%08x\n",
688 I915_READ(VLV_IER));
689 seq_printf(m, "Display IIR:\t%08x\n",
690 I915_READ(VLV_IIR));
691 seq_printf(m, "Display IIR_RW:\t%08x\n",
692 I915_READ(VLV_IIR_RW));
693 seq_printf(m, "Display IMR:\t%08x\n",
694 I915_READ(VLV_IMR));
695 for_each_pipe(pipe)
696 seq_printf(m, "Pipe %c stat:\t%08x\n",
697 pipe_name(pipe),
698 I915_READ(PIPESTAT(pipe)));
699
700 seq_printf(m, "Master IER:\t%08x\n",
701 I915_READ(VLV_MASTER_IER));
702
703 seq_printf(m, "Render IER:\t%08x\n",
704 I915_READ(GTIER));
705 seq_printf(m, "Render IIR:\t%08x\n",
706 I915_READ(GTIIR));
707 seq_printf(m, "Render IMR:\t%08x\n",
708 I915_READ(GTIMR));
709
710 seq_printf(m, "PM IER:\t\t%08x\n",
711 I915_READ(GEN6_PMIER));
712 seq_printf(m, "PM IIR:\t\t%08x\n",
713 I915_READ(GEN6_PMIIR));
714 seq_printf(m, "PM IMR:\t\t%08x\n",
715 I915_READ(GEN6_PMIMR));
716
717 seq_printf(m, "Port hotplug:\t%08x\n",
718 I915_READ(PORT_HOTPLUG_EN));
719 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
720 I915_READ(VLV_DPFLIPSTAT));
721 seq_printf(m, "DPINVGTT:\t%08x\n",
722 I915_READ(DPINVGTT));
723
724 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 725 seq_printf(m, "Interrupt enable: %08x\n",
726 I915_READ(IER));
727 seq_printf(m, "Interrupt identity: %08x\n",
728 I915_READ(IIR));
729 seq_printf(m, "Interrupt mask: %08x\n",
730 I915_READ(IMR));
9db4a9c7
JB		 731 for_each_pipe(pipe)
732 seq_printf(m, "Pipe %c stat: %08x\n",
733 pipe_name(pipe),
734 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 735 } else {
736 seq_printf(m, "North Display Interrupt enable: %08x\n",
737 I915_READ(DEIER));
738 seq_printf(m, "North Display Interrupt identity: %08x\n",
739 I915_READ(DEIIR));
740 seq_printf(m, "North Display Interrupt mask: %08x\n",
741 I915_READ(DEIMR));
742 seq_printf(m, "South Display Interrupt enable: %08x\n",
743 I915_READ(SDEIER));
744 seq_printf(m, "South Display Interrupt identity: %08x\n",
745 I915_READ(SDEIIR));
746 seq_printf(m, "South Display Interrupt mask: %08x\n",
747 I915_READ(SDEIMR));
748 seq_printf(m, "Graphics Interrupt enable: %08x\n",
749 I915_READ(GTIER));
750 seq_printf(m, "Graphics Interrupt identity: %08x\n",
751 I915_READ(GTIIR));
752 seq_printf(m, "Graphics Interrupt mask: %08x\n",
753 I915_READ(GTIMR));
754 }
a2c7f6fd 755 for_each_ring(ring, dev_priv, i) {
a123f157 756 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 757 seq_printf(m,
758 "Graphics Interrupt mask (%s): %08x\n",
759 ring->name, I915_READ_IMR(ring));
9862e600 760 }
a2c7f6fd 761 i915_ring_seqno_info(m, ring);
9862e600 762 }
c8c8fb33 763 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 764 mutex_unlock(&dev->struct_mutex);
765
2017263e
BG		 766 return 0;
767}
768
a6172a80
CW		 769static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
770{
771 struct drm_info_node *node = (struct drm_info_node *) m->private;
772 struct drm_device *dev = node->minor->dev;
e277a1f8 773 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 774 int i, ret;
775
776 ret = mutex_lock_interruptible(&dev->struct_mutex);
777 if (ret)
778 return ret;
a6172a80
CW		 779
780 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
781 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
782 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 783 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 784
6c085a72
CW		 785 seq_printf(m, "Fence %d, pin count = %d, object = ",
786 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 787 if (obj == NULL)
267f0c90 788 seq_puts(m, "unused");
c2c347a9 789 else
05394f39 790 describe_obj(m, obj);
267f0c90 791 seq_putc(m, '\n');
a6172a80
CW		 792 }
793
05394f39 794 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 795 return 0;
796}
797
2017263e
BG		 798static int i915_hws_info(struct seq_file *m, void *data)
799{
800 struct drm_info_node *node = (struct drm_info_node *) m->private;
801 struct drm_device *dev = node->minor->dev;
e277a1f8 802 struct drm_i915_private *dev_priv = dev->dev_private;
4066c0ae 803 struct intel_ring_buffer *ring;
1a240d4d 804 const u32 *hws;
4066c0ae
CW		 805 int i;
806
1ec14ad3 807 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 808 hws = ring->status_page.page_addr;
2017263e
BG		 809 if (hws == NULL)
810 return 0;
811
812 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
813 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
814 i * 4,
815 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
816 }
817 return 0;
818}
819
d5442303
DV		 820static ssize_t
821i915_error_state_write(struct file *filp,
822 const char __user *ubuf,
823 size_t cnt,
824 loff_t *ppos)
825{
edc3d884 826 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 827 struct drm_device *dev = error_priv->dev;
22bcfc6a 828 int ret;
d5442303
DV		 829
830 DRM_DEBUG_DRIVER("Resetting error state\n");
831
22bcfc6a
DV		 832 ret = mutex_lock_interruptible(&dev->struct_mutex);
833 if (ret)
834 return ret;
835
d5442303
DV		 836 i915_destroy_error_state(dev);
837 mutex_unlock(&dev->struct_mutex);
838
839 return cnt;
840}
841
842static int i915_error_state_open(struct inode *inode, struct file *file)
843{
844 struct drm_device *dev = inode->i_private;
d5442303 845 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 846
847 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
848 if (!error_priv)
849 return -ENOMEM;
850
851 error_priv->dev = dev;
852
95d5bfb3 853 i915_error_state_get(dev, error_priv);
d5442303 854
edc3d884
MK		 855 file->private_data = error_priv;
856
857 return 0;
d5442303
DV		 858}
859
860static int i915_error_state_release(struct inode *inode, struct file *file)
861{
edc3d884 862 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 863
95d5bfb3 864 i915_error_state_put(error_priv);
d5442303
DV		 865 kfree(error_priv);
866
edc3d884
MK		 867 return 0;
868}
869
4dc955f7
MK		 870static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
871 size_t count, loff_t *pos)
872{
873 struct i915_error_state_file_priv *error_priv = file->private_data;
874 struct drm_i915_error_state_buf error_str;
875 loff_t tmp_pos = 0;
876 ssize_t ret_count = 0;
877 int ret;
878
879 ret = i915_error_state_buf_init(&error_str, count, *pos);
880 if (ret)
881 return ret;
edc3d884 882
fc16b48b 883 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 884 if (ret)
885 goto out;
886
edc3d884
MK		 887 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
888 error_str.buf,
889 error_str.bytes);
890
891 if (ret_count < 0)
892 ret = ret_count;
893 else
894 *pos = error_str.start + ret_count;
895out:
4dc955f7 896 i915_error_state_buf_release(&error_str);
edc3d884 897 return ret ?: ret_count;
d5442303
DV		 898}
899
900static const struct file_operations i915_error_state_fops = {
901 .owner = THIS_MODULE,
902 .open = i915_error_state_open,
edc3d884 903 .read = i915_error_state_read,
d5442303
DV		 904 .write = i915_error_state_write,
905 .llseek = default_llseek,
906 .release = i915_error_state_release,
907};
908
647416f9
KC		 909static int
910i915_next_seqno_get(void *data, u64 *val)
40633219 911{
647416f9 912 struct drm_device *dev = data;
e277a1f8 913 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 914 int ret;
915
916 ret = mutex_lock_interruptible(&dev->struct_mutex);
917 if (ret)
918 return ret;
919
647416f9 920 *val = dev_priv->next_seqno;
40633219
MK		 921 mutex_unlock(&dev->struct_mutex);
922
647416f9 923 return 0;
40633219
MK		 924}
925
647416f9
KC		 926static int
927i915_next_seqno_set(void *data, u64 val)
928{
929 struct drm_device *dev = data;
40633219
MK		 930 int ret;
931
40633219
MK		 932 ret = mutex_lock_interruptible(&dev->struct_mutex);
933 if (ret)
934 return ret;
935
e94fbaa8 936 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 937 mutex_unlock(&dev->struct_mutex);
938
647416f9 939 return ret;
40633219
MK		 940}
941
647416f9
KC		 942DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
943 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 944 "0x%llx\n");
40633219 945
f97108d1
JB		 946static int i915_rstdby_delays(struct seq_file *m, void *unused)
947{
948 struct drm_info_node *node = (struct drm_info_node *) m->private;
949 struct drm_device *dev = node->minor->dev;
e277a1f8 950 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 951 u16 crstanddelay;
952 int ret;
953
954 ret = mutex_lock_interruptible(&dev->struct_mutex);
955 if (ret)
956 return ret;
c8c8fb33 957 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 958
959 crstanddelay = I915_READ16(CRSTANDVID);
960
c8c8fb33 961 intel_runtime_pm_put(dev_priv);
616fdb5a 962 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 963
964 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
965
966 return 0;
967}
968
adb4bd12 969static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1
JB		 970{
971 struct drm_info_node *node = (struct drm_info_node *) m->private;
972 struct drm_device *dev = node->minor->dev;
e277a1f8 973 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 974 int ret = 0;
975
976 intel_runtime_pm_get(dev_priv);
3b8d8d91 977
5c9669ce
TR		 978 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
979
3b8d8d91
JB		 980 if (IS_GEN5(dev)) {
981 u16 rgvswctl = I915_READ16(MEMSWCTL);
982 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
983
984 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
985 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
986 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
987 MEMSTAT_VID_SHIFT);
988 seq_printf(m, "Current P-state: %d\n",
989 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 990 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 991 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
992 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
993 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 994 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 995 u32 rpstat, cagf, reqf;
ccab5c82
JB		 996 u32 rpupei, rpcurup, rpprevup;
997 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 998 int max_freq;
999
1000 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1001 ret = mutex_lock_interruptible(&dev->struct_mutex);
1002 if (ret)
c8c8fb33 1003 goto out;
d1ebd816 1004
c8d9a590 1005 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1006
8e8c06cd
CW		 1007 reqf = I915_READ(GEN6_RPNSWREQ);
1008 reqf &= ~GEN6_TURBO_DISABLE;
1009 if (IS_HASWELL(dev))
1010 reqf >>= 24;
1011 else
1012 reqf >>= 25;
1013 reqf *= GT_FREQUENCY_MULTIPLIER;
1014
0d8f9491
CW		 1015 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1016 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1017 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1018
ccab5c82
JB		 1019 rpstat = I915_READ(GEN6_RPSTAT1);
1020 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1021 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1022 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1023 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1024 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1025 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 1026 if (IS_HASWELL(dev))
1027 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1028 else
1029 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1030 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1031
c8d9a590 1032 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1033 mutex_unlock(&dev->struct_mutex);
1034
0d8f9491
CW		 1035 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1036 I915_READ(GEN6_PMIER),
1037 I915_READ(GEN6_PMIMR),
1038 I915_READ(GEN6_PMISR),
1039 I915_READ(GEN6_PMIIR),
1040 I915_READ(GEN6_PMINTRMSK));
3b8d8d91 1041 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1042 seq_printf(m, "Render p-state ratio: %d\n",
1043 (gt_perf_status & 0xff00) >> 8);
1044 seq_printf(m, "Render p-state VID: %d\n",
1045 gt_perf_status & 0xff);
1046 seq_printf(m, "Render p-state limit: %d\n",
1047 rp_state_limits & 0xff);
0d8f9491
CW		 1048 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1049 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1050 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1051 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1052 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1053 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1054 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1055 GEN6_CURICONT_MASK);
1056 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1057 GEN6_CURBSYTAVG_MASK);
1058 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1059 GEN6_CURBSYTAVG_MASK);
1060 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1061 GEN6_CURIAVG_MASK);
1062 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1063 GEN6_CURBSYTAVG_MASK);
1064 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1065 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1066
1067 max_freq = (rp_state_cap & 0xff0000) >> 16;
1068 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1069 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1070
1071 max_freq = (rp_state_cap & 0xff00) >> 8;
1072 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1073 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1074
1075 max_freq = rp_state_cap & 0xff;
1076 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1077 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1078
1079 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1080 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1081 } else if (IS_VALLEYVIEW(dev)) {
1082 u32 freq_sts, val;
1083
259bd5d4 1084 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1085 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1086 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1087 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1088
c5bd2bf6 1089 val = valleyview_rps_max_freq(dev_priv);
0a073b84 1090 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 1091 vlv_gpu_freq(dev_priv, val));
0a073b84 1092
c5bd2bf6 1093 val = valleyview_rps_min_freq(dev_priv);
0a073b84 1094 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 1095 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 1096
1097 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1098 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1099 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1100 } else {
267f0c90 1101 seq_puts(m, "no P-state info available\n");
3b8d8d91 1102 }
f97108d1 1103
c8c8fb33
PZ		 1104out:
1105 intel_runtime_pm_put(dev_priv);
1106 return ret;
f97108d1
JB		 1107}
1108
1109static int i915_delayfreq_table(struct seq_file *m, void *unused)
1110{
1111 struct drm_info_node *node = (struct drm_info_node *) m->private;
1112 struct drm_device *dev = node->minor->dev;
e277a1f8 1113 struct drm_i915_private *dev_priv = dev->dev_private;
f97108d1 1114 u32 delayfreq;
616fdb5a
BW		 1115 int ret, i;
1116
1117 ret = mutex_lock_interruptible(&dev->struct_mutex);
1118 if (ret)
1119 return ret;
c8c8fb33 1120 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1121
1122 for (i = 0; i < 16; i++) {
1123 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1124 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1125 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1126 }
1127
c8c8fb33
PZ		 1128 intel_runtime_pm_put(dev_priv);
1129
616fdb5a
BW		 1130 mutex_unlock(&dev->struct_mutex);
1131
f97108d1
JB		 1132 return 0;
1133}
1134
1135static inline int MAP_TO_MV(int map)
1136{
1137 return 1250 - (map * 25);
1138}
1139
1140static int i915_inttoext_table(struct seq_file *m, void *unused)
1141{
1142 struct drm_info_node *node = (struct drm_info_node *) m->private;
1143 struct drm_device *dev = node->minor->dev;
e277a1f8 1144 struct drm_i915_private *dev_priv = dev->dev_private;
f97108d1 1145 u32 inttoext;
616fdb5a
BW		 1146 int ret, i;
1147
1148 ret = mutex_lock_interruptible(&dev->struct_mutex);
1149 if (ret)
1150 return ret;
c8c8fb33 1151 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1152
1153 for (i = 1; i <= 32; i++) {
1154 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1155 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1156 }
1157
c8c8fb33 1158 intel_runtime_pm_put(dev_priv);
616fdb5a
BW		 1159 mutex_unlock(&dev->struct_mutex);
1160
f97108d1
JB		 1161 return 0;
1162}
1163
4d85529d 1164static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1165{
1166 struct drm_info_node *node = (struct drm_info_node *) m->private;
1167 struct drm_device *dev = node->minor->dev;
e277a1f8 1168 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1169 u32 rgvmodectl, rstdbyctl;
1170 u16 crstandvid;
1171 int ret;
1172
1173 ret = mutex_lock_interruptible(&dev->struct_mutex);
1174 if (ret)
1175 return ret;
c8c8fb33 1176 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1177
1178 rgvmodectl = I915_READ(MEMMODECTL);
1179 rstdbyctl = I915_READ(RSTDBYCTL);
1180 crstandvid = I915_READ16(CRSTANDVID);
1181
c8c8fb33 1182 intel_runtime_pm_put(dev_priv);
616fdb5a 1183 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1184
1185 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1186 "yes" : "no");
1187 seq_printf(m, "Boost freq: %d\n",
1188 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1189 MEMMODE_BOOST_FREQ_SHIFT);
1190 seq_printf(m, "HW control enabled: %s\n",
1191 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1192 seq_printf(m, "SW control enabled: %s\n",
1193 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1194 seq_printf(m, "Gated voltage change: %s\n",
1195 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1196 seq_printf(m, "Starting frequency: P%d\n",
1197 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1198 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1199 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1200 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1201 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1202 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1203 seq_printf(m, "Render standby enabled: %s\n",
1204 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1205 seq_puts(m, "Current RS state: ");
88271da3
JB		 1206 switch (rstdbyctl & RSX_STATUS_MASK) {
1207 case RSX_STATUS_ON:
267f0c90 1208 seq_puts(m, "on\n");
88271da3
JB		 1209 break;
1210 case RSX_STATUS_RC1:
267f0c90 1211 seq_puts(m, "RC1\n");
88271da3
JB		 1212 break;
1213 case RSX_STATUS_RC1E:
267f0c90 1214 seq_puts(m, "RC1E\n");
88271da3
JB		 1215 break;
1216 case RSX_STATUS_RS1:
267f0c90 1217 seq_puts(m, "RS1\n");
88271da3
JB		 1218 break;
1219 case RSX_STATUS_RS2:
267f0c90 1220 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1221 break;
1222 case RSX_STATUS_RS3:
267f0c90 1223 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1224 break;
1225 default:
267f0c90 1226 seq_puts(m, "unknown\n");
88271da3
JB		 1227 break;
1228 }
f97108d1
JB		 1229
1230 return 0;
1231}
1232
669ab5aa
D		 1233static int vlv_drpc_info(struct seq_file *m)
1234{
1235
1236 struct drm_info_node *node = (struct drm_info_node *) m->private;
1237 struct drm_device *dev = node->minor->dev;
1238 struct drm_i915_private *dev_priv = dev->dev_private;
1239 u32 rpmodectl1, rcctl1;
1240 unsigned fw_rendercount = 0, fw_mediacount = 0;
1241
1242 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1243 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1244
1245 seq_printf(m, "Video Turbo Mode: %s\n",
1246 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1247 seq_printf(m, "Turbo enabled: %s\n",
1248 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1249 seq_printf(m, "HW control enabled: %s\n",
1250 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1251 seq_printf(m, "SW control enabled: %s\n",
1252 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1253 GEN6_RP_MEDIA_SW_MODE));
1254 seq_printf(m, "RC6 Enabled: %s\n",
1255 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1256 GEN6_RC_CTL_EI_MODE(1))));
1257 seq_printf(m, "Render Power Well: %s\n",
1258 (I915_READ(VLV_GTLC_PW_STATUS) &
1259 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1260 seq_printf(m, "Media Power Well: %s\n",
1261 (I915_READ(VLV_GTLC_PW_STATUS) &
1262 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1263
9cc19be5
ID		 1264 seq_printf(m, "Render RC6 residency since boot: %u\n",
1265 I915_READ(VLV_GT_RENDER_RC6));
1266 seq_printf(m, "Media RC6 residency since boot: %u\n",
1267 I915_READ(VLV_GT_MEDIA_RC6));
1268
669ab5aa
D		 1269 spin_lock_irq(&dev_priv->uncore.lock);
1270 fw_rendercount = dev_priv->uncore.fw_rendercount;
1271 fw_mediacount = dev_priv->uncore.fw_mediacount;
1272 spin_unlock_irq(&dev_priv->uncore.lock);
1273
1274 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1275 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1276
1277
1278 return 0;
1279}
1280
1281
4d85529d
BW		 1282static int gen6_drpc_info(struct seq_file *m)
1283{
1284
1285 struct drm_info_node *node = (struct drm_info_node *) m->private;
1286 struct drm_device *dev = node->minor->dev;
1287 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1288 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1289 unsigned forcewake_count;
aee56cff 1290 int count = 0, ret;
4d85529d
BW		 1291
1292 ret = mutex_lock_interruptible(&dev->struct_mutex);
1293 if (ret)
1294 return ret;
c8c8fb33 1295 intel_runtime_pm_get(dev_priv);
4d85529d 1296
907b28c5
CW		 1297 spin_lock_irq(&dev_priv->uncore.lock);
1298 forcewake_count = dev_priv->uncore.forcewake_count;
1299 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1300
1301 if (forcewake_count) {
267f0c90
DL		 1302 seq_puts(m, "RC information inaccurate because somebody "
1303 "holds a forcewake reference \n");
4d85529d
BW		 1304 } else {
1305 /* NB: we cannot use forcewake, else we read the wrong values */
1306 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1307 udelay(10);
1308 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1309 }
1310
1311 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1312 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1313
1314 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1315 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1316 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1317 mutex_lock(&dev_priv->rps.hw_lock);
1318 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1319 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1320
c8c8fb33
PZ		 1321 intel_runtime_pm_put(dev_priv);
1322
4d85529d
BW		 1323 seq_printf(m, "Video Turbo Mode: %s\n",
1324 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1325 seq_printf(m, "HW control enabled: %s\n",
1326 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1327 seq_printf(m, "SW control enabled: %s\n",
1328 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1329 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1330 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1331 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1332 seq_printf(m, "RC6 Enabled: %s\n",
1333 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1334 seq_printf(m, "Deep RC6 Enabled: %s\n",
1335 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1336 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1337 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1338 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1339 switch (gt_core_status & GEN6_RCn_MASK) {
1340 case GEN6_RC0:
1341 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1342 seq_puts(m, "Core Power Down\n");
4d85529d 1343 else
267f0c90 1344 seq_puts(m, "on\n");
4d85529d
BW		 1345 break;
1346 case GEN6_RC3:
267f0c90 1347 seq_puts(m, "RC3\n");
4d85529d
BW		 1348 break;
1349 case GEN6_RC6:
267f0c90 1350 seq_puts(m, "RC6\n");
4d85529d
BW		 1351 break;
1352 case GEN6_RC7:
267f0c90 1353 seq_puts(m, "RC7\n");
4d85529d
BW		 1354 break;
1355 default:
267f0c90 1356 seq_puts(m, "Unknown\n");
4d85529d
BW		 1357 break;
1358 }
1359
1360 seq_printf(m, "Core Power Down: %s\n",
1361 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1362
1363 /* Not exactly sure what this is */
1364 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1365 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1366 seq_printf(m, "RC6 residency since boot: %u\n",
1367 I915_READ(GEN6_GT_GFX_RC6));
1368 seq_printf(m, "RC6+ residency since boot: %u\n",
1369 I915_READ(GEN6_GT_GFX_RC6p));
1370 seq_printf(m, "RC6++ residency since boot: %u\n",
1371 I915_READ(GEN6_GT_GFX_RC6pp));
1372
ecd8faea
BW		 1373 seq_printf(m, "RC6 voltage: %dmV\n",
1374 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1375 seq_printf(m, "RC6+ voltage: %dmV\n",
1376 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1377 seq_printf(m, "RC6++ voltage: %dmV\n",
1378 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1379 return 0;
1380}
1381
1382static int i915_drpc_info(struct seq_file *m, void *unused)
1383{
1384 struct drm_info_node *node = (struct drm_info_node *) m->private;
1385 struct drm_device *dev = node->minor->dev;
1386
669ab5aa
D		 1387 if (IS_VALLEYVIEW(dev))
1388 return vlv_drpc_info(m);
1389 else if (IS_GEN6(dev) || IS_GEN7(dev))
4d85529d
BW		 1390 return gen6_drpc_info(m);
1391 else
1392 return ironlake_drpc_info(m);
1393}
1394
b5e50c3f
JB		 1395static int i915_fbc_status(struct seq_file *m, void *unused)
1396{
1397 struct drm_info_node *node = (struct drm_info_node *) m->private;
1398 struct drm_device *dev = node->minor->dev;
e277a1f8 1399 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1400
3a77c4c4 1401 if (!HAS_FBC(dev)) {
267f0c90 1402 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1403 return 0;
1404 }
1405
36623ef8
PZ		 1406 intel_runtime_pm_get(dev_priv);
1407
ee5382ae 1408 if (intel_fbc_enabled(dev)) {
267f0c90 1409 seq_puts(m, "FBC enabled\n");
b5e50c3f 1410 } else {
267f0c90 1411 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1412 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1413 case FBC_OK:
1414 seq_puts(m, "FBC actived, but currently disabled in hardware");
1415 break;
1416 case FBC_UNSUPPORTED:
1417 seq_puts(m, "unsupported by this chipset");
1418 break;
bed4a673 1419 case FBC_NO_OUTPUT:
267f0c90 1420 seq_puts(m, "no outputs");
bed4a673 1421 break;
b5e50c3f 1422 case FBC_STOLEN_TOO_SMALL:
267f0c90 1423 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1424 break;
1425 case FBC_UNSUPPORTED_MODE:
267f0c90 1426 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1427 break;
1428 case FBC_MODE_TOO_LARGE:
267f0c90 1429 seq_puts(m, "mode too large");
b5e50c3f
JB		 1430 break;
1431 case FBC_BAD_PLANE:
267f0c90 1432 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1433 break;
1434 case FBC_NOT_TILED:
267f0c90 1435 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1436 break;
9c928d16 1437 case FBC_MULTIPLE_PIPES:
267f0c90 1438 seq_puts(m, "multiple pipes are enabled");
9c928d16 1439 break;
c1a9f047 1440 case FBC_MODULE_PARAM:
267f0c90 1441 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1442 break;
8a5729a3 1443 case FBC_CHIP_DEFAULT:
267f0c90 1444 seq_puts(m, "disabled per chip default");
8a5729a3 1445 break;
b5e50c3f 1446 default:
267f0c90 1447 seq_puts(m, "unknown reason");
b5e50c3f 1448 }
267f0c90 1449 seq_putc(m, '\n');
b5e50c3f 1450 }
36623ef8
PZ		 1451
1452 intel_runtime_pm_put(dev_priv);
1453
b5e50c3f
JB		 1454 return 0;
1455}
1456
92d44621
PZ		 1457static int i915_ips_status(struct seq_file *m, void *unused)
1458{
1459 struct drm_info_node *node = (struct drm_info_node *) m->private;
1460 struct drm_device *dev = node->minor->dev;
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462
f5adf94e 1463 if (!HAS_IPS(dev)) {
92d44621
PZ		 1464 seq_puts(m, "not supported\n");
1465 return 0;
1466 }
1467
36623ef8
PZ		 1468 intel_runtime_pm_get(dev_priv);
1469
e59150dc 1470 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
92d44621
PZ		 1471 seq_puts(m, "enabled\n");
1472 else
1473 seq_puts(m, "disabled\n");
1474
36623ef8
PZ		 1475 intel_runtime_pm_put(dev_priv);
1476
92d44621
PZ		 1477 return 0;
1478}
1479
4a9bef37
JB		 1480static int i915_sr_status(struct seq_file *m, void *unused)
1481{
1482 struct drm_info_node *node = (struct drm_info_node *) m->private;
1483 struct drm_device *dev = node->minor->dev;
e277a1f8 1484 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1485 bool sr_enabled = false;
1486
36623ef8
PZ		 1487 intel_runtime_pm_get(dev_priv);
1488
1398261a 1489 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1490 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1491 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1492 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1493 else if (IS_I915GM(dev))
1494 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1495 else if (IS_PINEVIEW(dev))
1496 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1497
36623ef8
PZ		 1498 intel_runtime_pm_put(dev_priv);
1499
5ba2aaaa
CW		 1500 seq_printf(m, "self-refresh: %s\n",
1501 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1502
1503 return 0;
1504}
1505
7648fa99
JB		 1506static int i915_emon_status(struct seq_file *m, void *unused)
1507{
1508 struct drm_info_node *node = (struct drm_info_node *) m->private;
1509 struct drm_device *dev = node->minor->dev;
e277a1f8 1510 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1511 unsigned long temp, chipset, gfx;
de227ef0
CW		 1512 int ret;
1513
582be6b4
CW		 1514 if (!IS_GEN5(dev))
1515 return -ENODEV;
1516
de227ef0
CW		 1517 ret = mutex_lock_interruptible(&dev->struct_mutex);
1518 if (ret)
1519 return ret;
7648fa99
JB		 1520
1521 temp = i915_mch_val(dev_priv);
1522 chipset = i915_chipset_val(dev_priv);
1523 gfx = i915_gfx_val(dev_priv);
de227ef0 1524 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1525
1526 seq_printf(m, "GMCH temp: %ld\n", temp);
1527 seq_printf(m, "Chipset power: %ld\n", chipset);
1528 seq_printf(m, "GFX power: %ld\n", gfx);
1529 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1530
1531 return 0;
1532}
1533
23b2f8bb
JB		 1534static int i915_ring_freq_table(struct seq_file *m, void *unused)
1535{
1536 struct drm_info_node *node = (struct drm_info_node *) m->private;
1537 struct drm_device *dev = node->minor->dev;
e277a1f8 1538 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1539 int ret = 0;
23b2f8bb
JB		 1540 int gpu_freq, ia_freq;
1541
1c70c0ce 1542 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1543 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1544 return 0;
1545 }
1546
5bfa0199
PZ		 1547 intel_runtime_pm_get(dev_priv);
1548
5c9669ce
TR		 1549 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1550
4fc688ce 1551 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1552 if (ret)
5bfa0199 1553 goto out;
23b2f8bb 1554
267f0c90 1555 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1556
b39fb297
BW		 1557 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1558 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1559 gpu_freq++) {
42c0526c
BW		 1560 ia_freq = gpu_freq;
1561 sandybridge_pcode_read(dev_priv,
1562 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1563 &ia_freq);
3ebecd07
CW		 1564 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1565 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1566 ((ia_freq >> 0) & 0xff) * 100,
1567 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1568 }
1569
4fc688ce 1570 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1571
5bfa0199
PZ		 1572out:
1573 intel_runtime_pm_put(dev_priv);
1574 return ret;
23b2f8bb
JB		 1575}
1576
7648fa99
JB		 1577static int i915_gfxec(struct seq_file *m, void *unused)
1578{
1579 struct drm_info_node *node = (struct drm_info_node *) m->private;
1580 struct drm_device *dev = node->minor->dev;
e277a1f8 1581 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1582 int ret;
1583
1584 ret = mutex_lock_interruptible(&dev->struct_mutex);
1585 if (ret)
1586 return ret;
c8c8fb33 1587 intel_runtime_pm_get(dev_priv);
7648fa99
JB		 1588
1589 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
c8c8fb33 1590 intel_runtime_pm_put(dev_priv);
7648fa99 1591
616fdb5a
BW		 1592 mutex_unlock(&dev->struct_mutex);
1593
7648fa99
JB		 1594 return 0;
1595}
1596
44834a67
CW		 1597static int i915_opregion(struct seq_file *m, void *unused)
1598{
1599 struct drm_info_node *node = (struct drm_info_node *) m->private;
1600 struct drm_device *dev = node->minor->dev;
e277a1f8 1601 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1602 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1603 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1604 int ret;
1605
0d38f009
DV		 1606 if (data == NULL)
1607 return -ENOMEM;
1608
44834a67
CW		 1609 ret = mutex_lock_interruptible(&dev->struct_mutex);
1610 if (ret)
0d38f009 1611 goto out;
44834a67 1612
0d38f009
DV		 1613 if (opregion->header) {
1614 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1615 seq_write(m, data, OPREGION_SIZE);
1616 }
44834a67
CW		 1617
1618 mutex_unlock(&dev->struct_mutex);
1619
0d38f009
DV		 1620out:
1621 kfree(data);
44834a67
CW		 1622 return 0;
1623}
1624
37811fcc
CW		 1625static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1626{
1627 struct drm_info_node *node = (struct drm_info_node *) m->private;
1628 struct drm_device *dev = node->minor->dev;
4520f53a 1629 struct intel_fbdev *ifbdev = NULL;
37811fcc 1630 struct intel_framebuffer *fb;
37811fcc 1631
4520f53a
DV		 1632#ifdef CONFIG_DRM_I915_FBDEV
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1635 if (ret)
1636 return ret;
1637
1638 ifbdev = dev_priv->fbdev;
1639 fb = to_intel_framebuffer(ifbdev->helper.fb);
1640
623f9783 1641 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1642 fb->base.width,
1643 fb->base.height,
1644 fb->base.depth,
623f9783
DV		 1645 fb->base.bits_per_pixel,
1646 atomic_read(&fb->base.refcount.refcount));
05394f39 1647 describe_obj(m, fb->obj);
267f0c90 1648 seq_putc(m, '\n');
4b096ac1 1649 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1650#endif
37811fcc 1651
4b096ac1 1652 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1653 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1654 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1655 continue;
1656
623f9783 1657 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1658 fb->base.width,
1659 fb->base.height,
1660 fb->base.depth,
623f9783
DV		 1661 fb->base.bits_per_pixel,
1662 atomic_read(&fb->base.refcount.refcount));
05394f39 1663 describe_obj(m, fb->obj);
267f0c90 1664 seq_putc(m, '\n');
37811fcc 1665 }
4b096ac1 1666 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1667
1668 return 0;
1669}
1670
e76d3630
BW		 1671static int i915_context_status(struct seq_file *m, void *unused)
1672{
1673 struct drm_info_node *node = (struct drm_info_node *) m->private;
1674 struct drm_device *dev = node->minor->dev;
e277a1f8 1675 struct drm_i915_private *dev_priv = dev->dev_private;
a168c293 1676 struct intel_ring_buffer *ring;
a33afea5 1677 struct i915_hw_context *ctx;
a168c293 1678 int ret, i;
e76d3630
BW		 1679
1680 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1681 if (ret)
1682 return ret;
1683
3e373948 1684 if (dev_priv->ips.pwrctx) {
267f0c90 1685 seq_puts(m, "power context ");
3e373948 1686 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1687 seq_putc(m, '\n');
dc501fbc 1688 }
e76d3630 1689
3e373948 1690 if (dev_priv->ips.renderctx) {
267f0c90 1691 seq_puts(m, "render context ");
3e373948 1692 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1693 seq_putc(m, '\n');
dc501fbc 1694 }
e76d3630 1695
a33afea5
BW		 1696 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1697 seq_puts(m, "HW context ");
3ccfd19d 1698 describe_ctx(m, ctx);
a33afea5
BW		 1699 for_each_ring(ring, dev_priv, i)
1700 if (ring->default_context == ctx)
1701 seq_printf(m, "(default context %s) ", ring->name);
1702
1703 describe_obj(m, ctx->obj);
1704 seq_putc(m, '\n');
a168c293
BW		 1705 }
1706
e76d3630
BW		 1707 mutex_unlock(&dev->mode_config.mutex);
1708
1709 return 0;
1710}
1711
6d794d42
BW		 1712static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1713{
1714 struct drm_info_node *node = (struct drm_info_node *) m->private;
1715 struct drm_device *dev = node->minor->dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1717 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1718
907b28c5 1719 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1720 if (IS_VALLEYVIEW(dev)) {
1721 fw_rendercount = dev_priv->uncore.fw_rendercount;
1722 fw_mediacount = dev_priv->uncore.fw_mediacount;
1723 } else
1724 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1725 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1726
43709ba0
D		 1727 if (IS_VALLEYVIEW(dev)) {
1728 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1729 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1730 } else
1731 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1732
1733 return 0;
1734}
1735
ea16a3cd
DV		 1736static const char *swizzle_string(unsigned swizzle)
1737{
aee56cff 1738 switch (swizzle) {
ea16a3cd
DV		 1739 case I915_BIT_6_SWIZZLE_NONE:
1740 return "none";
1741 case I915_BIT_6_SWIZZLE_9:
1742 return "bit9";
1743 case I915_BIT_6_SWIZZLE_9_10:
1744 return "bit9/bit10";
1745 case I915_BIT_6_SWIZZLE_9_11:
1746 return "bit9/bit11";
1747 case I915_BIT_6_SWIZZLE_9_10_11:
1748 return "bit9/bit10/bit11";
1749 case I915_BIT_6_SWIZZLE_9_17:
1750 return "bit9/bit17";
1751 case I915_BIT_6_SWIZZLE_9_10_17:
1752 return "bit9/bit10/bit17";
1753 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1754 return "unknown";
ea16a3cd
DV		 1755 }
1756
1757 return "bug";
1758}
1759
1760static int i915_swizzle_info(struct seq_file *m, void *data)
1761{
1762 struct drm_info_node *node = (struct drm_info_node *) m->private;
1763 struct drm_device *dev = node->minor->dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1765 int ret;
1766
1767 ret = mutex_lock_interruptible(&dev->struct_mutex);
1768 if (ret)
1769 return ret;
c8c8fb33 1770 intel_runtime_pm_get(dev_priv);
ea16a3cd 1771
ea16a3cd
DV		 1772 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1773 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1774 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1775 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1776
1777 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1778 seq_printf(m, "DDC = 0x%08x\n",
1779 I915_READ(DCC));
1780 seq_printf(m, "C0DRB3 = 0x%04x\n",
1781 I915_READ16(C0DRB3));
1782 seq_printf(m, "C1DRB3 = 0x%04x\n",
1783 I915_READ16(C1DRB3));
9d3203e1 1784 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1785 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1786 I915_READ(MAD_DIMM_C0));
1787 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1788 I915_READ(MAD_DIMM_C1));
1789 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1790 I915_READ(MAD_DIMM_C2));
1791 seq_printf(m, "TILECTL = 0x%08x\n",
1792 I915_READ(TILECTL));
9d3203e1
BW		 1793 if (IS_GEN8(dev))
1794 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1795 I915_READ(GAMTARBMODE));
1796 else
1797 seq_printf(m, "ARB_MODE = 0x%08x\n",
1798 I915_READ(ARB_MODE));
3fa7d235
DV		 1799 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1800 I915_READ(DISP_ARB_CTL));
ea16a3cd 1801 }
c8c8fb33 1802 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1803 mutex_unlock(&dev->struct_mutex);
1804
1805 return 0;
1806}
1807
1c60fef5
BW		 1808static int per_file_ctx(int id, void *ptr, void *data)
1809{
1810 struct i915_hw_context *ctx = ptr;
1811 struct seq_file *m = data;
1812 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1813
1814 ppgtt->debug_dump(ppgtt, m);
1815
1816 return 0;
1817}
1818
77df6772 1819static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1820{
3cf17fc5
DV		 1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 struct intel_ring_buffer *ring;
77df6772
BW		 1823 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1824 int unused, i;
3cf17fc5 1825
77df6772
BW		 1826 if (!ppgtt)
1827 return;
1828
1829 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 1830 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 1831 for_each_ring(ring, dev_priv, unused) {
1832 seq_printf(m, "%s\n", ring->name);
1833 for (i = 0; i < 4; i++) {
1834 u32 offset = 0x270 + i * 8;
1835 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1836 pdp <<= 32;
1837 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 1838 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 1839 }
1840 }
1841}
1842
1843static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1844{
1845 struct drm_i915_private *dev_priv = dev->dev_private;
1846 struct intel_ring_buffer *ring;
1c60fef5 1847 struct drm_file *file;
77df6772 1848 int i;
3cf17fc5 1849
3cf17fc5
DV		 1850 if (INTEL_INFO(dev)->gen == 6)
1851 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1852
a2c7f6fd 1853 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1854 seq_printf(m, "%s\n", ring->name);
1855 if (INTEL_INFO(dev)->gen == 7)
1856 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1857 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1858 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1859 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1860 }
1861 if (dev_priv->mm.aliasing_ppgtt) {
1862 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1863
267f0c90 1864 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 1865 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 1866
87d60b63 1867 ppgtt->debug_dump(ppgtt, m);
1c60fef5
BW		 1868 } else
1869 return;
1870
1871 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1872 struct drm_i915_file_private *file_priv = file->driver_priv;
1873 struct i915_hw_ppgtt *pvt_ppgtt;
1874
1875 pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);
1876 seq_printf(m, "proc: %s\n",
1877 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1878 seq_puts(m, " default context:\n");
1879 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 1880 }
1881 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1882}
1883
1884static int i915_ppgtt_info(struct seq_file *m, void *data)
1885{
1886 struct drm_info_node *node = (struct drm_info_node *) m->private;
1887 struct drm_device *dev = node->minor->dev;
c8c8fb33 1888 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 1889
1890 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1891 if (ret)
1892 return ret;
c8c8fb33 1893 intel_runtime_pm_get(dev_priv);
77df6772
BW		 1894
1895 if (INTEL_INFO(dev)->gen >= 8)
1896 gen8_ppgtt_info(m, dev);
1897 else if (INTEL_INFO(dev)->gen >= 6)
1898 gen6_ppgtt_info(m, dev);
1899
c8c8fb33 1900 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 1901 mutex_unlock(&dev->struct_mutex);
1902
1903 return 0;
1904}
1905
63573eb7
BW		 1906static int i915_llc(struct seq_file *m, void *data)
1907{
1908 struct drm_info_node *node = (struct drm_info_node *) m->private;
1909 struct drm_device *dev = node->minor->dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911
1912 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1913 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1914 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1915
1916 return 0;
1917}
1918
e91fd8c6
RV		 1919static int i915_edp_psr_status(struct seq_file *m, void *data)
1920{
1921 struct drm_info_node *node = m->private;
1922 struct drm_device *dev = node->minor->dev;
1923 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1924 u32 psrperf = 0;
1925 bool enabled = false;
e91fd8c6 1926
c8c8fb33
PZ		 1927 intel_runtime_pm_get(dev_priv);
1928
a031d709
RV		 1929 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1930 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1931
a031d709
RV		 1932 enabled = HAS_PSR(dev) &&
1933 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1934 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1935
a031d709
RV		 1936 if (HAS_PSR(dev))
1937 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1938 EDP_PSR_PERF_CNT_MASK;
1939 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6 1940
c8c8fb33 1941 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 1942 return 0;
1943}
1944
d2e216d0
RV		 1945static int i915_sink_crc(struct seq_file *m, void *data)
1946{
1947 struct drm_info_node *node = m->private;
1948 struct drm_device *dev = node->minor->dev;
1949 struct intel_encoder *encoder;
1950 struct intel_connector *connector;
1951 struct intel_dp *intel_dp = NULL;
1952 int ret;
1953 u8 crc[6];
1954
1955 drm_modeset_lock_all(dev);
1956 list_for_each_entry(connector, &dev->mode_config.connector_list,
1957 base.head) {
1958
1959 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1960 continue;
1961
b6ae3c7c
PZ		 1962 if (!connector->base.encoder)
1963 continue;
1964
d2e216d0
RV		 1965 encoder = to_intel_encoder(connector->base.encoder);
1966 if (encoder->type != INTEL_OUTPUT_EDP)
1967 continue;
1968
1969 intel_dp = enc_to_intel_dp(&encoder->base);
1970
1971 ret = intel_dp_sink_crc(intel_dp, crc);
1972 if (ret)
1973 goto out;
1974
1975 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1976 crc[0], crc[1], crc[2],
1977 crc[3], crc[4], crc[5]);
1978 goto out;
1979 }
1980 ret = -ENODEV;
1981out:
1982 drm_modeset_unlock_all(dev);
1983 return ret;
1984}
1985
ec013e7f
JB		 1986static int i915_energy_uJ(struct seq_file *m, void *data)
1987{
1988 struct drm_info_node *node = m->private;
1989 struct drm_device *dev = node->minor->dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 u64 power;
1992 u32 units;
1993
1994 if (INTEL_INFO(dev)->gen < 6)
1995 return -ENODEV;
1996
36623ef8
PZ		 1997 intel_runtime_pm_get(dev_priv);
1998
ec013e7f
JB		 1999 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2000 power = (power & 0x1f00) >> 8;
2001 units = 1000000 / (1 << power); /* convert to uJ */
2002 power = I915_READ(MCH_SECP_NRG_STTS);
2003 power *= units;
2004
36623ef8
PZ		 2005 intel_runtime_pm_put(dev_priv);
2006
ec013e7f 2007 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2008
2009 return 0;
2010}
2011
2012static int i915_pc8_status(struct seq_file *m, void *unused)
2013{
2014 struct drm_info_node *node = (struct drm_info_node *) m->private;
2015 struct drm_device *dev = node->minor->dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017
85b8d5c2 2018 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2019 seq_puts(m, "not supported\n");
2020 return 0;
2021 }
2022
86c4ec0d 2023 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2024 seq_printf(m, "IRQs disabled: %s\n",
5d584b2e 2025 yesno(dev_priv->pm.irqs_disabled));
371db66a 2026
ec013e7f
JB		 2027 return 0;
2028}
2029
1da51581
ID		 2030static const char *power_domain_str(enum intel_display_power_domain domain)
2031{
2032 switch (domain) {
2033 case POWER_DOMAIN_PIPE_A:
2034 return "PIPE_A";
2035 case POWER_DOMAIN_PIPE_B:
2036 return "PIPE_B";
2037 case POWER_DOMAIN_PIPE_C:
2038 return "PIPE_C";
2039 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2040 return "PIPE_A_PANEL_FITTER";
2041 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2042 return "PIPE_B_PANEL_FITTER";
2043 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2044 return "PIPE_C_PANEL_FITTER";
2045 case POWER_DOMAIN_TRANSCODER_A:
2046 return "TRANSCODER_A";
2047 case POWER_DOMAIN_TRANSCODER_B:
2048 return "TRANSCODER_B";
2049 case POWER_DOMAIN_TRANSCODER_C:
2050 return "TRANSCODER_C";
2051 case POWER_DOMAIN_TRANSCODER_EDP:
2052 return "TRANSCODER_EDP";
319be8ae
ID		 2053 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2054 return "PORT_DDI_A_2_LANES";
2055 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2056 return "PORT_DDI_A_4_LANES";
2057 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2058 return "PORT_DDI_B_2_LANES";
2059 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2060 return "PORT_DDI_B_4_LANES";
2061 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2062 return "PORT_DDI_C_2_LANES";
2063 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2064 return "PORT_DDI_C_4_LANES";
2065 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2066 return "PORT_DDI_D_2_LANES";
2067 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2068 return "PORT_DDI_D_4_LANES";
2069 case POWER_DOMAIN_PORT_DSI:
2070 return "PORT_DSI";
2071 case POWER_DOMAIN_PORT_CRT:
2072 return "PORT_CRT";
2073 case POWER_DOMAIN_PORT_OTHER:
2074 return "PORT_OTHER";
1da51581
ID		 2075 case POWER_DOMAIN_VGA:
2076 return "VGA";
2077 case POWER_DOMAIN_AUDIO:
2078 return "AUDIO";
2079 case POWER_DOMAIN_INIT:
2080 return "INIT";
2081 default:
2082 WARN_ON(1);
2083 return "?";
2084 }
2085}
2086
2087static int i915_power_domain_info(struct seq_file *m, void *unused)
2088{
2089 struct drm_info_node *node = (struct drm_info_node *) m->private;
2090 struct drm_device *dev = node->minor->dev;
2091 struct drm_i915_private *dev_priv = dev->dev_private;
2092 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2093 int i;
2094
2095 mutex_lock(&power_domains->lock);
2096
2097 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2098 for (i = 0; i < power_domains->power_well_count; i++) {
2099 struct i915_power_well *power_well;
2100 enum intel_display_power_domain power_domain;
2101
2102 power_well = &power_domains->power_wells[i];
2103 seq_printf(m, "%-25s %d\n", power_well->name,
2104 power_well->count);
2105
2106 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2107 power_domain++) {
2108 if (!(BIT(power_domain) & power_well->domains))
2109 continue;
2110
2111 seq_printf(m, " %-23s %d\n",
2112 power_domain_str(power_domain),
2113 power_domains->domain_use_count[power_domain]);
2114 }
2115 }
2116
2117 mutex_unlock(&power_domains->lock);
2118
2119 return 0;
2120}
2121
53f5e3ca
JB		 2122static void intel_seq_print_mode(struct seq_file *m, int tabs,
2123 struct drm_display_mode *mode)
2124{
2125 int i;
2126
2127 for (i = 0; i < tabs; i++)
2128 seq_putc(m, '\t');
2129
2130 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2131 mode->base.id, mode->name,
2132 mode->vrefresh, mode->clock,
2133 mode->hdisplay, mode->hsync_start,
2134 mode->hsync_end, mode->htotal,
2135 mode->vdisplay, mode->vsync_start,
2136 mode->vsync_end, mode->vtotal,
2137 mode->type, mode->flags);
2138}
2139
2140static void intel_encoder_info(struct seq_file *m,
2141 struct intel_crtc *intel_crtc,
2142 struct intel_encoder *intel_encoder)
2143{
2144 struct drm_info_node *node = (struct drm_info_node *) m->private;
2145 struct drm_device *dev = node->minor->dev;
2146 struct drm_crtc *crtc = &intel_crtc->base;
2147 struct intel_connector *intel_connector;
2148 struct drm_encoder *encoder;
2149
2150 encoder = &intel_encoder->base;
2151 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2152 encoder->base.id, drm_get_encoder_name(encoder));
2153 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2154 struct drm_connector *connector = &intel_connector->base;
2155 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2156 connector->base.id,
2157 drm_get_connector_name(connector),
2158 drm_get_connector_status_name(connector->status));
2159 if (connector->status == connector_status_connected) {
2160 struct drm_display_mode *mode = &crtc->mode;
2161 seq_printf(m, ", mode:\n");
2162 intel_seq_print_mode(m, 2, mode);
2163 } else {
2164 seq_putc(m, '\n');
2165 }
2166 }
2167}
2168
2169static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2170{
2171 struct drm_info_node *node = (struct drm_info_node *) m->private;
2172 struct drm_device *dev = node->minor->dev;
2173 struct drm_crtc *crtc = &intel_crtc->base;
2174 struct intel_encoder *intel_encoder;
2175
2176 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
f4510a27
MR		 2177 crtc->primary->fb->base.id, crtc->x, crtc->y,
2178 crtc->primary->fb->width, crtc->primary->fb->height);
53f5e3ca
JB		 2179 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2180 intel_encoder_info(m, intel_crtc, intel_encoder);
2181}
2182
2183static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2184{
2185 struct drm_display_mode *mode = panel->fixed_mode;
2186
2187 seq_printf(m, "\tfixed mode:\n");
2188 intel_seq_print_mode(m, 2, mode);
2189}
2190
2191static void intel_dp_info(struct seq_file *m,
2192 struct intel_connector *intel_connector)
2193{
2194 struct intel_encoder *intel_encoder = intel_connector->encoder;
2195 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2196
2197 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2198 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2199 "no");
2200 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2201 intel_panel_info(m, &intel_connector->panel);
2202}
2203
2204static void intel_hdmi_info(struct seq_file *m,
2205 struct intel_connector *intel_connector)
2206{
2207 struct intel_encoder *intel_encoder = intel_connector->encoder;
2208 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2209
2210 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2211 "no");
2212}
2213
2214static void intel_lvds_info(struct seq_file *m,
2215 struct intel_connector *intel_connector)
2216{
2217 intel_panel_info(m, &intel_connector->panel);
2218}
2219
2220static void intel_connector_info(struct seq_file *m,
2221 struct drm_connector *connector)
2222{
2223 struct intel_connector *intel_connector = to_intel_connector(connector);
2224 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2225 struct drm_display_mode *mode;
53f5e3ca
JB		 2226
2227 seq_printf(m, "connector %d: type %s, status: %s\n",
2228 connector->base.id, drm_get_connector_name(connector),
2229 drm_get_connector_status_name(connector->status));
2230 if (connector->status == connector_status_connected) {
2231 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2232 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2233 connector->display_info.width_mm,
2234 connector->display_info.height_mm);
2235 seq_printf(m, "\tsubpixel order: %s\n",
2236 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2237 seq_printf(m, "\tCEA rev: %d\n",
2238 connector->display_info.cea_rev);
2239 }
2240 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2241 intel_encoder->type == INTEL_OUTPUT_EDP)
2242 intel_dp_info(m, intel_connector);
2243 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2244 intel_hdmi_info(m, intel_connector);
2245 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2246 intel_lvds_info(m, intel_connector);
2247
f103fc7d
JB		 2248 seq_printf(m, "\tmodes:\n");
2249 list_for_each_entry(mode, &connector->modes, head)
2250 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2251}
2252
065f2ec2
CW		 2253static bool cursor_active(struct drm_device *dev, int pipe)
2254{
2255 struct drm_i915_private *dev_priv = dev->dev_private;
2256 u32 state;
2257
2258 if (IS_845G(dev) || IS_I865G(dev))
2259 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2260 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
2261 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2262 else
2263 state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
2264
2265 return state;
2266}
2267
2268static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2269{
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271 u32 pos;
2272
2273 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
2274 pos = I915_READ(CURPOS_IVB(pipe));
2275 else
2276 pos = I915_READ(CURPOS(pipe));
2277
2278 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2279 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2280 *x = -*x;
2281
2282 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2283 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2284 *y = -*y;
2285
2286 return cursor_active(dev, pipe);
2287}
2288
53f5e3ca
JB		 2289static int i915_display_info(struct seq_file *m, void *unused)
2290{
2291 struct drm_info_node *node = (struct drm_info_node *) m->private;
2292 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2293 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2294 struct intel_crtc *crtc;
53f5e3ca
JB		 2295 struct drm_connector *connector;
2296
b0e5ddf3 2297 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2298 drm_modeset_lock_all(dev);
2299 seq_printf(m, "CRTC info\n");
2300 seq_printf(m, "---------\n");
065f2ec2
CW		 2301 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2302 bool active;
2303 int x, y;
53f5e3ca
JB		 2304
2305 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
065f2ec2
CW		 2306 crtc->base.base.id, pipe_name(crtc->pipe),
2307 yesno(crtc->active));
a23dc658 2308 if (crtc->active) {
065f2ec2
CW		 2309 intel_crtc_info(m, crtc);
2310
a23dc658
PZ		 2311 active = cursor_position(dev, crtc->pipe, &x, &y);
2312 seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2313 yesno(crtc->cursor_visible),
2314 x, y, crtc->cursor_addr,
2315 yesno(active));
2316 }
53f5e3ca
JB		 2317 }
2318
2319 seq_printf(m, "\n");
2320 seq_printf(m, "Connector info\n");
2321 seq_printf(m, "--------------\n");
2322 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2323 intel_connector_info(m, connector);
2324 }
2325 drm_modeset_unlock_all(dev);
b0e5ddf3 2326 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2327
2328 return 0;
2329}
2330
07144428
DL		 2331struct pipe_crc_info {
2332 const char *name;
2333 struct drm_device *dev;
2334 enum pipe pipe;
2335};
2336
2337static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2338{
be5c7a90
DL		 2339 struct pipe_crc_info *info = inode->i_private;
2340 struct drm_i915_private *dev_priv = info->dev->dev_private;
2341 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2342
7eb1c496
DV		 2343 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2344 return -ENODEV;
2345
d538bbdf
DL		 2346 spin_lock_irq(&pipe_crc->lock);
2347
2348 if (pipe_crc->opened) {
2349 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2350 return -EBUSY; /* already open */
2351 }
2352
d538bbdf 2353 pipe_crc->opened = true;
07144428
DL		 2354 filep->private_data = inode->i_private;
2355
d538bbdf
DL		 2356 spin_unlock_irq(&pipe_crc->lock);
2357
07144428
DL		 2358 return 0;
2359}
2360
2361static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2362{
be5c7a90
DL		 2363 struct pipe_crc_info *info = inode->i_private;
2364 struct drm_i915_private *dev_priv = info->dev->dev_private;
2365 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2366
d538bbdf
DL		 2367 spin_lock_irq(&pipe_crc->lock);
2368 pipe_crc->opened = false;
2369 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2370
07144428
DL		 2371 return 0;
2372}
2373
2374/* (6 fields, 8 chars each, space separated (5) + '\n') */
2375#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2376/* account for \'0' */
2377#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2378
2379static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2380{
d538bbdf
DL		 2381 assert_spin_locked(&pipe_crc->lock);
2382 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2383 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2384}
2385
2386static ssize_t
2387i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2388 loff_t *pos)
2389{
2390 struct pipe_crc_info *info = filep->private_data;
2391 struct drm_device *dev = info->dev;
2392 struct drm_i915_private *dev_priv = dev->dev_private;
2393 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2394 char buf[PIPE_CRC_BUFFER_LEN];
2395 int head, tail, n_entries, n;
2396 ssize_t bytes_read;
2397
2398 /*
2399 * Don't allow user space to provide buffers not big enough to hold
2400 * a line of data.
2401 */
2402 if (count < PIPE_CRC_LINE_LEN)
2403 return -EINVAL;
2404
2405 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2406 return 0;
07144428
DL		 2407
2408 /* nothing to read */
d538bbdf 2409 spin_lock_irq(&pipe_crc->lock);
07144428 2410 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2411 int ret;
2412
2413 if (filep->f_flags & O_NONBLOCK) {
2414 spin_unlock_irq(&pipe_crc->lock);
07144428 2415 return -EAGAIN;
d538bbdf 2416 }
07144428 2417
d538bbdf
DL		 2418 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2419 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2420 if (ret) {
2421 spin_unlock_irq(&pipe_crc->lock);
2422 return ret;
2423 }
8bf1e9f1
SH		 2424 }
2425
07144428 2426 /* We now have one or more entries to read */
d538bbdf
DL		 2427 head = pipe_crc->head;
2428 tail = pipe_crc->tail;
07144428
DL		 2429 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2430 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2431 spin_unlock_irq(&pipe_crc->lock);
2432
07144428
DL		 2433 bytes_read = 0;
2434 n = 0;
2435 do {
b2c88f5b 2436 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2437 int ret;
8bf1e9f1 2438
07144428
DL		 2439 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2440 "%8u %8x %8x %8x %8x %8x\n",
2441 entry->frame, entry->crc[0],
2442 entry->crc[1], entry->crc[2],
2443 entry->crc[3], entry->crc[4]);
2444
2445 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2446 buf, PIPE_CRC_LINE_LEN);
2447 if (ret == PIPE_CRC_LINE_LEN)
2448 return -EFAULT;
b2c88f5b
DL		 2449
2450 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2451 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2452 n++;
2453 } while (--n_entries);
8bf1e9f1 2454
d538bbdf
DL		 2455 spin_lock_irq(&pipe_crc->lock);
2456 pipe_crc->tail = tail;
2457 spin_unlock_irq(&pipe_crc->lock);
2458
07144428
DL		 2459 return bytes_read;
2460}
2461
2462static const struct file_operations i915_pipe_crc_fops = {
2463 .owner = THIS_MODULE,
2464 .open = i915_pipe_crc_open,
2465 .read = i915_pipe_crc_read,
2466 .release = i915_pipe_crc_release,
2467};
2468
2469static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2470 {
2471 .name = "i915_pipe_A_crc",
2472 .pipe = PIPE_A,
2473 },
2474 {
2475 .name = "i915_pipe_B_crc",
2476 .pipe = PIPE_B,
2477 },
2478 {
2479 .name = "i915_pipe_C_crc",
2480 .pipe = PIPE_C,
2481 },
2482};
2483
2484static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2485 enum pipe pipe)
2486{
2487 struct drm_device *dev = minor->dev;
2488 struct dentry *ent;
2489 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2490
2491 info->dev = dev;
2492 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2493 &i915_pipe_crc_fops);
f3c5fe97
WY		 2494 if (!ent)
2495 return -ENOMEM;
07144428
DL		 2496
2497 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2498}
2499
e8dfcf78 2500static const char * const pipe_crc_sources[] = {
926321d5
DV		 2501 "none",
2502 "plane1",
2503 "plane2",
2504 "pf",
5b3a856b 2505 "pipe",
3d099a05
DV		 2506 "TV",
2507 "DP-B",
2508 "DP-C",
2509 "DP-D",
46a19188 2510 "auto",
926321d5
DV		 2511};
2512
2513static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2514{
2515 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2516 return pipe_crc_sources[source];
2517}
2518
bd9db02f 2519static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2520{
2521 struct drm_device *dev = m->private;
2522 struct drm_i915_private *dev_priv = dev->dev_private;
2523 int i;
2524
2525 for (i = 0; i < I915_MAX_PIPES; i++)
2526 seq_printf(m, "%c %s\n", pipe_name(i),
2527 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2528
2529 return 0;
2530}
2531
bd9db02f 2532static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2533{
2534 struct drm_device *dev = inode->i_private;
2535
bd9db02f 2536 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2537}
2538
46a19188 2539static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2540 uint32_t *val)
2541{
46a19188
DV		 2542 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2543 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2544
2545 switch (*source) {
52f843f6
DV		 2546 case INTEL_PIPE_CRC_SOURCE_PIPE:
2547 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2548 break;
2549 case INTEL_PIPE_CRC_SOURCE_NONE:
2550 *val = 0;
2551 break;
2552 default:
2553 return -EINVAL;
2554 }
2555
2556 return 0;
2557}
2558
46a19188
DV		 2559static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2560 enum intel_pipe_crc_source *source)
2561{
2562 struct intel_encoder *encoder;
2563 struct intel_crtc *crtc;
26756809 2564 struct intel_digital_port *dig_port;
46a19188
DV		 2565 int ret = 0;
2566
2567 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2568
2569 mutex_lock(&dev->mode_config.mutex);
2570 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2571 base.head) {
2572 if (!encoder->base.crtc)
2573 continue;
2574
2575 crtc = to_intel_crtc(encoder->base.crtc);
2576
2577 if (crtc->pipe != pipe)
2578 continue;
2579
2580 switch (encoder->type) {
2581 case INTEL_OUTPUT_TVOUT:
2582 *source = INTEL_PIPE_CRC_SOURCE_TV;
2583 break;
2584 case INTEL_OUTPUT_DISPLAYPORT:
2585 case INTEL_OUTPUT_EDP:
26756809
DV		 2586 dig_port = enc_to_dig_port(&encoder->base);
2587 switch (dig_port->port) {
2588 case PORT_B:
2589 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2590 break;
2591 case PORT_C:
2592 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2593 break;
2594 case PORT_D:
2595 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2596 break;
2597 default:
2598 WARN(1, "nonexisting DP port %c\n",
2599 port_name(dig_port->port));
2600 break;
2601 }
46a19188
DV		 2602 break;
2603 }
2604 }
2605 mutex_unlock(&dev->mode_config.mutex);
2606
2607 return ret;
2608}
2609
2610static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2611 enum pipe pipe,
2612 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2613 uint32_t *val)
2614{
8d2f24ca
DV		 2615 struct drm_i915_private *dev_priv = dev->dev_private;
2616 bool need_stable_symbols = false;
2617
46a19188
DV		 2618 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2619 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2620 if (ret)
2621 return ret;
2622 }
2623
2624 switch (*source) {
7ac0129b
DV		 2625 case INTEL_PIPE_CRC_SOURCE_PIPE:
2626 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2627 break;
2628 case INTEL_PIPE_CRC_SOURCE_DP_B:
2629 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2630 need_stable_symbols = true;
7ac0129b
DV		 2631 break;
2632 case INTEL_PIPE_CRC_SOURCE_DP_C:
2633 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2634 need_stable_symbols = true;
7ac0129b
DV		 2635 break;
2636 case INTEL_PIPE_CRC_SOURCE_NONE:
2637 *val = 0;
2638 break;
2639 default:
2640 return -EINVAL;
2641 }
2642
8d2f24ca
DV		 2643 /*
2644 * When the pipe CRC tap point is after the transcoders we need
2645 * to tweak symbol-level features to produce a deterministic series of
2646 * symbols for a given frame. We need to reset those features only once
2647 * a frame (instead of every nth symbol):
2648 * - DC-balance: used to ensure a better clock recovery from the data
2649 * link (SDVO)
2650 * - DisplayPort scrambling: used for EMI reduction
2651 */
2652 if (need_stable_symbols) {
2653 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2654
8d2f24ca
DV		 2655 tmp |= DC_BALANCE_RESET_VLV;
2656 if (pipe == PIPE_A)
2657 tmp |= PIPE_A_SCRAMBLE_RESET;
2658 else
2659 tmp |= PIPE_B_SCRAMBLE_RESET;
2660
2661 I915_WRITE(PORT_DFT2_G4X, tmp);
2662 }
2663
7ac0129b
DV		 2664 return 0;
2665}
2666
4b79ebf7 2667static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2668 enum pipe pipe,
2669 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2670 uint32_t *val)
2671{
84093603
DV		 2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 bool need_stable_symbols = false;
2674
46a19188
DV		 2675 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2676 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2677 if (ret)
2678 return ret;
2679 }
2680
2681 switch (*source) {
4b79ebf7
DV		 2682 case INTEL_PIPE_CRC_SOURCE_PIPE:
2683 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2684 break;
2685 case INTEL_PIPE_CRC_SOURCE_TV:
2686 if (!SUPPORTS_TV(dev))
2687 return -EINVAL;
2688 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2689 break;
2690 case INTEL_PIPE_CRC_SOURCE_DP_B:
2691 if (!IS_G4X(dev))
2692 return -EINVAL;
2693 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2694 need_stable_symbols = true;
4b79ebf7
DV		 2695 break;
2696 case INTEL_PIPE_CRC_SOURCE_DP_C:
2697 if (!IS_G4X(dev))
2698 return -EINVAL;
2699 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2700 need_stable_symbols = true;
4b79ebf7
DV		 2701 break;
2702 case INTEL_PIPE_CRC_SOURCE_DP_D:
2703 if (!IS_G4X(dev))
2704 return -EINVAL;
2705 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2706 need_stable_symbols = true;
4b79ebf7
DV		 2707 break;
2708 case INTEL_PIPE_CRC_SOURCE_NONE:
2709 *val = 0;
2710 break;
2711 default:
2712 return -EINVAL;
2713 }
2714
84093603
DV		 2715 /*
2716 * When the pipe CRC tap point is after the transcoders we need
2717 * to tweak symbol-level features to produce a deterministic series of
2718 * symbols for a given frame. We need to reset those features only once
2719 * a frame (instead of every nth symbol):
2720 * - DC-balance: used to ensure a better clock recovery from the data
2721 * link (SDVO)
2722 * - DisplayPort scrambling: used for EMI reduction
2723 */
2724 if (need_stable_symbols) {
2725 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2726
2727 WARN_ON(!IS_G4X(dev));
2728
2729 I915_WRITE(PORT_DFT_I9XX,
2730 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2731
2732 if (pipe == PIPE_A)
2733 tmp |= PIPE_A_SCRAMBLE_RESET;
2734 else
2735 tmp |= PIPE_B_SCRAMBLE_RESET;
2736
2737 I915_WRITE(PORT_DFT2_G4X, tmp);
2738 }
2739
4b79ebf7
DV		 2740 return 0;
2741}
2742
8d2f24ca
DV		 2743static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2744 enum pipe pipe)
2745{
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2748
2749 if (pipe == PIPE_A)
2750 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2751 else
2752 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2753 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2754 tmp &= ~DC_BALANCE_RESET_VLV;
2755 I915_WRITE(PORT_DFT2_G4X, tmp);
2756
2757}
2758
84093603
DV		 2759static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2760 enum pipe pipe)
2761{
2762 struct drm_i915_private *dev_priv = dev->dev_private;
2763 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2764
2765 if (pipe == PIPE_A)
2766 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2767 else
2768 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2769 I915_WRITE(PORT_DFT2_G4X, tmp);
2770
2771 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2772 I915_WRITE(PORT_DFT_I9XX,
2773 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2774 }
2775}
2776
46a19188 2777static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2778 uint32_t *val)
2779{
46a19188
DV		 2780 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2781 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2782
2783 switch (*source) {
5b3a856b
DV		 2784 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2785 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2786 break;
2787 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2788 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2789 break;
5b3a856b
DV		 2790 case INTEL_PIPE_CRC_SOURCE_PIPE:
2791 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2792 break;
3d099a05 2793 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2794 *val = 0;
2795 break;
3d099a05
DV		 2796 default:
2797 return -EINVAL;
5b3a856b
DV		 2798 }
2799
2800 return 0;
2801}
2802
46a19188 2803static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2804 uint32_t *val)
2805{
46a19188
DV		 2806 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2807 *source = INTEL_PIPE_CRC_SOURCE_PF;
2808
2809 switch (*source) {
5b3a856b
DV		 2810 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2811 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2812 break;
2813 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2814 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2815 break;
2816 case INTEL_PIPE_CRC_SOURCE_PF:
2817 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2818 break;
3d099a05 2819 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2820 *val = 0;
2821 break;
3d099a05
DV		 2822 default:
2823 return -EINVAL;
5b3a856b
DV		 2824 }
2825
2826 return 0;
2827}
2828
926321d5
DV		 2829static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2830 enum intel_pipe_crc_source source)
2831{
2832 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2833 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2834 u32 val = 0; /* shut up gcc */
5b3a856b 2835 int ret;
926321d5 2836
cc3da175
DL		 2837 if (pipe_crc->source == source)
2838 return 0;
2839
ae676fcd
DL		 2840 /* forbid changing the source without going back to 'none' */
2841 if (pipe_crc->source && source)
2842 return -EINVAL;
2843
52f843f6 2844 if (IS_GEN2(dev))
46a19188 2845 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2846 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2847 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2848 else if (IS_VALLEYVIEW(dev))
46a19188 2849 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2850 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2851 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2852 else
46a19188 2853 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2854
2855 if (ret != 0)
2856 return ret;
2857
4b584369
DL		 2858 /* none -> real source transition */
2859 if (source) {
7cd6ccff
DL		 2860 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2861 pipe_name(pipe), pipe_crc_source_name(source));
2862
e5f75aca
DL		 2863 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2864 INTEL_PIPE_CRC_ENTRIES_NR,
2865 GFP_KERNEL);
2866 if (!pipe_crc->entries)
2867 return -ENOMEM;
2868
d538bbdf
DL		 2869 spin_lock_irq(&pipe_crc->lock);
2870 pipe_crc->head = 0;
2871 pipe_crc->tail = 0;
2872 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2873 }
2874
cc3da175 2875 pipe_crc->source = source;
926321d5 2876
926321d5
DV		 2877 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2878 POSTING_READ(PIPE_CRC_CTL(pipe));
2879
e5f75aca
DL		 2880 /* real source -> none transition */
2881 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2882 struct intel_pipe_crc_entry *entries;
2883
7cd6ccff
DL		 2884 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2885 pipe_name(pipe));
2886
bcf17ab2
DV		 2887 intel_wait_for_vblank(dev, pipe);
2888
d538bbdf
DL		 2889 spin_lock_irq(&pipe_crc->lock);
2890 entries = pipe_crc->entries;
e5f75aca 2891 pipe_crc->entries = NULL;
d538bbdf
DL		 2892 spin_unlock_irq(&pipe_crc->lock);
2893
2894 kfree(entries);
84093603
DV		 2895
2896 if (IS_G4X(dev))
2897 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2898 else if (IS_VALLEYVIEW(dev))
2899 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2900 }
2901
926321d5
DV		 2902 return 0;
2903}
2904
2905/*
2906 * Parse pipe CRC command strings:
b94dec87
DL		 2907 * command: wsp* object wsp+ name wsp+ source wsp*
2908 * object: 'pipe'
2909 * name: (A | B | C)
926321d5
DV		 2910 * source: (none | plane1 | plane2 | pf)
2911 * wsp: (#0x20 | #0x9 | #0xA)+
2912 *
2913 * eg.:
b94dec87
DL		 2914 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2915 * "pipe A none" -> Stop CRC
926321d5 2916 */
bd9db02f 2917static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2918{
2919 int n_words = 0;
2920
2921 while (*buf) {
2922 char *end;
2923
2924 /* skip leading white space */
2925 buf = skip_spaces(buf);
2926 if (!*buf)
2927 break; /* end of buffer */
2928
2929 /* find end of word */
2930 for (end = buf; *end && !isspace(*end); end++)
2931 ;
2932
2933 if (n_words == max_words) {
2934 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2935 max_words);
2936 return -EINVAL; /* ran out of words[] before bytes */
2937 }
2938
2939 if (*end)
2940 *end++ = '\0';
2941 words[n_words++] = buf;
2942 buf = end;
2943 }
2944
2945 return n_words;
2946}
2947
b94dec87
DL		 2948enum intel_pipe_crc_object {
2949 PIPE_CRC_OBJECT_PIPE,
2950};
2951
e8dfcf78 2952static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2953 "pipe",
2954};
2955
2956static int
bd9db02f 2957display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2958{
2959 int i;
2960
2961 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2962 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2963 *o = i;
b94dec87
DL		 2964 return 0;
2965 }
2966
2967 return -EINVAL;
2968}
2969
bd9db02f 2970static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2971{
2972 const char name = buf[0];
2973
2974 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2975 return -EINVAL;
2976
2977 *pipe = name - 'A';
2978
2979 return 0;
2980}
2981
2982static int
bd9db02f 2983display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 2984{
2985 int i;
2986
2987 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2988 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 2989 *s = i;
926321d5
DV		 2990 return 0;
2991 }
2992
2993 return -EINVAL;
2994}
2995
bd9db02f 2996static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 2997{
b94dec87 2998#define N_WORDS 3
926321d5 2999 int n_words;
b94dec87 3000 char *words[N_WORDS];
926321d5 3001 enum pipe pipe;
b94dec87 3002 enum intel_pipe_crc_object object;
926321d5
DV		 3003 enum intel_pipe_crc_source source;
3004
bd9db02f 3005 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3006 if (n_words != N_WORDS) {
3007 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3008 N_WORDS);
3009 return -EINVAL;
3010 }
3011
bd9db02f 3012 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3013 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3014 return -EINVAL;
3015 }
3016
bd9db02f 3017 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3018 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3019 return -EINVAL;
3020 }
3021
bd9db02f 3022 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3023 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3024 return -EINVAL;
3025 }
3026
3027 return pipe_crc_set_source(dev, pipe, source);
3028}
3029
bd9db02f
DL		 3030static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3031 size_t len, loff_t *offp)
926321d5
DV		 3032{
3033 struct seq_file *m = file->private_data;
3034 struct drm_device *dev = m->private;
3035 char *tmpbuf;
3036 int ret;
3037
3038 if (len == 0)
3039 return 0;
3040
3041 if (len > PAGE_SIZE - 1) {
3042 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3043 PAGE_SIZE);
3044 return -E2BIG;
3045 }
3046
3047 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3048 if (!tmpbuf)
3049 return -ENOMEM;
3050
3051 if (copy_from_user(tmpbuf, ubuf, len)) {
3052 ret = -EFAULT;
3053 goto out;
3054 }
3055 tmpbuf[len] = '\0';
3056
bd9db02f 3057 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3058
3059out:
3060 kfree(tmpbuf);
3061 if (ret < 0)
3062 return ret;
3063
3064 *offp += len;
3065 return len;
3066}
3067
bd9db02f 3068static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3069 .owner = THIS_MODULE,
bd9db02f 3070 .open = display_crc_ctl_open,
926321d5
DV		 3071 .read = seq_read,
3072 .llseek = seq_lseek,
3073 .release = single_release,
bd9db02f 3074 .write = display_crc_ctl_write
926321d5
DV		 3075};
3076
369a1342
VS		 3077static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3078{
3079 struct drm_device *dev = m->private;
3080 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3081 int level;
3082
3083 drm_modeset_lock_all(dev);
3084
3085 for (level = 0; level < num_levels; level++) {
3086 unsigned int latency = wm[level];
3087
3088 /* WM1+ latency values in 0.5us units */
3089 if (level > 0)
3090 latency *= 5;
3091
3092 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3093 level, wm[level],
3094 latency / 10, latency % 10);
3095 }
3096
3097 drm_modeset_unlock_all(dev);
3098}
3099
3100static int pri_wm_latency_show(struct seq_file *m, void *data)
3101{
3102 struct drm_device *dev = m->private;
3103
3104 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3105
3106 return 0;
3107}
3108
3109static int spr_wm_latency_show(struct seq_file *m, void *data)
3110{
3111 struct drm_device *dev = m->private;
3112
3113 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3114
3115 return 0;
3116}
3117
3118static int cur_wm_latency_show(struct seq_file *m, void *data)
3119{
3120 struct drm_device *dev = m->private;
3121
3122 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3123
3124 return 0;
3125}
3126
3127static int pri_wm_latency_open(struct inode *inode, struct file *file)
3128{
3129 struct drm_device *dev = inode->i_private;
3130
3131 if (!HAS_PCH_SPLIT(dev))
3132 return -ENODEV;
3133
3134 return single_open(file, pri_wm_latency_show, dev);
3135}
3136
3137static int spr_wm_latency_open(struct inode *inode, struct file *file)
3138{
3139 struct drm_device *dev = inode->i_private;
3140
3141 if (!HAS_PCH_SPLIT(dev))
3142 return -ENODEV;
3143
3144 return single_open(file, spr_wm_latency_show, dev);
3145}
3146
3147static int cur_wm_latency_open(struct inode *inode, struct file *file)
3148{
3149 struct drm_device *dev = inode->i_private;
3150
3151 if (!HAS_PCH_SPLIT(dev))
3152 return -ENODEV;
3153
3154 return single_open(file, cur_wm_latency_show, dev);
3155}
3156
3157static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3158 size_t len, loff_t *offp, uint16_t wm[5])
3159{
3160 struct seq_file *m = file->private_data;
3161 struct drm_device *dev = m->private;
3162 uint16_t new[5] = { 0 };
3163 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3164 int level;
3165 int ret;
3166 char tmp[32];
3167
3168 if (len >= sizeof(tmp))
3169 return -EINVAL;
3170
3171 if (copy_from_user(tmp, ubuf, len))
3172 return -EFAULT;
3173
3174 tmp[len] = '\0';
3175
3176 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3177 if (ret != num_levels)
3178 return -EINVAL;
3179
3180 drm_modeset_lock_all(dev);
3181
3182 for (level = 0; level < num_levels; level++)
3183 wm[level] = new[level];
3184
3185 drm_modeset_unlock_all(dev);
3186
3187 return len;
3188}
3189
3190
3191static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3192 size_t len, loff_t *offp)
3193{
3194 struct seq_file *m = file->private_data;
3195 struct drm_device *dev = m->private;
3196
3197 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3198}
3199
3200static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3201 size_t len, loff_t *offp)
3202{
3203 struct seq_file *m = file->private_data;
3204 struct drm_device *dev = m->private;
3205
3206 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3207}
3208
3209static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3210 size_t len, loff_t *offp)
3211{
3212 struct seq_file *m = file->private_data;
3213 struct drm_device *dev = m->private;
3214
3215 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3216}
3217
3218static const struct file_operations i915_pri_wm_latency_fops = {
3219 .owner = THIS_MODULE,
3220 .open = pri_wm_latency_open,
3221 .read = seq_read,
3222 .llseek = seq_lseek,
3223 .release = single_release,
3224 .write = pri_wm_latency_write
3225};
3226
3227static const struct file_operations i915_spr_wm_latency_fops = {
3228 .owner = THIS_MODULE,
3229 .open = spr_wm_latency_open,
3230 .read = seq_read,
3231 .llseek = seq_lseek,
3232 .release = single_release,
3233 .write = spr_wm_latency_write
3234};
3235
3236static const struct file_operations i915_cur_wm_latency_fops = {
3237 .owner = THIS_MODULE,
3238 .open = cur_wm_latency_open,
3239 .read = seq_read,
3240 .llseek = seq_lseek,
3241 .release = single_release,
3242 .write = cur_wm_latency_write
3243};
3244
647416f9
KC		 3245static int
3246i915_wedged_get(void *data, u64 *val)
f3cd474b 3247{
647416f9 3248 struct drm_device *dev = data;
e277a1f8 3249 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3250
647416f9 3251 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3252
647416f9 3253 return 0;
f3cd474b
CW		 3254}
3255
647416f9
KC		 3256static int
3257i915_wedged_set(void *data, u64 val)
f3cd474b 3258{
647416f9 3259 struct drm_device *dev = data;
f3cd474b 3260
58174462
MK		 3261 i915_handle_error(dev, val,
3262 "Manually setting wedged to %llu", val);
647416f9 3263 return 0;
f3cd474b
CW		 3264}
3265
647416f9
KC		 3266DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3267 i915_wedged_get, i915_wedged_set,
3a3b4f98 3268 "%llu\n");
f3cd474b 3269
647416f9
KC		 3270static int
3271i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3272{
647416f9 3273 struct drm_device *dev = data;
e277a1f8 3274 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3275
647416f9 3276 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3277
647416f9 3278 return 0;
e5eb3d63
DV		 3279}
3280
647416f9
KC		 3281static int
3282i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3283{
647416f9 3284 struct drm_device *dev = data;
e5eb3d63 3285 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3286 int ret;
e5eb3d63 3287
647416f9 3288 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3289
22bcfc6a
DV		 3290 ret = mutex_lock_interruptible(&dev->struct_mutex);
3291 if (ret)
3292 return ret;
3293
99584db3 3294 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3295 mutex_unlock(&dev->struct_mutex);
3296
647416f9 3297 return 0;
e5eb3d63
DV		 3298}
3299
647416f9
KC		 3300DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3301 i915_ring_stop_get, i915_ring_stop_set,
3302 "0x%08llx\n");
d5442303 3303
094f9a54
CW		 3304static int
3305i915_ring_missed_irq_get(void *data, u64 *val)
3306{
3307 struct drm_device *dev = data;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309
3310 *val = dev_priv->gpu_error.missed_irq_rings;
3311 return 0;
3312}
3313
3314static int
3315i915_ring_missed_irq_set(void *data, u64 val)
3316{
3317 struct drm_device *dev = data;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 int ret;
3320
3321 /* Lock against concurrent debugfs callers */
3322 ret = mutex_lock_interruptible(&dev->struct_mutex);
3323 if (ret)
3324 return ret;
3325 dev_priv->gpu_error.missed_irq_rings = val;
3326 mutex_unlock(&dev->struct_mutex);
3327
3328 return 0;
3329}
3330
3331DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3332 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3333 "0x%08llx\n");
3334
3335static int
3336i915_ring_test_irq_get(void *data, u64 *val)
3337{
3338 struct drm_device *dev = data;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340
3341 *val = dev_priv->gpu_error.test_irq_rings;
3342
3343 return 0;
3344}
3345
3346static int
3347i915_ring_test_irq_set(void *data, u64 val)
3348{
3349 struct drm_device *dev = data;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 int ret;
3352
3353 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3354
3355 /* Lock against concurrent debugfs callers */
3356 ret = mutex_lock_interruptible(&dev->struct_mutex);
3357 if (ret)
3358 return ret;
3359
3360 dev_priv->gpu_error.test_irq_rings = val;
3361 mutex_unlock(&dev->struct_mutex);
3362
3363 return 0;
3364}
3365
3366DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3367 i915_ring_test_irq_get, i915_ring_test_irq_set,
3368 "0x%08llx\n");
3369
dd624afd
CW		 3370#define DROP_UNBOUND 0x1
3371#define DROP_BOUND 0x2
3372#define DROP_RETIRE 0x4
3373#define DROP_ACTIVE 0x8
3374#define DROP_ALL (DROP_UNBOUND | \
3375 DROP_BOUND | \
3376 DROP_RETIRE | \
3377 DROP_ACTIVE)
647416f9
KC		 3378static int
3379i915_drop_caches_get(void *data, u64 *val)
dd624afd 3380{
647416f9 3381 *val = DROP_ALL;
dd624afd 3382
647416f9 3383 return 0;
dd624afd
CW		 3384}
3385
647416f9
KC		 3386static int
3387i915_drop_caches_set(void *data, u64 val)
dd624afd 3388{
647416f9 3389 struct drm_device *dev = data;
dd624afd
CW		 3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 3392 struct i915_address_space *vm;
3393 struct i915_vma *vma, *x;
647416f9 3394 int ret;
dd624afd 3395
2f9fe5ff 3396 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3397
3398 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3399 * on ioctls on -EAGAIN. */
3400 ret = mutex_lock_interruptible(&dev->struct_mutex);
3401 if (ret)
3402 return ret;
3403
3404 if (val & DROP_ACTIVE) {
3405 ret = i915_gpu_idle(dev);
3406 if (ret)
3407 goto unlock;
3408 }
3409
3410 if (val & (DROP_RETIRE | DROP_ACTIVE))
3411 i915_gem_retire_requests(dev);
3412
3413 if (val & DROP_BOUND) {
ca191b13
BW		 3414 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3415 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3416 mm_list) {
d7f46fc4 3417 if (vma->pin_count)
ca191b13
BW		 3418 continue;
3419
3420 ret = i915_vma_unbind(vma);
3421 if (ret)
3422 goto unlock;
3423 }
31a46c9c 3424 }
dd624afd
CW		 3425 }
3426
3427 if (val & DROP_UNBOUND) {
35c20a60
BW		 3428 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3429 global_list)
dd624afd
CW		 3430 if (obj->pages_pin_count == 0) {
3431 ret = i915_gem_object_put_pages(obj);
3432 if (ret)
3433 goto unlock;
3434 }
3435 }
3436
3437unlock:
3438 mutex_unlock(&dev->struct_mutex);
3439
647416f9 3440 return ret;
dd624afd
CW		 3441}
3442
647416f9
KC		 3443DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3444 i915_drop_caches_get, i915_drop_caches_set,
3445 "0x%08llx\n");
dd624afd 3446
647416f9
KC		 3447static int
3448i915_max_freq_get(void *data, u64 *val)
358733e9 3449{
647416f9 3450 struct drm_device *dev = data;
e277a1f8 3451 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3452 int ret;
004777cb
DV		 3453
3454 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3455 return -ENODEV;
3456
5c9669ce
TR		 3457 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3458
4fc688ce 3459 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3460 if (ret)
3461 return ret;
358733e9 3462
0a073b84 3463 if (IS_VALLEYVIEW(dev))
b39fb297 3464 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 3465 else
b39fb297 3466 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3467 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3468
647416f9 3469 return 0;
358733e9
JB		 3470}
3471
647416f9
KC		 3472static int
3473i915_max_freq_set(void *data, u64 val)
358733e9 3474{
647416f9 3475 struct drm_device *dev = data;
358733e9 3476 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3477 u32 rp_state_cap, hw_max, hw_min;
647416f9 3478 int ret;
004777cb
DV		 3479
3480 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3481 return -ENODEV;
358733e9 3482
5c9669ce
TR		 3483 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3484
647416f9 3485 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3486
4fc688ce 3487 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3488 if (ret)
3489 return ret;
3490
358733e9
JB		 3491 /*
3492 * Turbo will still be enabled, but won't go above the set value.
3493 */
0a073b84 3494 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3495 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3496
3497 hw_max = valleyview_rps_max_freq(dev_priv);
3498 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3499 } else {
3500 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3501
3502 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3503 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3504 hw_min = (rp_state_cap >> 16) & 0xff;
3505 }
3506
b39fb297 3507 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 3508 mutex_unlock(&dev_priv->rps.hw_lock);
3509 return -EINVAL;
0a073b84
JB		 3510 }
3511
b39fb297 3512 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 3513
3514 if (IS_VALLEYVIEW(dev))
3515 valleyview_set_rps(dev, val);
3516 else
3517 gen6_set_rps(dev, val);
3518
4fc688ce 3519 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3520
647416f9 3521 return 0;
358733e9
JB		 3522}
3523
647416f9
KC		 3524DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3525 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3526 "%llu\n");
358733e9 3527
647416f9
KC		 3528static int
3529i915_min_freq_get(void *data, u64 *val)
1523c310 3530{
647416f9 3531 struct drm_device *dev = data;
e277a1f8 3532 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3533 int ret;
004777cb
DV		 3534
3535 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3536 return -ENODEV;
3537
5c9669ce
TR		 3538 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3539
4fc688ce 3540 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3541 if (ret)
3542 return ret;
1523c310 3543
0a073b84 3544 if (IS_VALLEYVIEW(dev))
b39fb297 3545 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 3546 else
b39fb297 3547 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3548 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3549
647416f9 3550 return 0;
1523c310
JB		 3551}
3552
647416f9
KC		 3553static int
3554i915_min_freq_set(void *data, u64 val)
1523c310 3555{
647416f9 3556 struct drm_device *dev = data;
1523c310 3557 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3558 u32 rp_state_cap, hw_max, hw_min;
647416f9 3559 int ret;
004777cb
DV		 3560
3561 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3562 return -ENODEV;
1523c310 3563
5c9669ce
TR		 3564 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3565
647416f9 3566 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3567
4fc688ce 3568 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3569 if (ret)
3570 return ret;
3571
1523c310
JB		 3572 /*
3573 * Turbo will still be enabled, but won't go below the set value.
3574 */
0a073b84 3575 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3576 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3577
3578 hw_max = valleyview_rps_max_freq(dev_priv);
3579 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3580 } else {
3581 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3582
3583 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3584 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3585 hw_min = (rp_state_cap >> 16) & 0xff;
3586 }
3587
b39fb297 3588 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 3589 mutex_unlock(&dev_priv->rps.hw_lock);
3590 return -EINVAL;
0a073b84 3591 }
dd0a1aa1 3592
b39fb297 3593 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 3594
3595 if (IS_VALLEYVIEW(dev))
3596 valleyview_set_rps(dev, val);
3597 else
3598 gen6_set_rps(dev, val);
3599
4fc688ce 3600 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3601
647416f9 3602 return 0;
1523c310
JB		 3603}
3604
647416f9
KC		 3605DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3606 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3607 "%llu\n");
1523c310 3608
647416f9
KC		 3609static int
3610i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3611{
647416f9 3612 struct drm_device *dev = data;
e277a1f8 3613 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3614 u32 snpcr;
647416f9 3615 int ret;
07b7ddd9 3616
004777cb
DV		 3617 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3618 return -ENODEV;
3619
22bcfc6a
DV		 3620 ret = mutex_lock_interruptible(&dev->struct_mutex);
3621 if (ret)
3622 return ret;
c8c8fb33 3623 intel_runtime_pm_get(dev_priv);
22bcfc6a 3624
07b7ddd9 3625 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 3626
3627 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 3628 mutex_unlock(&dev_priv->dev->struct_mutex);
3629
647416f9 3630 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3631
647416f9 3632 return 0;
07b7ddd9
JB		 3633}
3634
647416f9
KC		 3635static int
3636i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3637{
647416f9 3638 struct drm_device *dev = data;
07b7ddd9 3639 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3640 u32 snpcr;
07b7ddd9 3641
004777cb
DV		 3642 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3643 return -ENODEV;
3644
647416f9 3645 if (val > 3)
07b7ddd9
JB		 3646 return -EINVAL;
3647
c8c8fb33 3648 intel_runtime_pm_get(dev_priv);
647416f9 3649 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3650
3651 /* Update the cache sharing policy here as well */
3652 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3653 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3654 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3655 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3656
c8c8fb33 3657 intel_runtime_pm_put(dev_priv);
647416f9 3658 return 0;
07b7ddd9
JB		 3659}
3660
647416f9
KC		 3661DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3662 i915_cache_sharing_get, i915_cache_sharing_set,
3663 "%llu\n");
07b7ddd9 3664
6d794d42
BW		 3665static int i915_forcewake_open(struct inode *inode, struct file *file)
3666{
3667 struct drm_device *dev = inode->i_private;
3668 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3669
075edca4 3670 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3671 return 0;
3672
c8d9a590 3673 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3674
3675 return 0;
3676}
3677
c43b5634 3678static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3679{
3680 struct drm_device *dev = inode->i_private;
3681 struct drm_i915_private *dev_priv = dev->dev_private;
3682
075edca4 3683 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3684 return 0;
3685
c8d9a590 3686 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3687
3688 return 0;
3689}
3690
3691static const struct file_operations i915_forcewake_fops = {
3692 .owner = THIS_MODULE,
3693 .open = i915_forcewake_open,
3694 .release = i915_forcewake_release,
3695};
3696
3697static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3698{
3699 struct drm_device *dev = minor->dev;
3700 struct dentry *ent;
3701
3702 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3703 S_IRUSR,
6d794d42
BW		 3704 root, dev,
3705 &i915_forcewake_fops);
f3c5fe97
WY		 3706 if (!ent)
3707 return -ENOMEM;
6d794d42 3708
8eb57294 3709 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3710}
3711
6a9c308d
DV		 3712static int i915_debugfs_create(struct dentry *root,
3713 struct drm_minor *minor,
3714 const char *name,
3715 const struct file_operations *fops)
07b7ddd9
JB		 3716{
3717 struct drm_device *dev = minor->dev;
3718 struct dentry *ent;
3719
6a9c308d 3720 ent = debugfs_create_file(name,
07b7ddd9
JB		 3721 S_IRUGO | S_IWUSR,
3722 root, dev,
6a9c308d 3723 fops);
f3c5fe97
WY		 3724 if (!ent)
3725 return -ENOMEM;
07b7ddd9 3726
6a9c308d 3727 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3728}
3729
06c5bf8c 3730static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3731 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3732 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3733 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3734 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3735 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3736 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3737 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3738 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3739 {"i915_gem_request", i915_gem_request_info, 0},
3740 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3741 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3742 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3743 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3744 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3745 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3746 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1 3747 {"i915_rstdby_delays", i915_rstdby_delays, 0},
adb4bd12 3748 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1
JB		 3749 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3750 {"i915_inttoext_table", i915_inttoext_table, 0},
3751 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3752 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3753 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 3754 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 3755 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3756 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3757 {"i915_sr_status", i915_sr_status, 0},
44834a67 3758 {"i915_opregion", i915_opregion, 0},
37811fcc 3759 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3760 {"i915_context_status", i915_context_status, 0},
6d794d42 3761 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3762 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3763 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 3764 {"i915_llc", i915_llc, 0},
e91fd8c6 3765 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 3766 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 3767 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3768 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3769 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 3770 {"i915_display_info", i915_display_info, 0},
2017263e 3771};
27c202ad 3772#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3773
06c5bf8c 3774static const struct i915_debugfs_files {
34b9674c
DV		 3775 const char *name;
3776 const struct file_operations *fops;
3777} i915_debugfs_files[] = {
3778 {"i915_wedged", &i915_wedged_fops},
3779 {"i915_max_freq", &i915_max_freq_fops},
3780 {"i915_min_freq", &i915_min_freq_fops},
3781 {"i915_cache_sharing", &i915_cache_sharing_fops},
3782 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3783 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3784 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3785 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3786 {"i915_error_state", &i915_error_state_fops},
3787 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3788 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 3789 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3790 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3791 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
34b9674c
DV		 3792};
3793
07144428
DL		 3794void intel_display_crc_init(struct drm_device *dev)
3795{
3796 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3797 enum pipe pipe;
07144428 3798
b378360e
DV		 3799 for_each_pipe(pipe) {
3800 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3801
d538bbdf
DL		 3802 pipe_crc->opened = false;
3803 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3804 init_waitqueue_head(&pipe_crc->wq);
3805 }
3806}
3807
27c202ad 3808int i915_debugfs_init(struct drm_minor *minor)
2017263e 3809{
34b9674c 3810 int ret, i;
f3cd474b 3811
6d794d42 3812 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3813 if (ret)
3814 return ret;
6a9c308d 3815
07144428
DL		 3816 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3817 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3818 if (ret)
3819 return ret;
3820 }
3821
34b9674c
DV		 3822 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3823 ret = i915_debugfs_create(minor->debugfs_root, minor,
3824 i915_debugfs_files[i].name,
3825 i915_debugfs_files[i].fops);
3826 if (ret)
3827 return ret;
3828 }
40633219 3829
27c202ad
BG		 3830 return drm_debugfs_create_files(i915_debugfs_list,
3831 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3832 minor->debugfs_root, minor);
3833}
3834
27c202ad 3835void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3836{
34b9674c
DV		 3837 int i;
3838
27c202ad
BG		 3839 drm_debugfs_remove_files(i915_debugfs_list,
3840 I915_DEBUGFS_ENTRIES, minor);
07144428 3841
6d794d42
BW		 3842 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3843 1, minor);
07144428 3844
e309a997 3845 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3846 struct drm_info_list *info_list =
3847 (struct drm_info_list *)&i915_pipe_crc_data[i];
3848
3849 drm_debugfs_remove_files(info_list, 1, minor);
3850 }
3851
34b9674c
DV		 3852 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3853 struct drm_info_list *info_list =
3854 (struct drm_info_list *) i915_debugfs_files[i].fops;
3855
3856 drm_debugfs_remove_files(info_list, 1, minor);
3857 }
2017263e 3858}
Linux 6.x block layer and io_uring tree(s)