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drm/i915: GuC-specific firmware loader
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
baaa5cfb 99 if (obj->pin_display)
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
ca1543be
TU		 120static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
121{
122 u64 size = 0;
123 struct i915_vma *vma;
124
125 list_for_each_entry(vma, &obj->vma_list, vma_link) {
126 if (i915_is_ggtt(vma->vm) &&
127 drm_mm_node_allocated(&vma->node))
128 size += vma->node.size;
129 }
130
131 return size;
132}
133
37811fcc
CW		 134static void
135describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
136{
b4716185
CW		 137 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
138 struct intel_engine_cs *ring;
1d693bcc 139 struct i915_vma *vma;
d7f46fc4 140 int pin_count = 0;
b4716185 141 int i;
d7f46fc4 142
b4716185 143 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 144 &obj->base,
481a3d43 145 obj->active ? "*" : " ",
37811fcc
CW		 146 get_pin_flag(obj),
147 get_tiling_flag(obj),
1d693bcc 148 get_global_flag(obj),
a05a5862 149 obj->base.size / 1024,
37811fcc 150 obj->base.read_domains,
b4716185
CW		 151 obj->base.write_domain);
152 for_each_ring(ring, dev_priv, i)
153 seq_printf(m, "%x ",
154 i915_gem_request_get_seqno(obj->last_read_req[i]));
155 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 156 i915_gem_request_get_seqno(obj->last_write_req),
157 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 158 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 159 obj->dirty ? " dirty" : "",
160 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
161 if (obj->base.name)
162 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 163 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 164 if (vma->pin_count > 0)
165 pin_count++;
ba0635ff
DC		 166 }
167 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 168 if (obj->pin_display)
169 seq_printf(m, " (display)");
37811fcc
CW		 170 if (obj->fence_reg != I915_FENCE_REG_NONE)
171 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc 172 list_for_each_entry(vma, &obj->vma_list, vma_link) {
8d2fdc3f
TU		 173 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
174 i915_is_ggtt(vma->vm) ? "g" : "pp",
175 vma->node.start, vma->node.size);
176 if (i915_is_ggtt(vma->vm))
177 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
1d693bcc 178 else
8d2fdc3f 179 seq_puts(m, ")");
1d693bcc 180 }
c1ad11fc 181 if (obj->stolen)
440fd528 182 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 183 if (obj->pin_display || obj->fault_mappable) {
6299f992 184 char s[3], *t = s;
30154650 185 if (obj->pin_display)
6299f992
CW		 186 *t++ = 'p';
187 if (obj->fault_mappable)
188 *t++ = 'f';
189 *t = '\0';
190 seq_printf(m, " (%s mappable)", s);
191 }
b4716185 192 if (obj->last_write_req != NULL)
41c52415 193 seq_printf(m, " (%s)",
b4716185 194 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 195 if (obj->frontbuffer_bits)
196 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 197}
198
273497e5 199static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 200{
ea0c76f8 201 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 202 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
203 seq_putc(m, ' ');
204}
205
433e12f7 206static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 207{
9f25d007 208 struct drm_info_node *node = m->private;
433e12f7
BG		 209 uintptr_t list = (uintptr_t) node->info_ent->data;
210 struct list_head *head;
2017263e 211 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 212 struct drm_i915_private *dev_priv = dev->dev_private;
213 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 214 struct i915_vma *vma;
c44ef60e 215 u64 total_obj_size, total_gtt_size;
8f2480fb 216 int count, ret;
de227ef0
CW		 217
218 ret = mutex_lock_interruptible(&dev->struct_mutex);
219 if (ret)
220 return ret;
2017263e 221
ca191b13 222 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 223 switch (list) {
224 case ACTIVE_LIST:
267f0c90 225 seq_puts(m, "Active:\n");
5cef07e1 226 head = &vm->active_list;
433e12f7
BG		 227 break;
228 case INACTIVE_LIST:
267f0c90 229 seq_puts(m, "Inactive:\n");
5cef07e1 230 head = &vm->inactive_list;
433e12f7 231 break;
433e12f7 232 default:
de227ef0
CW		 233 mutex_unlock(&dev->struct_mutex);
234 return -EINVAL;
2017263e 235 }
2017263e 236
8f2480fb 237 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 238 list_for_each_entry(vma, head, mm_list) {
239 seq_printf(m, " ");
240 describe_obj(m, vma->obj);
241 seq_printf(m, "\n");
242 total_obj_size += vma->obj->base.size;
243 total_gtt_size += vma->node.size;
8f2480fb 244 count++;
2017263e 245 }
de227ef0 246 mutex_unlock(&dev->struct_mutex);
5e118f41 247
c44ef60e 248 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 249 count, total_obj_size, total_gtt_size);
2017263e
BG		 250 return 0;
251}
252
6d2b8885
CW		 253static int obj_rank_by_stolen(void *priv,
254 struct list_head *A, struct list_head *B)
255{
256 struct drm_i915_gem_object *a =
b25cb2f8 257 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 258 struct drm_i915_gem_object *b =
b25cb2f8 259 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 260
261 return a->stolen->start - b->stolen->start;
262}
263
264static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
265{
9f25d007 266 struct drm_info_node *node = m->private;
6d2b8885
CW		 267 struct drm_device *dev = node->minor->dev;
268 struct drm_i915_private *dev_priv = dev->dev_private;
269 struct drm_i915_gem_object *obj;
c44ef60e 270 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 271 LIST_HEAD(stolen);
272 int count, ret;
273
274 ret = mutex_lock_interruptible(&dev->struct_mutex);
275 if (ret)
276 return ret;
277
278 total_obj_size = total_gtt_size = count = 0;
279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
280 if (obj->stolen == NULL)
281 continue;
282
b25cb2f8 283 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 284
285 total_obj_size += obj->base.size;
ca1543be 286 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 287 count++;
288 }
289 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
290 if (obj->stolen == NULL)
291 continue;
292
b25cb2f8 293 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 294
295 total_obj_size += obj->base.size;
296 count++;
297 }
298 list_sort(NULL, &stolen, obj_rank_by_stolen);
299 seq_puts(m, "Stolen:\n");
300 while (!list_empty(&stolen)) {
b25cb2f8 301 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 302 seq_puts(m, " ");
303 describe_obj(m, obj);
304 seq_putc(m, '\n');
b25cb2f8 305 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 306 }
307 mutex_unlock(&dev->struct_mutex);
308
c44ef60e 309 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 310 count, total_obj_size, total_gtt_size);
311 return 0;
312}
313
6299f992
CW		 314#define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
ca1543be 316 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 317 ++count; \
318 if (obj->map_and_fenceable) { \
f343c5f6 319 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 320 ++mappable_count; \
321 } \
322 } \
0206e353 323} while (0)
6299f992 324
2db8e9d6 325struct file_stats {
6313c204 326 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 327 unsigned long count;
328 u64 total, unbound;
329 u64 global, shared;
330 u64 active, inactive;
2db8e9d6
CW		 331};
332
333static int per_file_stats(int id, void *ptr, void *data)
334{
335 struct drm_i915_gem_object *obj = ptr;
336 struct file_stats *stats = data;
6313c204 337 struct i915_vma *vma;
2db8e9d6
CW		 338
339 stats->count++;
340 stats->total += obj->base.size;
341
c67a17e9
CW		 342 if (obj->base.name || obj->base.dma_buf)
343 stats->shared += obj->base.size;
344
6313c204
CW		 345 if (USES_FULL_PPGTT(obj->base.dev)) {
346 list_for_each_entry(vma, &obj->vma_list, vma_link) {
347 struct i915_hw_ppgtt *ppgtt;
348
349 if (!drm_mm_node_allocated(&vma->node))
350 continue;
351
352 if (i915_is_ggtt(vma->vm)) {
353 stats->global += obj->base.size;
354 continue;
355 }
356
357 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 358 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 359 continue;
360
41c52415 361 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 362 stats->active += obj->base.size;
363 else
364 stats->inactive += obj->base.size;
365
366 return 0;
367 }
2db8e9d6 368 } else {
6313c204
CW		 369 if (i915_gem_obj_ggtt_bound(obj)) {
370 stats->global += obj->base.size;
41c52415 371 if (obj->active)
6313c204
CW		 372 stats->active += obj->base.size;
373 else
374 stats->inactive += obj->base.size;
375 return 0;
376 }
2db8e9d6
CW		 377 }
378
6313c204
CW		 379 if (!list_empty(&obj->global_list))
380 stats->unbound += obj->base.size;
381
2db8e9d6
CW		 382 return 0;
383}
384
b0da1b79
CW		 385#define print_file_stats(m, name, stats) do { \
386 if (stats.count) \
c44ef60e 387 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 388 name, \
389 stats.count, \
390 stats.total, \
391 stats.active, \
392 stats.inactive, \
393 stats.global, \
394 stats.shared, \
395 stats.unbound); \
396} while (0)
493018dc
BV		 397
398static void print_batch_pool_stats(struct seq_file *m,
399 struct drm_i915_private *dev_priv)
400{
401 struct drm_i915_gem_object *obj;
402 struct file_stats stats;
06fbca71 403 struct intel_engine_cs *ring;
8d9d5744 404 int i, j;
493018dc
BV		 405
406 memset(&stats, 0, sizeof(stats));
407
06fbca71 408 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 409 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
410 list_for_each_entry(obj,
411 &ring->batch_pool.cache_list[j],
412 batch_pool_link)
413 per_file_stats(0, obj, &stats);
414 }
06fbca71 415 }
493018dc 416
b0da1b79 417 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 418}
419
ca191b13
BW		 420#define count_vmas(list, member) do { \
421 list_for_each_entry(vma, list, member) { \
ca1543be 422 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 423 ++count; \
424 if (vma->obj->map_and_fenceable) { \
425 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
426 ++mappable_count; \
427 } \
428 } \
429} while (0)
430
431static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 432{
9f25d007 433 struct drm_info_node *node = m->private;
73aa808f
CW		 434 struct drm_device *dev = node->minor->dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714 436 u32 count, mappable_count, purgeable_count;
c44ef60e 437 u64 size, mappable_size, purgeable_size;
6299f992 438 struct drm_i915_gem_object *obj;
5cef07e1 439 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 440 struct drm_file *file;
ca191b13 441 struct i915_vma *vma;
73aa808f
CW		 442 int ret;
443
444 ret = mutex_lock_interruptible(&dev->struct_mutex);
445 if (ret)
446 return ret;
447
6299f992
CW		 448 seq_printf(m, "%u objects, %zu bytes\n",
449 dev_priv->mm.object_count,
450 dev_priv->mm.object_memory);
451
452 size = count = mappable_size = mappable_count = 0;
35c20a60 453 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 454 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 455 count, mappable_count, size, mappable_size);
456
457 size = count = mappable_size = mappable_count = 0;
ca191b13 458 count_vmas(&vm->active_list, mm_list);
c44ef60e 459 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 460 count, mappable_count, size, mappable_size);
461
6299f992 462 size = count = mappable_size = mappable_count = 0;
ca191b13 463 count_vmas(&vm->inactive_list, mm_list);
c44ef60e 464 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 465 count, mappable_count, size, mappable_size);
466
b7abb714 467 size = count = purgeable_size = purgeable_count = 0;
35c20a60 468 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 469 size += obj->base.size, ++count;
b7abb714
CW		 470 if (obj->madv == I915_MADV_DONTNEED)
471 purgeable_size += obj->base.size, ++purgeable_count;
472 }
c44ef60e 473 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 474
6299f992 475 size = count = mappable_size = mappable_count = 0;
35c20a60 476 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 477 if (obj->fault_mappable) {
f343c5f6 478 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 479 ++count;
480 }
30154650 481 if (obj->pin_display) {
f343c5f6 482 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 483 ++mappable_count;
484 }
b7abb714
CW		 485 if (obj->madv == I915_MADV_DONTNEED) {
486 purgeable_size += obj->base.size;
487 ++purgeable_count;
488 }
6299f992 489 }
c44ef60e 490 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 491 purgeable_count, purgeable_size);
c44ef60e 492 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 493 mappable_count, mappable_size);
c44ef60e 494 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 495 count, size);
496
c44ef60e 497 seq_printf(m, "%llu [%llu] gtt total\n",
853ba5d2 498 dev_priv->gtt.base.total,
c44ef60e 499 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 500
493018dc
BV		 501 seq_putc(m, '\n');
502 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 503 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
504 struct file_stats stats;
3ec2f427 505 struct task_struct *task;
2db8e9d6
CW		 506
507 memset(&stats, 0, sizeof(stats));
6313c204 508 stats.file_priv = file->driver_priv;
5b5ffff0 509 spin_lock(&file->table_lock);
2db8e9d6 510 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 511 spin_unlock(&file->table_lock);
3ec2f427
TH		 512 /*
513 * Although we have a valid reference on file->pid, that does
514 * not guarantee that the task_struct who called get_pid() is
515 * still alive (e.g. get_pid(current) => fork() => exit()).
516 * Therefore, we need to protect this ->comm access using RCU.
517 */
518 rcu_read_lock();
519 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 520 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 521 rcu_read_unlock();
2db8e9d6
CW		 522 }
523
73aa808f
CW		 524 mutex_unlock(&dev->struct_mutex);
525
526 return 0;
527}
528
aee56cff 529static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 530{
9f25d007 531 struct drm_info_node *node = m->private;
08c18323 532 struct drm_device *dev = node->minor->dev;
1b50247a 533 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 534 struct drm_i915_private *dev_priv = dev->dev_private;
535 struct drm_i915_gem_object *obj;
c44ef60e 536 u64 total_obj_size, total_gtt_size;
08c18323
CW		 537 int count, ret;
538
539 ret = mutex_lock_interruptible(&dev->struct_mutex);
540 if (ret)
541 return ret;
542
543 total_obj_size = total_gtt_size = count = 0;
35c20a60 544 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 545 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 546 continue;
547
267f0c90 548 seq_puts(m, " ");
08c18323 549 describe_obj(m, obj);
267f0c90 550 seq_putc(m, '\n');
08c18323 551 total_obj_size += obj->base.size;
ca1543be 552 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 553 count++;
554 }
555
556 mutex_unlock(&dev->struct_mutex);
557
c44ef60e 558 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 559 count, total_obj_size, total_gtt_size);
560
561 return 0;
562}
563
4e5359cd
SF		 564static int i915_gem_pageflip_info(struct seq_file *m, void *data)
565{
9f25d007 566 struct drm_info_node *node = m->private;
4e5359cd 567 struct drm_device *dev = node->minor->dev;
d6bbafa1 568 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 569 struct intel_crtc *crtc;
8a270ebf
DV		 570 int ret;
571
572 ret = mutex_lock_interruptible(&dev->struct_mutex);
573 if (ret)
574 return ret;
4e5359cd 575
d3fcc808 576 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 577 const char pipe = pipe_name(crtc->pipe);
578 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 579 struct intel_unpin_work *work;
580
5e2d7afc 581 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 582 work = crtc->unpin_work;
583 if (work == NULL) {
9db4a9c7 584 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 585 pipe, plane);
586 } else {
d6bbafa1
CW		 587 u32 addr;
588
e7d841ca 589 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 590 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 591 pipe, plane);
592 } else {
9db4a9c7 593 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 594 pipe, plane);
595 }
3a8a946e
DV		 596 if (work->flip_queued_req) {
597 struct intel_engine_cs *ring =
598 i915_gem_request_get_ring(work->flip_queued_req);
599
20e28fba 600 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 601 ring->name,
f06cc1b9 602 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 603 dev_priv->next_seqno,
3a8a946e 604 ring->get_seqno(ring, true),
1b5a433a 605 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 606 } else
607 seq_printf(m, "Flip not associated with any ring\n");
608 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
609 work->flip_queued_vblank,
610 work->flip_ready_vblank,
1e3feefd 611 drm_crtc_vblank_count(&crtc->base));
4e5359cd 612 if (work->enable_stall_check)
267f0c90 613 seq_puts(m, "Stall check enabled, ");
4e5359cd 614 else
267f0c90 615 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 616 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 617
d6bbafa1
CW		 618 if (INTEL_INFO(dev)->gen >= 4)
619 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
620 else
621 addr = I915_READ(DSPADDR(crtc->plane));
622 seq_printf(m, "Current scanout address 0x%08x\n", addr);
623
4e5359cd 624 if (work->pending_flip_obj) {
d6bbafa1
CW		 625 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
626 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 627 }
628 }
5e2d7afc 629 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 630 }
631
8a270ebf
DV		 632 mutex_unlock(&dev->struct_mutex);
633
4e5359cd
SF		 634 return 0;
635}
636
493018dc
BV		 637static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
638{
639 struct drm_info_node *node = m->private;
640 struct drm_device *dev = node->minor->dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642 struct drm_i915_gem_object *obj;
06fbca71 643 struct intel_engine_cs *ring;
8d9d5744
CW		 644 int total = 0;
645 int ret, i, j;
493018dc
BV		 646
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 if (ret)
649 return ret;
650
06fbca71 651 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 652 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
653 int count;
654
655 count = 0;
656 list_for_each_entry(obj,
657 &ring->batch_pool.cache_list[j],
658 batch_pool_link)
659 count++;
660 seq_printf(m, "%s cache[%d]: %d objects\n",
661 ring->name, j, count);
662
663 list_for_each_entry(obj,
664 &ring->batch_pool.cache_list[j],
665 batch_pool_link) {
666 seq_puts(m, " ");
667 describe_obj(m, obj);
668 seq_putc(m, '\n');
669 }
670
671 total += count;
06fbca71 672 }
493018dc
BV		 673 }
674
8d9d5744 675 seq_printf(m, "total: %d\n", total);
493018dc
BV		 676
677 mutex_unlock(&dev->struct_mutex);
678
679 return 0;
680}
681
2017263e
BG		 682static int i915_gem_request_info(struct seq_file *m, void *data)
683{
9f25d007 684 struct drm_info_node *node = m->private;
2017263e 685 struct drm_device *dev = node->minor->dev;
e277a1f8 686 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 687 struct intel_engine_cs *ring;
eed29a5b 688 struct drm_i915_gem_request *req;
2d1070b2 689 int ret, any, i;
de227ef0
CW		 690
691 ret = mutex_lock_interruptible(&dev->struct_mutex);
692 if (ret)
693 return ret;
2017263e 694
2d1070b2 695 any = 0;
a2c7f6fd 696 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 697 int count;
698
699 count = 0;
eed29a5b 700 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 701 count++;
702 if (count == 0)
a2c7f6fd
CW		 703 continue;
704
2d1070b2 705 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 706 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 707 struct task_struct *task;
708
709 rcu_read_lock();
710 task = NULL;
eed29a5b
DV		 711 if (req->pid)
712 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 713 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 714 req->seqno,
715 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 716 task ? task->comm : "<unknown>",
717 task ? task->pid : -1);
718 rcu_read_unlock();
c2c347a9 719 }
2d1070b2
CW		 720
721 any++;
2017263e 722 }
de227ef0
CW		 723 mutex_unlock(&dev->struct_mutex);
724
2d1070b2 725 if (any == 0)
267f0c90 726 seq_puts(m, "No requests\n");
c2c347a9 727
2017263e
BG		 728 return 0;
729}
730
b2223497 731static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 732 struct intel_engine_cs *ring)
b2223497
CW		 733{
734 if (ring->get_seqno) {
20e28fba 735 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 736 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 737 }
738}
739
2017263e
BG		 740static int i915_gem_seqno_info(struct seq_file *m, void *data)
741{
9f25d007 742 struct drm_info_node *node = m->private;
2017263e 743 struct drm_device *dev = node->minor->dev;
e277a1f8 744 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 745 struct intel_engine_cs *ring;
1ec14ad3 746 int ret, i;
de227ef0
CW		 747
748 ret = mutex_lock_interruptible(&dev->struct_mutex);
749 if (ret)
750 return ret;
c8c8fb33 751 intel_runtime_pm_get(dev_priv);
2017263e 752
a2c7f6fd
CW		 753 for_each_ring(ring, dev_priv, i)
754 i915_ring_seqno_info(m, ring);
de227ef0 755
c8c8fb33 756 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 757 mutex_unlock(&dev->struct_mutex);
758
2017263e
BG		 759 return 0;
760}
761
762
763static int i915_interrupt_info(struct seq_file *m, void *data)
764{
9f25d007 765 struct drm_info_node *node = m->private;
2017263e 766 struct drm_device *dev = node->minor->dev;
e277a1f8 767 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 768 struct intel_engine_cs *ring;
9db4a9c7 769 int ret, i, pipe;
de227ef0
CW		 770
771 ret = mutex_lock_interruptible(&dev->struct_mutex);
772 if (ret)
773 return ret;
c8c8fb33 774 intel_runtime_pm_get(dev_priv);
2017263e 775
74e1ca8c 776 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 777 seq_printf(m, "Master Interrupt Control:\t%08x\n",
778 I915_READ(GEN8_MASTER_IRQ));
779
780 seq_printf(m, "Display IER:\t%08x\n",
781 I915_READ(VLV_IER));
782 seq_printf(m, "Display IIR:\t%08x\n",
783 I915_READ(VLV_IIR));
784 seq_printf(m, "Display IIR_RW:\t%08x\n",
785 I915_READ(VLV_IIR_RW));
786 seq_printf(m, "Display IMR:\t%08x\n",
787 I915_READ(VLV_IMR));
055e393f 788 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 789 seq_printf(m, "Pipe %c stat:\t%08x\n",
790 pipe_name(pipe),
791 I915_READ(PIPESTAT(pipe)));
792
793 seq_printf(m, "Port hotplug:\t%08x\n",
794 I915_READ(PORT_HOTPLUG_EN));
795 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
796 I915_READ(VLV_DPFLIPSTAT));
797 seq_printf(m, "DPINVGTT:\t%08x\n",
798 I915_READ(DPINVGTT));
799
800 for (i = 0; i < 4; i++) {
801 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
802 i, I915_READ(GEN8_GT_IMR(i)));
803 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
804 i, I915_READ(GEN8_GT_IIR(i)));
805 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
806 i, I915_READ(GEN8_GT_IER(i)));
807 }
808
809 seq_printf(m, "PCU interrupt mask:\t%08x\n",
810 I915_READ(GEN8_PCU_IMR));
811 seq_printf(m, "PCU interrupt identity:\t%08x\n",
812 I915_READ(GEN8_PCU_IIR));
813 seq_printf(m, "PCU interrupt enable:\t%08x\n",
814 I915_READ(GEN8_PCU_IER));
815 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 816 seq_printf(m, "Master Interrupt Control:\t%08x\n",
817 I915_READ(GEN8_MASTER_IRQ));
818
819 for (i = 0; i < 4; i++) {
820 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
821 i, I915_READ(GEN8_GT_IMR(i)));
822 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
823 i, I915_READ(GEN8_GT_IIR(i)));
824 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
825 i, I915_READ(GEN8_GT_IER(i)));
826 }
827
055e393f 828 for_each_pipe(dev_priv, pipe) {
f458ebbc 829 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 830 POWER_DOMAIN_PIPE(pipe))) {
831 seq_printf(m, "Pipe %c power disabled\n",
832 pipe_name(pipe));
833 continue;
834 }
a123f157 835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 836 pipe_name(pipe),
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 839 pipe_name(pipe),
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 841 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 842 pipe_name(pipe),
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 844 }
845
846 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
847 I915_READ(GEN8_DE_PORT_IMR));
848 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IIR));
850 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IER));
852
853 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
854 I915_READ(GEN8_DE_MISC_IMR));
855 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IIR));
857 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IER));
859
860 seq_printf(m, "PCU interrupt mask:\t%08x\n",
861 I915_READ(GEN8_PCU_IMR));
862 seq_printf(m, "PCU interrupt identity:\t%08x\n",
863 I915_READ(GEN8_PCU_IIR));
864 seq_printf(m, "PCU interrupt enable:\t%08x\n",
865 I915_READ(GEN8_PCU_IER));
866 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 867 seq_printf(m, "Display IER:\t%08x\n",
868 I915_READ(VLV_IER));
869 seq_printf(m, "Display IIR:\t%08x\n",
870 I915_READ(VLV_IIR));
871 seq_printf(m, "Display IIR_RW:\t%08x\n",
872 I915_READ(VLV_IIR_RW));
873 seq_printf(m, "Display IMR:\t%08x\n",
874 I915_READ(VLV_IMR));
055e393f 875 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 876 seq_printf(m, "Pipe %c stat:\t%08x\n",
877 pipe_name(pipe),
878 I915_READ(PIPESTAT(pipe)));
879
880 seq_printf(m, "Master IER:\t%08x\n",
881 I915_READ(VLV_MASTER_IER));
882
883 seq_printf(m, "Render IER:\t%08x\n",
884 I915_READ(GTIER));
885 seq_printf(m, "Render IIR:\t%08x\n",
886 I915_READ(GTIIR));
887 seq_printf(m, "Render IMR:\t%08x\n",
888 I915_READ(GTIMR));
889
890 seq_printf(m, "PM IER:\t\t%08x\n",
891 I915_READ(GEN6_PMIER));
892 seq_printf(m, "PM IIR:\t\t%08x\n",
893 I915_READ(GEN6_PMIIR));
894 seq_printf(m, "PM IMR:\t\t%08x\n",
895 I915_READ(GEN6_PMIMR));
896
897 seq_printf(m, "Port hotplug:\t%08x\n",
898 I915_READ(PORT_HOTPLUG_EN));
899 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
900 I915_READ(VLV_DPFLIPSTAT));
901 seq_printf(m, "DPINVGTT:\t%08x\n",
902 I915_READ(DPINVGTT));
903
904 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 905 seq_printf(m, "Interrupt enable: %08x\n",
906 I915_READ(IER));
907 seq_printf(m, "Interrupt identity: %08x\n",
908 I915_READ(IIR));
909 seq_printf(m, "Interrupt mask: %08x\n",
910 I915_READ(IMR));
055e393f 911 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 912 seq_printf(m, "Pipe %c stat: %08x\n",
913 pipe_name(pipe),
914 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 915 } else {
916 seq_printf(m, "North Display Interrupt enable: %08x\n",
917 I915_READ(DEIER));
918 seq_printf(m, "North Display Interrupt identity: %08x\n",
919 I915_READ(DEIIR));
920 seq_printf(m, "North Display Interrupt mask: %08x\n",
921 I915_READ(DEIMR));
922 seq_printf(m, "South Display Interrupt enable: %08x\n",
923 I915_READ(SDEIER));
924 seq_printf(m, "South Display Interrupt identity: %08x\n",
925 I915_READ(SDEIIR));
926 seq_printf(m, "South Display Interrupt mask: %08x\n",
927 I915_READ(SDEIMR));
928 seq_printf(m, "Graphics Interrupt enable: %08x\n",
929 I915_READ(GTIER));
930 seq_printf(m, "Graphics Interrupt identity: %08x\n",
931 I915_READ(GTIIR));
932 seq_printf(m, "Graphics Interrupt mask: %08x\n",
933 I915_READ(GTIMR));
934 }
a2c7f6fd 935 for_each_ring(ring, dev_priv, i) {
a123f157 936 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 937 seq_printf(m,
938 "Graphics Interrupt mask (%s): %08x\n",
939 ring->name, I915_READ_IMR(ring));
9862e600 940 }
a2c7f6fd 941 i915_ring_seqno_info(m, ring);
9862e600 942 }
c8c8fb33 943 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 944 mutex_unlock(&dev->struct_mutex);
945
2017263e
BG		 946 return 0;
947}
948
a6172a80
CW		 949static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
950{
9f25d007 951 struct drm_info_node *node = m->private;
a6172a80 952 struct drm_device *dev = node->minor->dev;
e277a1f8 953 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 954 int i, ret;
955
956 ret = mutex_lock_interruptible(&dev->struct_mutex);
957 if (ret)
958 return ret;
a6172a80
CW		 959
960 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
961 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
962 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 963 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 964
6c085a72
CW		 965 seq_printf(m, "Fence %d, pin count = %d, object = ",
966 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 967 if (obj == NULL)
267f0c90 968 seq_puts(m, "unused");
c2c347a9 969 else
05394f39 970 describe_obj(m, obj);
267f0c90 971 seq_putc(m, '\n');
a6172a80
CW		 972 }
973
05394f39 974 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 975 return 0;
976}
977
2017263e
BG		 978static int i915_hws_info(struct seq_file *m, void *data)
979{
9f25d007 980 struct drm_info_node *node = m->private;
2017263e 981 struct drm_device *dev = node->minor->dev;
e277a1f8 982 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 983 struct intel_engine_cs *ring;
1a240d4d 984 const u32 *hws;
4066c0ae
CW		 985 int i;
986
1ec14ad3 987 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 988 hws = ring->status_page.page_addr;
2017263e
BG		 989 if (hws == NULL)
990 return 0;
991
992 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
993 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
994 i * 4,
995 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
996 }
997 return 0;
998}
999
d5442303
DV		 1000static ssize_t
1001i915_error_state_write(struct file *filp,
1002 const char __user *ubuf,
1003 size_t cnt,
1004 loff_t *ppos)
1005{
edc3d884 1006 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1007 struct drm_device *dev = error_priv->dev;
22bcfc6a 1008 int ret;
d5442303
DV		 1009
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1011
22bcfc6a
DV		 1012 ret = mutex_lock_interruptible(&dev->struct_mutex);
1013 if (ret)
1014 return ret;
1015
d5442303
DV		 1016 i915_destroy_error_state(dev);
1017 mutex_unlock(&dev->struct_mutex);
1018
1019 return cnt;
1020}
1021
1022static int i915_error_state_open(struct inode *inode, struct file *file)
1023{
1024 struct drm_device *dev = inode->i_private;
d5442303 1025 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1026
1027 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1028 if (!error_priv)
1029 return -ENOMEM;
1030
1031 error_priv->dev = dev;
1032
95d5bfb3 1033 i915_error_state_get(dev, error_priv);
d5442303 1034
edc3d884
MK		 1035 file->private_data = error_priv;
1036
1037 return 0;
d5442303
DV		 1038}
1039
1040static int i915_error_state_release(struct inode *inode, struct file *file)
1041{
edc3d884 1042 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1043
95d5bfb3 1044 i915_error_state_put(error_priv);
d5442303
DV		 1045 kfree(error_priv);
1046
edc3d884
MK		 1047 return 0;
1048}
1049
4dc955f7
MK		 1050static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051 size_t count, loff_t *pos)
1052{
1053 struct i915_error_state_file_priv *error_priv = file->private_data;
1054 struct drm_i915_error_state_buf error_str;
1055 loff_t tmp_pos = 0;
1056 ssize_t ret_count = 0;
1057 int ret;
1058
0a4cd7c8 1059 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1060 if (ret)
1061 return ret;
edc3d884 1062
fc16b48b 1063 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1064 if (ret)
1065 goto out;
1066
edc3d884
MK		 1067 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1068 error_str.buf,
1069 error_str.bytes);
1070
1071 if (ret_count < 0)
1072 ret = ret_count;
1073 else
1074 *pos = error_str.start + ret_count;
1075out:
4dc955f7 1076 i915_error_state_buf_release(&error_str);
edc3d884 1077 return ret ?: ret_count;
d5442303
DV		 1078}
1079
1080static const struct file_operations i915_error_state_fops = {
1081 .owner = THIS_MODULE,
1082 .open = i915_error_state_open,
edc3d884 1083 .read = i915_error_state_read,
d5442303
DV		 1084 .write = i915_error_state_write,
1085 .llseek = default_llseek,
1086 .release = i915_error_state_release,
1087};
1088
647416f9
KC		 1089static int
1090i915_next_seqno_get(void *data, u64 *val)
40633219 1091{
647416f9 1092 struct drm_device *dev = data;
e277a1f8 1093 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1094 int ret;
1095
1096 ret = mutex_lock_interruptible(&dev->struct_mutex);
1097 if (ret)
1098 return ret;
1099
647416f9 1100 *val = dev_priv->next_seqno;
40633219
MK		 1101 mutex_unlock(&dev->struct_mutex);
1102
647416f9 1103 return 0;
40633219
MK		 1104}
1105
647416f9
KC		 1106static int
1107i915_next_seqno_set(void *data, u64 val)
1108{
1109 struct drm_device *dev = data;
40633219
MK		 1110 int ret;
1111
40633219
MK		 1112 ret = mutex_lock_interruptible(&dev->struct_mutex);
1113 if (ret)
1114 return ret;
1115
e94fbaa8 1116 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1117 mutex_unlock(&dev->struct_mutex);
1118
647416f9 1119 return ret;
40633219
MK		 1120}
1121
647416f9
KC		 1122DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1124 "0x%llx\n");
40633219 1125
adb4bd12 1126static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1127{
9f25d007 1128 struct drm_info_node *node = m->private;
f97108d1 1129 struct drm_device *dev = node->minor->dev;
e277a1f8 1130 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1131 int ret = 0;
1132
1133 intel_runtime_pm_get(dev_priv);
3b8d8d91 1134
5c9669ce
TR		 1135 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136
3b8d8d91
JB		 1137 if (IS_GEN5(dev)) {
1138 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1140
1141 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1144 MEMSTAT_VID_SHIFT);
1145 seq_printf(m, "Current P-state: %d\n",
1146 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1147 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1148 IS_BROADWELL(dev) || IS_GEN9(dev)) {
35040562
BP		 1149 u32 rp_state_limits;
1150 u32 gt_perf_status;
1151 u32 rp_state_cap;
0d8f9491 1152 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1153 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1154 u32 rpupei, rpcurup, rpprevup;
1155 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1156 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1157 int max_freq;
1158
35040562
BP		 1159 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1160 if (IS_BROXTON(dev)) {
1161 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1162 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1163 } else {
1164 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1165 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1166 }
1167
3b8d8d91 1168 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1169 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170 if (ret)
c8c8fb33 1171 goto out;
d1ebd816 1172
59bad947 1173 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1174
8e8c06cd 1175 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1176 if (IS_GEN9(dev))
1177 reqf >>= 23;
1178 else {
1179 reqf &= ~GEN6_TURBO_DISABLE;
1180 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1181 reqf >>= 24;
1182 else
1183 reqf >>= 25;
1184 }
7c59a9c1 1185 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1186
0d8f9491
CW		 1187 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1188 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1189 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1190
ccab5c82
JB		 1191 rpstat = I915_READ(GEN6_RPSTAT1);
1192 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1193 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1194 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1195 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1196 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1197 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1198 if (IS_GEN9(dev))
1199 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1200 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1201 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1202 else
1203 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1204 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1205
59bad947 1206 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1207 mutex_unlock(&dev->struct_mutex);
1208
9dd3c605
PZ		 1209 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1210 pm_ier = I915_READ(GEN6_PMIER);
1211 pm_imr = I915_READ(GEN6_PMIMR);
1212 pm_isr = I915_READ(GEN6_PMISR);
1213 pm_iir = I915_READ(GEN6_PMIIR);
1214 pm_mask = I915_READ(GEN6_PMINTRMSK);
1215 } else {
1216 pm_ier = I915_READ(GEN8_GT_IER(2));
1217 pm_imr = I915_READ(GEN8_GT_IMR(2));
1218 pm_isr = I915_READ(GEN8_GT_ISR(2));
1219 pm_iir = I915_READ(GEN8_GT_IIR(2));
1220 pm_mask = I915_READ(GEN6_PMINTRMSK);
1221 }
0d8f9491 1222 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1223 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1224 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1225 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1226 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1227 seq_printf(m, "Render p-state VID: %d\n",
1228 gt_perf_status & 0xff);
1229 seq_printf(m, "Render p-state limit: %d\n",
1230 rp_state_limits & 0xff);
0d8f9491
CW		 1231 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1232 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1233 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1234 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1235 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1236 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1237 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1238 GEN6_CURICONT_MASK);
1239 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1240 GEN6_CURBSYTAVG_MASK);
1241 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1242 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1243 seq_printf(m, "Up threshold: %d%%\n",
1244 dev_priv->rps.up_threshold);
1245
ccab5c82
JB		 1246 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1247 GEN6_CURIAVG_MASK);
1248 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1249 GEN6_CURBSYTAVG_MASK);
1250 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1251 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1252 seq_printf(m, "Down threshold: %d%%\n",
1253 dev_priv->rps.down_threshold);
3b8d8d91 1254
35040562
BP		 1255 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1256 rp_state_cap >> 16) & 0xff;
60260a5b 1257 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1258 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1259 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1260
1261 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1262 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1263 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1264 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1265
35040562
BP		 1266 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267 rp_state_cap >> 0) & 0xff;
60260a5b 1268 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1269 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1270 intel_gpu_freq(dev_priv, max_freq));
31c77388 1271 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1272 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1273
d86ed34a
CW		 1274 seq_printf(m, "Current freq: %d MHz\n",
1275 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1276 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1277 seq_printf(m, "Idle freq: %d MHz\n",
1278 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1279 seq_printf(m, "Min freq: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1281 seq_printf(m, "Max freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1283 seq_printf(m,
1284 "efficient (RPe) frequency: %d MHz\n",
1285 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84 1286 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1287 u32 freq_sts;
0a073b84 1288
259bd5d4 1289 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1290 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1291 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1292 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1293
d86ed34a
CW		 1294 seq_printf(m, "actual GPU freq: %d MHz\n",
1295 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1296
1297 seq_printf(m, "current GPU freq: %d MHz\n",
1298 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1299
0a073b84 1300 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1301 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1302
0a073b84 1303 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1304 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1305
aed242ff
CW		 1306 seq_printf(m, "idle GPU freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1308
7c59a9c1
VS		 1309 seq_printf(m,
1310 "efficient (RPe) frequency: %d MHz\n",
1311 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
259bd5d4 1312 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1313 } else {
267f0c90 1314 seq_puts(m, "no P-state info available\n");
3b8d8d91 1315 }
f97108d1 1316
c8c8fb33
PZ		 1317out:
1318 intel_runtime_pm_put(dev_priv);
1319 return ret;
f97108d1
JB		 1320}
1321
f654449a
CW		 1322static int i915_hangcheck_info(struct seq_file *m, void *unused)
1323{
1324 struct drm_info_node *node = m->private;
ebbc7546
MK		 1325 struct drm_device *dev = node->minor->dev;
1326 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1327 struct intel_engine_cs *ring;
ebbc7546
MK		 1328 u64 acthd[I915_NUM_RINGS];
1329 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1330 int i;
1331
1332 if (!i915.enable_hangcheck) {
1333 seq_printf(m, "Hangcheck disabled\n");
1334 return 0;
1335 }
1336
ebbc7546
MK		 1337 intel_runtime_pm_get(dev_priv);
1338
1339 for_each_ring(ring, dev_priv, i) {
1340 seqno[i] = ring->get_seqno(ring, false);
1341 acthd[i] = intel_ring_get_active_head(ring);
1342 }
1343
1344 intel_runtime_pm_put(dev_priv);
1345
f654449a
CW		 1346 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1347 seq_printf(m, "Hangcheck active, fires in %dms\n",
1348 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1349 jiffies));
1350 } else
1351 seq_printf(m, "Hangcheck inactive\n");
1352
1353 for_each_ring(ring, dev_priv, i) {
1354 seq_printf(m, "%s:\n", ring->name);
1355 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1356 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1357 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1358 (long long)ring->hangcheck.acthd,
ebbc7546 1359 (long long)acthd[i]);
f654449a
CW		 1360 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1361 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1362 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1363 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1364 }
1365
1366 return 0;
1367}
1368
4d85529d 1369static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1370{
9f25d007 1371 struct drm_info_node *node = m->private;
f97108d1 1372 struct drm_device *dev = node->minor->dev;
e277a1f8 1373 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1374 u32 rgvmodectl, rstdbyctl;
1375 u16 crstandvid;
1376 int ret;
1377
1378 ret = mutex_lock_interruptible(&dev->struct_mutex);
1379 if (ret)
1380 return ret;
c8c8fb33 1381 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1382
1383 rgvmodectl = I915_READ(MEMMODECTL);
1384 rstdbyctl = I915_READ(RSTDBYCTL);
1385 crstandvid = I915_READ16(CRSTANDVID);
1386
c8c8fb33 1387 intel_runtime_pm_put(dev_priv);
616fdb5a 1388 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1389
1390 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1391 "yes" : "no");
1392 seq_printf(m, "Boost freq: %d\n",
1393 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1394 MEMMODE_BOOST_FREQ_SHIFT);
1395 seq_printf(m, "HW control enabled: %s\n",
1396 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1397 seq_printf(m, "SW control enabled: %s\n",
1398 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1399 seq_printf(m, "Gated voltage change: %s\n",
1400 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1401 seq_printf(m, "Starting frequency: P%d\n",
1402 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1403 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1404 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1405 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1406 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1407 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1408 seq_printf(m, "Render standby enabled: %s\n",
1409 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1410 seq_puts(m, "Current RS state: ");
88271da3
JB		 1411 switch (rstdbyctl & RSX_STATUS_MASK) {
1412 case RSX_STATUS_ON:
267f0c90 1413 seq_puts(m, "on\n");
88271da3
JB		 1414 break;
1415 case RSX_STATUS_RC1:
267f0c90 1416 seq_puts(m, "RC1\n");
88271da3
JB		 1417 break;
1418 case RSX_STATUS_RC1E:
267f0c90 1419 seq_puts(m, "RC1E\n");
88271da3
JB		 1420 break;
1421 case RSX_STATUS_RS1:
267f0c90 1422 seq_puts(m, "RS1\n");
88271da3
JB		 1423 break;
1424 case RSX_STATUS_RS2:
267f0c90 1425 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1426 break;
1427 case RSX_STATUS_RS3:
267f0c90 1428 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1429 break;
1430 default:
267f0c90 1431 seq_puts(m, "unknown\n");
88271da3
JB		 1432 break;
1433 }
f97108d1
JB		 1434
1435 return 0;
1436}
1437
f65367b5 1438static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1439{
b2cff0db
CW		 1440 struct drm_info_node *node = m->private;
1441 struct drm_device *dev = node->minor->dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1444 int i;
1445
1446 spin_lock_irq(&dev_priv->uncore.lock);
1447 for_each_fw_domain(fw_domain, dev_priv, i) {
1448 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1449 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1450 fw_domain->wake_count);
1451 }
1452 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1453
b2cff0db
CW		 1454 return 0;
1455}
1456
1457static int vlv_drpc_info(struct seq_file *m)
1458{
9f25d007 1459 struct drm_info_node *node = m->private;
669ab5aa
D		 1460 struct drm_device *dev = node->minor->dev;
1461 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1462 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1463
d46c0517
ID		 1464 intel_runtime_pm_get(dev_priv);
1465
6b312cd3 1466 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1467 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1468 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1469
d46c0517
ID		 1470 intel_runtime_pm_put(dev_priv);
1471
669ab5aa
D		 1472 seq_printf(m, "Video Turbo Mode: %s\n",
1473 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1474 seq_printf(m, "Turbo enabled: %s\n",
1475 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1476 seq_printf(m, "HW control enabled: %s\n",
1477 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478 seq_printf(m, "SW control enabled: %s\n",
1479 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1480 GEN6_RP_MEDIA_SW_MODE));
1481 seq_printf(m, "RC6 Enabled: %s\n",
1482 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1483 GEN6_RC_CTL_EI_MODE(1))));
1484 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1485 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1486 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1487 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1488
9cc19be5
ID		 1489 seq_printf(m, "Render RC6 residency since boot: %u\n",
1490 I915_READ(VLV_GT_RENDER_RC6));
1491 seq_printf(m, "Media RC6 residency since boot: %u\n",
1492 I915_READ(VLV_GT_MEDIA_RC6));
1493
f65367b5 1494 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1495}
1496
4d85529d
BW		 1497static int gen6_drpc_info(struct seq_file *m)
1498{
9f25d007 1499 struct drm_info_node *node = m->private;
4d85529d
BW		 1500 struct drm_device *dev = node->minor->dev;
1501 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1502 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1503 unsigned forcewake_count;
aee56cff 1504 int count = 0, ret;
4d85529d
BW		 1505
1506 ret = mutex_lock_interruptible(&dev->struct_mutex);
1507 if (ret)
1508 return ret;
c8c8fb33 1509 intel_runtime_pm_get(dev_priv);
4d85529d 1510
907b28c5 1511 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1512 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1513 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1514
1515 if (forcewake_count) {
267f0c90
DL		 1516 seq_puts(m, "RC information inaccurate because somebody "
1517 "holds a forcewake reference \n");
4d85529d
BW		 1518 } else {
1519 /* NB: we cannot use forcewake, else we read the wrong values */
1520 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1521 udelay(10);
1522 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1523 }
1524
1525 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1526 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1527
1528 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1529 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1530 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1531 mutex_lock(&dev_priv->rps.hw_lock);
1532 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1533 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1534
c8c8fb33
PZ		 1535 intel_runtime_pm_put(dev_priv);
1536
4d85529d
BW		 1537 seq_printf(m, "Video Turbo Mode: %s\n",
1538 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1539 seq_printf(m, "HW control enabled: %s\n",
1540 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1541 seq_printf(m, "SW control enabled: %s\n",
1542 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1543 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1544 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1545 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546 seq_printf(m, "RC6 Enabled: %s\n",
1547 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548 seq_printf(m, "Deep RC6 Enabled: %s\n",
1549 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1550 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1551 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1552 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1553 switch (gt_core_status & GEN6_RCn_MASK) {
1554 case GEN6_RC0:
1555 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1556 seq_puts(m, "Core Power Down\n");
4d85529d 1557 else
267f0c90 1558 seq_puts(m, "on\n");
4d85529d
BW		 1559 break;
1560 case GEN6_RC3:
267f0c90 1561 seq_puts(m, "RC3\n");
4d85529d
BW		 1562 break;
1563 case GEN6_RC6:
267f0c90 1564 seq_puts(m, "RC6\n");
4d85529d
BW		 1565 break;
1566 case GEN6_RC7:
267f0c90 1567 seq_puts(m, "RC7\n");
4d85529d
BW		 1568 break;
1569 default:
267f0c90 1570 seq_puts(m, "Unknown\n");
4d85529d
BW		 1571 break;
1572 }
1573
1574 seq_printf(m, "Core Power Down: %s\n",
1575 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1576
1577 /* Not exactly sure what this is */
1578 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1579 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1580 seq_printf(m, "RC6 residency since boot: %u\n",
1581 I915_READ(GEN6_GT_GFX_RC6));
1582 seq_printf(m, "RC6+ residency since boot: %u\n",
1583 I915_READ(GEN6_GT_GFX_RC6p));
1584 seq_printf(m, "RC6++ residency since boot: %u\n",
1585 I915_READ(GEN6_GT_GFX_RC6pp));
1586
ecd8faea
BW		 1587 seq_printf(m, "RC6 voltage: %dmV\n",
1588 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1589 seq_printf(m, "RC6+ voltage: %dmV\n",
1590 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1591 seq_printf(m, "RC6++ voltage: %dmV\n",
1592 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1593 return 0;
1594}
1595
1596static int i915_drpc_info(struct seq_file *m, void *unused)
1597{
9f25d007 1598 struct drm_info_node *node = m->private;
4d85529d
BW		 1599 struct drm_device *dev = node->minor->dev;
1600
669ab5aa
D		 1601 if (IS_VALLEYVIEW(dev))
1602 return vlv_drpc_info(m);
ac66cf4b 1603 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1604 return gen6_drpc_info(m);
1605 else
1606 return ironlake_drpc_info(m);
1607}
1608
9a851789
DV		 1609static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1610{
1611 struct drm_info_node *node = m->private;
1612 struct drm_device *dev = node->minor->dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614
1615 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1616 dev_priv->fb_tracking.busy_bits);
1617
1618 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1619 dev_priv->fb_tracking.flip_bits);
1620
1621 return 0;
1622}
1623
b5e50c3f
JB		 1624static int i915_fbc_status(struct seq_file *m, void *unused)
1625{
9f25d007 1626 struct drm_info_node *node = m->private;
b5e50c3f 1627 struct drm_device *dev = node->minor->dev;
e277a1f8 1628 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1629
3a77c4c4 1630 if (!HAS_FBC(dev)) {
267f0c90 1631 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1632 return 0;
1633 }
1634
36623ef8 1635 intel_runtime_pm_get(dev_priv);
25ad93fd 1636 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1637
7733b49b 1638 if (intel_fbc_enabled(dev_priv))
267f0c90 1639 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1640 else
1641 seq_printf(m, "FBC disabled: %s\n",
1642 intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
36623ef8 1643
31b9df10
PZ		 1644 if (INTEL_INFO(dev_priv)->gen >= 7)
1645 seq_printf(m, "Compressing: %s\n",
1646 yesno(I915_READ(FBC_STATUS2) &
1647 FBC_COMPRESSION_MASK));
1648
25ad93fd 1649 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1650 intel_runtime_pm_put(dev_priv);
1651
b5e50c3f
JB		 1652 return 0;
1653}
1654
da46f936
RV		 1655static int i915_fbc_fc_get(void *data, u64 *val)
1656{
1657 struct drm_device *dev = data;
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659
1660 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1661 return -ENODEV;
1662
da46f936 1663 *val = dev_priv->fbc.false_color;
da46f936
RV		 1664
1665 return 0;
1666}
1667
1668static int i915_fbc_fc_set(void *data, u64 val)
1669{
1670 struct drm_device *dev = data;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 u32 reg;
1673
1674 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1675 return -ENODEV;
1676
25ad93fd 1677 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1678
1679 reg = I915_READ(ILK_DPFC_CONTROL);
1680 dev_priv->fbc.false_color = val;
1681
1682 I915_WRITE(ILK_DPFC_CONTROL, val ?
1683 (reg | FBC_CTL_FALSE_COLOR) :
1684 (reg & ~FBC_CTL_FALSE_COLOR));
1685
25ad93fd 1686 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1687 return 0;
1688}
1689
1690DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1691 i915_fbc_fc_get, i915_fbc_fc_set,
1692 "%llu\n");
1693
92d44621
PZ		 1694static int i915_ips_status(struct seq_file *m, void *unused)
1695{
9f25d007 1696 struct drm_info_node *node = m->private;
92d44621
PZ		 1697 struct drm_device *dev = node->minor->dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699
f5adf94e 1700 if (!HAS_IPS(dev)) {
92d44621
PZ		 1701 seq_puts(m, "not supported\n");
1702 return 0;
1703 }
1704
36623ef8
PZ		 1705 intel_runtime_pm_get(dev_priv);
1706
0eaa53f0
RV		 1707 seq_printf(m, "Enabled by kernel parameter: %s\n",
1708 yesno(i915.enable_ips));
1709
1710 if (INTEL_INFO(dev)->gen >= 8) {
1711 seq_puts(m, "Currently: unknown\n");
1712 } else {
1713 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1714 seq_puts(m, "Currently: enabled\n");
1715 else
1716 seq_puts(m, "Currently: disabled\n");
1717 }
92d44621 1718
36623ef8
PZ		 1719 intel_runtime_pm_put(dev_priv);
1720
92d44621
PZ		 1721 return 0;
1722}
1723
4a9bef37
JB		 1724static int i915_sr_status(struct seq_file *m, void *unused)
1725{
9f25d007 1726 struct drm_info_node *node = m->private;
4a9bef37 1727 struct drm_device *dev = node->minor->dev;
e277a1f8 1728 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1729 bool sr_enabled = false;
1730
36623ef8
PZ		 1731 intel_runtime_pm_get(dev_priv);
1732
1398261a 1733 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1734 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1735 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1736 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1737 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1738 else if (IS_I915GM(dev))
1739 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1740 else if (IS_PINEVIEW(dev))
1741 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
77b64555
ACO		 1742 else if (IS_VALLEYVIEW(dev))
1743 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1744
36623ef8
PZ		 1745 intel_runtime_pm_put(dev_priv);
1746
5ba2aaaa
CW		 1747 seq_printf(m, "self-refresh: %s\n",
1748 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1749
1750 return 0;
1751}
1752
7648fa99
JB		 1753static int i915_emon_status(struct seq_file *m, void *unused)
1754{
9f25d007 1755 struct drm_info_node *node = m->private;
7648fa99 1756 struct drm_device *dev = node->minor->dev;
e277a1f8 1757 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1758 unsigned long temp, chipset, gfx;
de227ef0
CW		 1759 int ret;
1760
582be6b4
CW		 1761 if (!IS_GEN5(dev))
1762 return -ENODEV;
1763
de227ef0
CW		 1764 ret = mutex_lock_interruptible(&dev->struct_mutex);
1765 if (ret)
1766 return ret;
7648fa99
JB		 1767
1768 temp = i915_mch_val(dev_priv);
1769 chipset = i915_chipset_val(dev_priv);
1770 gfx = i915_gfx_val(dev_priv);
de227ef0 1771 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1772
1773 seq_printf(m, "GMCH temp: %ld\n", temp);
1774 seq_printf(m, "Chipset power: %ld\n", chipset);
1775 seq_printf(m, "GFX power: %ld\n", gfx);
1776 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1777
1778 return 0;
1779}
1780
23b2f8bb
JB		 1781static int i915_ring_freq_table(struct seq_file *m, void *unused)
1782{
9f25d007 1783 struct drm_info_node *node = m->private;
23b2f8bb 1784 struct drm_device *dev = node->minor->dev;
e277a1f8 1785 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1786 int ret = 0;
23b2f8bb 1787 int gpu_freq, ia_freq;
f936ec34 1788 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1789
97d3308a 1790 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1791 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1792 return 0;
1793 }
1794
5bfa0199
PZ		 1795 intel_runtime_pm_get(dev_priv);
1796
5c9669ce
TR		 1797 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1798
4fc688ce 1799 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1800 if (ret)
5bfa0199 1801 goto out;
23b2f8bb 1802
f936ec34
AG		 1803 if (IS_SKYLAKE(dev)) {
1804 /* Convert GT frequency to 50 HZ units */
1805 min_gpu_freq =
1806 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1807 max_gpu_freq =
1808 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1809 } else {
1810 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1811 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1812 }
1813
267f0c90 1814 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1815
f936ec34 1816 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1817 ia_freq = gpu_freq;
1818 sandybridge_pcode_read(dev_priv,
1819 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1820 &ia_freq);
3ebecd07 1821 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34
AG		 1822 intel_gpu_freq(dev_priv, (gpu_freq *
1823 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1824 ((ia_freq >> 0) & 0xff) * 100,
1825 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1826 }
1827
4fc688ce 1828 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1829
5bfa0199
PZ		 1830out:
1831 intel_runtime_pm_put(dev_priv);
1832 return ret;
23b2f8bb
JB		 1833}
1834
44834a67
CW		 1835static int i915_opregion(struct seq_file *m, void *unused)
1836{
9f25d007 1837 struct drm_info_node *node = m->private;
44834a67 1838 struct drm_device *dev = node->minor->dev;
e277a1f8 1839 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1840 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1841 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1842 int ret;
1843
0d38f009
DV		 1844 if (data == NULL)
1845 return -ENOMEM;
1846
44834a67
CW		 1847 ret = mutex_lock_interruptible(&dev->struct_mutex);
1848 if (ret)
0d38f009 1849 goto out;
44834a67 1850
0d38f009
DV		 1851 if (opregion->header) {
1852 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1853 seq_write(m, data, OPREGION_SIZE);
1854 }
44834a67
CW		 1855
1856 mutex_unlock(&dev->struct_mutex);
1857
0d38f009
DV		 1858out:
1859 kfree(data);
44834a67
CW		 1860 return 0;
1861}
1862
37811fcc
CW		 1863static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1864{
9f25d007 1865 struct drm_info_node *node = m->private;
37811fcc 1866 struct drm_device *dev = node->minor->dev;
4520f53a 1867 struct intel_fbdev *ifbdev = NULL;
37811fcc 1868 struct intel_framebuffer *fb;
3a58ee10 1869 struct drm_framebuffer *drm_fb;
37811fcc 1870
4520f53a
DV		 1871#ifdef CONFIG_DRM_I915_FBDEV
1872 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1873
1874 ifbdev = dev_priv->fbdev;
1875 fb = to_intel_framebuffer(ifbdev->helper.fb);
1876
c1ca506d 1877 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1878 fb->base.width,
1879 fb->base.height,
1880 fb->base.depth,
623f9783 1881 fb->base.bits_per_pixel,
c1ca506d 1882 fb->base.modifier[0],
623f9783 1883 atomic_read(&fb->base.refcount.refcount));
05394f39 1884 describe_obj(m, fb->obj);
267f0c90 1885 seq_putc(m, '\n');
4520f53a 1886#endif
37811fcc 1887
4b096ac1 1888 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10
DV		 1889 drm_for_each_fb(drm_fb, dev) {
1890 fb = to_intel_framebuffer(drm_fb);
131a56dc 1891 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1892 continue;
1893
c1ca506d 1894 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1895 fb->base.width,
1896 fb->base.height,
1897 fb->base.depth,
623f9783 1898 fb->base.bits_per_pixel,
c1ca506d 1899 fb->base.modifier[0],
623f9783 1900 atomic_read(&fb->base.refcount.refcount));
05394f39 1901 describe_obj(m, fb->obj);
267f0c90 1902 seq_putc(m, '\n');
37811fcc 1903 }
4b096ac1 1904 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1905
1906 return 0;
1907}
1908
c9fe99bd
OM		 1909static void describe_ctx_ringbuf(struct seq_file *m,
1910 struct intel_ringbuffer *ringbuf)
1911{
1912 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1913 ringbuf->space, ringbuf->head, ringbuf->tail,
1914 ringbuf->last_retired_head);
1915}
1916
e76d3630
BW		 1917static int i915_context_status(struct seq_file *m, void *unused)
1918{
9f25d007 1919 struct drm_info_node *node = m->private;
e76d3630 1920 struct drm_device *dev = node->minor->dev;
e277a1f8 1921 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1922 struct intel_engine_cs *ring;
273497e5 1923 struct intel_context *ctx;
a168c293 1924 int ret, i;
e76d3630 1925
f3d28878 1926 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1927 if (ret)
1928 return ret;
1929
a33afea5 1930 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1931 if (!i915.enable_execlists &&
1932 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1933 continue;
1934
a33afea5 1935 seq_puts(m, "HW context ");
3ccfd19d 1936 describe_ctx(m, ctx);
c9fe99bd 1937 for_each_ring(ring, dev_priv, i) {
a33afea5 1938 if (ring->default_context == ctx)
c9fe99bd
OM		 1939 seq_printf(m, "(default context %s) ",
1940 ring->name);
1941 }
1942
1943 if (i915.enable_execlists) {
1944 seq_putc(m, '\n');
1945 for_each_ring(ring, dev_priv, i) {
1946 struct drm_i915_gem_object *ctx_obj =
1947 ctx->engine[i].state;
1948 struct intel_ringbuffer *ringbuf =
1949 ctx->engine[i].ringbuf;
1950
1951 seq_printf(m, "%s: ", ring->name);
1952 if (ctx_obj)
1953 describe_obj(m, ctx_obj);
1954 if (ringbuf)
1955 describe_ctx_ringbuf(m, ringbuf);
1956 seq_putc(m, '\n');
1957 }
1958 } else {
1959 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1960 }
a33afea5 1961
a33afea5 1962 seq_putc(m, '\n');
a168c293
BW		 1963 }
1964
f3d28878 1965 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1966
1967 return 0;
1968}
1969
064ca1d2
TD		 1970static void i915_dump_lrc_obj(struct seq_file *m,
1971 struct intel_engine_cs *ring,
1972 struct drm_i915_gem_object *ctx_obj)
1973{
1974 struct page *page;
1975 uint32_t *reg_state;
1976 int j;
1977 unsigned long ggtt_offset = 0;
1978
1979 if (ctx_obj == NULL) {
1980 seq_printf(m, "Context on %s with no gem object\n",
1981 ring->name);
1982 return;
1983 }
1984
1985 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1986 intel_execlists_ctx_id(ctx_obj));
1987
1988 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1989 seq_puts(m, "\tNot bound in GGTT\n");
1990 else
1991 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1992
1993 if (i915_gem_object_get_pages(ctx_obj)) {
1994 seq_puts(m, "\tFailed to get pages for context object\n");
1995 return;
1996 }
1997
1998 page = i915_gem_object_get_page(ctx_obj, 1);
1999 if (!WARN_ON(page == NULL)) {
2000 reg_state = kmap_atomic(page);
2001
2002 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2003 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2004 ggtt_offset + 4096 + (j * 4),
2005 reg_state[j], reg_state[j + 1],
2006 reg_state[j + 2], reg_state[j + 3]);
2007 }
2008 kunmap_atomic(reg_state);
2009 }
2010
2011 seq_putc(m, '\n');
2012}
2013
c0ab1ae9
BW		 2014static int i915_dump_lrc(struct seq_file *m, void *unused)
2015{
2016 struct drm_info_node *node = (struct drm_info_node *) m->private;
2017 struct drm_device *dev = node->minor->dev;
2018 struct drm_i915_private *dev_priv = dev->dev_private;
2019 struct intel_engine_cs *ring;
2020 struct intel_context *ctx;
2021 int ret, i;
2022
2023 if (!i915.enable_execlists) {
2024 seq_printf(m, "Logical Ring Contexts are disabled\n");
2025 return 0;
2026 }
2027
2028 ret = mutex_lock_interruptible(&dev->struct_mutex);
2029 if (ret)
2030 return ret;
2031
2032 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2033 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 2034 if (ring->default_context != ctx)
2035 i915_dump_lrc_obj(m, ring,
2036 ctx->engine[i].state);
c0ab1ae9
BW		 2037 }
2038 }
2039
2040 mutex_unlock(&dev->struct_mutex);
2041
2042 return 0;
2043}
2044
4ba70e44
OM		 2045static int i915_execlists(struct seq_file *m, void *data)
2046{
2047 struct drm_info_node *node = (struct drm_info_node *)m->private;
2048 struct drm_device *dev = node->minor->dev;
2049 struct drm_i915_private *dev_priv = dev->dev_private;
2050 struct intel_engine_cs *ring;
2051 u32 status_pointer;
2052 u8 read_pointer;
2053 u8 write_pointer;
2054 u32 status;
2055 u32 ctx_id;
2056 struct list_head *cursor;
2057 int ring_id, i;
2058 int ret;
2059
2060 if (!i915.enable_execlists) {
2061 seq_puts(m, "Logical Ring Contexts are disabled\n");
2062 return 0;
2063 }
2064
2065 ret = mutex_lock_interruptible(&dev->struct_mutex);
2066 if (ret)
2067 return ret;
2068
fc0412ec
MT		 2069 intel_runtime_pm_get(dev_priv);
2070
4ba70e44 2071 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2072 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2073 int count = 0;
2074 unsigned long flags;
2075
2076 seq_printf(m, "%s\n", ring->name);
2077
2078 status = I915_READ(RING_EXECLIST_STATUS(ring));
2079 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2080 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2081 status, ctx_id);
2082
2083 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2084 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2085
2086 read_pointer = ring->next_context_status_buffer;
2087 write_pointer = status_pointer & 0x07;
2088 if (read_pointer > write_pointer)
2089 write_pointer += 6;
2090 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2091 read_pointer, write_pointer);
2092
2093 for (i = 0; i < 6; i++) {
2094 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2095 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2096
2097 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2098 i, status, ctx_id);
2099 }
2100
2101 spin_lock_irqsave(&ring->execlist_lock, flags);
2102 list_for_each(cursor, &ring->execlist_queue)
2103 count++;
2104 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2105 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2106 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2107
2108 seq_printf(m, "\t%d requests in queue\n", count);
2109 if (head_req) {
2110 struct drm_i915_gem_object *ctx_obj;
2111
6d3d8274 2112 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2113 seq_printf(m, "\tHead request id: %u\n",
2114 intel_execlists_ctx_id(ctx_obj));
2115 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2116 head_req->tail);
4ba70e44
OM		 2117 }
2118
2119 seq_putc(m, '\n');
2120 }
2121
fc0412ec 2122 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2123 mutex_unlock(&dev->struct_mutex);
2124
2125 return 0;
2126}
2127
ea16a3cd
DV		 2128static const char *swizzle_string(unsigned swizzle)
2129{
aee56cff 2130 switch (swizzle) {
ea16a3cd
DV		 2131 case I915_BIT_6_SWIZZLE_NONE:
2132 return "none";
2133 case I915_BIT_6_SWIZZLE_9:
2134 return "bit9";
2135 case I915_BIT_6_SWIZZLE_9_10:
2136 return "bit9/bit10";
2137 case I915_BIT_6_SWIZZLE_9_11:
2138 return "bit9/bit11";
2139 case I915_BIT_6_SWIZZLE_9_10_11:
2140 return "bit9/bit10/bit11";
2141 case I915_BIT_6_SWIZZLE_9_17:
2142 return "bit9/bit17";
2143 case I915_BIT_6_SWIZZLE_9_10_17:
2144 return "bit9/bit10/bit17";
2145 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2146 return "unknown";
ea16a3cd
DV		 2147 }
2148
2149 return "bug";
2150}
2151
2152static int i915_swizzle_info(struct seq_file *m, void *data)
2153{
9f25d007 2154 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2155 struct drm_device *dev = node->minor->dev;
2156 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2157 int ret;
2158
2159 ret = mutex_lock_interruptible(&dev->struct_mutex);
2160 if (ret)
2161 return ret;
c8c8fb33 2162 intel_runtime_pm_get(dev_priv);
ea16a3cd 2163
ea16a3cd
DV		 2164 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2165 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2166 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2167 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2168
2169 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2170 seq_printf(m, "DDC = 0x%08x\n",
2171 I915_READ(DCC));
656bfa3a
DV		 2172 seq_printf(m, "DDC2 = 0x%08x\n",
2173 I915_READ(DCC2));
ea16a3cd
DV		 2174 seq_printf(m, "C0DRB3 = 0x%04x\n",
2175 I915_READ16(C0DRB3));
2176 seq_printf(m, "C1DRB3 = 0x%04x\n",
2177 I915_READ16(C1DRB3));
9d3203e1 2178 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2179 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2180 I915_READ(MAD_DIMM_C0));
2181 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2182 I915_READ(MAD_DIMM_C1));
2183 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2184 I915_READ(MAD_DIMM_C2));
2185 seq_printf(m, "TILECTL = 0x%08x\n",
2186 I915_READ(TILECTL));
5907f5fb 2187 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2188 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2189 I915_READ(GAMTARBMODE));
2190 else
2191 seq_printf(m, "ARB_MODE = 0x%08x\n",
2192 I915_READ(ARB_MODE));
3fa7d235
DV		 2193 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2194 I915_READ(DISP_ARB_CTL));
ea16a3cd 2195 }
656bfa3a
DV		 2196
2197 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2198 seq_puts(m, "L-shaped memory detected\n");
2199
c8c8fb33 2200 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2201 mutex_unlock(&dev->struct_mutex);
2202
2203 return 0;
2204}
2205
1c60fef5
BW		 2206static int per_file_ctx(int id, void *ptr, void *data)
2207{
273497e5 2208 struct intel_context *ctx = ptr;
1c60fef5 2209 struct seq_file *m = data;
ae6c4806
DV		 2210 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2211
2212 if (!ppgtt) {
2213 seq_printf(m, " no ppgtt for context %d\n",
2214 ctx->user_handle);
2215 return 0;
2216 }
1c60fef5 2217
f83d6518
OM		 2218 if (i915_gem_context_is_default(ctx))
2219 seq_puts(m, " default context:\n");
2220 else
821d66dd 2221 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2222 ppgtt->debug_dump(ppgtt, m);
2223
2224 return 0;
2225}
2226
77df6772 2227static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2228{
3cf17fc5 2229 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2230 struct intel_engine_cs *ring;
77df6772
BW		 2231 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2232 int unused, i;
3cf17fc5 2233
77df6772
BW		 2234 if (!ppgtt)
2235 return;
2236
77df6772
BW		 2237 for_each_ring(ring, dev_priv, unused) {
2238 seq_printf(m, "%s\n", ring->name);
2239 for (i = 0; i < 4; i++) {
2240 u32 offset = 0x270 + i * 8;
2241 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2242 pdp <<= 32;
2243 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2244 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2245 }
2246 }
2247}
2248
2249static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2250{
2251 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2252 struct intel_engine_cs *ring;
77df6772 2253 int i;
3cf17fc5 2254
3cf17fc5
DV		 2255 if (INTEL_INFO(dev)->gen == 6)
2256 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2257
a2c7f6fd 2258 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2259 seq_printf(m, "%s\n", ring->name);
2260 if (INTEL_INFO(dev)->gen == 7)
2261 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2262 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2263 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2264 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2265 }
2266 if (dev_priv->mm.aliasing_ppgtt) {
2267 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2268
267f0c90 2269 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2270 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2271
87d60b63 2272 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2273 }
1c60fef5 2274
3cf17fc5 2275 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2276}
2277
2278static int i915_ppgtt_info(struct seq_file *m, void *data)
2279{
9f25d007 2280 struct drm_info_node *node = m->private;
77df6772 2281 struct drm_device *dev = node->minor->dev;
c8c8fb33 2282 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2283 struct drm_file *file;
77df6772
BW		 2284
2285 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2286 if (ret)
2287 return ret;
c8c8fb33 2288 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2289
2290 if (INTEL_INFO(dev)->gen >= 8)
2291 gen8_ppgtt_info(m, dev);
2292 else if (INTEL_INFO(dev)->gen >= 6)
2293 gen6_ppgtt_info(m, dev);
2294
ea91e401
MT		 2295 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2296 struct drm_i915_file_private *file_priv = file->driver_priv;
2297
2298 seq_printf(m, "\nproc: %s\n",
2299 get_pid_task(file->pid, PIDTYPE_PID)->comm);
2300 idr_for_each(&file_priv->context_idr, per_file_ctx,
2301 (void *)(unsigned long)m);
2302 }
2303
c8c8fb33 2304 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2305 mutex_unlock(&dev->struct_mutex);
2306
2307 return 0;
2308}
2309
f5a4c67d
CW		 2310static int count_irq_waiters(struct drm_i915_private *i915)
2311{
2312 struct intel_engine_cs *ring;
2313 int count = 0;
2314 int i;
2315
2316 for_each_ring(ring, i915, i)
2317 count += ring->irq_refcount;
2318
2319 return count;
2320}
2321
1854d5ca
CW		 2322static int i915_rps_boost_info(struct seq_file *m, void *data)
2323{
2324 struct drm_info_node *node = m->private;
2325 struct drm_device *dev = node->minor->dev;
2326 struct drm_i915_private *dev_priv = dev->dev_private;
2327 struct drm_file *file;
1854d5ca 2328
f5a4c67d
CW		 2329 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2330 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2331 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2332 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2333 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2334 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2335 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2336 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2337 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2338 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2339 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2340 struct drm_i915_file_private *file_priv = file->driver_priv;
2341 struct task_struct *task;
2342
2343 rcu_read_lock();
2344 task = pid_task(file->pid, PIDTYPE_PID);
2345 seq_printf(m, "%s [%d]: %d boosts%s\n",
2346 task ? task->comm : "<unknown>",
2347 task ? task->pid : -1,
2e1b8730
CW		 2348 file_priv->rps.boosts,
2349 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2350 rcu_read_unlock();
2351 }
2e1b8730
CW		 2352 seq_printf(m, "Semaphore boosts: %d%s\n",
2353 dev_priv->rps.semaphores.boosts,
2354 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2355 seq_printf(m, "MMIO flip boosts: %d%s\n",
2356 dev_priv->rps.mmioflips.boosts,
2357 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2358 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2359 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2360
8d3afd7d 2361 return 0;
1854d5ca
CW		 2362}
2363
63573eb7
BW		 2364static int i915_llc(struct seq_file *m, void *data)
2365{
9f25d007 2366 struct drm_info_node *node = m->private;
63573eb7
BW		 2367 struct drm_device *dev = node->minor->dev;
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369
2370 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2371 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2372 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2373
2374 return 0;
2375}
2376
e91fd8c6
RV		 2377static int i915_edp_psr_status(struct seq_file *m, void *data)
2378{
2379 struct drm_info_node *node = m->private;
2380 struct drm_device *dev = node->minor->dev;
2381 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2382 u32 psrperf = 0;
a6cbdb8e
RV		 2383 u32 stat[3];
2384 enum pipe pipe;
a031d709 2385 bool enabled = false;
e91fd8c6 2386
3553a8ea
DL		 2387 if (!HAS_PSR(dev)) {
2388 seq_puts(m, "PSR not supported\n");
2389 return 0;
2390 }
2391
c8c8fb33
PZ		 2392 intel_runtime_pm_get(dev_priv);
2393
fa128fa6 2394 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2395 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2396 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2397 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2398 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2399 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2400 dev_priv->psr.busy_frontbuffer_bits);
2401 seq_printf(m, "Re-enable work scheduled: %s\n",
2402 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2403
3553a8ea
DL		 2404 if (HAS_DDI(dev))
2405 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2406 else {
2407 for_each_pipe(dev_priv, pipe) {
2408 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2409 VLV_EDP_PSR_CURR_STATE_MASK;
2410 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2411 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2412 enabled = true;
a6cbdb8e
RV		 2413 }
2414 }
2415 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2416
2417 if (!HAS_DDI(dev))
2418 for_each_pipe(dev_priv, pipe) {
2419 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2420 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2421 seq_printf(m, " pipe %c", pipe_name(pipe));
2422 }
2423 seq_puts(m, "\n");
e91fd8c6 2424
a6cbdb8e 2425 /* CHV PSR has no kind of performance counter */
3553a8ea 2426 if (HAS_DDI(dev)) {
a031d709
RV		 2427 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2428 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2429
2430 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2431 }
fa128fa6 2432 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2433
c8c8fb33 2434 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2435 return 0;
2436}
2437
d2e216d0
RV		 2438static int i915_sink_crc(struct seq_file *m, void *data)
2439{
2440 struct drm_info_node *node = m->private;
2441 struct drm_device *dev = node->minor->dev;
2442 struct intel_encoder *encoder;
2443 struct intel_connector *connector;
2444 struct intel_dp *intel_dp = NULL;
2445 int ret;
2446 u8 crc[6];
2447
2448 drm_modeset_lock_all(dev);
aca5e361 2449 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2450
2451 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2452 continue;
2453
b6ae3c7c
PZ		 2454 if (!connector->base.encoder)
2455 continue;
2456
d2e216d0
RV		 2457 encoder = to_intel_encoder(connector->base.encoder);
2458 if (encoder->type != INTEL_OUTPUT_EDP)
2459 continue;
2460
2461 intel_dp = enc_to_intel_dp(&encoder->base);
2462
2463 ret = intel_dp_sink_crc(intel_dp, crc);
2464 if (ret)
2465 goto out;
2466
2467 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2468 crc[0], crc[1], crc[2],
2469 crc[3], crc[4], crc[5]);
2470 goto out;
2471 }
2472 ret = -ENODEV;
2473out:
2474 drm_modeset_unlock_all(dev);
2475 return ret;
2476}
2477
ec013e7f
JB		 2478static int i915_energy_uJ(struct seq_file *m, void *data)
2479{
2480 struct drm_info_node *node = m->private;
2481 struct drm_device *dev = node->minor->dev;
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2483 u64 power;
2484 u32 units;
2485
2486 if (INTEL_INFO(dev)->gen < 6)
2487 return -ENODEV;
2488
36623ef8
PZ		 2489 intel_runtime_pm_get(dev_priv);
2490
ec013e7f
JB		 2491 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2492 power = (power & 0x1f00) >> 8;
2493 units = 1000000 / (1 << power); /* convert to uJ */
2494 power = I915_READ(MCH_SECP_NRG_STTS);
2495 power *= units;
2496
36623ef8
PZ		 2497 intel_runtime_pm_put(dev_priv);
2498
ec013e7f 2499 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2500
2501 return 0;
2502}
2503
6455c870 2504static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2505{
9f25d007 2506 struct drm_info_node *node = m->private;
371db66a
PZ		 2507 struct drm_device *dev = node->minor->dev;
2508 struct drm_i915_private *dev_priv = dev->dev_private;
2509
6455c870 2510 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2511 seq_puts(m, "not supported\n");
2512 return 0;
2513 }
2514
86c4ec0d 2515 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2516 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2517 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2518#ifdef CONFIG_PM
a6aaec8b
DL		 2519 seq_printf(m, "Usage count: %d\n",
2520 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2521#else
2522 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2523#endif
371db66a 2524
ec013e7f
JB		 2525 return 0;
2526}
2527
1da51581
ID		 2528static const char *power_domain_str(enum intel_display_power_domain domain)
2529{
2530 switch (domain) {
2531 case POWER_DOMAIN_PIPE_A:
2532 return "PIPE_A";
2533 case POWER_DOMAIN_PIPE_B:
2534 return "PIPE_B";
2535 case POWER_DOMAIN_PIPE_C:
2536 return "PIPE_C";
2537 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2538 return "PIPE_A_PANEL_FITTER";
2539 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2540 return "PIPE_B_PANEL_FITTER";
2541 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2542 return "PIPE_C_PANEL_FITTER";
2543 case POWER_DOMAIN_TRANSCODER_A:
2544 return "TRANSCODER_A";
2545 case POWER_DOMAIN_TRANSCODER_B:
2546 return "TRANSCODER_B";
2547 case POWER_DOMAIN_TRANSCODER_C:
2548 return "TRANSCODER_C";
2549 case POWER_DOMAIN_TRANSCODER_EDP:
2550 return "TRANSCODER_EDP";
319be8ae
ID		 2551 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2552 return "PORT_DDI_A_2_LANES";
2553 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2554 return "PORT_DDI_A_4_LANES";
2555 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2556 return "PORT_DDI_B_2_LANES";
2557 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2558 return "PORT_DDI_B_4_LANES";
2559 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2560 return "PORT_DDI_C_2_LANES";
2561 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2562 return "PORT_DDI_C_4_LANES";
2563 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2564 return "PORT_DDI_D_2_LANES";
2565 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2566 return "PORT_DDI_D_4_LANES";
2567 case POWER_DOMAIN_PORT_DSI:
2568 return "PORT_DSI";
2569 case POWER_DOMAIN_PORT_CRT:
2570 return "PORT_CRT";
2571 case POWER_DOMAIN_PORT_OTHER:
2572 return "PORT_OTHER";
1da51581
ID		 2573 case POWER_DOMAIN_VGA:
2574 return "VGA";
2575 case POWER_DOMAIN_AUDIO:
2576 return "AUDIO";
bd2bb1b9
PZ		 2577 case POWER_DOMAIN_PLLS:
2578 return "PLLS";
1407121a
S		 2579 case POWER_DOMAIN_AUX_A:
2580 return "AUX_A";
2581 case POWER_DOMAIN_AUX_B:
2582 return "AUX_B";
2583 case POWER_DOMAIN_AUX_C:
2584 return "AUX_C";
2585 case POWER_DOMAIN_AUX_D:
2586 return "AUX_D";
1da51581
ID		 2587 case POWER_DOMAIN_INIT:
2588 return "INIT";
2589 default:
5f77eeb0 2590 MISSING_CASE(domain);
1da51581
ID		 2591 return "?";
2592 }
2593}
2594
2595static int i915_power_domain_info(struct seq_file *m, void *unused)
2596{
9f25d007 2597 struct drm_info_node *node = m->private;
1da51581
ID		 2598 struct drm_device *dev = node->minor->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2601 int i;
2602
2603 mutex_lock(&power_domains->lock);
2604
2605 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2606 for (i = 0; i < power_domains->power_well_count; i++) {
2607 struct i915_power_well *power_well;
2608 enum intel_display_power_domain power_domain;
2609
2610 power_well = &power_domains->power_wells[i];
2611 seq_printf(m, "%-25s %d\n", power_well->name,
2612 power_well->count);
2613
2614 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2615 power_domain++) {
2616 if (!(BIT(power_domain) & power_well->domains))
2617 continue;
2618
2619 seq_printf(m, " %-23s %d\n",
2620 power_domain_str(power_domain),
2621 power_domains->domain_use_count[power_domain]);
2622 }
2623 }
2624
2625 mutex_unlock(&power_domains->lock);
2626
2627 return 0;
2628}
2629
53f5e3ca
JB		 2630static void intel_seq_print_mode(struct seq_file *m, int tabs,
2631 struct drm_display_mode *mode)
2632{
2633 int i;
2634
2635 for (i = 0; i < tabs; i++)
2636 seq_putc(m, '\t');
2637
2638 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2639 mode->base.id, mode->name,
2640 mode->vrefresh, mode->clock,
2641 mode->hdisplay, mode->hsync_start,
2642 mode->hsync_end, mode->htotal,
2643 mode->vdisplay, mode->vsync_start,
2644 mode->vsync_end, mode->vtotal,
2645 mode->type, mode->flags);
2646}
2647
2648static void intel_encoder_info(struct seq_file *m,
2649 struct intel_crtc *intel_crtc,
2650 struct intel_encoder *intel_encoder)
2651{
9f25d007 2652 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2653 struct drm_device *dev = node->minor->dev;
2654 struct drm_crtc *crtc = &intel_crtc->base;
2655 struct intel_connector *intel_connector;
2656 struct drm_encoder *encoder;
2657
2658 encoder = &intel_encoder->base;
2659 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2660 encoder->base.id, encoder->name);
53f5e3ca
JB		 2661 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2662 struct drm_connector *connector = &intel_connector->base;
2663 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2664 connector->base.id,
c23cc417 2665 connector->name,
53f5e3ca
JB		 2666 drm_get_connector_status_name(connector->status));
2667 if (connector->status == connector_status_connected) {
2668 struct drm_display_mode *mode = &crtc->mode;
2669 seq_printf(m, ", mode:\n");
2670 intel_seq_print_mode(m, 2, mode);
2671 } else {
2672 seq_putc(m, '\n');
2673 }
2674 }
2675}
2676
2677static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2678{
9f25d007 2679 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2680 struct drm_device *dev = node->minor->dev;
2681 struct drm_crtc *crtc = &intel_crtc->base;
2682 struct intel_encoder *intel_encoder;
2683
5aa8a937
MR		 2684 if (crtc->primary->fb)
2685 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2686 crtc->primary->fb->base.id, crtc->x, crtc->y,
2687 crtc->primary->fb->width, crtc->primary->fb->height);
2688 else
2689 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2690 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2691 intel_encoder_info(m, intel_crtc, intel_encoder);
2692}
2693
2694static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2695{
2696 struct drm_display_mode *mode = panel->fixed_mode;
2697
2698 seq_printf(m, "\tfixed mode:\n");
2699 intel_seq_print_mode(m, 2, mode);
2700}
2701
2702static void intel_dp_info(struct seq_file *m,
2703 struct intel_connector *intel_connector)
2704{
2705 struct intel_encoder *intel_encoder = intel_connector->encoder;
2706 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2707
2708 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2709 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2710 "no");
2711 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2712 intel_panel_info(m, &intel_connector->panel);
2713}
2714
2715static void intel_hdmi_info(struct seq_file *m,
2716 struct intel_connector *intel_connector)
2717{
2718 struct intel_encoder *intel_encoder = intel_connector->encoder;
2719 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2720
2721 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2722 "no");
2723}
2724
2725static void intel_lvds_info(struct seq_file *m,
2726 struct intel_connector *intel_connector)
2727{
2728 intel_panel_info(m, &intel_connector->panel);
2729}
2730
2731static void intel_connector_info(struct seq_file *m,
2732 struct drm_connector *connector)
2733{
2734 struct intel_connector *intel_connector = to_intel_connector(connector);
2735 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2736 struct drm_display_mode *mode;
53f5e3ca
JB		 2737
2738 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2739 connector->base.id, connector->name,
53f5e3ca
JB		 2740 drm_get_connector_status_name(connector->status));
2741 if (connector->status == connector_status_connected) {
2742 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2743 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2744 connector->display_info.width_mm,
2745 connector->display_info.height_mm);
2746 seq_printf(m, "\tsubpixel order: %s\n",
2747 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2748 seq_printf(m, "\tCEA rev: %d\n",
2749 connector->display_info.cea_rev);
2750 }
36cd7444
DA		 2751 if (intel_encoder) {
2752 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2753 intel_encoder->type == INTEL_OUTPUT_EDP)
2754 intel_dp_info(m, intel_connector);
2755 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2756 intel_hdmi_info(m, intel_connector);
2757 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2758 intel_lvds_info(m, intel_connector);
2759 }
53f5e3ca 2760
f103fc7d
JB		 2761 seq_printf(m, "\tmodes:\n");
2762 list_for_each_entry(mode, &connector->modes, head)
2763 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2764}
2765
065f2ec2
CW		 2766static bool cursor_active(struct drm_device *dev, int pipe)
2767{
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 u32 state;
2770
2771 if (IS_845G(dev) || IS_I865G(dev))
2772 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2773 else
5efb3e28 2774 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2775
2776 return state;
2777}
2778
2779static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2780{
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 u32 pos;
2783
5efb3e28 2784 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2785
2786 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2787 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2788 *x = -*x;
2789
2790 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2791 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2792 *y = -*y;
2793
2794 return cursor_active(dev, pipe);
2795}
2796
53f5e3ca
JB		 2797static int i915_display_info(struct seq_file *m, void *unused)
2798{
9f25d007 2799 struct drm_info_node *node = m->private;
53f5e3ca 2800 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2801 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2802 struct intel_crtc *crtc;
53f5e3ca
JB		 2803 struct drm_connector *connector;
2804
b0e5ddf3 2805 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2806 drm_modeset_lock_all(dev);
2807 seq_printf(m, "CRTC info\n");
2808 seq_printf(m, "---------\n");
d3fcc808 2809 for_each_intel_crtc(dev, crtc) {
065f2ec2 2810 bool active;
f77076c9 2811 struct intel_crtc_state *pipe_config;
065f2ec2 2812 int x, y;
53f5e3ca 2813
f77076c9
ML		 2814 pipe_config = to_intel_crtc_state(crtc->base.state);
2815
57127efa 2816 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2817 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9
ML		 2818 yesno(pipe_config->base.active),
2819 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2820 if (pipe_config->base.active) {
065f2ec2
CW		 2821 intel_crtc_info(m, crtc);
2822
a23dc658 2823 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2824 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2825 yesno(crtc->cursor_base),
3dd512fb
MR		 2826 x, y, crtc->base.cursor->state->crtc_w,
2827 crtc->base.cursor->state->crtc_h,
57127efa 2828 crtc->cursor_addr, yesno(active));
a23dc658 2829 }
cace841c
DV		 2830
2831 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2832 yesno(!crtc->cpu_fifo_underrun_disabled),
2833 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2834 }
2835
2836 seq_printf(m, "\n");
2837 seq_printf(m, "Connector info\n");
2838 seq_printf(m, "--------------\n");
2839 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2840 intel_connector_info(m, connector);
2841 }
2842 drm_modeset_unlock_all(dev);
b0e5ddf3 2843 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2844
2845 return 0;
2846}
2847
e04934cf
BW		 2848static int i915_semaphore_status(struct seq_file *m, void *unused)
2849{
2850 struct drm_info_node *node = (struct drm_info_node *) m->private;
2851 struct drm_device *dev = node->minor->dev;
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853 struct intel_engine_cs *ring;
2854 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2855 int i, j, ret;
2856
2857 if (!i915_semaphore_is_enabled(dev)) {
2858 seq_puts(m, "Semaphores are disabled\n");
2859 return 0;
2860 }
2861
2862 ret = mutex_lock_interruptible(&dev->struct_mutex);
2863 if (ret)
2864 return ret;
03872064 2865 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2866
2867 if (IS_BROADWELL(dev)) {
2868 struct page *page;
2869 uint64_t *seqno;
2870
2871 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2872
2873 seqno = (uint64_t *)kmap_atomic(page);
2874 for_each_ring(ring, dev_priv, i) {
2875 uint64_t offset;
2876
2877 seq_printf(m, "%s\n", ring->name);
2878
2879 seq_puts(m, " Last signal:");
2880 for (j = 0; j < num_rings; j++) {
2881 offset = i * I915_NUM_RINGS + j;
2882 seq_printf(m, "0x%08llx (0x%02llx) ",
2883 seqno[offset], offset * 8);
2884 }
2885 seq_putc(m, '\n');
2886
2887 seq_puts(m, " Last wait: ");
2888 for (j = 0; j < num_rings; j++) {
2889 offset = i + (j * I915_NUM_RINGS);
2890 seq_printf(m, "0x%08llx (0x%02llx) ",
2891 seqno[offset], offset * 8);
2892 }
2893 seq_putc(m, '\n');
2894
2895 }
2896 kunmap_atomic(seqno);
2897 } else {
2898 seq_puts(m, " Last signal:");
2899 for_each_ring(ring, dev_priv, i)
2900 for (j = 0; j < num_rings; j++)
2901 seq_printf(m, "0x%08x\n",
2902 I915_READ(ring->semaphore.mbox.signal[j]));
2903 seq_putc(m, '\n');
2904 }
2905
2906 seq_puts(m, "\nSync seqno:\n");
2907 for_each_ring(ring, dev_priv, i) {
2908 for (j = 0; j < num_rings; j++) {
2909 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2910 }
2911 seq_putc(m, '\n');
2912 }
2913 seq_putc(m, '\n');
2914
03872064 2915 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2916 mutex_unlock(&dev->struct_mutex);
2917 return 0;
2918}
2919
728e29d7
DV		 2920static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2921{
2922 struct drm_info_node *node = (struct drm_info_node *) m->private;
2923 struct drm_device *dev = node->minor->dev;
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925 int i;
2926
2927 drm_modeset_lock_all(dev);
2928 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2929 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2930
2931 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2932 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2933 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2934 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2935 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2936 seq_printf(m, " dpll_md: 0x%08x\n",
2937 pll->config.hw_state.dpll_md);
2938 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2939 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2940 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2941 }
2942 drm_modeset_unlock_all(dev);
2943
2944 return 0;
2945}
2946
1ed1ef9d 2947static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2948{
2949 int i;
2950 int ret;
2951 struct drm_info_node *node = (struct drm_info_node *) m->private;
2952 struct drm_device *dev = node->minor->dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954
888b5995
AS		 2955 ret = mutex_lock_interruptible(&dev->struct_mutex);
2956 if (ret)
2957 return ret;
2958
2959 intel_runtime_pm_get(dev_priv);
2960
7225342a
MK		 2961 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2962 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2963 u32 addr, mask, value, read;
2964 bool ok;
888b5995 2965
7225342a
MK		 2966 addr = dev_priv->workarounds.reg[i].addr;
2967 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2968 value = dev_priv->workarounds.reg[i].value;
2969 read = I915_READ(addr);
2970 ok = (value & mask) == (read & mask);
2971 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2972 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2973 }
2974
2975 intel_runtime_pm_put(dev_priv);
2976 mutex_unlock(&dev->struct_mutex);
2977
2978 return 0;
2979}
2980
c5511e44
DL		 2981static int i915_ddb_info(struct seq_file *m, void *unused)
2982{
2983 struct drm_info_node *node = m->private;
2984 struct drm_device *dev = node->minor->dev;
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 struct skl_ddb_allocation *ddb;
2987 struct skl_ddb_entry *entry;
2988 enum pipe pipe;
2989 int plane;
2990
2fcffe19
DL		 2991 if (INTEL_INFO(dev)->gen < 9)
2992 return 0;
2993
c5511e44
DL		 2994 drm_modeset_lock_all(dev);
2995
2996 ddb = &dev_priv->wm.skl_hw.ddb;
2997
2998 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2999
3000 for_each_pipe(dev_priv, pipe) {
3001 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3002
dd740780 3003 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3004 entry = &ddb->plane[pipe][plane];
3005 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3006 entry->start, entry->end,
3007 skl_ddb_entry_size(entry));
3008 }
3009
3010 entry = &ddb->cursor[pipe];
3011 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3012 entry->end, skl_ddb_entry_size(entry));
3013 }
3014
3015 drm_modeset_unlock_all(dev);
3016
3017 return 0;
3018}
3019
a54746e3
VK		 3020static void drrs_status_per_crtc(struct seq_file *m,
3021 struct drm_device *dev, struct intel_crtc *intel_crtc)
3022{
3023 struct intel_encoder *intel_encoder;
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 struct i915_drrs *drrs = &dev_priv->drrs;
3026 int vrefresh = 0;
3027
3028 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3029 /* Encoder connected on this CRTC */
3030 switch (intel_encoder->type) {
3031 case INTEL_OUTPUT_EDP:
3032 seq_puts(m, "eDP:\n");
3033 break;
3034 case INTEL_OUTPUT_DSI:
3035 seq_puts(m, "DSI:\n");
3036 break;
3037 case INTEL_OUTPUT_HDMI:
3038 seq_puts(m, "HDMI:\n");
3039 break;
3040 case INTEL_OUTPUT_DISPLAYPORT:
3041 seq_puts(m, "DP:\n");
3042 break;
3043 default:
3044 seq_printf(m, "Other encoder (id=%d).\n",
3045 intel_encoder->type);
3046 return;
3047 }
3048 }
3049
3050 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3051 seq_puts(m, "\tVBT: DRRS_type: Static");
3052 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3053 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3054 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3055 seq_puts(m, "\tVBT: DRRS_type: None");
3056 else
3057 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3058
3059 seq_puts(m, "\n\n");
3060
f77076c9 3061 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3062 struct intel_panel *panel;
3063
3064 mutex_lock(&drrs->mutex);
3065 /* DRRS Supported */
3066 seq_puts(m, "\tDRRS Supported: Yes\n");
3067
3068 /* disable_drrs() will make drrs->dp NULL */
3069 if (!drrs->dp) {
3070 seq_puts(m, "Idleness DRRS: Disabled");
3071 mutex_unlock(&drrs->mutex);
3072 return;
3073 }
3074
3075 panel = &drrs->dp->attached_connector->panel;
3076 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3077 drrs->busy_frontbuffer_bits);
3078
3079 seq_puts(m, "\n\t\t");
3080 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3081 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3082 vrefresh = panel->fixed_mode->vrefresh;
3083 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3084 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3085 vrefresh = panel->downclock_mode->vrefresh;
3086 } else {
3087 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3088 drrs->refresh_rate_type);
3089 mutex_unlock(&drrs->mutex);
3090 return;
3091 }
3092 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3093
3094 seq_puts(m, "\n\t\t");
3095 mutex_unlock(&drrs->mutex);
3096 } else {
3097 /* DRRS not supported. Print the VBT parameter*/
3098 seq_puts(m, "\tDRRS Supported : No");
3099 }
3100 seq_puts(m, "\n");
3101}
3102
3103static int i915_drrs_status(struct seq_file *m, void *unused)
3104{
3105 struct drm_info_node *node = m->private;
3106 struct drm_device *dev = node->minor->dev;
3107 struct intel_crtc *intel_crtc;
3108 int active_crtc_cnt = 0;
3109
3110 for_each_intel_crtc(dev, intel_crtc) {
3111 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3112
f77076c9 3113 if (intel_crtc->base.state->active) {
a54746e3
VK		 3114 active_crtc_cnt++;
3115 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3116
3117 drrs_status_per_crtc(m, dev, intel_crtc);
3118 }
3119
3120 drm_modeset_unlock(&intel_crtc->base.mutex);
3121 }
3122
3123 if (!active_crtc_cnt)
3124 seq_puts(m, "No active crtc found\n");
3125
3126 return 0;
3127}
3128
07144428
DL		 3129struct pipe_crc_info {
3130 const char *name;
3131 struct drm_device *dev;
3132 enum pipe pipe;
3133};
3134
11bed958
DA		 3135static int i915_dp_mst_info(struct seq_file *m, void *unused)
3136{
3137 struct drm_info_node *node = (struct drm_info_node *) m->private;
3138 struct drm_device *dev = node->minor->dev;
3139 struct drm_encoder *encoder;
3140 struct intel_encoder *intel_encoder;
3141 struct intel_digital_port *intel_dig_port;
3142 drm_modeset_lock_all(dev);
3143 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3144 intel_encoder = to_intel_encoder(encoder);
3145 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3146 continue;
3147 intel_dig_port = enc_to_dig_port(encoder);
3148 if (!intel_dig_port->dp.can_mst)
3149 continue;
3150
3151 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3152 }
3153 drm_modeset_unlock_all(dev);
3154 return 0;
3155}
3156
07144428
DL		 3157static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3158{
be5c7a90
DL		 3159 struct pipe_crc_info *info = inode->i_private;
3160 struct drm_i915_private *dev_priv = info->dev->dev_private;
3161 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3162
7eb1c496
DV		 3163 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3164 return -ENODEV;
3165
d538bbdf
DL		 3166 spin_lock_irq(&pipe_crc->lock);
3167
3168 if (pipe_crc->opened) {
3169 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3170 return -EBUSY; /* already open */
3171 }
3172
d538bbdf 3173 pipe_crc->opened = true;
07144428
DL		 3174 filep->private_data = inode->i_private;
3175
d538bbdf
DL		 3176 spin_unlock_irq(&pipe_crc->lock);
3177
07144428
DL		 3178 return 0;
3179}
3180
3181static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3182{
be5c7a90
DL		 3183 struct pipe_crc_info *info = inode->i_private;
3184 struct drm_i915_private *dev_priv = info->dev->dev_private;
3185 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3186
d538bbdf
DL		 3187 spin_lock_irq(&pipe_crc->lock);
3188 pipe_crc->opened = false;
3189 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3190
07144428
DL		 3191 return 0;
3192}
3193
3194/* (6 fields, 8 chars each, space separated (5) + '\n') */
3195#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3196/* account for \'0' */
3197#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3198
3199static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3200{
d538bbdf
DL		 3201 assert_spin_locked(&pipe_crc->lock);
3202 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3203 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3204}
3205
3206static ssize_t
3207i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3208 loff_t *pos)
3209{
3210 struct pipe_crc_info *info = filep->private_data;
3211 struct drm_device *dev = info->dev;
3212 struct drm_i915_private *dev_priv = dev->dev_private;
3213 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3214 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3215 int n_entries;
07144428
DL		 3216 ssize_t bytes_read;
3217
3218 /*
3219 * Don't allow user space to provide buffers not big enough to hold
3220 * a line of data.
3221 */
3222 if (count < PIPE_CRC_LINE_LEN)
3223 return -EINVAL;
3224
3225 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3226 return 0;
07144428
DL		 3227
3228 /* nothing to read */
d538bbdf 3229 spin_lock_irq(&pipe_crc->lock);
07144428 3230 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3231 int ret;
3232
3233 if (filep->f_flags & O_NONBLOCK) {
3234 spin_unlock_irq(&pipe_crc->lock);
07144428 3235 return -EAGAIN;
d538bbdf 3236 }
07144428 3237
d538bbdf
DL		 3238 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3239 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3240 if (ret) {
3241 spin_unlock_irq(&pipe_crc->lock);
3242 return ret;
3243 }
8bf1e9f1
SH		 3244 }
3245
07144428 3246 /* We now have one or more entries to read */
9ad6d99f 3247 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3248
07144428 3249 bytes_read = 0;
9ad6d99f
VS		 3250 while (n_entries > 0) {
3251 struct intel_pipe_crc_entry *entry =
3252 &pipe_crc->entries[pipe_crc->tail];
07144428 3253 int ret;
8bf1e9f1 3254
9ad6d99f
VS		 3255 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3256 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3257 break;
3258
3259 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3260 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3261
07144428
DL		 3262 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3263 "%8u %8x %8x %8x %8x %8x\n",
3264 entry->frame, entry->crc[0],
3265 entry->crc[1], entry->crc[2],
3266 entry->crc[3], entry->crc[4]);
3267
9ad6d99f
VS		 3268 spin_unlock_irq(&pipe_crc->lock);
3269
3270 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3271 if (ret == PIPE_CRC_LINE_LEN)
3272 return -EFAULT;
b2c88f5b 3273
9ad6d99f
VS		 3274 user_buf += PIPE_CRC_LINE_LEN;
3275 n_entries--;
3276
3277 spin_lock_irq(&pipe_crc->lock);
3278 }
8bf1e9f1 3279
d538bbdf
DL		 3280 spin_unlock_irq(&pipe_crc->lock);
3281
07144428
DL		 3282 return bytes_read;
3283}
3284
3285static const struct file_operations i915_pipe_crc_fops = {
3286 .owner = THIS_MODULE,
3287 .open = i915_pipe_crc_open,
3288 .read = i915_pipe_crc_read,
3289 .release = i915_pipe_crc_release,
3290};
3291
3292static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3293 {
3294 .name = "i915_pipe_A_crc",
3295 .pipe = PIPE_A,
3296 },
3297 {
3298 .name = "i915_pipe_B_crc",
3299 .pipe = PIPE_B,
3300 },
3301 {
3302 .name = "i915_pipe_C_crc",
3303 .pipe = PIPE_C,
3304 },
3305};
3306
3307static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3308 enum pipe pipe)
3309{
3310 struct drm_device *dev = minor->dev;
3311 struct dentry *ent;
3312 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3313
3314 info->dev = dev;
3315 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3316 &i915_pipe_crc_fops);
f3c5fe97
WY		 3317 if (!ent)
3318 return -ENOMEM;
07144428
DL		 3319
3320 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3321}
3322
e8dfcf78 3323static const char * const pipe_crc_sources[] = {
926321d5
DV		 3324 "none",
3325 "plane1",
3326 "plane2",
3327 "pf",
5b3a856b 3328 "pipe",
3d099a05
DV		 3329 "TV",
3330 "DP-B",
3331 "DP-C",
3332 "DP-D",
46a19188 3333 "auto",
926321d5
DV		 3334};
3335
3336static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3337{
3338 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3339 return pipe_crc_sources[source];
3340}
3341
bd9db02f 3342static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3343{
3344 struct drm_device *dev = m->private;
3345 struct drm_i915_private *dev_priv = dev->dev_private;
3346 int i;
3347
3348 for (i = 0; i < I915_MAX_PIPES; i++)
3349 seq_printf(m, "%c %s\n", pipe_name(i),
3350 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3351
3352 return 0;
3353}
3354
bd9db02f 3355static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3356{
3357 struct drm_device *dev = inode->i_private;
3358
bd9db02f 3359 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3360}
3361
46a19188 3362static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3363 uint32_t *val)
3364{
46a19188
DV		 3365 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3366 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3367
3368 switch (*source) {
52f843f6
DV		 3369 case INTEL_PIPE_CRC_SOURCE_PIPE:
3370 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3371 break;
3372 case INTEL_PIPE_CRC_SOURCE_NONE:
3373 *val = 0;
3374 break;
3375 default:
3376 return -EINVAL;
3377 }
3378
3379 return 0;
3380}
3381
46a19188
DV		 3382static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3383 enum intel_pipe_crc_source *source)
3384{
3385 struct intel_encoder *encoder;
3386 struct intel_crtc *crtc;
26756809 3387 struct intel_digital_port *dig_port;
46a19188
DV		 3388 int ret = 0;
3389
3390 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3391
6e9f798d 3392 drm_modeset_lock_all(dev);
b2784e15 3393 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3394 if (!encoder->base.crtc)
3395 continue;
3396
3397 crtc = to_intel_crtc(encoder->base.crtc);
3398
3399 if (crtc->pipe != pipe)
3400 continue;
3401
3402 switch (encoder->type) {
3403 case INTEL_OUTPUT_TVOUT:
3404 *source = INTEL_PIPE_CRC_SOURCE_TV;
3405 break;
3406 case INTEL_OUTPUT_DISPLAYPORT:
3407 case INTEL_OUTPUT_EDP:
26756809
DV		 3408 dig_port = enc_to_dig_port(&encoder->base);
3409 switch (dig_port->port) {
3410 case PORT_B:
3411 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3412 break;
3413 case PORT_C:
3414 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3415 break;
3416 case PORT_D:
3417 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3418 break;
3419 default:
3420 WARN(1, "nonexisting DP port %c\n",
3421 port_name(dig_port->port));
3422 break;
3423 }
46a19188 3424 break;
6847d71b
PZ		 3425 default:
3426 break;
46a19188
DV		 3427 }
3428 }
6e9f798d 3429 drm_modeset_unlock_all(dev);
46a19188
DV		 3430
3431 return ret;
3432}
3433
3434static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3435 enum pipe pipe,
3436 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3437 uint32_t *val)
3438{
8d2f24ca
DV		 3439 struct drm_i915_private *dev_priv = dev->dev_private;
3440 bool need_stable_symbols = false;
3441
46a19188
DV		 3442 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3443 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3444 if (ret)
3445 return ret;
3446 }
3447
3448 switch (*source) {
7ac0129b
DV		 3449 case INTEL_PIPE_CRC_SOURCE_PIPE:
3450 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3451 break;
3452 case INTEL_PIPE_CRC_SOURCE_DP_B:
3453 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3454 need_stable_symbols = true;
7ac0129b
DV		 3455 break;
3456 case INTEL_PIPE_CRC_SOURCE_DP_C:
3457 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3458 need_stable_symbols = true;
7ac0129b 3459 break;
2be57922
VS		 3460 case INTEL_PIPE_CRC_SOURCE_DP_D:
3461 if (!IS_CHERRYVIEW(dev))
3462 return -EINVAL;
3463 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3464 need_stable_symbols = true;
3465 break;
7ac0129b
DV		 3466 case INTEL_PIPE_CRC_SOURCE_NONE:
3467 *val = 0;
3468 break;
3469 default:
3470 return -EINVAL;
3471 }
3472
8d2f24ca
DV		 3473 /*
3474 * When the pipe CRC tap point is after the transcoders we need
3475 * to tweak symbol-level features to produce a deterministic series of
3476 * symbols for a given frame. We need to reset those features only once
3477 * a frame (instead of every nth symbol):
3478 * - DC-balance: used to ensure a better clock recovery from the data
3479 * link (SDVO)
3480 * - DisplayPort scrambling: used for EMI reduction
3481 */
3482 if (need_stable_symbols) {
3483 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3484
8d2f24ca 3485 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3486 switch (pipe) {
3487 case PIPE_A:
8d2f24ca 3488 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3489 break;
3490 case PIPE_B:
8d2f24ca 3491 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3492 break;
3493 case PIPE_C:
3494 tmp |= PIPE_C_SCRAMBLE_RESET;
3495 break;
3496 default:
3497 return -EINVAL;
3498 }
8d2f24ca
DV		 3499 I915_WRITE(PORT_DFT2_G4X, tmp);
3500 }
3501
7ac0129b
DV		 3502 return 0;
3503}
3504
4b79ebf7 3505static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3506 enum pipe pipe,
3507 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3508 uint32_t *val)
3509{
84093603
DV		 3510 struct drm_i915_private *dev_priv = dev->dev_private;
3511 bool need_stable_symbols = false;
3512
46a19188
DV		 3513 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3514 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3515 if (ret)
3516 return ret;
3517 }
3518
3519 switch (*source) {
4b79ebf7
DV		 3520 case INTEL_PIPE_CRC_SOURCE_PIPE:
3521 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3522 break;
3523 case INTEL_PIPE_CRC_SOURCE_TV:
3524 if (!SUPPORTS_TV(dev))
3525 return -EINVAL;
3526 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3527 break;
3528 case INTEL_PIPE_CRC_SOURCE_DP_B:
3529 if (!IS_G4X(dev))
3530 return -EINVAL;
3531 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3532 need_stable_symbols = true;
4b79ebf7
DV		 3533 break;
3534 case INTEL_PIPE_CRC_SOURCE_DP_C:
3535 if (!IS_G4X(dev))
3536 return -EINVAL;
3537 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3538 need_stable_symbols = true;
4b79ebf7
DV		 3539 break;
3540 case INTEL_PIPE_CRC_SOURCE_DP_D:
3541 if (!IS_G4X(dev))
3542 return -EINVAL;
3543 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3544 need_stable_symbols = true;
4b79ebf7
DV		 3545 break;
3546 case INTEL_PIPE_CRC_SOURCE_NONE:
3547 *val = 0;
3548 break;
3549 default:
3550 return -EINVAL;
3551 }
3552
84093603
DV		 3553 /*
3554 * When the pipe CRC tap point is after the transcoders we need
3555 * to tweak symbol-level features to produce a deterministic series of
3556 * symbols for a given frame. We need to reset those features only once
3557 * a frame (instead of every nth symbol):
3558 * - DC-balance: used to ensure a better clock recovery from the data
3559 * link (SDVO)
3560 * - DisplayPort scrambling: used for EMI reduction
3561 */
3562 if (need_stable_symbols) {
3563 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3564
3565 WARN_ON(!IS_G4X(dev));
3566
3567 I915_WRITE(PORT_DFT_I9XX,
3568 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3569
3570 if (pipe == PIPE_A)
3571 tmp |= PIPE_A_SCRAMBLE_RESET;
3572 else
3573 tmp |= PIPE_B_SCRAMBLE_RESET;
3574
3575 I915_WRITE(PORT_DFT2_G4X, tmp);
3576 }
3577
4b79ebf7
DV		 3578 return 0;
3579}
3580
8d2f24ca
DV		 3581static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3582 enum pipe pipe)
3583{
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3586
eb736679
VS		 3587 switch (pipe) {
3588 case PIPE_A:
8d2f24ca 3589 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3590 break;
3591 case PIPE_B:
8d2f24ca 3592 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3593 break;
3594 case PIPE_C:
3595 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3596 break;
3597 default:
3598 return;
3599 }
8d2f24ca
DV		 3600 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3601 tmp &= ~DC_BALANCE_RESET_VLV;
3602 I915_WRITE(PORT_DFT2_G4X, tmp);
3603
3604}
3605
84093603
DV		 3606static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3607 enum pipe pipe)
3608{
3609 struct drm_i915_private *dev_priv = dev->dev_private;
3610 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3611
3612 if (pipe == PIPE_A)
3613 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3614 else
3615 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3616 I915_WRITE(PORT_DFT2_G4X, tmp);
3617
3618 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3619 I915_WRITE(PORT_DFT_I9XX,
3620 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3621 }
3622}
3623
46a19188 3624static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3625 uint32_t *val)
3626{
46a19188
DV		 3627 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3628 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3629
3630 switch (*source) {
5b3a856b
DV		 3631 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3632 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3633 break;
3634 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3635 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3636 break;
5b3a856b
DV		 3637 case INTEL_PIPE_CRC_SOURCE_PIPE:
3638 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3639 break;
3d099a05 3640 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3641 *val = 0;
3642 break;
3d099a05
DV		 3643 default:
3644 return -EINVAL;
5b3a856b
DV		 3645 }
3646
3647 return 0;
3648}
3649
c4e2d043 3650static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3651{
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653 struct intel_crtc *crtc =
3654 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3655 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3656 struct drm_atomic_state *state;
3657 int ret = 0;
fabf6e51
DV		 3658
3659 drm_modeset_lock_all(dev);
c4e2d043
ML		 3660 state = drm_atomic_state_alloc(dev);
3661 if (!state) {
3662 ret = -ENOMEM;
3663 goto out;
fabf6e51 3664 }
fabf6e51 3665
c4e2d043
ML		 3666 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3667 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3668 if (IS_ERR(pipe_config)) {
3669 ret = PTR_ERR(pipe_config);
3670 goto out;
3671 }
fabf6e51 3672
c4e2d043
ML		 3673 pipe_config->pch_pfit.force_thru = enable;
3674 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3675 pipe_config->pch_pfit.enabled != enable)
3676 pipe_config->base.connectors_changed = true;
1b509259 3677
c4e2d043
ML		 3678 ret = drm_atomic_commit(state);
3679out:
fabf6e51 3680 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3681 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3682 if (ret)
3683 drm_atomic_state_free(state);
fabf6e51
DV		 3684}
3685
3686static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3687 enum pipe pipe,
3688 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3689 uint32_t *val)
3690{
46a19188
DV		 3691 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3692 *source = INTEL_PIPE_CRC_SOURCE_PF;
3693
3694 switch (*source) {
5b3a856b
DV		 3695 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3696 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3697 break;
3698 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3699 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3700 break;
3701 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 3702 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3703 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 3704
5b3a856b
DV		 3705 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3706 break;
3d099a05 3707 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3708 *val = 0;
3709 break;
3d099a05
DV		 3710 default:
3711 return -EINVAL;
5b3a856b
DV		 3712 }
3713
3714 return 0;
3715}
3716
926321d5
DV		 3717static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3718 enum intel_pipe_crc_source source)
3719{
3720 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3721 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3722 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3723 pipe));
432f3342 3724 u32 val = 0; /* shut up gcc */
5b3a856b 3725 int ret;
926321d5 3726
cc3da175
DL		 3727 if (pipe_crc->source == source)
3728 return 0;
3729
ae676fcd
DL		 3730 /* forbid changing the source without going back to 'none' */
3731 if (pipe_crc->source && source)
3732 return -EINVAL;
3733
9d8b0588
DV		 3734 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3735 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3736 return -EIO;
3737 }
3738
52f843f6 3739 if (IS_GEN2(dev))
46a19188 3740 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3741 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3742 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3743 else if (IS_VALLEYVIEW(dev))
fabf6e51 3744 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3745 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3746 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3747 else
fabf6e51 3748 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3749
3750 if (ret != 0)
3751 return ret;
3752
4b584369
DL		 3753 /* none -> real source transition */
3754 if (source) {
4252fbc3
VS		 3755 struct intel_pipe_crc_entry *entries;
3756
7cd6ccff
DL		 3757 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3758 pipe_name(pipe), pipe_crc_source_name(source));
3759
3cf54b34
VS		 3760 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3761 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3762 GFP_KERNEL);
3763 if (!entries)
e5f75aca
DL		 3764 return -ENOMEM;
3765
8c740dce
PZ		 3766 /*
3767 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3768 * enabled and disabled dynamically based on package C states,
3769 * user space can't make reliable use of the CRCs, so let's just
3770 * completely disable it.
3771 */
3772 hsw_disable_ips(crtc);
3773
d538bbdf 3774 spin_lock_irq(&pipe_crc->lock);
64387b61 3775 kfree(pipe_crc->entries);
4252fbc3 3776 pipe_crc->entries = entries;
d538bbdf
DL		 3777 pipe_crc->head = 0;
3778 pipe_crc->tail = 0;
3779 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3780 }
3781
cc3da175 3782 pipe_crc->source = source;
926321d5 3783
926321d5
DV		 3784 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3785 POSTING_READ(PIPE_CRC_CTL(pipe));
3786
e5f75aca
DL		 3787 /* real source -> none transition */
3788 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3789 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3790 struct intel_crtc *crtc =
3791 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3792
7cd6ccff
DL		 3793 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3794 pipe_name(pipe));
3795
a33d7105 3796 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 3797 if (crtc->base.state->active)
a33d7105
DV		 3798 intel_wait_for_vblank(dev, pipe);
3799 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3800
d538bbdf
DL		 3801 spin_lock_irq(&pipe_crc->lock);
3802 entries = pipe_crc->entries;
e5f75aca 3803 pipe_crc->entries = NULL;
9ad6d99f
VS		 3804 pipe_crc->head = 0;
3805 pipe_crc->tail = 0;
d538bbdf
DL		 3806 spin_unlock_irq(&pipe_crc->lock);
3807
3808 kfree(entries);
84093603
DV		 3809
3810 if (IS_G4X(dev))
3811 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3812 else if (IS_VALLEYVIEW(dev))
3813 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 3814 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3815 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 3816
3817 hsw_enable_ips(crtc);
e5f75aca
DL		 3818 }
3819
926321d5
DV		 3820 return 0;
3821}
3822
3823/*
3824 * Parse pipe CRC command strings:
b94dec87
DL		 3825 * command: wsp* object wsp+ name wsp+ source wsp*
3826 * object: 'pipe'
3827 * name: (A | B | C)
926321d5
DV		 3828 * source: (none | plane1 | plane2 | pf)
3829 * wsp: (#0x20 | #0x9 | #0xA)+
3830 *
3831 * eg.:
b94dec87
DL		 3832 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3833 * "pipe A none" -> Stop CRC
926321d5 3834 */
bd9db02f 3835static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3836{
3837 int n_words = 0;
3838
3839 while (*buf) {
3840 char *end;
3841
3842 /* skip leading white space */
3843 buf = skip_spaces(buf);
3844 if (!*buf)
3845 break; /* end of buffer */
3846
3847 /* find end of word */
3848 for (end = buf; *end && !isspace(*end); end++)
3849 ;
3850
3851 if (n_words == max_words) {
3852 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3853 max_words);
3854 return -EINVAL; /* ran out of words[] before bytes */
3855 }
3856
3857 if (*end)
3858 *end++ = '\0';
3859 words[n_words++] = buf;
3860 buf = end;
3861 }
3862
3863 return n_words;
3864}
3865
b94dec87
DL		 3866enum intel_pipe_crc_object {
3867 PIPE_CRC_OBJECT_PIPE,
3868};
3869
e8dfcf78 3870static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3871 "pipe",
3872};
3873
3874static int
bd9db02f 3875display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3876{
3877 int i;
3878
3879 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3880 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3881 *o = i;
b94dec87
DL		 3882 return 0;
3883 }
3884
3885 return -EINVAL;
3886}
3887
bd9db02f 3888static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3889{
3890 const char name = buf[0];
3891
3892 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3893 return -EINVAL;
3894
3895 *pipe = name - 'A';
3896
3897 return 0;
3898}
3899
3900static int
bd9db02f 3901display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3902{
3903 int i;
3904
3905 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3906 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3907 *s = i;
926321d5
DV		 3908 return 0;
3909 }
3910
3911 return -EINVAL;
3912}
3913
bd9db02f 3914static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3915{
b94dec87 3916#define N_WORDS 3
926321d5 3917 int n_words;
b94dec87 3918 char *words[N_WORDS];
926321d5 3919 enum pipe pipe;
b94dec87 3920 enum intel_pipe_crc_object object;
926321d5
DV		 3921 enum intel_pipe_crc_source source;
3922
bd9db02f 3923 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3924 if (n_words != N_WORDS) {
3925 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3926 N_WORDS);
3927 return -EINVAL;
3928 }
3929
bd9db02f 3930 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3931 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3932 return -EINVAL;
3933 }
3934
bd9db02f 3935 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3936 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3937 return -EINVAL;
3938 }
3939
bd9db02f 3940 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3941 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3942 return -EINVAL;
3943 }
3944
3945 return pipe_crc_set_source(dev, pipe, source);
3946}
3947
bd9db02f
DL		 3948static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3949 size_t len, loff_t *offp)
926321d5
DV		 3950{
3951 struct seq_file *m = file->private_data;
3952 struct drm_device *dev = m->private;
3953 char *tmpbuf;
3954 int ret;
3955
3956 if (len == 0)
3957 return 0;
3958
3959 if (len > PAGE_SIZE - 1) {
3960 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3961 PAGE_SIZE);
3962 return -E2BIG;
3963 }
3964
3965 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3966 if (!tmpbuf)
3967 return -ENOMEM;
3968
3969 if (copy_from_user(tmpbuf, ubuf, len)) {
3970 ret = -EFAULT;
3971 goto out;
3972 }
3973 tmpbuf[len] = '\0';
3974
bd9db02f 3975 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3976
3977out:
3978 kfree(tmpbuf);
3979 if (ret < 0)
3980 return ret;
3981
3982 *offp += len;
3983 return len;
3984}
3985
bd9db02f 3986static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3987 .owner = THIS_MODULE,
bd9db02f 3988 .open = display_crc_ctl_open,
926321d5
DV		 3989 .read = seq_read,
3990 .llseek = seq_lseek,
3991 .release = single_release,
bd9db02f 3992 .write = display_crc_ctl_write
926321d5
DV		 3993};
3994
eb3394fa
TP		 3995static ssize_t i915_displayport_test_active_write(struct file *file,
3996 const char __user *ubuf,
3997 size_t len, loff_t *offp)
3998{
3999 char *input_buffer;
4000 int status = 0;
eb3394fa
TP		 4001 struct drm_device *dev;
4002 struct drm_connector *connector;
4003 struct list_head *connector_list;
4004 struct intel_dp *intel_dp;
4005 int val = 0;
4006
9aaffa34 4007 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4008
eb3394fa
TP		 4009 connector_list = &dev->mode_config.connector_list;
4010
4011 if (len == 0)
4012 return 0;
4013
4014 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4015 if (!input_buffer)
4016 return -ENOMEM;
4017
4018 if (copy_from_user(input_buffer, ubuf, len)) {
4019 status = -EFAULT;
4020 goto out;
4021 }
4022
4023 input_buffer[len] = '\0';
4024 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4025
4026 list_for_each_entry(connector, connector_list, head) {
4027
4028 if (connector->connector_type !=
4029 DRM_MODE_CONNECTOR_DisplayPort)
4030 continue;
4031
b8bb08ec 4032 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4033 connector->encoder != NULL) {
4034 intel_dp = enc_to_intel_dp(connector->encoder);
4035 status = kstrtoint(input_buffer, 10, &val);
4036 if (status < 0)
4037 goto out;
4038 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4039 /* To prevent erroneous activation of the compliance
4040 * testing code, only accept an actual value of 1 here
4041 */
4042 if (val == 1)
4043 intel_dp->compliance_test_active = 1;
4044 else
4045 intel_dp->compliance_test_active = 0;
4046 }
4047 }
4048out:
4049 kfree(input_buffer);
4050 if (status < 0)
4051 return status;
4052
4053 *offp += len;
4054 return len;
4055}
4056
4057static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4058{
4059 struct drm_device *dev = m->private;
4060 struct drm_connector *connector;
4061 struct list_head *connector_list = &dev->mode_config.connector_list;
4062 struct intel_dp *intel_dp;
4063
eb3394fa
TP		 4064 list_for_each_entry(connector, connector_list, head) {
4065
4066 if (connector->connector_type !=
4067 DRM_MODE_CONNECTOR_DisplayPort)
4068 continue;
4069
4070 if (connector->status == connector_status_connected &&
4071 connector->encoder != NULL) {
4072 intel_dp = enc_to_intel_dp(connector->encoder);
4073 if (intel_dp->compliance_test_active)
4074 seq_puts(m, "1");
4075 else
4076 seq_puts(m, "0");
4077 } else
4078 seq_puts(m, "0");
4079 }
4080
4081 return 0;
4082}
4083
4084static int i915_displayport_test_active_open(struct inode *inode,
4085 struct file *file)
4086{
4087 struct drm_device *dev = inode->i_private;
4088
4089 return single_open(file, i915_displayport_test_active_show, dev);
4090}
4091
4092static const struct file_operations i915_displayport_test_active_fops = {
4093 .owner = THIS_MODULE,
4094 .open = i915_displayport_test_active_open,
4095 .read = seq_read,
4096 .llseek = seq_lseek,
4097 .release = single_release,
4098 .write = i915_displayport_test_active_write
4099};
4100
4101static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4102{
4103 struct drm_device *dev = m->private;
4104 struct drm_connector *connector;
4105 struct list_head *connector_list = &dev->mode_config.connector_list;
4106 struct intel_dp *intel_dp;
4107
eb3394fa
TP		 4108 list_for_each_entry(connector, connector_list, head) {
4109
4110 if (connector->connector_type !=
4111 DRM_MODE_CONNECTOR_DisplayPort)
4112 continue;
4113
4114 if (connector->status == connector_status_connected &&
4115 connector->encoder != NULL) {
4116 intel_dp = enc_to_intel_dp(connector->encoder);
4117 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4118 } else
4119 seq_puts(m, "0");
4120 }
4121
4122 return 0;
4123}
4124static int i915_displayport_test_data_open(struct inode *inode,
4125 struct file *file)
4126{
4127 struct drm_device *dev = inode->i_private;
4128
4129 return single_open(file, i915_displayport_test_data_show, dev);
4130}
4131
4132static const struct file_operations i915_displayport_test_data_fops = {
4133 .owner = THIS_MODULE,
4134 .open = i915_displayport_test_data_open,
4135 .read = seq_read,
4136 .llseek = seq_lseek,
4137 .release = single_release
4138};
4139
4140static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4141{
4142 struct drm_device *dev = m->private;
4143 struct drm_connector *connector;
4144 struct list_head *connector_list = &dev->mode_config.connector_list;
4145 struct intel_dp *intel_dp;
4146
eb3394fa
TP		 4147 list_for_each_entry(connector, connector_list, head) {
4148
4149 if (connector->connector_type !=
4150 DRM_MODE_CONNECTOR_DisplayPort)
4151 continue;
4152
4153 if (connector->status == connector_status_connected &&
4154 connector->encoder != NULL) {
4155 intel_dp = enc_to_intel_dp(connector->encoder);
4156 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4157 } else
4158 seq_puts(m, "0");
4159 }
4160
4161 return 0;
4162}
4163
4164static int i915_displayport_test_type_open(struct inode *inode,
4165 struct file *file)
4166{
4167 struct drm_device *dev = inode->i_private;
4168
4169 return single_open(file, i915_displayport_test_type_show, dev);
4170}
4171
4172static const struct file_operations i915_displayport_test_type_fops = {
4173 .owner = THIS_MODULE,
4174 .open = i915_displayport_test_type_open,
4175 .read = seq_read,
4176 .llseek = seq_lseek,
4177 .release = single_release
4178};
4179
97e94b22 4180static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4181{
4182 struct drm_device *dev = m->private;
369a1342 4183 int level;
de38b95c
VS		 4184 int num_levels;
4185
4186 if (IS_CHERRYVIEW(dev))
4187 num_levels = 3;
4188 else if (IS_VALLEYVIEW(dev))
4189 num_levels = 1;
4190 else
4191 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4192
4193 drm_modeset_lock_all(dev);
4194
4195 for (level = 0; level < num_levels; level++) {
4196 unsigned int latency = wm[level];
4197
97e94b22
DL		 4198 /*
4199 * - WM1+ latency values in 0.5us units
de38b95c 4200 * - latencies are in us on gen9/vlv/chv
97e94b22 4201 */
de38b95c 4202 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
97e94b22
DL		 4203 latency *= 10;
4204 else if (level > 0)
369a1342
VS		 4205 latency *= 5;
4206
4207 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4208 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4209 }
4210
4211 drm_modeset_unlock_all(dev);
4212}
4213
4214static int pri_wm_latency_show(struct seq_file *m, void *data)
4215{
4216 struct drm_device *dev = m->private;
97e94b22
DL		 4217 struct drm_i915_private *dev_priv = dev->dev_private;
4218 const uint16_t *latencies;
4219
4220 if (INTEL_INFO(dev)->gen >= 9)
4221 latencies = dev_priv->wm.skl_latency;
4222 else
4223 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4224
97e94b22 4225 wm_latency_show(m, latencies);
369a1342
VS		 4226
4227 return 0;
4228}
4229
4230static int spr_wm_latency_show(struct seq_file *m, void *data)
4231{
4232 struct drm_device *dev = m->private;
97e94b22
DL		 4233 struct drm_i915_private *dev_priv = dev->dev_private;
4234 const uint16_t *latencies;
4235
4236 if (INTEL_INFO(dev)->gen >= 9)
4237 latencies = dev_priv->wm.skl_latency;
4238 else
4239 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4240
97e94b22 4241 wm_latency_show(m, latencies);
369a1342
VS		 4242
4243 return 0;
4244}
4245
4246static int cur_wm_latency_show(struct seq_file *m, void *data)
4247{
4248 struct drm_device *dev = m->private;
97e94b22
DL		 4249 struct drm_i915_private *dev_priv = dev->dev_private;
4250 const uint16_t *latencies;
4251
4252 if (INTEL_INFO(dev)->gen >= 9)
4253 latencies = dev_priv->wm.skl_latency;
4254 else
4255 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4256
97e94b22 4257 wm_latency_show(m, latencies);
369a1342
VS		 4258
4259 return 0;
4260}
4261
4262static int pri_wm_latency_open(struct inode *inode, struct file *file)
4263{
4264 struct drm_device *dev = inode->i_private;
4265
de38b95c 4266 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4267 return -ENODEV;
4268
4269 return single_open(file, pri_wm_latency_show, dev);
4270}
4271
4272static int spr_wm_latency_open(struct inode *inode, struct file *file)
4273{
4274 struct drm_device *dev = inode->i_private;
4275
9ad0257c 4276 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4277 return -ENODEV;
4278
4279 return single_open(file, spr_wm_latency_show, dev);
4280}
4281
4282static int cur_wm_latency_open(struct inode *inode, struct file *file)
4283{
4284 struct drm_device *dev = inode->i_private;
4285
9ad0257c 4286 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4287 return -ENODEV;
4288
4289 return single_open(file, cur_wm_latency_show, dev);
4290}
4291
4292static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4293 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4294{
4295 struct seq_file *m = file->private_data;
4296 struct drm_device *dev = m->private;
97e94b22 4297 uint16_t new[8] = { 0 };
de38b95c 4298 int num_levels;
369a1342
VS		 4299 int level;
4300 int ret;
4301 char tmp[32];
4302
de38b95c
VS		 4303 if (IS_CHERRYVIEW(dev))
4304 num_levels = 3;
4305 else if (IS_VALLEYVIEW(dev))
4306 num_levels = 1;
4307 else
4308 num_levels = ilk_wm_max_level(dev) + 1;
4309
369a1342
VS		 4310 if (len >= sizeof(tmp))
4311 return -EINVAL;
4312
4313 if (copy_from_user(tmp, ubuf, len))
4314 return -EFAULT;
4315
4316 tmp[len] = '\0';
4317
97e94b22
DL		 4318 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4319 &new[0], &new[1], &new[2], &new[3],
4320 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4321 if (ret != num_levels)
4322 return -EINVAL;
4323
4324 drm_modeset_lock_all(dev);
4325
4326 for (level = 0; level < num_levels; level++)
4327 wm[level] = new[level];
4328
4329 drm_modeset_unlock_all(dev);
4330
4331 return len;
4332}
4333
4334
4335static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4336 size_t len, loff_t *offp)
4337{
4338 struct seq_file *m = file->private_data;
4339 struct drm_device *dev = m->private;
97e94b22
DL		 4340 struct drm_i915_private *dev_priv = dev->dev_private;
4341 uint16_t *latencies;
369a1342 4342
97e94b22
DL		 4343 if (INTEL_INFO(dev)->gen >= 9)
4344 latencies = dev_priv->wm.skl_latency;
4345 else
4346 latencies = to_i915(dev)->wm.pri_latency;
4347
4348 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4349}
4350
4351static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4352 size_t len, loff_t *offp)
4353{
4354 struct seq_file *m = file->private_data;
4355 struct drm_device *dev = m->private;
97e94b22
DL		 4356 struct drm_i915_private *dev_priv = dev->dev_private;
4357 uint16_t *latencies;
369a1342 4358
97e94b22
DL		 4359 if (INTEL_INFO(dev)->gen >= 9)
4360 latencies = dev_priv->wm.skl_latency;
4361 else
4362 latencies = to_i915(dev)->wm.spr_latency;
4363
4364 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4365}
4366
4367static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4368 size_t len, loff_t *offp)
4369{
4370 struct seq_file *m = file->private_data;
4371 struct drm_device *dev = m->private;
97e94b22
DL		 4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 uint16_t *latencies;
4374
4375 if (INTEL_INFO(dev)->gen >= 9)
4376 latencies = dev_priv->wm.skl_latency;
4377 else
4378 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4379
97e94b22 4380 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4381}
4382
4383static const struct file_operations i915_pri_wm_latency_fops = {
4384 .owner = THIS_MODULE,
4385 .open = pri_wm_latency_open,
4386 .read = seq_read,
4387 .llseek = seq_lseek,
4388 .release = single_release,
4389 .write = pri_wm_latency_write
4390};
4391
4392static const struct file_operations i915_spr_wm_latency_fops = {
4393 .owner = THIS_MODULE,
4394 .open = spr_wm_latency_open,
4395 .read = seq_read,
4396 .llseek = seq_lseek,
4397 .release = single_release,
4398 .write = spr_wm_latency_write
4399};
4400
4401static const struct file_operations i915_cur_wm_latency_fops = {
4402 .owner = THIS_MODULE,
4403 .open = cur_wm_latency_open,
4404 .read = seq_read,
4405 .llseek = seq_lseek,
4406 .release = single_release,
4407 .write = cur_wm_latency_write
4408};
4409
647416f9
KC		 4410static int
4411i915_wedged_get(void *data, u64 *val)
f3cd474b 4412{
647416f9 4413 struct drm_device *dev = data;
e277a1f8 4414 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4415
647416f9 4416 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4417
647416f9 4418 return 0;
f3cd474b
CW		 4419}
4420
647416f9
KC		 4421static int
4422i915_wedged_set(void *data, u64 val)
f3cd474b 4423{
647416f9 4424 struct drm_device *dev = data;
d46c0517
ID		 4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426
b8d24a06
MK		 4427 /*
4428 * There is no safeguard against this debugfs entry colliding
4429 * with the hangcheck calling same i915_handle_error() in
4430 * parallel, causing an explosion. For now we assume that the
4431 * test harness is responsible enough not to inject gpu hangs
4432 * while it is writing to 'i915_wedged'
4433 */
4434
4435 if (i915_reset_in_progress(&dev_priv->gpu_error))
4436 return -EAGAIN;
4437
d46c0517 4438 intel_runtime_pm_get(dev_priv);
f3cd474b 4439
58174462
MK		 4440 i915_handle_error(dev, val,
4441 "Manually setting wedged to %llu", val);
d46c0517
ID		 4442
4443 intel_runtime_pm_put(dev_priv);
4444
647416f9 4445 return 0;
f3cd474b
CW		 4446}
4447
647416f9
KC		 4448DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4449 i915_wedged_get, i915_wedged_set,
3a3b4f98 4450 "%llu\n");
f3cd474b 4451
647416f9
KC		 4452static int
4453i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4454{
647416f9 4455 struct drm_device *dev = data;
e277a1f8 4456 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4457
647416f9 4458 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4459
647416f9 4460 return 0;
e5eb3d63
DV		 4461}
4462
647416f9
KC		 4463static int
4464i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4465{
647416f9 4466 struct drm_device *dev = data;
e5eb3d63 4467 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4468 int ret;
e5eb3d63 4469
647416f9 4470 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4471
22bcfc6a
DV		 4472 ret = mutex_lock_interruptible(&dev->struct_mutex);
4473 if (ret)
4474 return ret;
4475
99584db3 4476 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4477 mutex_unlock(&dev->struct_mutex);
4478
647416f9 4479 return 0;
e5eb3d63
DV		 4480}
4481
647416f9
KC		 4482DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4483 i915_ring_stop_get, i915_ring_stop_set,
4484 "0x%08llx\n");
d5442303 4485
094f9a54
CW		 4486static int
4487i915_ring_missed_irq_get(void *data, u64 *val)
4488{
4489 struct drm_device *dev = data;
4490 struct drm_i915_private *dev_priv = dev->dev_private;
4491
4492 *val = dev_priv->gpu_error.missed_irq_rings;
4493 return 0;
4494}
4495
4496static int
4497i915_ring_missed_irq_set(void *data, u64 val)
4498{
4499 struct drm_device *dev = data;
4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501 int ret;
4502
4503 /* Lock against concurrent debugfs callers */
4504 ret = mutex_lock_interruptible(&dev->struct_mutex);
4505 if (ret)
4506 return ret;
4507 dev_priv->gpu_error.missed_irq_rings = val;
4508 mutex_unlock(&dev->struct_mutex);
4509
4510 return 0;
4511}
4512
4513DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4514 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4515 "0x%08llx\n");
4516
4517static int
4518i915_ring_test_irq_get(void *data, u64 *val)
4519{
4520 struct drm_device *dev = data;
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522
4523 *val = dev_priv->gpu_error.test_irq_rings;
4524
4525 return 0;
4526}
4527
4528static int
4529i915_ring_test_irq_set(void *data, u64 val)
4530{
4531 struct drm_device *dev = data;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 int ret;
4534
4535 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4536
4537 /* Lock against concurrent debugfs callers */
4538 ret = mutex_lock_interruptible(&dev->struct_mutex);
4539 if (ret)
4540 return ret;
4541
4542 dev_priv->gpu_error.test_irq_rings = val;
4543 mutex_unlock(&dev->struct_mutex);
4544
4545 return 0;
4546}
4547
4548DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4549 i915_ring_test_irq_get, i915_ring_test_irq_set,
4550 "0x%08llx\n");
4551
dd624afd
CW		 4552#define DROP_UNBOUND 0x1
4553#define DROP_BOUND 0x2
4554#define DROP_RETIRE 0x4
4555#define DROP_ACTIVE 0x8
4556#define DROP_ALL (DROP_UNBOUND | \
4557 DROP_BOUND | \
4558 DROP_RETIRE | \
4559 DROP_ACTIVE)
647416f9
KC		 4560static int
4561i915_drop_caches_get(void *data, u64 *val)
dd624afd 4562{
647416f9 4563 *val = DROP_ALL;
dd624afd 4564
647416f9 4565 return 0;
dd624afd
CW		 4566}
4567
647416f9
KC		 4568static int
4569i915_drop_caches_set(void *data, u64 val)
dd624afd 4570{
647416f9 4571 struct drm_device *dev = data;
dd624afd 4572 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4573 int ret;
dd624afd 4574
2f9fe5ff 4575 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4576
4577 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4578 * on ioctls on -EAGAIN. */
4579 ret = mutex_lock_interruptible(&dev->struct_mutex);
4580 if (ret)
4581 return ret;
4582
4583 if (val & DROP_ACTIVE) {
4584 ret = i915_gpu_idle(dev);
4585 if (ret)
4586 goto unlock;
4587 }
4588
4589 if (val & (DROP_RETIRE | DROP_ACTIVE))
4590 i915_gem_retire_requests(dev);
4591
21ab4e74
CW		 4592 if (val & DROP_BOUND)
4593 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4594
21ab4e74
CW		 4595 if (val & DROP_UNBOUND)
4596 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4597
4598unlock:
4599 mutex_unlock(&dev->struct_mutex);
4600
647416f9 4601 return ret;
dd624afd
CW		 4602}
4603
647416f9
KC		 4604DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4605 i915_drop_caches_get, i915_drop_caches_set,
4606 "0x%08llx\n");
dd624afd 4607
647416f9
KC		 4608static int
4609i915_max_freq_get(void *data, u64 *val)
358733e9 4610{
647416f9 4611 struct drm_device *dev = data;
e277a1f8 4612 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4613 int ret;
004777cb 4614
daa3afb2 4615 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4616 return -ENODEV;
4617
5c9669ce
TR		 4618 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4619
4fc688ce 4620 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4621 if (ret)
4622 return ret;
358733e9 4623
7c59a9c1 4624 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4625 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4626
647416f9 4627 return 0;
358733e9
JB		 4628}
4629
647416f9
KC		 4630static int
4631i915_max_freq_set(void *data, u64 val)
358733e9 4632{
647416f9 4633 struct drm_device *dev = data;
358733e9 4634 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4635 u32 hw_max, hw_min;
647416f9 4636 int ret;
004777cb 4637
daa3afb2 4638 if (INTEL_INFO(dev)->gen < 6)
004777cb 4639 return -ENODEV;
358733e9 4640
5c9669ce
TR		 4641 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4642
647416f9 4643 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4644
4fc688ce 4645 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4646 if (ret)
4647 return ret;
4648
358733e9
JB		 4649 /*
4650 * Turbo will still be enabled, but won't go above the set value.
4651 */
bc4d91f6 4652 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4653
bc4d91f6
AG		 4654 hw_max = dev_priv->rps.max_freq;
4655 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4656
b39fb297 4657 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4658 mutex_unlock(&dev_priv->rps.hw_lock);
4659 return -EINVAL;
0a073b84
JB		 4660 }
4661
b39fb297 4662 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4663
ffe02b40 4664 intel_set_rps(dev, val);
dd0a1aa1 4665
4fc688ce 4666 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4667
647416f9 4668 return 0;
358733e9
JB		 4669}
4670
647416f9
KC		 4671DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4672 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4673 "%llu\n");
358733e9 4674
647416f9
KC		 4675static int
4676i915_min_freq_get(void *data, u64 *val)
1523c310 4677{
647416f9 4678 struct drm_device *dev = data;
e277a1f8 4679 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4680 int ret;
004777cb 4681
daa3afb2 4682 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4683 return -ENODEV;
4684
5c9669ce
TR		 4685 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4686
4fc688ce 4687 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4688 if (ret)
4689 return ret;
1523c310 4690
7c59a9c1 4691 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4692 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4693
647416f9 4694 return 0;
1523c310
JB		 4695}
4696
647416f9
KC		 4697static int
4698i915_min_freq_set(void *data, u64 val)
1523c310 4699{
647416f9 4700 struct drm_device *dev = data;
1523c310 4701 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4702 u32 hw_max, hw_min;
647416f9 4703 int ret;
004777cb 4704
daa3afb2 4705 if (INTEL_INFO(dev)->gen < 6)
004777cb 4706 return -ENODEV;
1523c310 4707
5c9669ce
TR		 4708 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4709
647416f9 4710 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4711
4fc688ce 4712 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4713 if (ret)
4714 return ret;
4715
1523c310
JB		 4716 /*
4717 * Turbo will still be enabled, but won't go below the set value.
4718 */
bc4d91f6 4719 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4720
bc4d91f6
AG		 4721 hw_max = dev_priv->rps.max_freq;
4722 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4723
b39fb297 4724 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4725 mutex_unlock(&dev_priv->rps.hw_lock);
4726 return -EINVAL;
0a073b84 4727 }
dd0a1aa1 4728
b39fb297 4729 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4730
ffe02b40 4731 intel_set_rps(dev, val);
dd0a1aa1 4732
4fc688ce 4733 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4734
647416f9 4735 return 0;
1523c310
JB		 4736}
4737
647416f9
KC		 4738DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4739 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4740 "%llu\n");
1523c310 4741
647416f9
KC		 4742static int
4743i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4744{
647416f9 4745 struct drm_device *dev = data;
e277a1f8 4746 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4747 u32 snpcr;
647416f9 4748 int ret;
07b7ddd9 4749
004777cb
DV		 4750 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4751 return -ENODEV;
4752
22bcfc6a
DV		 4753 ret = mutex_lock_interruptible(&dev->struct_mutex);
4754 if (ret)
4755 return ret;
c8c8fb33 4756 intel_runtime_pm_get(dev_priv);
22bcfc6a 4757
07b7ddd9 4758 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4759
4760 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4761 mutex_unlock(&dev_priv->dev->struct_mutex);
4762
647416f9 4763 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4764
647416f9 4765 return 0;
07b7ddd9
JB		 4766}
4767
647416f9
KC		 4768static int
4769i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4770{
647416f9 4771 struct drm_device *dev = data;
07b7ddd9 4772 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4773 u32 snpcr;
07b7ddd9 4774
004777cb
DV		 4775 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4776 return -ENODEV;
4777
647416f9 4778 if (val > 3)
07b7ddd9
JB		 4779 return -EINVAL;
4780
c8c8fb33 4781 intel_runtime_pm_get(dev_priv);
647416f9 4782 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4783
4784 /* Update the cache sharing policy here as well */
4785 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4786 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4787 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4788 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4789
c8c8fb33 4790 intel_runtime_pm_put(dev_priv);
647416f9 4791 return 0;
07b7ddd9
JB		 4792}
4793
647416f9
KC		 4794DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4795 i915_cache_sharing_get, i915_cache_sharing_set,
4796 "%llu\n");
07b7ddd9 4797
5d39525a
JM		 4798struct sseu_dev_status {
4799 unsigned int slice_total;
4800 unsigned int subslice_total;
4801 unsigned int subslice_per_slice;
4802 unsigned int eu_total;
4803 unsigned int eu_per_subslice;
4804};
4805
4806static void cherryview_sseu_device_status(struct drm_device *dev,
4807 struct sseu_dev_status *stat)
4808{
4809 struct drm_i915_private *dev_priv = dev->dev_private;
4810 const int ss_max = 2;
4811 int ss;
4812 u32 sig1[ss_max], sig2[ss_max];
4813
4814 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4815 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4816 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4817 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4818
4819 for (ss = 0; ss < ss_max; ss++) {
4820 unsigned int eu_cnt;
4821
4822 if (sig1[ss] & CHV_SS_PG_ENABLE)
4823 /* skip disabled subslice */
4824 continue;
4825
4826 stat->slice_total = 1;
4827 stat->subslice_per_slice++;
4828 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4829 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4830 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4831 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4832 stat->eu_total += eu_cnt;
4833 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4834 }
4835 stat->subslice_total = stat->subslice_per_slice;
4836}
4837
4838static void gen9_sseu_device_status(struct drm_device *dev,
4839 struct sseu_dev_status *stat)
4840{
4841 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 4842 int s_max = 3, ss_max = 4;
5d39525a
JM		 4843 int s, ss;
4844 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4845
1c046bc1
JM		 4846 /* BXT has a single slice and at most 3 subslices. */
4847 if (IS_BROXTON(dev)) {
4848 s_max = 1;
4849 ss_max = 3;
4850 }
4851
4852 for (s = 0; s < s_max; s++) {
4853 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4854 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4855 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4856 }
4857
5d39525a
JM		 4858 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4859 GEN9_PGCTL_SSA_EU19_ACK |
4860 GEN9_PGCTL_SSA_EU210_ACK |
4861 GEN9_PGCTL_SSA_EU311_ACK;
4862 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4863 GEN9_PGCTL_SSB_EU19_ACK |
4864 GEN9_PGCTL_SSB_EU210_ACK |
4865 GEN9_PGCTL_SSB_EU311_ACK;
4866
4867 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 4868 unsigned int ss_cnt = 0;
4869
5d39525a
JM		 4870 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4871 /* skip disabled slice */
4872 continue;
4873
4874 stat->slice_total++;
1c046bc1
JM		 4875
4876 if (IS_SKYLAKE(dev))
4877 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4878
5d39525a
JM		 4879 for (ss = 0; ss < ss_max; ss++) {
4880 unsigned int eu_cnt;
4881
1c046bc1
JM		 4882 if (IS_BROXTON(dev) &&
4883 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4884 /* skip disabled subslice */
4885 continue;
4886
4887 if (IS_BROXTON(dev))
4888 ss_cnt++;
4889
5d39525a
JM		 4890 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4891 eu_mask[ss%2]);
4892 stat->eu_total += eu_cnt;
4893 stat->eu_per_subslice = max(stat->eu_per_subslice,
4894 eu_cnt);
4895 }
1c046bc1
JM		 4896
4897 stat->subslice_total += ss_cnt;
4898 stat->subslice_per_slice = max(stat->subslice_per_slice,
4899 ss_cnt);
5d39525a
JM		 4900 }
4901}
4902
3873218f
JM		 4903static int i915_sseu_status(struct seq_file *m, void *unused)
4904{
4905 struct drm_info_node *node = (struct drm_info_node *) m->private;
4906 struct drm_device *dev = node->minor->dev;
5d39525a 4907 struct sseu_dev_status stat;
3873218f 4908
5575f03a 4909 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
3873218f
JM		 4910 return -ENODEV;
4911
4912 seq_puts(m, "SSEU Device Info\n");
4913 seq_printf(m, " Available Slice Total: %u\n",
4914 INTEL_INFO(dev)->slice_total);
4915 seq_printf(m, " Available Subslice Total: %u\n",
4916 INTEL_INFO(dev)->subslice_total);
4917 seq_printf(m, " Available Subslice Per Slice: %u\n",
4918 INTEL_INFO(dev)->subslice_per_slice);
4919 seq_printf(m, " Available EU Total: %u\n",
4920 INTEL_INFO(dev)->eu_total);
4921 seq_printf(m, " Available EU Per Subslice: %u\n",
4922 INTEL_INFO(dev)->eu_per_subslice);
4923 seq_printf(m, " Has Slice Power Gating: %s\n",
4924 yesno(INTEL_INFO(dev)->has_slice_pg));
4925 seq_printf(m, " Has Subslice Power Gating: %s\n",
4926 yesno(INTEL_INFO(dev)->has_subslice_pg));
4927 seq_printf(m, " Has EU Power Gating: %s\n",
4928 yesno(INTEL_INFO(dev)->has_eu_pg));
4929
7f992aba 4930 seq_puts(m, "SSEU Device Status\n");
5d39525a 4931 memset(&stat, 0, sizeof(stat));
5575f03a 4932 if (IS_CHERRYVIEW(dev)) {
5d39525a 4933 cherryview_sseu_device_status(dev, &stat);
1c046bc1 4934 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 4935 gen9_sseu_device_status(dev, &stat);
7f992aba 4936 }
5d39525a
JM		 4937 seq_printf(m, " Enabled Slice Total: %u\n",
4938 stat.slice_total);
4939 seq_printf(m, " Enabled Subslice Total: %u\n",
4940 stat.subslice_total);
4941 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
4942 stat.subslice_per_slice);
4943 seq_printf(m, " Enabled EU Total: %u\n",
4944 stat.eu_total);
4945 seq_printf(m, " Enabled EU Per Subslice: %u\n",
4946 stat.eu_per_subslice);
7f992aba 4947
3873218f
JM		 4948 return 0;
4949}
4950
6d794d42
BW		 4951static int i915_forcewake_open(struct inode *inode, struct file *file)
4952{
4953 struct drm_device *dev = inode->i_private;
4954 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4955
075edca4 4956 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4957 return 0;
4958
6daccb0b 4959 intel_runtime_pm_get(dev_priv);
59bad947 4960 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4961
4962 return 0;
4963}
4964
c43b5634 4965static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4966{
4967 struct drm_device *dev = inode->i_private;
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969
075edca4 4970 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4971 return 0;
4972
59bad947 4973 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4974 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4975
4976 return 0;
4977}
4978
4979static const struct file_operations i915_forcewake_fops = {
4980 .owner = THIS_MODULE,
4981 .open = i915_forcewake_open,
4982 .release = i915_forcewake_release,
4983};
4984
4985static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4986{
4987 struct drm_device *dev = minor->dev;
4988 struct dentry *ent;
4989
4990 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4991 S_IRUSR,
6d794d42
BW		 4992 root, dev,
4993 &i915_forcewake_fops);
f3c5fe97
WY		 4994 if (!ent)
4995 return -ENOMEM;
6d794d42 4996
8eb57294 4997 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4998}
4999
6a9c308d
DV		 5000static int i915_debugfs_create(struct dentry *root,
5001 struct drm_minor *minor,
5002 const char *name,
5003 const struct file_operations *fops)
07b7ddd9
JB		 5004{
5005 struct drm_device *dev = minor->dev;
5006 struct dentry *ent;
5007
6a9c308d 5008 ent = debugfs_create_file(name,
07b7ddd9
JB		 5009 S_IRUGO | S_IWUSR,
5010 root, dev,
6a9c308d 5011 fops);
f3c5fe97
WY		 5012 if (!ent)
5013 return -ENOMEM;
07b7ddd9 5014
6a9c308d 5015 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5016}
5017
06c5bf8c 5018static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5019 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5020 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5021 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5022 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5023 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5024 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5025 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5026 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5027 {"i915_gem_request", i915_gem_request_info, 0},
5028 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5029 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5030 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5031 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5032 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5033 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5034 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5035 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 5036 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5037 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5038 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5039 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5040 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5041 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5042 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5043 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5044 {"i915_sr_status", i915_sr_status, 0},
44834a67 5045 {"i915_opregion", i915_opregion, 0},
37811fcc 5046 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5047 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5048 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5049 {"i915_execlists", i915_execlists, 0},
f65367b5 5050 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5051 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5052 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5053 {"i915_llc", i915_llc, 0},
e91fd8c6 5054 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5055 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5056 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5057 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5058 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 5059 {"i915_display_info", i915_display_info, 0},
e04934cf 5060 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5061 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5062 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5063 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5064 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5065 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5066 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5067 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5068};
27c202ad 5069#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5070
06c5bf8c 5071static const struct i915_debugfs_files {
34b9674c
DV		 5072 const char *name;
5073 const struct file_operations *fops;
5074} i915_debugfs_files[] = {
5075 {"i915_wedged", &i915_wedged_fops},
5076 {"i915_max_freq", &i915_max_freq_fops},
5077 {"i915_min_freq", &i915_min_freq_fops},
5078 {"i915_cache_sharing", &i915_cache_sharing_fops},
5079 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5080 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5081 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5082 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5083 {"i915_error_state", &i915_error_state_fops},
5084 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5085 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5086 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5087 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5088 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5089 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5090 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5091 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5092 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5093};
5094
07144428
DL		 5095void intel_display_crc_init(struct drm_device *dev)
5096{
5097 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5098 enum pipe pipe;
07144428 5099
055e393f 5100 for_each_pipe(dev_priv, pipe) {
b378360e 5101 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5102
d538bbdf
DL		 5103 pipe_crc->opened = false;
5104 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5105 init_waitqueue_head(&pipe_crc->wq);
5106 }
5107}
5108
27c202ad 5109int i915_debugfs_init(struct drm_minor *minor)
2017263e 5110{
34b9674c 5111 int ret, i;
f3cd474b 5112
6d794d42 5113 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5114 if (ret)
5115 return ret;
6a9c308d 5116
07144428
DL		 5117 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5118 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5119 if (ret)
5120 return ret;
5121 }
5122
34b9674c
DV		 5123 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5124 ret = i915_debugfs_create(minor->debugfs_root, minor,
5125 i915_debugfs_files[i].name,
5126 i915_debugfs_files[i].fops);
5127 if (ret)
5128 return ret;
5129 }
40633219 5130
27c202ad
BG		 5131 return drm_debugfs_create_files(i915_debugfs_list,
5132 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5133 minor->debugfs_root, minor);
5134}
5135
27c202ad 5136void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5137{
34b9674c
DV		 5138 int i;
5139
27c202ad
BG		 5140 drm_debugfs_remove_files(i915_debugfs_list,
5141 I915_DEBUGFS_ENTRIES, minor);
07144428 5142
6d794d42
BW		 5143 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5144 1, minor);
07144428 5145
e309a997 5146 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5147 struct drm_info_list *info_list =
5148 (struct drm_info_list *)&i915_pipe_crc_data[i];
5149
5150 drm_debugfs_remove_files(info_list, 1, minor);
5151 }
5152
34b9674c
DV		 5153 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5154 struct drm_info_list *info_list =
5155 (struct drm_info_list *) i915_debugfs_files[i].fops;
5156
5157 drm_debugfs_remove_files(info_list, 1, minor);
5158 }
2017263e 5159}
aa7471d2
JN		 5160
5161struct dpcd_block {
5162 /* DPCD dump start address. */
5163 unsigned int offset;
5164 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5165 unsigned int end;
5166 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5167 size_t size;
5168 /* Only valid for eDP. */
5169 bool edp;
5170};
5171
5172static const struct dpcd_block i915_dpcd_debug[] = {
5173 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5174 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5175 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5176 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5177 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5178 { .offset = DP_SET_POWER },
5179 { .offset = DP_EDP_DPCD_REV },
5180 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5181 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5182 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5183};
5184
5185static int i915_dpcd_show(struct seq_file *m, void *data)
5186{
5187 struct drm_connector *connector = m->private;
5188 struct intel_dp *intel_dp =
5189 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5190 uint8_t buf[16];
5191 ssize_t err;
5192 int i;
5193
5c1a8875
MK		 5194 if (connector->status != connector_status_connected)
5195 return -ENODEV;
5196
aa7471d2
JN		 5197 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5198 const struct dpcd_block *b = &i915_dpcd_debug[i];
5199 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5200
5201 if (b->edp &&
5202 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5203 continue;
5204
5205 /* low tech for now */
5206 if (WARN_ON(size > sizeof(buf)))
5207 continue;
5208
5209 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5210 if (err <= 0) {
5211 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5212 size, b->offset, err);
5213 continue;
5214 }
5215
5216 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5217 }
aa7471d2
JN		 5218
5219 return 0;
5220}
5221
5222static int i915_dpcd_open(struct inode *inode, struct file *file)
5223{
5224 return single_open(file, i915_dpcd_show, inode->i_private);
5225}
5226
5227static const struct file_operations i915_dpcd_fops = {
5228 .owner = THIS_MODULE,
5229 .open = i915_dpcd_open,
5230 .read = seq_read,
5231 .llseek = seq_lseek,
5232 .release = single_release,
5233};
5234
5235/**
5236 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5237 * @connector: pointer to a registered drm_connector
5238 *
5239 * Cleanup will be done by drm_connector_unregister() through a call to
5240 * drm_debugfs_connector_remove().
5241 *
5242 * Returns 0 on success, negative error codes on error.
5243 */
5244int i915_debugfs_connector_add(struct drm_connector *connector)
5245{
5246 struct dentry *root = connector->debugfs_entry;
5247
5248 /* The connector must have been registered beforehands. */
5249 if (!root)
5250 return -ENODEV;
5251
5252 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5253 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5254 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5255 &i915_dpcd_fops);
5256
5257 return 0;
5258}
Linux 6.x block layer and io_uring tree(s)