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drm/i915: Workaround to bump rc6 voltage to 450
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
f3cd474b 30#include <linux/debugfs.h>
5a0e3ad6 31#include <linux/slab.h>
2d1a8a48 32#include <linux/export.h>
2017263e
BG		 33#include "drmP.h"
34#include "drm.h"
4e5359cd 35#include "intel_drv.h"
e5c65260 36#include "intel_ringbuffer.h"
2017263e
BG		 37#include "i915_drm.h"
38#include "i915_drv.h"
39
40#define DRM_I915_RING_DEBUG 1
41
42
43#if defined(CONFIG_DEBUG_FS)
44
f13d3f73 45enum {
69dc4987 46 ACTIVE_LIST,
f13d3f73 47 INACTIVE_LIST,
d21d5975 48 PINNED_LIST,
f13d3f73 49};
2017263e 50
70d39fe4
CW		 51static const char *yesno(int v)
52{
53 return v ? "yes" : "no";
54}
55
56static int i915_capabilities(struct seq_file *m, void *data)
57{
58 struct drm_info_node *node = (struct drm_info_node *) m->private;
59 struct drm_device *dev = node->minor->dev;
60 const struct intel_device_info *info = INTEL_INFO(dev);
61
62 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
c96ea64e
DV		 64#define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65#define DEV_INFO_SEP ;
66 DEV_INFO_FLAGS;
67#undef DEV_INFO_FLAG
68#undef DEV_INFO_SEP
70d39fe4
CW		 69
70 return 0;
71}
2017263e 72
05394f39 73static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 74{
05394f39 75 if (obj->user_pin_count > 0)
a6172a80 76 return "P";
05394f39 77 else if (obj->pin_count > 0)
a6172a80
CW		 78 return "p";
79 else
80 return " ";
81}
82
05394f39 83static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 84{
0206e353
AJ		 85 switch (obj->tiling_mode) {
86 default:
87 case I915_TILING_NONE: return " ";
88 case I915_TILING_X: return "X";
89 case I915_TILING_Y: return "Y";
90 }
a6172a80
CW		 91}
92
93dfb40c 93static const char *cache_level_str(int type)
08c18323
CW		 94{
95 switch (type) {
93dfb40c
CW		 96 case I915_CACHE_NONE: return " uncached";
97 case I915_CACHE_LLC: return " snooped (LLC)";
98 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
08c18323
CW		 99 default: return "";
100 }
101}
102
37811fcc
CW		 103static void
104describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
105{
0201f1ec 106 seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d %d%s%s%s",
37811fcc
CW		 107 &obj->base,
108 get_pin_flag(obj),
109 get_tiling_flag(obj),
a05a5862 110 obj->base.size / 1024,
37811fcc
CW		 111 obj->base.read_domains,
112 obj->base.write_domain,
0201f1ec
CW		 113 obj->last_read_seqno,
114 obj->last_write_seqno,
caea7476 115 obj->last_fenced_seqno,
93dfb40c 116 cache_level_str(obj->cache_level),
37811fcc
CW		 117 obj->dirty ? " dirty" : "",
118 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
119 if (obj->base.name)
120 seq_printf(m, " (name: %d)", obj->base.name);
c110a6d7
CW		 121 if (obj->pin_count)
122 seq_printf(m, " (pinned x %d)", obj->pin_count);
37811fcc
CW		 123 if (obj->fence_reg != I915_FENCE_REG_NONE)
124 seq_printf(m, " (fence: %d)", obj->fence_reg);
125 if (obj->gtt_space != NULL)
a00b10c3
CW		 126 seq_printf(m, " (gtt offset: %08x, size: %08x)",
127 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
6299f992
CW		 128 if (obj->pin_mappable || obj->fault_mappable) {
129 char s[3], *t = s;
130 if (obj->pin_mappable)
131 *t++ = 'p';
132 if (obj->fault_mappable)
133 *t++ = 'f';
134 *t = '\0';
135 seq_printf(m, " (%s mappable)", s);
136 }
69dc4987
CW		 137 if (obj->ring != NULL)
138 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 139}
140
433e12f7 141static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 142{
143 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 144 uintptr_t list = (uintptr_t) node->info_ent->data;
145 struct list_head *head;
2017263e
BG		 146 struct drm_device *dev = node->minor->dev;
147 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 148 struct drm_i915_gem_object *obj;
8f2480fb
CW		 149 size_t total_obj_size, total_gtt_size;
150 int count, ret;
de227ef0
CW		 151
152 ret = mutex_lock_interruptible(&dev->struct_mutex);
153 if (ret)
154 return ret;
2017263e 155
433e12f7
BG		 156 switch (list) {
157 case ACTIVE_LIST:
158 seq_printf(m, "Active:\n");
69dc4987 159 head = &dev_priv->mm.active_list;
433e12f7
BG		 160 break;
161 case INACTIVE_LIST:
a17458fc 162 seq_printf(m, "Inactive:\n");
433e12f7
BG		 163 head = &dev_priv->mm.inactive_list;
164 break;
433e12f7 165 default:
de227ef0
CW		 166 mutex_unlock(&dev->struct_mutex);
167 return -EINVAL;
2017263e 168 }
2017263e 169
8f2480fb 170 total_obj_size = total_gtt_size = count = 0;
05394f39 171 list_for_each_entry(obj, head, mm_list) {
37811fcc 172 seq_printf(m, " ");
05394f39 173 describe_obj(m, obj);
f4ceda89 174 seq_printf(m, "\n");
05394f39
CW		 175 total_obj_size += obj->base.size;
176 total_gtt_size += obj->gtt_space->size;
8f2480fb 177 count++;
2017263e 178 }
de227ef0 179 mutex_unlock(&dev->struct_mutex);
5e118f41 180
8f2480fb
CW		 181 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
182 count, total_obj_size, total_gtt_size);
2017263e
BG		 183 return 0;
184}
185
6299f992
CW		 186#define count_objects(list, member) do { \
187 list_for_each_entry(obj, list, member) { \
188 size += obj->gtt_space->size; \
189 ++count; \
190 if (obj->map_and_fenceable) { \
191 mappable_size += obj->gtt_space->size; \
192 ++mappable_count; \
193 } \
194 } \
0206e353 195} while (0)
6299f992 196
73aa808f
CW		 197static int i915_gem_object_info(struct seq_file *m, void* data)
198{
199 struct drm_info_node *node = (struct drm_info_node *) m->private;
200 struct drm_device *dev = node->minor->dev;
201 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 202 u32 count, mappable_count, purgeable_count;
203 size_t size, mappable_size, purgeable_size;
6299f992 204 struct drm_i915_gem_object *obj;
73aa808f
CW		 205 int ret;
206
207 ret = mutex_lock_interruptible(&dev->struct_mutex);
208 if (ret)
209 return ret;
210
6299f992
CW		 211 seq_printf(m, "%u objects, %zu bytes\n",
212 dev_priv->mm.object_count,
213 dev_priv->mm.object_memory);
214
215 size = count = mappable_size = mappable_count = 0;
6c085a72 216 count_objects(&dev_priv->mm.bound_list, gtt_list);
6299f992
CW		 217 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
218 count, mappable_count, size, mappable_size);
219
220 size = count = mappable_size = mappable_count = 0;
221 count_objects(&dev_priv->mm.active_list, mm_list);
6299f992
CW		 222 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
223 count, mappable_count, size, mappable_size);
224
6299f992
CW		 225 size = count = mappable_size = mappable_count = 0;
226 count_objects(&dev_priv->mm.inactive_list, mm_list);
227 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
228 count, mappable_count, size, mappable_size);
229
b7abb714
CW		 230 size = count = purgeable_size = purgeable_count = 0;
231 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
6c085a72 232 size += obj->base.size, ++count;
b7abb714
CW		 233 if (obj->madv == I915_MADV_DONTNEED)
234 purgeable_size += obj->base.size, ++purgeable_count;
235 }
6c085a72
CW		 236 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
237
6299f992 238 size = count = mappable_size = mappable_count = 0;
6c085a72 239 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
6299f992
CW		 240 if (obj->fault_mappable) {
241 size += obj->gtt_space->size;
242 ++count;
243 }
244 if (obj->pin_mappable) {
245 mappable_size += obj->gtt_space->size;
246 ++mappable_count;
247 }
b7abb714
CW		 248 if (obj->madv == I915_MADV_DONTNEED) {
249 purgeable_size += obj->base.size;
250 ++purgeable_count;
251 }
6299f992 252 }
b7abb714
CW		 253 seq_printf(m, "%u purgeable objects, %zu bytes\n",
254 purgeable_count, purgeable_size);
6299f992
CW		 255 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
256 mappable_count, mappable_size);
257 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
258 count, size);
259
260 seq_printf(m, "%zu [%zu] gtt total\n",
261 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
73aa808f
CW		 262
263 mutex_unlock(&dev->struct_mutex);
264
265 return 0;
266}
267
08c18323
CW		 268static int i915_gem_gtt_info(struct seq_file *m, void* data)
269{
270 struct drm_info_node *node = (struct drm_info_node *) m->private;
271 struct drm_device *dev = node->minor->dev;
1b50247a 272 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 273 struct drm_i915_private *dev_priv = dev->dev_private;
274 struct drm_i915_gem_object *obj;
275 size_t total_obj_size, total_gtt_size;
276 int count, ret;
277
278 ret = mutex_lock_interruptible(&dev->struct_mutex);
279 if (ret)
280 return ret;
281
282 total_obj_size = total_gtt_size = count = 0;
6c085a72 283 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1b50247a
CW		 284 if (list == PINNED_LIST && obj->pin_count == 0)
285 continue;
286
08c18323
CW		 287 seq_printf(m, " ");
288 describe_obj(m, obj);
289 seq_printf(m, "\n");
290 total_obj_size += obj->base.size;
291 total_gtt_size += obj->gtt_space->size;
292 count++;
293 }
294
295 mutex_unlock(&dev->struct_mutex);
296
297 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
298 count, total_obj_size, total_gtt_size);
299
300 return 0;
301}
302
4e5359cd
SF		 303static int i915_gem_pageflip_info(struct seq_file *m, void *data)
304{
305 struct drm_info_node *node = (struct drm_info_node *) m->private;
306 struct drm_device *dev = node->minor->dev;
307 unsigned long flags;
308 struct intel_crtc *crtc;
309
310 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 311 const char pipe = pipe_name(crtc->pipe);
312 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 313 struct intel_unpin_work *work;
314
315 spin_lock_irqsave(&dev->event_lock, flags);
316 work = crtc->unpin_work;
317 if (work == NULL) {
9db4a9c7 318 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 319 pipe, plane);
320 } else {
321 if (!work->pending) {
9db4a9c7 322 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 323 pipe, plane);
324 } else {
9db4a9c7 325 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 326 pipe, plane);
327 }
328 if (work->enable_stall_check)
329 seq_printf(m, "Stall check enabled, ");
330 else
331 seq_printf(m, "Stall check waiting for page flip ioctl, ");
332 seq_printf(m, "%d prepares\n", work->pending);
333
334 if (work->old_fb_obj) {
05394f39
CW		 335 struct drm_i915_gem_object *obj = work->old_fb_obj;
336 if (obj)
337 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 338 }
339 if (work->pending_flip_obj) {
05394f39
CW		 340 struct drm_i915_gem_object *obj = work->pending_flip_obj;
341 if (obj)
342 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 343 }
344 }
345 spin_unlock_irqrestore(&dev->event_lock, flags);
346 }
347
348 return 0;
349}
350
2017263e
BG		 351static int i915_gem_request_info(struct seq_file *m, void *data)
352{
353 struct drm_info_node *node = (struct drm_info_node *) m->private;
354 struct drm_device *dev = node->minor->dev;
355 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 356 struct intel_ring_buffer *ring;
2017263e 357 struct drm_i915_gem_request *gem_request;
a2c7f6fd 358 int ret, count, i;
de227ef0
CW		 359
360 ret = mutex_lock_interruptible(&dev->struct_mutex);
361 if (ret)
362 return ret;
2017263e 363
c2c347a9 364 count = 0;
a2c7f6fd
CW		 365 for_each_ring(ring, dev_priv, i) {
366 if (list_empty(&ring->request_list))
367 continue;
368
369 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 370 list_for_each_entry(gem_request,
a2c7f6fd 371 &ring->request_list,
c2c347a9
CW		 372 list) {
373 seq_printf(m, " %d @ %d\n",
374 gem_request->seqno,
375 (int) (jiffies - gem_request->emitted_jiffies));
376 }
377 count++;
2017263e 378 }
de227ef0
CW		 379 mutex_unlock(&dev->struct_mutex);
380
c2c347a9
CW		 381 if (count == 0)
382 seq_printf(m, "No requests\n");
383
2017263e
BG		 384 return 0;
385}
386
b2223497
CW		 387static void i915_ring_seqno_info(struct seq_file *m,
388 struct intel_ring_buffer *ring)
389{
390 if (ring->get_seqno) {
391 seq_printf(m, "Current sequence (%s): %d\n",
b2eadbc8 392 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 393 }
394}
395
2017263e
BG		 396static int i915_gem_seqno_info(struct seq_file *m, void *data)
397{
398 struct drm_info_node *node = (struct drm_info_node *) m->private;
399 struct drm_device *dev = node->minor->dev;
400 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 401 struct intel_ring_buffer *ring;
1ec14ad3 402 int ret, i;
de227ef0
CW		 403
404 ret = mutex_lock_interruptible(&dev->struct_mutex);
405 if (ret)
406 return ret;
2017263e 407
a2c7f6fd
CW		 408 for_each_ring(ring, dev_priv, i)
409 i915_ring_seqno_info(m, ring);
de227ef0
CW		 410
411 mutex_unlock(&dev->struct_mutex);
412
2017263e
BG		 413 return 0;
414}
415
416
417static int i915_interrupt_info(struct seq_file *m, void *data)
418{
419 struct drm_info_node *node = (struct drm_info_node *) m->private;
420 struct drm_device *dev = node->minor->dev;
421 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 422 struct intel_ring_buffer *ring;
9db4a9c7 423 int ret, i, pipe;
de227ef0
CW		 424
425 ret = mutex_lock_interruptible(&dev->struct_mutex);
426 if (ret)
427 return ret;
2017263e 428
7e231dbe
JB		 429 if (IS_VALLEYVIEW(dev)) {
430 seq_printf(m, "Display IER:\t%08x\n",
431 I915_READ(VLV_IER));
432 seq_printf(m, "Display IIR:\t%08x\n",
433 I915_READ(VLV_IIR));
434 seq_printf(m, "Display IIR_RW:\t%08x\n",
435 I915_READ(VLV_IIR_RW));
436 seq_printf(m, "Display IMR:\t%08x\n",
437 I915_READ(VLV_IMR));
438 for_each_pipe(pipe)
439 seq_printf(m, "Pipe %c stat:\t%08x\n",
440 pipe_name(pipe),
441 I915_READ(PIPESTAT(pipe)));
442
443 seq_printf(m, "Master IER:\t%08x\n",
444 I915_READ(VLV_MASTER_IER));
445
446 seq_printf(m, "Render IER:\t%08x\n",
447 I915_READ(GTIER));
448 seq_printf(m, "Render IIR:\t%08x\n",
449 I915_READ(GTIIR));
450 seq_printf(m, "Render IMR:\t%08x\n",
451 I915_READ(GTIMR));
452
453 seq_printf(m, "PM IER:\t\t%08x\n",
454 I915_READ(GEN6_PMIER));
455 seq_printf(m, "PM IIR:\t\t%08x\n",
456 I915_READ(GEN6_PMIIR));
457 seq_printf(m, "PM IMR:\t\t%08x\n",
458 I915_READ(GEN6_PMIMR));
459
460 seq_printf(m, "Port hotplug:\t%08x\n",
461 I915_READ(PORT_HOTPLUG_EN));
462 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
463 I915_READ(VLV_DPFLIPSTAT));
464 seq_printf(m, "DPINVGTT:\t%08x\n",
465 I915_READ(DPINVGTT));
466
467 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 468 seq_printf(m, "Interrupt enable: %08x\n",
469 I915_READ(IER));
470 seq_printf(m, "Interrupt identity: %08x\n",
471 I915_READ(IIR));
472 seq_printf(m, "Interrupt mask: %08x\n",
473 I915_READ(IMR));
9db4a9c7
JB		 474 for_each_pipe(pipe)
475 seq_printf(m, "Pipe %c stat: %08x\n",
476 pipe_name(pipe),
477 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 478 } else {
479 seq_printf(m, "North Display Interrupt enable: %08x\n",
480 I915_READ(DEIER));
481 seq_printf(m, "North Display Interrupt identity: %08x\n",
482 I915_READ(DEIIR));
483 seq_printf(m, "North Display Interrupt mask: %08x\n",
484 I915_READ(DEIMR));
485 seq_printf(m, "South Display Interrupt enable: %08x\n",
486 I915_READ(SDEIER));
487 seq_printf(m, "South Display Interrupt identity: %08x\n",
488 I915_READ(SDEIIR));
489 seq_printf(m, "South Display Interrupt mask: %08x\n",
490 I915_READ(SDEIMR));
491 seq_printf(m, "Graphics Interrupt enable: %08x\n",
492 I915_READ(GTIER));
493 seq_printf(m, "Graphics Interrupt identity: %08x\n",
494 I915_READ(GTIIR));
495 seq_printf(m, "Graphics Interrupt mask: %08x\n",
496 I915_READ(GTIMR));
497 }
2017263e
BG		 498 seq_printf(m, "Interrupts received: %d\n",
499 atomic_read(&dev_priv->irq_received));
a2c7f6fd 500 for_each_ring(ring, dev_priv, i) {
da64c6fc 501 if (IS_GEN6(dev) || IS_GEN7(dev)) {
a2c7f6fd
CW		 502 seq_printf(m,
503 "Graphics Interrupt mask (%s): %08x\n",
504 ring->name, I915_READ_IMR(ring));
9862e600 505 }
a2c7f6fd 506 i915_ring_seqno_info(m, ring);
9862e600 507 }
de227ef0
CW		 508 mutex_unlock(&dev->struct_mutex);
509
2017263e
BG		 510 return 0;
511}
512
a6172a80
CW		 513static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
514{
515 struct drm_info_node *node = (struct drm_info_node *) m->private;
516 struct drm_device *dev = node->minor->dev;
517 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 518 int i, ret;
519
520 ret = mutex_lock_interruptible(&dev->struct_mutex);
521 if (ret)
522 return ret;
a6172a80
CW		 523
524 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
525 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
526 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 527 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 528
6c085a72
CW		 529 seq_printf(m, "Fence %d, pin count = %d, object = ",
530 i, dev_priv->fence_regs[i].pin_count);
c2c347a9
CW		 531 if (obj == NULL)
532 seq_printf(m, "unused");
533 else
05394f39 534 describe_obj(m, obj);
c2c347a9 535 seq_printf(m, "\n");
a6172a80
CW		 536 }
537
05394f39 538 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 539 return 0;
540}
541
2017263e
BG		 542static int i915_hws_info(struct seq_file *m, void *data)
543{
544 struct drm_info_node *node = (struct drm_info_node *) m->private;
545 struct drm_device *dev = node->minor->dev;
546 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 547 struct intel_ring_buffer *ring;
311bd68e 548 const volatile u32 __iomem *hws;
4066c0ae
CW		 549 int i;
550
1ec14ad3 551 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
311bd68e 552 hws = (volatile u32 __iomem *)ring->status_page.page_addr;
2017263e
BG		 553 if (hws == NULL)
554 return 0;
555
556 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
557 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
558 i * 4,
559 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
560 }
561 return 0;
562}
563
e5c65260
CW		 564static const char *ring_str(int ring)
565{
566 switch (ring) {
96154f2f
DV		 567 case RCS: return "render";
568 case VCS: return "bsd";
569 case BCS: return "blt";
e5c65260
CW		 570 default: return "";
571 }
572}
573
9df30794
CW		 574static const char *pin_flag(int pinned)
575{
576 if (pinned > 0)
577 return " P";
578 else if (pinned < 0)
579 return " p";
580 else
581 return "";
582}
583
584static const char *tiling_flag(int tiling)
585{
586 switch (tiling) {
587 default:
588 case I915_TILING_NONE: return "";
589 case I915_TILING_X: return " X";
590 case I915_TILING_Y: return " Y";
591 }
592}
593
594static const char *dirty_flag(int dirty)
595{
596 return dirty ? " dirty" : "";
597}
598
599static const char *purgeable_flag(int purgeable)
600{
601 return purgeable ? " purgeable" : "";
602}
603
c724e8a9
CW		 604static void print_error_buffers(struct seq_file *m,
605 const char *name,
606 struct drm_i915_error_buffer *err,
607 int count)
608{
609 seq_printf(m, "%s [%d]:\n", name, count);
610
611 while (count--) {
0201f1ec 612 seq_printf(m, " %08x %8u %04x %04x %x %x%s%s%s%s%s%s%s",
c724e8a9
CW		 613 err->gtt_offset,
614 err->size,
615 err->read_domains,
616 err->write_domain,
0201f1ec 617 err->rseqno, err->wseqno,
c724e8a9
CW		 618 pin_flag(err->pinned),
619 tiling_flag(err->tiling),
620 dirty_flag(err->dirty),
621 purgeable_flag(err->purgeable),
96154f2f 622 err->ring != -1 ? " " : "",
a779e5ab 623 ring_str(err->ring),
93dfb40c 624 cache_level_str(err->cache_level));
c724e8a9
CW		 625
626 if (err->name)
627 seq_printf(m, " (name: %d)", err->name);
628 if (err->fence_reg != I915_FENCE_REG_NONE)
629 seq_printf(m, " (fence: %d)", err->fence_reg);
630
631 seq_printf(m, "\n");
632 err++;
633 }
634}
635
d27b1e0e
DV		 636static void i915_ring_error_state(struct seq_file *m,
637 struct drm_device *dev,
638 struct drm_i915_error_state *error,
639 unsigned ring)
640{
ec34a01d 641 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
d27b1e0e 642 seq_printf(m, "%s command stream:\n", ring_str(ring));
c1cd90ed
DV		 643 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
644 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
d27b1e0e
DV		 645 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
646 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
647 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
648 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
050ee91f 649 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
c1cd90ed 650 seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
050ee91f 651
c1cd90ed
DV		 652 if (INTEL_INFO(dev)->gen >= 4)
653 seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
654 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
9d2f41fa 655 seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
33f3f518 656 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 657 seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
33f3f518 658 seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
7e3b8737
DV		 659 seq_printf(m, " SYNC_0: 0x%08x\n",
660 error->semaphore_mboxes[ring][0]);
661 seq_printf(m, " SYNC_1: 0x%08x\n",
662 error->semaphore_mboxes[ring][1]);
33f3f518 663 }
d27b1e0e 664 seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
9574b3fe 665 seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
7e3b8737
DV		 666 seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
667 seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
d27b1e0e
DV		 668}
669
d5442303
DV		 670struct i915_error_state_file_priv {
671 struct drm_device *dev;
672 struct drm_i915_error_state *error;
673};
674
63eeaf38
JB		 675static int i915_error_state(struct seq_file *m, void *unused)
676{
d5442303
DV		 677 struct i915_error_state_file_priv *error_priv = m->private;
678 struct drm_device *dev = error_priv->dev;
63eeaf38 679 drm_i915_private_t *dev_priv = dev->dev_private;
d5442303 680 struct drm_i915_error_state *error = error_priv->error;
b4519513 681 struct intel_ring_buffer *ring;
52d39a21 682 int i, j, page, offset, elt;
63eeaf38 683
742cbee8 684 if (!error) {
63eeaf38 685 seq_printf(m, "no error state collected\n");
742cbee8 686 return 0;
63eeaf38
JB		 687 }
688
8a905236
JB		 689 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
690 error->time.tv_usec);
9df30794 691 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
1d8f38f4 692 seq_printf(m, "EIR: 0x%08x\n", error->eir);
be998e2e 693 seq_printf(m, "IER: 0x%08x\n", error->ier);
1d8f38f4 694 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
b9a3906b 695 seq_printf(m, "CCID: 0x%08x\n", error->ccid);
9df30794 696
bf3301ab 697 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 698 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
699
050ee91f
BW		 700 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
701 seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]);
702
33f3f518 703 if (INTEL_INFO(dev)->gen >= 6) {
d27b1e0e 704 seq_printf(m, "ERROR: 0x%08x\n", error->error);
33f3f518
DV		 705 seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
706 }
d27b1e0e 707
71e172e8
BW		 708 if (INTEL_INFO(dev)->gen == 7)
709 seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
710
b4519513
CW		 711 for_each_ring(ring, dev_priv, i)
712 i915_ring_error_state(m, dev, error, i);
d27b1e0e 713
c724e8a9
CW		 714 if (error->active_bo)
715 print_error_buffers(m, "Active",
716 error->active_bo,
717 error->active_bo_count);
718
719 if (error->pinned_bo)
720 print_error_buffers(m, "Pinned",
721 error->pinned_bo,
722 error->pinned_bo_count);
9df30794 723
52d39a21
CW		 724 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
725 struct drm_i915_error_object *obj;
9df30794 726
52d39a21 727 if ((obj = error->ring[i].batchbuffer)) {
bcfb2e28
CW		 728 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
729 dev_priv->ring[i].name,
730 obj->gtt_offset);
9df30794
CW		 731 offset = 0;
732 for (page = 0; page < obj->page_count; page++) {
733 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
734 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
735 offset += 4;
736 }
737 }
738 }
9df30794 739
52d39a21
CW		 740 if (error->ring[i].num_requests) {
741 seq_printf(m, "%s --- %d requests\n",
742 dev_priv->ring[i].name,
743 error->ring[i].num_requests);
744 for (j = 0; j < error->ring[i].num_requests; j++) {
ee4f42b1 745 seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
52d39a21 746 error->ring[i].requests[j].seqno,
ee4f42b1
CW		 747 error->ring[i].requests[j].jiffies,
748 error->ring[i].requests[j].tail);
52d39a21
CW		 749 }
750 }
751
752 if ((obj = error->ring[i].ringbuffer)) {
e2f973d5
CW		 753 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
754 dev_priv->ring[i].name,
755 obj->gtt_offset);
756 offset = 0;
757 for (page = 0; page < obj->page_count; page++) {
758 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
759 seq_printf(m, "%08x : %08x\n",
760 offset,
761 obj->pages[page][elt]);
762 offset += 4;
763 }
9df30794
CW		 764 }
765 }
766 }
63eeaf38 767
6ef3d427
CW		 768 if (error->overlay)
769 intel_overlay_print_error_state(m, error->overlay);
770
c4a1d9e4
CW		 771 if (error->display)
772 intel_display_print_error_state(m, dev, error->display);
773
63eeaf38
JB		 774 return 0;
775}
6911a9b8 776
d5442303
DV		 777static ssize_t
778i915_error_state_write(struct file *filp,
779 const char __user *ubuf,
780 size_t cnt,
781 loff_t *ppos)
782{
783 struct seq_file *m = filp->private_data;
784 struct i915_error_state_file_priv *error_priv = m->private;
785 struct drm_device *dev = error_priv->dev;
22bcfc6a 786 int ret;
d5442303
DV		 787
788 DRM_DEBUG_DRIVER("Resetting error state\n");
789
22bcfc6a
DV		 790 ret = mutex_lock_interruptible(&dev->struct_mutex);
791 if (ret)
792 return ret;
793
d5442303
DV		 794 i915_destroy_error_state(dev);
795 mutex_unlock(&dev->struct_mutex);
796
797 return cnt;
798}
799
800static int i915_error_state_open(struct inode *inode, struct file *file)
801{
802 struct drm_device *dev = inode->i_private;
803 drm_i915_private_t *dev_priv = dev->dev_private;
804 struct i915_error_state_file_priv *error_priv;
805 unsigned long flags;
806
807 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
808 if (!error_priv)
809 return -ENOMEM;
810
811 error_priv->dev = dev;
812
813 spin_lock_irqsave(&dev_priv->error_lock, flags);
814 error_priv->error = dev_priv->first_error;
815 if (error_priv->error)
816 kref_get(&error_priv->error->ref);
817 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
818
819 return single_open(file, i915_error_state, error_priv);
820}
821
822static int i915_error_state_release(struct inode *inode, struct file *file)
823{
824 struct seq_file *m = file->private_data;
825 struct i915_error_state_file_priv *error_priv = m->private;
826
827 if (error_priv->error)
828 kref_put(&error_priv->error->ref, i915_error_state_free);
829 kfree(error_priv);
830
831 return single_release(inode, file);
832}
833
834static const struct file_operations i915_error_state_fops = {
835 .owner = THIS_MODULE,
836 .open = i915_error_state_open,
837 .read = seq_read,
838 .write = i915_error_state_write,
839 .llseek = default_llseek,
840 .release = i915_error_state_release,
841};
842
f97108d1
JB		 843static int i915_rstdby_delays(struct seq_file *m, void *unused)
844{
845 struct drm_info_node *node = (struct drm_info_node *) m->private;
846 struct drm_device *dev = node->minor->dev;
847 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 848 u16 crstanddelay;
849 int ret;
850
851 ret = mutex_lock_interruptible(&dev->struct_mutex);
852 if (ret)
853 return ret;
854
855 crstanddelay = I915_READ16(CRSTANDVID);
856
857 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 858
859 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
860
861 return 0;
862}
863
864static int i915_cur_delayinfo(struct seq_file *m, void *unused)
865{
866 struct drm_info_node *node = (struct drm_info_node *) m->private;
867 struct drm_device *dev = node->minor->dev;
868 drm_i915_private_t *dev_priv = dev->dev_private;
d1ebd816 869 int ret;
3b8d8d91
JB		 870
871 if (IS_GEN5(dev)) {
872 u16 rgvswctl = I915_READ16(MEMSWCTL);
873 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
874
875 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
876 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
877 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
878 MEMSTAT_VID_SHIFT);
879 seq_printf(m, "Current P-state: %d\n",
880 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1c70c0ce 881 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91
JB		 882 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
883 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
884 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
ccab5c82
JB		 885 u32 rpstat;
886 u32 rpupei, rpcurup, rpprevup;
887 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 888 int max_freq;
889
890 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 891 ret = mutex_lock_interruptible(&dev->struct_mutex);
892 if (ret)
893 return ret;
894
fcca7926 895 gen6_gt_force_wake_get(dev_priv);
3b8d8d91 896
ccab5c82
JB		 897 rpstat = I915_READ(GEN6_RPSTAT1);
898 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
899 rpcurup = I915_READ(GEN6_RP_CUR_UP);
900 rpprevup = I915_READ(GEN6_RP_PREV_UP);
901 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
902 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
903 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
904
d1ebd816
BW		 905 gen6_gt_force_wake_put(dev_priv);
906 mutex_unlock(&dev->struct_mutex);
907
3b8d8d91 908 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 909 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 910 seq_printf(m, "Render p-state ratio: %d\n",
911 (gt_perf_status & 0xff00) >> 8);
912 seq_printf(m, "Render p-state VID: %d\n",
913 gt_perf_status & 0xff);
914 seq_printf(m, "Render p-state limit: %d\n",
915 rp_state_limits & 0xff);
ccab5c82 916 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
c8735b0c 917 GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER);
ccab5c82
JB		 918 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
919 GEN6_CURICONT_MASK);
920 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
921 GEN6_CURBSYTAVG_MASK);
922 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
923 GEN6_CURBSYTAVG_MASK);
924 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
925 GEN6_CURIAVG_MASK);
926 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
927 GEN6_CURBSYTAVG_MASK);
928 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
929 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 930
931 max_freq = (rp_state_cap & 0xff0000) >> 16;
932 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 933 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 934
935 max_freq = (rp_state_cap & 0xff00) >> 8;
936 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 937 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 938
939 max_freq = rp_state_cap & 0xff;
940 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 941 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 942 } else {
943 seq_printf(m, "no P-state info available\n");
944 }
f97108d1
JB		 945
946 return 0;
947}
948
949static int i915_delayfreq_table(struct seq_file *m, void *unused)
950{
951 struct drm_info_node *node = (struct drm_info_node *) m->private;
952 struct drm_device *dev = node->minor->dev;
953 drm_i915_private_t *dev_priv = dev->dev_private;
954 u32 delayfreq;
616fdb5a
BW		 955 int ret, i;
956
957 ret = mutex_lock_interruptible(&dev->struct_mutex);
958 if (ret)
959 return ret;
f97108d1
JB		 960
961 for (i = 0; i < 16; i++) {
962 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 963 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
964 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 965 }
966
616fdb5a
BW		 967 mutex_unlock(&dev->struct_mutex);
968
f97108d1
JB		 969 return 0;
970}
971
972static inline int MAP_TO_MV(int map)
973{
974 return 1250 - (map * 25);
975}
976
977static int i915_inttoext_table(struct seq_file *m, void *unused)
978{
979 struct drm_info_node *node = (struct drm_info_node *) m->private;
980 struct drm_device *dev = node->minor->dev;
981 drm_i915_private_t *dev_priv = dev->dev_private;
982 u32 inttoext;
616fdb5a
BW		 983 int ret, i;
984
985 ret = mutex_lock_interruptible(&dev->struct_mutex);
986 if (ret)
987 return ret;
f97108d1
JB		 988
989 for (i = 1; i <= 32; i++) {
990 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
991 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
992 }
993
616fdb5a
BW		 994 mutex_unlock(&dev->struct_mutex);
995
f97108d1
JB		 996 return 0;
997}
998
4d85529d 999static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1000{
1001 struct drm_info_node *node = (struct drm_info_node *) m->private;
1002 struct drm_device *dev = node->minor->dev;
1003 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1004 u32 rgvmodectl, rstdbyctl;
1005 u16 crstandvid;
1006 int ret;
1007
1008 ret = mutex_lock_interruptible(&dev->struct_mutex);
1009 if (ret)
1010 return ret;
1011
1012 rgvmodectl = I915_READ(MEMMODECTL);
1013 rstdbyctl = I915_READ(RSTDBYCTL);
1014 crstandvid = I915_READ16(CRSTANDVID);
1015
1016 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1017
1018 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1019 "yes" : "no");
1020 seq_printf(m, "Boost freq: %d\n",
1021 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1022 MEMMODE_BOOST_FREQ_SHIFT);
1023 seq_printf(m, "HW control enabled: %s\n",
1024 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1025 seq_printf(m, "SW control enabled: %s\n",
1026 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1027 seq_printf(m, "Gated voltage change: %s\n",
1028 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1029 seq_printf(m, "Starting frequency: P%d\n",
1030 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1031 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1032 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1033 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1034 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1035 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1036 seq_printf(m, "Render standby enabled: %s\n",
1037 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
88271da3
JB		 1038 seq_printf(m, "Current RS state: ");
1039 switch (rstdbyctl & RSX_STATUS_MASK) {
1040 case RSX_STATUS_ON:
1041 seq_printf(m, "on\n");
1042 break;
1043 case RSX_STATUS_RC1:
1044 seq_printf(m, "RC1\n");
1045 break;
1046 case RSX_STATUS_RC1E:
1047 seq_printf(m, "RC1E\n");
1048 break;
1049 case RSX_STATUS_RS1:
1050 seq_printf(m, "RS1\n");
1051 break;
1052 case RSX_STATUS_RS2:
1053 seq_printf(m, "RS2 (RC6)\n");
1054 break;
1055 case RSX_STATUS_RS3:
1056 seq_printf(m, "RC3 (RC6+)\n");
1057 break;
1058 default:
1059 seq_printf(m, "unknown\n");
1060 break;
1061 }
f97108d1
JB		 1062
1063 return 0;
1064}
1065
4d85529d
BW		 1066static int gen6_drpc_info(struct seq_file *m)
1067{
1068
1069 struct drm_info_node *node = (struct drm_info_node *) m->private;
1070 struct drm_device *dev = node->minor->dev;
1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 u32 rpmodectl1, gt_core_status, rcctl1;
93b525dc 1073 unsigned forcewake_count;
4d85529d
BW		 1074 int count=0, ret;
1075
1076
1077 ret = mutex_lock_interruptible(&dev->struct_mutex);
1078 if (ret)
1079 return ret;
1080
93b525dc
DV		 1081 spin_lock_irq(&dev_priv->gt_lock);
1082 forcewake_count = dev_priv->forcewake_count;
1083 spin_unlock_irq(&dev_priv->gt_lock);
1084
1085 if (forcewake_count) {
1086 seq_printf(m, "RC information inaccurate because somebody "
1087 "holds a forcewake reference \n");
4d85529d
BW		 1088 } else {
1089 /* NB: we cannot use forcewake, else we read the wrong values */
1090 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1091 udelay(10);
1092 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1093 }
1094
1095 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1096 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1097
1098 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1099 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1100 mutex_unlock(&dev->struct_mutex);
1101
1102 seq_printf(m, "Video Turbo Mode: %s\n",
1103 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1104 seq_printf(m, "HW control enabled: %s\n",
1105 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1106 seq_printf(m, "SW control enabled: %s\n",
1107 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1108 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1109 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1110 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1111 seq_printf(m, "RC6 Enabled: %s\n",
1112 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1113 seq_printf(m, "Deep RC6 Enabled: %s\n",
1114 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1115 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1116 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1117 seq_printf(m, "Current RC state: ");
1118 switch (gt_core_status & GEN6_RCn_MASK) {
1119 case GEN6_RC0:
1120 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1121 seq_printf(m, "Core Power Down\n");
1122 else
1123 seq_printf(m, "on\n");
1124 break;
1125 case GEN6_RC3:
1126 seq_printf(m, "RC3\n");
1127 break;
1128 case GEN6_RC6:
1129 seq_printf(m, "RC6\n");
1130 break;
1131 case GEN6_RC7:
1132 seq_printf(m, "RC7\n");
1133 break;
1134 default:
1135 seq_printf(m, "Unknown\n");
1136 break;
1137 }
1138
1139 seq_printf(m, "Core Power Down: %s\n",
1140 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1141
1142 /* Not exactly sure what this is */
1143 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1144 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1145 seq_printf(m, "RC6 residency since boot: %u\n",
1146 I915_READ(GEN6_GT_GFX_RC6));
1147 seq_printf(m, "RC6+ residency since boot: %u\n",
1148 I915_READ(GEN6_GT_GFX_RC6p));
1149 seq_printf(m, "RC6++ residency since boot: %u\n",
1150 I915_READ(GEN6_GT_GFX_RC6pp));
1151
4d85529d
BW		 1152 return 0;
1153}
1154
1155static int i915_drpc_info(struct seq_file *m, void *unused)
1156{
1157 struct drm_info_node *node = (struct drm_info_node *) m->private;
1158 struct drm_device *dev = node->minor->dev;
1159
1160 if (IS_GEN6(dev) || IS_GEN7(dev))
1161 return gen6_drpc_info(m);
1162 else
1163 return ironlake_drpc_info(m);
1164}
1165
b5e50c3f
JB		 1166static int i915_fbc_status(struct seq_file *m, void *unused)
1167{
1168 struct drm_info_node *node = (struct drm_info_node *) m->private;
1169 struct drm_device *dev = node->minor->dev;
b5e50c3f 1170 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1171
ee5382ae 1172 if (!I915_HAS_FBC(dev)) {
b5e50c3f
JB		 1173 seq_printf(m, "FBC unsupported on this chipset\n");
1174 return 0;
1175 }
1176
ee5382ae 1177 if (intel_fbc_enabled(dev)) {
b5e50c3f
JB		 1178 seq_printf(m, "FBC enabled\n");
1179 } else {
1180 seq_printf(m, "FBC disabled: ");
1181 switch (dev_priv->no_fbc_reason) {
bed4a673
CW		 1182 case FBC_NO_OUTPUT:
1183 seq_printf(m, "no outputs");
1184 break;
b5e50c3f
JB		 1185 case FBC_STOLEN_TOO_SMALL:
1186 seq_printf(m, "not enough stolen memory");
1187 break;
1188 case FBC_UNSUPPORTED_MODE:
1189 seq_printf(m, "mode not supported");
1190 break;
1191 case FBC_MODE_TOO_LARGE:
1192 seq_printf(m, "mode too large");
1193 break;
1194 case FBC_BAD_PLANE:
1195 seq_printf(m, "FBC unsupported on plane");
1196 break;
1197 case FBC_NOT_TILED:
1198 seq_printf(m, "scanout buffer not tiled");
1199 break;
9c928d16
JB		 1200 case FBC_MULTIPLE_PIPES:
1201 seq_printf(m, "multiple pipes are enabled");
1202 break;
c1a9f047
JB		 1203 case FBC_MODULE_PARAM:
1204 seq_printf(m, "disabled per module param (default off)");
1205 break;
b5e50c3f
JB		 1206 default:
1207 seq_printf(m, "unknown reason");
1208 }
1209 seq_printf(m, "\n");
1210 }
1211 return 0;
1212}
1213
4a9bef37
JB		 1214static int i915_sr_status(struct seq_file *m, void *unused)
1215{
1216 struct drm_info_node *node = (struct drm_info_node *) m->private;
1217 struct drm_device *dev = node->minor->dev;
1218 drm_i915_private_t *dev_priv = dev->dev_private;
1219 bool sr_enabled = false;
1220
1398261a 1221 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1222 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1223 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1224 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1225 else if (IS_I915GM(dev))
1226 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1227 else if (IS_PINEVIEW(dev))
1228 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1229
5ba2aaaa
CW		 1230 seq_printf(m, "self-refresh: %s\n",
1231 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1232
1233 return 0;
1234}
1235
7648fa99
JB		 1236static int i915_emon_status(struct seq_file *m, void *unused)
1237{
1238 struct drm_info_node *node = (struct drm_info_node *) m->private;
1239 struct drm_device *dev = node->minor->dev;
1240 drm_i915_private_t *dev_priv = dev->dev_private;
1241 unsigned long temp, chipset, gfx;
de227ef0
CW		 1242 int ret;
1243
582be6b4
CW		 1244 if (!IS_GEN5(dev))
1245 return -ENODEV;
1246
de227ef0
CW		 1247 ret = mutex_lock_interruptible(&dev->struct_mutex);
1248 if (ret)
1249 return ret;
7648fa99
JB		 1250
1251 temp = i915_mch_val(dev_priv);
1252 chipset = i915_chipset_val(dev_priv);
1253 gfx = i915_gfx_val(dev_priv);
de227ef0 1254 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1255
1256 seq_printf(m, "GMCH temp: %ld\n", temp);
1257 seq_printf(m, "Chipset power: %ld\n", chipset);
1258 seq_printf(m, "GFX power: %ld\n", gfx);
1259 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1260
1261 return 0;
1262}
1263
23b2f8bb
JB		 1264static int i915_ring_freq_table(struct seq_file *m, void *unused)
1265{
1266 struct drm_info_node *node = (struct drm_info_node *) m->private;
1267 struct drm_device *dev = node->minor->dev;
1268 drm_i915_private_t *dev_priv = dev->dev_private;
1269 int ret;
1270 int gpu_freq, ia_freq;
1271
1c70c0ce 1272 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
23b2f8bb
JB		 1273 seq_printf(m, "unsupported on this chipset\n");
1274 return 0;
1275 }
1276
1277 ret = mutex_lock_interruptible(&dev->struct_mutex);
1278 if (ret)
1279 return ret;
1280
1281 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1282
c6a828d3
DV		 1283 for (gpu_freq = dev_priv->rps.min_delay;
1284 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1285 gpu_freq++) {
42c0526c
BW		 1286 ia_freq = gpu_freq;
1287 sandybridge_pcode_read(dev_priv,
1288 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1289 &ia_freq);
c8735b0c 1290 seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
23b2f8bb
JB		 1291 }
1292
1293 mutex_unlock(&dev->struct_mutex);
1294
1295 return 0;
1296}
1297
7648fa99
JB		 1298static int i915_gfxec(struct seq_file *m, void *unused)
1299{
1300 struct drm_info_node *node = (struct drm_info_node *) m->private;
1301 struct drm_device *dev = node->minor->dev;
1302 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1303 int ret;
1304
1305 ret = mutex_lock_interruptible(&dev->struct_mutex);
1306 if (ret)
1307 return ret;
7648fa99
JB		 1308
1309 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1310
616fdb5a
BW		 1311 mutex_unlock(&dev->struct_mutex);
1312
7648fa99
JB		 1313 return 0;
1314}
1315
44834a67
CW		 1316static int i915_opregion(struct seq_file *m, void *unused)
1317{
1318 struct drm_info_node *node = (struct drm_info_node *) m->private;
1319 struct drm_device *dev = node->minor->dev;
1320 drm_i915_private_t *dev_priv = dev->dev_private;
1321 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1322 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1323 int ret;
1324
0d38f009
DV		 1325 if (data == NULL)
1326 return -ENOMEM;
1327
44834a67
CW		 1328 ret = mutex_lock_interruptible(&dev->struct_mutex);
1329 if (ret)
0d38f009 1330 goto out;
44834a67 1331
0d38f009
DV		 1332 if (opregion->header) {
1333 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1334 seq_write(m, data, OPREGION_SIZE);
1335 }
44834a67
CW		 1336
1337 mutex_unlock(&dev->struct_mutex);
1338
0d38f009
DV		 1339out:
1340 kfree(data);
44834a67
CW		 1341 return 0;
1342}
1343
37811fcc
CW		 1344static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1345{
1346 struct drm_info_node *node = (struct drm_info_node *) m->private;
1347 struct drm_device *dev = node->minor->dev;
1348 drm_i915_private_t *dev_priv = dev->dev_private;
1349 struct intel_fbdev *ifbdev;
1350 struct intel_framebuffer *fb;
1351 int ret;
1352
1353 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1354 if (ret)
1355 return ret;
1356
1357 ifbdev = dev_priv->fbdev;
1358 fb = to_intel_framebuffer(ifbdev->helper.fb);
1359
1360 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1361 fb->base.width,
1362 fb->base.height,
1363 fb->base.depth,
1364 fb->base.bits_per_pixel);
05394f39 1365 describe_obj(m, fb->obj);
37811fcc
CW		 1366 seq_printf(m, "\n");
1367
1368 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1369 if (&fb->base == ifbdev->helper.fb)
1370 continue;
1371
1372 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1373 fb->base.width,
1374 fb->base.height,
1375 fb->base.depth,
1376 fb->base.bits_per_pixel);
05394f39 1377 describe_obj(m, fb->obj);
37811fcc
CW		 1378 seq_printf(m, "\n");
1379 }
1380
1381 mutex_unlock(&dev->mode_config.mutex);
1382
1383 return 0;
1384}
1385
e76d3630
BW		 1386static int i915_context_status(struct seq_file *m, void *unused)
1387{
1388 struct drm_info_node *node = (struct drm_info_node *) m->private;
1389 struct drm_device *dev = node->minor->dev;
1390 drm_i915_private_t *dev_priv = dev->dev_private;
1391 int ret;
1392
1393 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1394 if (ret)
1395 return ret;
1396
dc501fbc
BW		 1397 if (dev_priv->pwrctx) {
1398 seq_printf(m, "power context ");
1399 describe_obj(m, dev_priv->pwrctx);
1400 seq_printf(m, "\n");
1401 }
e76d3630 1402
dc501fbc
BW		 1403 if (dev_priv->renderctx) {
1404 seq_printf(m, "render context ");
1405 describe_obj(m, dev_priv->renderctx);
1406 seq_printf(m, "\n");
1407 }
e76d3630
BW		 1408
1409 mutex_unlock(&dev->mode_config.mutex);
1410
1411 return 0;
1412}
1413
6d794d42
BW		 1414static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1415{
1416 struct drm_info_node *node = (struct drm_info_node *) m->private;
1417 struct drm_device *dev = node->minor->dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
9f1f46a4 1419 unsigned forcewake_count;
6d794d42 1420
9f1f46a4
DV		 1421 spin_lock_irq(&dev_priv->gt_lock);
1422 forcewake_count = dev_priv->forcewake_count;
1423 spin_unlock_irq(&dev_priv->gt_lock);
6d794d42 1424
9f1f46a4 1425 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1426
1427 return 0;
1428}
1429
ea16a3cd
DV		 1430static const char *swizzle_string(unsigned swizzle)
1431{
1432 switch(swizzle) {
1433 case I915_BIT_6_SWIZZLE_NONE:
1434 return "none";
1435 case I915_BIT_6_SWIZZLE_9:
1436 return "bit9";
1437 case I915_BIT_6_SWIZZLE_9_10:
1438 return "bit9/bit10";
1439 case I915_BIT_6_SWIZZLE_9_11:
1440 return "bit9/bit11";
1441 case I915_BIT_6_SWIZZLE_9_10_11:
1442 return "bit9/bit10/bit11";
1443 case I915_BIT_6_SWIZZLE_9_17:
1444 return "bit9/bit17";
1445 case I915_BIT_6_SWIZZLE_9_10_17:
1446 return "bit9/bit10/bit17";
1447 case I915_BIT_6_SWIZZLE_UNKNOWN:
1448 return "unkown";
1449 }
1450
1451 return "bug";
1452}
1453
1454static int i915_swizzle_info(struct seq_file *m, void *data)
1455{
1456 struct drm_info_node *node = (struct drm_info_node *) m->private;
1457 struct drm_device *dev = node->minor->dev;
1458 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1459 int ret;
1460
1461 ret = mutex_lock_interruptible(&dev->struct_mutex);
1462 if (ret)
1463 return ret;
ea16a3cd 1464
ea16a3cd
DV		 1465 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1466 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1467 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1468 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1469
1470 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1471 seq_printf(m, "DDC = 0x%08x\n",
1472 I915_READ(DCC));
1473 seq_printf(m, "C0DRB3 = 0x%04x\n",
1474 I915_READ16(C0DRB3));
1475 seq_printf(m, "C1DRB3 = 0x%04x\n",
1476 I915_READ16(C1DRB3));
3fa7d235
DV		 1477 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1478 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1479 I915_READ(MAD_DIMM_C0));
1480 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1481 I915_READ(MAD_DIMM_C1));
1482 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1483 I915_READ(MAD_DIMM_C2));
1484 seq_printf(m, "TILECTL = 0x%08x\n",
1485 I915_READ(TILECTL));
1486 seq_printf(m, "ARB_MODE = 0x%08x\n",
1487 I915_READ(ARB_MODE));
1488 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1489 I915_READ(DISP_ARB_CTL));
ea16a3cd
DV		 1490 }
1491 mutex_unlock(&dev->struct_mutex);
1492
1493 return 0;
1494}
1495
3cf17fc5
DV		 1496static int i915_ppgtt_info(struct seq_file *m, void *data)
1497{
1498 struct drm_info_node *node = (struct drm_info_node *) m->private;
1499 struct drm_device *dev = node->minor->dev;
1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 struct intel_ring_buffer *ring;
1502 int i, ret;
1503
1504
1505 ret = mutex_lock_interruptible(&dev->struct_mutex);
1506 if (ret)
1507 return ret;
1508 if (INTEL_INFO(dev)->gen == 6)
1509 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1510
a2c7f6fd 1511 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1512 seq_printf(m, "%s\n", ring->name);
1513 if (INTEL_INFO(dev)->gen == 7)
1514 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1515 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1516 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1517 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1518 }
1519 if (dev_priv->mm.aliasing_ppgtt) {
1520 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1521
1522 seq_printf(m, "aliasing PPGTT:\n");
1523 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1524 }
1525 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1526 mutex_unlock(&dev->struct_mutex);
1527
1528 return 0;
1529}
1530
57f350b6
JB		 1531static int i915_dpio_info(struct seq_file *m, void *data)
1532{
1533 struct drm_info_node *node = (struct drm_info_node *) m->private;
1534 struct drm_device *dev = node->minor->dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 int ret;
1537
1538
1539 if (!IS_VALLEYVIEW(dev)) {
1540 seq_printf(m, "unsupported\n");
1541 return 0;
1542 }
1543
1544 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1545 if (ret)
1546 return ret;
1547
1548 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1549
1550 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1551 intel_dpio_read(dev_priv, _DPIO_DIV_A));
1552 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1553 intel_dpio_read(dev_priv, _DPIO_DIV_B));
1554
1555 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1556 intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
1557 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1558 intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
1559
1560 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1561 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1562 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1563 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1564
1565 seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1566 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
1567 seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1568 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
1569
1570 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1571 intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1572
1573 mutex_unlock(&dev->mode_config.mutex);
1574
1575 return 0;
1576}
1577
f3cd474b
CW		 1578static ssize_t
1579i915_wedged_read(struct file *filp,
1580 char __user *ubuf,
1581 size_t max,
1582 loff_t *ppos)
1583{
1584 struct drm_device *dev = filp->private_data;
1585 drm_i915_private_t *dev_priv = dev->dev_private;
1586 char buf[80];
1587 int len;
1588
0206e353 1589 len = snprintf(buf, sizeof(buf),
f3cd474b
CW		 1590 "wedged : %d\n",
1591 atomic_read(&dev_priv->mm.wedged));
1592
0206e353
AJ		 1593 if (len > sizeof(buf))
1594 len = sizeof(buf);
f4433a8d 1595
f3cd474b
CW		 1596 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1597}
1598
1599static ssize_t
1600i915_wedged_write(struct file *filp,
1601 const char __user *ubuf,
1602 size_t cnt,
1603 loff_t *ppos)
1604{
1605 struct drm_device *dev = filp->private_data;
f3cd474b
CW		 1606 char buf[20];
1607 int val = 1;
1608
1609 if (cnt > 0) {
0206e353 1610 if (cnt > sizeof(buf) - 1)
f3cd474b
CW		 1611 return -EINVAL;
1612
1613 if (copy_from_user(buf, ubuf, cnt))
1614 return -EFAULT;
1615 buf[cnt] = 0;
1616
1617 val = simple_strtoul(buf, NULL, 0);
1618 }
1619
1620 DRM_INFO("Manually setting wedged to %d\n", val);
527f9e90 1621 i915_handle_error(dev, val);
f3cd474b
CW		 1622
1623 return cnt;
1624}
1625
1626static const struct file_operations i915_wedged_fops = {
1627 .owner = THIS_MODULE,
234e3405 1628 .open = simple_open,
f3cd474b
CW		 1629 .read = i915_wedged_read,
1630 .write = i915_wedged_write,
6038f373 1631 .llseek = default_llseek,
f3cd474b
CW		 1632};
1633
e5eb3d63
DV		 1634static ssize_t
1635i915_ring_stop_read(struct file *filp,
1636 char __user *ubuf,
1637 size_t max,
1638 loff_t *ppos)
1639{
1640 struct drm_device *dev = filp->private_data;
1641 drm_i915_private_t *dev_priv = dev->dev_private;
1642 char buf[20];
1643 int len;
1644
1645 len = snprintf(buf, sizeof(buf),
1646 "0x%08x\n", dev_priv->stop_rings);
1647
1648 if (len > sizeof(buf))
1649 len = sizeof(buf);
1650
1651 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1652}
1653
1654static ssize_t
1655i915_ring_stop_write(struct file *filp,
1656 const char __user *ubuf,
1657 size_t cnt,
1658 loff_t *ppos)
1659{
1660 struct drm_device *dev = filp->private_data;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662 char buf[20];
22bcfc6a 1663 int val = 0, ret;
e5eb3d63
DV		 1664
1665 if (cnt > 0) {
1666 if (cnt > sizeof(buf) - 1)
1667 return -EINVAL;
1668
1669 if (copy_from_user(buf, ubuf, cnt))
1670 return -EFAULT;
1671 buf[cnt] = 0;
1672
1673 val = simple_strtoul(buf, NULL, 0);
1674 }
1675
1676 DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
1677
22bcfc6a
DV		 1678 ret = mutex_lock_interruptible(&dev->struct_mutex);
1679 if (ret)
1680 return ret;
1681
e5eb3d63
DV		 1682 dev_priv->stop_rings = val;
1683 mutex_unlock(&dev->struct_mutex);
1684
1685 return cnt;
1686}
1687
1688static const struct file_operations i915_ring_stop_fops = {
1689 .owner = THIS_MODULE,
1690 .open = simple_open,
1691 .read = i915_ring_stop_read,
1692 .write = i915_ring_stop_write,
1693 .llseek = default_llseek,
1694};
d5442303 1695
358733e9
JB		 1696static ssize_t
1697i915_max_freq_read(struct file *filp,
1698 char __user *ubuf,
1699 size_t max,
1700 loff_t *ppos)
1701{
1702 struct drm_device *dev = filp->private_data;
1703 drm_i915_private_t *dev_priv = dev->dev_private;
1704 char buf[80];
004777cb
DV		 1705 int len, ret;
1706
1707 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1708 return -ENODEV;
1709
1710 ret = mutex_lock_interruptible(&dev->struct_mutex);
1711 if (ret)
1712 return ret;
358733e9 1713
0206e353 1714 len = snprintf(buf, sizeof(buf),
c8735b0c 1715 "max freq: %d\n", dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER);
004777cb 1716 mutex_unlock(&dev->struct_mutex);
358733e9 1717
0206e353
AJ		 1718 if (len > sizeof(buf))
1719 len = sizeof(buf);
358733e9
JB		 1720
1721 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1722}
1723
1724static ssize_t
1725i915_max_freq_write(struct file *filp,
1726 const char __user *ubuf,
1727 size_t cnt,
1728 loff_t *ppos)
1729{
1730 struct drm_device *dev = filp->private_data;
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 char buf[20];
004777cb
DV		 1733 int val = 1, ret;
1734
1735 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1736 return -ENODEV;
358733e9
JB		 1737
1738 if (cnt > 0) {
0206e353 1739 if (cnt > sizeof(buf) - 1)
358733e9
JB		 1740 return -EINVAL;
1741
1742 if (copy_from_user(buf, ubuf, cnt))
1743 return -EFAULT;
1744 buf[cnt] = 0;
1745
1746 val = simple_strtoul(buf, NULL, 0);
1747 }
1748
1749 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1750
004777cb
DV		 1751 ret = mutex_lock_interruptible(&dev->struct_mutex);
1752 if (ret)
1753 return ret;
1754
358733e9
JB		 1755 /*
1756 * Turbo will still be enabled, but won't go above the set value.
1757 */
c8735b0c 1758 dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER;
358733e9 1759
c8735b0c 1760 gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
004777cb 1761 mutex_unlock(&dev->struct_mutex);
358733e9
JB		 1762
1763 return cnt;
1764}
1765
1766static const struct file_operations i915_max_freq_fops = {
1767 .owner = THIS_MODULE,
234e3405 1768 .open = simple_open,
358733e9
JB		 1769 .read = i915_max_freq_read,
1770 .write = i915_max_freq_write,
1771 .llseek = default_llseek,
1772};
1773
1523c310
JB		 1774static ssize_t
1775i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
1776 loff_t *ppos)
1777{
1778 struct drm_device *dev = filp->private_data;
1779 drm_i915_private_t *dev_priv = dev->dev_private;
1780 char buf[80];
004777cb
DV		 1781 int len, ret;
1782
1783 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1784 return -ENODEV;
1785
1786 ret = mutex_lock_interruptible(&dev->struct_mutex);
1787 if (ret)
1788 return ret;
1523c310
JB		 1789
1790 len = snprintf(buf, sizeof(buf),
c8735b0c 1791 "min freq: %d\n", dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER);
004777cb 1792 mutex_unlock(&dev->struct_mutex);
1523c310
JB		 1793
1794 if (len > sizeof(buf))
1795 len = sizeof(buf);
1796
1797 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1798}
1799
1800static ssize_t
1801i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
1802 loff_t *ppos)
1803{
1804 struct drm_device *dev = filp->private_data;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 char buf[20];
004777cb
DV		 1807 int val = 1, ret;
1808
1809 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1810 return -ENODEV;
1523c310
JB		 1811
1812 if (cnt > 0) {
1813 if (cnt > sizeof(buf) - 1)
1814 return -EINVAL;
1815
1816 if (copy_from_user(buf, ubuf, cnt))
1817 return -EFAULT;
1818 buf[cnt] = 0;
1819
1820 val = simple_strtoul(buf, NULL, 0);
1821 }
1822
1823 DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
1824
004777cb
DV		 1825 ret = mutex_lock_interruptible(&dev->struct_mutex);
1826 if (ret)
1827 return ret;
1828
1523c310
JB		 1829 /*
1830 * Turbo will still be enabled, but won't go below the set value.
1831 */
c8735b0c 1832 dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER;
1523c310 1833
c8735b0c 1834 gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
004777cb 1835 mutex_unlock(&dev->struct_mutex);
1523c310
JB		 1836
1837 return cnt;
1838}
1839
1840static const struct file_operations i915_min_freq_fops = {
1841 .owner = THIS_MODULE,
1842 .open = simple_open,
1843 .read = i915_min_freq_read,
1844 .write = i915_min_freq_write,
1845 .llseek = default_llseek,
1846};
1847
07b7ddd9
JB		 1848static ssize_t
1849i915_cache_sharing_read(struct file *filp,
1850 char __user *ubuf,
1851 size_t max,
1852 loff_t *ppos)
1853{
1854 struct drm_device *dev = filp->private_data;
1855 drm_i915_private_t *dev_priv = dev->dev_private;
1856 char buf[80];
1857 u32 snpcr;
22bcfc6a 1858 int len, ret;
07b7ddd9 1859
004777cb
DV		 1860 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1861 return -ENODEV;
1862
22bcfc6a
DV		 1863 ret = mutex_lock_interruptible(&dev->struct_mutex);
1864 if (ret)
1865 return ret;
1866
07b7ddd9
JB		 1867 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1868 mutex_unlock(&dev_priv->dev->struct_mutex);
1869
0206e353 1870 len = snprintf(buf, sizeof(buf),
07b7ddd9
JB		 1871 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1872 GEN6_MBC_SNPCR_SHIFT);
1873
0206e353
AJ		 1874 if (len > sizeof(buf))
1875 len = sizeof(buf);
07b7ddd9
JB		 1876
1877 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1878}
1879
1880static ssize_t
1881i915_cache_sharing_write(struct file *filp,
1882 const char __user *ubuf,
1883 size_t cnt,
1884 loff_t *ppos)
1885{
1886 struct drm_device *dev = filp->private_data;
1887 struct drm_i915_private *dev_priv = dev->dev_private;
1888 char buf[20];
1889 u32 snpcr;
1890 int val = 1;
1891
004777cb
DV		 1892 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1893 return -ENODEV;
1894
07b7ddd9 1895 if (cnt > 0) {
0206e353 1896 if (cnt > sizeof(buf) - 1)
07b7ddd9
JB		 1897 return -EINVAL;
1898
1899 if (copy_from_user(buf, ubuf, cnt))
1900 return -EFAULT;
1901 buf[cnt] = 0;
1902
1903 val = simple_strtoul(buf, NULL, 0);
1904 }
1905
1906 if (val < 0 || val > 3)
1907 return -EINVAL;
1908
1909 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
1910
1911 /* Update the cache sharing policy here as well */
1912 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1913 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1914 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1915 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1916
1917 return cnt;
1918}
1919
1920static const struct file_operations i915_cache_sharing_fops = {
1921 .owner = THIS_MODULE,
234e3405 1922 .open = simple_open,
07b7ddd9
JB		 1923 .read = i915_cache_sharing_read,
1924 .write = i915_cache_sharing_write,
1925 .llseek = default_llseek,
1926};
1927
f3cd474b
CW		 1928/* As the drm_debugfs_init() routines are called before dev->dev_private is
1929 * allocated we need to hook into the minor for release. */
1930static int
1931drm_add_fake_info_node(struct drm_minor *minor,
1932 struct dentry *ent,
1933 const void *key)
1934{
1935 struct drm_info_node *node;
1936
1937 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1938 if (node == NULL) {
1939 debugfs_remove(ent);
1940 return -ENOMEM;
1941 }
1942
1943 node->minor = minor;
1944 node->dent = ent;
1945 node->info_ent = (void *) key;
b3e067c0
MS		 1946
1947 mutex_lock(&minor->debugfs_lock);
1948 list_add(&node->list, &minor->debugfs_list);
1949 mutex_unlock(&minor->debugfs_lock);
f3cd474b
CW		 1950
1951 return 0;
1952}
1953
6d794d42
BW		 1954static int i915_forcewake_open(struct inode *inode, struct file *file)
1955{
1956 struct drm_device *dev = inode->i_private;
1957 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 1958
075edca4 1959 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 1960 return 0;
1961
6d794d42 1962 gen6_gt_force_wake_get(dev_priv);
6d794d42
BW		 1963
1964 return 0;
1965}
1966
c43b5634 1967static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 1968{
1969 struct drm_device *dev = inode->i_private;
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1971
075edca4 1972 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 1973 return 0;
1974
6d794d42 1975 gen6_gt_force_wake_put(dev_priv);
6d794d42
BW		 1976
1977 return 0;
1978}
1979
1980static const struct file_operations i915_forcewake_fops = {
1981 .owner = THIS_MODULE,
1982 .open = i915_forcewake_open,
1983 .release = i915_forcewake_release,
1984};
1985
1986static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
1987{
1988 struct drm_device *dev = minor->dev;
1989 struct dentry *ent;
1990
1991 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 1992 S_IRUSR,
6d794d42
BW		 1993 root, dev,
1994 &i915_forcewake_fops);
1995 if (IS_ERR(ent))
1996 return PTR_ERR(ent);
1997
8eb57294 1998 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 1999}
2000
6a9c308d
DV		 2001static int i915_debugfs_create(struct dentry *root,
2002 struct drm_minor *minor,
2003 const char *name,
2004 const struct file_operations *fops)
07b7ddd9
JB		 2005{
2006 struct drm_device *dev = minor->dev;
2007 struct dentry *ent;
2008
6a9c308d 2009 ent = debugfs_create_file(name,
07b7ddd9
JB		 2010 S_IRUGO | S_IWUSR,
2011 root, dev,
6a9c308d 2012 fops);
07b7ddd9
JB		 2013 if (IS_ERR(ent))
2014 return PTR_ERR(ent);
2015
6a9c308d 2016 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 2017}
2018
27c202ad 2019static struct drm_info_list i915_debugfs_list[] = {
311bd68e 2020 {"i915_capabilities", i915_capabilities, 0},
73aa808f 2021 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 2022 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 2023 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 2024 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 2025 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4e5359cd 2026 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 2027 {"i915_gem_request", i915_gem_request_info, 0},
2028 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 2029 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 2030 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 2031 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2032 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2033 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
f97108d1
JB		 2034 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2035 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2036 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2037 {"i915_inttoext_table", i915_inttoext_table, 0},
2038 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 2039 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 2040 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 2041 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 2042 {"i915_fbc_status", i915_fbc_status, 0},
4a9bef37 2043 {"i915_sr_status", i915_sr_status, 0},
44834a67 2044 {"i915_opregion", i915_opregion, 0},
37811fcc 2045 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 2046 {"i915_context_status", i915_context_status, 0},
6d794d42 2047 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 2048 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 2049 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 2050 {"i915_dpio", i915_dpio_info, 0},
2017263e 2051};
27c202ad 2052#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 2053
27c202ad 2054int i915_debugfs_init(struct drm_minor *minor)
2017263e 2055{
f3cd474b
CW		 2056 int ret;
2057
6a9c308d
DV		 2058 ret = i915_debugfs_create(minor->debugfs_root, minor,
2059 "i915_wedged",
2060 &i915_wedged_fops);
f3cd474b
CW		 2061 if (ret)
2062 return ret;
2063
6d794d42 2064 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 2065 if (ret)
2066 return ret;
6a9c308d
DV		 2067
2068 ret = i915_debugfs_create(minor->debugfs_root, minor,
2069 "i915_max_freq",
2070 &i915_max_freq_fops);
07b7ddd9
JB		 2071 if (ret)
2072 return ret;
6a9c308d 2073
1523c310
JB		 2074 ret = i915_debugfs_create(minor->debugfs_root, minor,
2075 "i915_min_freq",
2076 &i915_min_freq_fops);
2077 if (ret)
2078 return ret;
2079
6a9c308d
DV		 2080 ret = i915_debugfs_create(minor->debugfs_root, minor,
2081 "i915_cache_sharing",
2082 &i915_cache_sharing_fops);
6d794d42
BW		 2083 if (ret)
2084 return ret;
004777cb 2085
e5eb3d63
DV		 2086 ret = i915_debugfs_create(minor->debugfs_root, minor,
2087 "i915_ring_stop",
2088 &i915_ring_stop_fops);
2089 if (ret)
2090 return ret;
6d794d42 2091
d5442303
DV		 2092 ret = i915_debugfs_create(minor->debugfs_root, minor,
2093 "i915_error_state",
2094 &i915_error_state_fops);
2095 if (ret)
2096 return ret;
2097
27c202ad
BG		 2098 return drm_debugfs_create_files(i915_debugfs_list,
2099 I915_DEBUGFS_ENTRIES,
2017263e
BG		 2100 minor->debugfs_root, minor);
2101}
2102
27c202ad 2103void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 2104{
27c202ad
BG		 2105 drm_debugfs_remove_files(i915_debugfs_list,
2106 I915_DEBUGFS_ENTRIES, minor);
6d794d42
BW		 2107 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2108 1, minor);
33db679b
KH		 2109 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
2110 1, minor);
358733e9
JB		 2111 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
2112 1, minor);
1523c310
JB		 2113 drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
2114 1, minor);
07b7ddd9
JB		 2115 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
2116 1, minor);
e5eb3d63
DV		 2117 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2118 1, minor);
6bd459df
DV		 2119 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2120 1, minor);
2017263e
BG		 2121}
2122
2123#endif /* CONFIG_DEBUG_FS */
Linux 6.x block layer and io_uring tree(s)