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drm/i915: call drm_vblank_cleanup() earlier at unload
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
0a4cd7c8 139 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 336 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 337 continue;
338
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
349 if (obj->ring)
350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
ca191b13
BW		 363#define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
366 ++count; \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
369 ++mappable_count; \
370 } \
371 } \
372} while (0)
373
374static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 375{
9f25d007 376 struct drm_info_node *node = m->private;
73aa808f
CW		 377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
6299f992 381 struct drm_i915_gem_object *obj;
5cef07e1 382 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 383 struct drm_file *file;
ca191b13 384 struct i915_vma *vma;
73aa808f
CW		 385 int ret;
386
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
388 if (ret)
389 return ret;
390
6299f992
CW		 391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
394
395 size = count = mappable_size = mappable_count = 0;
35c20a60 396 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
399
400 size = count = mappable_size = mappable_count = 0;
ca191b13 401 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
404
6299f992 405 size = count = mappable_size = mappable_count = 0;
ca191b13 406 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
409
b7abb714 410 size = count = purgeable_size = purgeable_count = 0;
35c20a60 411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 412 size += obj->base.size, ++count;
b7abb714
CW		 413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
415 }
6c085a72
CW		 416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
417
6299f992 418 size = count = mappable_size = mappable_count = 0;
35c20a60 419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 420 if (obj->fault_mappable) {
f343c5f6 421 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 422 ++count;
423 }
424 if (obj->pin_mappable) {
f343c5f6 425 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 426 ++mappable_count;
427 }
b7abb714
CW		 428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
430 ++purgeable_count;
431 }
6299f992 432 }
b7abb714
CW		 433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
6299f992
CW		 435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 count, size);
439
93d18799 440 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 443
267f0c90 444 seq_putc(m, '\n');
2db8e9d6
CW		 445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
3ec2f427 447 struct task_struct *task;
2db8e9d6
CW		 448
449 memset(&stats, 0, sizeof(stats));
6313c204 450 stats.file_priv = file->driver_priv;
5b5ffff0 451 spin_lock(&file->table_lock);
2db8e9d6 452 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 453 spin_unlock(&file->table_lock);
3ec2f427
TH		 454 /*
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
459 */
460 rcu_read_lock();
461 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 463 task ? task->comm : "<unknown>",
2db8e9d6
CW		 464 stats.count,
465 stats.total,
466 stats.active,
467 stats.inactive,
6313c204 468 stats.global,
c67a17e9 469 stats.shared,
2db8e9d6 470 stats.unbound);
3ec2f427 471 rcu_read_unlock();
2db8e9d6
CW		 472 }
473
73aa808f
CW		 474 mutex_unlock(&dev->struct_mutex);
475
476 return 0;
477}
478
aee56cff 479static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 480{
9f25d007 481 struct drm_info_node *node = m->private;
08c18323 482 struct drm_device *dev = node->minor->dev;
1b50247a 483 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
487 int count, ret;
488
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
490 if (ret)
491 return ret;
492
493 total_obj_size = total_gtt_size = count = 0;
35c20a60 494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 496 continue;
497
267f0c90 498 seq_puts(m, " ");
08c18323 499 describe_obj(m, obj);
267f0c90 500 seq_putc(m, '\n');
08c18323 501 total_obj_size += obj->base.size;
f343c5f6 502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 503 count++;
504 }
505
506 mutex_unlock(&dev->struct_mutex);
507
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
510
511 return 0;
512}
513
4e5359cd
SF		 514static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515{
9f25d007 516 struct drm_info_node *node = m->private;
4e5359cd 517 struct drm_device *dev = node->minor->dev;
d6bbafa1 518 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 519 struct intel_crtc *crtc;
8a270ebf
DV		 520 int ret;
521
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
523 if (ret)
524 return ret;
4e5359cd 525
d3fcc808 526 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 529 struct intel_unpin_work *work;
530
5e2d7afc 531 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 532 work = crtc->unpin_work;
533 if (work == NULL) {
9db4a9c7 534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 535 pipe, plane);
536 } else {
d6bbafa1
CW		 537 u32 addr;
538
e7d841ca 539 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 540 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 541 pipe, plane);
542 } else {
9db4a9c7 543 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 544 pipe, plane);
545 }
d6bbafa1
CW		 546 if (work->flip_queued_ring) {
547 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
548 work->flip_queued_ring->name,
549 work->flip_queued_seqno,
550 dev_priv->next_seqno,
551 work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
552 i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
553 work->flip_queued_seqno));
554 } else
555 seq_printf(m, "Flip not associated with any ring\n");
556 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
557 work->flip_queued_vblank,
558 work->flip_ready_vblank,
559 drm_vblank_count(dev, crtc->pipe));
4e5359cd 560 if (work->enable_stall_check)
267f0c90 561 seq_puts(m, "Stall check enabled, ");
4e5359cd 562 else
267f0c90 563 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 564 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 565
d6bbafa1
CW		 566 if (INTEL_INFO(dev)->gen >= 4)
567 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
568 else
569 addr = I915_READ(DSPADDR(crtc->plane));
570 seq_printf(m, "Current scanout address 0x%08x\n", addr);
571
4e5359cd 572 if (work->pending_flip_obj) {
d6bbafa1
CW		 573 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
574 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 575 }
576 }
5e2d7afc 577 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 578 }
579
8a270ebf
DV		 580 mutex_unlock(&dev->struct_mutex);
581
4e5359cd
SF		 582 return 0;
583}
584
2017263e
BG		 585static int i915_gem_request_info(struct seq_file *m, void *data)
586{
9f25d007 587 struct drm_info_node *node = m->private;
2017263e 588 struct drm_device *dev = node->minor->dev;
e277a1f8 589 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 590 struct intel_engine_cs *ring;
2017263e 591 struct drm_i915_gem_request *gem_request;
a2c7f6fd 592 int ret, count, i;
de227ef0
CW		 593
594 ret = mutex_lock_interruptible(&dev->struct_mutex);
595 if (ret)
596 return ret;
2017263e 597
c2c347a9 598 count = 0;
a2c7f6fd
CW		 599 for_each_ring(ring, dev_priv, i) {
600 if (list_empty(&ring->request_list))
601 continue;
602
603 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 604 list_for_each_entry(gem_request,
a2c7f6fd 605 &ring->request_list,
c2c347a9
CW		 606 list) {
607 seq_printf(m, " %d @ %d\n",
608 gem_request->seqno,
609 (int) (jiffies - gem_request->emitted_jiffies));
610 }
611 count++;
2017263e 612 }
de227ef0
CW		 613 mutex_unlock(&dev->struct_mutex);
614
c2c347a9 615 if (count == 0)
267f0c90 616 seq_puts(m, "No requests\n");
c2c347a9 617
2017263e
BG		 618 return 0;
619}
620
b2223497 621static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 622 struct intel_engine_cs *ring)
b2223497
CW		 623{
624 if (ring->get_seqno) {
43a7b924 625 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 626 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 627 }
628}
629
2017263e
BG		 630static int i915_gem_seqno_info(struct seq_file *m, void *data)
631{
9f25d007 632 struct drm_info_node *node = m->private;
2017263e 633 struct drm_device *dev = node->minor->dev;
e277a1f8 634 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 635 struct intel_engine_cs *ring;
1ec14ad3 636 int ret, i;
de227ef0
CW		 637
638 ret = mutex_lock_interruptible(&dev->struct_mutex);
639 if (ret)
640 return ret;
c8c8fb33 641 intel_runtime_pm_get(dev_priv);
2017263e 642
a2c7f6fd
CW		 643 for_each_ring(ring, dev_priv, i)
644 i915_ring_seqno_info(m, ring);
de227ef0 645
c8c8fb33 646 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 647 mutex_unlock(&dev->struct_mutex);
648
2017263e
BG		 649 return 0;
650}
651
652
653static int i915_interrupt_info(struct seq_file *m, void *data)
654{
9f25d007 655 struct drm_info_node *node = m->private;
2017263e 656 struct drm_device *dev = node->minor->dev;
e277a1f8 657 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 658 struct intel_engine_cs *ring;
9db4a9c7 659 int ret, i, pipe;
de227ef0
CW		 660
661 ret = mutex_lock_interruptible(&dev->struct_mutex);
662 if (ret)
663 return ret;
c8c8fb33 664 intel_runtime_pm_get(dev_priv);
2017263e 665
74e1ca8c 666 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 667 seq_printf(m, "Master Interrupt Control:\t%08x\n",
668 I915_READ(GEN8_MASTER_IRQ));
669
670 seq_printf(m, "Display IER:\t%08x\n",
671 I915_READ(VLV_IER));
672 seq_printf(m, "Display IIR:\t%08x\n",
673 I915_READ(VLV_IIR));
674 seq_printf(m, "Display IIR_RW:\t%08x\n",
675 I915_READ(VLV_IIR_RW));
676 seq_printf(m, "Display IMR:\t%08x\n",
677 I915_READ(VLV_IMR));
055e393f 678 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 679 seq_printf(m, "Pipe %c stat:\t%08x\n",
680 pipe_name(pipe),
681 I915_READ(PIPESTAT(pipe)));
682
683 seq_printf(m, "Port hotplug:\t%08x\n",
684 I915_READ(PORT_HOTPLUG_EN));
685 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
686 I915_READ(VLV_DPFLIPSTAT));
687 seq_printf(m, "DPINVGTT:\t%08x\n",
688 I915_READ(DPINVGTT));
689
690 for (i = 0; i < 4; i++) {
691 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
692 i, I915_READ(GEN8_GT_IMR(i)));
693 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
694 i, I915_READ(GEN8_GT_IIR(i)));
695 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
696 i, I915_READ(GEN8_GT_IER(i)));
697 }
698
699 seq_printf(m, "PCU interrupt mask:\t%08x\n",
700 I915_READ(GEN8_PCU_IMR));
701 seq_printf(m, "PCU interrupt identity:\t%08x\n",
702 I915_READ(GEN8_PCU_IIR));
703 seq_printf(m, "PCU interrupt enable:\t%08x\n",
704 I915_READ(GEN8_PCU_IER));
705 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 706 seq_printf(m, "Master Interrupt Control:\t%08x\n",
707 I915_READ(GEN8_MASTER_IRQ));
708
709 for (i = 0; i < 4; i++) {
710 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
711 i, I915_READ(GEN8_GT_IMR(i)));
712 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
713 i, I915_READ(GEN8_GT_IIR(i)));
714 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
715 i, I915_READ(GEN8_GT_IER(i)));
716 }
717
055e393f 718 for_each_pipe(dev_priv, pipe) {
f458ebbc 719 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 720 POWER_DOMAIN_PIPE(pipe))) {
721 seq_printf(m, "Pipe %c power disabled\n",
722 pipe_name(pipe));
723 continue;
724 }
a123f157 725 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 726 pipe_name(pipe),
727 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 728 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 729 pipe_name(pipe),
730 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 731 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 732 pipe_name(pipe),
733 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 734 }
735
736 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
737 I915_READ(GEN8_DE_PORT_IMR));
738 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
739 I915_READ(GEN8_DE_PORT_IIR));
740 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
741 I915_READ(GEN8_DE_PORT_IER));
742
743 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
744 I915_READ(GEN8_DE_MISC_IMR));
745 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
746 I915_READ(GEN8_DE_MISC_IIR));
747 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
748 I915_READ(GEN8_DE_MISC_IER));
749
750 seq_printf(m, "PCU interrupt mask:\t%08x\n",
751 I915_READ(GEN8_PCU_IMR));
752 seq_printf(m, "PCU interrupt identity:\t%08x\n",
753 I915_READ(GEN8_PCU_IIR));
754 seq_printf(m, "PCU interrupt enable:\t%08x\n",
755 I915_READ(GEN8_PCU_IER));
756 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 757 seq_printf(m, "Display IER:\t%08x\n",
758 I915_READ(VLV_IER));
759 seq_printf(m, "Display IIR:\t%08x\n",
760 I915_READ(VLV_IIR));
761 seq_printf(m, "Display IIR_RW:\t%08x\n",
762 I915_READ(VLV_IIR_RW));
763 seq_printf(m, "Display IMR:\t%08x\n",
764 I915_READ(VLV_IMR));
055e393f 765 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 766 seq_printf(m, "Pipe %c stat:\t%08x\n",
767 pipe_name(pipe),
768 I915_READ(PIPESTAT(pipe)));
769
770 seq_printf(m, "Master IER:\t%08x\n",
771 I915_READ(VLV_MASTER_IER));
772
773 seq_printf(m, "Render IER:\t%08x\n",
774 I915_READ(GTIER));
775 seq_printf(m, "Render IIR:\t%08x\n",
776 I915_READ(GTIIR));
777 seq_printf(m, "Render IMR:\t%08x\n",
778 I915_READ(GTIMR));
779
780 seq_printf(m, "PM IER:\t\t%08x\n",
781 I915_READ(GEN6_PMIER));
782 seq_printf(m, "PM IIR:\t\t%08x\n",
783 I915_READ(GEN6_PMIIR));
784 seq_printf(m, "PM IMR:\t\t%08x\n",
785 I915_READ(GEN6_PMIMR));
786
787 seq_printf(m, "Port hotplug:\t%08x\n",
788 I915_READ(PORT_HOTPLUG_EN));
789 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
790 I915_READ(VLV_DPFLIPSTAT));
791 seq_printf(m, "DPINVGTT:\t%08x\n",
792 I915_READ(DPINVGTT));
793
794 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 795 seq_printf(m, "Interrupt enable: %08x\n",
796 I915_READ(IER));
797 seq_printf(m, "Interrupt identity: %08x\n",
798 I915_READ(IIR));
799 seq_printf(m, "Interrupt mask: %08x\n",
800 I915_READ(IMR));
055e393f 801 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 802 seq_printf(m, "Pipe %c stat: %08x\n",
803 pipe_name(pipe),
804 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 805 } else {
806 seq_printf(m, "North Display Interrupt enable: %08x\n",
807 I915_READ(DEIER));
808 seq_printf(m, "North Display Interrupt identity: %08x\n",
809 I915_READ(DEIIR));
810 seq_printf(m, "North Display Interrupt mask: %08x\n",
811 I915_READ(DEIMR));
812 seq_printf(m, "South Display Interrupt enable: %08x\n",
813 I915_READ(SDEIER));
814 seq_printf(m, "South Display Interrupt identity: %08x\n",
815 I915_READ(SDEIIR));
816 seq_printf(m, "South Display Interrupt mask: %08x\n",
817 I915_READ(SDEIMR));
818 seq_printf(m, "Graphics Interrupt enable: %08x\n",
819 I915_READ(GTIER));
820 seq_printf(m, "Graphics Interrupt identity: %08x\n",
821 I915_READ(GTIIR));
822 seq_printf(m, "Graphics Interrupt mask: %08x\n",
823 I915_READ(GTIMR));
824 }
a2c7f6fd 825 for_each_ring(ring, dev_priv, i) {
a123f157 826 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 827 seq_printf(m,
828 "Graphics Interrupt mask (%s): %08x\n",
829 ring->name, I915_READ_IMR(ring));
9862e600 830 }
a2c7f6fd 831 i915_ring_seqno_info(m, ring);
9862e600 832 }
c8c8fb33 833 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 834 mutex_unlock(&dev->struct_mutex);
835
2017263e
BG		 836 return 0;
837}
838
a6172a80
CW		 839static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
840{
9f25d007 841 struct drm_info_node *node = m->private;
a6172a80 842 struct drm_device *dev = node->minor->dev;
e277a1f8 843 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 844 int i, ret;
845
846 ret = mutex_lock_interruptible(&dev->struct_mutex);
847 if (ret)
848 return ret;
a6172a80
CW		 849
850 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
851 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
852 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 853 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 854
6c085a72
CW		 855 seq_printf(m, "Fence %d, pin count = %d, object = ",
856 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 857 if (obj == NULL)
267f0c90 858 seq_puts(m, "unused");
c2c347a9 859 else
05394f39 860 describe_obj(m, obj);
267f0c90 861 seq_putc(m, '\n');
a6172a80
CW		 862 }
863
05394f39 864 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 865 return 0;
866}
867
2017263e
BG		 868static int i915_hws_info(struct seq_file *m, void *data)
869{
9f25d007 870 struct drm_info_node *node = m->private;
2017263e 871 struct drm_device *dev = node->minor->dev;
e277a1f8 872 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 873 struct intel_engine_cs *ring;
1a240d4d 874 const u32 *hws;
4066c0ae
CW		 875 int i;
876
1ec14ad3 877 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 878 hws = ring->status_page.page_addr;
2017263e
BG		 879 if (hws == NULL)
880 return 0;
881
882 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
883 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
884 i * 4,
885 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
886 }
887 return 0;
888}
889
d5442303
DV		 890static ssize_t
891i915_error_state_write(struct file *filp,
892 const char __user *ubuf,
893 size_t cnt,
894 loff_t *ppos)
895{
edc3d884 896 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 897 struct drm_device *dev = error_priv->dev;
22bcfc6a 898 int ret;
d5442303
DV		 899
900 DRM_DEBUG_DRIVER("Resetting error state\n");
901
22bcfc6a
DV		 902 ret = mutex_lock_interruptible(&dev->struct_mutex);
903 if (ret)
904 return ret;
905
d5442303
DV		 906 i915_destroy_error_state(dev);
907 mutex_unlock(&dev->struct_mutex);
908
909 return cnt;
910}
911
912static int i915_error_state_open(struct inode *inode, struct file *file)
913{
914 struct drm_device *dev = inode->i_private;
d5442303 915 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 916
917 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
918 if (!error_priv)
919 return -ENOMEM;
920
921 error_priv->dev = dev;
922
95d5bfb3 923 i915_error_state_get(dev, error_priv);
d5442303 924
edc3d884
MK		 925 file->private_data = error_priv;
926
927 return 0;
d5442303
DV		 928}
929
930static int i915_error_state_release(struct inode *inode, struct file *file)
931{
edc3d884 932 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 933
95d5bfb3 934 i915_error_state_put(error_priv);
d5442303
DV		 935 kfree(error_priv);
936
edc3d884
MK		 937 return 0;
938}
939
4dc955f7
MK		 940static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
941 size_t count, loff_t *pos)
942{
943 struct i915_error_state_file_priv *error_priv = file->private_data;
944 struct drm_i915_error_state_buf error_str;
945 loff_t tmp_pos = 0;
946 ssize_t ret_count = 0;
947 int ret;
948
0a4cd7c8 949 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 950 if (ret)
951 return ret;
edc3d884 952
fc16b48b 953 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 954 if (ret)
955 goto out;
956
edc3d884
MK		 957 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
958 error_str.buf,
959 error_str.bytes);
960
961 if (ret_count < 0)
962 ret = ret_count;
963 else
964 *pos = error_str.start + ret_count;
965out:
4dc955f7 966 i915_error_state_buf_release(&error_str);
edc3d884 967 return ret ?: ret_count;
d5442303
DV		 968}
969
970static const struct file_operations i915_error_state_fops = {
971 .owner = THIS_MODULE,
972 .open = i915_error_state_open,
edc3d884 973 .read = i915_error_state_read,
d5442303
DV		 974 .write = i915_error_state_write,
975 .llseek = default_llseek,
976 .release = i915_error_state_release,
977};
978
647416f9
KC		 979static int
980i915_next_seqno_get(void *data, u64 *val)
40633219 981{
647416f9 982 struct drm_device *dev = data;
e277a1f8 983 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 984 int ret;
985
986 ret = mutex_lock_interruptible(&dev->struct_mutex);
987 if (ret)
988 return ret;
989
647416f9 990 *val = dev_priv->next_seqno;
40633219
MK		 991 mutex_unlock(&dev->struct_mutex);
992
647416f9 993 return 0;
40633219
MK		 994}
995
647416f9
KC		 996static int
997i915_next_seqno_set(void *data, u64 val)
998{
999 struct drm_device *dev = data;
40633219
MK		 1000 int ret;
1001
40633219
MK		 1002 ret = mutex_lock_interruptible(&dev->struct_mutex);
1003 if (ret)
1004 return ret;
1005
e94fbaa8 1006 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1007 mutex_unlock(&dev->struct_mutex);
1008
647416f9 1009 return ret;
40633219
MK		 1010}
1011
647416f9
KC		 1012DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1013 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1014 "0x%llx\n");
40633219 1015
adb4bd12 1016static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1017{
9f25d007 1018 struct drm_info_node *node = m->private;
f97108d1 1019 struct drm_device *dev = node->minor->dev;
e277a1f8 1020 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1021 int ret = 0;
1022
1023 intel_runtime_pm_get(dev_priv);
3b8d8d91 1024
5c9669ce
TR		 1025 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1026
3b8d8d91
JB		 1027 if (IS_GEN5(dev)) {
1028 u16 rgvswctl = I915_READ16(MEMSWCTL);
1029 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1030
1031 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1032 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1033 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1034 MEMSTAT_VID_SHIFT);
1035 seq_printf(m, "Current P-state: %d\n",
1036 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1037 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1038 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1039 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1040 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1041 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1042 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1043 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1044 u32 rpupei, rpcurup, rpprevup;
1045 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1046 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1047 int max_freq;
1048
1049 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1050 ret = mutex_lock_interruptible(&dev->struct_mutex);
1051 if (ret)
c8c8fb33 1052 goto out;
d1ebd816 1053
c8d9a590 1054 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1055
8e8c06cd
CW		 1056 reqf = I915_READ(GEN6_RPNSWREQ);
1057 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1058 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1059 reqf >>= 24;
1060 else
1061 reqf >>= 25;
1062 reqf *= GT_FREQUENCY_MULTIPLIER;
1063
0d8f9491
CW		 1064 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1065 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1066 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1067
ccab5c82
JB		 1068 rpstat = I915_READ(GEN6_RPSTAT1);
1069 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1070 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1071 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1072 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1073 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1074 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1075 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1076 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1077 else
1078 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1079 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1080
c8d9a590 1081 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1082 mutex_unlock(&dev->struct_mutex);
1083
9dd3c605
PZ		 1084 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1085 pm_ier = I915_READ(GEN6_PMIER);
1086 pm_imr = I915_READ(GEN6_PMIMR);
1087 pm_isr = I915_READ(GEN6_PMISR);
1088 pm_iir = I915_READ(GEN6_PMIIR);
1089 pm_mask = I915_READ(GEN6_PMINTRMSK);
1090 } else {
1091 pm_ier = I915_READ(GEN8_GT_IER(2));
1092 pm_imr = I915_READ(GEN8_GT_IMR(2));
1093 pm_isr = I915_READ(GEN8_GT_ISR(2));
1094 pm_iir = I915_READ(GEN8_GT_IIR(2));
1095 pm_mask = I915_READ(GEN6_PMINTRMSK);
1096 }
0d8f9491 1097 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1098 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1099 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1100 seq_printf(m, "Render p-state ratio: %d\n",
1101 (gt_perf_status & 0xff00) >> 8);
1102 seq_printf(m, "Render p-state VID: %d\n",
1103 gt_perf_status & 0xff);
1104 seq_printf(m, "Render p-state limit: %d\n",
1105 rp_state_limits & 0xff);
0d8f9491
CW		 1106 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1107 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1108 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1109 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1110 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1111 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1112 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1113 GEN6_CURICONT_MASK);
1114 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1115 GEN6_CURBSYTAVG_MASK);
1116 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1117 GEN6_CURBSYTAVG_MASK);
1118 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1119 GEN6_CURIAVG_MASK);
1120 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1121 GEN6_CURBSYTAVG_MASK);
1122 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1123 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1124
1125 max_freq = (rp_state_cap & 0xff0000) >> 16;
1126 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1127 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1128
1129 max_freq = (rp_state_cap & 0xff00) >> 8;
1130 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1131 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1132
1133 max_freq = rp_state_cap & 0xff;
1134 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1135 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1136
1137 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1138 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84 1139 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1140 u32 freq_sts;
0a073b84 1141
259bd5d4 1142 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1143 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1144 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1145 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1146
0a073b84 1147 seq_printf(m, "max GPU freq: %d MHz\n",
b2435c94 1148 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1149
0a073b84 1150 seq_printf(m, "min GPU freq: %d MHz\n",
b2435c94 1151 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045
VS		 1152
1153 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
b2435c94 1154 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1155
1156 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1157 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1158 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1159 } else {
267f0c90 1160 seq_puts(m, "no P-state info available\n");
3b8d8d91 1161 }
f97108d1 1162
c8c8fb33
PZ		 1163out:
1164 intel_runtime_pm_put(dev_priv);
1165 return ret;
f97108d1
JB		 1166}
1167
4d85529d 1168static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1169{
9f25d007 1170 struct drm_info_node *node = m->private;
f97108d1 1171 struct drm_device *dev = node->minor->dev;
e277a1f8 1172 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1173 u32 rgvmodectl, rstdbyctl;
1174 u16 crstandvid;
1175 int ret;
1176
1177 ret = mutex_lock_interruptible(&dev->struct_mutex);
1178 if (ret)
1179 return ret;
c8c8fb33 1180 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1181
1182 rgvmodectl = I915_READ(MEMMODECTL);
1183 rstdbyctl = I915_READ(RSTDBYCTL);
1184 crstandvid = I915_READ16(CRSTANDVID);
1185
c8c8fb33 1186 intel_runtime_pm_put(dev_priv);
616fdb5a 1187 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1188
1189 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1190 "yes" : "no");
1191 seq_printf(m, "Boost freq: %d\n",
1192 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1193 MEMMODE_BOOST_FREQ_SHIFT);
1194 seq_printf(m, "HW control enabled: %s\n",
1195 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1196 seq_printf(m, "SW control enabled: %s\n",
1197 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1198 seq_printf(m, "Gated voltage change: %s\n",
1199 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1200 seq_printf(m, "Starting frequency: P%d\n",
1201 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1202 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1203 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1204 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1205 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1206 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1207 seq_printf(m, "Render standby enabled: %s\n",
1208 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1209 seq_puts(m, "Current RS state: ");
88271da3
JB		 1210 switch (rstdbyctl & RSX_STATUS_MASK) {
1211 case RSX_STATUS_ON:
267f0c90 1212 seq_puts(m, "on\n");
88271da3
JB		 1213 break;
1214 case RSX_STATUS_RC1:
267f0c90 1215 seq_puts(m, "RC1\n");
88271da3
JB		 1216 break;
1217 case RSX_STATUS_RC1E:
267f0c90 1218 seq_puts(m, "RC1E\n");
88271da3
JB		 1219 break;
1220 case RSX_STATUS_RS1:
267f0c90 1221 seq_puts(m, "RS1\n");
88271da3
JB		 1222 break;
1223 case RSX_STATUS_RS2:
267f0c90 1224 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1225 break;
1226 case RSX_STATUS_RS3:
267f0c90 1227 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1228 break;
1229 default:
267f0c90 1230 seq_puts(m, "unknown\n");
88271da3
JB		 1231 break;
1232 }
f97108d1
JB		 1233
1234 return 0;
1235}
1236
669ab5aa
D		 1237static int vlv_drpc_info(struct seq_file *m)
1238{
1239
9f25d007 1240 struct drm_info_node *node = m->private;
669ab5aa
D		 1241 struct drm_device *dev = node->minor->dev;
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 u32 rpmodectl1, rcctl1;
1244 unsigned fw_rendercount = 0, fw_mediacount = 0;
1245
d46c0517
ID		 1246 intel_runtime_pm_get(dev_priv);
1247
669ab5aa
D		 1248 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1249 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1250
d46c0517
ID		 1251 intel_runtime_pm_put(dev_priv);
1252
669ab5aa
D		 1253 seq_printf(m, "Video Turbo Mode: %s\n",
1254 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1255 seq_printf(m, "Turbo enabled: %s\n",
1256 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1257 seq_printf(m, "HW control enabled: %s\n",
1258 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1259 seq_printf(m, "SW control enabled: %s\n",
1260 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1261 GEN6_RP_MEDIA_SW_MODE));
1262 seq_printf(m, "RC6 Enabled: %s\n",
1263 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1264 GEN6_RC_CTL_EI_MODE(1))));
1265 seq_printf(m, "Render Power Well: %s\n",
1266 (I915_READ(VLV_GTLC_PW_STATUS) &
1267 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1268 seq_printf(m, "Media Power Well: %s\n",
1269 (I915_READ(VLV_GTLC_PW_STATUS) &
1270 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1271
9cc19be5
ID		 1272 seq_printf(m, "Render RC6 residency since boot: %u\n",
1273 I915_READ(VLV_GT_RENDER_RC6));
1274 seq_printf(m, "Media RC6 residency since boot: %u\n",
1275 I915_READ(VLV_GT_MEDIA_RC6));
1276
669ab5aa
D		 1277 spin_lock_irq(&dev_priv->uncore.lock);
1278 fw_rendercount = dev_priv->uncore.fw_rendercount;
1279 fw_mediacount = dev_priv->uncore.fw_mediacount;
1280 spin_unlock_irq(&dev_priv->uncore.lock);
1281
1282 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1283 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1284
1285
1286 return 0;
1287}
1288
1289
4d85529d
BW		 1290static int gen6_drpc_info(struct seq_file *m)
1291{
1292
9f25d007 1293 struct drm_info_node *node = m->private;
4d85529d
BW		 1294 struct drm_device *dev = node->minor->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1296 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1297 unsigned forcewake_count;
aee56cff 1298 int count = 0, ret;
4d85529d
BW		 1299
1300 ret = mutex_lock_interruptible(&dev->struct_mutex);
1301 if (ret)
1302 return ret;
c8c8fb33 1303 intel_runtime_pm_get(dev_priv);
4d85529d 1304
907b28c5
CW		 1305 spin_lock_irq(&dev_priv->uncore.lock);
1306 forcewake_count = dev_priv->uncore.forcewake_count;
1307 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1308
1309 if (forcewake_count) {
267f0c90
DL		 1310 seq_puts(m, "RC information inaccurate because somebody "
1311 "holds a forcewake reference \n");
4d85529d
BW		 1312 } else {
1313 /* NB: we cannot use forcewake, else we read the wrong values */
1314 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1315 udelay(10);
1316 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1317 }
1318
1319 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1320 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1321
1322 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1323 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1324 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1325 mutex_lock(&dev_priv->rps.hw_lock);
1326 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1327 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1328
c8c8fb33
PZ		 1329 intel_runtime_pm_put(dev_priv);
1330
4d85529d
BW		 1331 seq_printf(m, "Video Turbo Mode: %s\n",
1332 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1333 seq_printf(m, "HW control enabled: %s\n",
1334 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1335 seq_printf(m, "SW control enabled: %s\n",
1336 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1337 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1338 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1339 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1340 seq_printf(m, "RC6 Enabled: %s\n",
1341 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1342 seq_printf(m, "Deep RC6 Enabled: %s\n",
1343 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1344 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1345 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1346 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1347 switch (gt_core_status & GEN6_RCn_MASK) {
1348 case GEN6_RC0:
1349 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1350 seq_puts(m, "Core Power Down\n");
4d85529d 1351 else
267f0c90 1352 seq_puts(m, "on\n");
4d85529d
BW		 1353 break;
1354 case GEN6_RC3:
267f0c90 1355 seq_puts(m, "RC3\n");
4d85529d
BW		 1356 break;
1357 case GEN6_RC6:
267f0c90 1358 seq_puts(m, "RC6\n");
4d85529d
BW		 1359 break;
1360 case GEN6_RC7:
267f0c90 1361 seq_puts(m, "RC7\n");
4d85529d
BW		 1362 break;
1363 default:
267f0c90 1364 seq_puts(m, "Unknown\n");
4d85529d
BW		 1365 break;
1366 }
1367
1368 seq_printf(m, "Core Power Down: %s\n",
1369 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1370
1371 /* Not exactly sure what this is */
1372 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1373 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1374 seq_printf(m, "RC6 residency since boot: %u\n",
1375 I915_READ(GEN6_GT_GFX_RC6));
1376 seq_printf(m, "RC6+ residency since boot: %u\n",
1377 I915_READ(GEN6_GT_GFX_RC6p));
1378 seq_printf(m, "RC6++ residency since boot: %u\n",
1379 I915_READ(GEN6_GT_GFX_RC6pp));
1380
ecd8faea
BW		 1381 seq_printf(m, "RC6 voltage: %dmV\n",
1382 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1383 seq_printf(m, "RC6+ voltage: %dmV\n",
1384 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1385 seq_printf(m, "RC6++ voltage: %dmV\n",
1386 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1387 return 0;
1388}
1389
1390static int i915_drpc_info(struct seq_file *m, void *unused)
1391{
9f25d007 1392 struct drm_info_node *node = m->private;
4d85529d
BW		 1393 struct drm_device *dev = node->minor->dev;
1394
669ab5aa
D		 1395 if (IS_VALLEYVIEW(dev))
1396 return vlv_drpc_info(m);
ac66cf4b 1397 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1398 return gen6_drpc_info(m);
1399 else
1400 return ironlake_drpc_info(m);
1401}
1402
b5e50c3f
JB		 1403static int i915_fbc_status(struct seq_file *m, void *unused)
1404{
9f25d007 1405 struct drm_info_node *node = m->private;
b5e50c3f 1406 struct drm_device *dev = node->minor->dev;
e277a1f8 1407 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1408
3a77c4c4 1409 if (!HAS_FBC(dev)) {
267f0c90 1410 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1411 return 0;
1412 }
1413
36623ef8
PZ		 1414 intel_runtime_pm_get(dev_priv);
1415
ee5382ae 1416 if (intel_fbc_enabled(dev)) {
267f0c90 1417 seq_puts(m, "FBC enabled\n");
b5e50c3f 1418 } else {
267f0c90 1419 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1420 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1421 case FBC_OK:
1422 seq_puts(m, "FBC actived, but currently disabled in hardware");
1423 break;
1424 case FBC_UNSUPPORTED:
1425 seq_puts(m, "unsupported by this chipset");
1426 break;
bed4a673 1427 case FBC_NO_OUTPUT:
267f0c90 1428 seq_puts(m, "no outputs");
bed4a673 1429 break;
b5e50c3f 1430 case FBC_STOLEN_TOO_SMALL:
267f0c90 1431 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1432 break;
1433 case FBC_UNSUPPORTED_MODE:
267f0c90 1434 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1435 break;
1436 case FBC_MODE_TOO_LARGE:
267f0c90 1437 seq_puts(m, "mode too large");
b5e50c3f
JB		 1438 break;
1439 case FBC_BAD_PLANE:
267f0c90 1440 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1441 break;
1442 case FBC_NOT_TILED:
267f0c90 1443 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1444 break;
9c928d16 1445 case FBC_MULTIPLE_PIPES:
267f0c90 1446 seq_puts(m, "multiple pipes are enabled");
9c928d16 1447 break;
c1a9f047 1448 case FBC_MODULE_PARAM:
267f0c90 1449 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1450 break;
8a5729a3 1451 case FBC_CHIP_DEFAULT:
267f0c90 1452 seq_puts(m, "disabled per chip default");
8a5729a3 1453 break;
b5e50c3f 1454 default:
267f0c90 1455 seq_puts(m, "unknown reason");
b5e50c3f 1456 }
267f0c90 1457 seq_putc(m, '\n');
b5e50c3f 1458 }
36623ef8
PZ		 1459
1460 intel_runtime_pm_put(dev_priv);
1461
b5e50c3f
JB		 1462 return 0;
1463}
1464
da46f936
RV		 1465static int i915_fbc_fc_get(void *data, u64 *val)
1466{
1467 struct drm_device *dev = data;
1468 struct drm_i915_private *dev_priv = dev->dev_private;
1469
1470 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1471 return -ENODEV;
1472
1473 drm_modeset_lock_all(dev);
1474 *val = dev_priv->fbc.false_color;
1475 drm_modeset_unlock_all(dev);
1476
1477 return 0;
1478}
1479
1480static int i915_fbc_fc_set(void *data, u64 val)
1481{
1482 struct drm_device *dev = data;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 u32 reg;
1485
1486 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1487 return -ENODEV;
1488
1489 drm_modeset_lock_all(dev);
1490
1491 reg = I915_READ(ILK_DPFC_CONTROL);
1492 dev_priv->fbc.false_color = val;
1493
1494 I915_WRITE(ILK_DPFC_CONTROL, val ?
1495 (reg | FBC_CTL_FALSE_COLOR) :
1496 (reg & ~FBC_CTL_FALSE_COLOR));
1497
1498 drm_modeset_unlock_all(dev);
1499 return 0;
1500}
1501
1502DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1503 i915_fbc_fc_get, i915_fbc_fc_set,
1504 "%llu\n");
1505
92d44621
PZ		 1506static int i915_ips_status(struct seq_file *m, void *unused)
1507{
9f25d007 1508 struct drm_info_node *node = m->private;
92d44621
PZ		 1509 struct drm_device *dev = node->minor->dev;
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511
f5adf94e 1512 if (!HAS_IPS(dev)) {
92d44621
PZ		 1513 seq_puts(m, "not supported\n");
1514 return 0;
1515 }
1516
36623ef8
PZ		 1517 intel_runtime_pm_get(dev_priv);
1518
0eaa53f0
RV		 1519 seq_printf(m, "Enabled by kernel parameter: %s\n",
1520 yesno(i915.enable_ips));
1521
1522 if (INTEL_INFO(dev)->gen >= 8) {
1523 seq_puts(m, "Currently: unknown\n");
1524 } else {
1525 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1526 seq_puts(m, "Currently: enabled\n");
1527 else
1528 seq_puts(m, "Currently: disabled\n");
1529 }
92d44621 1530
36623ef8
PZ		 1531 intel_runtime_pm_put(dev_priv);
1532
92d44621
PZ		 1533 return 0;
1534}
1535
4a9bef37
JB		 1536static int i915_sr_status(struct seq_file *m, void *unused)
1537{
9f25d007 1538 struct drm_info_node *node = m->private;
4a9bef37 1539 struct drm_device *dev = node->minor->dev;
e277a1f8 1540 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1541 bool sr_enabled = false;
1542
36623ef8
PZ		 1543 intel_runtime_pm_get(dev_priv);
1544
1398261a 1545 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1546 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1547 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1548 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1549 else if (IS_I915GM(dev))
1550 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1551 else if (IS_PINEVIEW(dev))
1552 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1553
36623ef8
PZ		 1554 intel_runtime_pm_put(dev_priv);
1555
5ba2aaaa
CW		 1556 seq_printf(m, "self-refresh: %s\n",
1557 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1558
1559 return 0;
1560}
1561
7648fa99
JB		 1562static int i915_emon_status(struct seq_file *m, void *unused)
1563{
9f25d007 1564 struct drm_info_node *node = m->private;
7648fa99 1565 struct drm_device *dev = node->minor->dev;
e277a1f8 1566 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1567 unsigned long temp, chipset, gfx;
de227ef0
CW		 1568 int ret;
1569
582be6b4
CW		 1570 if (!IS_GEN5(dev))
1571 return -ENODEV;
1572
de227ef0
CW		 1573 ret = mutex_lock_interruptible(&dev->struct_mutex);
1574 if (ret)
1575 return ret;
7648fa99
JB		 1576
1577 temp = i915_mch_val(dev_priv);
1578 chipset = i915_chipset_val(dev_priv);
1579 gfx = i915_gfx_val(dev_priv);
de227ef0 1580 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1581
1582 seq_printf(m, "GMCH temp: %ld\n", temp);
1583 seq_printf(m, "Chipset power: %ld\n", chipset);
1584 seq_printf(m, "GFX power: %ld\n", gfx);
1585 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1586
1587 return 0;
1588}
1589
23b2f8bb
JB		 1590static int i915_ring_freq_table(struct seq_file *m, void *unused)
1591{
9f25d007 1592 struct drm_info_node *node = m->private;
23b2f8bb 1593 struct drm_device *dev = node->minor->dev;
e277a1f8 1594 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1595 int ret = 0;
23b2f8bb
JB		 1596 int gpu_freq, ia_freq;
1597
1c70c0ce 1598 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1599 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1600 return 0;
1601 }
1602
5bfa0199
PZ		 1603 intel_runtime_pm_get(dev_priv);
1604
5c9669ce
TR		 1605 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1606
4fc688ce 1607 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1608 if (ret)
5bfa0199 1609 goto out;
23b2f8bb 1610
267f0c90 1611 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1612
b39fb297
BW		 1613 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1614 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1615 gpu_freq++) {
42c0526c
BW		 1616 ia_freq = gpu_freq;
1617 sandybridge_pcode_read(dev_priv,
1618 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1619 &ia_freq);
3ebecd07
CW		 1620 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1621 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1622 ((ia_freq >> 0) & 0xff) * 100,
1623 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1624 }
1625
4fc688ce 1626 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1627
5bfa0199
PZ		 1628out:
1629 intel_runtime_pm_put(dev_priv);
1630 return ret;
23b2f8bb
JB		 1631}
1632
44834a67
CW		 1633static int i915_opregion(struct seq_file *m, void *unused)
1634{
9f25d007 1635 struct drm_info_node *node = m->private;
44834a67 1636 struct drm_device *dev = node->minor->dev;
e277a1f8 1637 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1638 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1639 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1640 int ret;
1641
0d38f009
DV		 1642 if (data == NULL)
1643 return -ENOMEM;
1644
44834a67
CW		 1645 ret = mutex_lock_interruptible(&dev->struct_mutex);
1646 if (ret)
0d38f009 1647 goto out;
44834a67 1648
0d38f009
DV		 1649 if (opregion->header) {
1650 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1651 seq_write(m, data, OPREGION_SIZE);
1652 }
44834a67
CW		 1653
1654 mutex_unlock(&dev->struct_mutex);
1655
0d38f009
DV		 1656out:
1657 kfree(data);
44834a67
CW		 1658 return 0;
1659}
1660
37811fcc
CW		 1661static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1662{
9f25d007 1663 struct drm_info_node *node = m->private;
37811fcc 1664 struct drm_device *dev = node->minor->dev;
4520f53a 1665 struct intel_fbdev *ifbdev = NULL;
37811fcc 1666 struct intel_framebuffer *fb;
37811fcc 1667
4520f53a
DV		 1668#ifdef CONFIG_DRM_I915_FBDEV
1669 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1670
1671 ifbdev = dev_priv->fbdev;
1672 fb = to_intel_framebuffer(ifbdev->helper.fb);
1673
623f9783 1674 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1675 fb->base.width,
1676 fb->base.height,
1677 fb->base.depth,
623f9783
DV		 1678 fb->base.bits_per_pixel,
1679 atomic_read(&fb->base.refcount.refcount));
05394f39 1680 describe_obj(m, fb->obj);
267f0c90 1681 seq_putc(m, '\n');
4520f53a 1682#endif
37811fcc 1683
4b096ac1 1684 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1685 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1686 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1687 continue;
1688
623f9783 1689 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1690 fb->base.width,
1691 fb->base.height,
1692 fb->base.depth,
623f9783
DV		 1693 fb->base.bits_per_pixel,
1694 atomic_read(&fb->base.refcount.refcount));
05394f39 1695 describe_obj(m, fb->obj);
267f0c90 1696 seq_putc(m, '\n');
37811fcc 1697 }
4b096ac1 1698 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1699
1700 return 0;
1701}
1702
c9fe99bd
OM		 1703static void describe_ctx_ringbuf(struct seq_file *m,
1704 struct intel_ringbuffer *ringbuf)
1705{
1706 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1707 ringbuf->space, ringbuf->head, ringbuf->tail,
1708 ringbuf->last_retired_head);
1709}
1710
e76d3630
BW		 1711static int i915_context_status(struct seq_file *m, void *unused)
1712{
9f25d007 1713 struct drm_info_node *node = m->private;
e76d3630 1714 struct drm_device *dev = node->minor->dev;
e277a1f8 1715 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1716 struct intel_engine_cs *ring;
273497e5 1717 struct intel_context *ctx;
a168c293 1718 int ret, i;
e76d3630 1719
f3d28878 1720 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1721 if (ret)
1722 return ret;
1723
3e373948 1724 if (dev_priv->ips.pwrctx) {
267f0c90 1725 seq_puts(m, "power context ");
3e373948 1726 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1727 seq_putc(m, '\n');
dc501fbc 1728 }
e76d3630 1729
3e373948 1730 if (dev_priv->ips.renderctx) {
267f0c90 1731 seq_puts(m, "render context ");
3e373948 1732 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1733 seq_putc(m, '\n');
dc501fbc 1734 }
e76d3630 1735
a33afea5 1736 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1737 if (!i915.enable_execlists &&
1738 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1739 continue;
1740
a33afea5 1741 seq_puts(m, "HW context ");
3ccfd19d 1742 describe_ctx(m, ctx);
c9fe99bd 1743 for_each_ring(ring, dev_priv, i) {
a33afea5 1744 if (ring->default_context == ctx)
c9fe99bd
OM		 1745 seq_printf(m, "(default context %s) ",
1746 ring->name);
1747 }
1748
1749 if (i915.enable_execlists) {
1750 seq_putc(m, '\n');
1751 for_each_ring(ring, dev_priv, i) {
1752 struct drm_i915_gem_object *ctx_obj =
1753 ctx->engine[i].state;
1754 struct intel_ringbuffer *ringbuf =
1755 ctx->engine[i].ringbuf;
1756
1757 seq_printf(m, "%s: ", ring->name);
1758 if (ctx_obj)
1759 describe_obj(m, ctx_obj);
1760 if (ringbuf)
1761 describe_ctx_ringbuf(m, ringbuf);
1762 seq_putc(m, '\n');
1763 }
1764 } else {
1765 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1766 }
a33afea5 1767
a33afea5 1768 seq_putc(m, '\n');
a168c293
BW		 1769 }
1770
f3d28878 1771 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1772
1773 return 0;
1774}
1775
c0ab1ae9
BW		 1776static int i915_dump_lrc(struct seq_file *m, void *unused)
1777{
1778 struct drm_info_node *node = (struct drm_info_node *) m->private;
1779 struct drm_device *dev = node->minor->dev;
1780 struct drm_i915_private *dev_priv = dev->dev_private;
1781 struct intel_engine_cs *ring;
1782 struct intel_context *ctx;
1783 int ret, i;
1784
1785 if (!i915.enable_execlists) {
1786 seq_printf(m, "Logical Ring Contexts are disabled\n");
1787 return 0;
1788 }
1789
1790 ret = mutex_lock_interruptible(&dev->struct_mutex);
1791 if (ret)
1792 return ret;
1793
1794 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1795 for_each_ring(ring, dev_priv, i) {
1796 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1797
1798 if (ring->default_context == ctx)
1799 continue;
1800
1801 if (ctx_obj) {
1802 struct page *page = i915_gem_object_get_page(ctx_obj, 1);
1803 uint32_t *reg_state = kmap_atomic(page);
1804 int j;
1805
1806 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1807 intel_execlists_ctx_id(ctx_obj));
1808
1809 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1810 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1811 i915_gem_obj_ggtt_offset(ctx_obj) + 4096 + (j * 4),
1812 reg_state[j], reg_state[j + 1],
1813 reg_state[j + 2], reg_state[j + 3]);
1814 }
1815 kunmap_atomic(reg_state);
1816
1817 seq_putc(m, '\n');
1818 }
1819 }
1820 }
1821
1822 mutex_unlock(&dev->struct_mutex);
1823
1824 return 0;
1825}
1826
4ba70e44
OM		 1827static int i915_execlists(struct seq_file *m, void *data)
1828{
1829 struct drm_info_node *node = (struct drm_info_node *)m->private;
1830 struct drm_device *dev = node->minor->dev;
1831 struct drm_i915_private *dev_priv = dev->dev_private;
1832 struct intel_engine_cs *ring;
1833 u32 status_pointer;
1834 u8 read_pointer;
1835 u8 write_pointer;
1836 u32 status;
1837 u32 ctx_id;
1838 struct list_head *cursor;
1839 int ring_id, i;
1840 int ret;
1841
1842 if (!i915.enable_execlists) {
1843 seq_puts(m, "Logical Ring Contexts are disabled\n");
1844 return 0;
1845 }
1846
1847 ret = mutex_lock_interruptible(&dev->struct_mutex);
1848 if (ret)
1849 return ret;
1850
1851 for_each_ring(ring, dev_priv, ring_id) {
1852 struct intel_ctx_submit_request *head_req = NULL;
1853 int count = 0;
1854 unsigned long flags;
1855
1856 seq_printf(m, "%s\n", ring->name);
1857
1858 status = I915_READ(RING_EXECLIST_STATUS(ring));
1859 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1860 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1861 status, ctx_id);
1862
1863 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1864 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1865
1866 read_pointer = ring->next_context_status_buffer;
1867 write_pointer = status_pointer & 0x07;
1868 if (read_pointer > write_pointer)
1869 write_pointer += 6;
1870 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1871 read_pointer, write_pointer);
1872
1873 for (i = 0; i < 6; i++) {
1874 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1875 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1876
1877 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1878 i, status, ctx_id);
1879 }
1880
1881 spin_lock_irqsave(&ring->execlist_lock, flags);
1882 list_for_each(cursor, &ring->execlist_queue)
1883 count++;
1884 head_req = list_first_entry_or_null(&ring->execlist_queue,
1885 struct intel_ctx_submit_request, execlist_link);
1886 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1887
1888 seq_printf(m, "\t%d requests in queue\n", count);
1889 if (head_req) {
1890 struct drm_i915_gem_object *ctx_obj;
1891
1892 ctx_obj = head_req->ctx->engine[ring_id].state;
1893 seq_printf(m, "\tHead request id: %u\n",
1894 intel_execlists_ctx_id(ctx_obj));
1895 seq_printf(m, "\tHead request tail: %u\n",
1896 head_req->tail);
1897 }
1898
1899 seq_putc(m, '\n');
1900 }
1901
1902 mutex_unlock(&dev->struct_mutex);
1903
1904 return 0;
1905}
1906
6d794d42
BW		 1907static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1908{
9f25d007 1909 struct drm_info_node *node = m->private;
6d794d42
BW		 1910 struct drm_device *dev = node->minor->dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1912 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1913
907b28c5 1914 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1915 if (IS_VALLEYVIEW(dev)) {
1916 fw_rendercount = dev_priv->uncore.fw_rendercount;
1917 fw_mediacount = dev_priv->uncore.fw_mediacount;
1918 } else
1919 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1920 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1921
43709ba0
D		 1922 if (IS_VALLEYVIEW(dev)) {
1923 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1924 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1925 } else
1926 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1927
1928 return 0;
1929}
1930
ea16a3cd
DV		 1931static const char *swizzle_string(unsigned swizzle)
1932{
aee56cff 1933 switch (swizzle) {
ea16a3cd
DV		 1934 case I915_BIT_6_SWIZZLE_NONE:
1935 return "none";
1936 case I915_BIT_6_SWIZZLE_9:
1937 return "bit9";
1938 case I915_BIT_6_SWIZZLE_9_10:
1939 return "bit9/bit10";
1940 case I915_BIT_6_SWIZZLE_9_11:
1941 return "bit9/bit11";
1942 case I915_BIT_6_SWIZZLE_9_10_11:
1943 return "bit9/bit10/bit11";
1944 case I915_BIT_6_SWIZZLE_9_17:
1945 return "bit9/bit17";
1946 case I915_BIT_6_SWIZZLE_9_10_17:
1947 return "bit9/bit10/bit17";
1948 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1949 return "unknown";
ea16a3cd
DV		 1950 }
1951
1952 return "bug";
1953}
1954
1955static int i915_swizzle_info(struct seq_file *m, void *data)
1956{
9f25d007 1957 struct drm_info_node *node = m->private;
ea16a3cd
DV		 1958 struct drm_device *dev = node->minor->dev;
1959 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1960 int ret;
1961
1962 ret = mutex_lock_interruptible(&dev->struct_mutex);
1963 if (ret)
1964 return ret;
c8c8fb33 1965 intel_runtime_pm_get(dev_priv);
ea16a3cd 1966
ea16a3cd
DV		 1967 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1968 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1969 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1970 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1971
1972 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1973 seq_printf(m, "DDC = 0x%08x\n",
1974 I915_READ(DCC));
1975 seq_printf(m, "C0DRB3 = 0x%04x\n",
1976 I915_READ16(C0DRB3));
1977 seq_printf(m, "C1DRB3 = 0x%04x\n",
1978 I915_READ16(C1DRB3));
9d3203e1 1979 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1980 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1981 I915_READ(MAD_DIMM_C0));
1982 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1983 I915_READ(MAD_DIMM_C1));
1984 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1985 I915_READ(MAD_DIMM_C2));
1986 seq_printf(m, "TILECTL = 0x%08x\n",
1987 I915_READ(TILECTL));
5907f5fb 1988 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 1989 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1990 I915_READ(GAMTARBMODE));
1991 else
1992 seq_printf(m, "ARB_MODE = 0x%08x\n",
1993 I915_READ(ARB_MODE));
3fa7d235
DV		 1994 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1995 I915_READ(DISP_ARB_CTL));
ea16a3cd 1996 }
c8c8fb33 1997 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1998 mutex_unlock(&dev->struct_mutex);
1999
2000 return 0;
2001}
2002
1c60fef5
BW		 2003static int per_file_ctx(int id, void *ptr, void *data)
2004{
273497e5 2005 struct intel_context *ctx = ptr;
1c60fef5 2006 struct seq_file *m = data;
ae6c4806
DV		 2007 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2008
2009 if (!ppgtt) {
2010 seq_printf(m, " no ppgtt for context %d\n",
2011 ctx->user_handle);
2012 return 0;
2013 }
1c60fef5 2014
f83d6518
OM		 2015 if (i915_gem_context_is_default(ctx))
2016 seq_puts(m, " default context:\n");
2017 else
821d66dd 2018 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2019 ppgtt->debug_dump(ppgtt, m);
2020
2021 return 0;
2022}
2023
77df6772 2024static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2025{
3cf17fc5 2026 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2027 struct intel_engine_cs *ring;
77df6772
BW		 2028 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2029 int unused, i;
3cf17fc5 2030
77df6772
BW		 2031 if (!ppgtt)
2032 return;
2033
2034 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2035 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2036 for_each_ring(ring, dev_priv, unused) {
2037 seq_printf(m, "%s\n", ring->name);
2038 for (i = 0; i < 4; i++) {
2039 u32 offset = 0x270 + i * 8;
2040 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2041 pdp <<= 32;
2042 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2043 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2044 }
2045 }
2046}
2047
2048static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2049{
2050 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2051 struct intel_engine_cs *ring;
1c60fef5 2052 struct drm_file *file;
77df6772 2053 int i;
3cf17fc5 2054
3cf17fc5
DV		 2055 if (INTEL_INFO(dev)->gen == 6)
2056 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2057
a2c7f6fd 2058 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2059 seq_printf(m, "%s\n", ring->name);
2060 if (INTEL_INFO(dev)->gen == 7)
2061 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2062 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2063 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2064 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2065 }
2066 if (dev_priv->mm.aliasing_ppgtt) {
2067 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2068
267f0c90 2069 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 2070 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 2071
87d60b63 2072 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2073 }
1c60fef5
BW		 2074
2075 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2076 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2077
1c60fef5
BW		 2078 seq_printf(m, "proc: %s\n",
2079 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2080 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2081 }
2082 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2083}
2084
2085static int i915_ppgtt_info(struct seq_file *m, void *data)
2086{
9f25d007 2087 struct drm_info_node *node = m->private;
77df6772 2088 struct drm_device *dev = node->minor->dev;
c8c8fb33 2089 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2090
2091 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2092 if (ret)
2093 return ret;
c8c8fb33 2094 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2095
2096 if (INTEL_INFO(dev)->gen >= 8)
2097 gen8_ppgtt_info(m, dev);
2098 else if (INTEL_INFO(dev)->gen >= 6)
2099 gen6_ppgtt_info(m, dev);
2100
c8c8fb33 2101 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2102 mutex_unlock(&dev->struct_mutex);
2103
2104 return 0;
2105}
2106
63573eb7
BW		 2107static int i915_llc(struct seq_file *m, void *data)
2108{
9f25d007 2109 struct drm_info_node *node = m->private;
63573eb7
BW		 2110 struct drm_device *dev = node->minor->dev;
2111 struct drm_i915_private *dev_priv = dev->dev_private;
2112
2113 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2114 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2115 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2116
2117 return 0;
2118}
2119
e91fd8c6
RV		 2120static int i915_edp_psr_status(struct seq_file *m, void *data)
2121{
2122 struct drm_info_node *node = m->private;
2123 struct drm_device *dev = node->minor->dev;
2124 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 2125 u32 psrperf = 0;
2126 bool enabled = false;
e91fd8c6 2127
c8c8fb33
PZ		 2128 intel_runtime_pm_get(dev_priv);
2129
fa128fa6 2130 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2131 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2132 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2133 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2134 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2135 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2136 dev_priv->psr.busy_frontbuffer_bits);
2137 seq_printf(m, "Re-enable work scheduled: %s\n",
2138 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2139
a031d709
RV		 2140 enabled = HAS_PSR(dev) &&
2141 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
5755c78f 2142 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
e91fd8c6 2143
a031d709
RV		 2144 if (HAS_PSR(dev))
2145 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2146 EDP_PSR_PERF_CNT_MASK;
2147 seq_printf(m, "Performance_Counter: %u\n", psrperf);
fa128fa6 2148 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2149
c8c8fb33 2150 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2151 return 0;
2152}
2153
d2e216d0
RV		 2154static int i915_sink_crc(struct seq_file *m, void *data)
2155{
2156 struct drm_info_node *node = m->private;
2157 struct drm_device *dev = node->minor->dev;
2158 struct intel_encoder *encoder;
2159 struct intel_connector *connector;
2160 struct intel_dp *intel_dp = NULL;
2161 int ret;
2162 u8 crc[6];
2163
2164 drm_modeset_lock_all(dev);
2165 list_for_each_entry(connector, &dev->mode_config.connector_list,
2166 base.head) {
2167
2168 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2169 continue;
2170
b6ae3c7c
PZ		 2171 if (!connector->base.encoder)
2172 continue;
2173
d2e216d0
RV		 2174 encoder = to_intel_encoder(connector->base.encoder);
2175 if (encoder->type != INTEL_OUTPUT_EDP)
2176 continue;
2177
2178 intel_dp = enc_to_intel_dp(&encoder->base);
2179
2180 ret = intel_dp_sink_crc(intel_dp, crc);
2181 if (ret)
2182 goto out;
2183
2184 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2185 crc[0], crc[1], crc[2],
2186 crc[3], crc[4], crc[5]);
2187 goto out;
2188 }
2189 ret = -ENODEV;
2190out:
2191 drm_modeset_unlock_all(dev);
2192 return ret;
2193}
2194
ec013e7f
JB		 2195static int i915_energy_uJ(struct seq_file *m, void *data)
2196{
2197 struct drm_info_node *node = m->private;
2198 struct drm_device *dev = node->minor->dev;
2199 struct drm_i915_private *dev_priv = dev->dev_private;
2200 u64 power;
2201 u32 units;
2202
2203 if (INTEL_INFO(dev)->gen < 6)
2204 return -ENODEV;
2205
36623ef8
PZ		 2206 intel_runtime_pm_get(dev_priv);
2207
ec013e7f
JB		 2208 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2209 power = (power & 0x1f00) >> 8;
2210 units = 1000000 / (1 << power); /* convert to uJ */
2211 power = I915_READ(MCH_SECP_NRG_STTS);
2212 power *= units;
2213
36623ef8
PZ		 2214 intel_runtime_pm_put(dev_priv);
2215
ec013e7f 2216 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2217
2218 return 0;
2219}
2220
2221static int i915_pc8_status(struct seq_file *m, void *unused)
2222{
9f25d007 2223 struct drm_info_node *node = m->private;
371db66a
PZ		 2224 struct drm_device *dev = node->minor->dev;
2225 struct drm_i915_private *dev_priv = dev->dev_private;
2226
85b8d5c2 2227 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2228 seq_puts(m, "not supported\n");
2229 return 0;
2230 }
2231
86c4ec0d 2232 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2233 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2234 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2235
ec013e7f
JB		 2236 return 0;
2237}
2238
1da51581
ID		 2239static const char *power_domain_str(enum intel_display_power_domain domain)
2240{
2241 switch (domain) {
2242 case POWER_DOMAIN_PIPE_A:
2243 return "PIPE_A";
2244 case POWER_DOMAIN_PIPE_B:
2245 return "PIPE_B";
2246 case POWER_DOMAIN_PIPE_C:
2247 return "PIPE_C";
2248 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2249 return "PIPE_A_PANEL_FITTER";
2250 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2251 return "PIPE_B_PANEL_FITTER";
2252 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2253 return "PIPE_C_PANEL_FITTER";
2254 case POWER_DOMAIN_TRANSCODER_A:
2255 return "TRANSCODER_A";
2256 case POWER_DOMAIN_TRANSCODER_B:
2257 return "TRANSCODER_B";
2258 case POWER_DOMAIN_TRANSCODER_C:
2259 return "TRANSCODER_C";
2260 case POWER_DOMAIN_TRANSCODER_EDP:
2261 return "TRANSCODER_EDP";
319be8ae
ID		 2262 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2263 return "PORT_DDI_A_2_LANES";
2264 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2265 return "PORT_DDI_A_4_LANES";
2266 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2267 return "PORT_DDI_B_2_LANES";
2268 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2269 return "PORT_DDI_B_4_LANES";
2270 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2271 return "PORT_DDI_C_2_LANES";
2272 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2273 return "PORT_DDI_C_4_LANES";
2274 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2275 return "PORT_DDI_D_2_LANES";
2276 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2277 return "PORT_DDI_D_4_LANES";
2278 case POWER_DOMAIN_PORT_DSI:
2279 return "PORT_DSI";
2280 case POWER_DOMAIN_PORT_CRT:
2281 return "PORT_CRT";
2282 case POWER_DOMAIN_PORT_OTHER:
2283 return "PORT_OTHER";
1da51581
ID		 2284 case POWER_DOMAIN_VGA:
2285 return "VGA";
2286 case POWER_DOMAIN_AUDIO:
2287 return "AUDIO";
bd2bb1b9
PZ		 2288 case POWER_DOMAIN_PLLS:
2289 return "PLLS";
1da51581
ID		 2290 case POWER_DOMAIN_INIT:
2291 return "INIT";
2292 default:
2293 WARN_ON(1);
2294 return "?";
2295 }
2296}
2297
2298static int i915_power_domain_info(struct seq_file *m, void *unused)
2299{
9f25d007 2300 struct drm_info_node *node = m->private;
1da51581
ID		 2301 struct drm_device *dev = node->minor->dev;
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2304 int i;
2305
2306 mutex_lock(&power_domains->lock);
2307
2308 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2309 for (i = 0; i < power_domains->power_well_count; i++) {
2310 struct i915_power_well *power_well;
2311 enum intel_display_power_domain power_domain;
2312
2313 power_well = &power_domains->power_wells[i];
2314 seq_printf(m, "%-25s %d\n", power_well->name,
2315 power_well->count);
2316
2317 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2318 power_domain++) {
2319 if (!(BIT(power_domain) & power_well->domains))
2320 continue;
2321
2322 seq_printf(m, " %-23s %d\n",
2323 power_domain_str(power_domain),
2324 power_domains->domain_use_count[power_domain]);
2325 }
2326 }
2327
2328 mutex_unlock(&power_domains->lock);
2329
2330 return 0;
2331}
2332
53f5e3ca
JB		 2333static void intel_seq_print_mode(struct seq_file *m, int tabs,
2334 struct drm_display_mode *mode)
2335{
2336 int i;
2337
2338 for (i = 0; i < tabs; i++)
2339 seq_putc(m, '\t');
2340
2341 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2342 mode->base.id, mode->name,
2343 mode->vrefresh, mode->clock,
2344 mode->hdisplay, mode->hsync_start,
2345 mode->hsync_end, mode->htotal,
2346 mode->vdisplay, mode->vsync_start,
2347 mode->vsync_end, mode->vtotal,
2348 mode->type, mode->flags);
2349}
2350
2351static void intel_encoder_info(struct seq_file *m,
2352 struct intel_crtc *intel_crtc,
2353 struct intel_encoder *intel_encoder)
2354{
9f25d007 2355 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2356 struct drm_device *dev = node->minor->dev;
2357 struct drm_crtc *crtc = &intel_crtc->base;
2358 struct intel_connector *intel_connector;
2359 struct drm_encoder *encoder;
2360
2361 encoder = &intel_encoder->base;
2362 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2363 encoder->base.id, encoder->name);
53f5e3ca
JB		 2364 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2365 struct drm_connector *connector = &intel_connector->base;
2366 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2367 connector->base.id,
c23cc417 2368 connector->name,
53f5e3ca
JB		 2369 drm_get_connector_status_name(connector->status));
2370 if (connector->status == connector_status_connected) {
2371 struct drm_display_mode *mode = &crtc->mode;
2372 seq_printf(m, ", mode:\n");
2373 intel_seq_print_mode(m, 2, mode);
2374 } else {
2375 seq_putc(m, '\n');
2376 }
2377 }
2378}
2379
2380static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2381{
9f25d007 2382 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2383 struct drm_device *dev = node->minor->dev;
2384 struct drm_crtc *crtc = &intel_crtc->base;
2385 struct intel_encoder *intel_encoder;
2386
5aa8a937
MR		 2387 if (crtc->primary->fb)
2388 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2389 crtc->primary->fb->base.id, crtc->x, crtc->y,
2390 crtc->primary->fb->width, crtc->primary->fb->height);
2391 else
2392 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2393 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2394 intel_encoder_info(m, intel_crtc, intel_encoder);
2395}
2396
2397static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2398{
2399 struct drm_display_mode *mode = panel->fixed_mode;
2400
2401 seq_printf(m, "\tfixed mode:\n");
2402 intel_seq_print_mode(m, 2, mode);
2403}
2404
2405static void intel_dp_info(struct seq_file *m,
2406 struct intel_connector *intel_connector)
2407{
2408 struct intel_encoder *intel_encoder = intel_connector->encoder;
2409 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2410
2411 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2412 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2413 "no");
2414 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2415 intel_panel_info(m, &intel_connector->panel);
2416}
2417
2418static void intel_hdmi_info(struct seq_file *m,
2419 struct intel_connector *intel_connector)
2420{
2421 struct intel_encoder *intel_encoder = intel_connector->encoder;
2422 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2423
2424 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2425 "no");
2426}
2427
2428static void intel_lvds_info(struct seq_file *m,
2429 struct intel_connector *intel_connector)
2430{
2431 intel_panel_info(m, &intel_connector->panel);
2432}
2433
2434static void intel_connector_info(struct seq_file *m,
2435 struct drm_connector *connector)
2436{
2437 struct intel_connector *intel_connector = to_intel_connector(connector);
2438 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2439 struct drm_display_mode *mode;
53f5e3ca
JB		 2440
2441 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2442 connector->base.id, connector->name,
53f5e3ca
JB		 2443 drm_get_connector_status_name(connector->status));
2444 if (connector->status == connector_status_connected) {
2445 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2446 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2447 connector->display_info.width_mm,
2448 connector->display_info.height_mm);
2449 seq_printf(m, "\tsubpixel order: %s\n",
2450 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2451 seq_printf(m, "\tCEA rev: %d\n",
2452 connector->display_info.cea_rev);
2453 }
36cd7444
DA		 2454 if (intel_encoder) {
2455 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2456 intel_encoder->type == INTEL_OUTPUT_EDP)
2457 intel_dp_info(m, intel_connector);
2458 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2459 intel_hdmi_info(m, intel_connector);
2460 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2461 intel_lvds_info(m, intel_connector);
2462 }
53f5e3ca 2463
f103fc7d
JB		 2464 seq_printf(m, "\tmodes:\n");
2465 list_for_each_entry(mode, &connector->modes, head)
2466 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2467}
2468
065f2ec2
CW		 2469static bool cursor_active(struct drm_device *dev, int pipe)
2470{
2471 struct drm_i915_private *dev_priv = dev->dev_private;
2472 u32 state;
2473
2474 if (IS_845G(dev) || IS_I865G(dev))
2475 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2476 else
5efb3e28 2477 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2478
2479 return state;
2480}
2481
2482static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2483{
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485 u32 pos;
2486
5efb3e28 2487 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2488
2489 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2490 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2491 *x = -*x;
2492
2493 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2494 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2495 *y = -*y;
2496
2497 return cursor_active(dev, pipe);
2498}
2499
53f5e3ca
JB		 2500static int i915_display_info(struct seq_file *m, void *unused)
2501{
9f25d007 2502 struct drm_info_node *node = m->private;
53f5e3ca 2503 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2504 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2505 struct intel_crtc *crtc;
53f5e3ca
JB		 2506 struct drm_connector *connector;
2507
b0e5ddf3 2508 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2509 drm_modeset_lock_all(dev);
2510 seq_printf(m, "CRTC info\n");
2511 seq_printf(m, "---------\n");
d3fcc808 2512 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2513 bool active;
2514 int x, y;
53f5e3ca 2515
57127efa 2516 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2517 crtc->base.base.id, pipe_name(crtc->pipe),
57127efa 2518 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
a23dc658 2519 if (crtc->active) {
065f2ec2
CW		 2520 intel_crtc_info(m, crtc);
2521
a23dc658 2522 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2523 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2524 yesno(crtc->cursor_base),
57127efa
CW		 2525 x, y, crtc->cursor_width, crtc->cursor_height,
2526 crtc->cursor_addr, yesno(active));
a23dc658 2527 }
cace841c
DV		 2528
2529 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2530 yesno(!crtc->cpu_fifo_underrun_disabled),
2531 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2532 }
2533
2534 seq_printf(m, "\n");
2535 seq_printf(m, "Connector info\n");
2536 seq_printf(m, "--------------\n");
2537 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2538 intel_connector_info(m, connector);
2539 }
2540 drm_modeset_unlock_all(dev);
b0e5ddf3 2541 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2542
2543 return 0;
2544}
2545
e04934cf
BW		 2546static int i915_semaphore_status(struct seq_file *m, void *unused)
2547{
2548 struct drm_info_node *node = (struct drm_info_node *) m->private;
2549 struct drm_device *dev = node->minor->dev;
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551 struct intel_engine_cs *ring;
2552 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2553 int i, j, ret;
2554
2555 if (!i915_semaphore_is_enabled(dev)) {
2556 seq_puts(m, "Semaphores are disabled\n");
2557 return 0;
2558 }
2559
2560 ret = mutex_lock_interruptible(&dev->struct_mutex);
2561 if (ret)
2562 return ret;
03872064 2563 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2564
2565 if (IS_BROADWELL(dev)) {
2566 struct page *page;
2567 uint64_t *seqno;
2568
2569 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2570
2571 seqno = (uint64_t *)kmap_atomic(page);
2572 for_each_ring(ring, dev_priv, i) {
2573 uint64_t offset;
2574
2575 seq_printf(m, "%s\n", ring->name);
2576
2577 seq_puts(m, " Last signal:");
2578 for (j = 0; j < num_rings; j++) {
2579 offset = i * I915_NUM_RINGS + j;
2580 seq_printf(m, "0x%08llx (0x%02llx) ",
2581 seqno[offset], offset * 8);
2582 }
2583 seq_putc(m, '\n');
2584
2585 seq_puts(m, " Last wait: ");
2586 for (j = 0; j < num_rings; j++) {
2587 offset = i + (j * I915_NUM_RINGS);
2588 seq_printf(m, "0x%08llx (0x%02llx) ",
2589 seqno[offset], offset * 8);
2590 }
2591 seq_putc(m, '\n');
2592
2593 }
2594 kunmap_atomic(seqno);
2595 } else {
2596 seq_puts(m, " Last signal:");
2597 for_each_ring(ring, dev_priv, i)
2598 for (j = 0; j < num_rings; j++)
2599 seq_printf(m, "0x%08x\n",
2600 I915_READ(ring->semaphore.mbox.signal[j]));
2601 seq_putc(m, '\n');
2602 }
2603
2604 seq_puts(m, "\nSync seqno:\n");
2605 for_each_ring(ring, dev_priv, i) {
2606 for (j = 0; j < num_rings; j++) {
2607 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2608 }
2609 seq_putc(m, '\n');
2610 }
2611 seq_putc(m, '\n');
2612
03872064 2613 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2614 mutex_unlock(&dev->struct_mutex);
2615 return 0;
2616}
2617
728e29d7
DV		 2618static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2619{
2620 struct drm_info_node *node = (struct drm_info_node *) m->private;
2621 struct drm_device *dev = node->minor->dev;
2622 struct drm_i915_private *dev_priv = dev->dev_private;
2623 int i;
2624
2625 drm_modeset_lock_all(dev);
2626 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2627 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2628
2629 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2630 seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount,
2631 pll->active, yesno(pll->on));
2632 seq_printf(m, " tracked hardware state:\n");
2633 seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll);
2634 seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
2635 seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0);
2636 seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1);
d452c5b6 2637 seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll);
728e29d7
DV		 2638 }
2639 drm_modeset_unlock_all(dev);
2640
2641 return 0;
2642}
2643
1ed1ef9d 2644static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2645{
2646 int i;
2647 int ret;
2648 struct drm_info_node *node = (struct drm_info_node *) m->private;
2649 struct drm_device *dev = node->minor->dev;
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651
888b5995
AS		 2652 ret = mutex_lock_interruptible(&dev->struct_mutex);
2653 if (ret)
2654 return ret;
2655
2656 intel_runtime_pm_get(dev_priv);
2657
7225342a
MK		 2658 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2659 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2660 u32 addr, mask, value, read;
2661 bool ok;
888b5995 2662
7225342a
MK		 2663 addr = dev_priv->workarounds.reg[i].addr;
2664 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2665 value = dev_priv->workarounds.reg[i].value;
2666 read = I915_READ(addr);
2667 ok = (value & mask) == (read & mask);
2668 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2669 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2670 }
2671
2672 intel_runtime_pm_put(dev_priv);
2673 mutex_unlock(&dev->struct_mutex);
2674
2675 return 0;
2676}
2677
07144428
DL		 2678struct pipe_crc_info {
2679 const char *name;
2680 struct drm_device *dev;
2681 enum pipe pipe;
2682};
2683
11bed958
DA		 2684static int i915_dp_mst_info(struct seq_file *m, void *unused)
2685{
2686 struct drm_info_node *node = (struct drm_info_node *) m->private;
2687 struct drm_device *dev = node->minor->dev;
2688 struct drm_encoder *encoder;
2689 struct intel_encoder *intel_encoder;
2690 struct intel_digital_port *intel_dig_port;
2691 drm_modeset_lock_all(dev);
2692 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2693 intel_encoder = to_intel_encoder(encoder);
2694 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2695 continue;
2696 intel_dig_port = enc_to_dig_port(encoder);
2697 if (!intel_dig_port->dp.can_mst)
2698 continue;
2699
2700 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2701 }
2702 drm_modeset_unlock_all(dev);
2703 return 0;
2704}
2705
07144428
DL		 2706static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2707{
be5c7a90
DL		 2708 struct pipe_crc_info *info = inode->i_private;
2709 struct drm_i915_private *dev_priv = info->dev->dev_private;
2710 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2711
7eb1c496
DV		 2712 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2713 return -ENODEV;
2714
d538bbdf
DL		 2715 spin_lock_irq(&pipe_crc->lock);
2716
2717 if (pipe_crc->opened) {
2718 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2719 return -EBUSY; /* already open */
2720 }
2721
d538bbdf 2722 pipe_crc->opened = true;
07144428
DL		 2723 filep->private_data = inode->i_private;
2724
d538bbdf
DL		 2725 spin_unlock_irq(&pipe_crc->lock);
2726
07144428
DL		 2727 return 0;
2728}
2729
2730static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2731{
be5c7a90
DL		 2732 struct pipe_crc_info *info = inode->i_private;
2733 struct drm_i915_private *dev_priv = info->dev->dev_private;
2734 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2735
d538bbdf
DL		 2736 spin_lock_irq(&pipe_crc->lock);
2737 pipe_crc->opened = false;
2738 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2739
07144428
DL		 2740 return 0;
2741}
2742
2743/* (6 fields, 8 chars each, space separated (5) + '\n') */
2744#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2745/* account for \'0' */
2746#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2747
2748static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2749{
d538bbdf
DL		 2750 assert_spin_locked(&pipe_crc->lock);
2751 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2752 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2753}
2754
2755static ssize_t
2756i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2757 loff_t *pos)
2758{
2759 struct pipe_crc_info *info = filep->private_data;
2760 struct drm_device *dev = info->dev;
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2763 char buf[PIPE_CRC_BUFFER_LEN];
2764 int head, tail, n_entries, n;
2765 ssize_t bytes_read;
2766
2767 /*
2768 * Don't allow user space to provide buffers not big enough to hold
2769 * a line of data.
2770 */
2771 if (count < PIPE_CRC_LINE_LEN)
2772 return -EINVAL;
2773
2774 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2775 return 0;
07144428
DL		 2776
2777 /* nothing to read */
d538bbdf 2778 spin_lock_irq(&pipe_crc->lock);
07144428 2779 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2780 int ret;
2781
2782 if (filep->f_flags & O_NONBLOCK) {
2783 spin_unlock_irq(&pipe_crc->lock);
07144428 2784 return -EAGAIN;
d538bbdf 2785 }
07144428 2786
d538bbdf
DL		 2787 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2788 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2789 if (ret) {
2790 spin_unlock_irq(&pipe_crc->lock);
2791 return ret;
2792 }
8bf1e9f1
SH		 2793 }
2794
07144428 2795 /* We now have one or more entries to read */
d538bbdf
DL		 2796 head = pipe_crc->head;
2797 tail = pipe_crc->tail;
07144428
DL		 2798 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2799 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2800 spin_unlock_irq(&pipe_crc->lock);
2801
07144428
DL		 2802 bytes_read = 0;
2803 n = 0;
2804 do {
b2c88f5b 2805 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2806 int ret;
8bf1e9f1 2807
07144428
DL		 2808 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2809 "%8u %8x %8x %8x %8x %8x\n",
2810 entry->frame, entry->crc[0],
2811 entry->crc[1], entry->crc[2],
2812 entry->crc[3], entry->crc[4]);
2813
2814 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2815 buf, PIPE_CRC_LINE_LEN);
2816 if (ret == PIPE_CRC_LINE_LEN)
2817 return -EFAULT;
b2c88f5b
DL		 2818
2819 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2820 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2821 n++;
2822 } while (--n_entries);
8bf1e9f1 2823
d538bbdf
DL		 2824 spin_lock_irq(&pipe_crc->lock);
2825 pipe_crc->tail = tail;
2826 spin_unlock_irq(&pipe_crc->lock);
2827
07144428
DL		 2828 return bytes_read;
2829}
2830
2831static const struct file_operations i915_pipe_crc_fops = {
2832 .owner = THIS_MODULE,
2833 .open = i915_pipe_crc_open,
2834 .read = i915_pipe_crc_read,
2835 .release = i915_pipe_crc_release,
2836};
2837
2838static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2839 {
2840 .name = "i915_pipe_A_crc",
2841 .pipe = PIPE_A,
2842 },
2843 {
2844 .name = "i915_pipe_B_crc",
2845 .pipe = PIPE_B,
2846 },
2847 {
2848 .name = "i915_pipe_C_crc",
2849 .pipe = PIPE_C,
2850 },
2851};
2852
2853static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2854 enum pipe pipe)
2855{
2856 struct drm_device *dev = minor->dev;
2857 struct dentry *ent;
2858 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2859
2860 info->dev = dev;
2861 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2862 &i915_pipe_crc_fops);
f3c5fe97
WY		 2863 if (!ent)
2864 return -ENOMEM;
07144428
DL		 2865
2866 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2867}
2868
e8dfcf78 2869static const char * const pipe_crc_sources[] = {
926321d5
DV		 2870 "none",
2871 "plane1",
2872 "plane2",
2873 "pf",
5b3a856b 2874 "pipe",
3d099a05
DV		 2875 "TV",
2876 "DP-B",
2877 "DP-C",
2878 "DP-D",
46a19188 2879 "auto",
926321d5
DV		 2880};
2881
2882static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2883{
2884 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2885 return pipe_crc_sources[source];
2886}
2887
bd9db02f 2888static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2889{
2890 struct drm_device *dev = m->private;
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 int i;
2893
2894 for (i = 0; i < I915_MAX_PIPES; i++)
2895 seq_printf(m, "%c %s\n", pipe_name(i),
2896 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2897
2898 return 0;
2899}
2900
bd9db02f 2901static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2902{
2903 struct drm_device *dev = inode->i_private;
2904
bd9db02f 2905 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2906}
2907
46a19188 2908static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2909 uint32_t *val)
2910{
46a19188
DV		 2911 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2912 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2913
2914 switch (*source) {
52f843f6
DV		 2915 case INTEL_PIPE_CRC_SOURCE_PIPE:
2916 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2917 break;
2918 case INTEL_PIPE_CRC_SOURCE_NONE:
2919 *val = 0;
2920 break;
2921 default:
2922 return -EINVAL;
2923 }
2924
2925 return 0;
2926}
2927
46a19188
DV		 2928static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2929 enum intel_pipe_crc_source *source)
2930{
2931 struct intel_encoder *encoder;
2932 struct intel_crtc *crtc;
26756809 2933 struct intel_digital_port *dig_port;
46a19188
DV		 2934 int ret = 0;
2935
2936 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2937
6e9f798d 2938 drm_modeset_lock_all(dev);
b2784e15 2939 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 2940 if (!encoder->base.crtc)
2941 continue;
2942
2943 crtc = to_intel_crtc(encoder->base.crtc);
2944
2945 if (crtc->pipe != pipe)
2946 continue;
2947
2948 switch (encoder->type) {
2949 case INTEL_OUTPUT_TVOUT:
2950 *source = INTEL_PIPE_CRC_SOURCE_TV;
2951 break;
2952 case INTEL_OUTPUT_DISPLAYPORT:
2953 case INTEL_OUTPUT_EDP:
26756809
DV		 2954 dig_port = enc_to_dig_port(&encoder->base);
2955 switch (dig_port->port) {
2956 case PORT_B:
2957 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2958 break;
2959 case PORT_C:
2960 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2961 break;
2962 case PORT_D:
2963 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2964 break;
2965 default:
2966 WARN(1, "nonexisting DP port %c\n",
2967 port_name(dig_port->port));
2968 break;
2969 }
46a19188
DV		 2970 break;
2971 }
2972 }
6e9f798d 2973 drm_modeset_unlock_all(dev);
46a19188
DV		 2974
2975 return ret;
2976}
2977
2978static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2979 enum pipe pipe,
2980 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2981 uint32_t *val)
2982{
8d2f24ca
DV		 2983 struct drm_i915_private *dev_priv = dev->dev_private;
2984 bool need_stable_symbols = false;
2985
46a19188
DV		 2986 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2987 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2988 if (ret)
2989 return ret;
2990 }
2991
2992 switch (*source) {
7ac0129b
DV		 2993 case INTEL_PIPE_CRC_SOURCE_PIPE:
2994 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2995 break;
2996 case INTEL_PIPE_CRC_SOURCE_DP_B:
2997 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2998 need_stable_symbols = true;
7ac0129b
DV		 2999 break;
3000 case INTEL_PIPE_CRC_SOURCE_DP_C:
3001 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3002 need_stable_symbols = true;
7ac0129b
DV		 3003 break;
3004 case INTEL_PIPE_CRC_SOURCE_NONE:
3005 *val = 0;
3006 break;
3007 default:
3008 return -EINVAL;
3009 }
3010
8d2f24ca
DV		 3011 /*
3012 * When the pipe CRC tap point is after the transcoders we need
3013 * to tweak symbol-level features to produce a deterministic series of
3014 * symbols for a given frame. We need to reset those features only once
3015 * a frame (instead of every nth symbol):
3016 * - DC-balance: used to ensure a better clock recovery from the data
3017 * link (SDVO)
3018 * - DisplayPort scrambling: used for EMI reduction
3019 */
3020 if (need_stable_symbols) {
3021 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3022
8d2f24ca
DV		 3023 tmp |= DC_BALANCE_RESET_VLV;
3024 if (pipe == PIPE_A)
3025 tmp |= PIPE_A_SCRAMBLE_RESET;
3026 else
3027 tmp |= PIPE_B_SCRAMBLE_RESET;
3028
3029 I915_WRITE(PORT_DFT2_G4X, tmp);
3030 }
3031
7ac0129b
DV		 3032 return 0;
3033}
3034
4b79ebf7 3035static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3036 enum pipe pipe,
3037 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3038 uint32_t *val)
3039{
84093603
DV		 3040 struct drm_i915_private *dev_priv = dev->dev_private;
3041 bool need_stable_symbols = false;
3042
46a19188
DV		 3043 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3044 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3045 if (ret)
3046 return ret;
3047 }
3048
3049 switch (*source) {
4b79ebf7
DV		 3050 case INTEL_PIPE_CRC_SOURCE_PIPE:
3051 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3052 break;
3053 case INTEL_PIPE_CRC_SOURCE_TV:
3054 if (!SUPPORTS_TV(dev))
3055 return -EINVAL;
3056 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3057 break;
3058 case INTEL_PIPE_CRC_SOURCE_DP_B:
3059 if (!IS_G4X(dev))
3060 return -EINVAL;
3061 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3062 need_stable_symbols = true;
4b79ebf7
DV		 3063 break;
3064 case INTEL_PIPE_CRC_SOURCE_DP_C:
3065 if (!IS_G4X(dev))
3066 return -EINVAL;
3067 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3068 need_stable_symbols = true;
4b79ebf7
DV		 3069 break;
3070 case INTEL_PIPE_CRC_SOURCE_DP_D:
3071 if (!IS_G4X(dev))
3072 return -EINVAL;
3073 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3074 need_stable_symbols = true;
4b79ebf7
DV		 3075 break;
3076 case INTEL_PIPE_CRC_SOURCE_NONE:
3077 *val = 0;
3078 break;
3079 default:
3080 return -EINVAL;
3081 }
3082
84093603
DV		 3083 /*
3084 * When the pipe CRC tap point is after the transcoders we need
3085 * to tweak symbol-level features to produce a deterministic series of
3086 * symbols for a given frame. We need to reset those features only once
3087 * a frame (instead of every nth symbol):
3088 * - DC-balance: used to ensure a better clock recovery from the data
3089 * link (SDVO)
3090 * - DisplayPort scrambling: used for EMI reduction
3091 */
3092 if (need_stable_symbols) {
3093 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3094
3095 WARN_ON(!IS_G4X(dev));
3096
3097 I915_WRITE(PORT_DFT_I9XX,
3098 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3099
3100 if (pipe == PIPE_A)
3101 tmp |= PIPE_A_SCRAMBLE_RESET;
3102 else
3103 tmp |= PIPE_B_SCRAMBLE_RESET;
3104
3105 I915_WRITE(PORT_DFT2_G4X, tmp);
3106 }
3107
4b79ebf7
DV		 3108 return 0;
3109}
3110
8d2f24ca
DV		 3111static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3112 enum pipe pipe)
3113{
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3116
3117 if (pipe == PIPE_A)
3118 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3119 else
3120 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3121 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3122 tmp &= ~DC_BALANCE_RESET_VLV;
3123 I915_WRITE(PORT_DFT2_G4X, tmp);
3124
3125}
3126
84093603
DV		 3127static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3128 enum pipe pipe)
3129{
3130 struct drm_i915_private *dev_priv = dev->dev_private;
3131 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3132
3133 if (pipe == PIPE_A)
3134 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3135 else
3136 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3137 I915_WRITE(PORT_DFT2_G4X, tmp);
3138
3139 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3140 I915_WRITE(PORT_DFT_I9XX,
3141 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3142 }
3143}
3144
46a19188 3145static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3146 uint32_t *val)
3147{
46a19188
DV		 3148 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3149 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3150
3151 switch (*source) {
5b3a856b
DV		 3152 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3153 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3154 break;
3155 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3156 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3157 break;
5b3a856b
DV		 3158 case INTEL_PIPE_CRC_SOURCE_PIPE:
3159 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3160 break;
3d099a05 3161 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3162 *val = 0;
3163 break;
3d099a05
DV		 3164 default:
3165 return -EINVAL;
5b3a856b
DV		 3166 }
3167
3168 return 0;
3169}
3170
fabf6e51
DV		 3171static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3172{
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 struct intel_crtc *crtc =
3175 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3176
3177 drm_modeset_lock_all(dev);
3178 /*
3179 * If we use the eDP transcoder we need to make sure that we don't
3180 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3181 * relevant on hsw with pipe A when using the always-on power well
3182 * routing.
3183 */
3184 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3185 !crtc->config.pch_pfit.enabled) {
3186 crtc->config.pch_pfit.force_thru = true;
3187
3188 intel_display_power_get(dev_priv,
3189 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3190
3191 dev_priv->display.crtc_disable(&crtc->base);
3192 dev_priv->display.crtc_enable(&crtc->base);
3193 }
3194 drm_modeset_unlock_all(dev);
3195}
3196
3197static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3198{
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 struct intel_crtc *crtc =
3201 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3202
3203 drm_modeset_lock_all(dev);
3204 /*
3205 * If we use the eDP transcoder we need to make sure that we don't
3206 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3207 * relevant on hsw with pipe A when using the always-on power well
3208 * routing.
3209 */
3210 if (crtc->config.pch_pfit.force_thru) {
3211 crtc->config.pch_pfit.force_thru = false;
3212
3213 dev_priv->display.crtc_disable(&crtc->base);
3214 dev_priv->display.crtc_enable(&crtc->base);
3215
3216 intel_display_power_put(dev_priv,
3217 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3218 }
3219 drm_modeset_unlock_all(dev);
3220}
3221
3222static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3223 enum pipe pipe,
3224 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3225 uint32_t *val)
3226{
46a19188
DV		 3227 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3228 *source = INTEL_PIPE_CRC_SOURCE_PF;
3229
3230 switch (*source) {
5b3a856b
DV		 3231 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3232 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3233 break;
3234 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3235 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3236 break;
3237 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3238 if (IS_HASWELL(dev) && pipe == PIPE_A)
3239 hsw_trans_edp_pipe_A_crc_wa(dev);
3240
5b3a856b
DV		 3241 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3242 break;
3d099a05 3243 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3244 *val = 0;
3245 break;
3d099a05
DV		 3246 default:
3247 return -EINVAL;
5b3a856b
DV		 3248 }
3249
3250 return 0;
3251}
3252
926321d5
DV		 3253static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3254 enum intel_pipe_crc_source source)
3255{
3256 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3257 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 3258 u32 val = 0; /* shut up gcc */
5b3a856b 3259 int ret;
926321d5 3260
cc3da175
DL		 3261 if (pipe_crc->source == source)
3262 return 0;
3263
ae676fcd
DL		 3264 /* forbid changing the source without going back to 'none' */
3265 if (pipe_crc->source && source)
3266 return -EINVAL;
3267
52f843f6 3268 if (IS_GEN2(dev))
46a19188 3269 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3270 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3271 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3272 else if (IS_VALLEYVIEW(dev))
fabf6e51 3273 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3274 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3275 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3276 else
fabf6e51 3277 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3278
3279 if (ret != 0)
3280 return ret;
3281
4b584369
DL		 3282 /* none -> real source transition */
3283 if (source) {
7cd6ccff
DL		 3284 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3285 pipe_name(pipe), pipe_crc_source_name(source));
3286
e5f75aca
DL		 3287 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
3288 INTEL_PIPE_CRC_ENTRIES_NR,
3289 GFP_KERNEL);
3290 if (!pipe_crc->entries)
3291 return -ENOMEM;
3292
d538bbdf
DL		 3293 spin_lock_irq(&pipe_crc->lock);
3294 pipe_crc->head = 0;
3295 pipe_crc->tail = 0;
3296 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3297 }
3298
cc3da175 3299 pipe_crc->source = source;
926321d5 3300
926321d5
DV		 3301 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3302 POSTING_READ(PIPE_CRC_CTL(pipe));
3303
e5f75aca
DL		 3304 /* real source -> none transition */
3305 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3306 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3307 struct intel_crtc *crtc =
3308 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3309
7cd6ccff
DL		 3310 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3311 pipe_name(pipe));
3312
a33d7105
DV		 3313 drm_modeset_lock(&crtc->base.mutex, NULL);
3314 if (crtc->active)
3315 intel_wait_for_vblank(dev, pipe);
3316 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3317
d538bbdf
DL		 3318 spin_lock_irq(&pipe_crc->lock);
3319 entries = pipe_crc->entries;
e5f75aca 3320 pipe_crc->entries = NULL;
d538bbdf
DL		 3321 spin_unlock_irq(&pipe_crc->lock);
3322
3323 kfree(entries);
84093603
DV		 3324
3325 if (IS_G4X(dev))
3326 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3327 else if (IS_VALLEYVIEW(dev))
3328 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3329 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3330 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
e5f75aca
DL		 3331 }
3332
926321d5
DV		 3333 return 0;
3334}
3335
3336/*
3337 * Parse pipe CRC command strings:
b94dec87
DL		 3338 * command: wsp* object wsp+ name wsp+ source wsp*
3339 * object: 'pipe'
3340 * name: (A | B | C)
926321d5
DV		 3341 * source: (none | plane1 | plane2 | pf)
3342 * wsp: (#0x20 | #0x9 | #0xA)+
3343 *
3344 * eg.:
b94dec87
DL		 3345 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3346 * "pipe A none" -> Stop CRC
926321d5 3347 */
bd9db02f 3348static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3349{
3350 int n_words = 0;
3351
3352 while (*buf) {
3353 char *end;
3354
3355 /* skip leading white space */
3356 buf = skip_spaces(buf);
3357 if (!*buf)
3358 break; /* end of buffer */
3359
3360 /* find end of word */
3361 for (end = buf; *end && !isspace(*end); end++)
3362 ;
3363
3364 if (n_words == max_words) {
3365 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3366 max_words);
3367 return -EINVAL; /* ran out of words[] before bytes */
3368 }
3369
3370 if (*end)
3371 *end++ = '\0';
3372 words[n_words++] = buf;
3373 buf = end;
3374 }
3375
3376 return n_words;
3377}
3378
b94dec87
DL		 3379enum intel_pipe_crc_object {
3380 PIPE_CRC_OBJECT_PIPE,
3381};
3382
e8dfcf78 3383static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3384 "pipe",
3385};
3386
3387static int
bd9db02f 3388display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3389{
3390 int i;
3391
3392 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3393 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3394 *o = i;
b94dec87
DL		 3395 return 0;
3396 }
3397
3398 return -EINVAL;
3399}
3400
bd9db02f 3401static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3402{
3403 const char name = buf[0];
3404
3405 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3406 return -EINVAL;
3407
3408 *pipe = name - 'A';
3409
3410 return 0;
3411}
3412
3413static int
bd9db02f 3414display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3415{
3416 int i;
3417
3418 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3419 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3420 *s = i;
926321d5
DV		 3421 return 0;
3422 }
3423
3424 return -EINVAL;
3425}
3426
bd9db02f 3427static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3428{
b94dec87 3429#define N_WORDS 3
926321d5 3430 int n_words;
b94dec87 3431 char *words[N_WORDS];
926321d5 3432 enum pipe pipe;
b94dec87 3433 enum intel_pipe_crc_object object;
926321d5
DV		 3434 enum intel_pipe_crc_source source;
3435
bd9db02f 3436 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3437 if (n_words != N_WORDS) {
3438 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3439 N_WORDS);
3440 return -EINVAL;
3441 }
3442
bd9db02f 3443 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3444 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3445 return -EINVAL;
3446 }
3447
bd9db02f 3448 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3449 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3450 return -EINVAL;
3451 }
3452
bd9db02f 3453 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3454 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3455 return -EINVAL;
3456 }
3457
3458 return pipe_crc_set_source(dev, pipe, source);
3459}
3460
bd9db02f
DL		 3461static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3462 size_t len, loff_t *offp)
926321d5
DV		 3463{
3464 struct seq_file *m = file->private_data;
3465 struct drm_device *dev = m->private;
3466 char *tmpbuf;
3467 int ret;
3468
3469 if (len == 0)
3470 return 0;
3471
3472 if (len > PAGE_SIZE - 1) {
3473 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3474 PAGE_SIZE);
3475 return -E2BIG;
3476 }
3477
3478 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3479 if (!tmpbuf)
3480 return -ENOMEM;
3481
3482 if (copy_from_user(tmpbuf, ubuf, len)) {
3483 ret = -EFAULT;
3484 goto out;
3485 }
3486 tmpbuf[len] = '\0';
3487
bd9db02f 3488 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3489
3490out:
3491 kfree(tmpbuf);
3492 if (ret < 0)
3493 return ret;
3494
3495 *offp += len;
3496 return len;
3497}
3498
bd9db02f 3499static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3500 .owner = THIS_MODULE,
bd9db02f 3501 .open = display_crc_ctl_open,
926321d5
DV		 3502 .read = seq_read,
3503 .llseek = seq_lseek,
3504 .release = single_release,
bd9db02f 3505 .write = display_crc_ctl_write
926321d5
DV		 3506};
3507
369a1342
VS		 3508static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3509{
3510 struct drm_device *dev = m->private;
546c81fd 3511 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3512 int level;
3513
3514 drm_modeset_lock_all(dev);
3515
3516 for (level = 0; level < num_levels; level++) {
3517 unsigned int latency = wm[level];
3518
3519 /* WM1+ latency values in 0.5us units */
3520 if (level > 0)
3521 latency *= 5;
3522
3523 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3524 level, wm[level],
3525 latency / 10, latency % 10);
3526 }
3527
3528 drm_modeset_unlock_all(dev);
3529}
3530
3531static int pri_wm_latency_show(struct seq_file *m, void *data)
3532{
3533 struct drm_device *dev = m->private;
3534
3535 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3536
3537 return 0;
3538}
3539
3540static int spr_wm_latency_show(struct seq_file *m, void *data)
3541{
3542 struct drm_device *dev = m->private;
3543
3544 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3545
3546 return 0;
3547}
3548
3549static int cur_wm_latency_show(struct seq_file *m, void *data)
3550{
3551 struct drm_device *dev = m->private;
3552
3553 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3554
3555 return 0;
3556}
3557
3558static int pri_wm_latency_open(struct inode *inode, struct file *file)
3559{
3560 struct drm_device *dev = inode->i_private;
3561
9ad0257c 3562 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3563 return -ENODEV;
3564
3565 return single_open(file, pri_wm_latency_show, dev);
3566}
3567
3568static int spr_wm_latency_open(struct inode *inode, struct file *file)
3569{
3570 struct drm_device *dev = inode->i_private;
3571
9ad0257c 3572 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3573 return -ENODEV;
3574
3575 return single_open(file, spr_wm_latency_show, dev);
3576}
3577
3578static int cur_wm_latency_open(struct inode *inode, struct file *file)
3579{
3580 struct drm_device *dev = inode->i_private;
3581
9ad0257c 3582 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3583 return -ENODEV;
3584
3585 return single_open(file, cur_wm_latency_show, dev);
3586}
3587
3588static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3589 size_t len, loff_t *offp, uint16_t wm[5])
3590{
3591 struct seq_file *m = file->private_data;
3592 struct drm_device *dev = m->private;
3593 uint16_t new[5] = { 0 };
546c81fd 3594 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3595 int level;
3596 int ret;
3597 char tmp[32];
3598
3599 if (len >= sizeof(tmp))
3600 return -EINVAL;
3601
3602 if (copy_from_user(tmp, ubuf, len))
3603 return -EFAULT;
3604
3605 tmp[len] = '\0';
3606
3607 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3608 if (ret != num_levels)
3609 return -EINVAL;
3610
3611 drm_modeset_lock_all(dev);
3612
3613 for (level = 0; level < num_levels; level++)
3614 wm[level] = new[level];
3615
3616 drm_modeset_unlock_all(dev);
3617
3618 return len;
3619}
3620
3621
3622static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3623 size_t len, loff_t *offp)
3624{
3625 struct seq_file *m = file->private_data;
3626 struct drm_device *dev = m->private;
3627
3628 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3629}
3630
3631static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3632 size_t len, loff_t *offp)
3633{
3634 struct seq_file *m = file->private_data;
3635 struct drm_device *dev = m->private;
3636
3637 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3638}
3639
3640static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3641 size_t len, loff_t *offp)
3642{
3643 struct seq_file *m = file->private_data;
3644 struct drm_device *dev = m->private;
3645
3646 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3647}
3648
3649static const struct file_operations i915_pri_wm_latency_fops = {
3650 .owner = THIS_MODULE,
3651 .open = pri_wm_latency_open,
3652 .read = seq_read,
3653 .llseek = seq_lseek,
3654 .release = single_release,
3655 .write = pri_wm_latency_write
3656};
3657
3658static const struct file_operations i915_spr_wm_latency_fops = {
3659 .owner = THIS_MODULE,
3660 .open = spr_wm_latency_open,
3661 .read = seq_read,
3662 .llseek = seq_lseek,
3663 .release = single_release,
3664 .write = spr_wm_latency_write
3665};
3666
3667static const struct file_operations i915_cur_wm_latency_fops = {
3668 .owner = THIS_MODULE,
3669 .open = cur_wm_latency_open,
3670 .read = seq_read,
3671 .llseek = seq_lseek,
3672 .release = single_release,
3673 .write = cur_wm_latency_write
3674};
3675
647416f9
KC		 3676static int
3677i915_wedged_get(void *data, u64 *val)
f3cd474b 3678{
647416f9 3679 struct drm_device *dev = data;
e277a1f8 3680 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3681
647416f9 3682 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3683
647416f9 3684 return 0;
f3cd474b
CW		 3685}
3686
647416f9
KC		 3687static int
3688i915_wedged_set(void *data, u64 val)
f3cd474b 3689{
647416f9 3690 struct drm_device *dev = data;
d46c0517
ID		 3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692
3693 intel_runtime_pm_get(dev_priv);
f3cd474b 3694
58174462
MK		 3695 i915_handle_error(dev, val,
3696 "Manually setting wedged to %llu", val);
d46c0517
ID		 3697
3698 intel_runtime_pm_put(dev_priv);
3699
647416f9 3700 return 0;
f3cd474b
CW		 3701}
3702
647416f9
KC		 3703DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3704 i915_wedged_get, i915_wedged_set,
3a3b4f98 3705 "%llu\n");
f3cd474b 3706
647416f9
KC		 3707static int
3708i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3709{
647416f9 3710 struct drm_device *dev = data;
e277a1f8 3711 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3712
647416f9 3713 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3714
647416f9 3715 return 0;
e5eb3d63
DV		 3716}
3717
647416f9
KC		 3718static int
3719i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3720{
647416f9 3721 struct drm_device *dev = data;
e5eb3d63 3722 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3723 int ret;
e5eb3d63 3724
647416f9 3725 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3726
22bcfc6a
DV		 3727 ret = mutex_lock_interruptible(&dev->struct_mutex);
3728 if (ret)
3729 return ret;
3730
99584db3 3731 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3732 mutex_unlock(&dev->struct_mutex);
3733
647416f9 3734 return 0;
e5eb3d63
DV		 3735}
3736
647416f9
KC		 3737DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3738 i915_ring_stop_get, i915_ring_stop_set,
3739 "0x%08llx\n");
d5442303 3740
094f9a54
CW		 3741static int
3742i915_ring_missed_irq_get(void *data, u64 *val)
3743{
3744 struct drm_device *dev = data;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746
3747 *val = dev_priv->gpu_error.missed_irq_rings;
3748 return 0;
3749}
3750
3751static int
3752i915_ring_missed_irq_set(void *data, u64 val)
3753{
3754 struct drm_device *dev = data;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 int ret;
3757
3758 /* Lock against concurrent debugfs callers */
3759 ret = mutex_lock_interruptible(&dev->struct_mutex);
3760 if (ret)
3761 return ret;
3762 dev_priv->gpu_error.missed_irq_rings = val;
3763 mutex_unlock(&dev->struct_mutex);
3764
3765 return 0;
3766}
3767
3768DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3769 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3770 "0x%08llx\n");
3771
3772static int
3773i915_ring_test_irq_get(void *data, u64 *val)
3774{
3775 struct drm_device *dev = data;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777
3778 *val = dev_priv->gpu_error.test_irq_rings;
3779
3780 return 0;
3781}
3782
3783static int
3784i915_ring_test_irq_set(void *data, u64 val)
3785{
3786 struct drm_device *dev = data;
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 int ret;
3789
3790 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3791
3792 /* Lock against concurrent debugfs callers */
3793 ret = mutex_lock_interruptible(&dev->struct_mutex);
3794 if (ret)
3795 return ret;
3796
3797 dev_priv->gpu_error.test_irq_rings = val;
3798 mutex_unlock(&dev->struct_mutex);
3799
3800 return 0;
3801}
3802
3803DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3804 i915_ring_test_irq_get, i915_ring_test_irq_set,
3805 "0x%08llx\n");
3806
dd624afd
CW		 3807#define DROP_UNBOUND 0x1
3808#define DROP_BOUND 0x2
3809#define DROP_RETIRE 0x4
3810#define DROP_ACTIVE 0x8
3811#define DROP_ALL (DROP_UNBOUND | \
3812 DROP_BOUND | \
3813 DROP_RETIRE | \
3814 DROP_ACTIVE)
647416f9
KC		 3815static int
3816i915_drop_caches_get(void *data, u64 *val)
dd624afd 3817{
647416f9 3818 *val = DROP_ALL;
dd624afd 3819
647416f9 3820 return 0;
dd624afd
CW		 3821}
3822
647416f9
KC		 3823static int
3824i915_drop_caches_set(void *data, u64 val)
dd624afd 3825{
647416f9 3826 struct drm_device *dev = data;
dd624afd 3827 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3828 int ret;
dd624afd 3829
2f9fe5ff 3830 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3831
3832 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3833 * on ioctls on -EAGAIN. */
3834 ret = mutex_lock_interruptible(&dev->struct_mutex);
3835 if (ret)
3836 return ret;
3837
3838 if (val & DROP_ACTIVE) {
3839 ret = i915_gpu_idle(dev);
3840 if (ret)
3841 goto unlock;
3842 }
3843
3844 if (val & (DROP_RETIRE | DROP_ACTIVE))
3845 i915_gem_retire_requests(dev);
3846
21ab4e74
CW		 3847 if (val & DROP_BOUND)
3848 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 3849
21ab4e74
CW		 3850 if (val & DROP_UNBOUND)
3851 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 3852
3853unlock:
3854 mutex_unlock(&dev->struct_mutex);
3855
647416f9 3856 return ret;
dd624afd
CW		 3857}
3858
647416f9
KC		 3859DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3860 i915_drop_caches_get, i915_drop_caches_set,
3861 "0x%08llx\n");
dd624afd 3862
647416f9
KC		 3863static int
3864i915_max_freq_get(void *data, u64 *val)
358733e9 3865{
647416f9 3866 struct drm_device *dev = data;
e277a1f8 3867 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3868 int ret;
004777cb 3869
daa3afb2 3870 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3871 return -ENODEV;
3872
5c9669ce
TR		 3873 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3874
4fc688ce 3875 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3876 if (ret)
3877 return ret;
358733e9 3878
0a073b84 3879 if (IS_VALLEYVIEW(dev))
b39fb297 3880 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 3881 else
b39fb297 3882 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3883 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3884
647416f9 3885 return 0;
358733e9
JB		 3886}
3887
647416f9
KC		 3888static int
3889i915_max_freq_set(void *data, u64 val)
358733e9 3890{
647416f9 3891 struct drm_device *dev = data;
358733e9 3892 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3893 u32 rp_state_cap, hw_max, hw_min;
647416f9 3894 int ret;
004777cb 3895
daa3afb2 3896 if (INTEL_INFO(dev)->gen < 6)
004777cb 3897 return -ENODEV;
358733e9 3898
5c9669ce
TR		 3899 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3900
647416f9 3901 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3902
4fc688ce 3903 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3904 if (ret)
3905 return ret;
3906
358733e9
JB		 3907 /*
3908 * Turbo will still be enabled, but won't go above the set value.
3909 */
0a073b84 3910 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3911 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 3912
03af2045
VS		 3913 hw_max = dev_priv->rps.max_freq;
3914 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 3915 } else {
3916 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3917
3918 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3919 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3920 hw_min = (rp_state_cap >> 16) & 0xff;
3921 }
3922
b39fb297 3923 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 3924 mutex_unlock(&dev_priv->rps.hw_lock);
3925 return -EINVAL;
0a073b84
JB		 3926 }
3927
b39fb297 3928 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 3929
3930 if (IS_VALLEYVIEW(dev))
3931 valleyview_set_rps(dev, val);
3932 else
3933 gen6_set_rps(dev, val);
3934
4fc688ce 3935 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3936
647416f9 3937 return 0;
358733e9
JB		 3938}
3939
647416f9
KC		 3940DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3941 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3942 "%llu\n");
358733e9 3943
647416f9
KC		 3944static int
3945i915_min_freq_get(void *data, u64 *val)
1523c310 3946{
647416f9 3947 struct drm_device *dev = data;
e277a1f8 3948 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3949 int ret;
004777cb 3950
daa3afb2 3951 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3952 return -ENODEV;
3953
5c9669ce
TR		 3954 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3955
4fc688ce 3956 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3957 if (ret)
3958 return ret;
1523c310 3959
0a073b84 3960 if (IS_VALLEYVIEW(dev))
b39fb297 3961 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 3962 else
b39fb297 3963 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3964 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3965
647416f9 3966 return 0;
1523c310
JB		 3967}
3968
647416f9
KC		 3969static int
3970i915_min_freq_set(void *data, u64 val)
1523c310 3971{
647416f9 3972 struct drm_device *dev = data;
1523c310 3973 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3974 u32 rp_state_cap, hw_max, hw_min;
647416f9 3975 int ret;
004777cb 3976
daa3afb2 3977 if (INTEL_INFO(dev)->gen < 6)
004777cb 3978 return -ENODEV;
1523c310 3979
5c9669ce
TR		 3980 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3981
647416f9 3982 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3983
4fc688ce 3984 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3985 if (ret)
3986 return ret;
3987
1523c310
JB		 3988 /*
3989 * Turbo will still be enabled, but won't go below the set value.
3990 */
0a073b84 3991 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3992 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 3993
03af2045
VS		 3994 hw_max = dev_priv->rps.max_freq;
3995 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 3996 } else {
3997 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3998
3999 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4000 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4001 hw_min = (rp_state_cap >> 16) & 0xff;
4002 }
4003
b39fb297 4004 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4005 mutex_unlock(&dev_priv->rps.hw_lock);
4006 return -EINVAL;
0a073b84 4007 }
dd0a1aa1 4008
b39fb297 4009 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 4010
4011 if (IS_VALLEYVIEW(dev))
4012 valleyview_set_rps(dev, val);
4013 else
4014 gen6_set_rps(dev, val);
4015
4fc688ce 4016 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4017
647416f9 4018 return 0;
1523c310
JB		 4019}
4020
647416f9
KC		 4021DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4022 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4023 "%llu\n");
1523c310 4024
647416f9
KC		 4025static int
4026i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4027{
647416f9 4028 struct drm_device *dev = data;
e277a1f8 4029 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4030 u32 snpcr;
647416f9 4031 int ret;
07b7ddd9 4032
004777cb
DV		 4033 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4034 return -ENODEV;
4035
22bcfc6a
DV		 4036 ret = mutex_lock_interruptible(&dev->struct_mutex);
4037 if (ret)
4038 return ret;
c8c8fb33 4039 intel_runtime_pm_get(dev_priv);
22bcfc6a 4040
07b7ddd9 4041 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4042
4043 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4044 mutex_unlock(&dev_priv->dev->struct_mutex);
4045
647416f9 4046 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4047
647416f9 4048 return 0;
07b7ddd9
JB		 4049}
4050
647416f9
KC		 4051static int
4052i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4053{
647416f9 4054 struct drm_device *dev = data;
07b7ddd9 4055 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4056 u32 snpcr;
07b7ddd9 4057
004777cb
DV		 4058 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4059 return -ENODEV;
4060
647416f9 4061 if (val > 3)
07b7ddd9
JB		 4062 return -EINVAL;
4063
c8c8fb33 4064 intel_runtime_pm_get(dev_priv);
647416f9 4065 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4066
4067 /* Update the cache sharing policy here as well */
4068 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4069 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4070 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4071 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4072
c8c8fb33 4073 intel_runtime_pm_put(dev_priv);
647416f9 4074 return 0;
07b7ddd9
JB		 4075}
4076
647416f9
KC		 4077DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4078 i915_cache_sharing_get, i915_cache_sharing_set,
4079 "%llu\n");
07b7ddd9 4080
6d794d42
BW		 4081static int i915_forcewake_open(struct inode *inode, struct file *file)
4082{
4083 struct drm_device *dev = inode->i_private;
4084 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4085
075edca4 4086 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4087 return 0;
4088
c8d9a590 4089 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4090
4091 return 0;
4092}
4093
c43b5634 4094static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4095{
4096 struct drm_device *dev = inode->i_private;
4097 struct drm_i915_private *dev_priv = dev->dev_private;
4098
075edca4 4099 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4100 return 0;
4101
c8d9a590 4102 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4103
4104 return 0;
4105}
4106
4107static const struct file_operations i915_forcewake_fops = {
4108 .owner = THIS_MODULE,
4109 .open = i915_forcewake_open,
4110 .release = i915_forcewake_release,
4111};
4112
4113static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4114{
4115 struct drm_device *dev = minor->dev;
4116 struct dentry *ent;
4117
4118 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4119 S_IRUSR,
6d794d42
BW		 4120 root, dev,
4121 &i915_forcewake_fops);
f3c5fe97
WY		 4122 if (!ent)
4123 return -ENOMEM;
6d794d42 4124
8eb57294 4125 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4126}
4127
6a9c308d
DV		 4128static int i915_debugfs_create(struct dentry *root,
4129 struct drm_minor *minor,
4130 const char *name,
4131 const struct file_operations *fops)
07b7ddd9
JB		 4132{
4133 struct drm_device *dev = minor->dev;
4134 struct dentry *ent;
4135
6a9c308d 4136 ent = debugfs_create_file(name,
07b7ddd9
JB		 4137 S_IRUGO | S_IWUSR,
4138 root, dev,
6a9c308d 4139 fops);
f3c5fe97
WY		 4140 if (!ent)
4141 return -ENOMEM;
07b7ddd9 4142
6a9c308d 4143 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4144}
4145
06c5bf8c 4146static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4147 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4148 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4149 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4150 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4151 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4152 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4153 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4154 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4155 {"i915_gem_request", i915_gem_request_info, 0},
4156 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4157 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4158 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4159 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4160 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4161 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4162 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
adb4bd12 4163 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 4164 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4165 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4166 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4167 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4168 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4169 {"i915_sr_status", i915_sr_status, 0},
44834a67 4170 {"i915_opregion", i915_opregion, 0},
37811fcc 4171 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4172 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4173 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4174 {"i915_execlists", i915_execlists, 0},
6d794d42 4175 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 4176 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4177 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4178 {"i915_llc", i915_llc, 0},
e91fd8c6 4179 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4180 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4181 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4182 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4183 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4184 {"i915_display_info", i915_display_info, 0},
e04934cf 4185 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4186 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4187 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4188 {"i915_wa_registers", i915_wa_registers, 0},
2017263e 4189};
27c202ad 4190#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4191
06c5bf8c 4192static const struct i915_debugfs_files {
34b9674c
DV		 4193 const char *name;
4194 const struct file_operations *fops;
4195} i915_debugfs_files[] = {
4196 {"i915_wedged", &i915_wedged_fops},
4197 {"i915_max_freq", &i915_max_freq_fops},
4198 {"i915_min_freq", &i915_min_freq_fops},
4199 {"i915_cache_sharing", &i915_cache_sharing_fops},
4200 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4201 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4202 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4203 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4204 {"i915_error_state", &i915_error_state_fops},
4205 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4206 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4207 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4208 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4209 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4210 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4211};
4212
07144428
DL		 4213void intel_display_crc_init(struct drm_device *dev)
4214{
4215 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4216 enum pipe pipe;
07144428 4217
055e393f 4218 for_each_pipe(dev_priv, pipe) {
b378360e 4219 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4220
d538bbdf
DL		 4221 pipe_crc->opened = false;
4222 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4223 init_waitqueue_head(&pipe_crc->wq);
4224 }
4225}
4226
27c202ad 4227int i915_debugfs_init(struct drm_minor *minor)
2017263e 4228{
34b9674c 4229 int ret, i;
f3cd474b 4230
6d794d42 4231 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4232 if (ret)
4233 return ret;
6a9c308d 4234
07144428
DL		 4235 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4236 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4237 if (ret)
4238 return ret;
4239 }
4240
34b9674c
DV		 4241 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4242 ret = i915_debugfs_create(minor->debugfs_root, minor,
4243 i915_debugfs_files[i].name,
4244 i915_debugfs_files[i].fops);
4245 if (ret)
4246 return ret;
4247 }
40633219 4248
27c202ad
BG		 4249 return drm_debugfs_create_files(i915_debugfs_list,
4250 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4251 minor->debugfs_root, minor);
4252}
4253
27c202ad 4254void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4255{
34b9674c
DV		 4256 int i;
4257
27c202ad
BG		 4258 drm_debugfs_remove_files(i915_debugfs_list,
4259 I915_DEBUGFS_ENTRIES, minor);
07144428 4260
6d794d42
BW		 4261 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4262 1, minor);
07144428 4263
e309a997 4264 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4265 struct drm_info_list *info_list =
4266 (struct drm_info_list *)&i915_pipe_crc_data[i];
4267
4268 drm_debugfs_remove_files(info_list, 1, minor);
4269 }
4270
34b9674c
DV		 4271 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4272 struct drm_info_list *info_list =
4273 (struct drm_info_list *) i915_debugfs_files[i].fops;
4274
4275 drm_debugfs_remove_files(info_list, 1, minor);
4276 }
2017263e 4277}
Linux 6.x block layer and io_uring tree(s)