drm/i915: allow 945 to control self refresh (CxSR) automatically
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
f3cd474b 30#include <linux/debugfs.h>
5a0e3ad6 31#include <linux/slab.h>
2017263e
BG
32#include "drmP.h"
33#include "drm.h"
4e5359cd 34#include "intel_drv.h"
e5c65260 35#include "intel_ringbuffer.h"
2017263e
BG
36#include "i915_drm.h"
37#include "i915_drv.h"
38
39#define DRM_I915_RING_DEBUG 1
40
41
42#if defined(CONFIG_DEBUG_FS)
43
f13d3f73 44enum {
69dc4987 45 ACTIVE_LIST,
f13d3f73
CW
46 FLUSHING_LIST,
47 INACTIVE_LIST,
d21d5975
CW
48 PINNED_LIST,
49 DEFERRED_FREE_LIST,
f13d3f73 50};
2017263e 51
70d39fe4
CW
52static const char *yesno(int v)
53{
54 return v ? "yes" : "no";
55}
56
57static int i915_capabilities(struct seq_file *m, void *data)
58{
59 struct drm_info_node *node = (struct drm_info_node *) m->private;
60 struct drm_device *dev = node->minor->dev;
61 const struct intel_device_info *info = INTEL_INFO(dev);
62
63 seq_printf(m, "gen: %d\n", info->gen);
64#define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65 B(is_mobile);
70d39fe4
CW
66 B(is_i85x);
67 B(is_i915g);
70d39fe4 68 B(is_i945gm);
70d39fe4
CW
69 B(is_g33);
70 B(need_gfx_hws);
71 B(is_g4x);
72 B(is_pineview);
73 B(is_broadwater);
74 B(is_crestline);
70d39fe4 75 B(has_fbc);
70d39fe4
CW
76 B(has_pipe_cxsr);
77 B(has_hotplug);
78 B(cursor_needs_physical);
79 B(has_overlay);
80 B(overlay_needs_physical);
a6c45cf0 81 B(supports_tv);
549f7365
CW
82 B(has_bsd_ring);
83 B(has_blt_ring);
70d39fe4
CW
84#undef B
85
86 return 0;
87}
2017263e 88
05394f39 89static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 90{
05394f39 91 if (obj->user_pin_count > 0)
a6172a80 92 return "P";
05394f39 93 else if (obj->pin_count > 0)
a6172a80
CW
94 return "p";
95 else
96 return " ";
97}
98
05394f39 99static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 100{
05394f39 101 switch (obj->tiling_mode) {
a6172a80
CW
102 default:
103 case I915_TILING_NONE: return " ";
104 case I915_TILING_X: return "X";
105 case I915_TILING_Y: return "Y";
106 }
107}
108
08c18323
CW
109static const char *agp_type_str(int type)
110{
111 switch (type) {
112 case 0: return " uncached";
113 case 1: return " snooped";
114 default: return "";
115 }
116}
117
37811fcc
CW
118static void
119describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
120{
08c18323 121 seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s",
37811fcc
CW
122 &obj->base,
123 get_pin_flag(obj),
124 get_tiling_flag(obj),
125 obj->base.size,
126 obj->base.read_domains,
127 obj->base.write_domain,
128 obj->last_rendering_seqno,
caea7476 129 obj->last_fenced_seqno,
08c18323 130 agp_type_str(obj->agp_type == AGP_USER_CACHED_MEMORY),
37811fcc
CW
131 obj->dirty ? " dirty" : "",
132 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
133 if (obj->base.name)
134 seq_printf(m, " (name: %d)", obj->base.name);
135 if (obj->fence_reg != I915_FENCE_REG_NONE)
136 seq_printf(m, " (fence: %d)", obj->fence_reg);
137 if (obj->gtt_space != NULL)
a00b10c3
CW
138 seq_printf(m, " (gtt offset: %08x, size: %08x)",
139 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
6299f992
CW
140 if (obj->pin_mappable || obj->fault_mappable) {
141 char s[3], *t = s;
142 if (obj->pin_mappable)
143 *t++ = 'p';
144 if (obj->fault_mappable)
145 *t++ = 'f';
146 *t = '\0';
147 seq_printf(m, " (%s mappable)", s);
148 }
69dc4987
CW
149 if (obj->ring != NULL)
150 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW
151}
152
433e12f7 153static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG
154{
155 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG
156 uintptr_t list = (uintptr_t) node->info_ent->data;
157 struct list_head *head;
2017263e
BG
158 struct drm_device *dev = node->minor->dev;
159 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 160 struct drm_i915_gem_object *obj;
8f2480fb
CW
161 size_t total_obj_size, total_gtt_size;
162 int count, ret;
de227ef0
CW
163
164 ret = mutex_lock_interruptible(&dev->struct_mutex);
165 if (ret)
166 return ret;
2017263e 167
433e12f7
BG
168 switch (list) {
169 case ACTIVE_LIST:
170 seq_printf(m, "Active:\n");
69dc4987 171 head = &dev_priv->mm.active_list;
433e12f7
BG
172 break;
173 case INACTIVE_LIST:
a17458fc 174 seq_printf(m, "Inactive:\n");
433e12f7
BG
175 head = &dev_priv->mm.inactive_list;
176 break;
f13d3f73
CW
177 case PINNED_LIST:
178 seq_printf(m, "Pinned:\n");
179 head = &dev_priv->mm.pinned_list;
180 break;
433e12f7
BG
181 case FLUSHING_LIST:
182 seq_printf(m, "Flushing:\n");
183 head = &dev_priv->mm.flushing_list;
184 break;
d21d5975
CW
185 case DEFERRED_FREE_LIST:
186 seq_printf(m, "Deferred free:\n");
187 head = &dev_priv->mm.deferred_free_list;
188 break;
433e12f7 189 default:
de227ef0
CW
190 mutex_unlock(&dev->struct_mutex);
191 return -EINVAL;
2017263e 192 }
2017263e 193
8f2480fb 194 total_obj_size = total_gtt_size = count = 0;
05394f39 195 list_for_each_entry(obj, head, mm_list) {
37811fcc 196 seq_printf(m, " ");
05394f39 197 describe_obj(m, obj);
f4ceda89 198 seq_printf(m, "\n");
05394f39
CW
199 total_obj_size += obj->base.size;
200 total_gtt_size += obj->gtt_space->size;
8f2480fb 201 count++;
2017263e 202 }
de227ef0 203 mutex_unlock(&dev->struct_mutex);
5e118f41 204
8f2480fb
CW
205 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
206 count, total_obj_size, total_gtt_size);
2017263e
BG
207 return 0;
208}
209
6299f992
CW
210#define count_objects(list, member) do { \
211 list_for_each_entry(obj, list, member) { \
212 size += obj->gtt_space->size; \
213 ++count; \
214 if (obj->map_and_fenceable) { \
215 mappable_size += obj->gtt_space->size; \
216 ++mappable_count; \
217 } \
218 } \
219} while(0)
220
73aa808f
CW
221static int i915_gem_object_info(struct seq_file *m, void* data)
222{
223 struct drm_info_node *node = (struct drm_info_node *) m->private;
224 struct drm_device *dev = node->minor->dev;
225 struct drm_i915_private *dev_priv = dev->dev_private;
6299f992
CW
226 u32 count, mappable_count;
227 size_t size, mappable_size;
228 struct drm_i915_gem_object *obj;
73aa808f
CW
229 int ret;
230
231 ret = mutex_lock_interruptible(&dev->struct_mutex);
232 if (ret)
233 return ret;
234
6299f992
CW
235 seq_printf(m, "%u objects, %zu bytes\n",
236 dev_priv->mm.object_count,
237 dev_priv->mm.object_memory);
238
239 size = count = mappable_size = mappable_count = 0;
240 count_objects(&dev_priv->mm.gtt_list, gtt_list);
241 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
242 count, mappable_count, size, mappable_size);
243
244 size = count = mappable_size = mappable_count = 0;
245 count_objects(&dev_priv->mm.active_list, mm_list);
246 count_objects(&dev_priv->mm.flushing_list, mm_list);
247 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
248 count, mappable_count, size, mappable_size);
249
250 size = count = mappable_size = mappable_count = 0;
251 count_objects(&dev_priv->mm.pinned_list, mm_list);
252 seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
253 count, mappable_count, size, mappable_size);
254
255 size = count = mappable_size = mappable_count = 0;
256 count_objects(&dev_priv->mm.inactive_list, mm_list);
257 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
258 count, mappable_count, size, mappable_size);
259
260 size = count = mappable_size = mappable_count = 0;
261 count_objects(&dev_priv->mm.deferred_free_list, mm_list);
262 seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
263 count, mappable_count, size, mappable_size);
264
265 size = count = mappable_size = mappable_count = 0;
266 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
267 if (obj->fault_mappable) {
268 size += obj->gtt_space->size;
269 ++count;
270 }
271 if (obj->pin_mappable) {
272 mappable_size += obj->gtt_space->size;
273 ++mappable_count;
274 }
275 }
276 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
277 mappable_count, mappable_size);
278 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
279 count, size);
280
281 seq_printf(m, "%zu [%zu] gtt total\n",
282 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
73aa808f
CW
283
284 mutex_unlock(&dev->struct_mutex);
285
286 return 0;
287}
288
08c18323
CW
289static int i915_gem_gtt_info(struct seq_file *m, void* data)
290{
291 struct drm_info_node *node = (struct drm_info_node *) m->private;
292 struct drm_device *dev = node->minor->dev;
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 struct drm_i915_gem_object *obj;
295 size_t total_obj_size, total_gtt_size;
296 int count, ret;
297
298 ret = mutex_lock_interruptible(&dev->struct_mutex);
299 if (ret)
300 return ret;
301
302 total_obj_size = total_gtt_size = count = 0;
303 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
304 seq_printf(m, " ");
305 describe_obj(m, obj);
306 seq_printf(m, "\n");
307 total_obj_size += obj->base.size;
308 total_gtt_size += obj->gtt_space->size;
309 count++;
310 }
311
312 mutex_unlock(&dev->struct_mutex);
313
314 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
315 count, total_obj_size, total_gtt_size);
316
317 return 0;
318}
319
73aa808f 320
4e5359cd
SF
321static int i915_gem_pageflip_info(struct seq_file *m, void *data)
322{
323 struct drm_info_node *node = (struct drm_info_node *) m->private;
324 struct drm_device *dev = node->minor->dev;
325 unsigned long flags;
326 struct intel_crtc *crtc;
327
328 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
329 const char *pipe = crtc->pipe ? "B" : "A";
330 const char *plane = crtc->plane ? "B" : "A";
331 struct intel_unpin_work *work;
332
333 spin_lock_irqsave(&dev->event_lock, flags);
334 work = crtc->unpin_work;
335 if (work == NULL) {
336 seq_printf(m, "No flip due on pipe %s (plane %s)\n",
337 pipe, plane);
338 } else {
339 if (!work->pending) {
340 seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
341 pipe, plane);
342 } else {
343 seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
344 pipe, plane);
345 }
346 if (work->enable_stall_check)
347 seq_printf(m, "Stall check enabled, ");
348 else
349 seq_printf(m, "Stall check waiting for page flip ioctl, ");
350 seq_printf(m, "%d prepares\n", work->pending);
351
352 if (work->old_fb_obj) {
05394f39
CW
353 struct drm_i915_gem_object *obj = work->old_fb_obj;
354 if (obj)
355 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF
356 }
357 if (work->pending_flip_obj) {
05394f39
CW
358 struct drm_i915_gem_object *obj = work->pending_flip_obj;
359 if (obj)
360 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF
361 }
362 }
363 spin_unlock_irqrestore(&dev->event_lock, flags);
364 }
365
366 return 0;
367}
368
2017263e
BG
369static int i915_gem_request_info(struct seq_file *m, void *data)
370{
371 struct drm_info_node *node = (struct drm_info_node *) m->private;
372 struct drm_device *dev = node->minor->dev;
373 drm_i915_private_t *dev_priv = dev->dev_private;
374 struct drm_i915_gem_request *gem_request;
c2c347a9 375 int ret, count;
de227ef0
CW
376
377 ret = mutex_lock_interruptible(&dev->struct_mutex);
378 if (ret)
379 return ret;
2017263e 380
c2c347a9 381 count = 0;
1ec14ad3 382 if (!list_empty(&dev_priv->ring[RCS].request_list)) {
c2c347a9
CW
383 seq_printf(m, "Render requests:\n");
384 list_for_each_entry(gem_request,
1ec14ad3 385 &dev_priv->ring[RCS].request_list,
c2c347a9
CW
386 list) {
387 seq_printf(m, " %d @ %d\n",
388 gem_request->seqno,
389 (int) (jiffies - gem_request->emitted_jiffies));
390 }
391 count++;
392 }
1ec14ad3 393 if (!list_empty(&dev_priv->ring[VCS].request_list)) {
c2c347a9
CW
394 seq_printf(m, "BSD requests:\n");
395 list_for_each_entry(gem_request,
1ec14ad3 396 &dev_priv->ring[VCS].request_list,
c2c347a9
CW
397 list) {
398 seq_printf(m, " %d @ %d\n",
399 gem_request->seqno,
400 (int) (jiffies - gem_request->emitted_jiffies));
401 }
402 count++;
403 }
1ec14ad3 404 if (!list_empty(&dev_priv->ring[BCS].request_list)) {
c2c347a9
CW
405 seq_printf(m, "BLT requests:\n");
406 list_for_each_entry(gem_request,
1ec14ad3 407 &dev_priv->ring[BCS].request_list,
c2c347a9
CW
408 list) {
409 seq_printf(m, " %d @ %d\n",
410 gem_request->seqno,
411 (int) (jiffies - gem_request->emitted_jiffies));
412 }
413 count++;
2017263e 414 }
de227ef0
CW
415 mutex_unlock(&dev->struct_mutex);
416
c2c347a9
CW
417 if (count == 0)
418 seq_printf(m, "No requests\n");
419
2017263e
BG
420 return 0;
421}
422
b2223497
CW
423static void i915_ring_seqno_info(struct seq_file *m,
424 struct intel_ring_buffer *ring)
425{
426 if (ring->get_seqno) {
427 seq_printf(m, "Current sequence (%s): %d\n",
428 ring->name, ring->get_seqno(ring));
429 seq_printf(m, "Waiter sequence (%s): %d\n",
430 ring->name, ring->waiting_seqno);
431 seq_printf(m, "IRQ sequence (%s): %d\n",
432 ring->name, ring->irq_seqno);
433 }
434}
435
2017263e
BG
436static int i915_gem_seqno_info(struct seq_file *m, void *data)
437{
438 struct drm_info_node *node = (struct drm_info_node *) m->private;
439 struct drm_device *dev = node->minor->dev;
440 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 441 int ret, i;
de227ef0
CW
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
2017263e 446
1ec14ad3
CW
447 for (i = 0; i < I915_NUM_RINGS; i++)
448 i915_ring_seqno_info(m, &dev_priv->ring[i]);
de227ef0
CW
449
450 mutex_unlock(&dev->struct_mutex);
451
2017263e
BG
452 return 0;
453}
454
455
456static int i915_interrupt_info(struct seq_file *m, void *data)
457{
458 struct drm_info_node *node = (struct drm_info_node *) m->private;
459 struct drm_device *dev = node->minor->dev;
460 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 461 int ret, i;
de227ef0
CW
462
463 ret = mutex_lock_interruptible(&dev->struct_mutex);
464 if (ret)
465 return ret;
2017263e 466
bad720ff 467 if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW
468 seq_printf(m, "Interrupt enable: %08x\n",
469 I915_READ(IER));
470 seq_printf(m, "Interrupt identity: %08x\n",
471 I915_READ(IIR));
472 seq_printf(m, "Interrupt mask: %08x\n",
473 I915_READ(IMR));
474 seq_printf(m, "Pipe A stat: %08x\n",
475 I915_READ(PIPEASTAT));
476 seq_printf(m, "Pipe B stat: %08x\n",
477 I915_READ(PIPEBSTAT));
478 } else {
479 seq_printf(m, "North Display Interrupt enable: %08x\n",
480 I915_READ(DEIER));
481 seq_printf(m, "North Display Interrupt identity: %08x\n",
482 I915_READ(DEIIR));
483 seq_printf(m, "North Display Interrupt mask: %08x\n",
484 I915_READ(DEIMR));
485 seq_printf(m, "South Display Interrupt enable: %08x\n",
486 I915_READ(SDEIER));
487 seq_printf(m, "South Display Interrupt identity: %08x\n",
488 I915_READ(SDEIIR));
489 seq_printf(m, "South Display Interrupt mask: %08x\n",
490 I915_READ(SDEIMR));
491 seq_printf(m, "Graphics Interrupt enable: %08x\n",
492 I915_READ(GTIER));
493 seq_printf(m, "Graphics Interrupt identity: %08x\n",
494 I915_READ(GTIIR));
495 seq_printf(m, "Graphics Interrupt mask: %08x\n",
496 I915_READ(GTIMR));
497 }
2017263e
BG
498 seq_printf(m, "Interrupts received: %d\n",
499 atomic_read(&dev_priv->irq_received));
9862e600
CW
500 for (i = 0; i < I915_NUM_RINGS; i++) {
501 if (IS_GEN6(dev)) {
502 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
503 dev_priv->ring[i].name,
504 I915_READ_IMR(&dev_priv->ring[i]));
505 }
1ec14ad3 506 i915_ring_seqno_info(m, &dev_priv->ring[i]);
9862e600 507 }
de227ef0
CW
508 mutex_unlock(&dev->struct_mutex);
509
2017263e
BG
510 return 0;
511}
512
a6172a80
CW
513static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
514{
515 struct drm_info_node *node = (struct drm_info_node *) m->private;
516 struct drm_device *dev = node->minor->dev;
517 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW
518 int i, ret;
519
520 ret = mutex_lock_interruptible(&dev->struct_mutex);
521 if (ret)
522 return ret;
a6172a80
CW
523
524 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
525 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
526 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 527 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 528
c2c347a9
CW
529 seq_printf(m, "Fenced object[%2d] = ", i);
530 if (obj == NULL)
531 seq_printf(m, "unused");
532 else
05394f39 533 describe_obj(m, obj);
c2c347a9 534 seq_printf(m, "\n");
a6172a80
CW
535 }
536
05394f39 537 mutex_unlock(&dev->struct_mutex);
a6172a80
CW
538 return 0;
539}
540
2017263e
BG
541static int i915_hws_info(struct seq_file *m, void *data)
542{
543 struct drm_info_node *node = (struct drm_info_node *) m->private;
544 struct drm_device *dev = node->minor->dev;
545 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 546 struct intel_ring_buffer *ring;
2017263e 547 volatile u32 *hws;
4066c0ae
CW
548 int i;
549
1ec14ad3 550 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
4066c0ae 551 hws = (volatile u32 *)ring->status_page.page_addr;
2017263e
BG
552 if (hws == NULL)
553 return 0;
554
555 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
556 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
557 i * 4,
558 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
559 }
560 return 0;
561}
562
5cdf5881
CW
563static void i915_dump_object(struct seq_file *m,
564 struct io_mapping *mapping,
05394f39 565 struct drm_i915_gem_object *obj)
6911a9b8 566{
5cdf5881 567 int page, page_count, i;
6911a9b8 568
05394f39 569 page_count = obj->base.size / PAGE_SIZE;
6911a9b8 570 for (page = 0; page < page_count; page++) {
5cdf5881 571 u32 *mem = io_mapping_map_wc(mapping,
05394f39 572 obj->gtt_offset + page * PAGE_SIZE);
6911a9b8
BG
573 for (i = 0; i < PAGE_SIZE; i += 4)
574 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
5cdf5881 575 io_mapping_unmap(mem);
6911a9b8
BG
576 }
577}
578
579static int i915_batchbuffer_info(struct seq_file *m, void *data)
580{
581 struct drm_info_node *node = (struct drm_info_node *) m->private;
582 struct drm_device *dev = node->minor->dev;
583 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 584 struct drm_i915_gem_object *obj;
6911a9b8
BG
585 int ret;
586
de227ef0
CW
587 ret = mutex_lock_interruptible(&dev->struct_mutex);
588 if (ret)
589 return ret;
6911a9b8 590
05394f39
CW
591 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
592 if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) {
593 seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
594 i915_dump_object(m, dev_priv->mm.gtt_mapping, obj);
6911a9b8
BG
595 }
596 }
597
de227ef0 598 mutex_unlock(&dev->struct_mutex);
6911a9b8
BG
599 return 0;
600}
601
602static int i915_ringbuffer_data(struct seq_file *m, void *data)
603{
604 struct drm_info_node *node = (struct drm_info_node *) m->private;
605 struct drm_device *dev = node->minor->dev;
606 drm_i915_private_t *dev_priv = dev->dev_private;
c2c347a9 607 struct intel_ring_buffer *ring;
de227ef0
CW
608 int ret;
609
610 ret = mutex_lock_interruptible(&dev->struct_mutex);
611 if (ret)
612 return ret;
6911a9b8 613
1ec14ad3 614 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
05394f39 615 if (!ring->obj) {
6911a9b8 616 seq_printf(m, "No ringbuffer setup\n");
de227ef0 617 } else {
c2c347a9 618 u8 *virt = ring->virtual_start;
de227ef0 619 uint32_t off;
6911a9b8 620
c2c347a9 621 for (off = 0; off < ring->size; off += 4) {
de227ef0
CW
622 uint32_t *ptr = (uint32_t *)(virt + off);
623 seq_printf(m, "%08x : %08x\n", off, *ptr);
624 }
6911a9b8 625 }
de227ef0 626 mutex_unlock(&dev->struct_mutex);
6911a9b8
BG
627
628 return 0;
629}
630
631static int i915_ringbuffer_info(struct seq_file *m, void *data)
632{
633 struct drm_info_node *node = (struct drm_info_node *) m->private;
634 struct drm_device *dev = node->minor->dev;
635 drm_i915_private_t *dev_priv = dev->dev_private;
c2c347a9
CW
636 struct intel_ring_buffer *ring;
637
1ec14ad3 638 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
c2c347a9 639 if (ring->size == 0)
1ec14ad3 640 return 0;
6911a9b8 641
c2c347a9
CW
642 seq_printf(m, "Ring %s:\n", ring->name);
643 seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
644 seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
645 seq_printf(m, " Size : %08x\n", ring->size);
646 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
1ec14ad3
CW
647 seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
648 if (IS_GEN6(dev)) {
649 seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
650 seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
651 }
c2c347a9
CW
652 seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
653 seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
6911a9b8
BG
654
655 return 0;
656}
657
e5c65260
CW
658static const char *ring_str(int ring)
659{
660 switch (ring) {
3685092b
CW
661 case RING_RENDER: return " render";
662 case RING_BSD: return " bsd";
663 case RING_BLT: return " blt";
e5c65260
CW
664 default: return "";
665 }
666}
667
9df30794
CW
668static const char *pin_flag(int pinned)
669{
670 if (pinned > 0)
671 return " P";
672 else if (pinned < 0)
673 return " p";
674 else
675 return "";
676}
677
678static const char *tiling_flag(int tiling)
679{
680 switch (tiling) {
681 default:
682 case I915_TILING_NONE: return "";
683 case I915_TILING_X: return " X";
684 case I915_TILING_Y: return " Y";
685 }
686}
687
688static const char *dirty_flag(int dirty)
689{
690 return dirty ? " dirty" : "";
691}
692
693static const char *purgeable_flag(int purgeable)
694{
695 return purgeable ? " purgeable" : "";
696}
697
c724e8a9
CW
698static void print_error_buffers(struct seq_file *m,
699 const char *name,
700 struct drm_i915_error_buffer *err,
701 int count)
702{
703 seq_printf(m, "%s [%d]:\n", name, count);
704
705 while (count--) {
833bcb00 706 seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s",
c724e8a9
CW
707 err->gtt_offset,
708 err->size,
709 err->read_domains,
710 err->write_domain,
711 err->seqno,
712 pin_flag(err->pinned),
713 tiling_flag(err->tiling),
714 dirty_flag(err->dirty),
715 purgeable_flag(err->purgeable),
a779e5ab
CW
716 ring_str(err->ring),
717 agp_type_str(err->agp_type));
c724e8a9
CW
718
719 if (err->name)
720 seq_printf(m, " (name: %d)", err->name);
721 if (err->fence_reg != I915_FENCE_REG_NONE)
722 seq_printf(m, " (fence: %d)", err->fence_reg);
723
724 seq_printf(m, "\n");
725 err++;
726 }
727}
728
63eeaf38
JB
729static int i915_error_state(struct seq_file *m, void *unused)
730{
731 struct drm_info_node *node = (struct drm_info_node *) m->private;
732 struct drm_device *dev = node->minor->dev;
733 drm_i915_private_t *dev_priv = dev->dev_private;
734 struct drm_i915_error_state *error;
735 unsigned long flags;
9df30794 736 int i, page, offset, elt;
63eeaf38
JB
737
738 spin_lock_irqsave(&dev_priv->error_lock, flags);
739 if (!dev_priv->first_error) {
740 seq_printf(m, "no error state collected\n");
741 goto out;
742 }
743
744 error = dev_priv->first_error;
745
8a905236
JB
746 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
747 error->time.tv_usec);
9df30794 748 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
1d8f38f4
CW
749 seq_printf(m, "EIR: 0x%08x\n", error->eir);
750 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
f406839f
CW
751 if (INTEL_INFO(dev)->gen >= 6) {
752 seq_printf(m, "ERROR: 0x%08x\n", error->error);
1d8f38f4
CW
753 seq_printf(m, "Blitter command stream:\n");
754 seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
1d8f38f4 755 seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
e5c65260 756 seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
1d8f38f4
CW
757 seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
758 seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
add354dd
CW
759 seq_printf(m, "Video (BSD) command stream:\n");
760 seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
add354dd 761 seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
e5c65260 762 seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
add354dd
CW
763 seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
764 seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
f406839f 765 }
1d8f38f4
CW
766 seq_printf(m, "Render command stream:\n");
767 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
63eeaf38
JB
768 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
769 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
770 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
a6c45cf0 771 if (INTEL_INFO(dev)->gen >= 4) {
63eeaf38 772 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
1d8f38f4 773 seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
63eeaf38 774 }
1d8f38f4
CW
775 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
776 seq_printf(m, " seqno: 0x%08x\n", error->seqno);
9df30794 777
748ebc60
CW
778 for (i = 0; i < 16; i++)
779 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
780
c724e8a9
CW
781 if (error->active_bo)
782 print_error_buffers(m, "Active",
783 error->active_bo,
784 error->active_bo_count);
785
786 if (error->pinned_bo)
787 print_error_buffers(m, "Pinned",
788 error->pinned_bo,
789 error->pinned_bo_count);
9df30794
CW
790
791 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
792 if (error->batchbuffer[i]) {
793 struct drm_i915_error_object *obj = error->batchbuffer[i];
794
bcfb2e28
CW
795 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
796 dev_priv->ring[i].name,
797 obj->gtt_offset);
9df30794
CW
798 offset = 0;
799 for (page = 0; page < obj->page_count; page++) {
800 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
801 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
802 offset += 4;
803 }
804 }
805 }
806 }
807
808 if (error->ringbuffer) {
809 struct drm_i915_error_object *obj = error->ringbuffer;
810
811 seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset);
812 offset = 0;
813 for (page = 0; page < obj->page_count; page++) {
814 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
815 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
816 offset += 4;
817 }
818 }
819 }
63eeaf38 820
6ef3d427
CW
821 if (error->overlay)
822 intel_overlay_print_error_state(m, error->overlay);
823
c4a1d9e4
CW
824 if (error->display)
825 intel_display_print_error_state(m, dev, error->display);
826
63eeaf38
JB
827out:
828 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
829
830 return 0;
831}
6911a9b8 832
f97108d1
JB
833static int i915_rstdby_delays(struct seq_file *m, void *unused)
834{
835 struct drm_info_node *node = (struct drm_info_node *) m->private;
836 struct drm_device *dev = node->minor->dev;
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 u16 crstanddelay = I915_READ16(CRSTANDVID);
839
840 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
841
842 return 0;
843}
844
845static int i915_cur_delayinfo(struct seq_file *m, void *unused)
846{
847 struct drm_info_node *node = (struct drm_info_node *) m->private;
848 struct drm_device *dev = node->minor->dev;
849 drm_i915_private_t *dev_priv = dev->dev_private;
3b8d8d91
JB
850
851 if (IS_GEN5(dev)) {
852 u16 rgvswctl = I915_READ16(MEMSWCTL);
853 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
854
855 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
856 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
857 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
858 MEMSTAT_VID_SHIFT);
859 seq_printf(m, "Current P-state: %d\n",
860 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
861 } else if (IS_GEN6(dev)) {
862 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
863 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
864 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
865 int max_freq;
866
867 /* RPSTAT1 is in the GT power well */
868 __gen6_force_wake_get(dev_priv);
869
870 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
871 seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1));
872 seq_printf(m, "Render p-state ratio: %d\n",
873 (gt_perf_status & 0xff00) >> 8);
874 seq_printf(m, "Render p-state VID: %d\n",
875 gt_perf_status & 0xff);
876 seq_printf(m, "Render p-state limit: %d\n",
877 rp_state_limits & 0xff);
878
879 max_freq = (rp_state_cap & 0xff0000) >> 16;
880 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
881 max_freq * 100);
882
883 max_freq = (rp_state_cap & 0xff00) >> 8;
884 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
885 max_freq * 100);
886
887 max_freq = rp_state_cap & 0xff;
888 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
889 max_freq * 100);
890
891 __gen6_force_wake_put(dev_priv);
892 } else {
893 seq_printf(m, "no P-state info available\n");
894 }
f97108d1
JB
895
896 return 0;
897}
898
899static int i915_delayfreq_table(struct seq_file *m, void *unused)
900{
901 struct drm_info_node *node = (struct drm_info_node *) m->private;
902 struct drm_device *dev = node->minor->dev;
903 drm_i915_private_t *dev_priv = dev->dev_private;
904 u32 delayfreq;
905 int i;
906
907 for (i = 0; i < 16; i++) {
908 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB
909 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
910 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB
911 }
912
913 return 0;
914}
915
916static inline int MAP_TO_MV(int map)
917{
918 return 1250 - (map * 25);
919}
920
921static int i915_inttoext_table(struct seq_file *m, void *unused)
922{
923 struct drm_info_node *node = (struct drm_info_node *) m->private;
924 struct drm_device *dev = node->minor->dev;
925 drm_i915_private_t *dev_priv = dev->dev_private;
926 u32 inttoext;
927 int i;
928
929 for (i = 1; i <= 32; i++) {
930 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
931 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
932 }
933
934 return 0;
935}
936
937static int i915_drpc_info(struct seq_file *m, void *unused)
938{
939 struct drm_info_node *node = (struct drm_info_node *) m->private;
940 struct drm_device *dev = node->minor->dev;
941 drm_i915_private_t *dev_priv = dev->dev_private;
942 u32 rgvmodectl = I915_READ(MEMMODECTL);
88271da3 943 u32 rstdbyctl = I915_READ(RSTDBYCTL);
7648fa99 944 u16 crstandvid = I915_READ16(CRSTANDVID);
f97108d1
JB
945
946 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
947 "yes" : "no");
948 seq_printf(m, "Boost freq: %d\n",
949 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
950 MEMMODE_BOOST_FREQ_SHIFT);
951 seq_printf(m, "HW control enabled: %s\n",
952 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
953 seq_printf(m, "SW control enabled: %s\n",
954 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
955 seq_printf(m, "Gated voltage change: %s\n",
956 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
957 seq_printf(m, "Starting frequency: P%d\n",
958 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 959 seq_printf(m, "Max P-state: P%d\n",
f97108d1 960 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB
961 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
962 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
963 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
964 seq_printf(m, "Render standby enabled: %s\n",
965 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
88271da3
JB
966 seq_printf(m, "Current RS state: ");
967 switch (rstdbyctl & RSX_STATUS_MASK) {
968 case RSX_STATUS_ON:
969 seq_printf(m, "on\n");
970 break;
971 case RSX_STATUS_RC1:
972 seq_printf(m, "RC1\n");
973 break;
974 case RSX_STATUS_RC1E:
975 seq_printf(m, "RC1E\n");
976 break;
977 case RSX_STATUS_RS1:
978 seq_printf(m, "RS1\n");
979 break;
980 case RSX_STATUS_RS2:
981 seq_printf(m, "RS2 (RC6)\n");
982 break;
983 case RSX_STATUS_RS3:
984 seq_printf(m, "RC3 (RC6+)\n");
985 break;
986 default:
987 seq_printf(m, "unknown\n");
988 break;
989 }
f97108d1
JB
990
991 return 0;
992}
993
b5e50c3f
JB
994static int i915_fbc_status(struct seq_file *m, void *unused)
995{
996 struct drm_info_node *node = (struct drm_info_node *) m->private;
997 struct drm_device *dev = node->minor->dev;
b5e50c3f 998 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 999
ee5382ae 1000 if (!I915_HAS_FBC(dev)) {
b5e50c3f
JB
1001 seq_printf(m, "FBC unsupported on this chipset\n");
1002 return 0;
1003 }
1004
ee5382ae 1005 if (intel_fbc_enabled(dev)) {
b5e50c3f
JB
1006 seq_printf(m, "FBC enabled\n");
1007 } else {
1008 seq_printf(m, "FBC disabled: ");
1009 switch (dev_priv->no_fbc_reason) {
bed4a673
CW
1010 case FBC_NO_OUTPUT:
1011 seq_printf(m, "no outputs");
1012 break;
b5e50c3f
JB
1013 case FBC_STOLEN_TOO_SMALL:
1014 seq_printf(m, "not enough stolen memory");
1015 break;
1016 case FBC_UNSUPPORTED_MODE:
1017 seq_printf(m, "mode not supported");
1018 break;
1019 case FBC_MODE_TOO_LARGE:
1020 seq_printf(m, "mode too large");
1021 break;
1022 case FBC_BAD_PLANE:
1023 seq_printf(m, "FBC unsupported on plane");
1024 break;
1025 case FBC_NOT_TILED:
1026 seq_printf(m, "scanout buffer not tiled");
1027 break;
9c928d16
JB
1028 case FBC_MULTIPLE_PIPES:
1029 seq_printf(m, "multiple pipes are enabled");
1030 break;
b5e50c3f
JB
1031 default:
1032 seq_printf(m, "unknown reason");
1033 }
1034 seq_printf(m, "\n");
1035 }
1036 return 0;
1037}
1038
4a9bef37
JB
1039static int i915_sr_status(struct seq_file *m, void *unused)
1040{
1041 struct drm_info_node *node = (struct drm_info_node *) m->private;
1042 struct drm_device *dev = node->minor->dev;
1043 drm_i915_private_t *dev_priv = dev->dev_private;
1044 bool sr_enabled = false;
1045
1398261a 1046 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1047 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1048 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB
1049 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1050 else if (IS_I915GM(dev))
1051 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1052 else if (IS_PINEVIEW(dev))
1053 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1054
5ba2aaaa
CW
1055 seq_printf(m, "self-refresh: %s\n",
1056 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB
1057
1058 return 0;
1059}
1060
7648fa99
JB
1061static int i915_emon_status(struct seq_file *m, void *unused)
1062{
1063 struct drm_info_node *node = (struct drm_info_node *) m->private;
1064 struct drm_device *dev = node->minor->dev;
1065 drm_i915_private_t *dev_priv = dev->dev_private;
1066 unsigned long temp, chipset, gfx;
de227ef0
CW
1067 int ret;
1068
1069 ret = mutex_lock_interruptible(&dev->struct_mutex);
1070 if (ret)
1071 return ret;
7648fa99
JB
1072
1073 temp = i915_mch_val(dev_priv);
1074 chipset = i915_chipset_val(dev_priv);
1075 gfx = i915_gfx_val(dev_priv);
de227ef0 1076 mutex_unlock(&dev->struct_mutex);
7648fa99
JB
1077
1078 seq_printf(m, "GMCH temp: %ld\n", temp);
1079 seq_printf(m, "Chipset power: %ld\n", chipset);
1080 seq_printf(m, "GFX power: %ld\n", gfx);
1081 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1082
1083 return 0;
1084}
1085
1086static int i915_gfxec(struct seq_file *m, void *unused)
1087{
1088 struct drm_info_node *node = (struct drm_info_node *) m->private;
1089 struct drm_device *dev = node->minor->dev;
1090 drm_i915_private_t *dev_priv = dev->dev_private;
1091
1092 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1093
1094 return 0;
1095}
1096
44834a67
CW
1097static int i915_opregion(struct seq_file *m, void *unused)
1098{
1099 struct drm_info_node *node = (struct drm_info_node *) m->private;
1100 struct drm_device *dev = node->minor->dev;
1101 drm_i915_private_t *dev_priv = dev->dev_private;
1102 struct intel_opregion *opregion = &dev_priv->opregion;
1103 int ret;
1104
1105 ret = mutex_lock_interruptible(&dev->struct_mutex);
1106 if (ret)
1107 return ret;
1108
1109 if (opregion->header)
1110 seq_write(m, opregion->header, OPREGION_SIZE);
1111
1112 mutex_unlock(&dev->struct_mutex);
1113
1114 return 0;
1115}
1116
37811fcc
CW
1117static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1118{
1119 struct drm_info_node *node = (struct drm_info_node *) m->private;
1120 struct drm_device *dev = node->minor->dev;
1121 drm_i915_private_t *dev_priv = dev->dev_private;
1122 struct intel_fbdev *ifbdev;
1123 struct intel_framebuffer *fb;
1124 int ret;
1125
1126 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1127 if (ret)
1128 return ret;
1129
1130 ifbdev = dev_priv->fbdev;
1131 fb = to_intel_framebuffer(ifbdev->helper.fb);
1132
1133 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1134 fb->base.width,
1135 fb->base.height,
1136 fb->base.depth,
1137 fb->base.bits_per_pixel);
05394f39 1138 describe_obj(m, fb->obj);
37811fcc
CW
1139 seq_printf(m, "\n");
1140
1141 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1142 if (&fb->base == ifbdev->helper.fb)
1143 continue;
1144
1145 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1146 fb->base.width,
1147 fb->base.height,
1148 fb->base.depth,
1149 fb->base.bits_per_pixel);
05394f39 1150 describe_obj(m, fb->obj);
37811fcc
CW
1151 seq_printf(m, "\n");
1152 }
1153
1154 mutex_unlock(&dev->mode_config.mutex);
1155
1156 return 0;
1157}
1158
f3cd474b
CW
1159static int
1160i915_wedged_open(struct inode *inode,
1161 struct file *filp)
1162{
1163 filp->private_data = inode->i_private;
1164 return 0;
1165}
1166
1167static ssize_t
1168i915_wedged_read(struct file *filp,
1169 char __user *ubuf,
1170 size_t max,
1171 loff_t *ppos)
1172{
1173 struct drm_device *dev = filp->private_data;
1174 drm_i915_private_t *dev_priv = dev->dev_private;
1175 char buf[80];
1176 int len;
1177
1178 len = snprintf(buf, sizeof (buf),
1179 "wedged : %d\n",
1180 atomic_read(&dev_priv->mm.wedged));
1181
f4433a8d
DC
1182 if (len > sizeof (buf))
1183 len = sizeof (buf);
1184
f3cd474b
CW
1185 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1186}
1187
1188static ssize_t
1189i915_wedged_write(struct file *filp,
1190 const char __user *ubuf,
1191 size_t cnt,
1192 loff_t *ppos)
1193{
1194 struct drm_device *dev = filp->private_data;
f3cd474b
CW
1195 char buf[20];
1196 int val = 1;
1197
1198 if (cnt > 0) {
1199 if (cnt > sizeof (buf) - 1)
1200 return -EINVAL;
1201
1202 if (copy_from_user(buf, ubuf, cnt))
1203 return -EFAULT;
1204 buf[cnt] = 0;
1205
1206 val = simple_strtoul(buf, NULL, 0);
1207 }
1208
1209 DRM_INFO("Manually setting wedged to %d\n", val);
527f9e90 1210 i915_handle_error(dev, val);
f3cd474b
CW
1211
1212 return cnt;
1213}
1214
1215static const struct file_operations i915_wedged_fops = {
1216 .owner = THIS_MODULE,
1217 .open = i915_wedged_open,
1218 .read = i915_wedged_read,
1219 .write = i915_wedged_write,
6038f373 1220 .llseek = default_llseek,
f3cd474b
CW
1221};
1222
1223/* As the drm_debugfs_init() routines are called before dev->dev_private is
1224 * allocated we need to hook into the minor for release. */
1225static int
1226drm_add_fake_info_node(struct drm_minor *minor,
1227 struct dentry *ent,
1228 const void *key)
1229{
1230 struct drm_info_node *node;
1231
1232 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1233 if (node == NULL) {
1234 debugfs_remove(ent);
1235 return -ENOMEM;
1236 }
1237
1238 node->minor = minor;
1239 node->dent = ent;
1240 node->info_ent = (void *) key;
1241 list_add(&node->list, &minor->debugfs_nodes.list);
1242
1243 return 0;
1244}
1245
1246static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
1247{
1248 struct drm_device *dev = minor->dev;
1249 struct dentry *ent;
1250
1251 ent = debugfs_create_file("i915_wedged",
1252 S_IRUGO | S_IWUSR,
1253 root, dev,
1254 &i915_wedged_fops);
1255 if (IS_ERR(ent))
1256 return PTR_ERR(ent);
1257
1258 return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
1259}
9e3a6d15 1260
27c202ad 1261static struct drm_info_list i915_debugfs_list[] = {
70d39fe4 1262 {"i915_capabilities", i915_capabilities, 0, 0},
73aa808f 1263 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 1264 {"i915_gem_gtt", i915_gem_gtt_info, 0},
433e12f7
BG
1265 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
1266 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
1267 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
f13d3f73 1268 {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
d21d5975 1269 {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
4e5359cd 1270 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG
1271 {"i915_gem_request", i915_gem_request_info, 0},
1272 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 1273 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 1274 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW
1275 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1276 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1277 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1278 {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
1279 {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
1280 {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
1281 {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
1282 {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
1283 {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
6911a9b8 1284 {"i915_batchbuffers", i915_batchbuffer_info, 0},
63eeaf38 1285 {"i915_error_state", i915_error_state, 0},
f97108d1
JB
1286 {"i915_rstdby_delays", i915_rstdby_delays, 0},
1287 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1288 {"i915_delayfreq_table", i915_delayfreq_table, 0},
1289 {"i915_inttoext_table", i915_inttoext_table, 0},
1290 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99
JB
1291 {"i915_emon_status", i915_emon_status, 0},
1292 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 1293 {"i915_fbc_status", i915_fbc_status, 0},
4a9bef37 1294 {"i915_sr_status", i915_sr_status, 0},
44834a67 1295 {"i915_opregion", i915_opregion, 0},
37811fcc 1296 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2017263e 1297};
27c202ad 1298#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 1299
27c202ad 1300int i915_debugfs_init(struct drm_minor *minor)
2017263e 1301{
f3cd474b
CW
1302 int ret;
1303
1304 ret = i915_wedged_create(minor->debugfs_root, minor);
1305 if (ret)
1306 return ret;
1307
27c202ad
BG
1308 return drm_debugfs_create_files(i915_debugfs_list,
1309 I915_DEBUGFS_ENTRIES,
2017263e
BG
1310 minor->debugfs_root, minor);
1311}
1312
27c202ad 1313void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 1314{
27c202ad
BG
1315 drm_debugfs_remove_files(i915_debugfs_list,
1316 I915_DEBUGFS_ENTRIES, minor);
33db679b
KH
1317 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1318 1, minor);
2017263e
BG
1319}
1320
1321#endif /* CONFIG_DEBUG_FS */