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drm/i915: Make the ring IMR handling private
[linux-2.6-block.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
f3cd474b 30#include <linux/debugfs.h>
5a0e3ad6 31#include <linux/slab.h>
2017263e
BG		 32#include "drmP.h"
33#include "drm.h"
4e5359cd 34#include "intel_drv.h"
e5c65260 35#include "intel_ringbuffer.h"
2017263e
BG		 36#include "i915_drm.h"
37#include "i915_drv.h"
38
39#define DRM_I915_RING_DEBUG 1
40
41
42#if defined(CONFIG_DEBUG_FS)
43
f13d3f73 44enum {
69dc4987 45 ACTIVE_LIST,
f13d3f73
CW		 46 FLUSHING_LIST,
47 INACTIVE_LIST,
d21d5975
CW		 48 PINNED_LIST,
49 DEFERRED_FREE_LIST,
f13d3f73 50};
2017263e 51
70d39fe4
CW		 52static const char *yesno(int v)
53{
54 return v ? "yes" : "no";
55}
56
57static int i915_capabilities(struct seq_file *m, void *data)
58{
59 struct drm_info_node *node = (struct drm_info_node *) m->private;
60 struct drm_device *dev = node->minor->dev;
61 const struct intel_device_info *info = INTEL_INFO(dev);
62
63 seq_printf(m, "gen: %d\n", info->gen);
64#define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65 B(is_mobile);
70d39fe4
CW		 66 B(is_i85x);
67 B(is_i915g);
70d39fe4 68 B(is_i945gm);
70d39fe4
CW		 69 B(is_g33);
70 B(need_gfx_hws);
71 B(is_g4x);
72 B(is_pineview);
73 B(is_broadwater);
74 B(is_crestline);
70d39fe4 75 B(has_fbc);
70d39fe4
CW		 76 B(has_pipe_cxsr);
77 B(has_hotplug);
78 B(cursor_needs_physical);
79 B(has_overlay);
80 B(overlay_needs_physical);
a6c45cf0 81 B(supports_tv);
549f7365
CW		 82 B(has_bsd_ring);
83 B(has_blt_ring);
70d39fe4
CW		 84#undef B
85
86 return 0;
87}
2017263e 88
05394f39 89static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 90{
05394f39 91 if (obj->user_pin_count > 0)
a6172a80 92 return "P";
05394f39 93 else if (obj->pin_count > 0)
a6172a80
CW		 94 return "p";
95 else
96 return " ";
97}
98
05394f39 99static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 100{
05394f39 101 switch (obj->tiling_mode) {
a6172a80
CW		 102 default:
103 case I915_TILING_NONE: return " ";
104 case I915_TILING_X: return "X";
105 case I915_TILING_Y: return "Y";
106 }
107}
108
37811fcc
CW		 109static void
110describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
111{
caea7476 112 seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s",
37811fcc
CW		 113 &obj->base,
114 get_pin_flag(obj),
115 get_tiling_flag(obj),
116 obj->base.size,
117 obj->base.read_domains,
118 obj->base.write_domain,
119 obj->last_rendering_seqno,
caea7476 120 obj->last_fenced_seqno,
37811fcc
CW		 121 obj->dirty ? " dirty" : "",
122 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
123 if (obj->base.name)
124 seq_printf(m, " (name: %d)", obj->base.name);
125 if (obj->fence_reg != I915_FENCE_REG_NONE)
126 seq_printf(m, " (fence: %d)", obj->fence_reg);
127 if (obj->gtt_space != NULL)
a00b10c3
CW		 128 seq_printf(m, " (gtt offset: %08x, size: %08x)",
129 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
6299f992
CW		 130 if (obj->pin_mappable || obj->fault_mappable) {
131 char s[3], *t = s;
132 if (obj->pin_mappable)
133 *t++ = 'p';
134 if (obj->fault_mappable)
135 *t++ = 'f';
136 *t = '\0';
137 seq_printf(m, " (%s mappable)", s);
138 }
69dc4987
CW		 139 if (obj->ring != NULL)
140 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 141}
142
433e12f7 143static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 144{
145 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 146 uintptr_t list = (uintptr_t) node->info_ent->data;
147 struct list_head *head;
2017263e
BG		 148 struct drm_device *dev = node->minor->dev;
149 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 150 struct drm_i915_gem_object *obj;
8f2480fb
CW		 151 size_t total_obj_size, total_gtt_size;
152 int count, ret;
de227ef0
CW		 153
154 ret = mutex_lock_interruptible(&dev->struct_mutex);
155 if (ret)
156 return ret;
2017263e 157
433e12f7
BG		 158 switch (list) {
159 case ACTIVE_LIST:
160 seq_printf(m, "Active:\n");
69dc4987 161 head = &dev_priv->mm.active_list;
433e12f7
BG		 162 break;
163 case INACTIVE_LIST:
a17458fc 164 seq_printf(m, "Inactive:\n");
433e12f7
BG		 165 head = &dev_priv->mm.inactive_list;
166 break;
f13d3f73
CW		 167 case PINNED_LIST:
168 seq_printf(m, "Pinned:\n");
169 head = &dev_priv->mm.pinned_list;
170 break;
433e12f7
BG		 171 case FLUSHING_LIST:
172 seq_printf(m, "Flushing:\n");
173 head = &dev_priv->mm.flushing_list;
174 break;
d21d5975
CW		 175 case DEFERRED_FREE_LIST:
176 seq_printf(m, "Deferred free:\n");
177 head = &dev_priv->mm.deferred_free_list;
178 break;
433e12f7 179 default:
de227ef0
CW		 180 mutex_unlock(&dev->struct_mutex);
181 return -EINVAL;
2017263e 182 }
2017263e 183
8f2480fb 184 total_obj_size = total_gtt_size = count = 0;
05394f39 185 list_for_each_entry(obj, head, mm_list) {
37811fcc 186 seq_printf(m, " ");
05394f39 187 describe_obj(m, obj);
f4ceda89 188 seq_printf(m, "\n");
05394f39
CW		 189 total_obj_size += obj->base.size;
190 total_gtt_size += obj->gtt_space->size;
8f2480fb 191 count++;
2017263e 192 }
de227ef0 193 mutex_unlock(&dev->struct_mutex);
5e118f41 194
8f2480fb
CW		 195 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
196 count, total_obj_size, total_gtt_size);
2017263e
BG		 197 return 0;
198}
199
6299f992
CW		 200#define count_objects(list, member) do { \
201 list_for_each_entry(obj, list, member) { \
202 size += obj->gtt_space->size; \
203 ++count; \
204 if (obj->map_and_fenceable) { \
205 mappable_size += obj->gtt_space->size; \
206 ++mappable_count; \
207 } \
208 } \
209} while(0)
210
73aa808f
CW		 211static int i915_gem_object_info(struct seq_file *m, void* data)
212{
213 struct drm_info_node *node = (struct drm_info_node *) m->private;
214 struct drm_device *dev = node->minor->dev;
215 struct drm_i915_private *dev_priv = dev->dev_private;
6299f992
CW		 216 u32 count, mappable_count;
217 size_t size, mappable_size;
218 struct drm_i915_gem_object *obj;
73aa808f
CW		 219 int ret;
220
221 ret = mutex_lock_interruptible(&dev->struct_mutex);
222 if (ret)
223 return ret;
224
6299f992
CW		 225 seq_printf(m, "%u objects, %zu bytes\n",
226 dev_priv->mm.object_count,
227 dev_priv->mm.object_memory);
228
229 size = count = mappable_size = mappable_count = 0;
230 count_objects(&dev_priv->mm.gtt_list, gtt_list);
231 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
232 count, mappable_count, size, mappable_size);
233
234 size = count = mappable_size = mappable_count = 0;
235 count_objects(&dev_priv->mm.active_list, mm_list);
236 count_objects(&dev_priv->mm.flushing_list, mm_list);
237 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
238 count, mappable_count, size, mappable_size);
239
240 size = count = mappable_size = mappable_count = 0;
241 count_objects(&dev_priv->mm.pinned_list, mm_list);
242 seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
243 count, mappable_count, size, mappable_size);
244
245 size = count = mappable_size = mappable_count = 0;
246 count_objects(&dev_priv->mm.inactive_list, mm_list);
247 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
248 count, mappable_count, size, mappable_size);
249
250 size = count = mappable_size = mappable_count = 0;
251 count_objects(&dev_priv->mm.deferred_free_list, mm_list);
252 seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
253 count, mappable_count, size, mappable_size);
254
255 size = count = mappable_size = mappable_count = 0;
256 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
257 if (obj->fault_mappable) {
258 size += obj->gtt_space->size;
259 ++count;
260 }
261 if (obj->pin_mappable) {
262 mappable_size += obj->gtt_space->size;
263 ++mappable_count;
264 }
265 }
266 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
267 mappable_count, mappable_size);
268 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
269 count, size);
270
271 seq_printf(m, "%zu [%zu] gtt total\n",
272 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
73aa808f
CW		 273
274 mutex_unlock(&dev->struct_mutex);
275
276 return 0;
277}
278
279
4e5359cd
SF		 280static int i915_gem_pageflip_info(struct seq_file *m, void *data)
281{
282 struct drm_info_node *node = (struct drm_info_node *) m->private;
283 struct drm_device *dev = node->minor->dev;
284 unsigned long flags;
285 struct intel_crtc *crtc;
286
287 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
288 const char *pipe = crtc->pipe ? "B" : "A";
289 const char *plane = crtc->plane ? "B" : "A";
290 struct intel_unpin_work *work;
291
292 spin_lock_irqsave(&dev->event_lock, flags);
293 work = crtc->unpin_work;
294 if (work == NULL) {
295 seq_printf(m, "No flip due on pipe %s (plane %s)\n",
296 pipe, plane);
297 } else {
298 if (!work->pending) {
299 seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
300 pipe, plane);
301 } else {
302 seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
303 pipe, plane);
304 }
305 if (work->enable_stall_check)
306 seq_printf(m, "Stall check enabled, ");
307 else
308 seq_printf(m, "Stall check waiting for page flip ioctl, ");
309 seq_printf(m, "%d prepares\n", work->pending);
310
311 if (work->old_fb_obj) {
05394f39
CW		 312 struct drm_i915_gem_object *obj = work->old_fb_obj;
313 if (obj)
314 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 315 }
316 if (work->pending_flip_obj) {
05394f39
CW		 317 struct drm_i915_gem_object *obj = work->pending_flip_obj;
318 if (obj)
319 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 320 }
321 }
322 spin_unlock_irqrestore(&dev->event_lock, flags);
323 }
324
325 return 0;
326}
327
2017263e
BG		 328static int i915_gem_request_info(struct seq_file *m, void *data)
329{
330 struct drm_info_node *node = (struct drm_info_node *) m->private;
331 struct drm_device *dev = node->minor->dev;
332 drm_i915_private_t *dev_priv = dev->dev_private;
333 struct drm_i915_gem_request *gem_request;
c2c347a9 334 int ret, count;
de227ef0
CW		 335
336 ret = mutex_lock_interruptible(&dev->struct_mutex);
337 if (ret)
338 return ret;
2017263e 339
c2c347a9 340 count = 0;
1ec14ad3 341 if (!list_empty(&dev_priv->ring[RCS].request_list)) {
c2c347a9
CW		 342 seq_printf(m, "Render requests:\n");
343 list_for_each_entry(gem_request,
1ec14ad3 344 &dev_priv->ring[RCS].request_list,
c2c347a9
CW		 345 list) {
346 seq_printf(m, " %d @ %d\n",
347 gem_request->seqno,
348 (int) (jiffies - gem_request->emitted_jiffies));
349 }
350 count++;
351 }
1ec14ad3 352 if (!list_empty(&dev_priv->ring[VCS].request_list)) {
c2c347a9
CW		 353 seq_printf(m, "BSD requests:\n");
354 list_for_each_entry(gem_request,
1ec14ad3 355 &dev_priv->ring[VCS].request_list,
c2c347a9
CW		 356 list) {
357 seq_printf(m, " %d @ %d\n",
358 gem_request->seqno,
359 (int) (jiffies - gem_request->emitted_jiffies));
360 }
361 count++;
362 }
1ec14ad3 363 if (!list_empty(&dev_priv->ring[BCS].request_list)) {
c2c347a9
CW		 364 seq_printf(m, "BLT requests:\n");
365 list_for_each_entry(gem_request,
1ec14ad3 366 &dev_priv->ring[BCS].request_list,
c2c347a9
CW		 367 list) {
368 seq_printf(m, " %d @ %d\n",
369 gem_request->seqno,
370 (int) (jiffies - gem_request->emitted_jiffies));
371 }
372 count++;
2017263e 373 }
de227ef0
CW		 374 mutex_unlock(&dev->struct_mutex);
375
c2c347a9
CW		 376 if (count == 0)
377 seq_printf(m, "No requests\n");
378
2017263e
BG		 379 return 0;
380}
381
b2223497
CW		 382static void i915_ring_seqno_info(struct seq_file *m,
383 struct intel_ring_buffer *ring)
384{
385 if (ring->get_seqno) {
386 seq_printf(m, "Current sequence (%s): %d\n",
387 ring->name, ring->get_seqno(ring));
388 seq_printf(m, "Waiter sequence (%s): %d\n",
389 ring->name, ring->waiting_seqno);
390 seq_printf(m, "IRQ sequence (%s): %d\n",
391 ring->name, ring->irq_seqno);
392 }
393}
394
2017263e
BG		 395static int i915_gem_seqno_info(struct seq_file *m, void *data)
396{
397 struct drm_info_node *node = (struct drm_info_node *) m->private;
398 struct drm_device *dev = node->minor->dev;
399 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 400 int ret, i;
de227ef0
CW		 401
402 ret = mutex_lock_interruptible(&dev->struct_mutex);
403 if (ret)
404 return ret;
2017263e 405
1ec14ad3
CW		 406 for (i = 0; i < I915_NUM_RINGS; i++)
407 i915_ring_seqno_info(m, &dev_priv->ring[i]);
de227ef0
CW		 408
409 mutex_unlock(&dev->struct_mutex);
410
2017263e
BG		 411 return 0;
412}
413
414
415static int i915_interrupt_info(struct seq_file *m, void *data)
416{
417 struct drm_info_node *node = (struct drm_info_node *) m->private;
418 struct drm_device *dev = node->minor->dev;
419 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 420 int ret, i;
de227ef0
CW		 421
422 ret = mutex_lock_interruptible(&dev->struct_mutex);
423 if (ret)
424 return ret;
2017263e 425
bad720ff 426 if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 427 seq_printf(m, "Interrupt enable: %08x\n",
428 I915_READ(IER));
429 seq_printf(m, "Interrupt identity: %08x\n",
430 I915_READ(IIR));
431 seq_printf(m, "Interrupt mask: %08x\n",
432 I915_READ(IMR));
433 seq_printf(m, "Pipe A stat: %08x\n",
434 I915_READ(PIPEASTAT));
435 seq_printf(m, "Pipe B stat: %08x\n",
436 I915_READ(PIPEBSTAT));
437 } else {
438 seq_printf(m, "North Display Interrupt enable: %08x\n",
439 I915_READ(DEIER));
440 seq_printf(m, "North Display Interrupt identity: %08x\n",
441 I915_READ(DEIIR));
442 seq_printf(m, "North Display Interrupt mask: %08x\n",
443 I915_READ(DEIMR));
444 seq_printf(m, "South Display Interrupt enable: %08x\n",
445 I915_READ(SDEIER));
446 seq_printf(m, "South Display Interrupt identity: %08x\n",
447 I915_READ(SDEIIR));
448 seq_printf(m, "South Display Interrupt mask: %08x\n",
449 I915_READ(SDEIMR));
450 seq_printf(m, "Graphics Interrupt enable: %08x\n",
451 I915_READ(GTIER));
452 seq_printf(m, "Graphics Interrupt identity: %08x\n",
453 I915_READ(GTIIR));
454 seq_printf(m, "Graphics Interrupt mask: %08x\n",
455 I915_READ(GTIMR));
456 }
2017263e
BG		 457 seq_printf(m, "Interrupts received: %d\n",
458 atomic_read(&dev_priv->irq_received));
9862e600
CW		 459 for (i = 0; i < I915_NUM_RINGS; i++) {
460 if (IS_GEN6(dev)) {
461 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
462 dev_priv->ring[i].name,
463 I915_READ_IMR(&dev_priv->ring[i]));
464 }
1ec14ad3 465 i915_ring_seqno_info(m, &dev_priv->ring[i]);
9862e600 466 }
de227ef0
CW		 467 mutex_unlock(&dev->struct_mutex);
468
2017263e
BG		 469 return 0;
470}
471
a6172a80
CW		 472static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
473{
474 struct drm_info_node *node = (struct drm_info_node *) m->private;
475 struct drm_device *dev = node->minor->dev;
476 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 477 int i, ret;
478
479 ret = mutex_lock_interruptible(&dev->struct_mutex);
480 if (ret)
481 return ret;
a6172a80
CW		 482
483 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
484 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
485 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 486 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 487
c2c347a9
CW		 488 seq_printf(m, "Fenced object[%2d] = ", i);
489 if (obj == NULL)
490 seq_printf(m, "unused");
491 else
05394f39 492 describe_obj(m, obj);
c2c347a9 493 seq_printf(m, "\n");
a6172a80
CW		 494 }
495
05394f39 496 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 497 return 0;
498}
499
2017263e
BG		 500static int i915_hws_info(struct seq_file *m, void *data)
501{
502 struct drm_info_node *node = (struct drm_info_node *) m->private;
503 struct drm_device *dev = node->minor->dev;
504 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 505 struct intel_ring_buffer *ring;
2017263e 506 volatile u32 *hws;
4066c0ae
CW		 507 int i;
508
1ec14ad3 509 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
4066c0ae 510 hws = (volatile u32 *)ring->status_page.page_addr;
2017263e
BG		 511 if (hws == NULL)
512 return 0;
513
514 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
515 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
516 i * 4,
517 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
518 }
519 return 0;
520}
521
5cdf5881
CW		 522static void i915_dump_object(struct seq_file *m,
523 struct io_mapping *mapping,
05394f39 524 struct drm_i915_gem_object *obj)
6911a9b8 525{
5cdf5881 526 int page, page_count, i;
6911a9b8 527
05394f39 528 page_count = obj->base.size / PAGE_SIZE;
6911a9b8 529 for (page = 0; page < page_count; page++) {
5cdf5881 530 u32 *mem = io_mapping_map_wc(mapping,
05394f39 531 obj->gtt_offset + page * PAGE_SIZE);
6911a9b8
BG		 532 for (i = 0; i < PAGE_SIZE; i += 4)
533 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
5cdf5881 534 io_mapping_unmap(mem);
6911a9b8
BG		 535 }
536}
537
538static int i915_batchbuffer_info(struct seq_file *m, void *data)
539{
540 struct drm_info_node *node = (struct drm_info_node *) m->private;
541 struct drm_device *dev = node->minor->dev;
542 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 543 struct drm_i915_gem_object *obj;
6911a9b8
BG		 544 int ret;
545
de227ef0
CW		 546 ret = mutex_lock_interruptible(&dev->struct_mutex);
547 if (ret)
548 return ret;
6911a9b8 549
05394f39
CW		 550 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
551 if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) {
552 seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
553 i915_dump_object(m, dev_priv->mm.gtt_mapping, obj);
6911a9b8
BG		 554 }
555 }
556
de227ef0 557 mutex_unlock(&dev->struct_mutex);
6911a9b8
BG		 558 return 0;
559}
560
561static int i915_ringbuffer_data(struct seq_file *m, void *data)
562{
563 struct drm_info_node *node = (struct drm_info_node *) m->private;
564 struct drm_device *dev = node->minor->dev;
565 drm_i915_private_t *dev_priv = dev->dev_private;
c2c347a9 566 struct intel_ring_buffer *ring;
de227ef0
CW		 567 int ret;
568
569 ret = mutex_lock_interruptible(&dev->struct_mutex);
570 if (ret)
571 return ret;
6911a9b8 572
1ec14ad3 573 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
05394f39 574 if (!ring->obj) {
6911a9b8 575 seq_printf(m, "No ringbuffer setup\n");
de227ef0 576 } else {
c2c347a9 577 u8 *virt = ring->virtual_start;
de227ef0 578 uint32_t off;
6911a9b8 579
c2c347a9 580 for (off = 0; off < ring->size; off += 4) {
de227ef0
CW		 581 uint32_t *ptr = (uint32_t *)(virt + off);
582 seq_printf(m, "%08x : %08x\n", off, *ptr);
583 }
6911a9b8 584 }
de227ef0 585 mutex_unlock(&dev->struct_mutex);
6911a9b8
BG		 586
587 return 0;
588}
589
590static int i915_ringbuffer_info(struct seq_file *m, void *data)
591{
592 struct drm_info_node *node = (struct drm_info_node *) m->private;
593 struct drm_device *dev = node->minor->dev;
594 drm_i915_private_t *dev_priv = dev->dev_private;
c2c347a9
CW		 595 struct intel_ring_buffer *ring;
596
1ec14ad3 597 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
c2c347a9 598 if (ring->size == 0)
1ec14ad3 599 return 0;
6911a9b8 600
c2c347a9
CW		 601 seq_printf(m, "Ring %s:\n", ring->name);
602 seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
603 seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
604 seq_printf(m, " Size : %08x\n", ring->size);
605 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
1ec14ad3
CW		 606 seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
607 if (IS_GEN6(dev)) {
608 seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
609 seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
610 }
c2c347a9
CW		 611 seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
612 seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
6911a9b8
BG		 613
614 return 0;
615}
616
e5c65260
CW		 617static const char *ring_str(int ring)
618{
619 switch (ring) {
3685092b
CW		 620 case RING_RENDER: return " render";
621 case RING_BSD: return " bsd";
622 case RING_BLT: return " blt";
e5c65260
CW		 623 default: return "";
624 }
625}
626
9df30794
CW		 627static const char *pin_flag(int pinned)
628{
629 if (pinned > 0)
630 return " P";
631 else if (pinned < 0)
632 return " p";
633 else
634 return "";
635}
636
637static const char *tiling_flag(int tiling)
638{
639 switch (tiling) {
640 default:
641 case I915_TILING_NONE: return "";
642 case I915_TILING_X: return " X";
643 case I915_TILING_Y: return " Y";
644 }
645}
646
647static const char *dirty_flag(int dirty)
648{
649 return dirty ? " dirty" : "";
650}
651
652static const char *purgeable_flag(int purgeable)
653{
654 return purgeable ? " purgeable" : "";
655}
656
c724e8a9
CW		 657static void print_error_buffers(struct seq_file *m,
658 const char *name,
659 struct drm_i915_error_buffer *err,
660 int count)
661{
662 seq_printf(m, "%s [%d]:\n", name, count);
663
664 while (count--) {
665 seq_printf(m, " %08x %8zd %04x %04x %08x%s%s%s%s%s",
666 err->gtt_offset,
667 err->size,
668 err->read_domains,
669 err->write_domain,
670 err->seqno,
671 pin_flag(err->pinned),
672 tiling_flag(err->tiling),
673 dirty_flag(err->dirty),
674 purgeable_flag(err->purgeable),
675 ring_str(err->ring));
676
677 if (err->name)
678 seq_printf(m, " (name: %d)", err->name);
679 if (err->fence_reg != I915_FENCE_REG_NONE)
680 seq_printf(m, " (fence: %d)", err->fence_reg);
681
682 seq_printf(m, "\n");
683 err++;
684 }
685}
686
63eeaf38
JB		 687static int i915_error_state(struct seq_file *m, void *unused)
688{
689 struct drm_info_node *node = (struct drm_info_node *) m->private;
690 struct drm_device *dev = node->minor->dev;
691 drm_i915_private_t *dev_priv = dev->dev_private;
692 struct drm_i915_error_state *error;
693 unsigned long flags;
9df30794 694 int i, page, offset, elt;
63eeaf38
JB		 695
696 spin_lock_irqsave(&dev_priv->error_lock, flags);
697 if (!dev_priv->first_error) {
698 seq_printf(m, "no error state collected\n");
699 goto out;
700 }
701
702 error = dev_priv->first_error;
703
8a905236
JB		 704 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
705 error->time.tv_usec);
9df30794 706 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
1d8f38f4
CW		 707 seq_printf(m, "EIR: 0x%08x\n", error->eir);
708 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
f406839f
CW		 709 if (INTEL_INFO(dev)->gen >= 6) {
710 seq_printf(m, "ERROR: 0x%08x\n", error->error);
1d8f38f4
CW		 711 seq_printf(m, "Blitter command stream:\n");
712 seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
1d8f38f4 713 seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
e5c65260 714 seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
1d8f38f4
CW		 715 seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
716 seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
add354dd
CW		 717 seq_printf(m, "Video (BSD) command stream:\n");
718 seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
add354dd 719 seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
e5c65260 720 seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
add354dd
CW		 721 seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
722 seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
f406839f 723 }
1d8f38f4
CW		 724 seq_printf(m, "Render command stream:\n");
725 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
63eeaf38
JB		 726 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
727 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
728 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
a6c45cf0 729 if (INTEL_INFO(dev)->gen >= 4) {
63eeaf38 730 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
1d8f38f4 731 seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
63eeaf38 732 }
1d8f38f4
CW		 733 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
734 seq_printf(m, " seqno: 0x%08x\n", error->seqno);
9df30794 735
748ebc60
CW		 736 for (i = 0; i < 16; i++)
737 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
738
c724e8a9
CW		 739 if (error->active_bo)
740 print_error_buffers(m, "Active",
741 error->active_bo,
742 error->active_bo_count);
743
744 if (error->pinned_bo)
745 print_error_buffers(m, "Pinned",
746 error->pinned_bo,
747 error->pinned_bo_count);
9df30794
CW		 748
749 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
750 if (error->batchbuffer[i]) {
751 struct drm_i915_error_object *obj = error->batchbuffer[i];
752
753 seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
754 offset = 0;
755 for (page = 0; page < obj->page_count; page++) {
756 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
757 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
758 offset += 4;
759 }
760 }
761 }
762 }
763
764 if (error->ringbuffer) {
765 struct drm_i915_error_object *obj = error->ringbuffer;
766
767 seq_printf(m, "--- ringbuffer = 0x%08x\n", obj->gtt_offset);
768 offset = 0;
769 for (page = 0; page < obj->page_count; page++) {
770 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
771 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
772 offset += 4;
773 }
774 }
775 }
63eeaf38 776
6ef3d427
CW		 777 if (error->overlay)
778 intel_overlay_print_error_state(m, error->overlay);
779
c4a1d9e4
CW		 780 if (error->display)
781 intel_display_print_error_state(m, dev, error->display);
782
63eeaf38
JB		 783out:
784 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
785
786 return 0;
787}
6911a9b8 788
f97108d1
JB		 789static int i915_rstdby_delays(struct seq_file *m, void *unused)
790{
791 struct drm_info_node *node = (struct drm_info_node *) m->private;
792 struct drm_device *dev = node->minor->dev;
793 drm_i915_private_t *dev_priv = dev->dev_private;
794 u16 crstanddelay = I915_READ16(CRSTANDVID);
795
796 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
797
798 return 0;
799}
800
801static int i915_cur_delayinfo(struct seq_file *m, void *unused)
802{
803 struct drm_info_node *node = (struct drm_info_node *) m->private;
804 struct drm_device *dev = node->minor->dev;
805 drm_i915_private_t *dev_priv = dev->dev_private;
3b8d8d91
JB		 806
807 if (IS_GEN5(dev)) {
808 u16 rgvswctl = I915_READ16(MEMSWCTL);
809 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
810
811 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
812 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
813 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
814 MEMSTAT_VID_SHIFT);
815 seq_printf(m, "Current P-state: %d\n",
816 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
817 } else if (IS_GEN6(dev)) {
818 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
819 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
820 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
821 int max_freq;
822
823 /* RPSTAT1 is in the GT power well */
824 __gen6_force_wake_get(dev_priv);
825
826 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
827 seq_printf(m, "RPSTAT1: 0x%08x\n", I915_READ(GEN6_RPSTAT1));
828 seq_printf(m, "Render p-state ratio: %d\n",
829 (gt_perf_status & 0xff00) >> 8);
830 seq_printf(m, "Render p-state VID: %d\n",
831 gt_perf_status & 0xff);
832 seq_printf(m, "Render p-state limit: %d\n",
833 rp_state_limits & 0xff);
834
835 max_freq = (rp_state_cap & 0xff0000) >> 16;
836 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
837 max_freq * 100);
838
839 max_freq = (rp_state_cap & 0xff00) >> 8;
840 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
841 max_freq * 100);
842
843 max_freq = rp_state_cap & 0xff;
844 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
845 max_freq * 100);
846
847 __gen6_force_wake_put(dev_priv);
848 } else {
849 seq_printf(m, "no P-state info available\n");
850 }
f97108d1
JB		 851
852 return 0;
853}
854
855static int i915_delayfreq_table(struct seq_file *m, void *unused)
856{
857 struct drm_info_node *node = (struct drm_info_node *) m->private;
858 struct drm_device *dev = node->minor->dev;
859 drm_i915_private_t *dev_priv = dev->dev_private;
860 u32 delayfreq;
861 int i;
862
863 for (i = 0; i < 16; i++) {
864 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 865 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
866 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 867 }
868
869 return 0;
870}
871
872static inline int MAP_TO_MV(int map)
873{
874 return 1250 - (map * 25);
875}
876
877static int i915_inttoext_table(struct seq_file *m, void *unused)
878{
879 struct drm_info_node *node = (struct drm_info_node *) m->private;
880 struct drm_device *dev = node->minor->dev;
881 drm_i915_private_t *dev_priv = dev->dev_private;
882 u32 inttoext;
883 int i;
884
885 for (i = 1; i <= 32; i++) {
886 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
887 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
888 }
889
890 return 0;
891}
892
893static int i915_drpc_info(struct seq_file *m, void *unused)
894{
895 struct drm_info_node *node = (struct drm_info_node *) m->private;
896 struct drm_device *dev = node->minor->dev;
897 drm_i915_private_t *dev_priv = dev->dev_private;
898 u32 rgvmodectl = I915_READ(MEMMODECTL);
7648fa99
JB		 899 u32 rstdbyctl = I915_READ(MCHBAR_RENDER_STANDBY);
900 u16 crstandvid = I915_READ16(CRSTANDVID);
f97108d1
JB		 901
902 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
903 "yes" : "no");
904 seq_printf(m, "Boost freq: %d\n",
905 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
906 MEMMODE_BOOST_FREQ_SHIFT);
907 seq_printf(m, "HW control enabled: %s\n",
908 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
909 seq_printf(m, "SW control enabled: %s\n",
910 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
911 seq_printf(m, "Gated voltage change: %s\n",
912 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
913 seq_printf(m, "Starting frequency: P%d\n",
914 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 915 seq_printf(m, "Max P-state: P%d\n",
f97108d1 916 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 917 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
918 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
919 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
920 seq_printf(m, "Render standby enabled: %s\n",
921 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
f97108d1
JB		 922
923 return 0;
924}
925
b5e50c3f
JB		 926static int i915_fbc_status(struct seq_file *m, void *unused)
927{
928 struct drm_info_node *node = (struct drm_info_node *) m->private;
929 struct drm_device *dev = node->minor->dev;
b5e50c3f 930 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 931
ee5382ae 932 if (!I915_HAS_FBC(dev)) {
b5e50c3f
JB		 933 seq_printf(m, "FBC unsupported on this chipset\n");
934 return 0;
935 }
936
ee5382ae 937 if (intel_fbc_enabled(dev)) {
b5e50c3f
JB		 938 seq_printf(m, "FBC enabled\n");
939 } else {
940 seq_printf(m, "FBC disabled: ");
941 switch (dev_priv->no_fbc_reason) {
bed4a673
CW		 942 case FBC_NO_OUTPUT:
943 seq_printf(m, "no outputs");
944 break;
b5e50c3f
JB		 945 case FBC_STOLEN_TOO_SMALL:
946 seq_printf(m, "not enough stolen memory");
947 break;
948 case FBC_UNSUPPORTED_MODE:
949 seq_printf(m, "mode not supported");
950 break;
951 case FBC_MODE_TOO_LARGE:
952 seq_printf(m, "mode too large");
953 break;
954 case FBC_BAD_PLANE:
955 seq_printf(m, "FBC unsupported on plane");
956 break;
957 case FBC_NOT_TILED:
958 seq_printf(m, "scanout buffer not tiled");
959 break;
9c928d16
JB		 960 case FBC_MULTIPLE_PIPES:
961 seq_printf(m, "multiple pipes are enabled");
962 break;
b5e50c3f
JB		 963 default:
964 seq_printf(m, "unknown reason");
965 }
966 seq_printf(m, "\n");
967 }
968 return 0;
969}
970
4a9bef37
JB		 971static int i915_sr_status(struct seq_file *m, void *unused)
972{
973 struct drm_info_node *node = (struct drm_info_node *) m->private;
974 struct drm_device *dev = node->minor->dev;
975 drm_i915_private_t *dev_priv = dev->dev_private;
976 bool sr_enabled = false;
977
1398261a 978 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 979 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 980 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 981 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
982 else if (IS_I915GM(dev))
983 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
984 else if (IS_PINEVIEW(dev))
985 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
986
5ba2aaaa
CW		 987 seq_printf(m, "self-refresh: %s\n",
988 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 989
990 return 0;
991}
992
7648fa99
JB		 993static int i915_emon_status(struct seq_file *m, void *unused)
994{
995 struct drm_info_node *node = (struct drm_info_node *) m->private;
996 struct drm_device *dev = node->minor->dev;
997 drm_i915_private_t *dev_priv = dev->dev_private;
998 unsigned long temp, chipset, gfx;
de227ef0
CW		 999 int ret;
1000
1001 ret = mutex_lock_interruptible(&dev->struct_mutex);
1002 if (ret)
1003 return ret;
7648fa99
JB		 1004
1005 temp = i915_mch_val(dev_priv);
1006 chipset = i915_chipset_val(dev_priv);
1007 gfx = i915_gfx_val(dev_priv);
de227ef0 1008 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1009
1010 seq_printf(m, "GMCH temp: %ld\n", temp);
1011 seq_printf(m, "Chipset power: %ld\n", chipset);
1012 seq_printf(m, "GFX power: %ld\n", gfx);
1013 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1014
1015 return 0;
1016}
1017
1018static int i915_gfxec(struct seq_file *m, void *unused)
1019{
1020 struct drm_info_node *node = (struct drm_info_node *) m->private;
1021 struct drm_device *dev = node->minor->dev;
1022 drm_i915_private_t *dev_priv = dev->dev_private;
1023
1024 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1025
1026 return 0;
1027}
1028
44834a67
CW		 1029static int i915_opregion(struct seq_file *m, void *unused)
1030{
1031 struct drm_info_node *node = (struct drm_info_node *) m->private;
1032 struct drm_device *dev = node->minor->dev;
1033 drm_i915_private_t *dev_priv = dev->dev_private;
1034 struct intel_opregion *opregion = &dev_priv->opregion;
1035 int ret;
1036
1037 ret = mutex_lock_interruptible(&dev->struct_mutex);
1038 if (ret)
1039 return ret;
1040
1041 if (opregion->header)
1042 seq_write(m, opregion->header, OPREGION_SIZE);
1043
1044 mutex_unlock(&dev->struct_mutex);
1045
1046 return 0;
1047}
1048
37811fcc
CW		 1049static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1050{
1051 struct drm_info_node *node = (struct drm_info_node *) m->private;
1052 struct drm_device *dev = node->minor->dev;
1053 drm_i915_private_t *dev_priv = dev->dev_private;
1054 struct intel_fbdev *ifbdev;
1055 struct intel_framebuffer *fb;
1056 int ret;
1057
1058 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1059 if (ret)
1060 return ret;
1061
1062 ifbdev = dev_priv->fbdev;
1063 fb = to_intel_framebuffer(ifbdev->helper.fb);
1064
1065 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1066 fb->base.width,
1067 fb->base.height,
1068 fb->base.depth,
1069 fb->base.bits_per_pixel);
05394f39 1070 describe_obj(m, fb->obj);
37811fcc
CW		 1071 seq_printf(m, "\n");
1072
1073 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1074 if (&fb->base == ifbdev->helper.fb)
1075 continue;
1076
1077 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1078 fb->base.width,
1079 fb->base.height,
1080 fb->base.depth,
1081 fb->base.bits_per_pixel);
05394f39 1082 describe_obj(m, fb->obj);
37811fcc
CW		 1083 seq_printf(m, "\n");
1084 }
1085
1086 mutex_unlock(&dev->mode_config.mutex);
1087
1088 return 0;
1089}
1090
f3cd474b
CW		 1091static int
1092i915_wedged_open(struct inode *inode,
1093 struct file *filp)
1094{
1095 filp->private_data = inode->i_private;
1096 return 0;
1097}
1098
1099static ssize_t
1100i915_wedged_read(struct file *filp,
1101 char __user *ubuf,
1102 size_t max,
1103 loff_t *ppos)
1104{
1105 struct drm_device *dev = filp->private_data;
1106 drm_i915_private_t *dev_priv = dev->dev_private;
1107 char buf[80];
1108 int len;
1109
1110 len = snprintf(buf, sizeof (buf),
1111 "wedged : %d\n",
1112 atomic_read(&dev_priv->mm.wedged));
1113
f4433a8d
DC		 1114 if (len > sizeof (buf))
1115 len = sizeof (buf);
1116
f3cd474b
CW		 1117 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1118}
1119
1120static ssize_t
1121i915_wedged_write(struct file *filp,
1122 const char __user *ubuf,
1123 size_t cnt,
1124 loff_t *ppos)
1125{
1126 struct drm_device *dev = filp->private_data;
f3cd474b
CW		 1127 char buf[20];
1128 int val = 1;
1129
1130 if (cnt > 0) {
1131 if (cnt > sizeof (buf) - 1)
1132 return -EINVAL;
1133
1134 if (copy_from_user(buf, ubuf, cnt))
1135 return -EFAULT;
1136 buf[cnt] = 0;
1137
1138 val = simple_strtoul(buf, NULL, 0);
1139 }
1140
1141 DRM_INFO("Manually setting wedged to %d\n", val);
527f9e90 1142 i915_handle_error(dev, val);
f3cd474b
CW		 1143
1144 return cnt;
1145}
1146
1147static const struct file_operations i915_wedged_fops = {
1148 .owner = THIS_MODULE,
1149 .open = i915_wedged_open,
1150 .read = i915_wedged_read,
1151 .write = i915_wedged_write,
6038f373 1152 .llseek = default_llseek,
f3cd474b
CW		 1153};
1154
1155/* As the drm_debugfs_init() routines are called before dev->dev_private is
1156 * allocated we need to hook into the minor for release. */
1157static int
1158drm_add_fake_info_node(struct drm_minor *minor,
1159 struct dentry *ent,
1160 const void *key)
1161{
1162 struct drm_info_node *node;
1163
1164 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1165 if (node == NULL) {
1166 debugfs_remove(ent);
1167 return -ENOMEM;
1168 }
1169
1170 node->minor = minor;
1171 node->dent = ent;
1172 node->info_ent = (void *) key;
1173 list_add(&node->list, &minor->debugfs_nodes.list);
1174
1175 return 0;
1176}
1177
1178static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
1179{
1180 struct drm_device *dev = minor->dev;
1181 struct dentry *ent;
1182
1183 ent = debugfs_create_file("i915_wedged",
1184 S_IRUGO | S_IWUSR,
1185 root, dev,
1186 &i915_wedged_fops);
1187 if (IS_ERR(ent))
1188 return PTR_ERR(ent);
1189
1190 return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
1191}
9e3a6d15 1192
27c202ad 1193static struct drm_info_list i915_debugfs_list[] = {
70d39fe4 1194 {"i915_capabilities", i915_capabilities, 0, 0},
73aa808f 1195 {"i915_gem_objects", i915_gem_object_info, 0},
433e12f7
BG		 1196 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
1197 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
1198 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
f13d3f73 1199 {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
d21d5975 1200 {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
4e5359cd 1201 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 1202 {"i915_gem_request", i915_gem_request_info, 0},
1203 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 1204 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 1205 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 1206 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1207 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1208 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1209 {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
1210 {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
1211 {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
1212 {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
1213 {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
1214 {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
6911a9b8 1215 {"i915_batchbuffers", i915_batchbuffer_info, 0},
63eeaf38 1216 {"i915_error_state", i915_error_state, 0},
f97108d1
JB		 1217 {"i915_rstdby_delays", i915_rstdby_delays, 0},
1218 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1219 {"i915_delayfreq_table", i915_delayfreq_table, 0},
1220 {"i915_inttoext_table", i915_inttoext_table, 0},
1221 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99
JB		 1222 {"i915_emon_status", i915_emon_status, 0},
1223 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 1224 {"i915_fbc_status", i915_fbc_status, 0},
4a9bef37 1225 {"i915_sr_status", i915_sr_status, 0},
44834a67 1226 {"i915_opregion", i915_opregion, 0},
37811fcc 1227 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
2017263e 1228};
27c202ad 1229#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 1230
27c202ad 1231int i915_debugfs_init(struct drm_minor *minor)
2017263e 1232{
f3cd474b
CW		 1233 int ret;
1234
1235 ret = i915_wedged_create(minor->debugfs_root, minor);
1236 if (ret)
1237 return ret;
1238
27c202ad
BG		 1239 return drm_debugfs_create_files(i915_debugfs_list,
1240 I915_DEBUGFS_ENTRIES,
2017263e
BG		 1241 minor->debugfs_root, minor);
1242}
1243
27c202ad 1244void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 1245{
27c202ad
BG		 1246 drm_debugfs_remove_files(i915_debugfs_list,
1247 I915_DEBUGFS_ENTRIES, minor);
33db679b
KH		 1248 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1249 1, minor);
2017263e
BG		 1250}
1251
1252#endif /* CONFIG_DEBUG_FS */
Linux 6.x block layer and io_uring tree(s)