Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
7d57382e | 29 | #include <linux/delay.h> |
178f736a | 30 | #include <linux/hdmi.h> |
331c201a JN |
31 | #include <linux/i2c.h> |
32 | #include <linux/slab.h> | |
33 | ||
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
2320175f | 37 | #include <drm/drm_hdcp.h> |
15953637 | 38 | #include <drm/drm_scdc_helper.h> |
760285e7 | 39 | #include <drm/i915_drm.h> |
46d196ec | 40 | #include <drm/intel_lpe_audio.h> |
331c201a | 41 | |
2126d3e9 | 42 | #include "i915_debugfs.h" |
7d57382e | 43 | #include "i915_drv.h" |
12392a74 | 44 | #include "intel_atomic.h" |
331c201a | 45 | #include "intel_audio.h" |
ec7f29ff | 46 | #include "intel_connector.h" |
fdc24cf3 | 47 | #include "intel_ddi.h" |
1d455f8d | 48 | #include "intel_display_types.h" |
27fec1f9 | 49 | #include "intel_dp.h" |
b1ad4c39 | 50 | #include "intel_dpio_phy.h" |
8834e365 | 51 | #include "intel_fifo_underrun.h" |
3ce2ea65 | 52 | #include "intel_gmbus.h" |
408bd917 | 53 | #include "intel_hdcp.h" |
0550691d | 54 | #include "intel_hdmi.h" |
dbeb38d9 | 55 | #include "intel_hotplug.h" |
f3e18947 | 56 | #include "intel_lspcon.h" |
44c1220a | 57 | #include "intel_panel.h" |
1d455f8d | 58 | #include "intel_sdvo.h" |
56c5098f | 59 | #include "intel_sideband.h" |
7d57382e | 60 | |
30add22d PZ |
61 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
62 | { | |
da63a9f2 | 63 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
64 | } |
65 | ||
afba0188 DV |
66 | static void |
67 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
68 | { | |
30add22d | 69 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 70 | struct drm_i915_private *dev_priv = to_i915(dev); |
faa087c4 | 71 | u32 enabled_bits; |
afba0188 | 72 | |
4f8036a2 | 73 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 74 | |
b242b7f7 | 75 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
76 | "HDMI port enabled, expecting disabled\n"); |
77 | } | |
78 | ||
8fc0aa6e ID |
79 | static void |
80 | assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, | |
81 | enum transcoder cpu_transcoder) | |
82 | { | |
83 | WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & | |
84 | TRANS_DDI_FUNC_ENABLE, | |
85 | "HDMI transcoder function enabled, expecting disabled\n"); | |
86 | } | |
87 | ||
f5bbfca3 | 88 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 89 | { |
da63a9f2 PZ |
90 | struct intel_digital_port *intel_dig_port = |
91 | container_of(encoder, struct intel_digital_port, base.base); | |
92 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
93 | } |
94 | ||
df0e9248 CW |
95 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
96 | { | |
da63a9f2 | 97 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
98 | } |
99 | ||
1d776538 | 100 | static u32 g4x_infoframe_index(unsigned int type) |
3c17fe4b | 101 | { |
178f736a | 102 | switch (type) { |
5cb3c1a1 VS |
103 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
104 | return VIDEO_DIP_SELECT_GAMUT; | |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 106 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 107 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 108 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
109 | case HDMI_INFOFRAME_TYPE_VENDOR: |
110 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 111 | default: |
ffc85dab | 112 | MISSING_CASE(type); |
ed517fbb | 113 | return 0; |
45187ace | 114 | } |
45187ace JB |
115 | } |
116 | ||
1d776538 | 117 | static u32 g4x_infoframe_enable(unsigned int type) |
45187ace | 118 | { |
178f736a | 119 | switch (type) { |
5cb3c1a1 VS |
120 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
121 | return VIDEO_DIP_ENABLE_GCP; | |
122 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
123 | return VIDEO_DIP_ENABLE_GAMUT; | |
509efa2b VS |
124 | case DP_SDP_VSC: |
125 | return 0; | |
178f736a | 126 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 127 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 128 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 129 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
130 | case HDMI_INFOFRAME_TYPE_VENDOR: |
131 | return VIDEO_DIP_ENABLE_VENDOR; | |
c0560fab US |
132 | case HDMI_INFOFRAME_TYPE_DRM: |
133 | return 0; | |
fa193ff7 | 134 | default: |
ffc85dab | 135 | MISSING_CASE(type); |
ed517fbb | 136 | return 0; |
fa193ff7 | 137 | } |
fa193ff7 PZ |
138 | } |
139 | ||
1d776538 | 140 | static u32 hsw_infoframe_enable(unsigned int type) |
2da8af54 | 141 | { |
178f736a | 142 | switch (type) { |
5cb3c1a1 VS |
143 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
144 | return VIDEO_DIP_ENABLE_GCP_HSW; | |
145 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
146 | return VIDEO_DIP_ENABLE_GMP_HSW; | |
1d776538 VS |
147 | case DP_SDP_VSC: |
148 | return VIDEO_DIP_ENABLE_VSC_HSW; | |
4c614831 MN |
149 | case DP_SDP_PPS: |
150 | return VDIP_ENABLE_PPS; | |
178f736a | 151 | case HDMI_INFOFRAME_TYPE_AVI: |
2da8af54 | 152 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 153 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 154 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
155 | case HDMI_INFOFRAME_TYPE_VENDOR: |
156 | return VIDEO_DIP_ENABLE_VS_HSW; | |
44b42ebf VS |
157 | case HDMI_INFOFRAME_TYPE_DRM: |
158 | return VIDEO_DIP_ENABLE_DRM_GLK; | |
2da8af54 | 159 | default: |
ffc85dab | 160 | MISSING_CASE(type); |
2da8af54 PZ |
161 | return 0; |
162 | } | |
163 | } | |
164 | ||
f0f59a00 VS |
165 | static i915_reg_t |
166 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
167 | enum transcoder cpu_transcoder, | |
1d776538 | 168 | unsigned int type, |
f0f59a00 | 169 | int i) |
2da8af54 | 170 | { |
178f736a | 171 | switch (type) { |
5cb3c1a1 VS |
172 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
173 | return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); | |
1d776538 VS |
174 | case DP_SDP_VSC: |
175 | return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); | |
4c614831 MN |
176 | case DP_SDP_PPS: |
177 | return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); | |
178f736a | 178 | case HDMI_INFOFRAME_TYPE_AVI: |
436c6d4a | 179 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 180 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 181 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 182 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 183 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
44b42ebf VS |
184 | case HDMI_INFOFRAME_TYPE_DRM: |
185 | return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); | |
2da8af54 | 186 | default: |
ffc85dab | 187 | MISSING_CASE(type); |
f0f59a00 | 188 | return INVALID_MMIO_REG; |
2da8af54 PZ |
189 | } |
190 | } | |
191 | ||
4c614831 MN |
192 | static int hsw_dip_data_size(unsigned int type) |
193 | { | |
194 | switch (type) { | |
195 | case DP_SDP_VSC: | |
196 | return VIDEO_DIP_VSC_DATA_SIZE; | |
197 | case DP_SDP_PPS: | |
198 | return VIDEO_DIP_PPS_DATA_SIZE; | |
199 | default: | |
200 | return VIDEO_DIP_DATA_SIZE; | |
201 | } | |
202 | } | |
203 | ||
790ea70c | 204 | static void g4x_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 205 | const struct intel_crtc_state *crtc_state, |
1d776538 | 206 | unsigned int type, |
fff63867 | 207 | const void *frame, ssize_t len) |
45187ace | 208 | { |
faa087c4 | 209 | const u32 *data = frame; |
790ea70c | 210 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
22509ec8 | 211 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 212 | int i; |
3c17fe4b | 213 | |
822974ae PZ |
214 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
215 | ||
1d4f85ac | 216 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 217 | val |= g4x_infoframe_index(type); |
22509ec8 | 218 | |
178f736a | 219 | val &= ~g4x_infoframe_enable(type); |
45187ace | 220 | |
22509ec8 | 221 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 222 | |
45187ace | 223 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
224 | I915_WRITE(VIDEO_DIP_DATA, *data); |
225 | data++; | |
226 | } | |
adf00b26 PZ |
227 | /* Write every possible data byte to force correct ECC calculation. */ |
228 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
229 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
3c17fe4b | 230 | |
178f736a | 231 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 232 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 233 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 234 | |
22509ec8 | 235 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 236 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
237 | } |
238 | ||
f2a10d61 VS |
239 | static void g4x_read_infoframe(struct intel_encoder *encoder, |
240 | const struct intel_crtc_state *crtc_state, | |
241 | unsigned int type, | |
242 | void *frame, ssize_t len) | |
243 | { | |
244 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
245 | u32 val, *data = frame; | |
246 | int i; | |
247 | ||
248 | val = I915_READ(VIDEO_DIP_CTL); | |
249 | ||
250 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
251 | val |= g4x_infoframe_index(type); | |
252 | ||
253 | I915_WRITE(VIDEO_DIP_CTL, val); | |
254 | ||
255 | for (i = 0; i < len; i += 4) | |
256 | *data++ = I915_READ(VIDEO_DIP_DATA); | |
257 | } | |
258 | ||
509efa2b | 259 | static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 260 | const struct intel_crtc_state *pipe_config) |
e43823ec | 261 | { |
790ea70c | 262 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e43823ec JB |
263 | u32 val = I915_READ(VIDEO_DIP_CTL); |
264 | ||
ec1dc603 | 265 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 266 | return 0; |
89a35ecd | 267 | |
790ea70c | 268 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 269 | return 0; |
ec1dc603 VS |
270 | |
271 | return val & (VIDEO_DIP_ENABLE_AVI | | |
272 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
273 | } |
274 | ||
790ea70c | 275 | static void ibx_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 276 | const struct intel_crtc_state *crtc_state, |
1d776538 | 277 | unsigned int type, |
fff63867 | 278 | const void *frame, ssize_t len) |
fdf1250a | 279 | { |
faa087c4 | 280 | const u32 *data = frame; |
790ea70c | 281 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 282 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 283 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 284 | u32 val = I915_READ(reg); |
f0f59a00 | 285 | int i; |
fdf1250a | 286 | |
822974ae PZ |
287 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
288 | ||
fdf1250a | 289 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 290 | val |= g4x_infoframe_index(type); |
fdf1250a | 291 | |
178f736a | 292 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
293 | |
294 | I915_WRITE(reg, val); | |
295 | ||
296 | for (i = 0; i < len; i += 4) { | |
297 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
298 | data++; | |
299 | } | |
adf00b26 PZ |
300 | /* Write every possible data byte to force correct ECC calculation. */ |
301 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
302 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
fdf1250a | 303 | |
178f736a | 304 | val |= g4x_infoframe_enable(type); |
fdf1250a | 305 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 306 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
307 | |
308 | I915_WRITE(reg, val); | |
9d9740f0 | 309 | POSTING_READ(reg); |
fdf1250a PZ |
310 | } |
311 | ||
f2a10d61 VS |
312 | static void ibx_read_infoframe(struct intel_encoder *encoder, |
313 | const struct intel_crtc_state *crtc_state, | |
314 | unsigned int type, | |
315 | void *frame, ssize_t len) | |
316 | { | |
317 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
318 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
319 | u32 val, *data = frame; | |
320 | int i; | |
321 | ||
322 | val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); | |
323 | ||
324 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
325 | val |= g4x_infoframe_index(type); | |
326 | ||
327 | I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); | |
328 | ||
329 | for (i = 0; i < len; i += 4) | |
330 | *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); | |
331 | } | |
332 | ||
509efa2b | 333 | static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 334 | const struct intel_crtc_state *pipe_config) |
e43823ec | 335 | { |
790ea70c | 336 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
337 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
338 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
339 | u32 val = I915_READ(reg); |
340 | ||
ec1dc603 | 341 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 342 | return 0; |
ec1dc603 | 343 | |
790ea70c | 344 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 345 | return 0; |
052f62f7 | 346 | |
ec1dc603 VS |
347 | return val & (VIDEO_DIP_ENABLE_AVI | |
348 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
349 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
350 | } |
351 | ||
790ea70c | 352 | static void cpt_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 353 | const struct intel_crtc_state *crtc_state, |
1d776538 | 354 | unsigned int type, |
fff63867 | 355 | const void *frame, ssize_t len) |
b055c8f3 | 356 | { |
faa087c4 | 357 | const u32 *data = frame; |
790ea70c | 358 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 359 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 360 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 361 | u32 val = I915_READ(reg); |
f0f59a00 | 362 | int i; |
b055c8f3 | 363 | |
822974ae PZ |
364 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
365 | ||
64a8fc01 | 366 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 367 | val |= g4x_infoframe_index(type); |
45187ace | 368 | |
ecb97851 PZ |
369 | /* The DIP control register spec says that we need to update the AVI |
370 | * infoframe without clearing its enable bit */ | |
178f736a DL |
371 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
372 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 373 | |
22509ec8 | 374 | I915_WRITE(reg, val); |
45187ace JB |
375 | |
376 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
377 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
378 | data++; | |
379 | } | |
adf00b26 PZ |
380 | /* Write every possible data byte to force correct ECC calculation. */ |
381 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
382 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
b055c8f3 | 383 | |
178f736a | 384 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 385 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 386 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 387 | |
22509ec8 | 388 | I915_WRITE(reg, val); |
9d9740f0 | 389 | POSTING_READ(reg); |
45187ace | 390 | } |
90b107c8 | 391 | |
f2a10d61 VS |
392 | static void cpt_read_infoframe(struct intel_encoder *encoder, |
393 | const struct intel_crtc_state *crtc_state, | |
394 | unsigned int type, | |
395 | void *frame, ssize_t len) | |
396 | { | |
397 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
398 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
399 | u32 val, *data = frame; | |
400 | int i; | |
401 | ||
402 | val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); | |
403 | ||
404 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
405 | val |= g4x_infoframe_index(type); | |
406 | ||
407 | I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); | |
408 | ||
409 | for (i = 0; i < len; i += 4) | |
410 | *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); | |
411 | } | |
412 | ||
509efa2b | 413 | static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 414 | const struct intel_crtc_state *pipe_config) |
e43823ec | 415 | { |
790ea70c | 416 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
417 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
418 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 419 | |
ec1dc603 | 420 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 421 | return 0; |
ec1dc603 VS |
422 | |
423 | return val & (VIDEO_DIP_ENABLE_AVI | | |
424 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
425 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
426 | } |
427 | ||
790ea70c | 428 | static void vlv_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 429 | const struct intel_crtc_state *crtc_state, |
1d776538 | 430 | unsigned int type, |
fff63867 | 431 | const void *frame, ssize_t len) |
90b107c8 | 432 | { |
faa087c4 | 433 | const u32 *data = frame; |
790ea70c | 434 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 435 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 436 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 437 | u32 val = I915_READ(reg); |
f0f59a00 | 438 | int i; |
90b107c8 | 439 | |
822974ae PZ |
440 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
441 | ||
90b107c8 | 442 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 443 | val |= g4x_infoframe_index(type); |
22509ec8 | 444 | |
178f736a | 445 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 446 | |
22509ec8 | 447 | I915_WRITE(reg, val); |
90b107c8 SK |
448 | |
449 | for (i = 0; i < len; i += 4) { | |
450 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
451 | data++; | |
452 | } | |
adf00b26 PZ |
453 | /* Write every possible data byte to force correct ECC calculation. */ |
454 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
455 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
90b107c8 | 456 | |
178f736a | 457 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 458 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 459 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 460 | |
22509ec8 | 461 | I915_WRITE(reg, val); |
9d9740f0 | 462 | POSTING_READ(reg); |
90b107c8 SK |
463 | } |
464 | ||
f2a10d61 VS |
465 | static void vlv_read_infoframe(struct intel_encoder *encoder, |
466 | const struct intel_crtc_state *crtc_state, | |
467 | unsigned int type, | |
468 | void *frame, ssize_t len) | |
469 | { | |
470 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
471 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
472 | u32 val, *data = frame; | |
473 | int i; | |
474 | ||
475 | val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); | |
476 | ||
477 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
478 | val |= g4x_infoframe_index(type); | |
479 | ||
480 | I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val); | |
481 | ||
482 | for (i = 0; i < len; i += 4) | |
483 | *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe)); | |
484 | } | |
485 | ||
509efa2b | 486 | static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 487 | const struct intel_crtc_state *pipe_config) |
e43823ec | 488 | { |
790ea70c | 489 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
490 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
491 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 492 | |
ec1dc603 | 493 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 494 | return 0; |
ec1dc603 | 495 | |
790ea70c | 496 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 497 | return 0; |
535afa2e | 498 | |
ec1dc603 VS |
499 | return val & (VIDEO_DIP_ENABLE_AVI | |
500 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
501 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
502 | } |
503 | ||
790ea70c | 504 | static void hsw_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 505 | const struct intel_crtc_state *crtc_state, |
1d776538 | 506 | unsigned int type, |
fff63867 | 507 | const void *frame, ssize_t len) |
8c5f5f7c | 508 | { |
faa087c4 | 509 | const u32 *data = frame; |
790ea70c | 510 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 511 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 | 512 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
4c614831 | 513 | int data_size; |
178f736a | 514 | int i; |
2da8af54 | 515 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 516 | |
4c614831 MN |
517 | data_size = hsw_dip_data_size(type); |
518 | ||
178f736a | 519 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
520 | I915_WRITE(ctl_reg, val); |
521 | ||
522 | for (i = 0; i < len; i += 4) { | |
436c6d4a VS |
523 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
524 | type, i >> 2), *data); | |
2da8af54 PZ |
525 | data++; |
526 | } | |
adf00b26 | 527 | /* Write every possible data byte to force correct ECC calculation. */ |
1d776538 | 528 | for (; i < data_size; i += 4) |
436c6d4a VS |
529 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
530 | type, i >> 2), 0); | |
8c5f5f7c | 531 | |
178f736a | 532 | val |= hsw_infoframe_enable(type); |
2da8af54 | 533 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 534 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
535 | } |
536 | ||
f2a10d61 VS |
537 | static void hsw_read_infoframe(struct intel_encoder *encoder, |
538 | const struct intel_crtc_state *crtc_state, | |
539 | unsigned int type, | |
540 | void *frame, ssize_t len) | |
541 | { | |
542 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
543 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
544 | u32 val, *data = frame; | |
545 | int i; | |
546 | ||
547 | val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); | |
548 | ||
549 | for (i = 0; i < len; i += 4) | |
550 | *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, | |
551 | type, i >> 2)); | |
552 | } | |
553 | ||
509efa2b | 554 | static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 555 | const struct intel_crtc_state *pipe_config) |
e43823ec | 556 | { |
790ea70c | 557 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf | 558 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); |
44b42ebf VS |
559 | u32 mask; |
560 | ||
561 | mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | | |
562 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
563 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
564 | ||
565 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) | |
566 | mask |= VIDEO_DIP_ENABLE_DRM_GLK; | |
e43823ec | 567 | |
44b42ebf | 568 | return val & mask; |
e43823ec JB |
569 | } |
570 | ||
509efa2b VS |
571 | static const u8 infoframe_type_to_idx[] = { |
572 | HDMI_PACKET_TYPE_GENERAL_CONTROL, | |
573 | HDMI_PACKET_TYPE_GAMUT_METADATA, | |
574 | DP_SDP_VSC, | |
575 | HDMI_INFOFRAME_TYPE_AVI, | |
576 | HDMI_INFOFRAME_TYPE_SPD, | |
577 | HDMI_INFOFRAME_TYPE_VENDOR, | |
5a0200f6 | 578 | HDMI_INFOFRAME_TYPE_DRM, |
509efa2b VS |
579 | }; |
580 | ||
fbf08556 VS |
581 | u32 intel_hdmi_infoframe_enable(unsigned int type) |
582 | { | |
583 | int i; | |
584 | ||
585 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
586 | if (infoframe_type_to_idx[i] == type) | |
587 | return BIT(i); | |
588 | } | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
509efa2b VS |
593 | u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, |
594 | const struct intel_crtc_state *crtc_state) | |
595 | { | |
596 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
597 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
598 | u32 val, ret = 0; | |
599 | int i; | |
600 | ||
601 | val = dig_port->infoframes_enabled(encoder, crtc_state); | |
602 | ||
603 | /* map from hardware bits to dip idx */ | |
604 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
605 | unsigned int type = infoframe_type_to_idx[i]; | |
606 | ||
607 | if (HAS_DDI(dev_priv)) { | |
608 | if (val & hsw_infoframe_enable(type)) | |
609 | ret |= BIT(i); | |
610 | } else { | |
611 | if (val & g4x_infoframe_enable(type)) | |
612 | ret |= BIT(i); | |
613 | } | |
614 | } | |
615 | ||
616 | return ret; | |
617 | } | |
618 | ||
5adaea79 DL |
619 | /* |
620 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
621 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
622 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
623 | * used for both technologies. | |
624 | * | |
625 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
626 | * DW1: DB3 | DB2 | DB1 | DB0 | |
627 | * DW2: DB7 | DB6 | DB5 | DB4 | |
628 | * DW3: ... | |
629 | * | |
630 | * (HB is Header Byte, DB is Data Byte) | |
631 | * | |
632 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
633 | * trick them by giving an offset into the buffer and moving back the header | |
634 | * bytes by one. | |
635 | */ | |
790ea70c | 636 | static void intel_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 637 | const struct intel_crtc_state *crtc_state, |
fbf08556 VS |
638 | enum hdmi_infoframe_type type, |
639 | const union hdmi_infoframe *frame) | |
45187ace | 640 | { |
790ea70c | 641 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
faa087c4 | 642 | u8 buffer[VIDEO_DIP_DATA_SIZE]; |
5adaea79 | 643 | ssize_t len; |
45187ace | 644 | |
fbf08556 VS |
645 | if ((crtc_state->infoframes.enable & |
646 | intel_hdmi_infoframe_enable(type)) == 0) | |
647 | return; | |
648 | ||
649 | if (WARN_ON(frame->any.type != type)) | |
650 | return; | |
651 | ||
5adaea79 | 652 | /* see comment above for the reason for this offset */ |
fbf08556 VS |
653 | len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); |
654 | if (WARN_ON(len < 0)) | |
5adaea79 DL |
655 | return; |
656 | ||
657 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
121f0ff5 | 658 | memmove(&buffer[0], &buffer[1], 3); |
5adaea79 DL |
659 | buffer[3] = 0; |
660 | len++; | |
45187ace | 661 | |
fbf08556 | 662 | intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); |
45187ace JB |
663 | } |
664 | ||
f2a10d61 VS |
665 | void intel_read_infoframe(struct intel_encoder *encoder, |
666 | const struct intel_crtc_state *crtc_state, | |
667 | enum hdmi_infoframe_type type, | |
668 | union hdmi_infoframe *frame) | |
669 | { | |
670 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
671 | u8 buffer[VIDEO_DIP_DATA_SIZE]; | |
672 | int ret; | |
673 | ||
674 | if ((crtc_state->infoframes.enable & | |
675 | intel_hdmi_infoframe_enable(type)) == 0) | |
676 | return; | |
677 | ||
678 | intel_dig_port->read_infoframe(encoder, crtc_state, | |
679 | type, buffer, sizeof(buffer)); | |
680 | ||
681 | /* Fill the 'hole' (see big comment above) at position 3 */ | |
682 | memmove(&buffer[1], &buffer[0], 3); | |
683 | ||
684 | /* see comment above for the reason for this offset */ | |
685 | ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); | |
686 | if (ret) { | |
687 | DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); | |
688 | return; | |
689 | } | |
690 | ||
691 | if (frame->any.type != type) | |
692 | DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", | |
693 | frame->any.type, type); | |
694 | } | |
695 | ||
fbf08556 VS |
696 | static bool |
697 | intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, | |
698 | struct intel_crtc_state *crtc_state, | |
699 | struct drm_connector_state *conn_state) | |
45187ace | 700 | { |
fbf08556 | 701 | struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; |
779c4c28 VS |
702 | const struct drm_display_mode *adjusted_mode = |
703 | &crtc_state->base.adjusted_mode; | |
fbf08556 | 704 | struct drm_connector *connector = conn_state->connector; |
5adaea79 | 705 | int ret; |
45187ace | 706 | |
fbf08556 VS |
707 | if (!crtc_state->has_infoframe) |
708 | return true; | |
709 | ||
710 | crtc_state->infoframes.enable |= | |
711 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); | |
712 | ||
713 | ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, | |
13d0add3 | 714 | adjusted_mode); |
fbf08556 VS |
715 | if (ret) |
716 | return false; | |
c846b619 | 717 | |
33b7f3ee | 718 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
fbf08556 | 719 | frame->colorspace = HDMI_COLORSPACE_YUV420; |
8c79f844 | 720 | else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) |
fbf08556 | 721 | frame->colorspace = HDMI_COLORSPACE_YUV444; |
2d8bd2bf | 722 | else |
fbf08556 | 723 | frame->colorspace = HDMI_COLORSPACE_RGB; |
2d8bd2bf | 724 | |
0e2f54f8 | 725 | drm_hdmi_avi_infoframe_colorspace(frame, conn_state); |
2d8bd2bf | 726 | |
791ad5f1 VS |
727 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { |
728 | drm_hdmi_avi_infoframe_quant_range(frame, connector, | |
729 | adjusted_mode, | |
730 | crtc_state->limited_color_range ? | |
731 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
732 | HDMI_QUANTIZATION_RANGE_FULL); | |
733 | } else { | |
734 | frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; | |
735 | frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; | |
736 | } | |
abedc077 | 737 | |
fbf08556 | 738 | drm_hdmi_avi_infoframe_content_type(frame, conn_state); |
6553b123 | 739 | |
2d8bd2bf | 740 | /* TODO: handle pixel repetition for YCBCR420 outputs */ |
fbf08556 VS |
741 | |
742 | ret = hdmi_avi_infoframe_check(frame); | |
743 | if (WARN_ON(ret)) | |
744 | return false; | |
745 | ||
746 | return true; | |
b055c8f3 JB |
747 | } |
748 | ||
fbf08556 VS |
749 | static bool |
750 | intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, | |
751 | struct intel_crtc_state *crtc_state, | |
752 | struct drm_connector_state *conn_state) | |
c0864cb3 | 753 | { |
fbf08556 | 754 | struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; |
5adaea79 DL |
755 | int ret; |
756 | ||
fbf08556 VS |
757 | if (!crtc_state->has_infoframe) |
758 | return true; | |
c0864cb3 | 759 | |
fbf08556 VS |
760 | crtc_state->infoframes.enable |= |
761 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); | |
c0864cb3 | 762 | |
fbf08556 VS |
763 | ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); |
764 | if (WARN_ON(ret)) | |
765 | return false; | |
766 | ||
767 | frame->sdi = HDMI_SPD_SDI_PC; | |
768 | ||
769 | ret = hdmi_spd_infoframe_check(frame); | |
770 | if (WARN_ON(ret)) | |
771 | return false; | |
772 | ||
773 | return true; | |
c0864cb3 JB |
774 | } |
775 | ||
fbf08556 VS |
776 | static bool |
777 | intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, | |
778 | struct intel_crtc_state *crtc_state, | |
779 | struct drm_connector_state *conn_state) | |
780 | { | |
781 | struct hdmi_vendor_infoframe *frame = | |
782 | &crtc_state->infoframes.hdmi.vendor.hdmi; | |
783 | const struct drm_display_info *info = | |
784 | &conn_state->connector->display_info; | |
c8bb75af LD |
785 | int ret; |
786 | ||
fbf08556 VS |
787 | if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) |
788 | return true; | |
789 | ||
790 | crtc_state->infoframes.enable |= | |
791 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); | |
792 | ||
793 | ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, | |
f1781e9b | 794 | conn_state->connector, |
ac240288 | 795 | &crtc_state->base.adjusted_mode); |
fbf08556 VS |
796 | if (WARN_ON(ret)) |
797 | return false; | |
c8bb75af | 798 | |
fbf08556 VS |
799 | ret = hdmi_vendor_infoframe_check(frame); |
800 | if (WARN_ON(ret)) | |
801 | return false; | |
802 | ||
803 | return true; | |
c8bb75af LD |
804 | } |
805 | ||
5a0200f6 US |
806 | static bool |
807 | intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, | |
808 | struct intel_crtc_state *crtc_state, | |
809 | struct drm_connector_state *conn_state) | |
810 | { | |
811 | struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; | |
812 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
813 | int ret; | |
814 | ||
815 | if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) | |
816 | return true; | |
817 | ||
818 | if (!crtc_state->has_infoframe) | |
819 | return true; | |
820 | ||
821 | if (!conn_state->hdr_output_metadata) | |
822 | return true; | |
823 | ||
824 | crtc_state->infoframes.enable |= | |
825 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); | |
826 | ||
827 | ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); | |
828 | if (ret < 0) { | |
829 | DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); | |
830 | return false; | |
831 | } | |
832 | ||
833 | ret = hdmi_drm_infoframe_check(frame); | |
834 | if (WARN_ON(ret)) | |
835 | return false; | |
836 | ||
837 | return true; | |
838 | } | |
839 | ||
790ea70c | 840 | static void g4x_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 841 | bool enable, |
ac240288 ML |
842 | const struct intel_crtc_state *crtc_state, |
843 | const struct drm_connector_state *conn_state) | |
687f4d06 | 844 | { |
790ea70c VS |
845 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
846 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
69fde0a6 | 847 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 848 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 849 | u32 val = I915_READ(reg); |
790ea70c | 850 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 851 | |
afba0188 DV |
852 | assert_hdmi_port_disabled(intel_hdmi); |
853 | ||
0c14c7f9 PZ |
854 | /* If the registers were not initialized yet, they might be zeroes, |
855 | * which means we're selecting the AVI DIP and we're setting its | |
856 | * frequency to once. This seems to really confuse the HW and make | |
857 | * things stop working (the register spec says the AVI always needs to | |
858 | * be sent every VSync). So here we avoid writing to the register more | |
859 | * than we need and also explicitly select the AVI DIP and explicitly | |
860 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
861 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
862 | * either. */ | |
863 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
864 | ||
6897b4b5 | 865 | if (!enable) { |
0c14c7f9 PZ |
866 | if (!(val & VIDEO_DIP_ENABLE)) |
867 | return; | |
0be6f0c8 VS |
868 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
869 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
870 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
871 | return; | |
872 | } | |
873 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
874 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 875 | I915_WRITE(reg, val); |
9d9740f0 | 876 | POSTING_READ(reg); |
0c14c7f9 PZ |
877 | return; |
878 | } | |
879 | ||
72b78c9d PZ |
880 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
881 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
882 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
883 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
884 | return; | |
72b78c9d PZ |
885 | } |
886 | val &= ~VIDEO_DIP_PORT_MASK; | |
887 | val |= port; | |
888 | } | |
889 | ||
822974ae | 890 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
891 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
892 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 893 | |
f278d972 | 894 | I915_WRITE(reg, val); |
9d9740f0 | 895 | POSTING_READ(reg); |
f278d972 | 896 | |
fbf08556 VS |
897 | intel_write_infoframe(encoder, crtc_state, |
898 | HDMI_INFOFRAME_TYPE_AVI, | |
899 | &crtc_state->infoframes.avi); | |
900 | intel_write_infoframe(encoder, crtc_state, | |
901 | HDMI_INFOFRAME_TYPE_SPD, | |
902 | &crtc_state->infoframes.spd); | |
903 | intel_write_infoframe(encoder, crtc_state, | |
904 | HDMI_INFOFRAME_TYPE_VENDOR, | |
905 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
906 | } |
907 | ||
12aa3290 VS |
908 | /* |
909 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
910 | * | |
911 | * From HDMI specification 1.4a: | |
912 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
913 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
914 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
915 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
916 | * phase of 0 | |
917 | */ | |
918 | static bool gcp_default_phase_possible(int pipe_bpp, | |
919 | const struct drm_display_mode *mode) | |
920 | { | |
921 | unsigned int pixels_per_group; | |
922 | ||
923 | switch (pipe_bpp) { | |
924 | case 30: | |
925 | /* 4 pixels in 5 clocks */ | |
926 | pixels_per_group = 4; | |
927 | break; | |
928 | case 36: | |
929 | /* 2 pixels in 3 clocks */ | |
930 | pixels_per_group = 2; | |
931 | break; | |
932 | case 48: | |
933 | /* 1 pixel in 2 clocks */ | |
934 | pixels_per_group = 1; | |
935 | break; | |
936 | default: | |
937 | /* phase information not relevant for 8bpc */ | |
938 | return false; | |
939 | } | |
940 | ||
941 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
942 | mode->crtc_htotal % pixels_per_group == 0 && | |
943 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
944 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
945 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
946 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
947 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
948 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
949 | } | |
950 | ||
790ea70c | 951 | static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, |
ac240288 ML |
952 | const struct intel_crtc_state *crtc_state, |
953 | const struct drm_connector_state *conn_state) | |
6d67415f | 954 | { |
790ea70c | 955 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 956 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 957 | i915_reg_t reg; |
fbf08556 VS |
958 | |
959 | if ((crtc_state->infoframes.enable & | |
960 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
961 | return false; | |
6d67415f VS |
962 | |
963 | if (HAS_DDI(dev_priv)) | |
ac240288 | 964 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 965 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 966 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 967 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
968 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
969 | else | |
970 | return false; | |
971 | ||
fbf08556 VS |
972 | I915_WRITE(reg, crtc_state->infoframes.gcp); |
973 | ||
974 | return true; | |
975 | } | |
976 | ||
f2a10d61 VS |
977 | void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, |
978 | struct intel_crtc_state *crtc_state) | |
979 | { | |
980 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
981 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
982 | i915_reg_t reg; | |
983 | ||
984 | if ((crtc_state->infoframes.enable & | |
985 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
986 | return; | |
987 | ||
988 | if (HAS_DDI(dev_priv)) | |
989 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); | |
990 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
991 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); | |
992 | else if (HAS_PCH_SPLIT(dev_priv)) | |
993 | reg = TVIDEO_DIP_GCP(crtc->pipe); | |
994 | else | |
995 | return; | |
996 | ||
997 | crtc_state->infoframes.gcp = I915_READ(reg); | |
998 | } | |
999 | ||
fbf08556 VS |
1000 | static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, |
1001 | struct intel_crtc_state *crtc_state, | |
1002 | struct drm_connector_state *conn_state) | |
1003 | { | |
1004 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1005 | ||
1006 | if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) | |
1007 | return; | |
1008 | ||
1009 | crtc_state->infoframes.enable |= | |
1010 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); | |
1011 | ||
05d9c878 CT |
1012 | /* Indicate color indication for deep color mode */ |
1013 | if (crtc_state->pipe_bpp > 24) | |
fbf08556 | 1014 | crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; |
6d67415f | 1015 | |
12aa3290 | 1016 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
1017 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
1018 | &crtc_state->base.adjusted_mode)) | |
fbf08556 | 1019 | crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; |
6d67415f VS |
1020 | } |
1021 | ||
790ea70c | 1022 | static void ibx_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1023 | bool enable, |
ac240288 ML |
1024 | const struct intel_crtc_state *crtc_state, |
1025 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1026 | { |
790ea70c | 1027 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1028 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1029 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
69fde0a6 | 1030 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 1031 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 1032 | u32 val = I915_READ(reg); |
790ea70c | 1033 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 1034 | |
afba0188 DV |
1035 | assert_hdmi_port_disabled(intel_hdmi); |
1036 | ||
0c14c7f9 PZ |
1037 | /* See the big comment in g4x_set_infoframes() */ |
1038 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1039 | ||
6897b4b5 | 1040 | if (!enable) { |
0c14c7f9 PZ |
1041 | if (!(val & VIDEO_DIP_ENABLE)) |
1042 | return; | |
0be6f0c8 VS |
1043 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1044 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1045 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1046 | I915_WRITE(reg, val); |
9d9740f0 | 1047 | POSTING_READ(reg); |
0c14c7f9 PZ |
1048 | return; |
1049 | } | |
1050 | ||
72b78c9d | 1051 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
1052 | WARN(val & VIDEO_DIP_ENABLE, |
1053 | "DIP already enabled on port %c\n", | |
1054 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
1055 | val &= ~VIDEO_DIP_PORT_MASK; |
1056 | val |= port; | |
1057 | } | |
1058 | ||
822974ae | 1059 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1060 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1061 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1062 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1063 | |
ac240288 | 1064 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1065 | val |= VIDEO_DIP_ENABLE_GCP; |
1066 | ||
f278d972 | 1067 | I915_WRITE(reg, val); |
9d9740f0 | 1068 | POSTING_READ(reg); |
f278d972 | 1069 | |
fbf08556 VS |
1070 | intel_write_infoframe(encoder, crtc_state, |
1071 | HDMI_INFOFRAME_TYPE_AVI, | |
1072 | &crtc_state->infoframes.avi); | |
1073 | intel_write_infoframe(encoder, crtc_state, | |
1074 | HDMI_INFOFRAME_TYPE_SPD, | |
1075 | &crtc_state->infoframes.spd); | |
1076 | intel_write_infoframe(encoder, crtc_state, | |
1077 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1078 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1079 | } |
1080 | ||
790ea70c | 1081 | static void cpt_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1082 | bool enable, |
ac240288 ML |
1083 | const struct intel_crtc_state *crtc_state, |
1084 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1085 | { |
790ea70c | 1086 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1087 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1088 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 1089 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
1090 | u32 val = I915_READ(reg); |
1091 | ||
afba0188 DV |
1092 | assert_hdmi_port_disabled(intel_hdmi); |
1093 | ||
0c14c7f9 PZ |
1094 | /* See the big comment in g4x_set_infoframes() */ |
1095 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1096 | ||
6897b4b5 | 1097 | if (!enable) { |
0c14c7f9 PZ |
1098 | if (!(val & VIDEO_DIP_ENABLE)) |
1099 | return; | |
0be6f0c8 VS |
1100 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1101 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1102 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1103 | I915_WRITE(reg, val); |
9d9740f0 | 1104 | POSTING_READ(reg); |
0c14c7f9 PZ |
1105 | return; |
1106 | } | |
1107 | ||
822974ae PZ |
1108 | /* Set both together, unset both together: see the spec. */ |
1109 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 1110 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 1111 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 1112 | |
ac240288 | 1113 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1114 | val |= VIDEO_DIP_ENABLE_GCP; |
1115 | ||
822974ae | 1116 | I915_WRITE(reg, val); |
9d9740f0 | 1117 | POSTING_READ(reg); |
822974ae | 1118 | |
fbf08556 VS |
1119 | intel_write_infoframe(encoder, crtc_state, |
1120 | HDMI_INFOFRAME_TYPE_AVI, | |
1121 | &crtc_state->infoframes.avi); | |
1122 | intel_write_infoframe(encoder, crtc_state, | |
1123 | HDMI_INFOFRAME_TYPE_SPD, | |
1124 | &crtc_state->infoframes.spd); | |
1125 | intel_write_infoframe(encoder, crtc_state, | |
1126 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1127 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1128 | } |
1129 | ||
790ea70c | 1130 | static void vlv_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1131 | bool enable, |
ac240288 ML |
1132 | const struct intel_crtc_state *crtc_state, |
1133 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1134 | { |
790ea70c | 1135 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1136 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1137 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 1138 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 1139 | u32 val = I915_READ(reg); |
790ea70c | 1140 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 1141 | |
afba0188 DV |
1142 | assert_hdmi_port_disabled(intel_hdmi); |
1143 | ||
0c14c7f9 PZ |
1144 | /* See the big comment in g4x_set_infoframes() */ |
1145 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1146 | ||
6897b4b5 | 1147 | if (!enable) { |
0c14c7f9 PZ |
1148 | if (!(val & VIDEO_DIP_ENABLE)) |
1149 | return; | |
0be6f0c8 VS |
1150 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1151 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1152 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1153 | I915_WRITE(reg, val); |
9d9740f0 | 1154 | POSTING_READ(reg); |
0c14c7f9 PZ |
1155 | return; |
1156 | } | |
1157 | ||
6a2b8021 | 1158 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
1159 | WARN(val & VIDEO_DIP_ENABLE, |
1160 | "DIP already enabled on port %c\n", | |
1161 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
1162 | val &= ~VIDEO_DIP_PORT_MASK; |
1163 | val |= port; | |
1164 | } | |
1165 | ||
822974ae | 1166 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1167 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1168 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1169 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1170 | |
ac240288 | 1171 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1172 | val |= VIDEO_DIP_ENABLE_GCP; |
1173 | ||
822974ae | 1174 | I915_WRITE(reg, val); |
9d9740f0 | 1175 | POSTING_READ(reg); |
822974ae | 1176 | |
fbf08556 VS |
1177 | intel_write_infoframe(encoder, crtc_state, |
1178 | HDMI_INFOFRAME_TYPE_AVI, | |
1179 | &crtc_state->infoframes.avi); | |
1180 | intel_write_infoframe(encoder, crtc_state, | |
1181 | HDMI_INFOFRAME_TYPE_SPD, | |
1182 | &crtc_state->infoframes.spd); | |
1183 | intel_write_infoframe(encoder, crtc_state, | |
1184 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1185 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1186 | } |
1187 | ||
790ea70c | 1188 | static void hsw_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1189 | bool enable, |
ac240288 ML |
1190 | const struct intel_crtc_state *crtc_state, |
1191 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1192 | { |
790ea70c | 1193 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1194 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 1195 | u32 val = I915_READ(reg); |
0c14c7f9 | 1196 | |
8fc0aa6e ID |
1197 | assert_hdmi_transcoder_func_disabled(dev_priv, |
1198 | crtc_state->cpu_transcoder); | |
afba0188 | 1199 | |
0be6f0c8 VS |
1200 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
1201 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
44b42ebf VS |
1202 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | |
1203 | VIDEO_DIP_ENABLE_DRM_GLK); | |
0be6f0c8 | 1204 | |
6897b4b5 | 1205 | if (!enable) { |
0be6f0c8 | 1206 | I915_WRITE(reg, val); |
9d9740f0 | 1207 | POSTING_READ(reg); |
0c14c7f9 PZ |
1208 | return; |
1209 | } | |
1210 | ||
ac240288 | 1211 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1212 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
1213 | ||
0dd87d20 | 1214 | I915_WRITE(reg, val); |
9d9740f0 | 1215 | POSTING_READ(reg); |
0dd87d20 | 1216 | |
fbf08556 VS |
1217 | intel_write_infoframe(encoder, crtc_state, |
1218 | HDMI_INFOFRAME_TYPE_AVI, | |
1219 | &crtc_state->infoframes.avi); | |
1220 | intel_write_infoframe(encoder, crtc_state, | |
1221 | HDMI_INFOFRAME_TYPE_SPD, | |
1222 | &crtc_state->infoframes.spd); | |
1223 | intel_write_infoframe(encoder, crtc_state, | |
1224 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1225 | &crtc_state->infoframes.hdmi); | |
5a0200f6 US |
1226 | intel_write_infoframe(encoder, crtc_state, |
1227 | HDMI_INFOFRAME_TYPE_DRM, | |
1228 | &crtc_state->infoframes.drm); | |
687f4d06 PZ |
1229 | } |
1230 | ||
b2ccb822 VS |
1231 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
1232 | { | |
1233 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
1234 | struct i2c_adapter *adapter = | |
1235 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1236 | ||
1237 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
1238 | return; | |
1239 | ||
1240 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
1241 | enable ? "Enabling" : "Disabling"); | |
1242 | ||
1243 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
1244 | adapter, enable); | |
1245 | } | |
1246 | ||
2320175f SP |
1247 | static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, |
1248 | unsigned int offset, void *buffer, size_t size) | |
1249 | { | |
1250 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1251 | struct drm_i915_private *dev_priv = | |
1252 | intel_dig_port->base.base.dev->dev_private; | |
1253 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1254 | hdmi->ddc_bus); | |
1255 | int ret; | |
1256 | u8 start = offset & 0xff; | |
1257 | struct i2c_msg msgs[] = { | |
1258 | { | |
1259 | .addr = DRM_HDCP_DDC_ADDR, | |
1260 | .flags = 0, | |
1261 | .len = 1, | |
1262 | .buf = &start, | |
1263 | }, | |
1264 | { | |
1265 | .addr = DRM_HDCP_DDC_ADDR, | |
1266 | .flags = I2C_M_RD, | |
1267 | .len = size, | |
1268 | .buf = buffer | |
1269 | } | |
1270 | }; | |
1271 | ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); | |
1272 | if (ret == ARRAY_SIZE(msgs)) | |
1273 | return 0; | |
1274 | return ret >= 0 ? -EIO : ret; | |
1275 | } | |
1276 | ||
1277 | static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, | |
1278 | unsigned int offset, void *buffer, size_t size) | |
1279 | { | |
1280 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1281 | struct drm_i915_private *dev_priv = | |
1282 | intel_dig_port->base.base.dev->dev_private; | |
1283 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1284 | hdmi->ddc_bus); | |
1285 | int ret; | |
1286 | u8 *write_buf; | |
1287 | struct i2c_msg msg; | |
1288 | ||
1289 | write_buf = kzalloc(size + 1, GFP_KERNEL); | |
1290 | if (!write_buf) | |
1291 | return -ENOMEM; | |
1292 | ||
1293 | write_buf[0] = offset & 0xff; | |
1294 | memcpy(&write_buf[1], buffer, size); | |
1295 | ||
1296 | msg.addr = DRM_HDCP_DDC_ADDR; | |
1297 | msg.flags = 0, | |
1298 | msg.len = size + 1, | |
1299 | msg.buf = write_buf; | |
1300 | ||
1301 | ret = i2c_transfer(adapter, &msg, 1); | |
1302 | if (ret == 1) | |
1b1b1162 RV |
1303 | ret = 0; |
1304 | else if (ret >= 0) | |
1305 | ret = -EIO; | |
1306 | ||
1307 | kfree(write_buf); | |
1308 | return ret; | |
2320175f SP |
1309 | } |
1310 | ||
1311 | static | |
1312 | int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
1313 | u8 *an) | |
1314 | { | |
1315 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1316 | struct drm_i915_private *dev_priv = | |
1317 | intel_dig_port->base.base.dev->dev_private; | |
1318 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1319 | hdmi->ddc_bus); | |
1320 | int ret; | |
1321 | ||
1322 | ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, | |
1323 | DRM_HDCP_AN_LEN); | |
1324 | if (ret) { | |
3aae21fc | 1325 | DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); |
2320175f SP |
1326 | return ret; |
1327 | } | |
1328 | ||
1329 | ret = intel_gmbus_output_aksv(adapter); | |
1330 | if (ret < 0) { | |
3aae21fc | 1331 | DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); |
2320175f SP |
1332 | return ret; |
1333 | } | |
1334 | return 0; | |
1335 | } | |
1336 | ||
1337 | static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
1338 | u8 *bksv) | |
1339 | { | |
1340 | int ret; | |
1341 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, | |
1342 | DRM_HDCP_KSV_LEN); | |
1343 | if (ret) | |
3aae21fc | 1344 | DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); |
2320175f SP |
1345 | return ret; |
1346 | } | |
1347 | ||
1348 | static | |
1349 | int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
1350 | u8 *bstatus) | |
1351 | { | |
1352 | int ret; | |
1353 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, | |
1354 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
1355 | if (ret) | |
3aae21fc | 1356 | DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); |
2320175f SP |
1357 | return ret; |
1358 | } | |
1359 | ||
1360 | static | |
1361 | int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
1362 | bool *repeater_present) | |
1363 | { | |
1364 | int ret; | |
1365 | u8 val; | |
1366 | ||
1367 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1368 | if (ret) { | |
3aae21fc | 1369 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1370 | return ret; |
1371 | } | |
1372 | *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; | |
1373 | return 0; | |
1374 | } | |
1375 | ||
1376 | static | |
1377 | int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
1378 | u8 *ri_prime) | |
1379 | { | |
1380 | int ret; | |
1381 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, | |
1382 | ri_prime, DRM_HDCP_RI_LEN); | |
1383 | if (ret) | |
3aae21fc | 1384 | DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); |
2320175f SP |
1385 | return ret; |
1386 | } | |
1387 | ||
1388 | static | |
1389 | int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
1390 | bool *ksv_ready) | |
1391 | { | |
1392 | int ret; | |
1393 | u8 val; | |
1394 | ||
1395 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1396 | if (ret) { | |
3aae21fc | 1397 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1398 | return ret; |
1399 | } | |
1400 | *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; | |
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | static | |
1405 | int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
1406 | int num_downstream, u8 *ksv_fifo) | |
1407 | { | |
1408 | int ret; | |
1409 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, | |
1410 | ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); | |
1411 | if (ret) { | |
3aae21fc | 1412 | DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); |
2320175f SP |
1413 | return ret; |
1414 | } | |
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | static | |
1419 | int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
1420 | int i, u32 *part) | |
1421 | { | |
1422 | int ret; | |
1423 | ||
1424 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
1425 | return -EINVAL; | |
1426 | ||
1427 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), | |
1428 | part, DRM_HDCP_V_PRIME_PART_LEN); | |
1429 | if (ret) | |
3aae21fc | 1430 | DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); |
2320175f SP |
1431 | return ret; |
1432 | } | |
1433 | ||
7412826c R |
1434 | static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) |
1435 | { | |
1436 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
1437 | struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); | |
1438 | struct drm_crtc *crtc = connector->base.state->crtc; | |
1439 | struct intel_crtc *intel_crtc = container_of(crtc, | |
1440 | struct intel_crtc, base); | |
1441 | u32 scanline; | |
1442 | int ret; | |
1443 | ||
1444 | for (;;) { | |
1445 | scanline = I915_READ(PIPEDSL(intel_crtc->pipe)); | |
1446 | if (scanline > 100 && scanline < 200) | |
1447 | break; | |
1448 | usleep_range(25, 50); | |
1449 | } | |
1450 | ||
1451 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); | |
1452 | if (ret) { | |
1453 | DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret); | |
1454 | return ret; | |
1455 | } | |
1456 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); | |
1457 | if (ret) { | |
1458 | DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret); | |
1459 | return ret; | |
1460 | } | |
1461 | ||
1462 | return 0; | |
1463 | } | |
1464 | ||
2320175f SP |
1465 | static |
1466 | int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
1467 | bool enable) | |
1468 | { | |
7412826c R |
1469 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; |
1470 | struct intel_connector *connector = hdmi->attached_connector; | |
1471 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
2320175f SP |
1472 | int ret; |
1473 | ||
1474 | if (!enable) | |
1475 | usleep_range(6, 60); /* Bspec says >= 6us */ | |
1476 | ||
1477 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); | |
1478 | if (ret) { | |
1479 | DRM_ERROR("%s HDCP signalling failed (%d)\n", | |
1480 | enable ? "Enable" : "Disable", ret); | |
1481 | return ret; | |
1482 | } | |
7412826c R |
1483 | |
1484 | /* | |
1485 | * WA: To fix incorrect positioning of the window of | |
1486 | * opportunity and enc_en signalling in KABYLAKE. | |
1487 | */ | |
1488 | if (IS_KABYLAKE(dev_priv) && enable) | |
1489 | return kbl_repositioning_enc_en_signal(connector); | |
1490 | ||
2320175f SP |
1491 | return 0; |
1492 | } | |
1493 | ||
1494 | static | |
1495 | bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
1496 | { | |
1497 | struct drm_i915_private *dev_priv = | |
1498 | intel_dig_port->base.base.dev->dev_private; | |
69205931 R |
1499 | struct intel_connector *connector = |
1500 | intel_dig_port->hdmi.attached_connector; | |
2320175f | 1501 | enum port port = intel_dig_port->base.port; |
69205931 | 1502 | enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; |
2320175f SP |
1503 | int ret; |
1504 | union { | |
1505 | u32 reg; | |
1506 | u8 shim[DRM_HDCP_RI_LEN]; | |
1507 | } ri; | |
1508 | ||
1509 | ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); | |
1510 | if (ret) | |
1511 | return false; | |
1512 | ||
69205931 | 1513 | I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg); |
2320175f SP |
1514 | |
1515 | /* Wait for Ri prime match */ | |
69205931 | 1516 | if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) & |
2320175f SP |
1517 | (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { |
1518 | DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", | |
69205931 R |
1519 | I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, |
1520 | port))); | |
2320175f SP |
1521 | return false; |
1522 | } | |
1523 | return true; | |
1524 | } | |
1525 | ||
032048db | 1526 | struct hdcp2_hdmi_msg_data { |
2d4254e5 R |
1527 | u8 msg_id; |
1528 | u32 timeout; | |
1529 | u32 timeout2; | |
032048db JN |
1530 | }; |
1531 | ||
e63eacf7 | 1532 | static const struct hdcp2_hdmi_msg_data hdcp2_msg_data[] = { |
032048db JN |
1533 | { HDCP_2_2_AKE_INIT, 0, 0 }, |
1534 | { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0 }, | |
1535 | { HDCP_2_2_AKE_NO_STORED_KM, 0, 0 }, | |
1536 | { HDCP_2_2_AKE_STORED_KM, 0, 0 }, | |
1537 | { HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, | |
1538 | HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS }, | |
1539 | { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, 0 }, | |
1540 | { HDCP_2_2_LC_INIT, 0, 0 }, | |
1541 | { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0 }, | |
1542 | { HDCP_2_2_SKE_SEND_EKS, 0, 0 }, | |
1543 | { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 }, | |
1544 | { HDCP_2_2_REP_SEND_ACK, 0, 0 }, | |
1545 | { HDCP_2_2_REP_STREAM_MANAGE, 0, 0 }, | |
1546 | { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 }, | |
1547 | }; | |
2d4254e5 R |
1548 | |
1549 | static | |
1550 | int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, | |
126d0a94 | 1551 | u8 *rx_status) |
2d4254e5 R |
1552 | { |
1553 | return intel_hdmi_hdcp_read(intel_dig_port, | |
1554 | HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, | |
1555 | rx_status, | |
1556 | HDCP_2_2_HDMI_RXSTATUS_LEN); | |
1557 | } | |
1558 | ||
1559 | static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) | |
1560 | { | |
1561 | int i; | |
1562 | ||
1563 | for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++) | |
1564 | if (hdcp2_msg_data[i].msg_id == msg_id && | |
1565 | (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired)) | |
1566 | return hdcp2_msg_data[i].timeout; | |
1567 | else if (hdcp2_msg_data[i].msg_id == msg_id) | |
1568 | return hdcp2_msg_data[i].timeout2; | |
1569 | ||
1570 | return -EINVAL; | |
1571 | } | |
1572 | ||
1573 | static inline | |
1574 | int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port, | |
1575 | u8 msg_id, bool *msg_ready, | |
1576 | ssize_t *msg_sz) | |
1577 | { | |
1578 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1579 | int ret; | |
1580 | ||
1581 | ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status); | |
1582 | if (ret < 0) { | |
1583 | DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret); | |
1584 | return ret; | |
1585 | } | |
1586 | ||
1587 | *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | | |
1588 | rx_status[0]); | |
1589 | ||
1590 | if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) | |
1591 | *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && | |
1592 | *msg_sz); | |
1593 | else | |
1594 | *msg_ready = *msg_sz; | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | static ssize_t | |
1600 | intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, | |
1601 | u8 msg_id, bool paired) | |
1602 | { | |
1603 | bool msg_ready = false; | |
1604 | int timeout, ret; | |
1605 | ssize_t msg_sz = 0; | |
1606 | ||
1607 | timeout = get_hdcp2_msg_timeout(msg_id, paired); | |
1608 | if (timeout < 0) | |
1609 | return timeout; | |
1610 | ||
1611 | ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, | |
1612 | msg_id, &msg_ready, | |
1613 | &msg_sz), | |
1614 | !ret && msg_ready && msg_sz, timeout * 1000, | |
1615 | 1000, 5 * 1000); | |
1616 | if (ret) | |
1617 | DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n", | |
1618 | msg_id, ret, timeout); | |
1619 | ||
1620 | return ret ? ret : msg_sz; | |
1621 | } | |
1622 | ||
1623 | static | |
1624 | int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, | |
1625 | void *buf, size_t size) | |
1626 | { | |
1627 | unsigned int offset; | |
1628 | ||
1629 | offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; | |
1630 | return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); | |
1631 | } | |
1632 | ||
1633 | static | |
1634 | int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, | |
1635 | u8 msg_id, void *buf, size_t size) | |
1636 | { | |
1637 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1638 | struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; | |
1639 | unsigned int offset; | |
1640 | ssize_t ret; | |
1641 | ||
1642 | ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, | |
1643 | hdcp->is_paired); | |
1644 | if (ret < 0) | |
1645 | return ret; | |
1646 | ||
1647 | /* | |
1648 | * Available msg size should be equal to or lesser than the | |
1649 | * available buffer. | |
1650 | */ | |
1651 | if (ret > size) { | |
1652 | DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n", | |
1653 | ret, size); | |
1654 | return -1; | |
1655 | } | |
1656 | ||
1657 | offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; | |
1658 | ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); | |
1659 | if (ret) | |
1660 | DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret); | |
1661 | ||
1662 | return ret; | |
1663 | } | |
1664 | ||
1665 | static | |
1666 | int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) | |
1667 | { | |
1668 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1669 | int ret; | |
1670 | ||
1671 | ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); | |
1672 | if (ret) | |
1673 | return ret; | |
1674 | ||
1675 | /* | |
1676 | * Re-auth request and Link Integrity Failures are represented by | |
1677 | * same bit. i.e reauth_req. | |
1678 | */ | |
1679 | if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) | |
1680 | ret = HDCP_REAUTH_REQUEST; | |
1681 | else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) | |
1682 | ret = HDCP_TOPOLOGY_CHANGE; | |
1683 | ||
1684 | return ret; | |
1685 | } | |
1686 | ||
1687 | static | |
1688 | int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, | |
1689 | bool *capable) | |
1690 | { | |
1691 | u8 hdcp2_version; | |
1692 | int ret; | |
1693 | ||
1694 | *capable = false; | |
1695 | ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, | |
1696 | &hdcp2_version, sizeof(hdcp2_version)); | |
1697 | if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) | |
1698 | *capable = true; | |
1699 | ||
1700 | return ret; | |
1701 | } | |
1702 | ||
1703 | static inline | |
1704 | enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void) | |
1705 | { | |
1706 | return HDCP_PROTOCOL_HDMI; | |
1707 | } | |
1708 | ||
2320175f SP |
1709 | static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { |
1710 | .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, | |
1711 | .read_bksv = intel_hdmi_hdcp_read_bksv, | |
1712 | .read_bstatus = intel_hdmi_hdcp_read_bstatus, | |
1713 | .repeater_present = intel_hdmi_hdcp_repeater_present, | |
1714 | .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, | |
1715 | .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, | |
1716 | .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, | |
1717 | .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, | |
1718 | .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, | |
1719 | .check_link = intel_hdmi_hdcp_check_link, | |
2d4254e5 R |
1720 | .write_2_2_msg = intel_hdmi_hdcp2_write_msg, |
1721 | .read_2_2_msg = intel_hdmi_hdcp2_read_msg, | |
1722 | .check_2_2_link = intel_hdmi_hdcp2_check_link, | |
1723 | .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, | |
1724 | .protocol = HDCP_PROTOCOL_HDMI, | |
2320175f SP |
1725 | }; |
1726 | ||
ac240288 ML |
1727 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
1728 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 1729 | { |
c59423a3 | 1730 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1731 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1732 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 1733 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 1734 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 1735 | u32 hdmi_val; |
7d57382e | 1736 | |
b2ccb822 VS |
1737 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
1738 | ||
b242b7f7 | 1739 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 1740 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 1741 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 1742 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 1743 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 1744 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 1745 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 1746 | |
ac240288 | 1747 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 1748 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 1749 | else |
4f3a8bc7 | 1750 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 1751 | |
ac240288 | 1752 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 1753 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 1754 | |
6e266956 | 1755 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 1756 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 1757 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1758 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 1759 | else |
c59423a3 | 1760 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 1761 | |
b242b7f7 PZ |
1762 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
1763 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
1764 | } |
1765 | ||
85234cdc DV |
1766 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
1767 | enum pipe *pipe) | |
7d57382e | 1768 | { |
76203467 | 1769 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
85234cdc | 1770 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
0e6e0be4 | 1771 | intel_wakeref_t wakeref; |
5b092174 | 1772 | bool ret; |
85234cdc | 1773 | |
0e6e0be4 CW |
1774 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
1775 | encoder->power_domain); | |
1776 | if (!wakeref) | |
6d129bea ID |
1777 | return false; |
1778 | ||
76203467 | 1779 | ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); |
5b092174 | 1780 | |
0e6e0be4 | 1781 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
5b092174 ID |
1782 | |
1783 | return ret; | |
85234cdc DV |
1784 | } |
1785 | ||
045ac3b5 | 1786 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 1787 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
1788 | { |
1789 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca | 1790 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1791 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 1792 | u32 tmp, flags = 0; |
18442d08 | 1793 | int dotclock; |
045ac3b5 | 1794 | |
e1214b95 VS |
1795 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); |
1796 | ||
045ac3b5 JB |
1797 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
1798 | ||
1799 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
1800 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1801 | else | |
1802 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1803 | ||
1804 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
1805 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1806 | else | |
1807 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1808 | ||
6897b4b5 DV |
1809 | if (tmp & HDMI_MODE_SELECT_HDMI) |
1810 | pipe_config->has_hdmi_sink = true; | |
1811 | ||
e5e70d4a VS |
1812 | pipe_config->infoframes.enable |= |
1813 | intel_hdmi_infoframes_enabled(encoder, pipe_config); | |
1814 | ||
1815 | if (pipe_config->infoframes.enable) | |
e43823ec JB |
1816 | pipe_config->has_infoframe = true; |
1817 | ||
dd6090f8 | 1818 | if (tmp & HDMI_AUDIO_ENABLE) |
9ed109a7 DV |
1819 | pipe_config->has_audio = true; |
1820 | ||
6e266956 | 1821 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
1822 | tmp & HDMI_COLOR_RANGE_16_235) |
1823 | pipe_config->limited_color_range = true; | |
1824 | ||
2d112de7 | 1825 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
1826 | |
1827 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
1828 | dotclock = pipe_config->port_clock * 2 / 3; | |
1829 | else | |
1830 | dotclock = pipe_config->port_clock; | |
1831 | ||
be69a133 VS |
1832 | if (pipe_config->pixel_multiplier) |
1833 | dotclock /= pipe_config->pixel_multiplier; | |
1834 | ||
2d112de7 | 1835 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
1836 | |
1837 | pipe_config->lane_count = 4; | |
f2a10d61 VS |
1838 | |
1839 | intel_hdmi_read_gcp_infoframe(encoder, pipe_config); | |
1840 | ||
1841 | intel_read_infoframe(encoder, pipe_config, | |
1842 | HDMI_INFOFRAME_TYPE_AVI, | |
1843 | &pipe_config->infoframes.avi); | |
1844 | intel_read_infoframe(encoder, pipe_config, | |
1845 | HDMI_INFOFRAME_TYPE_SPD, | |
1846 | &pipe_config->infoframes.spd); | |
1847 | intel_read_infoframe(encoder, pipe_config, | |
1848 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1849 | &pipe_config->infoframes.hdmi); | |
045ac3b5 JB |
1850 | } |
1851 | ||
df18e721 | 1852 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
5f88a9c6 VS |
1853 | const struct intel_crtc_state *pipe_config, |
1854 | const struct drm_connector_state *conn_state) | |
d1b1589c | 1855 | { |
ac240288 | 1856 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 1857 | |
ac240288 | 1858 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
1859 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
1860 | pipe_name(crtc->pipe)); | |
bbf35e9d | 1861 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
1862 | } |
1863 | ||
fd6bbda9 | 1864 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1865 | const struct intel_crtc_state *pipe_config, |
1866 | const struct drm_connector_state *conn_state) | |
7d57382e | 1867 | { |
5ab432ef | 1868 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1869 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1870 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1871 | u32 temp; |
1872 | ||
b242b7f7 | 1873 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1874 | |
bf868c7d | 1875 | temp |= SDVO_ENABLE; |
df18e721 | 1876 | if (pipe_config->has_audio) |
dd6090f8 | 1877 | temp |= HDMI_AUDIO_ENABLE; |
7a87c289 | 1878 | |
bf868c7d VS |
1879 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1880 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1881 | ||
df18e721 ML |
1882 | if (pipe_config->has_audio) |
1883 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1884 | } |
1885 | ||
fd6bbda9 | 1886 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1887 | const struct intel_crtc_state *pipe_config, |
1888 | const struct drm_connector_state *conn_state) | |
bf868c7d VS |
1889 | { |
1890 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1891 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1892 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1893 | u32 temp; | |
1894 | ||
1895 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1896 | |
bf868c7d | 1897 | temp |= SDVO_ENABLE; |
ac240288 | 1898 | if (pipe_config->has_audio) |
dd6090f8 | 1899 | temp |= HDMI_AUDIO_ENABLE; |
5ab432ef | 1900 | |
bf868c7d VS |
1901 | /* |
1902 | * HW workaround, need to write this twice for issue | |
1903 | * that may result in first write getting masked. | |
1904 | */ | |
1905 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1906 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1907 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1908 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1909 | |
bf868c7d VS |
1910 | /* |
1911 | * HW workaround, need to toggle enable bit off and on | |
1912 | * for 12bpc with pixel repeat. | |
1913 | * | |
1914 | * FIXME: BSpec says this should be done at the end of | |
1915 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1916 | */ |
df18e721 ML |
1917 | if (pipe_config->pipe_bpp > 24 && |
1918 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1919 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1920 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1921 | ||
1922 | /* | |
1923 | * HW workaround, need to write this twice for issue | |
1924 | * that may result in first write getting masked. | |
1925 | */ | |
1926 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1927 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1928 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1929 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1930 | } |
c1dec79a | 1931 | |
df18e721 ML |
1932 | if (pipe_config->has_audio) |
1933 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1934 | } |
1935 | ||
fd6bbda9 | 1936 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1937 | const struct intel_crtc_state *pipe_config, |
1938 | const struct drm_connector_state *conn_state) | |
d1b1589c VS |
1939 | { |
1940 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1941 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1942 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1943 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1944 | enum pipe pipe = crtc->pipe; | |
1945 | u32 temp; | |
1946 | ||
1947 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1948 | ||
1949 | temp |= SDVO_ENABLE; | |
df18e721 | 1950 | if (pipe_config->has_audio) |
dd6090f8 | 1951 | temp |= HDMI_AUDIO_ENABLE; |
d1b1589c VS |
1952 | |
1953 | /* | |
1954 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1955 | * | |
1956 | * The procedure for 12bpc is as follows: | |
1957 | * 1. disable HDMI clock gating | |
1958 | * 2. enable HDMI with 8bpc | |
1959 | * 3. enable HDMI with 12bpc | |
1960 | * 4. enable HDMI clock gating | |
1961 | */ | |
1962 | ||
df18e721 | 1963 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1964 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1965 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1966 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1967 | ||
1968 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1969 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1970 | } |
d1b1589c VS |
1971 | |
1972 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1973 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1974 | ||
df18e721 | 1975 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1976 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1977 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1978 | ||
1979 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1980 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1981 | ||
1982 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1983 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1984 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1985 | } | |
1986 | ||
df18e721 ML |
1987 | if (pipe_config->has_audio) |
1988 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1989 | } |
89b667f8 | 1990 | |
fd6bbda9 | 1991 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1992 | const struct intel_crtc_state *pipe_config, |
1993 | const struct drm_connector_state *conn_state) | |
b76cf76b | 1994 | { |
5ab432ef DV |
1995 | } |
1996 | ||
fd6bbda9 | 1997 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1998 | const struct intel_crtc_state *old_crtc_state, |
1999 | const struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
2000 | { |
2001 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2002 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 2003 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f99be1b3 VS |
2004 | struct intel_digital_port *intel_dig_port = |
2005 | hdmi_to_dig_port(intel_hdmi); | |
ac240288 | 2006 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 2007 | u32 temp; |
5ab432ef | 2008 | |
b242b7f7 | 2009 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 2010 | |
dd6090f8 | 2011 | temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); |
b242b7f7 PZ |
2012 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
2013 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
2014 | |
2015 | /* | |
2016 | * HW workaround for IBX, we need to move the port | |
2017 | * to transcoder A after disabling it to allow the | |
2018 | * matching DP port to be enabled on transcoder A. | |
2019 | */ | |
6e266956 | 2020 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
2021 | /* |
2022 | * We get CPU/PCH FIFO underruns on the other pipe when | |
2023 | * doing the workaround. Sweep them under the rug. | |
2024 | */ | |
2025 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
2026 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
2027 | ||
76203467 VS |
2028 | temp &= ~SDVO_PIPE_SEL_MASK; |
2029 | temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); | |
1612c8bd VS |
2030 | /* |
2031 | * HW workaround, need to write this twice for issue | |
2032 | * that may result in first write getting masked. | |
2033 | */ | |
2034 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
2035 | POSTING_READ(intel_hdmi->hdmi_reg); | |
2036 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
2037 | POSTING_READ(intel_hdmi->hdmi_reg); | |
2038 | ||
2039 | temp &= ~SDVO_ENABLE; | |
2040 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
2041 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 2042 | |
0f0f74bc | 2043 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
2044 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
2045 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 2046 | } |
6d67415f | 2047 | |
790ea70c VS |
2048 | intel_dig_port->set_infoframes(encoder, |
2049 | false, | |
f99be1b3 | 2050 | old_crtc_state, old_conn_state); |
b2ccb822 VS |
2051 | |
2052 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
2053 | } |
2054 | ||
fd6bbda9 | 2055 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2056 | const struct intel_crtc_state *old_crtc_state, |
2057 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2058 | { |
df18e721 | 2059 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2060 | intel_audio_codec_disable(encoder, |
2061 | old_crtc_state, old_conn_state); | |
a4790cec | 2062 | |
fd6bbda9 | 2063 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2064 | } |
2065 | ||
fd6bbda9 | 2066 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2067 | const struct intel_crtc_state *old_crtc_state, |
2068 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2069 | { |
df18e721 | 2070 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2071 | intel_audio_codec_disable(encoder, |
2072 | old_crtc_state, old_conn_state); | |
a4790cec VS |
2073 | } |
2074 | ||
fd6bbda9 | 2075 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2076 | const struct intel_crtc_state *old_crtc_state, |
2077 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2078 | { |
fd6bbda9 | 2079 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2080 | } |
2081 | ||
d6038611 | 2082 | static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) |
7d148ef5 | 2083 | { |
d6038611 VS |
2084 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2085 | const struct ddi_vbt_port_info *info = | |
2086 | &dev_priv->vbt.ddi_port_info[encoder->port]; | |
2087 | int max_tmds_clock; | |
2088 | ||
9672a69c | 2089 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
d6038611 VS |
2090 | max_tmds_clock = 594000; |
2091 | else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) | |
2092 | max_tmds_clock = 300000; | |
2093 | else if (INTEL_GEN(dev_priv) >= 5) | |
2094 | max_tmds_clock = 225000; | |
7d148ef5 | 2095 | else |
d6038611 VS |
2096 | max_tmds_clock = 165000; |
2097 | ||
2098 | if (info->max_tmds_clock) | |
2099 | max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); | |
2100 | ||
2101 | return max_tmds_clock; | |
7d148ef5 DV |
2102 | } |
2103 | ||
b1ba124d | 2104 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f ML |
2105 | bool respect_downstream_limits, |
2106 | bool force_dvi) | |
b1ba124d | 2107 | { |
d6038611 VS |
2108 | struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; |
2109 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); | |
b1ba124d VS |
2110 | |
2111 | if (respect_downstream_limits) { | |
8cadab0a VS |
2112 | struct intel_connector *connector = hdmi->attached_connector; |
2113 | const struct drm_display_info *info = &connector->base.display_info; | |
2114 | ||
b1ba124d VS |
2115 | if (hdmi->dp_dual_mode.max_tmds_clock) |
2116 | max_tmds_clock = min(max_tmds_clock, | |
2117 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
2118 | |
2119 | if (info->max_tmds_clock) | |
2120 | max_tmds_clock = min(max_tmds_clock, | |
2121 | info->max_tmds_clock); | |
7a5ca19f | 2122 | else if (!hdmi->has_hdmi_sink || force_dvi) |
b1ba124d VS |
2123 | max_tmds_clock = min(max_tmds_clock, 165000); |
2124 | } | |
2125 | ||
2126 | return max_tmds_clock; | |
2127 | } | |
2128 | ||
e64e739e VS |
2129 | static enum drm_mode_status |
2130 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f ML |
2131 | int clock, bool respect_downstream_limits, |
2132 | bool force_dvi) | |
e64e739e | 2133 | { |
e2d214ae | 2134 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
2135 | |
2136 | if (clock < 25000) | |
2137 | return MODE_CLOCK_LOW; | |
7a5ca19f | 2138 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) |
e64e739e VS |
2139 | return MODE_CLOCK_HIGH; |
2140 | ||
5e6ccc0b | 2141 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 2142 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
2143 | return MODE_CLOCK_RANGE; |
2144 | ||
2145 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 2146 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
2147 | return MODE_CLOCK_RANGE; |
2148 | ||
2149 | return MODE_OK; | |
2150 | } | |
2151 | ||
c19de8eb DL |
2152 | static enum drm_mode_status |
2153 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
2154 | struct drm_display_mode *mode) | |
7d57382e | 2155 | { |
e64e739e VS |
2156 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
2157 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 2158 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
2159 | enum drm_mode_status status; |
2160 | int clock; | |
587bf496 | 2161 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
7a5ca19f ML |
2162 | bool force_dvi = |
2163 | READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; | |
e64e739e | 2164 | |
e4dd27aa VS |
2165 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
2166 | return MODE_NO_DBLESCAN; | |
2167 | ||
e64e739e | 2168 | clock = mode->clock; |
587bf496 MK |
2169 | |
2170 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
2171 | clock *= 2; | |
2172 | ||
2173 | if (clock > max_dotclk) | |
2174 | return MODE_CLOCK_HIGH; | |
2175 | ||
697c4078 CT |
2176 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
2177 | clock *= 2; | |
2178 | ||
b22ca995 SS |
2179 | if (drm_mode_is_420_only(&connector->display_info, mode)) |
2180 | clock /= 2; | |
2181 | ||
e64e739e | 2182 | /* check if we can do 8bpc */ |
7a5ca19f | 2183 | status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); |
7d57382e | 2184 | |
cd9e11a8 RS |
2185 | if (hdmi->has_hdmi_sink && !force_dvi) { |
2186 | /* if we can't do 8bpc we may still be able to do 12bpc */ | |
b2ae318a | 2187 | if (status != MODE_OK && !HAS_GMCH(dev_priv)) |
cd9e11a8 RS |
2188 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, |
2189 | true, force_dvi); | |
2190 | ||
2191 | /* if we can't do 8,12bpc we may still be able to do 10bpc */ | |
2192 | if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) | |
2193 | status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, | |
2194 | true, force_dvi); | |
2195 | } | |
2d20411e VS |
2196 | if (status != MODE_OK) |
2197 | return status; | |
7d57382e | 2198 | |
2d20411e | 2199 | return intel_mode_valid_max_plane_size(dev_priv, mode); |
7d57382e EA |
2200 | } |
2201 | ||
cd9e11a8 RS |
2202 | static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, |
2203 | int bpc) | |
71800632 | 2204 | { |
c750bdd3 VS |
2205 | struct drm_i915_private *dev_priv = |
2206 | to_i915(crtc_state->base.crtc->dev); | |
2207 | struct drm_atomic_state *state = crtc_state->base.state; | |
2208 | struct drm_connector_state *connector_state; | |
2209 | struct drm_connector *connector; | |
22dae8a0 RS |
2210 | const struct drm_display_mode *adjusted_mode = |
2211 | &crtc_state->base.adjusted_mode; | |
c750bdd3 | 2212 | int i; |
71800632 | 2213 | |
b2ae318a | 2214 | if (HAS_GMCH(dev_priv)) |
71800632 VS |
2215 | return false; |
2216 | ||
cd9e11a8 RS |
2217 | if (bpc == 10 && INTEL_GEN(dev_priv) < 11) |
2218 | return false; | |
2219 | ||
3fad10db | 2220 | if (crtc_state->pipe_bpp < bpc * 3) |
be33be5d VS |
2221 | return false; |
2222 | ||
2223 | if (!crtc_state->has_hdmi_sink) | |
2224 | return false; | |
2225 | ||
71800632 | 2226 | /* |
cd9e11a8 | 2227 | * HDMI deep color affects the clocks, so it's only possible |
71800632 VS |
2228 | * when not cloning with other encoder types. |
2229 | */ | |
c750bdd3 VS |
2230 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
2231 | return false; | |
2232 | ||
fe5f6b1f | 2233 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
c750bdd3 VS |
2234 | const struct drm_display_info *info = &connector->display_info; |
2235 | ||
2236 | if (connector_state->crtc != crtc_state->base.crtc) | |
2237 | continue; | |
2238 | ||
33b7f3ee | 2239 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { |
60436fd4 SS |
2240 | const struct drm_hdmi_info *hdmi = &info->hdmi; |
2241 | ||
cd9e11a8 RS |
2242 | if (bpc == 12 && !(hdmi->y420_dc_modes & |
2243 | DRM_EDID_YCBCR420_DC_36)) | |
2244 | return false; | |
2245 | else if (bpc == 10 && !(hdmi->y420_dc_modes & | |
2246 | DRM_EDID_YCBCR420_DC_30)) | |
60436fd4 SS |
2247 | return false; |
2248 | } else { | |
cd9e11a8 RS |
2249 | if (bpc == 12 && !(info->edid_hdmi_dc_modes & |
2250 | DRM_EDID_HDMI_DC_36)) | |
2251 | return false; | |
2252 | else if (bpc == 10 && !(info->edid_hdmi_dc_modes & | |
2253 | DRM_EDID_HDMI_DC_30)) | |
60436fd4 SS |
2254 | return false; |
2255 | } | |
c750bdd3 VS |
2256 | } |
2257 | ||
2abf3c0d | 2258 | /* Display WA #1139: glk */ |
cd9e11a8 | 2259 | if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && |
22dae8a0 RS |
2260 | adjusted_mode->htotal > 5460) |
2261 | return false; | |
2262 | ||
2263 | /* Display Wa_1405510057:icl */ | |
2264 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && | |
2dd24a9c | 2265 | bpc == 10 && INTEL_GEN(dev_priv) >= 11 && |
22dae8a0 RS |
2266 | (adjusted_mode->crtc_hblank_end - |
2267 | adjusted_mode->crtc_hblank_start) % 8 == 2) | |
46649d8b ACO |
2268 | return false; |
2269 | ||
c750bdd3 | 2270 | return true; |
71800632 VS |
2271 | } |
2272 | ||
60436fd4 SS |
2273 | static bool |
2274 | intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |
9e362992 | 2275 | struct intel_crtc_state *config) |
60436fd4 | 2276 | { |
e5c05931 SS |
2277 | struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); |
2278 | ||
60436fd4 SS |
2279 | if (!connector->ycbcr_420_allowed) { |
2280 | DRM_ERROR("Platform doesn't support YCBCR420 output\n"); | |
2281 | return false; | |
2282 | } | |
2283 | ||
33b7f3ee | 2284 | config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
e5c05931 SS |
2285 | |
2286 | /* YCBCR 420 output conversion needs a scaler */ | |
2287 | if (skl_update_scaler_crtc(config)) { | |
2288 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
2289 | return false; | |
2290 | } | |
2291 | ||
2292 | intel_pch_panel_fitting(intel_crtc, config, | |
2293 | DRM_MODE_SCALE_FULLSCREEN); | |
2294 | ||
60436fd4 SS |
2295 | return true; |
2296 | } | |
2297 | ||
9e362992 VS |
2298 | static int intel_hdmi_port_clock(int clock, int bpc) |
2299 | { | |
2300 | /* | |
2301 | * Need to adjust the port link by: | |
2302 | * 1.5x for 12bpc | |
2303 | * 1.25x for 10bpc | |
2304 | */ | |
2305 | return clock * bpc / 8; | |
2306 | } | |
2307 | ||
2308 | static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, | |
2309 | struct intel_crtc_state *crtc_state, | |
2310 | int clock, bool force_dvi) | |
2311 | { | |
2312 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
2313 | int bpc; | |
2314 | ||
2315 | for (bpc = 12; bpc >= 10; bpc -= 2) { | |
2316 | if (hdmi_deep_color_possible(crtc_state, bpc) && | |
2317 | hdmi_port_clock_valid(intel_hdmi, | |
2318 | intel_hdmi_port_clock(clock, bpc), | |
2319 | true, force_dvi) == MODE_OK) | |
2320 | return bpc; | |
2321 | } | |
2322 | ||
2323 | return 8; | |
2324 | } | |
2325 | ||
2326 | static int intel_hdmi_compute_clock(struct intel_encoder *encoder, | |
2327 | struct intel_crtc_state *crtc_state, | |
2328 | bool force_dvi) | |
2329 | { | |
2330 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
2331 | const struct drm_display_mode *adjusted_mode = | |
2332 | &crtc_state->base.adjusted_mode; | |
2333 | int bpc, clock = adjusted_mode->crtc_clock; | |
2334 | ||
2335 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) | |
2336 | clock *= 2; | |
2337 | ||
2338 | /* YCBCR420 TMDS rate requirement is half the pixel clock */ | |
2339 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
2340 | clock /= 2; | |
2341 | ||
2342 | bpc = intel_hdmi_compute_bpc(encoder, crtc_state, | |
2343 | clock, force_dvi); | |
2344 | ||
2345 | crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); | |
2346 | ||
2347 | /* | |
2348 | * pipe_bpp could already be below 8bpc due to | |
2349 | * FDI bandwidth constraints. We shouldn't bump it | |
2350 | * back up to 8bpc in that case. | |
2351 | */ | |
2352 | if (crtc_state->pipe_bpp > bpc * 3) | |
2353 | crtc_state->pipe_bpp = bpc * 3; | |
2354 | ||
2355 | DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n", | |
2356 | bpc, crtc_state->pipe_bpp); | |
2357 | ||
2358 | if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, | |
2359 | false, force_dvi) != MODE_OK) { | |
2360 | DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n", | |
2361 | crtc_state->port_clock); | |
2362 | return -EINVAL; | |
2363 | } | |
2364 | ||
2365 | return 0; | |
2366 | } | |
2367 | ||
204474a6 LP |
2368 | int intel_hdmi_compute_config(struct intel_encoder *encoder, |
2369 | struct intel_crtc_state *pipe_config, | |
2370 | struct drm_connector_state *conn_state) | |
7d57382e | 2371 | { |
5bfe2ac0 | 2372 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 2373 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 2374 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
60436fd4 SS |
2375 | struct drm_connector *connector = conn_state->connector; |
2376 | struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; | |
7a5ca19f ML |
2377 | struct intel_digital_connector_state *intel_conn_state = |
2378 | to_intel_digital_connector_state(conn_state); | |
7a5ca19f | 2379 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
9e362992 | 2380 | int ret; |
3685a8f3 | 2381 | |
e4dd27aa | 2382 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 2383 | return -EINVAL; |
e4dd27aa | 2384 | |
d9facae6 | 2385 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
7a5ca19f | 2386 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
6897b4b5 | 2387 | |
e43823ec JB |
2388 | if (pipe_config->has_hdmi_sink) |
2389 | pipe_config->has_infoframe = true; | |
2390 | ||
7a5ca19f | 2391 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db | 2392 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
0f2a2a75 VS |
2393 | pipe_config->limited_color_range = |
2394 | pipe_config->has_hdmi_sink && | |
c8127cf0 VS |
2395 | drm_default_rgb_quant_range(adjusted_mode) == |
2396 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
2397 | } else { |
2398 | pipe_config->limited_color_range = | |
7a5ca19f | 2399 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
2400 | } |
2401 | ||
9e362992 | 2402 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
697c4078 | 2403 | pipe_config->pixel_multiplier = 2; |
697c4078 | 2404 | |
60436fd4 | 2405 | if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { |
9e362992 | 2406 | if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) { |
60436fd4 | 2407 | DRM_ERROR("Can't support YCBCR420 output\n"); |
204474a6 | 2408 | return -EINVAL; |
60436fd4 SS |
2409 | } |
2410 | } | |
2411 | ||
4f8036a2 | 2412 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
2413 | pipe_config->has_pch_encoder = true; |
2414 | ||
7a5ca19f ML |
2415 | if (pipe_config->has_hdmi_sink) { |
2416 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
2417 | pipe_config->has_audio = intel_hdmi->has_audio; | |
2418 | else | |
2419 | pipe_config->has_audio = | |
2420 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
2421 | } | |
9ed109a7 | 2422 | |
9e362992 VS |
2423 | ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi); |
2424 | if (ret) | |
2425 | return ret; | |
325b9d04 | 2426 | |
28b468a0 | 2427 | /* Set user selected PAR to incoming mode's member */ |
0e9f25d0 | 2428 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
28b468a0 | 2429 | |
d4d6279a ACO |
2430 | pipe_config->lane_count = 4; |
2431 | ||
9672a69c RV |
2432 | if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || |
2433 | IS_GEMINILAKE(dev_priv))) { | |
15953637 SS |
2434 | if (scdc->scrambling.low_rates) |
2435 | pipe_config->hdmi_scrambling = true; | |
2436 | ||
2437 | if (pipe_config->port_clock > 340000) { | |
2438 | pipe_config->hdmi_scrambling = true; | |
2439 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
2440 | } | |
2441 | } | |
2442 | ||
fbf08556 VS |
2443 | intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); |
2444 | ||
2445 | if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { | |
2446 | DRM_DEBUG_KMS("bad AVI infoframe\n"); | |
2447 | return -EINVAL; | |
2448 | } | |
2449 | ||
2450 | if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { | |
2451 | DRM_DEBUG_KMS("bad SPD infoframe\n"); | |
2452 | return -EINVAL; | |
2453 | } | |
2454 | ||
2455 | if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { | |
2456 | DRM_DEBUG_KMS("bad HDMI infoframe\n"); | |
2457 | return -EINVAL; | |
2458 | } | |
2459 | ||
5a0200f6 US |
2460 | if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { |
2461 | DRM_DEBUG_KMS("bad DRM infoframe\n"); | |
2462 | return -EINVAL; | |
2463 | } | |
2464 | ||
39e2df09 R |
2465 | intel_hdcp_transcoder_config(intel_hdmi->attached_connector, |
2466 | pipe_config->cpu_transcoder); | |
2467 | ||
204474a6 | 2468 | return 0; |
7d57382e EA |
2469 | } |
2470 | ||
953ece69 CW |
2471 | static void |
2472 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 2473 | { |
df0e9248 | 2474 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 2475 | |
953ece69 CW |
2476 | intel_hdmi->has_hdmi_sink = false; |
2477 | intel_hdmi->has_audio = false; | |
953ece69 | 2478 | |
b1ba124d VS |
2479 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
2480 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
2481 | ||
953ece69 CW |
2482 | kfree(to_intel_connector(connector)->detect_edid); |
2483 | to_intel_connector(connector)->detect_edid = NULL; | |
2484 | } | |
2485 | ||
b1ba124d | 2486 | static void |
d6199256 | 2487 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
2488 | { |
2489 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2490 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
8f4f2797 | 2491 | enum port port = hdmi_to_dig_port(hdmi)->base.port; |
b1ba124d VS |
2492 | struct i2c_adapter *adapter = |
2493 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
2494 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
2495 | ||
d6199256 VS |
2496 | /* |
2497 | * Type 1 DVI adaptors are not required to implement any | |
2498 | * registers, so we can't always detect their presence. | |
2499 | * Ideally we should be able to check the state of the | |
2500 | * CONFIG1 pin, but no such luck on our hardware. | |
2501 | * | |
2502 | * The only method left to us is to check the VBT to see | |
2503 | * if the port is a dual mode capable DP port. But let's | |
2504 | * only do that when we sucesfully read the EDID, to avoid | |
2505 | * confusing log messages about DP dual mode adaptors when | |
2506 | * there's nothing connected to the port. | |
2507 | */ | |
2508 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
30190629 AJ |
2509 | /* An overridden EDID imply that we want this port for testing. |
2510 | * Make sure not to set limits for that port. | |
2511 | */ | |
2512 | if (has_edid && !connector->override_edid && | |
d6199256 VS |
2513 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { |
2514 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
2515 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
2516 | } else { | |
2517 | type = DRM_DP_DUAL_MODE_NONE; | |
2518 | } | |
2519 | } | |
2520 | ||
2521 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
2522 | return; |
2523 | ||
2524 | hdmi->dp_dual_mode.type = type; | |
2525 | hdmi->dp_dual_mode.max_tmds_clock = | |
2526 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
2527 | ||
2528 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
2529 | drm_dp_get_dual_mode_type_name(type), | |
2530 | hdmi->dp_dual_mode.max_tmds_clock); | |
2531 | } | |
2532 | ||
953ece69 | 2533 | static bool |
23f889bd | 2534 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
2535 | { |
2536 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2537 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
0e6e0be4 | 2538 | intel_wakeref_t wakeref; |
23f889bd | 2539 | struct edid *edid; |
953ece69 | 2540 | bool connected = false; |
cfb926e1 | 2541 | struct i2c_adapter *i2c; |
164c8598 | 2542 | |
0e6e0be4 | 2543 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 2544 | |
cfb926e1 SB |
2545 | i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); |
2546 | ||
2547 | edid = drm_get_edid(connector, i2c); | |
2548 | ||
2549 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
2550 | DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
2551 | intel_gmbus_force_bit(i2c, true); | |
2552 | edid = drm_get_edid(connector, i2c); | |
2553 | intel_gmbus_force_bit(i2c, false); | |
2554 | } | |
2ded9e27 | 2555 | |
23f889bd | 2556 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 2557 | |
0e6e0be4 | 2558 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
30ad48b7 | 2559 | |
953ece69 CW |
2560 | to_intel_connector(connector)->detect_edid = edid; |
2561 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
953ece69 | 2562 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
7a5ca19f | 2563 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
2564 | |
2565 | connected = true; | |
55b7d6e8 CW |
2566 | } |
2567 | ||
9c229127 NA |
2568 | cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); |
2569 | ||
953ece69 CW |
2570 | return connected; |
2571 | } | |
2572 | ||
8166fcea DV |
2573 | static enum drm_connector_status |
2574 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 2575 | { |
39d1e234 | 2576 | enum drm_connector_status status = connector_status_disconnected; |
8166fcea | 2577 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
9c229127 | 2578 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
39d1e234 | 2579 | struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; |
0e6e0be4 | 2580 | intel_wakeref_t wakeref; |
953ece69 | 2581 | |
8166fcea DV |
2582 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2583 | connector->base.id, connector->name); | |
2584 | ||
0e6e0be4 | 2585 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
29bb94bb | 2586 | |
2dd24a9c | 2587 | if (INTEL_GEN(dev_priv) >= 11 && |
39d1e234 PZ |
2588 | !intel_digital_port_connected(encoder)) |
2589 | goto out; | |
2590 | ||
8166fcea | 2591 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 2592 | |
7e732cac | 2593 | if (intel_hdmi_set_edid(connector)) |
953ece69 | 2594 | status = connector_status_connected; |
671dedd2 | 2595 | |
39d1e234 | 2596 | out: |
0e6e0be4 | 2597 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
29bb94bb | 2598 | |
9c229127 NA |
2599 | if (status != connector_status_connected) |
2600 | cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); | |
2601 | ||
2ded9e27 | 2602 | return status; |
7d57382e EA |
2603 | } |
2604 | ||
953ece69 CW |
2605 | static void |
2606 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 2607 | { |
953ece69 CW |
2608 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2609 | connector->base.id, connector->name); | |
7d57382e | 2610 | |
953ece69 | 2611 | intel_hdmi_unset_edid(connector); |
671dedd2 | 2612 | |
953ece69 CW |
2613 | if (connector->status != connector_status_connected) |
2614 | return; | |
671dedd2 | 2615 | |
23f889bd | 2616 | intel_hdmi_set_edid(connector); |
953ece69 | 2617 | } |
671dedd2 | 2618 | |
953ece69 CW |
2619 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
2620 | { | |
2621 | struct edid *edid; | |
2622 | ||
2623 | edid = to_intel_connector(connector)->detect_edid; | |
2624 | if (edid == NULL) | |
2625 | return 0; | |
671dedd2 | 2626 | |
953ece69 | 2627 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
2628 | } |
2629 | ||
fd6bbda9 | 2630 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2631 | const struct intel_crtc_state *pipe_config, |
2632 | const struct drm_connector_state *conn_state) | |
13732ba7 | 2633 | { |
f99be1b3 VS |
2634 | struct intel_digital_port *intel_dig_port = |
2635 | enc_to_dig_port(&encoder->base); | |
13732ba7 | 2636 | |
ac240288 | 2637 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2638 | |
790ea70c | 2639 | intel_dig_port->set_infoframes(encoder, |
f99be1b3 VS |
2640 | pipe_config->has_infoframe, |
2641 | pipe_config, conn_state); | |
13732ba7 JB |
2642 | } |
2643 | ||
fd6bbda9 | 2644 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2645 | const struct intel_crtc_state *pipe_config, |
2646 | const struct drm_connector_state *conn_state) | |
89b667f8 JB |
2647 | { |
2648 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2e1029c6 | 2649 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5f68c275 | 2650 | |
2e1029c6 | 2651 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
b76cf76b | 2652 | |
53d98725 ACO |
2653 | /* HDMI 1.0V-2dB */ |
2654 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
2655 | 0x2b247878); | |
2656 | ||
790ea70c | 2657 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2658 | pipe_config->has_infoframe, |
2659 | pipe_config, conn_state); | |
13732ba7 | 2660 | |
fd6bbda9 | 2661 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 2662 | |
9b6de0a1 | 2663 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
2664 | } |
2665 | ||
fd6bbda9 | 2666 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2667 | const struct intel_crtc_state *pipe_config, |
2668 | const struct drm_connector_state *conn_state) | |
89b667f8 | 2669 | { |
ac240288 | 2670 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2671 | |
2e1029c6 | 2672 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
89b667f8 JB |
2673 | } |
2674 | ||
fd6bbda9 | 2675 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2676 | const struct intel_crtc_state *pipe_config, |
2677 | const struct drm_connector_state *conn_state) | |
9197c88b | 2678 | { |
ac240288 | 2679 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 2680 | |
2e1029c6 | 2681 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
2682 | } |
2683 | ||
fd6bbda9 | 2684 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2685 | const struct intel_crtc_state *old_crtc_state, |
2686 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 2687 | { |
2e1029c6 | 2688 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
2689 | } |
2690 | ||
fd6bbda9 | 2691 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2692 | const struct intel_crtc_state *old_crtc_state, |
2693 | const struct drm_connector_state *old_conn_state) | |
89b667f8 | 2694 | { |
89b667f8 | 2695 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
2e1029c6 | 2696 | vlv_phy_reset_lanes(encoder, old_crtc_state); |
89b667f8 JB |
2697 | } |
2698 | ||
fd6bbda9 | 2699 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2700 | const struct intel_crtc_state *old_crtc_state, |
2701 | const struct drm_connector_state *old_conn_state) | |
580d3811 | 2702 | { |
580d3811 | 2703 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2704 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 2705 | |
221c7862 | 2706 | vlv_dpio_get(dev_priv); |
580d3811 | 2707 | |
a8f327fb | 2708 | /* Assert data lane reset */ |
2e1029c6 | 2709 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 2710 | |
221c7862 | 2711 | vlv_dpio_put(dev_priv); |
580d3811 VS |
2712 | } |
2713 | ||
fd6bbda9 | 2714 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2715 | const struct intel_crtc_state *pipe_config, |
2716 | const struct drm_connector_state *conn_state) | |
e4a1d846 CML |
2717 | { |
2718 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2719 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2720 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 2721 | |
2e1029c6 | 2722 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
a02ef3c7 | 2723 | |
e4a1d846 CML |
2724 | /* FIXME: Program the support xxx V-dB */ |
2725 | /* Use 800mV-0dB */ | |
b7fa22d8 | 2726 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 2727 | |
790ea70c | 2728 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2729 | pipe_config->has_infoframe, |
2730 | pipe_config, conn_state); | |
b4eb1564 | 2731 | |
fd6bbda9 | 2732 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 2733 | |
9b6de0a1 | 2734 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
2735 | |
2736 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2737 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2738 | } |
2739 | ||
7d09888e OV |
2740 | static struct i2c_adapter * |
2741 | intel_hdmi_get_i2c_adapter(struct drm_connector *connector) | |
2742 | { | |
2743 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2744 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
2745 | ||
2746 | return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); | |
2747 | } | |
2748 | ||
2749 | static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) | |
2750 | { | |
2751 | struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); | |
2752 | struct kobject *i2c_kobj = &adapter->dev.kobj; | |
2753 | struct kobject *connector_kobj = &connector->kdev->kobj; | |
2754 | int ret; | |
2755 | ||
2756 | ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); | |
2757 | if (ret) | |
2758 | DRM_ERROR("Failed to create i2c symlink (%d)\n", ret); | |
2759 | } | |
2760 | ||
2761 | static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) | |
2762 | { | |
2763 | struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); | |
2764 | struct kobject *i2c_kobj = &adapter->dev.kobj; | |
2765 | struct kobject *connector_kobj = &connector->kdev->kobj; | |
2766 | ||
2767 | sysfs_remove_link(connector_kobj, i2c_kobj->name); | |
2768 | } | |
2769 | ||
bdc93fe0 R |
2770 | static int |
2771 | intel_hdmi_connector_register(struct drm_connector *connector) | |
2772 | { | |
2773 | int ret; | |
2774 | ||
2775 | ret = intel_connector_register(connector); | |
2776 | if (ret) | |
2777 | return ret; | |
2778 | ||
2779 | i915_debugfs_connector_add(connector); | |
2780 | ||
7d09888e OV |
2781 | intel_hdmi_create_i2c_symlink(connector); |
2782 | ||
bdc93fe0 R |
2783 | return ret; |
2784 | } | |
2785 | ||
7d57382e EA |
2786 | static void intel_hdmi_destroy(struct drm_connector *connector) |
2787 | { | |
9c229127 NA |
2788 | if (intel_attached_hdmi(connector)->cec_notifier) |
2789 | cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier); | |
d4b26e4f JN |
2790 | |
2791 | intel_connector_destroy(connector); | |
7d57382e EA |
2792 | } |
2793 | ||
7d09888e OV |
2794 | static void intel_hdmi_connector_unregister(struct drm_connector *connector) |
2795 | { | |
2796 | intel_hdmi_remove_i2c_symlink(connector); | |
2797 | ||
2798 | intel_connector_unregister(connector); | |
2799 | } | |
2800 | ||
7d57382e | 2801 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
7d57382e | 2802 | .detect = intel_hdmi_detect, |
953ece69 | 2803 | .force = intel_hdmi_force, |
7d57382e | 2804 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
2805 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
2806 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
bdc93fe0 | 2807 | .late_register = intel_hdmi_connector_register, |
7d09888e | 2808 | .early_unregister = intel_hdmi_connector_unregister, |
7d57382e | 2809 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 2810 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 2811 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
2812 | }; |
2813 | ||
2814 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
2815 | .get_modes = intel_hdmi_get_modes, | |
2816 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 2817 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
2818 | }; |
2819 | ||
7d57382e | 2820 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 2821 | .destroy = intel_encoder_destroy, |
7d57382e EA |
2822 | }; |
2823 | ||
55b7d6e8 CW |
2824 | static void |
2825 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
2826 | { | |
f1a12172 | 2827 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
2f146b78 US |
2828 | struct intel_digital_port *intel_dig_port = |
2829 | hdmi_to_dig_port(intel_hdmi); | |
f1a12172 | 2830 | |
3f43c48d | 2831 | intel_attach_force_audio_property(connector); |
e953fd7b | 2832 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 2833 | intel_attach_aspect_ratio_property(connector); |
2f146b78 US |
2834 | |
2835 | /* | |
2836 | * Attach Colorspace property for Non LSPCON based device | |
2837 | * ToDo: This needs to be extended for LSPCON implementation | |
2838 | * as well. Will be implemented separately. | |
2839 | */ | |
2840 | if (!intel_dig_port->lspcon.active) | |
2841 | intel_attach_colorspace_property(connector); | |
2842 | ||
6553b123 | 2843 | drm_connector_attach_content_type_property(connector); |
0e9f25d0 | 2844 | connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
f1a12172 | 2845 | |
b7bedf31 US |
2846 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
2847 | drm_object_attach_property(&connector->base, | |
2848 | connector->dev->mode_config.hdr_output_metadata_property, 0); | |
2849 | ||
b2ae318a | 2850 | if (!HAS_GMCH(dev_priv)) |
f1a12172 | 2851 | drm_connector_attach_max_bpc_property(connector, 8, 12); |
55b7d6e8 CW |
2852 | } |
2853 | ||
15953637 SS |
2854 | /* |
2855 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
2856 | * @encoder: intel_encoder | |
2857 | * @connector: drm_connector | |
2858 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
2859 | * or reset the high tmds clock ratio for scrambling | |
2860 | * @scrambling: bool to Indicate if the function needs to set or reset | |
2861 | * sink scrambling | |
2862 | * | |
2863 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
2864 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
2865 | * it enables scrambling. This should be called before enabling the HDMI | |
2866 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
2867 | * detect a scrambled clock within 100 ms. | |
277ab5ab VS |
2868 | * |
2869 | * Returns: | |
2870 | * True on success, false on failure. | |
15953637 | 2871 | */ |
277ab5ab | 2872 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
15953637 SS |
2873 | struct drm_connector *connector, |
2874 | bool high_tmds_clock_ratio, | |
2875 | bool scrambling) | |
2876 | { | |
277ab5ab | 2877 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
15953637 | 2878 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
15953637 | 2879 | struct drm_scrambling *sink_scrambling = |
277ab5ab VS |
2880 | &connector->display_info.hdmi.scdc.scrambling; |
2881 | struct i2c_adapter *adapter = | |
2882 | intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); | |
15953637 SS |
2883 | |
2884 | if (!sink_scrambling->supported) | |
277ab5ab | 2885 | return true; |
15953637 | 2886 | |
277ab5ab VS |
2887 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", |
2888 | connector->base.id, connector->name, | |
2889 | yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); | |
15953637 | 2890 | |
277ab5ab VS |
2891 | /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ |
2892 | return drm_scdc_set_high_tmds_clock_ratio(adapter, | |
2893 | high_tmds_clock_ratio) && | |
2894 | drm_scdc_set_scrambling(adapter, scrambling); | |
15953637 SS |
2895 | } |
2896 | ||
cec3bb01 | 2897 | static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
e4ab73a1 | 2898 | { |
e4ab73a1 VS |
2899 | u8 ddc_pin; |
2900 | ||
cec3bb01 AS |
2901 | switch (port) { |
2902 | case PORT_B: | |
2903 | ddc_pin = GMBUS_PIN_DPB; | |
2904 | break; | |
2905 | case PORT_C: | |
2906 | ddc_pin = GMBUS_PIN_DPC; | |
2907 | break; | |
2908 | case PORT_D: | |
2909 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
2910 | break; | |
2911 | default: | |
2912 | MISSING_CASE(port); | |
2913 | ddc_pin = GMBUS_PIN_DPB; | |
2914 | break; | |
e4ab73a1 | 2915 | } |
cec3bb01 AS |
2916 | return ddc_pin; |
2917 | } | |
2918 | ||
2919 | static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) | |
2920 | { | |
2921 | u8 ddc_pin; | |
e4ab73a1 VS |
2922 | |
2923 | switch (port) { | |
2924 | case PORT_B: | |
cec3bb01 | 2925 | ddc_pin = GMBUS_PIN_1_BXT; |
e4ab73a1 VS |
2926 | break; |
2927 | case PORT_C: | |
cec3bb01 AS |
2928 | ddc_pin = GMBUS_PIN_2_BXT; |
2929 | break; | |
2930 | default: | |
2931 | MISSING_CASE(port); | |
2932 | ddc_pin = GMBUS_PIN_1_BXT; | |
2933 | break; | |
2934 | } | |
2935 | return ddc_pin; | |
2936 | } | |
2937 | ||
2938 | static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
2939 | enum port port) | |
2940 | { | |
2941 | u8 ddc_pin; | |
2942 | ||
2943 | switch (port) { | |
2944 | case PORT_B: | |
2945 | ddc_pin = GMBUS_PIN_1_BXT; | |
2946 | break; | |
2947 | case PORT_C: | |
2948 | ddc_pin = GMBUS_PIN_2_BXT; | |
e4ab73a1 VS |
2949 | break; |
2950 | case PORT_D: | |
cec3bb01 AS |
2951 | ddc_pin = GMBUS_PIN_4_CNP; |
2952 | break; | |
3a2a59cc RV |
2953 | case PORT_F: |
2954 | ddc_pin = GMBUS_PIN_3_BXT; | |
2955 | break; | |
cec3bb01 AS |
2956 | default: |
2957 | MISSING_CASE(port); | |
2958 | ddc_pin = GMBUS_PIN_1_BXT; | |
2959 | break; | |
2960 | } | |
2961 | return ddc_pin; | |
2962 | } | |
2963 | ||
5c749c52 AS |
2964 | static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
2965 | { | |
fb81cbe4 | 2966 | enum phy phy = intel_port_to_phy(dev_priv, port); |
5c749c52 | 2967 | |
fb81cbe4 LDM |
2968 | if (intel_phy_is_combo(dev_priv, phy)) |
2969 | return GMBUS_PIN_1_BXT + port; | |
2970 | else if (intel_phy_is_tc(dev_priv, phy)) | |
2971 | return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); | |
2972 | ||
2973 | WARN(1, "Unknown port:%c\n", port_name(port)); | |
2974 | return GMBUS_PIN_2_BXT; | |
5c749c52 AS |
2975 | } |
2976 | ||
c6f7acb8 MR |
2977 | static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
2978 | { | |
48cf0a1e | 2979 | enum phy phy = intel_port_to_phy(dev_priv, port); |
c6f7acb8 MR |
2980 | u8 ddc_pin; |
2981 | ||
48cf0a1e MR |
2982 | switch (phy) { |
2983 | case PHY_A: | |
c6f7acb8 MR |
2984 | ddc_pin = GMBUS_PIN_1_BXT; |
2985 | break; | |
48cf0a1e | 2986 | case PHY_B: |
c6f7acb8 MR |
2987 | ddc_pin = GMBUS_PIN_2_BXT; |
2988 | break; | |
48cf0a1e | 2989 | case PHY_C: |
c6f7acb8 MR |
2990 | ddc_pin = GMBUS_PIN_9_TC1_ICP; |
2991 | break; | |
2992 | default: | |
48cf0a1e | 2993 | MISSING_CASE(phy); |
c6f7acb8 MR |
2994 | ddc_pin = GMBUS_PIN_1_BXT; |
2995 | break; | |
2996 | } | |
2997 | return ddc_pin; | |
2998 | } | |
2999 | ||
cec3bb01 AS |
3000 | static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, |
3001 | enum port port) | |
3002 | { | |
3003 | u8 ddc_pin; | |
3004 | ||
3005 | switch (port) { | |
3006 | case PORT_B: | |
3007 | ddc_pin = GMBUS_PIN_DPB; | |
3008 | break; | |
3009 | case PORT_C: | |
3010 | ddc_pin = GMBUS_PIN_DPC; | |
3011 | break; | |
3012 | case PORT_D: | |
3013 | ddc_pin = GMBUS_PIN_DPD; | |
e4ab73a1 VS |
3014 | break; |
3015 | default: | |
3016 | MISSING_CASE(port); | |
3017 | ddc_pin = GMBUS_PIN_DPB; | |
3018 | break; | |
3019 | } | |
cec3bb01 AS |
3020 | return ddc_pin; |
3021 | } | |
3022 | ||
3023 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, | |
3024 | enum port port) | |
3025 | { | |
3026 | const struct ddi_vbt_port_info *info = | |
3027 | &dev_priv->vbt.ddi_port_info[port]; | |
3028 | u8 ddc_pin; | |
3029 | ||
3030 | if (info->alternate_ddc_pin) { | |
3031 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
3032 | info->alternate_ddc_pin, port_name(port)); | |
3033 | return info->alternate_ddc_pin; | |
3034 | } | |
3035 | ||
c6f7acb8 MR |
3036 | if (HAS_PCH_MCC(dev_priv)) |
3037 | ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); | |
b01a3ef3 | 3038 | else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) |
e0f83eb5 | 3039 | ddc_pin = icl_port_to_ddc_pin(dev_priv, port); |
cec3bb01 AS |
3040 | else if (HAS_PCH_CNP(dev_priv)) |
3041 | ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); | |
e0f83eb5 RV |
3042 | else if (IS_GEN9_LP(dev_priv)) |
3043 | ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); | |
3044 | else if (IS_CHERRYVIEW(dev_priv)) | |
3045 | ddc_pin = chv_port_to_ddc_pin(dev_priv, port); | |
cec3bb01 AS |
3046 | else |
3047 | ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); | |
e4ab73a1 VS |
3048 | |
3049 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
3050 | ddc_pin, port_name(port)); | |
3051 | ||
3052 | return ddc_pin; | |
3053 | } | |
3054 | ||
385e4de0 VS |
3055 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port) |
3056 | { | |
3057 | struct drm_i915_private *dev_priv = | |
3058 | to_i915(intel_dig_port->base.base.dev); | |
3059 | ||
3060 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
3061 | intel_dig_port->write_infoframe = vlv_write_infoframe; | |
f2a10d61 | 3062 | intel_dig_port->read_infoframe = vlv_read_infoframe; |
385e4de0 | 3063 | intel_dig_port->set_infoframes = vlv_set_infoframes; |
509efa2b | 3064 | intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; |
385e4de0 VS |
3065 | } else if (IS_G4X(dev_priv)) { |
3066 | intel_dig_port->write_infoframe = g4x_write_infoframe; | |
f2a10d61 | 3067 | intel_dig_port->read_infoframe = g4x_read_infoframe; |
385e4de0 | 3068 | intel_dig_port->set_infoframes = g4x_set_infoframes; |
509efa2b | 3069 | intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; |
385e4de0 | 3070 | } else if (HAS_DDI(dev_priv)) { |
06c812d7 | 3071 | if (intel_dig_port->lspcon.active) { |
509efa2b | 3072 | intel_dig_port->write_infoframe = lspcon_write_infoframe; |
f2a10d61 | 3073 | intel_dig_port->read_infoframe = lspcon_read_infoframe; |
06c812d7 | 3074 | intel_dig_port->set_infoframes = lspcon_set_infoframes; |
509efa2b | 3075 | intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; |
06c812d7 | 3076 | } else { |
06c812d7 | 3077 | intel_dig_port->write_infoframe = hsw_write_infoframe; |
f2a10d61 | 3078 | intel_dig_port->read_infoframe = hsw_read_infoframe; |
509efa2b VS |
3079 | intel_dig_port->set_infoframes = hsw_set_infoframes; |
3080 | intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; | |
06c812d7 | 3081 | } |
385e4de0 VS |
3082 | } else if (HAS_PCH_IBX(dev_priv)) { |
3083 | intel_dig_port->write_infoframe = ibx_write_infoframe; | |
f2a10d61 | 3084 | intel_dig_port->read_infoframe = ibx_read_infoframe; |
385e4de0 | 3085 | intel_dig_port->set_infoframes = ibx_set_infoframes; |
509efa2b | 3086 | intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; |
385e4de0 VS |
3087 | } else { |
3088 | intel_dig_port->write_infoframe = cpt_write_infoframe; | |
f2a10d61 | 3089 | intel_dig_port->read_infoframe = cpt_read_infoframe; |
385e4de0 | 3090 | intel_dig_port->set_infoframes = cpt_set_infoframes; |
509efa2b | 3091 | intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; |
385e4de0 VS |
3092 | } |
3093 | } | |
3094 | ||
00c09d70 PZ |
3095 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
3096 | struct intel_connector *intel_connector) | |
7d57382e | 3097 | { |
b9cb234c PZ |
3098 | struct drm_connector *connector = &intel_connector->base; |
3099 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
3100 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3101 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 3102 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 3103 | enum port port = intel_encoder->port; |
373a3cf7 | 3104 | |
66a990dd VS |
3105 | DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n", |
3106 | intel_encoder->base.base.id, intel_encoder->base.name); | |
22f35042 | 3107 | |
ccb1a831 | 3108 | if (WARN(intel_dig_port->max_lanes < 4, |
66a990dd VS |
3109 | "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", |
3110 | intel_dig_port->max_lanes, intel_encoder->base.base.id, | |
3111 | intel_encoder->base.name)) | |
ccb1a831 VS |
3112 | return; |
3113 | ||
7d57382e | 3114 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 3115 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
3116 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
3117 | ||
c3febcc4 | 3118 | connector->interlace_allowed = 1; |
7d57382e | 3119 | connector->doublescan_allowed = 0; |
573e74ad | 3120 | connector->stereo_allowed = 1; |
66a9278e | 3121 | |
9672a69c | 3122 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
eadc2e51 SS |
3123 | connector->ycbcr_420_allowed = true; |
3124 | ||
e4ab73a1 VS |
3125 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
3126 | ||
f761bef2 | 3127 | if (WARN_ON(port == PORT_A)) |
e4ab73a1 | 3128 | return; |
cf53902f | 3129 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
7d57382e | 3130 | |
4f8036a2 | 3131 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
3132 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3133 | else | |
3134 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
3135 | |
3136 | intel_hdmi_add_properties(intel_hdmi, connector); | |
3137 | ||
04707f97 R |
3138 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
3139 | intel_hdmi->attached_connector = intel_connector; | |
3140 | ||
fdddd08c | 3141 | if (is_hdcp_supported(dev_priv, port)) { |
2320175f SP |
3142 | int ret = intel_hdcp_init(intel_connector, |
3143 | &intel_hdmi_hdcp_shim); | |
3144 | if (ret) | |
3145 | DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); | |
3146 | } | |
3147 | ||
b9cb234c PZ |
3148 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3149 | * 0xd. Failure to do so will result in spurious interrupts being | |
3150 | * generated on the port when a cable is not attached. | |
3151 | */ | |
1c0f1b3d | 3152 | if (IS_G45(dev_priv)) { |
b9cb234c PZ |
3153 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
3154 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
3155 | } | |
9c229127 NA |
3156 | |
3157 | intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev, | |
3158 | port_identifier(port)); | |
3159 | if (!intel_hdmi->cec_notifier) | |
3160 | DRM_DEBUG_KMS("CEC notifier get failed\n"); | |
b9cb234c PZ |
3161 | } |
3162 | ||
bb80c925 JRS |
3163 | static enum intel_hotplug_state |
3164 | intel_hdmi_hotplug(struct intel_encoder *encoder, | |
3165 | struct intel_connector *connector, bool irq_received) | |
3166 | { | |
3167 | enum intel_hotplug_state state; | |
3168 | ||
3169 | state = intel_encoder_hotplug(encoder, connector, irq_received); | |
3170 | ||
3171 | /* | |
3172 | * On many platforms the HDMI live state signal is known to be | |
3173 | * unreliable, so we can't use it to detect if a sink is connected or | |
3174 | * not. Instead we detect if it's connected based on whether we can | |
3175 | * read the EDID or not. That in turn has a problem during disconnect, | |
3176 | * since the HPD interrupt may be raised before the DDC lines get | |
3177 | * disconnected (due to how the required length of DDC vs. HPD | |
3178 | * connector pins are specified) and so we'll still be able to get a | |
3179 | * valid EDID. To solve this schedule another detection cycle if this | |
3180 | * time around we didn't detect any change in the sink's connection | |
3181 | * status. | |
3182 | */ | |
3183 | if (state == INTEL_HOTPLUG_UNCHANGED && irq_received) | |
3184 | state = INTEL_HOTPLUG_RETRY; | |
3185 | ||
3186 | return state; | |
3187 | } | |
3188 | ||
c39055b0 | 3189 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 3190 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
3191 | { |
3192 | struct intel_digital_port *intel_dig_port; | |
3193 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
3194 | struct intel_connector *intel_connector; |
3195 | ||
b14c5679 | 3196 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
3197 | if (!intel_dig_port) |
3198 | return; | |
3199 | ||
08d9bc92 | 3200 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
3201 | if (!intel_connector) { |
3202 | kfree(intel_dig_port); | |
3203 | return; | |
3204 | } | |
3205 | ||
3206 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 3207 | |
c39055b0 ACO |
3208 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
3209 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
3210 | "HDMI %c", port_name(port)); | |
00c09d70 | 3211 | |
bb80c925 | 3212 | intel_encoder->hotplug = intel_hdmi_hotplug; |
5bfe2ac0 | 3213 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 3214 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
3215 | intel_encoder->disable = pch_disable_hdmi; |
3216 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
3217 | } else { | |
3218 | intel_encoder->disable = g4x_disable_hdmi; | |
3219 | } | |
00c09d70 | 3220 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 3221 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 3222 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 3223 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
3224 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
3225 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 3226 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 3227 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 3228 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
3229 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
3230 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 3231 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 3232 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 3233 | } else { |
13732ba7 | 3234 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 3235 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 3236 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 3237 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 3238 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 3239 | else |
bf868c7d | 3240 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 3241 | } |
5ab432ef | 3242 | |
b9cb234c | 3243 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 3244 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 3245 | intel_encoder->port = port; |
920a14b2 | 3246 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
3247 | if (port == PORT_D) |
3248 | intel_encoder->crtc_mask = 1 << 2; | |
3249 | else | |
3250 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
3251 | } else { | |
3252 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
3253 | } | |
301ea74a | 3254 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
3255 | /* |
3256 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
3257 | * to work on real hardware. And since g4x can send infoframes to | |
3258 | * only one port anyway, nothing is lost by allowing it. | |
3259 | */ | |
9beb5fea | 3260 | if (IS_G4X(dev_priv)) |
c6f1495d | 3261 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 3262 | |
b242b7f7 | 3263 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 3264 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 3265 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 3266 | |
385e4de0 VS |
3267 | intel_infoframe_init(intel_dig_port); |
3268 | ||
39053089 | 3269 | intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
b9cb234c | 3270 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 3271 | } |