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drm/i2c: tda998x: report whether we actually handled the IRQ
[linux-2.6-block.git] / drivers / gpu / drm / i2c / tda998x_drv.c
CommitLineData
e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
c707c361 18#include <linux/component.h>
893c3e53 19#include <linux/hdmi.h>
e7792ce2 20#include <linux/module.h>
12473b7d 21#include <linux/irq.h>
f0b33b28 22#include <sound/asoundef.h>
e7792ce2
RC		 23
24#include <drm/drmP.h>
25#include <drm/drm_crtc_helper.h>
26#include <drm/drm_encoder_slave.h>
27#include <drm/drm_edid.h>
5dbcf319 28#include <drm/drm_of.h>
c4c11dd1 29#include <drm/i2c/tda998x.h>
e7792ce2
RC		 30
31#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
32
33struct tda998x_priv {
34 struct i2c_client *cec;
2f7f730a 35 struct i2c_client *hdmi;
ed9a8426 36 struct mutex mutex;
6833d26e 37 struct delayed_work dwork;
e7792ce2
RC		 38 uint16_t rev;
39 uint8_t current_page;
40 int dpms;
c4c11dd1 41 bool is_hdmi_sink;
5e74c22c
RK		 42 u8 vip_cntrl_0;
43 u8 vip_cntrl_1;
44 u8 vip_cntrl_2;
c4c11dd1 45 struct tda998x_encoder_params params;
12473b7d
JFM		 46
47 wait_queue_head_t wq_edid;
48 volatile int wq_edid_wait;
49 struct drm_encoder *encoder;
e7792ce2
RC		 50};
51
52#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
53
54/* The TDA9988 series of devices use a paged register scheme.. to simplify
55 * things we encode the page # in upper bits of the register #. To read/
56 * write a given register, we need to make sure CURPAGE register is set
57 * appropriately. Which implies reads/writes are not atomic. Fun!
58 */
59
60#define REG(page, addr) (((page) << 8) | (addr))
61#define REG2ADDR(reg) ((reg) & 0xff)
62#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
63
64#define REG_CURPAGE 0xff /* write */
65
66
67/* Page 00h: General Control */
68#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
69#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
70# define MAIN_CNTRL0_SR (1 << 0)
71# define MAIN_CNTRL0_DECS (1 << 1)
72# define MAIN_CNTRL0_DEHS (1 << 2)
73# define MAIN_CNTRL0_CECS (1 << 3)
74# define MAIN_CNTRL0_CEHS (1 << 4)
75# define MAIN_CNTRL0_SCALER (1 << 7)
76#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
77#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
78# define SOFTRESET_AUDIO (1 << 0)
79# define SOFTRESET_I2C_MASTER (1 << 1)
80#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
81#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
82#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
83# define I2C_MASTER_DIS_MM (1 << 0)
84# define I2C_MASTER_DIS_FILT (1 << 1)
85# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1
RK		 86#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
87# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 88#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
89#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
90#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
91# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 92#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 93#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
94#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
95#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
96#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
97#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
98# define VIP_CNTRL_0_MIRR_A (1 << 7)
99# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
100# define VIP_CNTRL_0_MIRR_B (1 << 3)
101# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
102#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
103# define VIP_CNTRL_1_MIRR_C (1 << 7)
104# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
105# define VIP_CNTRL_1_MIRR_D (1 << 3)
106# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
107#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
108# define VIP_CNTRL_2_MIRR_E (1 << 7)
109# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
110# define VIP_CNTRL_2_MIRR_F (1 << 3)
111# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
112#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
113# define VIP_CNTRL_3_X_TGL (1 << 0)
114# define VIP_CNTRL_3_H_TGL (1 << 1)
115# define VIP_CNTRL_3_V_TGL (1 << 2)
116# define VIP_CNTRL_3_EMB (1 << 3)
117# define VIP_CNTRL_3_SYNC_DE (1 << 4)
118# define VIP_CNTRL_3_SYNC_HS (1 << 5)
119# define VIP_CNTRL_3_DE_INT (1 << 6)
120# define VIP_CNTRL_3_EDGE (1 << 7)
121#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
122# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
123# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
124# define VIP_CNTRL_4_CCIR656 (1 << 4)
125# define VIP_CNTRL_4_656_ALT (1 << 5)
126# define VIP_CNTRL_4_TST_656 (1 << 6)
127# define VIP_CNTRL_4_TST_PAT (1 << 7)
128#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
129# define VIP_CNTRL_5_CKCASE (1 << 0)
130# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 131#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
10df1a95
JFM		 132# define MUX_AP_SELECT_I2S 0x64
133# define MUX_AP_SELECT_SPDIF 0x40
bcb2481d 134#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 135#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
136# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
137# define MAT_CONTRL_MAT_BP (1 << 2)
138#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
139#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
140#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
141#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
142#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
143#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
144#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
145#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
146#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
147#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
148#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
149#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
150#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
151#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
152#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
153#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
154#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 155#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
156#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 157#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
158#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 159#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
160#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 161#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
162#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
163#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
164#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
165#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
166#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
167#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
168#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
169#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
170#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 171#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
172#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
173#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
174#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 175#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
176#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
177#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
178#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
179#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 180# define TBG_CNTRL_0_TOP_TGL (1 << 0)
181# define TBG_CNTRL_0_TOP_SEL (1 << 1)
182# define TBG_CNTRL_0_DE_EXT (1 << 2)
183# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 184# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
185# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
186# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
187#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 188# define TBG_CNTRL_1_H_TGL (1 << 0)
189# define TBG_CNTRL_1_V_TGL (1 << 1)
190# define TBG_CNTRL_1_TGL_EN (1 << 2)
191# define TBG_CNTRL_1_X_EXT (1 << 3)
192# define TBG_CNTRL_1_H_EXT (1 << 4)
193# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 194# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
195#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
196#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
197# define HVF_CNTRL_0_SM (1 << 7)
198# define HVF_CNTRL_0_RWB (1 << 6)
199# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
200# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
201#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
202# define HVF_CNTRL_1_FOR (1 << 0)
203# define HVF_CNTRL_1_YUVBLK (1 << 1)
204# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
205# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
206# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
207#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 208#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
209# define I2S_FORMAT(x) (((x) & 3) << 0)
210#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
10df1a95
JFM		 211# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
212# define AIP_CLKSEL_AIP_I2S (1 << 3)
213# define AIP_CLKSEL_FS_ACLK (0 << 0)
214# define AIP_CLKSEL_FS_MCLK (1 << 0)
215# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
e7792ce2
RC		 216
217/* Page 02h: PLL settings */
218#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
219# define PLL_SERIAL_1_SRL_FDN (1 << 0)
220# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
221# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
222#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 223# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 224# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
225#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
226# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
227# define PLL_SERIAL_3_SRL_DE (1 << 2)
228# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
229#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
230#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
231#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
232#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
233#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
234#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
235#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
236#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
237#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 238# define AUDIO_DIV_SERCLK_1 0
239# define AUDIO_DIV_SERCLK_2 1
240# define AUDIO_DIV_SERCLK_4 2
241# define AUDIO_DIV_SERCLK_8 3
242# define AUDIO_DIV_SERCLK_16 4
243# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 244#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
245# define SEL_CLK_SEL_CLK1 (1 << 0)
246# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
247# define SEL_CLK_ENA_SC_CLK (1 << 3)
248#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
249
250
251/* Page 09h: EDID Control */
252#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
253/* next 127 successive registers are the EDID block */
254#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
255#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
256#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
257#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
258#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
259
260
261/* Page 10h: information frames and packets */
c4c11dd1
RK		 262#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
263#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
264#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
265#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
266#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 267
268
269/* Page 11h: audio settings and content info packets */
270#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
271# define AIP_CNTRL_0_RST_FIFO (1 << 0)
272# define AIP_CNTRL_0_SWAP (1 << 1)
273# define AIP_CNTRL_0_LAYOUT (1 << 2)
274# define AIP_CNTRL_0_ACR_MAN (1 << 5)
275# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 276#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
277# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
278# define CA_I2S_HBR_CHSTAT (1 << 6)
279#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
280#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
281#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
282#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
283#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
284#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
285#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
286#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
287# define CTS_N_K(x) (((x) & 7) << 0)
288# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 289#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
290# define ENC_CNTRL_RST_ENC (1 << 0)
291# define ENC_CNTRL_RST_SEL (1 << 1)
292# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 293#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
294# define DIP_FLAGS_ACR (1 << 0)
295# define DIP_FLAGS_GC (1 << 1)
296#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
297# define DIP_IF_FLAGS_IF1 (1 << 1)
298# define DIP_IF_FLAGS_IF2 (1 << 2)
299# define DIP_IF_FLAGS_IF3 (1 << 3)
300# define DIP_IF_FLAGS_IF4 (1 << 4)
301# define DIP_IF_FLAGS_IF5 (1 << 5)
302#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 303
304
305/* Page 12h: HDCP and OTP */
306#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 307#define REG_TX4 REG(0x12, 0x9b) /* read/write */
308# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 309#define REG_TX33 REG(0x12, 0xb8) /* read/write */
310# define TX33_HDMI (1 << 1)
311
312
313/* Page 13h: Gamut related metadata packets */
314
315
316
317/* CEC registers: (not paged)
318 */
12473b7d
JFM		 319#define REG_CEC_INTSTATUS 0xee /* read */
320# define CEC_INTSTATUS_CEC (1 << 0)
321# define CEC_INTSTATUS_HDMI (1 << 1)
e7792ce2
RC		 322#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
323# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
324# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
325# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
326# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
12473b7d
JFM		 327#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
328#define REG_CEC_RXSHPDINT 0xfd /* read */
e7792ce2
RC		 329#define REG_CEC_RXSHPDLEV 0xfe /* read */
330# define CEC_RXSHPDLEV_RXSENS (1 << 0)
331# define CEC_RXSHPDLEV_HPD (1 << 1)
332
333#define REG_CEC_ENAMODS 0xff /* read/write */
334# define CEC_ENAMODS_DIS_FRO (1 << 6)
335# define CEC_ENAMODS_DIS_CCLK (1 << 5)
336# define CEC_ENAMODS_EN_RXSENS (1 << 2)
337# define CEC_ENAMODS_EN_HDMI (1 << 1)
338# define CEC_ENAMODS_EN_CEC (1 << 0)
339
340
341/* Device versions: */
342#define TDA9989N2 0x0101
343#define TDA19989 0x0201
344#define TDA19989N2 0x0202
345#define TDA19988 0x0301
346
347static void
2f7f730a 348cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val)
e7792ce2 349{
2f7f730a 350 struct i2c_client *client = priv->cec;
e7792ce2
RC		 351 uint8_t buf[] = {addr, val};
352 int ret;
353
704d63f5 354 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 355 if (ret < 0)
356 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
357}
358
359static uint8_t
2f7f730a 360cec_read(struct tda998x_priv *priv, uint8_t addr)
e7792ce2 361{
2f7f730a 362 struct i2c_client *client = priv->cec;
e7792ce2
RC		 363 uint8_t val;
364 int ret;
365
366 ret = i2c_master_send(client, &addr, sizeof(addr));
367 if (ret < 0)
368 goto fail;
369
370 ret = i2c_master_recv(client, &val, sizeof(val));
371 if (ret < 0)
372 goto fail;
373
374 return val;
375
376fail:
377 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
378 return 0;
379}
380
7d2eadc9 381static int
2f7f730a 382set_page(struct tda998x_priv *priv, uint16_t reg)
e7792ce2 383{
e7792ce2 384 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 385 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 386 uint8_t buf[] = {
387 REG_CURPAGE, REG2PAGE(reg)
388 };
389 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 390 if (ret < 0) {
288ffc73 391 dev_err(&client->dev, "%s %04x err %d\n", __func__,
704d63f5 392 reg, ret);
7d2eadc9
JFM		 393 return ret;
394 }
e7792ce2
RC		 395
396 priv->current_page = REG2PAGE(reg);
397 }
7d2eadc9 398 return 0;
e7792ce2
RC		 399}
400
401static int
2f7f730a 402reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt)
e7792ce2 403{
2f7f730a 404 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 405 uint8_t addr = REG2ADDR(reg);
406 int ret;
407
ed9a8426 408 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 409 ret = set_page(priv, reg);
410 if (ret < 0)
ed9a8426 411 goto out;
e7792ce2
RC		 412
413 ret = i2c_master_send(client, &addr, sizeof(addr));
414 if (ret < 0)
415 goto fail;
416
417 ret = i2c_master_recv(client, buf, cnt);
418 if (ret < 0)
419 goto fail;
420
ed9a8426 421 goto out;
e7792ce2
RC		 422
423fail:
424 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
ed9a8426
JFM		 425out:
426 mutex_unlock(&priv->mutex);
e7792ce2
RC		 427 return ret;
428}
429
c4c11dd1 430static void
2f7f730a 431reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt)
c4c11dd1 432{
2f7f730a 433 struct i2c_client *client = priv->hdmi;
c4c11dd1
RK		 434 uint8_t buf[cnt+1];
435 int ret;
436
437 buf[0] = REG2ADDR(reg);
438 memcpy(&buf[1], p, cnt);
439
ed9a8426 440 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 441 ret = set_page(priv, reg);
442 if (ret < 0)
ed9a8426 443 goto out;
c4c11dd1
RK		 444
445 ret = i2c_master_send(client, buf, cnt + 1);
446 if (ret < 0)
447 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 448out:
449 mutex_unlock(&priv->mutex);
c4c11dd1
RK		 450}
451
7d2eadc9 452static int
2f7f730a 453reg_read(struct tda998x_priv *priv, uint16_t reg)
e7792ce2
RC		 454{
455 uint8_t val = 0;
7d2eadc9
JFM		 456 int ret;
457
458 ret = reg_read_range(priv, reg, &val, sizeof(val));
459 if (ret < 0)
460 return ret;
e7792ce2
RC		 461 return val;
462}
463
464static void
2f7f730a 465reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 466{
2f7f730a 467 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 468 uint8_t buf[] = {REG2ADDR(reg), val};
469 int ret;
470
ed9a8426 471 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 472 ret = set_page(priv, reg);
473 if (ret < 0)
ed9a8426 474 goto out;
e7792ce2 475
704d63f5 476 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 477 if (ret < 0)
478 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 479out:
480 mutex_unlock(&priv->mutex);
e7792ce2
RC		 481}
482
483static void
2f7f730a 484reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val)
e7792ce2 485{
2f7f730a 486 struct i2c_client *client = priv->hdmi;
e7792ce2
RC		 487 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val};
488 int ret;
489
ed9a8426 490 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 491 ret = set_page(priv, reg);
492 if (ret < 0)
ed9a8426 493 goto out;
e7792ce2 494
704d63f5 495 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 496 if (ret < 0)
497 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 498out:
499 mutex_unlock(&priv->mutex);
e7792ce2
RC		 500}
501
502static void
2f7f730a 503reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 504{
7d2eadc9
JFM		 505 int old_val;
506
507 old_val = reg_read(priv, reg);
508 if (old_val >= 0)
509 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 510}
511
512static void
2f7f730a 513reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val)
e7792ce2 514{
7d2eadc9
JFM		 515 int old_val;
516
517 old_val = reg_read(priv, reg);
518 if (old_val >= 0)
519 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 520}
521
522static void
2f7f730a 523tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 524{
525 /* reset audio and i2c master: */
81b53a16 526 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 527 msleep(50);
81b53a16 528 reg_write(priv, REG_SOFTRESET, 0);
e7792ce2
RC		 529 msleep(50);
530
531 /* reset transmitter: */
2f7f730a
JFM		 532 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
533 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 534
535 /* PLL registers common configuration */
2f7f730a
JFM		 536 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
537 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
538 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
539 reg_write(priv, REG_SERIALIZER, 0x00);
540 reg_write(priv, REG_BUFFER_OUT, 0x00);
541 reg_write(priv, REG_PLL_SCG1, 0x00);
542 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
543 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
544 reg_write(priv, REG_PLL_SCGN1, 0xfa);
545 reg_write(priv, REG_PLL_SCGN2, 0x00);
546 reg_write(priv, REG_PLL_SCGR1, 0x5b);
547 reg_write(priv, REG_PLL_SCGR2, 0x00);
548 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 549
550 /* Write the default value MUX register */
2f7f730a 551 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 552}
553
6833d26e
JFM		 554/* handle HDMI connect/disconnect */
555static void tda998x_hpd(struct work_struct *work)
556{
557 struct delayed_work *dwork = to_delayed_work(work);
558 struct tda998x_priv *priv =
559 container_of(dwork, struct tda998x_priv, dwork);
560
3f3d0d00 561 if (priv->encoder->dev)
6833d26e
JFM		 562 drm_kms_helper_hotplug_event(priv->encoder->dev);
563}
564
12473b7d
JFM		 565/*
566 * only 2 interrupts may occur: screen plug/unplug and EDID read
567 */
568static irqreturn_t tda998x_irq_thread(int irq, void *data)
569{
570 struct tda998x_priv *priv = data;
571 u8 sta, cec, lvl, flag0, flag1, flag2;
f84a97d4 572 bool handled = false;
12473b7d 573
12473b7d
JFM		 574 sta = cec_read(priv, REG_CEC_INTSTATUS);
575 cec = cec_read(priv, REG_CEC_RXSHPDINT);
576 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
577 flag0 = reg_read(priv, REG_INT_FLAGS_0);
578 flag1 = reg_read(priv, REG_INT_FLAGS_1);
579 flag2 = reg_read(priv, REG_INT_FLAGS_2);
580 DRM_DEBUG_DRIVER(
581 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
582 sta, cec, lvl, flag0, flag1, flag2);
583 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
584 priv->wq_edid_wait = 0;
585 wake_up(&priv->wq_edid);
f84a97d4 586 handled = true;
12473b7d 587 } else if (cec != 0) { /* HPD change */
6833d26e 588 schedule_delayed_work(&priv->dwork, HZ/10);
f84a97d4 589 handled = true;
12473b7d 590 }
f84a97d4 591 return IRQ_RETVAL(handled);
12473b7d
JFM		 592}
593
c4c11dd1
RK		 594static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes)
595{
8268bd48 596 int sum = 0;
c4c11dd1
RK		 597
598 while (bytes--)
8268bd48
DV		 599 sum -= *buf++;
600 return sum;
c4c11dd1
RK		 601}
602
603#define HB(x) (x)
604#define PB(x) (HB(2) + 1 + (x))
605
606static void
2f7f730a 607tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr,
c4c11dd1
RK		 608 uint8_t *buf, size_t size)
609{
2f7f730a
JFM		 610 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
611 reg_write_range(priv, addr, buf, size);
612 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 613}
614
615static void
2f7f730a 616tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
c4c11dd1 617{
9e541466 618 u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
c4c11dd1 619
7288ca07 620 memset(buf, 0, sizeof(buf));
9e541466 621 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
c4c11dd1 622 buf[HB(1)] = 0x01;
9e541466 623 buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
c4c11dd1
RK		 624 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
625 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
626 buf[PB(4)] = p->audio_frame[4];
627 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
628
4a6ca1a2
JFM		 629 buf[PB(0)] = tda998x_cksum(buf, sizeof(buf));
630
2f7f730a 631 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
c4c11dd1
RK		 632 sizeof(buf));
633}
634
635static void
2f7f730a 636tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 637{
8c7a075d
RK		 638 struct hdmi_avi_infoframe frame;
639 u8 buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
640 ssize_t len;
c4c11dd1 641
8c7a075d
RK		 642 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
643
644 frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
645
646 len = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
647 if (len < 0) {
5296b7f9
RK		 648 dev_err(&priv->hdmi->dev,
649 "hdmi_avi_infoframe_pack() failed: %zd\n", len);
8c7a075d
RK		 650 return;
651 }
652
653 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, len);
c4c11dd1
RK		 654}
655
2f7f730a 656static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 657{
658 if (on) {
2f7f730a
JFM		 659 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
660 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
661 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 662 } else {
2f7f730a 663 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 664 }
665}
666
667static void
2f7f730a 668tda998x_configure_audio(struct tda998x_priv *priv,
c4c11dd1
RK		 669 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
670{
85c988bb 671 uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv;
c4c11dd1
RK		 672 uint32_t n;
673
674 /* Enable audio ports */
2f7f730a
JFM		 675 reg_write(priv, REG_ENA_AP, p->audio_cfg);
676 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
c4c11dd1
RK		 677
678 /* Set audio input source */
679 switch (p->audio_format) {
680 case AFMT_SPDIF:
10df1a95
JFM		 681 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
682 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
683 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
c4c11dd1 684 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1
RK		 685 break;
686
687 case AFMT_I2S:
10df1a95
JFM		 688 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
689 clksel_aip = AIP_CLKSEL_AIP_I2S;
690 clksel_fs = AIP_CLKSEL_FS_ACLK;
c4c11dd1 691 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1 692 break;
3b28802e
DH		 693
694 default:
695 BUG();
696 return;
c4c11dd1
RK		 697 }
698
2f7f730a 699 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
a8b517e5
JFM		 700 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
701 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
2f7f730a 702 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 703
704 /*
705 * Audio input somehow depends on HDMI line rate which is
706 * related to pixclk. Testing showed that modes with pixclk
707 * >100MHz need a larger divider while <40MHz need the default.
708 * There is no detailed info in the datasheet, so we just
709 * assume 100MHz requires larger divider.
710 */
2470fecc 711 adiv = AUDIO_DIV_SERCLK_8;
c4c11dd1 712 if (mode->clock > 100000)
2470fecc
JFM		 713 adiv++; /* AUDIO_DIV_SERCLK_16 */
714
715 /* S/PDIF asks for a larger divider */
716 if (p->audio_format == AFMT_SPDIF)
717 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
718
2f7f730a 719 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 720
721 /*
722 * This is the approximate value of N, which happens to be
723 * the recommended values for non-coherent clocks.
724 */
725 n = 128 * p->audio_sample_rate / 1000;
726
727 /* Write the CTS and N values */
728 buf[0] = 0x44;
729 buf[1] = 0x42;
730 buf[2] = 0x01;
731 buf[3] = n;
732 buf[4] = n >> 8;
733 buf[5] = n >> 16;
2f7f730a 734 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 735
736 /* Set CTS clock reference */
2f7f730a 737 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 738
739 /* Reset CTS generator */
2f7f730a
JFM		 740 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
741 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1
RK		 742
743 /* Write the channel status */
f0b33b28 744 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
c4c11dd1 745 buf[1] = 0x00;
f0b33b28
JFM		 746 buf[2] = IEC958_AES3_CON_FS_NOTID;
747 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
748 IEC958_AES4_CON_MAX_WORDLEN_24;
2f7f730a 749 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 750
2f7f730a 751 tda998x_audio_mute(priv, true);
73d5e253 752 msleep(20);
2f7f730a 753 tda998x_audio_mute(priv, false);
c4c11dd1
RK		 754
755 /* Write the audio information packet */
2f7f730a 756 tda998x_write_aif(priv, p);
c4c11dd1
RK		 757}
758
e7792ce2
RC		 759/* DRM encoder functions */
760
a8f4d4d6
RK		 761static void tda998x_encoder_set_config(struct tda998x_priv *priv,
762 const struct tda998x_encoder_params *p)
e7792ce2 763{
c4c11dd1
RK		 764 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
765 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
766 VIP_CNTRL_0_SWAP_B(p->swap_b) |
767 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
768 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
769 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
770 VIP_CNTRL_1_SWAP_D(p->swap_d) |
771 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
772 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
773 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
774 VIP_CNTRL_2_SWAP_F(p->swap_f) |
775 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
776
777 priv->params = *p;
e7792ce2
RC		 778}
779
a8f4d4d6 780static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode)
e7792ce2 781{
e7792ce2
RC		 782 /* we only care about on or off: */
783 if (mode != DRM_MODE_DPMS_ON)
784 mode = DRM_MODE_DPMS_OFF;
785
786 if (mode == priv->dpms)
787 return;
788
789 switch (mode) {
790 case DRM_MODE_DPMS_ON:
c4c11dd1 791 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 792 reg_write(priv, REG_ENA_VP_0, 0xff);
793 reg_write(priv, REG_ENA_VP_1, 0xff);
794 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 795 /* set muxing after enabling ports: */
2f7f730a
JFM		 796 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
797 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
798 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
e7792ce2
RC		 799 break;
800 case DRM_MODE_DPMS_OFF:
db6aaf4d 801 /* disable video ports */
2f7f730a
JFM		 802 reg_write(priv, REG_ENA_VP_0, 0x00);
803 reg_write(priv, REG_ENA_VP_1, 0x00);
804 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2
RC		 805 break;
806 }
807
808 priv->dpms = mode;
809}
810
811static void
812tda998x_encoder_save(struct drm_encoder *encoder)
813{
814 DBG("");
815}
816
817static void
818tda998x_encoder_restore(struct drm_encoder *encoder)
819{
820 DBG("");
821}
822
823static bool
824tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
825 const struct drm_display_mode *mode,
826 struct drm_display_mode *adjusted_mode)
827{
828 return true;
829}
830
a8f4d4d6
RK		 831static int tda998x_encoder_mode_valid(struct tda998x_priv *priv,
832 struct drm_display_mode *mode)
e7792ce2 833{
92fbdfcd
RK		 834 if (mode->clock > 150000)
835 return MODE_CLOCK_HIGH;
836 if (mode->htotal >= BIT(13))
837 return MODE_BAD_HVALUE;
838 if (mode->vtotal >= BIT(11))
839 return MODE_BAD_VVALUE;
e7792ce2
RC		 840 return MODE_OK;
841}
842
843static void
a8f4d4d6
RK		 844tda998x_encoder_mode_set(struct tda998x_priv *priv,
845 struct drm_display_mode *mode,
846 struct drm_display_mode *adjusted_mode)
e7792ce2 847{
088d61d1
SH		 848 uint16_t ref_pix, ref_line, n_pix, n_line;
849 uint16_t hs_pix_s, hs_pix_e;
850 uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
851 uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
852 uint16_t vwin1_line_s, vwin1_line_e;
853 uint16_t vwin2_line_s, vwin2_line_e;
854 uint16_t de_pix_s, de_pix_e;
e7792ce2
RC		 855 uint8_t reg, div, rep;
856
088d61d1
SH		 857 /*
858 * Internally TDA998x is using ITU-R BT.656 style sync but
859 * we get VESA style sync. TDA998x is using a reference pixel
860 * relative to ITU to sync to the input frame and for output
861 * sync generation. Currently, we are using reference detection
862 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
863 * which is position of rising VS with coincident rising HS.
864 *
865 * Now there is some issues to take care of:
866 * - HDMI data islands require sync-before-active
867 * - TDA998x register values must be > 0 to be enabled
868 * - REFLINE needs an additional offset of +1
869 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
870 *
871 * So we add +1 to all horizontal and vertical register values,
872 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 873 */
088d61d1
SH		 874 n_pix = mode->htotal;
875 n_line = mode->vtotal;
876
877 hs_pix_e = mode->hsync_end - mode->hdisplay;
878 hs_pix_s = mode->hsync_start - mode->hdisplay;
879 de_pix_e = mode->htotal;
880 de_pix_s = mode->htotal - mode->hdisplay;
881 ref_pix = 3 + hs_pix_s;
882
179f1aa4
SH		 883 /*
884 * Attached LCD controllers may generate broken sync. Allow
885 * those to adjust the position of the rising VS edge by adding
886 * HSKEW to ref_pix.
887 */
888 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
889 ref_pix += adjusted_mode->hskew;
890
088d61d1
SH		 891 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
892 ref_line = 1 + mode->vsync_start - mode->vdisplay;
893 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
894 vwin1_line_e = vwin1_line_s + mode->vdisplay;
895 vs1_pix_s = vs1_pix_e = hs_pix_s;
896 vs1_line_s = mode->vsync_start - mode->vdisplay;
897 vs1_line_e = vs1_line_s +
898 mode->vsync_end - mode->vsync_start;
899 vwin2_line_s = vwin2_line_e = 0;
900 vs2_pix_s = vs2_pix_e = 0;
901 vs2_line_s = vs2_line_e = 0;
902 } else {
903 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
904 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
905 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
906 vs1_pix_s = vs1_pix_e = hs_pix_s;
907 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
908 vs1_line_e = vs1_line_s +
909 (mode->vsync_end - mode->vsync_start)/2;
910 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
911 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
912 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
913 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
914 vs2_line_e = vs2_line_s +
915 (mode->vsync_end - mode->vsync_start)/2;
916 }
e7792ce2
RC		 917
918 div = 148500 / mode->clock;
3ae471f7
JFM		 919 if (div != 0) {
920 div--;
921 if (div > 3)
922 div = 3;
923 }
e7792ce2 924
e7792ce2 925 /* mute the audio FIFO: */
2f7f730a 926 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 927
928 /* set HDMI HDCP mode off: */
81b53a16 929 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
2f7f730a
JFM		 930 reg_clear(priv, REG_TX33, TX33_HDMI);
931 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 932
e7792ce2 933 /* no pre-filter or interpolator: */
2f7f730a 934 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 935 HVF_CNTRL_0_INTPOL(0));
2f7f730a
JFM		 936 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
937 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 938 VIP_CNTRL_4_BLC(0));
e7792ce2 939
2f7f730a 940 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
a8b517e5
JFM		 941 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
942 PLL_SERIAL_3_SRL_DE);
2f7f730a
JFM		 943 reg_write(priv, REG_SERIALIZER, 0);
944 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 945
946 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
947 rep = 0;
2f7f730a
JFM		 948 reg_write(priv, REG_RPT_CNTRL, 0);
949 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 950 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
951
2f7f730a 952 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 953 PLL_SERIAL_2_SRL_PR(rep));
954
e7792ce2 955 /* set color matrix bypass flag: */
81b53a16
JFM		 956 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
957 MAT_CONTRL_MAT_SC(1));
e7792ce2
RC		 958
959 /* set BIAS tmds value: */
2f7f730a 960 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 961
088d61d1
SH		 962 /*
963 * Sync on rising HSYNC/VSYNC
964 */
81b53a16 965 reg = VIP_CNTRL_3_SYNC_HS;
088d61d1
SH		 966
967 /*
968 * TDA19988 requires high-active sync at input stage,
969 * so invert low-active sync provided by master encoder here
970 */
971 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
81b53a16 972 reg |= VIP_CNTRL_3_H_TGL;
e7792ce2 973 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
81b53a16
JFM		 974 reg |= VIP_CNTRL_3_V_TGL;
975 reg_write(priv, REG_VIP_CNTRL_3, reg);
2f7f730a
JFM		 976
977 reg_write(priv, REG_VIDFORMAT, 0x00);
978 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
979 reg_write16(priv, REG_REFLINE_MSB, ref_line);
980 reg_write16(priv, REG_NPIX_MSB, n_pix);
981 reg_write16(priv, REG_NLINE_MSB, n_line);
982 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
983 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
984 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
985 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
986 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
987 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
988 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
989 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
990 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
991 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
992 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
993 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
994 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
995 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
996 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
997 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 998
999 if (priv->rev == TDA19988) {
1000 /* let incoming pixels fill the active space (if any) */
2f7f730a 1001 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 1002 }
1003
81b53a16
JFM		 1004 /*
1005 * Always generate sync polarity relative to input sync and
1006 * revert input stage toggled sync at output stage
1007 */
1008 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1009 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1010 reg |= TBG_CNTRL_1_H_TGL;
1011 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1012 reg |= TBG_CNTRL_1_V_TGL;
1013 reg_write(priv, REG_TBG_CNTRL_1, reg);
1014
e7792ce2 1015 /* must be last register set: */
81b53a16 1016 reg_write(priv, REG_TBG_CNTRL_0, 0);
c4c11dd1
RK		 1017
1018 /* Only setup the info frames if the sink is HDMI */
1019 if (priv->is_hdmi_sink) {
1020 /* We need to turn HDMI HDCP stuff on to get audio through */
81b53a16
JFM		 1021 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1022 reg_write(priv, REG_TBG_CNTRL_1, reg);
2f7f730a
JFM		 1023 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1024 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 1025
2f7f730a 1026 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1
RK		 1027
1028 if (priv->params.audio_cfg)
2f7f730a 1029 tda998x_configure_audio(priv, adjusted_mode,
c4c11dd1
RK		 1030 &priv->params);
1031 }
e7792ce2
RC		 1032}
1033
1034static enum drm_connector_status
a8f4d4d6 1035tda998x_encoder_detect(struct tda998x_priv *priv)
e7792ce2 1036{
2f7f730a
JFM		 1037 uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV);
1038
e7792ce2
RC		 1039 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1040 connector_status_disconnected;
1041}
1042
07259f8b 1043static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
e7792ce2 1044{
07259f8b 1045 struct tda998x_priv *priv = data;
e7792ce2
RC		 1046 uint8_t offset, segptr;
1047 int ret, i;
1048
e7792ce2
RC		 1049 offset = (blk & 1) ? 128 : 0;
1050 segptr = blk / 2;
1051
2f7f730a
JFM		 1052 reg_write(priv, REG_DDC_ADDR, 0xa0);
1053 reg_write(priv, REG_DDC_OFFS, offset);
1054 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1055 reg_write(priv, REG_DDC_SEGM, segptr);
e7792ce2
RC		 1056
1057 /* enable reading EDID: */
12473b7d 1058 priv->wq_edid_wait = 1;
2f7f730a 1059 reg_write(priv, REG_EDID_CTRL, 0x1);
e7792ce2
RC		 1060
1061 /* flag must be cleared by sw: */
2f7f730a 1062 reg_write(priv, REG_EDID_CTRL, 0x0);
e7792ce2
RC		 1063
1064 /* wait for block read to complete: */
12473b7d
JFM		 1065 if (priv->hdmi->irq) {
1066 i = wait_event_timeout(priv->wq_edid,
1067 !priv->wq_edid_wait,
1068 msecs_to_jiffies(100));
1069 if (i < 0) {
5e7fe2fe 1070 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
12473b7d
JFM		 1071 return i;
1072 }
1073 } else {
713456db
RK		 1074 for (i = 100; i > 0; i--) {
1075 msleep(1);
12473b7d
JFM		 1076 ret = reg_read(priv, REG_INT_FLAGS_2);
1077 if (ret < 0)
1078 return ret;
1079 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1080 break;
1081 }
e7792ce2
RC		 1082 }
1083
12473b7d 1084 if (i == 0) {
5e7fe2fe 1085 dev_err(&priv->hdmi->dev, "read edid timeout\n");
e7792ce2 1086 return -ETIMEDOUT;
12473b7d 1087 }
e7792ce2 1088
07259f8b
LP		 1089 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1090 if (ret != length) {
5e7fe2fe
RK		 1091 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1092 blk, ret);
e7792ce2
RC		 1093 return ret;
1094 }
1095
e7792ce2
RC		 1096 return 0;
1097}
1098
07259f8b
LP		 1099static int
1100tda998x_encoder_get_modes(struct tda998x_priv *priv,
1101 struct drm_connector *connector)
e7792ce2 1102{
07259f8b
LP		 1103 struct edid *edid;
1104 int n;
e7792ce2 1105
063b472f 1106 if (priv->rev == TDA19988)
2f7f730a 1107 reg_clear(priv, REG_TX4, TX4_PD_RAM);
063b472f 1108
07259f8b 1109 edid = drm_do_get_edid(connector, read_edid_block, priv);
e7792ce2 1110
063b472f 1111 if (priv->rev == TDA19988)
2f7f730a 1112 reg_set(priv, REG_TX4, TX4_PD_RAM);
063b472f 1113
07259f8b
LP		 1114 if (!edid) {
1115 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1116 return 0;
e7792ce2
RC		 1117 }
1118
07259f8b
LP		 1119 drm_mode_connector_update_edid_property(connector, edid);
1120 n = drm_add_edid_modes(connector, edid);
1121 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1122 kfree(edid);
1123
e7792ce2
RC		 1124 return n;
1125}
1126
a8f4d4d6
RK		 1127static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1128 struct drm_connector *connector)
e7792ce2 1129{
12473b7d
JFM		 1130 if (priv->hdmi->irq)
1131 connector->polled = DRM_CONNECTOR_POLL_HPD;
1132 else
1133 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1134 DRM_CONNECTOR_POLL_DISCONNECT;
e7792ce2
RC		 1135}
1136
1137static int
1138tda998x_encoder_set_property(struct drm_encoder *encoder,
1139 struct drm_connector *connector,
1140 struct drm_property *property,
1141 uint64_t val)
1142{
1143 DBG("");
1144 return 0;
1145}
1146
a8f4d4d6 1147static void tda998x_destroy(struct tda998x_priv *priv)
e7792ce2 1148{
12473b7d
JFM		 1149 /* disable all IRQs and free the IRQ handler */
1150 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1151 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
6833d26e 1152 if (priv->hdmi->irq) {
12473b7d 1153 free_irq(priv->hdmi->irq, priv);
6833d26e
JFM		 1154 cancel_delayed_work_sync(&priv->dwork);
1155 }
12473b7d 1156
89fc8686 1157 i2c_unregister_device(priv->cec);
a8f4d4d6
RK		 1158}
1159
1160/* Slave encoder support */
1161
1162static void
1163tda998x_encoder_slave_set_config(struct drm_encoder *encoder, void *params)
1164{
1165 tda998x_encoder_set_config(to_tda998x_priv(encoder), params);
1166}
1167
1168static void tda998x_encoder_slave_destroy(struct drm_encoder *encoder)
1169{
1170 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1171
1172 tda998x_destroy(priv);
2e48cecb 1173 drm_i2c_encoder_destroy(encoder);
e7792ce2
RC		 1174 kfree(priv);
1175}
1176
a8f4d4d6
RK		 1177static void tda998x_encoder_slave_dpms(struct drm_encoder *encoder, int mode)
1178{
1179 tda998x_encoder_dpms(to_tda998x_priv(encoder), mode);
1180}
e7792ce2 1181
a8f4d4d6
RK		 1182static int tda998x_encoder_slave_mode_valid(struct drm_encoder *encoder,
1183 struct drm_display_mode *mode)
1184{
1185 return tda998x_encoder_mode_valid(to_tda998x_priv(encoder), mode);
1186}
e7792ce2 1187
a8f4d4d6
RK		 1188static void
1189tda998x_encoder_slave_mode_set(struct drm_encoder *encoder,
1190 struct drm_display_mode *mode,
1191 struct drm_display_mode *adjusted_mode)
e7792ce2 1192{
a8f4d4d6
RK		 1193 tda998x_encoder_mode_set(to_tda998x_priv(encoder), mode, adjusted_mode);
1194}
1195
1196static enum drm_connector_status
1197tda998x_encoder_slave_detect(struct drm_encoder *encoder,
1198 struct drm_connector *connector)
1199{
1200 return tda998x_encoder_detect(to_tda998x_priv(encoder));
1201}
1202
1203static int tda998x_encoder_slave_get_modes(struct drm_encoder *encoder,
1204 struct drm_connector *connector)
1205{
1206 return tda998x_encoder_get_modes(to_tda998x_priv(encoder), connector);
e7792ce2
RC		 1207}
1208
1209static int
a8f4d4d6
RK		 1210tda998x_encoder_slave_create_resources(struct drm_encoder *encoder,
1211 struct drm_connector *connector)
e7792ce2 1212{
a8f4d4d6 1213 tda998x_encoder_set_polling(to_tda998x_priv(encoder), connector);
e7792ce2
RC		 1214 return 0;
1215}
1216
a8f4d4d6
RK		 1217static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs = {
1218 .set_config = tda998x_encoder_slave_set_config,
1219 .destroy = tda998x_encoder_slave_destroy,
1220 .dpms = tda998x_encoder_slave_dpms,
e7792ce2
RC		 1221 .save = tda998x_encoder_save,
1222 .restore = tda998x_encoder_restore,
1223 .mode_fixup = tda998x_encoder_mode_fixup,
a8f4d4d6
RK		 1224 .mode_valid = tda998x_encoder_slave_mode_valid,
1225 .mode_set = tda998x_encoder_slave_mode_set,
1226 .detect = tda998x_encoder_slave_detect,
1227 .get_modes = tda998x_encoder_slave_get_modes,
1228 .create_resources = tda998x_encoder_slave_create_resources,
e7792ce2
RC		 1229 .set_property = tda998x_encoder_set_property,
1230};
1231
1232/* I2C driver functions */
1233
a8f4d4d6 1234static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
e7792ce2 1235{
0d44ea19
JFM		 1236 struct device_node *np = client->dev.of_node;
1237 u32 video;
fb7544d7 1238 int rev_lo, rev_hi, ret;
cfe38757 1239 unsigned short cec_addr;
e7792ce2 1240
5e74c22c
RK		 1241 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1242 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1243 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1244
2eb4c7b1 1245 priv->current_page = 0xff;
2f7f730a 1246 priv->hdmi = client;
cfe38757
AJ		 1247 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1248 cec_addr = 0x34 + (client->addr & 0x03);
1249 priv->cec = i2c_new_dummy(client->adapter, cec_addr);
a8f4d4d6 1250 if (!priv->cec)
6ae668cc 1251 return -ENODEV;
12473b7d 1252
e7792ce2
RC		 1253 priv->dpms = DRM_MODE_DPMS_OFF;
1254
ed9a8426
JFM		 1255 mutex_init(&priv->mutex); /* protect the page access */
1256
e7792ce2 1257 /* wake up the device: */
2f7f730a 1258 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1259 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1260
2f7f730a 1261 tda998x_reset(priv);
e7792ce2
RC		 1262
1263 /* read version: */
fb7544d7
RK		 1264 rev_lo = reg_read(priv, REG_VERSION_LSB);
1265 rev_hi = reg_read(priv, REG_VERSION_MSB);
1266 if (rev_lo < 0 || rev_hi < 0) {
1267 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1268 goto fail;
fb7544d7
RK		 1269 }
1270
1271 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1272
1273 /* mask off feature bits: */
1274 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1275
1276 switch (priv->rev) {
b728fab7
JFM		 1277 case TDA9989N2:
1278 dev_info(&client->dev, "found TDA9989 n2");
1279 break;
1280 case TDA19989:
1281 dev_info(&client->dev, "found TDA19989");
1282 break;
1283 case TDA19989N2:
1284 dev_info(&client->dev, "found TDA19989 n2");
1285 break;
1286 case TDA19988:
1287 dev_info(&client->dev, "found TDA19988");
1288 break;
e7792ce2 1289 default:
b728fab7
JFM		 1290 dev_err(&client->dev, "found unsupported device: %04x\n",
1291 priv->rev);
e7792ce2
RC		 1292 goto fail;
1293 }
1294
1295 /* after reset, enable DDC: */
2f7f730a 1296 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1297
1298 /* set clock on DDC channel: */
2f7f730a 1299 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1300
1301 /* if necessary, disable multi-master: */
1302 if (priv->rev == TDA19989)
2f7f730a 1303 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1304
2f7f730a 1305 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1306 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1307
12473b7d
JFM		 1308 /* initialize the optional IRQ */
1309 if (client->irq) {
1310 int irqf_trigger;
1311
6833d26e 1312 /* init read EDID waitqueue and HDP work */
12473b7d 1313 init_waitqueue_head(&priv->wq_edid);
6833d26e 1314 INIT_DELAYED_WORK(&priv->dwork, tda998x_hpd);
12473b7d
JFM		 1315
1316 /* clear pending interrupts */
1317 reg_read(priv, REG_INT_FLAGS_0);
1318 reg_read(priv, REG_INT_FLAGS_1);
1319 reg_read(priv, REG_INT_FLAGS_2);
1320
1321 irqf_trigger =
1322 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1323 ret = request_threaded_irq(client->irq, NULL,
1324 tda998x_irq_thread,
1325 irqf_trigger | IRQF_ONESHOT,
1326 "tda998x", priv);
1327 if (ret) {
1328 dev_err(&client->dev,
1329 "failed to request IRQ#%u: %d\n",
1330 client->irq, ret);
1331 goto fail;
1332 }
1333
1334 /* enable HPD irq */
1335 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1336 }
1337
e4782627
JFM		 1338 /* enable EDID read irq: */
1339 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1340
0d44ea19
JFM		 1341 if (!np)
1342 return 0; /* non-DT */
1343
1344 /* get the optional video properties */
1345 ret = of_property_read_u32(np, "video-ports", &video);
1346 if (ret == 0) {
1347 priv->vip_cntrl_0 = video >> 16;
1348 priv->vip_cntrl_1 = video >> 8;
1349 priv->vip_cntrl_2 = video;
1350 }
1351
e7792ce2
RC		 1352 return 0;
1353
1354fail:
1355 /* if encoder_init fails, the encoder slave is never registered,
1356 * so cleanup here:
1357 */
1358 if (priv->cec)
1359 i2c_unregister_device(priv->cec);
e7792ce2
RC		 1360 return -ENXIO;
1361}
1362
a8f4d4d6
RK		 1363static int tda998x_encoder_init(struct i2c_client *client,
1364 struct drm_device *dev,
1365 struct drm_encoder_slave *encoder_slave)
1366{
1367 struct tda998x_priv *priv;
1368 int ret;
1369
1370 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1371 if (!priv)
1372 return -ENOMEM;
1373
1374 priv->encoder = &encoder_slave->base;
1375
1376 ret = tda998x_create(client, priv);
1377 if (ret) {
1378 kfree(priv);
1379 return ret;
1380 }
1381
1382 encoder_slave->slave_priv = priv;
1383 encoder_slave->slave_funcs = &tda998x_encoder_slave_funcs;
1384
1385 return 0;
1386}
1387
c707c361
RK		 1388struct tda998x_priv2 {
1389 struct tda998x_priv base;
1390 struct drm_encoder encoder;
1391 struct drm_connector connector;
1392};
1393
1394#define conn_to_tda998x_priv2(x) \
1395 container_of(x, struct tda998x_priv2, connector);
1396
1397#define enc_to_tda998x_priv2(x) \
1398 container_of(x, struct tda998x_priv2, encoder);
1399
1400static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode)
1401{
1402 struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1403
1404 tda998x_encoder_dpms(&priv->base, mode);
1405}
1406
1407static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1408{
1409 tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF);
1410}
1411
1412static void tda998x_encoder_commit(struct drm_encoder *encoder)
1413{
1414 tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON);
1415}
1416
1417static void tda998x_encoder2_mode_set(struct drm_encoder *encoder,
1418 struct drm_display_mode *mode,
1419 struct drm_display_mode *adjusted_mode)
1420{
1421 struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1422
1423 tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode);
1424}
1425
1426static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1427 .dpms = tda998x_encoder2_dpms,
1428 .save = tda998x_encoder_save,
1429 .restore = tda998x_encoder_restore,
1430 .mode_fixup = tda998x_encoder_mode_fixup,
1431 .prepare = tda998x_encoder_prepare,
1432 .commit = tda998x_encoder_commit,
1433 .mode_set = tda998x_encoder2_mode_set,
1434};
1435
1436static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1437{
1438 struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1439
1440 tda998x_destroy(&priv->base);
1441 drm_encoder_cleanup(encoder);
1442}
1443
1444static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1445 .destroy = tda998x_encoder_destroy,
1446};
1447
1448static int tda998x_connector_get_modes(struct drm_connector *connector)
1449{
1450 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1451
1452 return tda998x_encoder_get_modes(&priv->base, connector);
1453}
1454
1455static int tda998x_connector_mode_valid(struct drm_connector *connector,
1456 struct drm_display_mode *mode)
1457{
1458 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1459
1460 return tda998x_encoder_mode_valid(&priv->base, mode);
1461}
1462
1463static struct drm_encoder *
1464tda998x_connector_best_encoder(struct drm_connector *connector)
1465{
1466 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1467
1468 return &priv->encoder;
1469}
1470
1471static
1472const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1473 .get_modes = tda998x_connector_get_modes,
1474 .mode_valid = tda998x_connector_mode_valid,
1475 .best_encoder = tda998x_connector_best_encoder,
1476};
1477
1478static enum drm_connector_status
1479tda998x_connector_detect(struct drm_connector *connector, bool force)
1480{
1481 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1482
1483 return tda998x_encoder_detect(&priv->base);
1484}
1485
1486static void tda998x_connector_destroy(struct drm_connector *connector)
1487{
74cd62ea 1488 drm_connector_unregister(connector);
c707c361
RK		 1489 drm_connector_cleanup(connector);
1490}
1491
1492static const struct drm_connector_funcs tda998x_connector_funcs = {
1493 .dpms = drm_helper_connector_dpms,
1494 .fill_modes = drm_helper_probe_single_connector_modes,
1495 .detect = tda998x_connector_detect,
1496 .destroy = tda998x_connector_destroy,
1497};
1498
1499static int tda998x_bind(struct device *dev, struct device *master, void *data)
1500{
1501 struct tda998x_encoder_params *params = dev->platform_data;
1502 struct i2c_client *client = to_i2c_client(dev);
1503 struct drm_device *drm = data;
1504 struct tda998x_priv2 *priv;
5dbcf319 1505 uint32_t crtcs = 0;
c707c361
RK		 1506 int ret;
1507
1508 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1509 if (!priv)
1510 return -ENOMEM;
1511
1512 dev_set_drvdata(dev, priv);
1513
5dbcf319
RK		 1514 if (dev->of_node)
1515 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1516
1517 /* If no CRTCs were found, fall back to our old behaviour */
1518 if (crtcs == 0) {
1519 dev_warn(dev, "Falling back to first CRTC\n");
1520 crtcs = 1 << 0;
1521 }
1522
c707c361
RK		 1523 priv->base.encoder = &priv->encoder;
1524 priv->connector.interlace_allowed = 1;
5dbcf319 1525 priv->encoder.possible_crtcs = crtcs;
c707c361
RK		 1526
1527 ret = tda998x_create(client, &priv->base);
1528 if (ret)
1529 return ret;
1530
1531 if (!dev->of_node && params)
1532 tda998x_encoder_set_config(&priv->base, params);
1533
1534 tda998x_encoder_set_polling(&priv->base, &priv->connector);
1535
1536 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1537 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1538 DRM_MODE_ENCODER_TMDS);
1539 if (ret)
1540 goto err_encoder;
1541
1542 drm_connector_helper_add(&priv->connector,
1543 &tda998x_connector_helper_funcs);
1544 ret = drm_connector_init(drm, &priv->connector,
1545 &tda998x_connector_funcs,
1546 DRM_MODE_CONNECTOR_HDMIA);
1547 if (ret)
1548 goto err_connector;
1549
74cd62ea 1550 ret = drm_connector_register(&priv->connector);
c707c361
RK		 1551 if (ret)
1552 goto err_sysfs;
1553
1554 priv->connector.encoder = &priv->encoder;
1555 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1556
1557 return 0;
1558
1559err_sysfs:
1560 drm_connector_cleanup(&priv->connector);
1561err_connector:
1562 drm_encoder_cleanup(&priv->encoder);
1563err_encoder:
1564 tda998x_destroy(&priv->base);
1565 return ret;
1566}
1567
1568static void tda998x_unbind(struct device *dev, struct device *master,
1569 void *data)
1570{
1571 struct tda998x_priv2 *priv = dev_get_drvdata(dev);
1572
1573 drm_connector_cleanup(&priv->connector);
1574 drm_encoder_cleanup(&priv->encoder);
1575 tda998x_destroy(&priv->base);
1576}
1577
1578static const struct component_ops tda998x_ops = {
1579 .bind = tda998x_bind,
1580 .unbind = tda998x_unbind,
1581};
1582
1583static int
1584tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1585{
1586 return component_add(&client->dev, &tda998x_ops);
1587}
1588
1589static int tda998x_remove(struct i2c_client *client)
1590{
1591 component_del(&client->dev, &tda998x_ops);
1592 return 0;
1593}
1594
0d44ea19
JFM		 1595#ifdef CONFIG_OF
1596static const struct of_device_id tda998x_dt_ids[] = {
1597 { .compatible = "nxp,tda998x", },
1598 { }
1599};
1600MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1601#endif
1602
e7792ce2
RC		 1603static struct i2c_device_id tda998x_ids[] = {
1604 { "tda998x", 0 },
1605 { }
1606};
1607MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1608
1609static struct drm_i2c_encoder_driver tda998x_driver = {
1610 .i2c_driver = {
1611 .probe = tda998x_probe,
1612 .remove = tda998x_remove,
1613 .driver = {
1614 .name = "tda998x",
0d44ea19 1615 .of_match_table = of_match_ptr(tda998x_dt_ids),
e7792ce2
RC		 1616 },
1617 .id_table = tda998x_ids,
1618 },
1619 .encoder_init = tda998x_encoder_init,
1620};
1621
1622/* Module initialization */
1623
1624static int __init
1625tda998x_init(void)
1626{
1627 DBG("");
1628 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1629}
1630
1631static void __exit
1632tda998x_exit(void)
1633{
1634 DBG("");
1635 drm_i2c_encoder_unregister(&tda998x_driver);
1636}
1637
1638MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1639MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1640MODULE_LICENSE("GPL");
1641
1642module_init(tda998x_init);
1643module_exit(tda998x_exit);
Linux 6.x block layer and io_uring tree(s)