projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i2c: tda998x: convert to u8/u16/u32 types
[linux-2.6-block.git] / drivers / gpu / drm / i2c / tda998x_drv.c
CommitLineData
e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
c707c361 18#include <linux/component.h>
893c3e53 19#include <linux/hdmi.h>
e7792ce2 20#include <linux/module.h>
12473b7d 21#include <linux/irq.h>
f0b33b28 22#include <sound/asoundef.h>
e7792ce2
RC		 23
24#include <drm/drmP.h>
25#include <drm/drm_crtc_helper.h>
26#include <drm/drm_encoder_slave.h>
27#include <drm/drm_edid.h>
5dbcf319 28#include <drm/drm_of.h>
c4c11dd1 29#include <drm/i2c/tda998x.h>
e7792ce2
RC		 30
31#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
32
33struct tda998x_priv {
34 struct i2c_client *cec;
2f7f730a 35 struct i2c_client *hdmi;
ed9a8426 36 struct mutex mutex;
e66e03ab
RK		 37 u16 rev;
38 u8 current_page;
e7792ce2 39 int dpms;
c4c11dd1 40 bool is_hdmi_sink;
5e74c22c
RK		 41 u8 vip_cntrl_0;
42 u8 vip_cntrl_1;
43 u8 vip_cntrl_2;
c4c11dd1 44 struct tda998x_encoder_params params;
12473b7d
JFM		 45
46 wait_queue_head_t wq_edid;
47 volatile int wq_edid_wait;
48 struct drm_encoder *encoder;
0fc6f44d
RK		 49
50 struct work_struct detect_work;
51 struct timer_list edid_delay_timer;
52 wait_queue_head_t edid_delay_waitq;
53 bool edid_delay_active;
e7792ce2
RC		 54};
55
56#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv)
57
58/* The TDA9988 series of devices use a paged register scheme.. to simplify
59 * things we encode the page # in upper bits of the register #. To read/
60 * write a given register, we need to make sure CURPAGE register is set
61 * appropriately. Which implies reads/writes are not atomic. Fun!
62 */
63
64#define REG(page, addr) (((page) << 8) | (addr))
65#define REG2ADDR(reg) ((reg) & 0xff)
66#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
67
68#define REG_CURPAGE 0xff /* write */
69
70
71/* Page 00h: General Control */
72#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
73#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
74# define MAIN_CNTRL0_SR (1 << 0)
75# define MAIN_CNTRL0_DECS (1 << 1)
76# define MAIN_CNTRL0_DEHS (1 << 2)
77# define MAIN_CNTRL0_CECS (1 << 3)
78# define MAIN_CNTRL0_CEHS (1 << 4)
79# define MAIN_CNTRL0_SCALER (1 << 7)
80#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
81#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
82# define SOFTRESET_AUDIO (1 << 0)
83# define SOFTRESET_I2C_MASTER (1 << 1)
84#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
85#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
86#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
87# define I2C_MASTER_DIS_MM (1 << 0)
88# define I2C_MASTER_DIS_FILT (1 << 1)
89# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1
RK		 90#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
91# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 92#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
93#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
94#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
95# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 96#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 97#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
98#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
99#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
100#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
101#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
102# define VIP_CNTRL_0_MIRR_A (1 << 7)
103# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
104# define VIP_CNTRL_0_MIRR_B (1 << 3)
105# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
106#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
107# define VIP_CNTRL_1_MIRR_C (1 << 7)
108# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
109# define VIP_CNTRL_1_MIRR_D (1 << 3)
110# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
111#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
112# define VIP_CNTRL_2_MIRR_E (1 << 7)
113# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
114# define VIP_CNTRL_2_MIRR_F (1 << 3)
115# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
116#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
117# define VIP_CNTRL_3_X_TGL (1 << 0)
118# define VIP_CNTRL_3_H_TGL (1 << 1)
119# define VIP_CNTRL_3_V_TGL (1 << 2)
120# define VIP_CNTRL_3_EMB (1 << 3)
121# define VIP_CNTRL_3_SYNC_DE (1 << 4)
122# define VIP_CNTRL_3_SYNC_HS (1 << 5)
123# define VIP_CNTRL_3_DE_INT (1 << 6)
124# define VIP_CNTRL_3_EDGE (1 << 7)
125#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
126# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
127# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
128# define VIP_CNTRL_4_CCIR656 (1 << 4)
129# define VIP_CNTRL_4_656_ALT (1 << 5)
130# define VIP_CNTRL_4_TST_656 (1 << 6)
131# define VIP_CNTRL_4_TST_PAT (1 << 7)
132#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
133# define VIP_CNTRL_5_CKCASE (1 << 0)
134# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 135#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
10df1a95
JFM		 136# define MUX_AP_SELECT_I2S 0x64
137# define MUX_AP_SELECT_SPDIF 0x40
bcb2481d 138#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 139#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
140# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
141# define MAT_CONTRL_MAT_BP (1 << 2)
142#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
143#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
144#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
145#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
146#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
147#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
148#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
149#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
150#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
151#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
152#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
153#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
154#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
155#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
156#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
157#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
158#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 159#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
160#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 161#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
162#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 163#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
164#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 165#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
166#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
167#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
168#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
169#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
170#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
171#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
172#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
173#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
174#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 175#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
176#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
177#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
178#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 179#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
180#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
181#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
182#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
183#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 184# define TBG_CNTRL_0_TOP_TGL (1 << 0)
185# define TBG_CNTRL_0_TOP_SEL (1 << 1)
186# define TBG_CNTRL_0_DE_EXT (1 << 2)
187# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 188# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
189# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
190# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
191#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 192# define TBG_CNTRL_1_H_TGL (1 << 0)
193# define TBG_CNTRL_1_V_TGL (1 << 1)
194# define TBG_CNTRL_1_TGL_EN (1 << 2)
195# define TBG_CNTRL_1_X_EXT (1 << 3)
196# define TBG_CNTRL_1_H_EXT (1 << 4)
197# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 198# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
199#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
200#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
201# define HVF_CNTRL_0_SM (1 << 7)
202# define HVF_CNTRL_0_RWB (1 << 6)
203# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
204# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
205#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
206# define HVF_CNTRL_1_FOR (1 << 0)
207# define HVF_CNTRL_1_YUVBLK (1 << 1)
208# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
209# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
210# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
211#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 212#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
213# define I2S_FORMAT(x) (((x) & 3) << 0)
214#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
10df1a95
JFM		 215# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
216# define AIP_CLKSEL_AIP_I2S (1 << 3)
217# define AIP_CLKSEL_FS_ACLK (0 << 0)
218# define AIP_CLKSEL_FS_MCLK (1 << 0)
219# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
e7792ce2
RC		 220
221/* Page 02h: PLL settings */
222#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
223# define PLL_SERIAL_1_SRL_FDN (1 << 0)
224# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
225# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
226#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 227# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 228# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
229#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
230# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
231# define PLL_SERIAL_3_SRL_DE (1 << 2)
232# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
233#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
234#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
235#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
236#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
237#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
238#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
239#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
240#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
241#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 242# define AUDIO_DIV_SERCLK_1 0
243# define AUDIO_DIV_SERCLK_2 1
244# define AUDIO_DIV_SERCLK_4 2
245# define AUDIO_DIV_SERCLK_8 3
246# define AUDIO_DIV_SERCLK_16 4
247# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 248#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
249# define SEL_CLK_SEL_CLK1 (1 << 0)
250# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
251# define SEL_CLK_ENA_SC_CLK (1 << 3)
252#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
253
254
255/* Page 09h: EDID Control */
256#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
257/* next 127 successive registers are the EDID block */
258#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
259#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
260#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
261#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
262#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
263
264
265/* Page 10h: information frames and packets */
c4c11dd1
RK		 266#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
267#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
268#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
269#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
270#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 271
272
273/* Page 11h: audio settings and content info packets */
274#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
275# define AIP_CNTRL_0_RST_FIFO (1 << 0)
276# define AIP_CNTRL_0_SWAP (1 << 1)
277# define AIP_CNTRL_0_LAYOUT (1 << 2)
278# define AIP_CNTRL_0_ACR_MAN (1 << 5)
279# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 280#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
281# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
282# define CA_I2S_HBR_CHSTAT (1 << 6)
283#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
284#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
285#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
286#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
287#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
288#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
289#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
290#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
291# define CTS_N_K(x) (((x) & 7) << 0)
292# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 293#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
294# define ENC_CNTRL_RST_ENC (1 << 0)
295# define ENC_CNTRL_RST_SEL (1 << 1)
296# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 297#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
298# define DIP_FLAGS_ACR (1 << 0)
299# define DIP_FLAGS_GC (1 << 1)
300#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
301# define DIP_IF_FLAGS_IF1 (1 << 1)
302# define DIP_IF_FLAGS_IF2 (1 << 2)
303# define DIP_IF_FLAGS_IF3 (1 << 3)
304# define DIP_IF_FLAGS_IF4 (1 << 4)
305# define DIP_IF_FLAGS_IF5 (1 << 5)
306#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 307
308
309/* Page 12h: HDCP and OTP */
310#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 311#define REG_TX4 REG(0x12, 0x9b) /* read/write */
312# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 313#define REG_TX33 REG(0x12, 0xb8) /* read/write */
314# define TX33_HDMI (1 << 1)
315
316
317/* Page 13h: Gamut related metadata packets */
318
319
320
321/* CEC registers: (not paged)
322 */
12473b7d
JFM		 323#define REG_CEC_INTSTATUS 0xee /* read */
324# define CEC_INTSTATUS_CEC (1 << 0)
325# define CEC_INTSTATUS_HDMI (1 << 1)
e7792ce2
RC		 326#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
327# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
328# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
329# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
330# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
12473b7d
JFM		 331#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
332#define REG_CEC_RXSHPDINT 0xfd /* read */
e7792ce2
RC		 333#define REG_CEC_RXSHPDLEV 0xfe /* read */
334# define CEC_RXSHPDLEV_RXSENS (1 << 0)
335# define CEC_RXSHPDLEV_HPD (1 << 1)
336
337#define REG_CEC_ENAMODS 0xff /* read/write */
338# define CEC_ENAMODS_DIS_FRO (1 << 6)
339# define CEC_ENAMODS_DIS_CCLK (1 << 5)
340# define CEC_ENAMODS_EN_RXSENS (1 << 2)
341# define CEC_ENAMODS_EN_HDMI (1 << 1)
342# define CEC_ENAMODS_EN_CEC (1 << 0)
343
344
345/* Device versions: */
346#define TDA9989N2 0x0101
347#define TDA19989 0x0201
348#define TDA19989N2 0x0202
349#define TDA19988 0x0301
350
351static void
e66e03ab 352cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
e7792ce2 353{
2f7f730a 354 struct i2c_client *client = priv->cec;
e66e03ab 355 u8 buf[] = {addr, val};
e7792ce2
RC		 356 int ret;
357
704d63f5 358 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 359 if (ret < 0)
360 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
361}
362
e66e03ab
RK		 363static u8
364cec_read(struct tda998x_priv *priv, u8 addr)
e7792ce2 365{
2f7f730a 366 struct i2c_client *client = priv->cec;
e66e03ab 367 u8 val;
e7792ce2
RC		 368 int ret;
369
370 ret = i2c_master_send(client, &addr, sizeof(addr));
371 if (ret < 0)
372 goto fail;
373
374 ret = i2c_master_recv(client, &val, sizeof(val));
375 if (ret < 0)
376 goto fail;
377
378 return val;
379
380fail:
381 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
382 return 0;
383}
384
7d2eadc9 385static int
e66e03ab 386set_page(struct tda998x_priv *priv, u16 reg)
e7792ce2 387{
e7792ce2 388 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 389 struct i2c_client *client = priv->hdmi;
e66e03ab 390 u8 buf[] = {
e7792ce2
RC		 391 REG_CURPAGE, REG2PAGE(reg)
392 };
393 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 394 if (ret < 0) {
288ffc73 395 dev_err(&client->dev, "%s %04x err %d\n", __func__,
704d63f5 396 reg, ret);
7d2eadc9
JFM		 397 return ret;
398 }
e7792ce2
RC		 399
400 priv->current_page = REG2PAGE(reg);
401 }
7d2eadc9 402 return 0;
e7792ce2
RC		 403}
404
405static int
e66e03ab 406reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
e7792ce2 407{
2f7f730a 408 struct i2c_client *client = priv->hdmi;
e66e03ab 409 u8 addr = REG2ADDR(reg);
e7792ce2
RC		 410 int ret;
411
ed9a8426 412 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 413 ret = set_page(priv, reg);
414 if (ret < 0)
ed9a8426 415 goto out;
e7792ce2
RC		 416
417 ret = i2c_master_send(client, &addr, sizeof(addr));
418 if (ret < 0)
419 goto fail;
420
421 ret = i2c_master_recv(client, buf, cnt);
422 if (ret < 0)
423 goto fail;
424
ed9a8426 425 goto out;
e7792ce2
RC		 426
427fail:
428 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
ed9a8426
JFM		 429out:
430 mutex_unlock(&priv->mutex);
e7792ce2
RC		 431 return ret;
432}
433
c4c11dd1 434static void
e66e03ab 435reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
c4c11dd1 436{
2f7f730a 437 struct i2c_client *client = priv->hdmi;
e66e03ab 438 u8 buf[cnt+1];
c4c11dd1
RK		 439 int ret;
440
441 buf[0] = REG2ADDR(reg);
442 memcpy(&buf[1], p, cnt);
443
ed9a8426 444 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 445 ret = set_page(priv, reg);
446 if (ret < 0)
ed9a8426 447 goto out;
c4c11dd1
RK		 448
449 ret = i2c_master_send(client, buf, cnt + 1);
450 if (ret < 0)
451 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 452out:
453 mutex_unlock(&priv->mutex);
c4c11dd1
RK		 454}
455
7d2eadc9 456static int
e66e03ab 457reg_read(struct tda998x_priv *priv, u16 reg)
e7792ce2 458{
e66e03ab 459 u8 val = 0;
7d2eadc9
JFM		 460 int ret;
461
462 ret = reg_read_range(priv, reg, &val, sizeof(val));
463 if (ret < 0)
464 return ret;
e7792ce2
RC		 465 return val;
466}
467
468static void
e66e03ab 469reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 470{
2f7f730a 471 struct i2c_client *client = priv->hdmi;
e66e03ab 472 u8 buf[] = {REG2ADDR(reg), val};
e7792ce2
RC		 473 int ret;
474
ed9a8426 475 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 476 ret = set_page(priv, reg);
477 if (ret < 0)
ed9a8426 478 goto out;
e7792ce2 479
704d63f5 480 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 481 if (ret < 0)
482 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 483out:
484 mutex_unlock(&priv->mutex);
e7792ce2
RC		 485}
486
487static void
e66e03ab 488reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
e7792ce2 489{
2f7f730a 490 struct i2c_client *client = priv->hdmi;
e66e03ab 491 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
e7792ce2
RC		 492 int ret;
493
ed9a8426 494 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 495 ret = set_page(priv, reg);
496 if (ret < 0)
ed9a8426 497 goto out;
e7792ce2 498
704d63f5 499 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 500 if (ret < 0)
501 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 502out:
503 mutex_unlock(&priv->mutex);
e7792ce2
RC		 504}
505
506static void
e66e03ab 507reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 508{
7d2eadc9
JFM		 509 int old_val;
510
511 old_val = reg_read(priv, reg);
512 if (old_val >= 0)
513 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 514}
515
516static void
e66e03ab 517reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 518{
7d2eadc9
JFM		 519 int old_val;
520
521 old_val = reg_read(priv, reg);
522 if (old_val >= 0)
523 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 524}
525
526static void
2f7f730a 527tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 528{
529 /* reset audio and i2c master: */
81b53a16 530 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 531 msleep(50);
81b53a16 532 reg_write(priv, REG_SOFTRESET, 0);
e7792ce2
RC		 533 msleep(50);
534
535 /* reset transmitter: */
2f7f730a
JFM		 536 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
537 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 538
539 /* PLL registers common configuration */
2f7f730a
JFM		 540 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
541 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
542 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
543 reg_write(priv, REG_SERIALIZER, 0x00);
544 reg_write(priv, REG_BUFFER_OUT, 0x00);
545 reg_write(priv, REG_PLL_SCG1, 0x00);
546 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
547 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
548 reg_write(priv, REG_PLL_SCGN1, 0xfa);
549 reg_write(priv, REG_PLL_SCGN2, 0x00);
550 reg_write(priv, REG_PLL_SCGR1, 0x5b);
551 reg_write(priv, REG_PLL_SCGR2, 0x00);
552 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 553
554 /* Write the default value MUX register */
2f7f730a 555 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 556}
557
0fc6f44d
RK		 558/*
559 * The TDA998x has a problem when trying to read the EDID close to a
560 * HPD assertion: it needs a delay of 100ms to avoid timing out while
561 * trying to read EDID data.
562 *
563 * However, tda998x_encoder_get_modes() may be called at any moment
564 * after tda998x_encoder_detect() indicates that we are connected, so
565 * we need to delay probing modes in tda998x_encoder_get_modes() after
566 * we have seen a HPD inactive->active transition. This code implements
567 * that delay.
568 */
569static void tda998x_edid_delay_done(unsigned long data)
570{
571 struct tda998x_priv *priv = (struct tda998x_priv *)data;
572
573 priv->edid_delay_active = false;
574 wake_up(&priv->edid_delay_waitq);
575 schedule_work(&priv->detect_work);
576}
577
578static void tda998x_edid_delay_start(struct tda998x_priv *priv)
579{
580 priv->edid_delay_active = true;
581 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
582}
583
584static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
585{
586 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
587}
588
589/*
590 * We need to run the KMS hotplug event helper outside of our threaded
591 * interrupt routine as this can call back into our get_modes method,
592 * which will want to make use of interrupts.
593 */
594static void tda998x_detect_work(struct work_struct *work)
6833d26e 595{
6833d26e 596 struct tda998x_priv *priv =
0fc6f44d
RK		 597 container_of(work, struct tda998x_priv, detect_work);
598 struct drm_device *dev = priv->encoder->dev;
6833d26e 599
0fc6f44d
RK		 600 if (dev)
601 drm_kms_helper_hotplug_event(dev);
6833d26e
JFM		 602}
603
12473b7d
JFM		 604/*
605 * only 2 interrupts may occur: screen plug/unplug and EDID read
606 */
607static irqreturn_t tda998x_irq_thread(int irq, void *data)
608{
609 struct tda998x_priv *priv = data;
610 u8 sta, cec, lvl, flag0, flag1, flag2;
f84a97d4 611 bool handled = false;
12473b7d 612
12473b7d
JFM		 613 sta = cec_read(priv, REG_CEC_INTSTATUS);
614 cec = cec_read(priv, REG_CEC_RXSHPDINT);
615 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
616 flag0 = reg_read(priv, REG_INT_FLAGS_0);
617 flag1 = reg_read(priv, REG_INT_FLAGS_1);
618 flag2 = reg_read(priv, REG_INT_FLAGS_2);
619 DRM_DEBUG_DRIVER(
620 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
621 sta, cec, lvl, flag0, flag1, flag2);
622 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
623 priv->wq_edid_wait = 0;
624 wake_up(&priv->wq_edid);
f84a97d4 625 handled = true;
12473b7d 626 } else if (cec != 0) { /* HPD change */
0fc6f44d
RK		 627 if (lvl & CEC_RXSHPDLEV_HPD)
628 tda998x_edid_delay_start(priv);
629 else
630 schedule_work(&priv->detect_work);
631
f84a97d4 632 handled = true;
12473b7d 633 }
f84a97d4 634 return IRQ_RETVAL(handled);
12473b7d
JFM		 635}
636
e66e03ab 637static u8 tda998x_cksum(u8 *buf, size_t bytes)
c4c11dd1 638{
8268bd48 639 int sum = 0;
c4c11dd1
RK		 640
641 while (bytes--)
8268bd48
DV		 642 sum -= *buf++;
643 return sum;
c4c11dd1
RK		 644}
645
646#define HB(x) (x)
647#define PB(x) (HB(2) + 1 + (x))
648
649static void
e66e03ab
RK		 650tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
651 u8 *buf, size_t size)
c4c11dd1 652{
2f7f730a
JFM		 653 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
654 reg_write_range(priv, addr, buf, size);
655 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 656}
657
658static void
2f7f730a 659tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
c4c11dd1 660{
9e541466 661 u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1];
c4c11dd1 662
7288ca07 663 memset(buf, 0, sizeof(buf));
9e541466 664 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO;
c4c11dd1 665 buf[HB(1)] = 0x01;
9e541466 666 buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE;
c4c11dd1
RK		 667 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */
668 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */
669 buf[PB(4)] = p->audio_frame[4];
670 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */
671
4a6ca1a2
JFM		 672 buf[PB(0)] = tda998x_cksum(buf, sizeof(buf));
673
2f7f730a 674 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf,
c4c11dd1
RK		 675 sizeof(buf));
676}
677
678static void
2f7f730a 679tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 680{
8c7a075d
RK		 681 struct hdmi_avi_infoframe frame;
682 u8 buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
683 ssize_t len;
c4c11dd1 684
8c7a075d
RK		 685 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
686
687 frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
688
689 len = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf));
690 if (len < 0) {
5296b7f9
RK		 691 dev_err(&priv->hdmi->dev,
692 "hdmi_avi_infoframe_pack() failed: %zd\n", len);
8c7a075d
RK		 693 return;
694 }
695
696 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, len);
c4c11dd1
RK		 697}
698
2f7f730a 699static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 700{
701 if (on) {
2f7f730a
JFM		 702 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
703 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
704 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 705 } else {
2f7f730a 706 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 707 }
708}
709
710static void
2f7f730a 711tda998x_configure_audio(struct tda998x_priv *priv,
c4c11dd1
RK		 712 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
713{
e66e03ab
RK		 714 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
715 u32 n;
c4c11dd1
RK		 716
717 /* Enable audio ports */
2f7f730a
JFM		 718 reg_write(priv, REG_ENA_AP, p->audio_cfg);
719 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
c4c11dd1
RK		 720
721 /* Set audio input source */
722 switch (p->audio_format) {
723 case AFMT_SPDIF:
10df1a95
JFM		 724 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
725 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
726 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
c4c11dd1 727 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1
RK		 728 break;
729
730 case AFMT_I2S:
10df1a95
JFM		 731 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
732 clksel_aip = AIP_CLKSEL_AIP_I2S;
733 clksel_fs = AIP_CLKSEL_FS_ACLK;
c4c11dd1 734 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1 735 break;
3b28802e
DH		 736
737 default:
738 BUG();
739 return;
c4c11dd1
RK		 740 }
741
2f7f730a 742 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
a8b517e5
JFM		 743 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
744 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
2f7f730a 745 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 746
747 /*
748 * Audio input somehow depends on HDMI line rate which is
749 * related to pixclk. Testing showed that modes with pixclk
750 * >100MHz need a larger divider while <40MHz need the default.
751 * There is no detailed info in the datasheet, so we just
752 * assume 100MHz requires larger divider.
753 */
2470fecc 754 adiv = AUDIO_DIV_SERCLK_8;
c4c11dd1 755 if (mode->clock > 100000)
2470fecc
JFM		 756 adiv++; /* AUDIO_DIV_SERCLK_16 */
757
758 /* S/PDIF asks for a larger divider */
759 if (p->audio_format == AFMT_SPDIF)
760 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
761
2f7f730a 762 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 763
764 /*
765 * This is the approximate value of N, which happens to be
766 * the recommended values for non-coherent clocks.
767 */
768 n = 128 * p->audio_sample_rate / 1000;
769
770 /* Write the CTS and N values */
771 buf[0] = 0x44;
772 buf[1] = 0x42;
773 buf[2] = 0x01;
774 buf[3] = n;
775 buf[4] = n >> 8;
776 buf[5] = n >> 16;
2f7f730a 777 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 778
779 /* Set CTS clock reference */
2f7f730a 780 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 781
782 /* Reset CTS generator */
2f7f730a
JFM		 783 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
784 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1
RK		 785
786 /* Write the channel status */
f0b33b28 787 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
c4c11dd1 788 buf[1] = 0x00;
f0b33b28
JFM		 789 buf[2] = IEC958_AES3_CON_FS_NOTID;
790 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
791 IEC958_AES4_CON_MAX_WORDLEN_24;
2f7f730a 792 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 793
2f7f730a 794 tda998x_audio_mute(priv, true);
73d5e253 795 msleep(20);
2f7f730a 796 tda998x_audio_mute(priv, false);
c4c11dd1
RK		 797
798 /* Write the audio information packet */
2f7f730a 799 tda998x_write_aif(priv, p);
c4c11dd1
RK		 800}
801
e7792ce2
RC		 802/* DRM encoder functions */
803
a8f4d4d6
RK		 804static void tda998x_encoder_set_config(struct tda998x_priv *priv,
805 const struct tda998x_encoder_params *p)
e7792ce2 806{
c4c11dd1
RK		 807 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
808 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
809 VIP_CNTRL_0_SWAP_B(p->swap_b) |
810 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
811 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
812 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
813 VIP_CNTRL_1_SWAP_D(p->swap_d) |
814 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
815 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
816 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
817 VIP_CNTRL_2_SWAP_F(p->swap_f) |
818 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
819
820 priv->params = *p;
e7792ce2
RC		 821}
822
a8f4d4d6 823static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode)
e7792ce2 824{
e7792ce2
RC		 825 /* we only care about on or off: */
826 if (mode != DRM_MODE_DPMS_ON)
827 mode = DRM_MODE_DPMS_OFF;
828
829 if (mode == priv->dpms)
830 return;
831
832 switch (mode) {
833 case DRM_MODE_DPMS_ON:
c4c11dd1 834 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 835 reg_write(priv, REG_ENA_VP_0, 0xff);
836 reg_write(priv, REG_ENA_VP_1, 0xff);
837 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 838 /* set muxing after enabling ports: */
2f7f730a
JFM		 839 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
840 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
841 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
e7792ce2
RC		 842 break;
843 case DRM_MODE_DPMS_OFF:
db6aaf4d 844 /* disable video ports */
2f7f730a
JFM		 845 reg_write(priv, REG_ENA_VP_0, 0x00);
846 reg_write(priv, REG_ENA_VP_1, 0x00);
847 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2
RC		 848 break;
849 }
850
851 priv->dpms = mode;
852}
853
854static void
855tda998x_encoder_save(struct drm_encoder *encoder)
856{
857 DBG("");
858}
859
860static void
861tda998x_encoder_restore(struct drm_encoder *encoder)
862{
863 DBG("");
864}
865
866static bool
867tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
868 const struct drm_display_mode *mode,
869 struct drm_display_mode *adjusted_mode)
870{
871 return true;
872}
873
a8f4d4d6
RK		 874static int tda998x_encoder_mode_valid(struct tda998x_priv *priv,
875 struct drm_display_mode *mode)
e7792ce2 876{
92fbdfcd
RK		 877 if (mode->clock > 150000)
878 return MODE_CLOCK_HIGH;
879 if (mode->htotal >= BIT(13))
880 return MODE_BAD_HVALUE;
881 if (mode->vtotal >= BIT(11))
882 return MODE_BAD_VVALUE;
e7792ce2
RC		 883 return MODE_OK;
884}
885
886static void
a8f4d4d6
RK		 887tda998x_encoder_mode_set(struct tda998x_priv *priv,
888 struct drm_display_mode *mode,
889 struct drm_display_mode *adjusted_mode)
e7792ce2 890{
e66e03ab
RK		 891 u16 ref_pix, ref_line, n_pix, n_line;
892 u16 hs_pix_s, hs_pix_e;
893 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
894 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
895 u16 vwin1_line_s, vwin1_line_e;
896 u16 vwin2_line_s, vwin2_line_e;
897 u16 de_pix_s, de_pix_e;
898 u8 reg, div, rep;
e7792ce2 899
088d61d1
SH		 900 /*
901 * Internally TDA998x is using ITU-R BT.656 style sync but
902 * we get VESA style sync. TDA998x is using a reference pixel
903 * relative to ITU to sync to the input frame and for output
904 * sync generation. Currently, we are using reference detection
905 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
906 * which is position of rising VS with coincident rising HS.
907 *
908 * Now there is some issues to take care of:
909 * - HDMI data islands require sync-before-active
910 * - TDA998x register values must be > 0 to be enabled
911 * - REFLINE needs an additional offset of +1
912 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
913 *
914 * So we add +1 to all horizontal and vertical register values,
915 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 916 */
088d61d1
SH		 917 n_pix = mode->htotal;
918 n_line = mode->vtotal;
919
920 hs_pix_e = mode->hsync_end - mode->hdisplay;
921 hs_pix_s = mode->hsync_start - mode->hdisplay;
922 de_pix_e = mode->htotal;
923 de_pix_s = mode->htotal - mode->hdisplay;
924 ref_pix = 3 + hs_pix_s;
925
179f1aa4
SH		 926 /*
927 * Attached LCD controllers may generate broken sync. Allow
928 * those to adjust the position of the rising VS edge by adding
929 * HSKEW to ref_pix.
930 */
931 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
932 ref_pix += adjusted_mode->hskew;
933
088d61d1
SH		 934 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
935 ref_line = 1 + mode->vsync_start - mode->vdisplay;
936 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
937 vwin1_line_e = vwin1_line_s + mode->vdisplay;
938 vs1_pix_s = vs1_pix_e = hs_pix_s;
939 vs1_line_s = mode->vsync_start - mode->vdisplay;
940 vs1_line_e = vs1_line_s +
941 mode->vsync_end - mode->vsync_start;
942 vwin2_line_s = vwin2_line_e = 0;
943 vs2_pix_s = vs2_pix_e = 0;
944 vs2_line_s = vs2_line_e = 0;
945 } else {
946 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
947 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
948 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
949 vs1_pix_s = vs1_pix_e = hs_pix_s;
950 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
951 vs1_line_e = vs1_line_s +
952 (mode->vsync_end - mode->vsync_start)/2;
953 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
954 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
955 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
956 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
957 vs2_line_e = vs2_line_s +
958 (mode->vsync_end - mode->vsync_start)/2;
959 }
e7792ce2
RC		 960
961 div = 148500 / mode->clock;
3ae471f7
JFM		 962 if (div != 0) {
963 div--;
964 if (div > 3)
965 div = 3;
966 }
e7792ce2 967
e7792ce2 968 /* mute the audio FIFO: */
2f7f730a 969 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 970
971 /* set HDMI HDCP mode off: */
81b53a16 972 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
2f7f730a
JFM		 973 reg_clear(priv, REG_TX33, TX33_HDMI);
974 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 975
e7792ce2 976 /* no pre-filter or interpolator: */
2f7f730a 977 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 978 HVF_CNTRL_0_INTPOL(0));
2f7f730a
JFM		 979 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
980 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 981 VIP_CNTRL_4_BLC(0));
e7792ce2 982
2f7f730a 983 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
a8b517e5
JFM		 984 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
985 PLL_SERIAL_3_SRL_DE);
2f7f730a
JFM		 986 reg_write(priv, REG_SERIALIZER, 0);
987 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 988
989 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
990 rep = 0;
2f7f730a
JFM		 991 reg_write(priv, REG_RPT_CNTRL, 0);
992 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 993 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
994
2f7f730a 995 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 996 PLL_SERIAL_2_SRL_PR(rep));
997
e7792ce2 998 /* set color matrix bypass flag: */
81b53a16
JFM		 999 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1000 MAT_CONTRL_MAT_SC(1));
e7792ce2
RC		 1001
1002 /* set BIAS tmds value: */
2f7f730a 1003 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 1004
088d61d1
SH		 1005 /*
1006 * Sync on rising HSYNC/VSYNC
1007 */
81b53a16 1008 reg = VIP_CNTRL_3_SYNC_HS;
088d61d1
SH		 1009
1010 /*
1011 * TDA19988 requires high-active sync at input stage,
1012 * so invert low-active sync provided by master encoder here
1013 */
1014 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
81b53a16 1015 reg |= VIP_CNTRL_3_H_TGL;
e7792ce2 1016 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
81b53a16
JFM		 1017 reg |= VIP_CNTRL_3_V_TGL;
1018 reg_write(priv, REG_VIP_CNTRL_3, reg);
2f7f730a
JFM		 1019
1020 reg_write(priv, REG_VIDFORMAT, 0x00);
1021 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1022 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1023 reg_write16(priv, REG_NPIX_MSB, n_pix);
1024 reg_write16(priv, REG_NLINE_MSB, n_line);
1025 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1026 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1027 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1028 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1029 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1030 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1031 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1032 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1033 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1034 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1035 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1036 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1037 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1038 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1039 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1040 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 1041
1042 if (priv->rev == TDA19988) {
1043 /* let incoming pixels fill the active space (if any) */
2f7f730a 1044 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 1045 }
1046
81b53a16
JFM		 1047 /*
1048 * Always generate sync polarity relative to input sync and
1049 * revert input stage toggled sync at output stage
1050 */
1051 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1052 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1053 reg |= TBG_CNTRL_1_H_TGL;
1054 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1055 reg |= TBG_CNTRL_1_V_TGL;
1056 reg_write(priv, REG_TBG_CNTRL_1, reg);
1057
e7792ce2 1058 /* must be last register set: */
81b53a16 1059 reg_write(priv, REG_TBG_CNTRL_0, 0);
c4c11dd1
RK		 1060
1061 /* Only setup the info frames if the sink is HDMI */
1062 if (priv->is_hdmi_sink) {
1063 /* We need to turn HDMI HDCP stuff on to get audio through */
81b53a16
JFM		 1064 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1065 reg_write(priv, REG_TBG_CNTRL_1, reg);
2f7f730a
JFM		 1066 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1067 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 1068
2f7f730a 1069 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1
RK		 1070
1071 if (priv->params.audio_cfg)
2f7f730a 1072 tda998x_configure_audio(priv, adjusted_mode,
c4c11dd1
RK		 1073 &priv->params);
1074 }
e7792ce2
RC		 1075}
1076
1077static enum drm_connector_status
a8f4d4d6 1078tda998x_encoder_detect(struct tda998x_priv *priv)
e7792ce2 1079{
e66e03ab 1080 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
2f7f730a 1081
e7792ce2
RC		 1082 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1083 connector_status_disconnected;
1084}
1085
07259f8b 1086static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
e7792ce2 1087{
07259f8b 1088 struct tda998x_priv *priv = data;
e66e03ab 1089 u8 offset, segptr;
e7792ce2
RC		 1090 int ret, i;
1091
e7792ce2
RC		 1092 offset = (blk & 1) ? 128 : 0;
1093 segptr = blk / 2;
1094
2f7f730a
JFM		 1095 reg_write(priv, REG_DDC_ADDR, 0xa0);
1096 reg_write(priv, REG_DDC_OFFS, offset);
1097 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1098 reg_write(priv, REG_DDC_SEGM, segptr);
e7792ce2
RC		 1099
1100 /* enable reading EDID: */
12473b7d 1101 priv->wq_edid_wait = 1;
2f7f730a 1102 reg_write(priv, REG_EDID_CTRL, 0x1);
e7792ce2
RC		 1103
1104 /* flag must be cleared by sw: */
2f7f730a 1105 reg_write(priv, REG_EDID_CTRL, 0x0);
e7792ce2
RC		 1106
1107 /* wait for block read to complete: */
12473b7d
JFM		 1108 if (priv->hdmi->irq) {
1109 i = wait_event_timeout(priv->wq_edid,
1110 !priv->wq_edid_wait,
1111 msecs_to_jiffies(100));
1112 if (i < 0) {
5e7fe2fe 1113 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
12473b7d
JFM		 1114 return i;
1115 }
1116 } else {
713456db
RK		 1117 for (i = 100; i > 0; i--) {
1118 msleep(1);
12473b7d
JFM		 1119 ret = reg_read(priv, REG_INT_FLAGS_2);
1120 if (ret < 0)
1121 return ret;
1122 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1123 break;
1124 }
e7792ce2
RC		 1125 }
1126
12473b7d 1127 if (i == 0) {
5e7fe2fe 1128 dev_err(&priv->hdmi->dev, "read edid timeout\n");
e7792ce2 1129 return -ETIMEDOUT;
12473b7d 1130 }
e7792ce2 1131
07259f8b
LP		 1132 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1133 if (ret != length) {
5e7fe2fe
RK		 1134 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1135 blk, ret);
e7792ce2
RC		 1136 return ret;
1137 }
1138
e7792ce2
RC		 1139 return 0;
1140}
1141
07259f8b
LP		 1142static int
1143tda998x_encoder_get_modes(struct tda998x_priv *priv,
1144 struct drm_connector *connector)
e7792ce2 1145{
07259f8b
LP		 1146 struct edid *edid;
1147 int n;
e7792ce2 1148
0fc6f44d
RK		 1149 /*
1150 * If we get killed while waiting for the HPD timeout, return
1151 * no modes found: we are not in a restartable path, so we
1152 * can't handle signals gracefully.
1153 */
1154 if (tda998x_edid_delay_wait(priv))
1155 return 0;
1156
063b472f 1157 if (priv->rev == TDA19988)
2f7f730a 1158 reg_clear(priv, REG_TX4, TX4_PD_RAM);
063b472f 1159
07259f8b 1160 edid = drm_do_get_edid(connector, read_edid_block, priv);
e7792ce2 1161
063b472f 1162 if (priv->rev == TDA19988)
2f7f730a 1163 reg_set(priv, REG_TX4, TX4_PD_RAM);
063b472f 1164
07259f8b
LP		 1165 if (!edid) {
1166 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1167 return 0;
e7792ce2
RC		 1168 }
1169
07259f8b
LP		 1170 drm_mode_connector_update_edid_property(connector, edid);
1171 n = drm_add_edid_modes(connector, edid);
1172 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1173 kfree(edid);
1174
e7792ce2
RC		 1175 return n;
1176}
1177
a8f4d4d6
RK		 1178static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1179 struct drm_connector *connector)
e7792ce2 1180{
12473b7d
JFM		 1181 if (priv->hdmi->irq)
1182 connector->polled = DRM_CONNECTOR_POLL_HPD;
1183 else
1184 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1185 DRM_CONNECTOR_POLL_DISCONNECT;
e7792ce2
RC		 1186}
1187
1188static int
1189tda998x_encoder_set_property(struct drm_encoder *encoder,
1190 struct drm_connector *connector,
1191 struct drm_property *property,
1192 uint64_t val)
1193{
1194 DBG("");
1195 return 0;
1196}
1197
a8f4d4d6 1198static void tda998x_destroy(struct tda998x_priv *priv)
e7792ce2 1199{
12473b7d
JFM		 1200 /* disable all IRQs and free the IRQ handler */
1201 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1202 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
0fc6f44d
RK		 1203
1204 if (priv->hdmi->irq)
12473b7d 1205 free_irq(priv->hdmi->irq, priv);
0fc6f44d
RK		 1206
1207 del_timer_sync(&priv->edid_delay_timer);
1208 cancel_work_sync(&priv->detect_work);
12473b7d 1209
89fc8686 1210 i2c_unregister_device(priv->cec);
a8f4d4d6
RK		 1211}
1212
1213/* Slave encoder support */
1214
1215static void
1216tda998x_encoder_slave_set_config(struct drm_encoder *encoder, void *params)
1217{
1218 tda998x_encoder_set_config(to_tda998x_priv(encoder), params);
1219}
1220
1221static void tda998x_encoder_slave_destroy(struct drm_encoder *encoder)
1222{
1223 struct tda998x_priv *priv = to_tda998x_priv(encoder);
1224
1225 tda998x_destroy(priv);
2e48cecb 1226 drm_i2c_encoder_destroy(encoder);
e7792ce2
RC		 1227 kfree(priv);
1228}
1229
a8f4d4d6
RK		 1230static void tda998x_encoder_slave_dpms(struct drm_encoder *encoder, int mode)
1231{
1232 tda998x_encoder_dpms(to_tda998x_priv(encoder), mode);
1233}
e7792ce2 1234
a8f4d4d6
RK		 1235static int tda998x_encoder_slave_mode_valid(struct drm_encoder *encoder,
1236 struct drm_display_mode *mode)
1237{
1238 return tda998x_encoder_mode_valid(to_tda998x_priv(encoder), mode);
1239}
e7792ce2 1240
a8f4d4d6
RK		 1241static void
1242tda998x_encoder_slave_mode_set(struct drm_encoder *encoder,
1243 struct drm_display_mode *mode,
1244 struct drm_display_mode *adjusted_mode)
e7792ce2 1245{
a8f4d4d6
RK		 1246 tda998x_encoder_mode_set(to_tda998x_priv(encoder), mode, adjusted_mode);
1247}
1248
1249static enum drm_connector_status
1250tda998x_encoder_slave_detect(struct drm_encoder *encoder,
1251 struct drm_connector *connector)
1252{
1253 return tda998x_encoder_detect(to_tda998x_priv(encoder));
1254}
1255
1256static int tda998x_encoder_slave_get_modes(struct drm_encoder *encoder,
1257 struct drm_connector *connector)
1258{
1259 return tda998x_encoder_get_modes(to_tda998x_priv(encoder), connector);
e7792ce2
RC		 1260}
1261
1262static int
a8f4d4d6
RK		 1263tda998x_encoder_slave_create_resources(struct drm_encoder *encoder,
1264 struct drm_connector *connector)
e7792ce2 1265{
a8f4d4d6 1266 tda998x_encoder_set_polling(to_tda998x_priv(encoder), connector);
e7792ce2
RC		 1267 return 0;
1268}
1269
a8f4d4d6
RK		 1270static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs = {
1271 .set_config = tda998x_encoder_slave_set_config,
1272 .destroy = tda998x_encoder_slave_destroy,
1273 .dpms = tda998x_encoder_slave_dpms,
e7792ce2
RC		 1274 .save = tda998x_encoder_save,
1275 .restore = tda998x_encoder_restore,
1276 .mode_fixup = tda998x_encoder_mode_fixup,
a8f4d4d6
RK		 1277 .mode_valid = tda998x_encoder_slave_mode_valid,
1278 .mode_set = tda998x_encoder_slave_mode_set,
1279 .detect = tda998x_encoder_slave_detect,
1280 .get_modes = tda998x_encoder_slave_get_modes,
1281 .create_resources = tda998x_encoder_slave_create_resources,
e7792ce2
RC		 1282 .set_property = tda998x_encoder_set_property,
1283};
1284
1285/* I2C driver functions */
1286
a8f4d4d6 1287static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
e7792ce2 1288{
0d44ea19
JFM		 1289 struct device_node *np = client->dev.of_node;
1290 u32 video;
fb7544d7 1291 int rev_lo, rev_hi, ret;
cfe38757 1292 unsigned short cec_addr;
e7792ce2 1293
5e74c22c
RK		 1294 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1295 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1296 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1297
2eb4c7b1 1298 priv->current_page = 0xff;
2f7f730a 1299 priv->hdmi = client;
cfe38757
AJ		 1300 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1301 cec_addr = 0x34 + (client->addr & 0x03);
1302 priv->cec = i2c_new_dummy(client->adapter, cec_addr);
a8f4d4d6 1303 if (!priv->cec)
6ae668cc 1304 return -ENODEV;
12473b7d 1305
e7792ce2
RC		 1306 priv->dpms = DRM_MODE_DPMS_OFF;
1307
ed9a8426 1308 mutex_init(&priv->mutex); /* protect the page access */
0fc6f44d
RK		 1309 init_waitqueue_head(&priv->edid_delay_waitq);
1310 setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1311 (unsigned long)priv);
1312 INIT_WORK(&priv->detect_work, tda998x_detect_work);
ed9a8426 1313
e7792ce2 1314 /* wake up the device: */
2f7f730a 1315 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1316 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1317
2f7f730a 1318 tda998x_reset(priv);
e7792ce2
RC		 1319
1320 /* read version: */
fb7544d7
RK		 1321 rev_lo = reg_read(priv, REG_VERSION_LSB);
1322 rev_hi = reg_read(priv, REG_VERSION_MSB);
1323 if (rev_lo < 0 || rev_hi < 0) {
1324 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1325 goto fail;
fb7544d7
RK		 1326 }
1327
1328 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1329
1330 /* mask off feature bits: */
1331 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1332
1333 switch (priv->rev) {
b728fab7
JFM		 1334 case TDA9989N2:
1335 dev_info(&client->dev, "found TDA9989 n2");
1336 break;
1337 case TDA19989:
1338 dev_info(&client->dev, "found TDA19989");
1339 break;
1340 case TDA19989N2:
1341 dev_info(&client->dev, "found TDA19989 n2");
1342 break;
1343 case TDA19988:
1344 dev_info(&client->dev, "found TDA19988");
1345 break;
e7792ce2 1346 default:
b728fab7
JFM		 1347 dev_err(&client->dev, "found unsupported device: %04x\n",
1348 priv->rev);
e7792ce2
RC		 1349 goto fail;
1350 }
1351
1352 /* after reset, enable DDC: */
2f7f730a 1353 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1354
1355 /* set clock on DDC channel: */
2f7f730a 1356 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1357
1358 /* if necessary, disable multi-master: */
1359 if (priv->rev == TDA19989)
2f7f730a 1360 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1361
2f7f730a 1362 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1363 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1364
12473b7d
JFM		 1365 /* initialize the optional IRQ */
1366 if (client->irq) {
1367 int irqf_trigger;
1368
6833d26e 1369 /* init read EDID waitqueue and HDP work */
12473b7d
JFM		 1370 init_waitqueue_head(&priv->wq_edid);
1371
1372 /* clear pending interrupts */
1373 reg_read(priv, REG_INT_FLAGS_0);
1374 reg_read(priv, REG_INT_FLAGS_1);
1375 reg_read(priv, REG_INT_FLAGS_2);
1376
1377 irqf_trigger =
1378 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1379 ret = request_threaded_irq(client->irq, NULL,
1380 tda998x_irq_thread,
1381 irqf_trigger | IRQF_ONESHOT,
1382 "tda998x", priv);
1383 if (ret) {
1384 dev_err(&client->dev,
1385 "failed to request IRQ#%u: %d\n",
1386 client->irq, ret);
1387 goto fail;
1388 }
1389
1390 /* enable HPD irq */
1391 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1392 }
1393
e4782627
JFM		 1394 /* enable EDID read irq: */
1395 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1396
0d44ea19
JFM		 1397 if (!np)
1398 return 0; /* non-DT */
1399
1400 /* get the optional video properties */
1401 ret = of_property_read_u32(np, "video-ports", &video);
1402 if (ret == 0) {
1403 priv->vip_cntrl_0 = video >> 16;
1404 priv->vip_cntrl_1 = video >> 8;
1405 priv->vip_cntrl_2 = video;
1406 }
1407
e7792ce2
RC		 1408 return 0;
1409
1410fail:
1411 /* if encoder_init fails, the encoder slave is never registered,
1412 * so cleanup here:
1413 */
1414 if (priv->cec)
1415 i2c_unregister_device(priv->cec);
e7792ce2
RC		 1416 return -ENXIO;
1417}
1418
a8f4d4d6
RK		 1419static int tda998x_encoder_init(struct i2c_client *client,
1420 struct drm_device *dev,
1421 struct drm_encoder_slave *encoder_slave)
1422{
1423 struct tda998x_priv *priv;
1424 int ret;
1425
1426 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1427 if (!priv)
1428 return -ENOMEM;
1429
1430 priv->encoder = &encoder_slave->base;
1431
1432 ret = tda998x_create(client, priv);
1433 if (ret) {
1434 kfree(priv);
1435 return ret;
1436 }
1437
1438 encoder_slave->slave_priv = priv;
1439 encoder_slave->slave_funcs = &tda998x_encoder_slave_funcs;
1440
1441 return 0;
1442}
1443
c707c361
RK		 1444struct tda998x_priv2 {
1445 struct tda998x_priv base;
1446 struct drm_encoder encoder;
1447 struct drm_connector connector;
1448};
1449
1450#define conn_to_tda998x_priv2(x) \
1451 container_of(x, struct tda998x_priv2, connector);
1452
1453#define enc_to_tda998x_priv2(x) \
1454 container_of(x, struct tda998x_priv2, encoder);
1455
1456static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode)
1457{
1458 struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1459
1460 tda998x_encoder_dpms(&priv->base, mode);
1461}
1462
1463static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1464{
1465 tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF);
1466}
1467
1468static void tda998x_encoder_commit(struct drm_encoder *encoder)
1469{
1470 tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON);
1471}
1472
1473static void tda998x_encoder2_mode_set(struct drm_encoder *encoder,
1474 struct drm_display_mode *mode,
1475 struct drm_display_mode *adjusted_mode)
1476{
1477 struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1478
1479 tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode);
1480}
1481
1482static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1483 .dpms = tda998x_encoder2_dpms,
1484 .save = tda998x_encoder_save,
1485 .restore = tda998x_encoder_restore,
1486 .mode_fixup = tda998x_encoder_mode_fixup,
1487 .prepare = tda998x_encoder_prepare,
1488 .commit = tda998x_encoder_commit,
1489 .mode_set = tda998x_encoder2_mode_set,
1490};
1491
1492static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1493{
1494 struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder);
1495
1496 tda998x_destroy(&priv->base);
1497 drm_encoder_cleanup(encoder);
1498}
1499
1500static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1501 .destroy = tda998x_encoder_destroy,
1502};
1503
1504static int tda998x_connector_get_modes(struct drm_connector *connector)
1505{
1506 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1507
1508 return tda998x_encoder_get_modes(&priv->base, connector);
1509}
1510
1511static int tda998x_connector_mode_valid(struct drm_connector *connector,
1512 struct drm_display_mode *mode)
1513{
1514 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1515
1516 return tda998x_encoder_mode_valid(&priv->base, mode);
1517}
1518
1519static struct drm_encoder *
1520tda998x_connector_best_encoder(struct drm_connector *connector)
1521{
1522 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1523
1524 return &priv->encoder;
1525}
1526
1527static
1528const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1529 .get_modes = tda998x_connector_get_modes,
1530 .mode_valid = tda998x_connector_mode_valid,
1531 .best_encoder = tda998x_connector_best_encoder,
1532};
1533
1534static enum drm_connector_status
1535tda998x_connector_detect(struct drm_connector *connector, bool force)
1536{
1537 struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector);
1538
1539 return tda998x_encoder_detect(&priv->base);
1540}
1541
1542static void tda998x_connector_destroy(struct drm_connector *connector)
1543{
74cd62ea 1544 drm_connector_unregister(connector);
c707c361
RK		 1545 drm_connector_cleanup(connector);
1546}
1547
1548static const struct drm_connector_funcs tda998x_connector_funcs = {
1549 .dpms = drm_helper_connector_dpms,
1550 .fill_modes = drm_helper_probe_single_connector_modes,
1551 .detect = tda998x_connector_detect,
1552 .destroy = tda998x_connector_destroy,
1553};
1554
1555static int tda998x_bind(struct device *dev, struct device *master, void *data)
1556{
1557 struct tda998x_encoder_params *params = dev->platform_data;
1558 struct i2c_client *client = to_i2c_client(dev);
1559 struct drm_device *drm = data;
1560 struct tda998x_priv2 *priv;
e66e03ab 1561 u32 crtcs = 0;
c707c361
RK		 1562 int ret;
1563
1564 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1565 if (!priv)
1566 return -ENOMEM;
1567
1568 dev_set_drvdata(dev, priv);
1569
5dbcf319
RK		 1570 if (dev->of_node)
1571 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1572
1573 /* If no CRTCs were found, fall back to our old behaviour */
1574 if (crtcs == 0) {
1575 dev_warn(dev, "Falling back to first CRTC\n");
1576 crtcs = 1 << 0;
1577 }
1578
c707c361
RK		 1579 priv->base.encoder = &priv->encoder;
1580 priv->connector.interlace_allowed = 1;
5dbcf319 1581 priv->encoder.possible_crtcs = crtcs;
c707c361
RK		 1582
1583 ret = tda998x_create(client, &priv->base);
1584 if (ret)
1585 return ret;
1586
1587 if (!dev->of_node && params)
1588 tda998x_encoder_set_config(&priv->base, params);
1589
1590 tda998x_encoder_set_polling(&priv->base, &priv->connector);
1591
1592 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1593 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1594 DRM_MODE_ENCODER_TMDS);
1595 if (ret)
1596 goto err_encoder;
1597
1598 drm_connector_helper_add(&priv->connector,
1599 &tda998x_connector_helper_funcs);
1600 ret = drm_connector_init(drm, &priv->connector,
1601 &tda998x_connector_funcs,
1602 DRM_MODE_CONNECTOR_HDMIA);
1603 if (ret)
1604 goto err_connector;
1605
74cd62ea 1606 ret = drm_connector_register(&priv->connector);
c707c361
RK		 1607 if (ret)
1608 goto err_sysfs;
1609
1610 priv->connector.encoder = &priv->encoder;
1611 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1612
1613 return 0;
1614
1615err_sysfs:
1616 drm_connector_cleanup(&priv->connector);
1617err_connector:
1618 drm_encoder_cleanup(&priv->encoder);
1619err_encoder:
1620 tda998x_destroy(&priv->base);
1621 return ret;
1622}
1623
1624static void tda998x_unbind(struct device *dev, struct device *master,
1625 void *data)
1626{
1627 struct tda998x_priv2 *priv = dev_get_drvdata(dev);
1628
1629 drm_connector_cleanup(&priv->connector);
1630 drm_encoder_cleanup(&priv->encoder);
1631 tda998x_destroy(&priv->base);
1632}
1633
1634static const struct component_ops tda998x_ops = {
1635 .bind = tda998x_bind,
1636 .unbind = tda998x_unbind,
1637};
1638
1639static int
1640tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1641{
1642 return component_add(&client->dev, &tda998x_ops);
1643}
1644
1645static int tda998x_remove(struct i2c_client *client)
1646{
1647 component_del(&client->dev, &tda998x_ops);
1648 return 0;
1649}
1650
0d44ea19
JFM		 1651#ifdef CONFIG_OF
1652static const struct of_device_id tda998x_dt_ids[] = {
1653 { .compatible = "nxp,tda998x", },
1654 { }
1655};
1656MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1657#endif
1658
e7792ce2
RC		 1659static struct i2c_device_id tda998x_ids[] = {
1660 { "tda998x", 0 },
1661 { }
1662};
1663MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1664
1665static struct drm_i2c_encoder_driver tda998x_driver = {
1666 .i2c_driver = {
1667 .probe = tda998x_probe,
1668 .remove = tda998x_remove,
1669 .driver = {
1670 .name = "tda998x",
0d44ea19 1671 .of_match_table = of_match_ptr(tda998x_dt_ids),
e7792ce2
RC		 1672 },
1673 .id_table = tda998x_ids,
1674 },
1675 .encoder_init = tda998x_encoder_init,
1676};
1677
1678/* Module initialization */
1679
1680static int __init
1681tda998x_init(void)
1682{
1683 DBG("");
1684 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver);
1685}
1686
1687static void __exit
1688tda998x_exit(void)
1689{
1690 DBG("");
1691 drm_i2c_encoder_unregister(&tda998x_driver);
1692}
1693
1694MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1695MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1696MODULE_LICENSE("GPL");
1697
1698module_init(tda998x_init);
1699module_exit(tda998x_exit);
Linux 6.x block layer and io_uring tree(s)